1 /******************************************************************************
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3 * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
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5 * This program is free software; you can redistribute it and/or modify it
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6 * under the terms of version 2 of the GNU General Public License as
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7 * published by the Free Software Foundation.
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9 * This program is distributed in the hope that it will be useful, but WITHOUT
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10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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14 * You should have received a copy of the GNU General Public License along with
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15 * this program; if not, write to the Free Software Foundation, Inc.,
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16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
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19 ******************************************************************************/
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20 #define _RTL8723B_MP_C_
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21 #ifdef CONFIG_MP_INCLUDED
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23 #include <rtl8723b_hal.h>
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26 /*-----------------------------------------------------------------------------
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27 * Function: mpt_SwitchRfSetting
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29 * Overview: Change RF Setting when we siwthc channel/rate/BW for MP.
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31 * Input: IN PADAPTER pAdapter
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39 * 01/08/2009 MHC Suggestion from SD3 Willis for 92S series.
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40 * 01/09/2009 MHC Add CCK modification for 40MHZ. Suggestion from SD3.
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42 *---------------------------------------------------------------------------*/
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43 static void phy_SwitchRfSetting(PADAPTER pAdapter,u8 channel )
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46 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
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47 u32 u4RF_IPA[3], u4RF_TXBIAS, u4RF_SYN_G2;
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51 u4RF_IPA[0] = 0x4F424; //CCK
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52 u4RF_IPA[1] = 0xCF424; //OFDM
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53 u4RF_IPA[2] = 0x8F424; //MCS
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54 u4RF_TXBIAS = 0xC0356;
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55 u4RF_SYN_G2 = 0x4F200;
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61 u4RF_IPA[0] = 0x4F40C;
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62 u4RF_IPA[1] = 0xCF466;
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63 u4RF_TXBIAS = 0xC0350;
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67 u4RF_IPA[0] = 0x4F407;
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68 u4RF_TXBIAS = 0xC0350;
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72 u4RF_IPA[0] = 0x4F407;
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73 u4RF_IPA[2] = 0x8F466;
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74 u4RF_TXBIAS = 0xC0350;
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79 u4RF_SYN_G2 = 0x0F400;
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84 u4RF_IPA[0] = 0x4F40C;
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88 u4RF_IPA[0] = 0x4F40C;
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89 u4RF_SYN_G2 = 0x0F400;
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93 u4RF_IPA[2] = 0x8F454;
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94 u4RF_SYN_G2 = 0x0F400;
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98 u4RF_IPA[0] = 0x4F40C;
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99 u4RF_IPA[1] = 0xCF454;
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100 u4RF_SYN_G2 = 0x0F400;
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104 u4RF_IPA[0] = 0x4F424;
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105 u4RF_IPA[1] = 0x8F424;
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106 u4RF_IPA[2] = 0xCF424;
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107 u4RF_TXBIAS = 0xC0356;
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108 u4RF_SYN_G2 = 0x4F200;
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112 PHY_SetRFReg(pAdapter, RF_PATH_A, RF_IPA, bRFRegOffsetMask, u4RF_IPA[0]);
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113 PHY_SetRFReg(pAdapter, RF_PATH_A, RF_IPA, bRFRegOffsetMask, u4RF_IPA[1]);
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114 PHY_SetRFReg(pAdapter, RF_PATH_A, RF_IPA, bRFRegOffsetMask, u4RF_IPA[2]);
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115 PHY_SetRFReg(pAdapter, RF_PATH_A, RF_TXBIAS, bRFRegOffsetMask, u4RF_TXBIAS);
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116 PHY_SetRFReg(pAdapter, RF_PATH_A, RF_SYN_G2, bRFRegOffsetMask, u4RF_SYN_G2);
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120 void Hal_mpt_SwitchRfSetting(PADAPTER pAdapter)
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122 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
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123 PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.MptCtx);
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124 u8 ChannelToSw = pMptCtx->MptChannelToSw;
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126 phy_SwitchRfSetting(pAdapter, ChannelToSw);
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129 s32 Hal_SetPowerTracking(PADAPTER padapter, u8 enable)
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131 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
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132 struct dm_priv *pdmpriv = &pHalData->dmpriv;
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135 if (!netif_running(padapter->pnetdev)) {
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136 RT_TRACE(_module_mp_, _drv_warning_, ("SetPowerTracking! Fail: interface not opened!\n"));
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140 if (check_fwstate(&padapter->mlmepriv, WIFI_MP_STATE) == _FALSE) {
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141 RT_TRACE(_module_mp_, _drv_warning_, ("SetPowerTracking! Fail: not in MP mode!\n"));
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146 pdmpriv->TxPowerTrackControl = _TRUE;
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148 pdmpriv->TxPowerTrackControl = _FALSE;
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153 void Hal_GetPowerTracking(PADAPTER padapter, u8 *enable)
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155 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
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156 struct dm_priv *pdmpriv = &pHalData->dmpriv;
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159 *enable = pdmpriv->TxPowerTrackControl;
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162 static void Hal_disable_dm(PADAPTER padapter)
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165 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
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166 struct dm_priv *pdmpriv = &pHalData->dmpriv;
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169 //3 1. disable firmware dynamic mechanism
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170 // disable Power Training, Rate Adaptive
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171 v8 = rtw_read8(padapter, REG_BCN_CTRL);
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172 v8 &= ~EN_BCN_FUNCTION;
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173 rtw_write8(padapter, REG_BCN_CTRL, v8);
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175 //3 2. disable driver dynamic mechanism
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176 // disable Dynamic Initial Gain
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177 // disable High Power
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178 // disable Power Tracking
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179 Switch_DM_Func(padapter, DYNAMIC_FUNC_DISABLE, _FALSE);
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181 // enable APK, LCK and IQK but disable power tracking
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182 pdmpriv->TxPowerTrackControl = _FALSE;
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183 Switch_DM_Func(padapter, DYNAMIC_RF_TX_PWR_TRACK , _TRUE);
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186 void Hal_MPT_CCKTxPowerAdjust(PADAPTER Adapter, BOOLEAN bInCH14)
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188 u32 TempVal = 0, TempVal2 = 0, TempVal3 = 0;
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189 u32 CurrCCKSwingVal = 0, CCKSwingIndex = 12;
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191 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
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194 // get current cck swing value and check 0xa22 & 0xa23 later to match the table.
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195 CurrCCKSwingVal = read_bbreg(Adapter, rCCK0_TxFilter1, bMaskHWord);
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199 // Readback the current bb cck swing value and compare with the table to
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200 // get the current swing index
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201 for (i = 0; i < CCK_TABLE_SIZE; i++)
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203 if (((CurrCCKSwingVal&0xff) == (u32)CCKSwingTable_Ch1_Ch13[i][0]) &&
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204 (((CurrCCKSwingVal&0xff00)>>8) == (u32)CCKSwingTable_Ch1_Ch13[i][1]))
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207 // RT_TRACE(COMP_INIT, DBG_LOUD,("Ch1~13, Current reg0x%x = 0x%lx, CCKSwingIndex=0x%x\n",
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208 // (rCCK0_TxFilter1+2), CurrCCKSwingVal, CCKSwingIndex));
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213 //Write 0xa22 0xa23
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214 TempVal = CCKSwingTable_Ch1_Ch13[CCKSwingIndex][0] +
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215 (CCKSwingTable_Ch1_Ch13[CCKSwingIndex][1]<<8) ;
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218 //Write 0xa24 ~ 0xa27
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220 TempVal2 = CCKSwingTable_Ch1_Ch13[CCKSwingIndex][2] +
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221 (CCKSwingTable_Ch1_Ch13[CCKSwingIndex][3]<<8) +
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222 (CCKSwingTable_Ch1_Ch13[CCKSwingIndex][4]<<16 )+
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223 (CCKSwingTable_Ch1_Ch13[CCKSwingIndex][5]<<24);
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225 //Write 0xa28 0xa29
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227 TempVal3 = CCKSwingTable_Ch1_Ch13[CCKSwingIndex][6] +
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228 (CCKSwingTable_Ch1_Ch13[CCKSwingIndex][7]<<8) ;
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232 for (i = 0; i < CCK_TABLE_SIZE; i++)
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234 if (((CurrCCKSwingVal&0xff) == (u32)CCKSwingTable_Ch14[i][0]) &&
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235 (((CurrCCKSwingVal&0xff00)>>8) == (u32)CCKSwingTable_Ch14[i][1]))
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238 // RT_TRACE(COMP_INIT, DBG_LOUD,("Ch14, Current reg0x%x = 0x%lx, CCKSwingIndex=0x%x\n",
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239 // (rCCK0_TxFilter1+2), CurrCCKSwingVal, CCKSwingIndex));
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244 //Write 0xa22 0xa23
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245 TempVal = CCKSwingTable_Ch14[CCKSwingIndex][0] +
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246 (CCKSwingTable_Ch14[CCKSwingIndex][1]<<8) ;
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248 //Write 0xa24 ~ 0xa27
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250 TempVal2 = CCKSwingTable_Ch14[CCKSwingIndex][2] +
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251 (CCKSwingTable_Ch14[CCKSwingIndex][3]<<8) +
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252 (CCKSwingTable_Ch14[CCKSwingIndex][4]<<16 )+
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253 (CCKSwingTable_Ch14[CCKSwingIndex][5]<<24);
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255 //Write 0xa28 0xa29
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257 TempVal3 = CCKSwingTable_Ch14[CCKSwingIndex][6] +
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258 (CCKSwingTable_Ch14[CCKSwingIndex][7]<<8) ;
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261 write_bbreg(Adapter, rCCK0_TxFilter1, bMaskHWord, TempVal);
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262 write_bbreg(Adapter, rCCK0_TxFilter2, bMaskDWord, TempVal2);
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263 write_bbreg(Adapter, rCCK0_DebugPort, bMaskLWord, TempVal3);
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266 void Hal_MPT_CCKTxPowerAdjustbyIndex(PADAPTER pAdapter, BOOLEAN beven)
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269 u8 CCK_index, CCK_index_old=0;
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270 u8 Action = 0; //0: no action, 1: even->odd, 2:odd->even
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273 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
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274 PMPT_CONTEXT pMptCtx = &pAdapter->mppriv.MptCtx;
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277 if (!IS_92C_SERIAL(pHalData->VersionID))
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280 while(PlatformAtomicExchange(&Adapter->IntrCCKRefCount, TRUE) == TRUE)
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282 PlatformSleepUs(100);
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286 RTPRINT(FINIT, INIT_TxPower,
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287 ("!!!MPT_CCKTxPowerAdjustbyIndex Wait for check CCK gain index too long!!!\n" ));
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292 if (beven && !pMptCtx->bMptIndexEven) //odd->even
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295 pMptCtx->bMptIndexEven = _TRUE;
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297 else if (!beven && pMptCtx->bMptIndexEven) //even->odd
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300 pMptCtx->bMptIndexEven = _FALSE;
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305 //Query CCK default setting From 0xa24
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306 TempCCk = read_bbreg(pAdapter, rCCK0_TxFilter2, bMaskDWord) & bMaskCCK;
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307 for (i = 0; i < CCK_TABLE_SIZE; i++)
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309 if (pHalData->dmpriv.bCCKinCH14)
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311 if (_rtw_memcmp((void*)&TempCCk, (void*)&CCKSwingTable_Ch14[i][2], 4) == _TRUE)
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313 CCK_index_old = (u8) i;
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314 // RTPRINT(FINIT, INIT_TxPower,("MPT_CCKTxPowerAdjustbyIndex: Initial reg0x%x = 0x%lx, CCK_index=0x%x, ch 14 %d\n",
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315 // rCCK0_TxFilter2, TempCCk, CCK_index_old, pHalData->bCCKinCH14));
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321 if (_rtw_memcmp((void*)&TempCCk, (void*)&CCKSwingTable_Ch1_Ch13[i][2], 4) == _TRUE)
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323 CCK_index_old = (u8) i;
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324 // RTPRINT(FINIT, INIT_TxPower,("MPT_CCKTxPowerAdjustbyIndex: Initial reg0x%x = 0x%lx, CCK_index=0x%x, ch14 %d\n",
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325 // rCCK0_TxFilter2, TempCCk, CCK_index_old, pHalData->bCCKinCH14));
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332 if (CCK_index_old == 0)
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334 CCK_index = CCK_index_old - 1;
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336 CCK_index = CCK_index_old + 1;
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339 if (CCK_index == CCK_TABLE_SIZE) {
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340 CCK_index = CCK_TABLE_SIZE -1;
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341 RT_TRACE(_module_mp_, _drv_info_, ("CCK_index == CCK_TABLE_SIZE\n"));
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344 // RTPRINT(FINIT, INIT_TxPower,("MPT_CCKTxPowerAdjustbyIndex: new CCK_index=0x%x\n",
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347 //Adjust CCK according to gain index
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348 if (!pHalData->dmpriv.bCCKinCH14) {
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349 rtw_write8(pAdapter, 0xa22, CCKSwingTable_Ch1_Ch13[CCK_index][0]);
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350 rtw_write8(pAdapter, 0xa23, CCKSwingTable_Ch1_Ch13[CCK_index][1]);
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351 rtw_write8(pAdapter, 0xa24, CCKSwingTable_Ch1_Ch13[CCK_index][2]);
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352 rtw_write8(pAdapter, 0xa25, CCKSwingTable_Ch1_Ch13[CCK_index][3]);
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353 rtw_write8(pAdapter, 0xa26, CCKSwingTable_Ch1_Ch13[CCK_index][4]);
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354 rtw_write8(pAdapter, 0xa27, CCKSwingTable_Ch1_Ch13[CCK_index][5]);
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355 rtw_write8(pAdapter, 0xa28, CCKSwingTable_Ch1_Ch13[CCK_index][6]);
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356 rtw_write8(pAdapter, 0xa29, CCKSwingTable_Ch1_Ch13[CCK_index][7]);
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358 rtw_write8(pAdapter, 0xa22, CCKSwingTable_Ch14[CCK_index][0]);
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359 rtw_write8(pAdapter, 0xa23, CCKSwingTable_Ch14[CCK_index][1]);
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360 rtw_write8(pAdapter, 0xa24, CCKSwingTable_Ch14[CCK_index][2]);
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361 rtw_write8(pAdapter, 0xa25, CCKSwingTable_Ch14[CCK_index][3]);
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362 rtw_write8(pAdapter, 0xa26, CCKSwingTable_Ch14[CCK_index][4]);
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363 rtw_write8(pAdapter, 0xa27, CCKSwingTable_Ch14[CCK_index][5]);
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364 rtw_write8(pAdapter, 0xa28, CCKSwingTable_Ch14[CCK_index][6]);
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365 rtw_write8(pAdapter, 0xa29, CCKSwingTable_Ch14[CCK_index][7]);
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369 RTPRINT(FINIT, INIT_TxPower,
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370 ("MPT_CCKTxPowerAdjustbyIndex 0xa20=%x\n", PlatformEFIORead4Byte(Adapter, 0xa20)));
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372 PlatformAtomicExchange(&Adapter->IntrCCKRefCount, FALSE);
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375 /*---------------------------hal\rtl8192c\MPT_HelperFunc.c---------------------------*/
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380 * Use H2C command to change channel,
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381 * not only modify rf register, but also other setting need to be done.
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383 void Hal_SetChannel(PADAPTER pAdapter)
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386 struct mp_priv *pmp = &pAdapter->mppriv;
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388 // SelectChannel(pAdapter, pmp->channel);
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389 set_channel_bwmode(pAdapter, pmp->channel, pmp->channel_offset, pmp->bandwidth);
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393 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
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394 struct mp_priv *pmp = &pAdapter->mppriv;
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395 u8 channel = pmp->channel;
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396 u8 bandwidth = pmp->bandwidth;
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397 u8 rate = pmp->rateidx;
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400 // set RF channel register
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401 for (eRFPath = 0; eRFPath < pHalData->NumTotalRFPath; eRFPath++)
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403 if(IS_HARDWARE_TYPE_8192D(pAdapter))
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404 _write_rfreg(pAdapter, (RF_PATH)eRFPath, rRfChannel, 0xFF, channel);
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406 _write_rfreg(pAdapter, eRFPath, rRfChannel, 0x3FF, channel);
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408 Hal_mpt_SwitchRfSetting(pAdapter);
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410 SelectChannel(pAdapter, channel);
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412 if (pHalData->CurrentChannel == 14 && !pHalData->dmpriv.bCCKinCH14) {
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413 pHalData->dmpriv.bCCKinCH14 = _TRUE;
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414 Hal_MPT_CCKTxPowerAdjust(pAdapter, pHalData->dmpriv.bCCKinCH14);
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416 else if (pHalData->CurrentChannel != 14 && pHalData->dmpriv.bCCKinCH14) {
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417 pHalData->dmpriv.bCCKinCH14 = _FALSE;
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418 Hal_MPT_CCKTxPowerAdjust(pAdapter, pHalData->dmpriv.bCCKinCH14);
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426 * Switch bandwitdth may change center frequency(channel)
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428 void Hal_SetBandwidth(PADAPTER pAdapter)
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430 struct mp_priv *pmp = &pAdapter->mppriv;
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433 SetBWMode(pAdapter, pmp->bandwidth, pmp->prime_channel_offset);
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434 Hal_mpt_SwitchRfSetting(pAdapter);
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437 void Hal_SetCCKTxPower(PADAPTER pAdapter, u8 *TxPower)
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442 // rf-A cck tx power
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443 write_bbreg(pAdapter, rTxAGC_A_CCK1_Mcs32, bMaskByte1, TxPower[RF_PATH_A]);
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444 tmpval = (TxPower[RF_PATH_A]<<16) | (TxPower[RF_PATH_A]<<8) | TxPower[RF_PATH_A];
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445 write_bbreg(pAdapter, rTxAGC_B_CCK11_A_CCK2_11, bMaskH3Bytes, tmpval);
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447 // rf-B cck tx power
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448 write_bbreg(pAdapter, rTxAGC_B_CCK11_A_CCK2_11, bMaskByte0, TxPower[RF_PATH_B]);
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449 tmpval = (TxPower[RF_PATH_B]<<16) | (TxPower[RF_PATH_B]<<8) | TxPower[RF_PATH_B];
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450 write_bbreg(pAdapter, rTxAGC_B_CCK1_55_Mcs32, bMaskH3Bytes, tmpval);
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452 RT_TRACE(_module_mp_, _drv_notice_,
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453 ("-SetCCKTxPower: A[0x%02x] B[0x%02x]\n",
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454 TxPower[RF_PATH_A], TxPower[RF_PATH_B]));
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457 void Hal_SetOFDMTxPower(PADAPTER pAdapter, u8 *TxPower)
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461 PMPT_CONTEXT pMptCtx = &pAdapter->mppriv.MptCtx;
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462 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
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466 tmpval = TxPower[RF_PATH_A];
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467 TxAGC = (tmpval<<24) | (tmpval<<16) | (tmpval<<8) | tmpval;
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469 write_bbreg(pAdapter, rTxAGC_A_Rate18_06, bMaskDWord, TxAGC);
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470 write_bbreg(pAdapter, rTxAGC_A_Rate54_24, bMaskDWord, TxAGC);
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471 write_bbreg(pAdapter, rTxAGC_A_Mcs03_Mcs00, bMaskDWord, TxAGC);
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472 write_bbreg(pAdapter, rTxAGC_A_Mcs07_Mcs04, bMaskDWord, TxAGC);
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473 write_bbreg(pAdapter, rTxAGC_A_Mcs11_Mcs08, bMaskDWord, TxAGC);
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474 write_bbreg(pAdapter, rTxAGC_A_Mcs15_Mcs12, bMaskDWord, TxAGC);
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477 tmpval = TxPower[RF_PATH_B];
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478 TxAGC = (tmpval<<24) | (tmpval<<16) | (tmpval<<8) | tmpval;
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480 write_bbreg(pAdapter, rTxAGC_B_Rate18_06, bMaskDWord, TxAGC);
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481 write_bbreg(pAdapter, rTxAGC_B_Rate54_24, bMaskDWord, TxAGC);
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482 write_bbreg(pAdapter, rTxAGC_B_Mcs03_Mcs00, bMaskDWord, TxAGC);
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483 write_bbreg(pAdapter, rTxAGC_B_Mcs07_Mcs04, bMaskDWord, TxAGC);
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484 write_bbreg(pAdapter, rTxAGC_B_Mcs11_Mcs08, bMaskDWord, TxAGC);
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485 write_bbreg(pAdapter, rTxAGC_B_Mcs15_Mcs12, bMaskDWord, TxAGC);
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487 RT_TRACE(_module_mp_, _drv_notice_,
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488 ("-SetOFDMTxPower: A[0x%02x] B[0x%02x]\n",
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489 TxPower[RF_PATH_A], TxPower[RF_PATH_B]));
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492 void Hal_SetAntennaPathPower(PADAPTER pAdapter)
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494 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
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495 u8 TxPowerLevel[MAX_RF_PATH_NUMS];
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498 TxPowerLevel[RF_PATH_A] = pAdapter->mppriv.txpoweridx;
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499 TxPowerLevel[RF_PATH_B] = pAdapter->mppriv.txpoweridx_b;
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501 switch (pAdapter->mppriv.antenna_tx)
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505 rfPath = RF_PATH_A;
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508 rfPath = RF_PATH_B;
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511 rfPath = RF_PATH_C;
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515 switch (pHalData->rf_chip)
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520 Hal_SetCCKTxPower(pAdapter, TxPowerLevel);
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521 if (pAdapter->mppriv.rateidx < MPT_RATE_6M) // CCK rate
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522 Hal_MPT_CCKTxPowerAdjustbyIndex(pAdapter, TxPowerLevel[rfPath]%2 == 0);
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523 Hal_SetOFDMTxPower(pAdapter, TxPowerLevel);
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535 IN PADAPTER pAdapter,
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536 IN MPT_TXPWR_DEF Rate,
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537 IN pu1Byte pTxPower
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540 if (IS_HARDWARE_TYPE_JAGUAR(pAdapter))
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542 //mpt_SetTxPower_8812(pAdapter, Rate, pTxPower);
\r
551 u4Byte TxAGC = 0, pwr=0;
\r
554 pwr = pTxPower[ODM_RF_PATH_A];
\r
555 TxAGC = (pwr<<16)|(pwr<<8)|(pwr);
\r
556 PHY_SetBBReg(pAdapter, rTxAGC_A_CCK1_Mcs32, bMaskByte1, pTxPower[ODM_RF_PATH_A]);
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557 PHY_SetBBReg(pAdapter, rTxAGC_B_CCK11_A_CCK2_11, bMaskH3Bytes, TxAGC);
\r
559 pwr = pTxPower[ODM_RF_PATH_B];
\r
560 TxAGC = (pwr<<16)|(pwr<<8)|(pwr);
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561 PHY_SetBBReg(pAdapter, rTxAGC_B_CCK11_A_CCK2_11, bMaskByte0, pTxPower[ODM_RF_PATH_B]);
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562 PHY_SetBBReg(pAdapter, rTxAGC_B_CCK1_55_Mcs32, bMaskH3Bytes, TxAGC);
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570 PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.MptCtx);
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571 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
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574 TxAGC |= ((pwr<<24)|(pwr<<16)|(pwr<<8)|pwr);
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575 DBG_8192C("HT Tx-rf(A) Power = 0x%x\n", TxAGC);
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577 PHY_SetBBReg(pAdapter, rTxAGC_A_Rate18_06, bMaskDWord, TxAGC);
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578 PHY_SetBBReg(pAdapter, rTxAGC_A_Rate54_24, bMaskDWord, TxAGC);
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579 PHY_SetBBReg(pAdapter, rTxAGC_A_Mcs03_Mcs00, bMaskDWord, TxAGC);
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580 PHY_SetBBReg(pAdapter, rTxAGC_A_Mcs07_Mcs04, bMaskDWord, TxAGC);
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581 PHY_SetBBReg(pAdapter, rTxAGC_A_Mcs11_Mcs08, bMaskDWord, TxAGC);
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582 PHY_SetBBReg(pAdapter, rTxAGC_A_Mcs15_Mcs12, bMaskDWord, TxAGC);
\r
586 TxAGC |= ((pwr<<24)|(pwr<<16)|(pwr<<8)|pwr);
\r
587 DBG_8192C("HT Tx-rf(B) Power = 0x%x\n", TxAGC);
\r
589 PHY_SetBBReg(pAdapter, rTxAGC_B_Rate18_06, bMaskDWord, TxAGC);
\r
590 PHY_SetBBReg(pAdapter, rTxAGC_B_Rate54_24, bMaskDWord, TxAGC);
\r
591 PHY_SetBBReg(pAdapter, rTxAGC_B_Mcs03_Mcs00, bMaskDWord, TxAGC);
\r
592 PHY_SetBBReg(pAdapter, rTxAGC_B_Mcs07_Mcs04, bMaskDWord, TxAGC);
\r
593 PHY_SetBBReg(pAdapter, rTxAGC_B_Mcs11_Mcs08, bMaskDWord, TxAGC);
\r
594 PHY_SetBBReg(pAdapter, rTxAGC_B_Mcs15_Mcs12, bMaskDWord, TxAGC);
\r
605 void Hal_SetTxPower(PADAPTER pAdapter)
\r
607 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
\r
608 PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.MptCtx);
\r
609 PDM_ODM_T pDM_Odm = &pHalData->odmpriv;
\r
610 u8 TxPowerLevel[MAX_RF_PATH];
\r
613 //#if DEV_BUS_TYPE == RT_USB_INTERFACE || DEV_BUS_TYPE == RT_SDIO_INTERFACE
\r
614 //RT_ASSERT((KeGetCurrentIrql() == PASSIVE_LEVEL), ("MPT_ProSetTxPower(): not in PASSIVE_LEVEL!\n"));
\r
617 path = (pHalData->AntennaTxPath == ANTENNA_A) ? (ODM_RF_PATH_A) : (ODM_RF_PATH_B);
\r
619 if (pHalData->rf_chip < RF_TYPE_MAX)
\r
621 if (IS_HARDWARE_TYPE_JAGUAR(pAdapter))
\r
624 DBG_8192C("===> MPT_ProSetTxPower: Jaguar\n");
\r
626 mpt_SetTxPower_8812(pAdapter, MPT_CCK, pMptCtx->TxPwrLevel);
\r
627 mpt_SetTxPower_8812(pAdapter, MPT_OFDM, pMptCtx->TxPwrLevel);
\r
628 mpt_SetTxPower_8812(pAdapter, MPT_VHT_OFDM, pMptCtx->TxPwrLevel);
\r
633 DBG_8192C("===> MPT_ProSetTxPower: Others\n");
\r
634 mpt_SetTxPower(pAdapter, MPT_CCK, pMptCtx->TxPwrLevel);
\r
635 Hal_MPT_CCKTxPowerAdjustbyIndex(pAdapter, pMptCtx->TxPwrLevel[path]%2 == 0);
\r
636 mpt_SetTxPower(pAdapter, MPT_OFDM, pMptCtx->TxPwrLevel);
\r
641 DBG_8192C("RFChipID < RF_TYPE_MAX, the RF chip is not supported - %d\n", pHalData->rf_chip);
\r
644 ODM_ClearTxPowerTrackingState(pDM_Odm);
\r
648 void Hal_SetTxAGCOffset(PADAPTER pAdapter, u32 ulTxAGCOffset)
\r
651 u32 TxAGCOffset_B, TxAGCOffset_C, TxAGCOffset_D,tmpAGC;
\r
654 TxAGCOffset_B = (ulTxAGCOffset&0x000000ff);
\r
655 TxAGCOffset_C = ((ulTxAGCOffset&0x0000ff00)>>8);
\r
656 TxAGCOffset_D = ((ulTxAGCOffset&0x00ff0000)>>16);
\r
658 tmpAGC = (TxAGCOffset_D<<8 | TxAGCOffset_C<<4 | TxAGCOffset_B);
\r
659 write_bbreg(pAdapter, rFPGA0_TxGainStage,
\r
660 (bXBTxAGC|bXCTxAGC|bXDTxAGC), tmpAGC);
\r
664 void Hal_SetDataRate(PADAPTER pAdapter)
\r
666 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
\r
667 PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.MptCtx);
\r
670 DataRate=MptToMgntRate(pAdapter->mppriv.rateidx);
\r
672 if(!IS_HARDWARE_TYPE_8723A(pAdapter))
\r
673 Hal_mpt_SwitchRfSetting(pAdapter);
\r
674 if (IS_CCK_RATE(DataRate))
\r
676 if (pMptCtx->MptRfPath == ODM_RF_PATH_A) // S1
\r
677 PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, 0x51, 0xF, 0x6);
\r
679 PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, 0x71, 0xF, 0x6);
\r
683 if (pMptCtx->MptRfPath == ODM_RF_PATH_A) // S1
\r
684 PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, 0x51, 0xF, 0xE);
\r
686 PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, 0x71, 0xF, 0xE);
\r
689 // <20130913, Kordan> 8723BS TFBGA uses the default setting.
\r
690 if ((IS_HARDWARE_TYPE_8723BS(pAdapter) &&
\r
691 ((pHalData->PackageType == PACKAGE_TFBGA79) || (pHalData->PackageType == PACKAGE_TFBGA90))))
\r
693 if (pMptCtx->MptRfPath == ODM_RF_PATH_A) // S1
\r
694 PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, 0x51, 0xF, 0xE);
\r
696 PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, 0x71, 0xF, 0xE);
\r
700 #define RF_PATH_AB 22
\r
702 void Hal_SetAntenna(PADAPTER pAdapter)
\r
704 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
\r
705 u4Byte ulAntennaTx, ulAntennaRx;
\r
706 PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.MptCtx);
\r
707 PDM_ODM_T pDM_Odm = &pHalData->odmpriv;
\r
708 PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo);
\r
710 ulAntennaTx = pHalData->AntennaTxPath;
\r
711 ulAntennaRx = pHalData->AntennaRxPath;
\r
713 if (pHalData->rf_chip>= RF_TYPE_MAX)
\r
715 DBG_8192C("This RF chip ID is not supported\n");
\r
719 switch (pAdapter->mppriv.antenna_tx)
\r
721 u1Byte p = 0, i = 0;
\r
723 case ANTENNA_A: // Actually path S1 (Wi-Fi)
\r
725 pMptCtx->MptRfPath = ODM_RF_PATH_A;
\r
726 PHY_SetBBReg(pAdapter, rS0S1_PathSwitch, BIT9|BIT8|BIT7, 0x0);
\r
727 PHY_SetBBReg(pAdapter, 0xB2C, BIT31, 0x0); // AGC Table Sel
\r
729 //<20130522, Kordan> 0x51 and 0x71 should be set immediately after path switched, or they might be overwritten.
\r
730 if ((pHalData->PackageType == PACKAGE_TFBGA79) || (pHalData->PackageType == PACKAGE_TFBGA90))
\r
731 PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, 0x51, bRFRegOffsetMask, 0x6B10E);
\r
733 PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, 0x51, bRFRegOffsetMask, 0x6B04E);
\r
736 for (i = 0; i < 3; ++i)
\r
738 u4Byte offset = pRFCalibrateInfo->TxIQC_8723B[ODM_RF_PATH_A][i][0];
\r
739 u4Byte data = pRFCalibrateInfo->TxIQC_8723B[ODM_RF_PATH_A][i][1];
\r
741 PHY_SetBBReg(pAdapter, offset, bMaskDWord, data);
\r
742 DBG_8192C("Switch to S1 TxIQC(offset, data) = (0x%X, 0x%X)\n", offset, data);
\r
746 for (i = 0; i < 2; ++i)
\r
748 u4Byte offset = pRFCalibrateInfo->RxIQC_8723B[ODM_RF_PATH_A][i][0];
\r
749 u4Byte data = pRFCalibrateInfo->RxIQC_8723B[ODM_RF_PATH_A][i][1];
\r
751 PHY_SetBBReg(pAdapter, offset, bMaskDWord, data);
\r
752 DBG_8192C("Switch to S1 RxIQC (offset, data) = (0x%X, 0x%X)\n", offset, data);
\r
757 case ANTENNA_B: // Actually path S0 (BT)
\r
759 pMptCtx->MptRfPath = ODM_RF_PATH_B;
\r
760 PHY_SetBBReg(pAdapter, rS0S1_PathSwitch, BIT9|BIT8|BIT7, 0x5);
\r
761 PHY_SetBBReg(pAdapter, 0xB2C, BIT31, 0x1); // AGC Table Sel
\r
763 //<20130522, Kordan> 0x51 and 0x71 should be set immediately after path switched, or they might be overwritten.
\r
764 if ((pHalData->PackageType == PACKAGE_TFBGA79) || (pHalData->PackageType == PACKAGE_TFBGA90))
\r
765 PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, 0x51, bRFRegOffsetMask, 0x6B10E);
\r
767 PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, 0x51, bRFRegOffsetMask, 0x6B04E);
\r
770 for (i = 0; i < 3; ++i)
\r
772 // <20130603, Kordan> Because BB suppors only 1T1R, we restore IQC to S1 instead of S0.
\r
773 u4Byte offset = pRFCalibrateInfo->TxIQC_8723B[ODM_RF_PATH_A][i][0];
\r
774 u4Byte data = pRFCalibrateInfo->TxIQC_8723B[ODM_RF_PATH_B][i][1];
\r
775 if (pRFCalibrateInfo->TxIQC_8723B[ODM_RF_PATH_B][i][0] != 0) {
\r
776 PHY_SetBBReg(pAdapter, offset, bMaskDWord, data);
\r
777 DBG_8192C("Switch to S0 TxIQC (offset, data) = (0x%X, 0x%X)\n", offset, data);
\r
780 for (i = 0; i < 2; ++i)
\r
782 // <20130603, Kordan> Because BB suppors only 1T1R, we restore IQC to S1 instead of S0.
\r
783 u4Byte offset = pRFCalibrateInfo->RxIQC_8723B[ODM_RF_PATH_A][i][0];
\r
784 u4Byte data = pRFCalibrateInfo->RxIQC_8723B[ODM_RF_PATH_B][i][1];
\r
785 if (pRFCalibrateInfo->RxIQC_8723B[ODM_RF_PATH_B][i][0] != 0) {
\r
786 PHY_SetBBReg(pAdapter, offset, bMaskDWord, data);
\r
787 DBG_8192C("Switch to S0 RxIQC (offset, data) = (0x%X, 0x%X)\n", offset, data);
\r
794 pMptCtx->MptRfPath = RF_PATH_AB;
\r
795 RT_TRACE(_module_mp_, _drv_notice_, ("Unknown Tx antenna.\n"));
\r
799 RT_TRACE(_module_mp_, _drv_notice_, ("-SwitchAntenna: finished\n"));
\r
802 s32 Hal_SetThermalMeter(PADAPTER pAdapter, u8 target_ther)
\r
804 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
\r
807 if (!netif_running(pAdapter->pnetdev)) {
\r
808 RT_TRACE(_module_mp_, _drv_warning_, ("SetThermalMeter! Fail: interface not opened!\n"));
\r
812 if (check_fwstate(&pAdapter->mlmepriv, WIFI_MP_STATE) == _FALSE) {
\r
813 RT_TRACE(_module_mp_, _drv_warning_, ("SetThermalMeter: Fail! not in MP mode!\n"));
\r
817 target_ther &= 0xff;
\r
818 if (target_ther < 0x07)
\r
819 target_ther = 0x07;
\r
820 else if (target_ther > 0x1d)
\r
821 target_ther = 0x1d;
\r
823 pHalData->EEPROMThermalMeter = target_ther;
\r
828 void Hal_TriggerRFThermalMeter(PADAPTER pAdapter)
\r
830 PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, RF_T_METER_8723B, BIT17 | BIT16, 0x03);
\r
831 // RT_TRACE(_module_mp_,_drv_alert_, ("TriggerRFThermalMeter() finished.\n" ));
\r
834 u8 Hal_ReadRFThermalMeter(PADAPTER pAdapter)
\r
836 u32 ThermalValue = 0;
\r
838 ThermalValue = (u1Byte)PHY_QueryRFReg(pAdapter, ODM_RF_PATH_A, RF_T_METER_8723B, 0xfc00); // 0x42: RF Reg[15:10]
\r
840 return (u8)ThermalValue;
\r
843 void Hal_GetThermalMeter(PADAPTER pAdapter, u8 *value)
\r
846 fw_cmd(pAdapter, IOCMD_GET_THERMAL_METER);
\r
847 rtw_msleep_os(1000);
\r
848 fw_cmd_data(pAdapter, value, 1);
\r
852 Hal_TriggerRFThermalMeter(pAdapter);
\r
853 rtw_msleep_os(1000);
\r
854 *value = Hal_ReadRFThermalMeter(pAdapter);
\r
858 void Hal_SetSingleCarrierTx(PADAPTER pAdapter, u8 bStart)
\r
860 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
\r
861 pAdapter->mppriv.MptCtx.bSingleCarrier = bStart;
\r
862 if (bStart)// Start Single Carrier.
\r
864 RT_TRACE(_module_mp_,_drv_alert_, ("SetSingleCarrierTx: test start\n"));
\r
865 // Start Single Carrier.
\r
866 // 1. if OFDM block on?
\r
867 if(!PHY_QueryBBReg(pAdapter, rFPGA0_RFMOD, bOFDMEn))
\r
868 PHY_SetBBReg(pAdapter, rFPGA0_RFMOD, bOFDMEn, 1);//set OFDM block on
\r
870 // 2. set CCK test mode off, set to CCK normal mode
\r
871 PHY_SetBBReg(pAdapter, rCCK0_System, bCCKBBMode, 0);
\r
873 // 3. turn on scramble setting
\r
874 PHY_SetBBReg(pAdapter, rCCK0_System, bCCKScramble, 1);
\r
876 // 4. Turn On Continue Tx and turn off the other test modes.
\r
877 //if (IS_HARDWARE_TYPE_JAGUAR(pAdapter))
\r
878 //PHY_SetBBReg(pAdapter, rSingleTone_ContTx_Jaguar, BIT18|BIT17|BIT16, OFDM_SingleCarrier);
\r
880 PHY_SetBBReg(pAdapter, rOFDM1_LSTF, BIT30|BIT29|BIT28, OFDM_SingleCarrier);
\r
882 else// Stop Single Carrier.
\r
884 // Stop Single Carrier.
\r
885 // Turn off all test modes.
\r
886 //if (IS_HARDWARE_TYPE_JAGUAR(pAdapter))
\r
887 // PHY_SetBBReg(pAdapter, rSingleTone_ContTx_Jaguar, BIT18|BIT17|BIT16, OFDM_ALL_OFF);
\r
889 PHY_SetBBReg(pAdapter, rOFDM1_LSTF, BIT30|BIT29|BIT28, OFDM_ALL_OFF);
\r
893 PHY_SetBBReg(pAdapter, rPMAC_Reset, bBBResetB, 0x0);
\r
894 PHY_SetBBReg(pAdapter, rPMAC_Reset, bBBResetB, 0x1);
\r
899 void Hal_SetSingleToneTx(PADAPTER pAdapter, u8 bStart)
\r
901 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
\r
902 PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.MptCtx);
\r
903 BOOLEAN is92C = IS_92C_SERIAL(pHalData->VersionID);
\r
904 static u4Byte reg58 = 0x0;
\r
905 static u4Byte regRF0x0 = 0x0;
\r
906 static u4Byte reg0xCB0 = 0x0;
\r
907 static u4Byte reg0xEB0 = 0x0;
\r
908 static u4Byte reg0xCB4 = 0x0;
\r
909 static u4Byte reg0xEB4 = 0x0;
\r
912 switch (pAdapter->mppriv.antenna_tx)
\r
916 pMptCtx->MptRfPath = rfPath = RF_PATH_A;
\r
919 pMptCtx->MptRfPath = rfPath = RF_PATH_B;
\r
922 pMptCtx->MptRfPath = rfPath = RF_PATH_C;
\r
926 pAdapter->mppriv.MptCtx.bSingleTone = bStart;
\r
927 if (bStart)// Start Single Tone.
\r
930 // <20120326, Kordan> To amplify the power of tone for Xtal calibration. (asked by Edlu)
\r
931 if (IS_HARDWARE_TYPE_8188E(pAdapter))
\r
933 reg58 = PHY_QueryRFReg(pAdapter, rfPath, LNA_Low_Gain_3, bRFRegOffsetMask);
\r
934 if (rfPath == ODM_RF_PATH_A)
\r
935 pMptCtx->backup0x58_RF_A = reg58;
\r
937 pMptCtx->backup0x58_RF_B = reg58;
\r
939 PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, LNA_Low_Gain_3, BIT1, 0x1); // RF LO enabled
\r
940 PHY_SetBBReg(pAdapter, rFPGA0_RFMOD, bCCKEn, 0x0);
\r
941 PHY_SetBBReg(pAdapter, rFPGA0_RFMOD, bOFDMEn, 0x0);
\r
945 else if (IS_HARDWARE_TYPE_8192E(pAdapter))
\r
946 { // USB need to do RF LO disable first, PCIE isn't required to follow this order.
\r
947 PHY_SetRFReg(pAdapter, pMptCtx->MptRfPath, LNA_Low_Gain_3, BIT1, 0x1); // RF LO disabled
\r
948 PHY_SetRFReg(pAdapter, pMptCtx->MptRfPath, RF_AC, 0xF0000, 0x2); // Tx mode
\r
950 else if (IS_HARDWARE_TYPE_8723B(pAdapter))
\r
952 if (pMptCtx->MptRfPath == ODM_RF_PATH_A) {
\r
953 PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, RF_AC, 0xF0000, 0x2); // Tx mode
\r
954 PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, 0x56, 0xF, 0x1); // RF LO enabled
\r
956 // S0/S1 both use PATH A to configure
\r
957 PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, RF_AC, 0xF0000, 0x2); // Tx mode
\r
958 PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, 0x76, 0xF, 0x1); // RF LO enabled
\r
961 else if (IS_HARDWARE_TYPE_JAGUAR(pAdapter))
\r
964 u1Byte p = ODM_RF_PATH_A;
\r
966 regRF0x0 = PHY_QueryRFReg(pAdapter, ODM_RF_PATH_A, RF_AC_Jaguar, bRFRegOffsetMask);
\r
967 reg0xCB0 = PHY_QueryBBReg(pAdapter, rA_RFE_Pinmux_Jaguar, bMaskDWord);
\r
968 reg0xEB0 = PHY_QueryBBReg(pAdapter, rB_RFE_Pinmux_Jaguar, bMaskDWord);
\r
969 reg0xCB4 = PHY_QueryBBReg(pAdapter, rA_RFE_Pinmux_Jaguar+4, bMaskDWord);
\r
970 reg0xEB4 = PHY_QueryBBReg(pAdapter, rB_RFE_Pinmux_Jaguar+4, bMaskDWord);
\r
972 PHY_SetBBReg(pAdapter, rOFDMCCKEN_Jaguar, BIT29|BIT28, 0x0); // Disable CCK and OFDM
\r
974 if (pMptCtx->MptRfPath == RF_PATH_AB) {
\r
975 for (p = ODM_RF_PATH_A; p <= ODM_RF_PATH_B; ++p) {
\r
976 PHY_SetRFReg(pAdapter, p, RF_AC_Jaguar, 0xF0000, 0x2); // Tx mode: RF0x00[19:16]=4'b0010
\r
977 PHY_SetRFReg(pAdapter, p, RF_AC_Jaguar, 0x1F, 0x0); // Lowest RF gain index: RF_0x0[4:0] = 0
\r
978 PHY_SetRFReg(pAdapter, p, LNA_Low_Gain_3, BIT1, 0x1); // RF LO enabled
\r
981 PHY_SetRFReg(pAdapter, pMptCtx->MptRfPath, RF_AC_Jaguar, 0xF0000, 0x2); // Tx mode: RF0x00[19:16]=4'b0010
\r
982 PHY_SetRFReg(pAdapter, pMptCtx->MptRfPath, RF_AC_Jaguar, 0x1F, 0x0); // Lowest RF gain index: RF_0x0[4:0] = 0
\r
983 PHY_SetRFReg(pAdapter, pMptCtx->MptRfPath, LNA_Low_Gain_3, BIT1, 0x1); // RF LO enabled
\r
987 PHY_SetBBReg(pAdapter, rA_RFE_Pinmux_Jaguar, 0xFF00F0, 0x77007); // 0xCB0[[23:16, 7:4] = 0x77007
\r
988 PHY_SetBBReg(pAdapter, rB_RFE_Pinmux_Jaguar, 0xFF00F0, 0x77007); // 0xCB0[[23:16, 7:4] = 0x77007
\r
990 if (pHalData->ExternalPA_5G) {
\r
992 PHY_SetBBReg(pAdapter, rA_RFE_Pinmux_Jaguar+4, 0xFF00000, 0x12); // 0xCB4[23:16] = 0x12
\r
993 PHY_SetBBReg(pAdapter, rB_RFE_Pinmux_Jaguar+4, 0xFF00000, 0x12); // 0xEB4[23:16] = 0x12
\r
994 } else if (pHalData->ExternalPA_2G) {
\r
995 PHY_SetBBReg(pAdapter, rA_RFE_Pinmux_Jaguar+4, 0xFF00000, 0x11); // 0xCB4[23:16] = 0x11
\r
996 PHY_SetBBReg(pAdapter, rB_RFE_Pinmux_Jaguar+4, 0xFF00000, 0x11); // 0xEB4[23:16] = 0x11
\r
1002 // Turn On SingleTone and turn off the other test modes.
\r
1003 PHY_SetBBReg(pAdapter, rOFDM1_LSTF, BIT30|BIT29|BIT28, OFDM_SingleTone);
\r
1007 write_bbreg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000500);
\r
1008 write_bbreg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000500);
\r
1011 else// Stop Single Tone.
\r
1013 // Stop Single Tone.
\r
1014 if (IS_HARDWARE_TYPE_8188E(pAdapter))
\r
1016 PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, LNA_Low_Gain_3, bRFRegOffsetMask, pMptCtx->backup0x58_RF_A);
\r
1018 PHY_SetBBReg(pAdapter, rFPGA0_RFMOD, bCCKEn, 0x1);
\r
1019 PHY_SetBBReg(pAdapter, rFPGA0_RFMOD, bOFDMEn, 0x1);
\r
1021 else if (IS_HARDWARE_TYPE_8192E(pAdapter))
\r
1023 PHY_SetRFReg(pAdapter, pMptCtx->MptRfPath, RF_AC, 0xF0000, 0x3); // Tx mode
\r
1024 PHY_SetRFReg(pAdapter, pMptCtx->MptRfPath, LNA_Low_Gain_3, BIT1, 0x0); // RF LO disabled
\r
1026 else if (IS_HARDWARE_TYPE_8723B(pAdapter))
\r
1028 if (pMptCtx->MptRfPath == ODM_RF_PATH_A) {
\r
1029 PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, RF_AC, 0xF0000, 0x3); // Rx mode
\r
1030 PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, 0x56, 0xF, 0x0); // RF LO disabled
\r
1032 // S0/S1 both use PATH A to configure
\r
1033 PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, RF_AC, 0xF0000, 0x3); // Rx mode
\r
1034 PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, 0x76, 0xF, 0x0); // RF LO disabled
\r
1037 else if (IS_HARDWARE_TYPE_JAGUAR(pAdapter))
\r
1040 u1Byte p = ODM_RF_PATH_A;
\r
1042 PHY_SetBBReg(pAdapter, rOFDMCCKEN_Jaguar, BIT29|BIT28, 0x3); // Disable CCK and OFDM
\r
1044 if (pMptCtx->MptRfPath == RF_PATH_AB) {
\r
1045 for (p = ODM_RF_PATH_A; p <= ODM_RF_PATH_B; ++p) {
\r
1046 PHY_SetRFReg(pAdapter, p, RF_AC_Jaguar, bRFRegOffsetMask, regRF0x0);
\r
1047 PHY_SetRFReg(pAdapter, p, LNA_Low_Gain_3, BIT1, 0x0); // RF LO disabled
\r
1050 PHY_SetRFReg(pAdapter, p, RF_AC_Jaguar, bRFRegOffsetMask, regRF0x0);
\r
1051 PHY_SetRFReg(pAdapter, p, LNA_Low_Gain_3, BIT1, 0x0); // RF LO disabled
\r
1053 PHY_SetBBReg(pAdapter, rA_RFE_Pinmux_Jaguar, bMaskDWord, reg0xCB0);
\r
1054 PHY_SetBBReg(pAdapter, rB_RFE_Pinmux_Jaguar, bMaskDWord, reg0xEB0);
\r
1055 PHY_SetBBReg(pAdapter, rA_RFE_Pinmux_Jaguar+4, bMaskDWord, reg0xCB4);
\r
1056 PHY_SetBBReg(pAdapter, rB_RFE_Pinmux_Jaguar+4, bMaskDWord, reg0xEB4);
\r
1061 // Turn off all test modes.
\r
1063 PHY_SetBBReg(pAdapter, rSingleTone_ContTx_Jaguar, BIT18|BIT17|BIT16, OFDM_ALL_OFF);
\r
1067 write_bbreg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000100);
\r
1068 write_bbreg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000100);
\r
1075 void Hal_SetCarrierSuppressionTx(PADAPTER pAdapter, u8 bStart)
\r
1077 pAdapter->mppriv.MptCtx.bCarrierSuppression = bStart;
\r
1078 if (bStart) // Start Carrier Suppression.
\r
1080 RT_TRACE(_module_mp_,_drv_alert_, ("SetCarrierSuppressionTx: test start\n"));
\r
1081 //if(pMgntInfo->dot11CurrentWirelessMode == WIRELESS_MODE_B)
\r
1082 if (pAdapter->mppriv.rateidx <= MPT_RATE_11M)
\r
1084 // 1. if CCK block on?
\r
1085 if(!read_bbreg(pAdapter, rFPGA0_RFMOD, bCCKEn))
\r
1086 write_bbreg(pAdapter, rFPGA0_RFMOD, bCCKEn, bEnable);//set CCK block on
\r
1088 //Turn Off All Test Mode
\r
1089 write_bbreg(pAdapter, rOFDM1_LSTF, bOFDMContinueTx, bDisable);
\r
1090 write_bbreg(pAdapter, rOFDM1_LSTF, bOFDMSingleCarrier, bDisable);
\r
1091 write_bbreg(pAdapter, rOFDM1_LSTF, bOFDMSingleTone, bDisable);
\r
1093 write_bbreg(pAdapter, rCCK0_System, bCCKBBMode, 0x2); //transmit mode
\r
1094 write_bbreg(pAdapter, rCCK0_System, bCCKScramble, 0x0); //turn off scramble setting
\r
1096 //Set CCK Tx Test Rate
\r
1097 //PHY_SetBBReg(pAdapter, rCCK0_System, bCCKTxRate, pMgntInfo->ForcedDataRate);
\r
1098 write_bbreg(pAdapter, rCCK0_System, bCCKTxRate, 0x0); //Set FTxRate to 1Mbps
\r
1101 //Set for dynamic set Power index
\r
1102 write_bbreg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000500);
\r
1103 write_bbreg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000500);
\r
1106 else// Stop Carrier Suppression.
\r
1108 RT_TRACE(_module_mp_,_drv_alert_, ("SetCarrierSuppressionTx: test stop\n"));
\r
1109 //if(pMgntInfo->dot11CurrentWirelessMode == WIRELESS_MODE_B)
\r
1110 if (pAdapter->mppriv.rateidx <= MPT_RATE_11M ) {
\r
1111 write_bbreg(pAdapter, rCCK0_System, bCCKBBMode, 0x0); //normal mode
\r
1112 write_bbreg(pAdapter, rCCK0_System, bCCKScramble, 0x1); //turn on scramble setting
\r
1115 write_bbreg(pAdapter, rPMAC_Reset, bBBResetB, 0x0);
\r
1116 write_bbreg(pAdapter, rPMAC_Reset, bBBResetB, 0x1);
\r
1118 //Stop for dynamic set Power index
\r
1119 write_bbreg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000100);
\r
1120 write_bbreg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000100);
\r
1122 //DbgPrint("\n MPT_ProSetCarrierSupp() is finished. \n");
\r
1125 void Hal_SetCCKContinuousTx(PADAPTER pAdapter, u8 bStart)
\r
1131 RT_TRACE(_module_mp_, _drv_alert_,
\r
1132 ("SetCCKContinuousTx: test start\n"));
\r
1134 // 1. if CCK block on?
\r
1135 if(!read_bbreg(pAdapter, rFPGA0_RFMOD, bCCKEn))
\r
1136 write_bbreg(pAdapter, rFPGA0_RFMOD, bCCKEn, bEnable);//set CCK block on
\r
1138 //Turn Off All Test Mode
\r
1139 //if (IS_HARDWARE_TYPE_JAGUAR(pAdapter))
\r
1140 //PHY_SetBBReg(pAdapter, rSingleTone_ContTx_Jaguar, BIT18|BIT17|BIT16, OFDM_ALL_OFF);
\r
1142 PHY_SetBBReg(pAdapter, rOFDM1_LSTF, BIT30|BIT29|BIT28, OFDM_ALL_OFF);
\r
1143 //Set CCK Tx Test Rate
\r
1145 switch(pAdapter->mppriv.rateidx)
\r
1164 cckrate = pAdapter->mppriv.rateidx;
\r
1166 write_bbreg(pAdapter, rCCK0_System, bCCKTxRate, cckrate);
\r
1167 write_bbreg(pAdapter, rCCK0_System, bCCKBBMode, 0x2); //transmit mode
\r
1168 write_bbreg(pAdapter, rCCK0_System, bCCKScramble, bEnable); //turn on scramble setting
\r
1170 write_bbreg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000500);
\r
1171 write_bbreg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000500);
\r
1172 #ifdef CONFIG_RTL8192C
\r
1173 // Patch for CCK 11M waveform
\r
1174 if (cckrate == MPT_RATE_1M)
\r
1175 write_bbreg(pAdapter, 0xA71, BIT(6), bDisable);
\r
1177 write_bbreg(pAdapter, 0xA71, BIT(6), bEnable);
\r
1182 RT_TRACE(_module_mp_, _drv_info_,
\r
1183 ("SetCCKContinuousTx: test stop\n"));
\r
1185 write_bbreg(pAdapter, rCCK0_System, bCCKBBMode, 0x0); //normal mode
\r
1186 write_bbreg(pAdapter, rCCK0_System, bCCKScramble, bEnable); //turn on scramble setting
\r
1189 write_bbreg(pAdapter, rPMAC_Reset, bBBResetB, 0x0);
\r
1190 write_bbreg(pAdapter, rPMAC_Reset, bBBResetB, 0x1);
\r
1192 write_bbreg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000100);
\r
1193 write_bbreg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000100);
\r
1196 pAdapter->mppriv.MptCtx.bCckContTx = bStart;
\r
1197 pAdapter->mppriv.MptCtx.bOfdmContTx = _FALSE;
\r
1198 }/* mpt_StartCckContTx */
\r
1200 void Hal_SetOFDMContinuousTx(PADAPTER pAdapter, u8 bStart)
\r
1202 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
\r
1205 RT_TRACE(_module_mp_, _drv_info_, ("SetOFDMContinuousTx: test start\n"));
\r
1206 // 1. if OFDM block on?
\r
1207 if(!read_bbreg(pAdapter, rFPGA0_RFMOD, bOFDMEn))
\r
1208 write_bbreg(pAdapter, rFPGA0_RFMOD, bOFDMEn, bEnable);//set OFDM block on
\r
1211 // 2. set CCK test mode off, set to CCK normal mode
\r
1212 write_bbreg(pAdapter, rCCK0_System, bCCKBBMode, bDisable);
\r
1214 // 3. turn on scramble setting
\r
1215 write_bbreg(pAdapter, rCCK0_System, bCCKScramble, bEnable);
\r
1217 // 4. Turn On Continue Tx and turn off the other test modes.
\r
1218 write_bbreg(pAdapter, rOFDM1_LSTF, bOFDMContinueTx, bEnable);
\r
1219 write_bbreg(pAdapter, rOFDM1_LSTF, bOFDMSingleCarrier, bDisable);
\r
1220 write_bbreg(pAdapter, rOFDM1_LSTF, bOFDMSingleTone, bDisable);
\r
1222 write_bbreg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000500);
\r
1223 write_bbreg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000500);
\r
1226 RT_TRACE(_module_mp_,_drv_info_, ("SetOFDMContinuousTx: test stop\n"));
\r
1227 write_bbreg(pAdapter, rOFDM1_LSTF, bOFDMContinueTx, bDisable);
\r
1228 write_bbreg(pAdapter, rOFDM1_LSTF, bOFDMSingleCarrier, bDisable);
\r
1229 write_bbreg(pAdapter, rOFDM1_LSTF, bOFDMSingleTone, bDisable);
\r
1231 rtw_msleep_os(10);
\r
1233 write_bbreg(pAdapter, rPMAC_Reset, bBBResetB, 0x0);
\r
1234 write_bbreg(pAdapter, rPMAC_Reset, bBBResetB, 0x1);
\r
1236 write_bbreg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000100);
\r
1237 write_bbreg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000100);
\r
1240 pAdapter->mppriv.MptCtx.bCckContTx = _FALSE;
\r
1241 pAdapter->mppriv.MptCtx.bOfdmContTx = bStart;
\r
1242 }/* mpt_StartOfdmContTx */
\r
1244 void Hal_SetContinuousTx(PADAPTER pAdapter, u8 bStart)
\r
1247 // ADC turn off [bit24-21] adc port0 ~ port1
\r
1249 write_bbreg(pAdapter, rRx_Wait_CCCA, read_bbreg(pAdapter, rRx_Wait_CCCA) & 0xFE1FFFFF);
\r
1250 rtw_usleep_os(100);
\r
1253 RT_TRACE(_module_mp_, _drv_info_,
\r
1254 ("SetContinuousTx: rate:%d\n", pAdapter->mppriv.rateidx));
\r
1256 pAdapter->mppriv.MptCtx.bStartContTx = bStart;
\r
1258 //write_bbreg(pAdapter, rFixContTxRate, bFixContTxRate, bStart);
\r
1260 if (pAdapter->mppriv.rateidx <= MPT_RATE_11M)
\r
1262 Hal_SetCCKContinuousTx(pAdapter, bStart);
\r
1264 else if ((pAdapter->mppriv.rateidx >= MPT_RATE_6M) &&
\r
1265 (pAdapter->mppriv.rateidx <= MPT_RATE_MCS15))
\r
1267 Hal_SetOFDMContinuousTx(pAdapter, bStart);
\r
1270 // ADC turn on [bit24-21] adc port0 ~ port1
\r
1272 write_bbreg(pAdapter, rRx_Wait_CCCA, read_bbreg(pAdapter, rRx_Wait_CCCA) | 0x01E00000);
\r
1279 u8 MRateToHwRate8723B( u8 rate)
\r
1281 u8 ret = DESC8723B_RATE1M;
\r
1285 // CCK and OFDM non-HT rates
\r
1286 case MPT_RATE_1M: ret = DESC8723B_RATE1M; break;
\r
1287 case MPT_RATE_2M: ret = DESC8723B_RATE2M; break;
\r
1288 case MPT_RATE_55M: ret = DESC8723B_RATE5_5M; break;
\r
1289 case MPT_RATE_11M: ret = DESC8723B_RATE11M; break;
\r
1290 case MPT_RATE_6M: ret = DESC8723B_RATE6M; break;
\r
1291 case MPT_RATE_9M: ret = DESC8723B_RATE9M; break;
\r
1292 case MPT_RATE_12M: ret = DESC8723B_RATE12M; break;
\r
1293 case MPT_RATE_18M: ret = DESC8723B_RATE18M; break;
\r
1294 case MPT_RATE_24M: ret = DESC8723B_RATE24M; break;
\r
1295 case MPT_RATE_36M: ret = DESC8723B_RATE36M; break;
\r
1296 case MPT_RATE_48M: ret = DESC8723B_RATE48M; break;
\r
1297 case MPT_RATE_54M: ret = DESC8723B_RATE54M; break;
\r
1299 // HT rates since here
\r
1300 case MPT_RATE_MCS0: ret = DESC8723B_RATEMCS0; break;
\r
1301 case MPT_RATE_MCS1: ret = DESC8723B_RATEMCS1; break;
\r
1302 case MPT_RATE_MCS2: ret = DESC8723B_RATEMCS2; break;
\r
1303 case MPT_RATE_MCS3: ret = DESC8723B_RATEMCS3; break;
\r
1304 case MPT_RATE_MCS4: ret = DESC8723B_RATEMCS4; break;
\r
1305 case MPT_RATE_MCS5: ret = DESC8723B_RATEMCS5; break;
\r
1306 case MPT_RATE_MCS6: ret = DESC8723B_RATEMCS6; break;
\r
1307 case MPT_RATE_MCS7: ret = DESC8723B_RATEMCS7; break;
\r
1308 case MPT_RATE_MCS8: ret = DESC8723B_RATEMCS8; break;
\r
1309 case MPT_RATE_MCS9: ret = DESC8723B_RATEMCS9; break;
\r
1310 case MPT_RATE_MCS10: ret = DESC8723B_RATEMCS10; break;
\r
1311 case MPT_RATE_MCS11: ret = DESC8723B_RATEMCS11; break;
\r
1312 case MPT_RATE_MCS12: ret = DESC8723B_RATEMCS12; break;
\r
1313 case MPT_RATE_MCS13: ret = DESC8723B_RATEMCS13; break;
\r
1314 case MPT_RATE_MCS14: ret = DESC8723B_RATEMCS14; break;
\r
1315 case MPT_RATE_MCS15: ret = DESC8723B_RATEMCS15; break;
\r
1316 case MPT_RATE_VHT1SS_MCS0: ret = DESC8723B_RATEVHTSS1MCS0; break;
\r
1317 case MPT_RATE_VHT1SS_MCS1: ret = DESC8723B_RATEVHTSS1MCS1; break;
\r
1318 case MPT_RATE_VHT1SS_MCS2: ret = DESC8723B_RATEVHTSS1MCS2; break;
\r
1319 case MPT_RATE_VHT1SS_MCS3: ret = DESC8723B_RATEVHTSS1MCS3; break;
\r
1320 case MPT_RATE_VHT1SS_MCS4: ret = DESC8723B_RATEVHTSS1MCS4; break;
\r
1321 case MPT_RATE_VHT1SS_MCS5: ret = DESC8723B_RATEVHTSS1MCS5; break;
\r
1322 case MPT_RATE_VHT1SS_MCS6: ret = DESC8723B_RATEVHTSS1MCS6; break;
\r
1323 case MPT_RATE_VHT1SS_MCS7: ret = DESC8723B_RATEVHTSS1MCS7; break;
\r
1324 case MPT_RATE_VHT1SS_MCS8: ret = DESC8723B_RATEVHTSS1MCS8; break;
\r
1325 case MPT_RATE_VHT1SS_MCS9: ret = DESC8723B_RATEVHTSS1MCS9; break;
\r
1326 case MPT_RATE_VHT2SS_MCS0: ret = DESC8723B_RATEVHTSS2MCS0; break;
\r
1327 case MPT_RATE_VHT2SS_MCS1: ret = DESC8723B_RATEVHTSS2MCS1; break;
\r
1328 case MPT_RATE_VHT2SS_MCS2: ret = DESC8723B_RATEVHTSS2MCS2; break;
\r
1329 case MPT_RATE_VHT2SS_MCS3: ret = DESC8723B_RATEVHTSS2MCS3; break;
\r
1330 case MPT_RATE_VHT2SS_MCS4: ret = DESC8723B_RATEVHTSS2MCS4; break;
\r
1331 case MPT_RATE_VHT2SS_MCS5: ret = DESC8723B_RATEVHTSS2MCS5; break;
\r
1332 case MPT_RATE_VHT2SS_MCS6: ret = DESC8723B_RATEVHTSS2MCS6; break;
\r
1333 case MPT_RATE_VHT2SS_MCS7: ret = DESC8723B_RATEVHTSS2MCS7; break;
\r
1334 case MPT_RATE_VHT2SS_MCS8: ret = DESC8723B_RATEVHTSS2MCS8; break;
\r
1335 case MPT_RATE_VHT2SS_MCS9: ret = DESC8723B_RATEVHTSS2MCS9; break;
\r
1343 u8 HwRateToMRate8723B(u8 rate)
\r
1346 u8 ret_rate = MGN_1M;
\r
1352 case DESC8723B_RATE1M: ret_rate = MGN_1M; break;
\r
1353 case DESC8723B_RATE2M: ret_rate = MGN_2M; break;
\r
1354 case DESC8723B_RATE5_5M: ret_rate = MGN_5_5M; break;
\r
1355 case DESC8723B_RATE11M: ret_rate = MGN_11M; break;
\r
1356 case DESC8723B_RATE6M: ret_rate = MGN_6M; break;
\r
1357 case DESC8723B_RATE9M: ret_rate = MGN_9M; break;
\r
1358 case DESC8723B_RATE12M: ret_rate = MGN_12M; break;
\r
1359 case DESC8723B_RATE18M: ret_rate = MGN_18M; break;
\r
1360 case DESC8723B_RATE24M: ret_rate = MGN_24M; break;
\r
1361 case DESC8723B_RATE36M: ret_rate = MGN_36M; break;
\r
1362 case DESC8723B_RATE48M: ret_rate = MGN_48M; break;
\r
1363 case DESC8723B_RATE54M: ret_rate = MGN_54M; break;
\r
1364 case DESC8723B_RATEMCS0: ret_rate = MGN_MCS0; break;
\r
1365 case DESC8723B_RATEMCS1: ret_rate = MGN_MCS1; break;
\r
1366 case DESC8723B_RATEMCS2: ret_rate = MGN_MCS2; break;
\r
1367 case DESC8723B_RATEMCS3: ret_rate = MGN_MCS3; break;
\r
1368 case DESC8723B_RATEMCS4: ret_rate = MGN_MCS4; break;
\r
1369 case DESC8723B_RATEMCS5: ret_rate = MGN_MCS5; break;
\r
1370 case DESC8723B_RATEMCS6: ret_rate = MGN_MCS6; break;
\r
1371 case DESC8723B_RATEMCS7: ret_rate = MGN_MCS7; break;
\r
1372 case DESC8723B_RATEMCS8: ret_rate = MGN_MCS8; break;
\r
1373 case DESC8723B_RATEMCS9: ret_rate = MGN_MCS9; break;
\r
1374 case DESC8723B_RATEMCS10: ret_rate = MGN_MCS10; break;
\r
1375 case DESC8723B_RATEMCS11: ret_rate = MGN_MCS11; break;
\r
1376 case DESC8723B_RATEMCS12: ret_rate = MGN_MCS12; break;
\r
1377 case DESC8723B_RATEMCS13: ret_rate = MGN_MCS13; break;
\r
1378 case DESC8723B_RATEMCS14: ret_rate = MGN_MCS14; break;
\r
1379 case DESC8723B_RATEMCS15: ret_rate = MGN_MCS15; break;
\r
1380 case DESC8723B_RATEVHTSS1MCS0: ret_rate = MGN_VHT1SS_MCS0; break;
\r
1381 case DESC8723B_RATEVHTSS1MCS1: ret_rate = MGN_VHT1SS_MCS1; break;
\r
1382 case DESC8723B_RATEVHTSS1MCS2: ret_rate = MGN_VHT1SS_MCS2; break;
\r
1383 case DESC8723B_RATEVHTSS1MCS3: ret_rate = MGN_VHT1SS_MCS3; break;
\r
1384 case DESC8723B_RATEVHTSS1MCS4: ret_rate = MGN_VHT1SS_MCS4; break;
\r
1385 case DESC8723B_RATEVHTSS1MCS5: ret_rate = MGN_VHT1SS_MCS5; break;
\r
1386 case DESC8723B_RATEVHTSS1MCS6: ret_rate = MGN_VHT1SS_MCS6; break;
\r
1387 case DESC8723B_RATEVHTSS1MCS7: ret_rate = MGN_VHT1SS_MCS7; break;
\r
1388 case DESC8723B_RATEVHTSS1MCS8: ret_rate = MGN_VHT1SS_MCS8; break;
\r
1389 case DESC8723B_RATEVHTSS1MCS9: ret_rate = MGN_VHT1SS_MCS9; break;
\r
1390 case DESC8723B_RATEVHTSS2MCS0: ret_rate = MGN_VHT2SS_MCS0; break;
\r
1391 case DESC8723B_RATEVHTSS2MCS1: ret_rate = MGN_VHT2SS_MCS1; break;
\r
1392 case DESC8723B_RATEVHTSS2MCS2: ret_rate = MGN_VHT2SS_MCS2; break;
\r
1393 case DESC8723B_RATEVHTSS2MCS3: ret_rate = MGN_VHT2SS_MCS3; break;
\r
1394 case DESC8723B_RATEVHTSS2MCS4: ret_rate = MGN_VHT2SS_MCS4; break;
\r
1395 case DESC8723B_RATEVHTSS2MCS5: ret_rate = MGN_VHT2SS_MCS5; break;
\r
1396 case DESC8723B_RATEVHTSS2MCS6: ret_rate = MGN_VHT2SS_MCS6; break;
\r
1397 case DESC8723B_RATEVHTSS2MCS7: ret_rate = MGN_VHT2SS_MCS7; break;
\r
1398 case DESC8723B_RATEVHTSS2MCS8: ret_rate = MGN_VHT2SS_MCS8; break;
\r
1399 case DESC8723B_RATEVHTSS2MCS9: ret_rate = MGN_VHT2SS_MCS9; break;
\r
1402 DBG_8192C("HwRateToMRate8723B(): Non supported Rate [%x]!!!\n",rate );
\r
1408 #endif // CONFIG_MP_INCLUDE
\r