drivers/net/wireless/rockchip_wlan/rtl8723bs/hal/rtl8723b/sdio/sdio_halinit.c

   1 /******************************************************************************
   2  *
   3  * Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of version 2 of the GNU General Public License as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program; if not, write to the Free Software Foundation, Inc.,
  16  * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  17  *
  18  *
  19  ******************************************************************************/
  20 #define _SDIO_HALINIT_C_
  21
  22 #include <rtl8723b_hal.h>
  23
  24 #ifdef CONFIG_EFUSE_CONFIG_FILE
  25 #include <linux/fs.h>
  26 #include <asm/uaccess.h>
  27 #endif
  28 #include "hal_com_h2c.h"
  29 /*
  30  * Description:
  31  *      Call power on sequence to enable card
  32  *
  33  * Return:
  34  *      _SUCCESS        enable success
  35  *      _FAIL           enable fail
  36  */
  37 static u8 CardEnable(PADAPTER padapter)
  38 {
  39         u8 bMacPwrCtrlOn;
  40         u8 ret = _FAIL;
  41
  42
  43         rtw_hal_get_hwreg(padapter, HW_VAR_APFM_ON_MAC, &bMacPwrCtrlOn);
  44         if (bMacPwrCtrlOn == _FALSE)
  45         {
  46                 // RSV_CTRL 0x1C[7:0] = 0x00
  47                 // unlock ISO/CLK/Power control register
  48                 rtw_write8(padapter, REG_RSV_CTRL, 0x0);
  49
  50                 ret = HalPwrSeqCmdParsing(padapter, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, rtl8723B_card_enable_flow);
  51                 if (ret == _SUCCESS) {
  52                         u8 bMacPwrCtrlOn = _TRUE;
  53                         rtw_hal_set_hwreg(padapter, HW_VAR_APFM_ON_MAC, &bMacPwrCtrlOn);
  54                 }
  55         } else
  56                 ret = _SUCCESS;
  57
  58         return ret;
  59 }
  60
  61 /*
  62  * Description:
  63  *      Call this function to make sure power on successfully
  64  *
  65  * Return:
  66  *      _SUCCESS        enable success
  67  *      _FAIL   enable fail
  68  */
  69 static int PowerOnCheck(PADAPTER padapter)
  70 {
  71         u32     val_offset0, val_offset1, val_offset2, val_offset3;
  72         u32 val_mix = 0;
  73         u32 res = 0;
  74         u8      ret = _FAIL;
  75         int index = 0;
  76
  77         val_offset0 = rtw_read8(padapter, REG_CR);
  78         val_offset1 = rtw_read8(padapter, REG_CR+1);
  79         val_offset2 = rtw_read8(padapter, REG_CR+2);
  80         val_offset3 = rtw_read8(padapter, REG_CR+3);
  81
  82         if (val_offset0 == 0xEA || val_offset1 == 0xEA ||
  83                         val_offset2 == 0xEA || val_offset3 ==0xEA) {
  84                 DBG_871X("%s: power on fail, do Power on again\n", __func__);
  85                 return ret;
  86         }
  87
  88         val_mix = val_offset3 << 24 | val_mix;
  89         val_mix = val_offset2 << 16 | val_mix;
  90         val_mix = val_offset1 << 8 | val_mix;
  91         val_mix = val_offset0 | val_mix;
  92
  93         res = rtw_read32(padapter, REG_CR);
  94
  95         DBG_871X("%s: val_mix:0x%08x, res:0x%08x\n", __func__, val_mix, res);
  96
  97         while(index < 100) {
  98                 if (res == val_mix) {
  99                         DBG_871X("%s: 0x100 the result of cmd52 and cmd53 is the same.\n", __func__);
 100                         ret = _SUCCESS;
 101                         break;
 102                 } else {
 103                         DBG_871X("%s: 0x100 cmd52 and cmd53 is not the same(index:%d).\n", __func__, index);
 104                         res = rtw_read32(padapter, REG_CR);
 105                         index ++;
 106                         ret = _FAIL;
 107                 }
 108         }
 109
 110         if (ret) {
 111                 index = 0;
 112                 while(index < 100) {
 113                         rtw_write32(padapter, 0x1B8, 0x12345678);
 114                         res = rtw_read32(padapter, 0x1B8);
 115                         if (res == 0x12345678) {
 116                                 DBG_871X("%s: 0x1B8 test Pass.\n", __func__);
 117                                 ret = _SUCCESS;
 118                                 break;
 119                         } else {
 120                                 index ++;
 121                                 DBG_871X("%s: 0x1B8 test Fail(index: %d).\n", __func__, index);
 122                                 ret = _FAIL;
 123                         }
 124                 }
 125         } else {
 126                 DBG_871X("%s: fail at cmd52, cmd53.\n", __func__);
 127         }
 128
 129         if (ret == _FAIL) {
 130                 DBG_871X_LEVEL(_drv_err_, "Dump MAC Page0 register:\n");
 131                 /* Dump Page0 for check cystal*/
 132                 for (index = 0 ; index < 0xff ; index++) {
 133                         if(index%16==0)
 134                                 printk("0x%02x ",index);
 135
 136                         printk("%02x ", rtw_read8(padapter, index));
 137
 138                         if(index%16==15)
 139                                 printk("\n");
 140                         else if(index%8==7)
 141                                 printk("\t");
 142                 }
 143                 printk("\n");
 144         }
 145
 146         return ret;
 147 }
 148
 149 //static
 150 u8 _InitPowerOn_8723BS(PADAPTER padapter)
 151 {
 152         u8 value8;
 153         u16 value16;
 154         u32 value32;
 155         u8 ret;
 156         u8 pwron_chk_cnt=0;
 157 //      u8 bMacPwrCtrlOn;
 158
 159 _init_power_on:
 160
 161 #if 1
 162         // all of these MUST be configured before power on
 163 #ifdef CONFIG_XTAL_26M
 164         // Config PLL Reference CLK,
 165         // Change crystal to 26M, APLL_FREF_SEL = 4b'0101
 166         // APLL_FREF_SEL[0]=1b'1
 167         value8 = rtw_read8(padapter, REG_AFE_PLL_CTRL);
 168         value8 |= BIT(2);
 169         rtw_write8(padapter, REG_AFE_PLL_CTRL, value8);
 170         // APLL_FREF_SEL[2:1]=2b'10
 171         value8 = rtw_read8(padapter, REG_AFE_CTRL_4_8723B+1);
 172         value8 &= ~(BIT(1)|BIT(0));
 173         value8 |= BIT(1);
 174         rtw_write16(padapter, REG_AFE_CTRL_4_8723B+1, value8);
 175         // APLL_FREF_SEL[3]=1b'0
 176         value8 = rtw_read8(padapter, REG_AFE_CTRL_4_8723B);
 177         value8 &= ~BIT(7);
 178         rtw_write16(padapter, REG_AFE_CTRL_4_8723B, value8);
 179 #endif // CONFIG_XTAL_26M
 180
 181 #ifdef CONFIG_EXT_CLK
 182         // Use external crystal(XTAL)
 183         value8 = rtw_read8(padapter, REG_PAD_CTRL1_8723B+2);
 184         value8 |=  BIT(7);
 185         rtw_write8(padapter, REG_PAD_CTRL1_8723B+2, value8);
 186
 187         // CLK_REQ High active or Low Active
 188         // Request GPIO polarity:
 189         // 0: low active
 190         // 1: high active
 191         value8 = rtw_read8(padapter, REG_MULTI_FUNC_CTRL+1);
 192         value8 |= BIT(5);
 193         rtw_write8(padapter, REG_MULTI_FUNC_CTRL+1, value8);
 194 #endif // CONFIG_EXT_CLK
 195 #endif // all of these MUST be configured before power on
 196
 197         // only cmd52 can be used before power on(card enable)
 198         ret = CardEnable(padapter);
 199         if (ret == _FALSE) {
 200                 RT_TRACE(_module_hci_hal_init_c_, _drv_emerg_,
 201                                 ("%s: run power on flow fail\n", __FUNCTION__));
 202                 return _FAIL;
 203         }
 204
 205         // Radio-Off Pin Trigger
 206         value8 = rtw_read8(padapter, REG_GPIO_INTM+1);
 207         value8 |= BIT(1); // Enable falling edge triggering interrupt
 208         rtw_write8(padapter, REG_GPIO_INTM+1, value8);
 209         value8 = rtw_read8(padapter, REG_GPIO_IO_SEL_2+1);
 210         value8 |= BIT(1);
 211         rtw_write8(padapter, REG_GPIO_IO_SEL_2+1, value8);
 212
 213         // Enable power down and GPIO interrupt
 214         value16 = rtw_read16(padapter, REG_APS_FSMCO);
 215         value16 |= EnPDN; // Enable HW power down and RF on
 216         rtw_write16(padapter, REG_APS_FSMCO, value16);
 217
 218         // Enable CMD53 R/W Operation
 219 //      bMacPwrCtrlOn = _TRUE;
 220 //      rtw_hal_set_hwreg(padapter, HW_VAR_APFM_ON_MAC, &bMacPwrCtrlOn);
 221
 222         rtw_write8(padapter, REG_CR, 0x00);
 223         // Enable MAC DMA/WMAC/SCHEDULE/SEC block
 224         value16 = rtw_read16(padapter, REG_CR);
 225         value16 |= (HCI_TXDMA_EN | HCI_RXDMA_EN | TXDMA_EN | RXDMA_EN
 226                                 | PROTOCOL_EN | SCHEDULE_EN | ENSEC | CALTMR_EN);
 227         rtw_write16(padapter, REG_CR, value16);
 228
 229
 230         //PowerOnCheck()
 231         ret = PowerOnCheck(padapter);
 232         pwron_chk_cnt++;
 233         if (_FAIL == ret ) {
 234                 if (pwron_chk_cnt > 1) {
 235                         DBG_871X("Failed to init Power On!\n");
 236                         return _FAIL;
 237                 }
 238                 DBG_871X("Power on Fail! do it again\n");
 239                 goto _init_power_on;
 240         }
 241
 242 #ifdef CONFIG_BT_COEXIST
 243         rtw_btcoex_PowerOnSetting(padapter);
 244
 245         // external switch to S1
 246         // 0x38[11] = 0x1
 247         // 0x4c[23] = 0x1
 248         // 0x64[0] = 0
 249         value16 = rtw_read16(padapter, REG_PWR_DATA);
 250         // Switch the control of EESK, EECS to RFC for DPDT or Antenna switch
 251         value16 |= BIT(11); // BIT_EEPRPAD_RFE_CTRL_EN
 252         rtw_write16(padapter, REG_PWR_DATA, value16);
 253 //      DBG_8192C("%s: REG_PWR_DATA(0x%x)=0x%04X\n", __FUNCTION__, REG_PWR_DATA, rtw_read16(padapter, REG_PWR_DATA));
 254
 255         value32 = rtw_read32(padapter, REG_LEDCFG0);
 256         value32 |= BIT(23); // DPDT_SEL_EN, 1 for SW control
 257         rtw_write32(padapter, REG_LEDCFG0, value32);
 258 //      DBG_8192C("%s: REG_LEDCFG0(0x%x)=0x%08X\n", __FUNCTION__, REG_LEDCFG0, rtw_read32(padapter, REG_LEDCFG0));
 259
 260         value8 = rtw_read8(padapter, REG_PAD_CTRL1_8723B);
 261         value8 &= ~BIT(0); // BIT_SW_DPDT_SEL_DATA, DPDT_SEL default configuration
 262         rtw_write8(padapter, REG_PAD_CTRL1_8723B, value8);
 263 //      DBG_8192C("%s: REG_PAD_CTRL1(0x%x)=0x%02X\n", __FUNCTION__, REG_PAD_CTRL1_8723B, rtw_read8(padapter, REG_PAD_CTRL1_8723B));
 264 #endif // CONFIG_BT_COEXIST
 265
 266 #ifdef CONFIG_GPIO_WAKEUP
 267         rtw_clear_hostwakeupgpio(padapter);
 268 #endif // CONFIG_GPIO_WAKEUP
 269
 270         return _SUCCESS;
 271 }
 272
 273 //Tx Page FIFO threshold
 274 static void _init_available_page_threshold(PADAPTER padapter, u8 numHQ, u8 numNQ, u8 numLQ, u8 numPubQ)
 275 {
 276         u16     HQ_threshold, NQ_threshold, LQ_threshold;
 277
 278         HQ_threshold = (numPubQ + numHQ + 1) >> 1;
 279         HQ_threshold |= (HQ_threshold<<8);
 280
 281         NQ_threshold = (numPubQ + numNQ + 1) >> 1;
 282         NQ_threshold |= (NQ_threshold<<8);
 283
 284         LQ_threshold = (numPubQ + numLQ + 1) >> 1;
 285         LQ_threshold |= (LQ_threshold<<8);
 286
 287         rtw_write16(padapter, 0x218, HQ_threshold);
 288         rtw_write16(padapter, 0x21A, NQ_threshold);
 289         rtw_write16(padapter, 0x21C, LQ_threshold);
 290         DBG_8192C("%s(): Enable Tx FIFO Page Threshold H:0x%x,N:0x%x,L:0x%x\n", __FUNCTION__, HQ_threshold, NQ_threshold, LQ_threshold);
 291 }
 292
 293 static void _InitQueueReservedPage(PADAPTER padapter)
 294 {
 295         HAL_DATA_TYPE           *pHalData = GET_HAL_DATA(padapter);
 296         struct registry_priv    *pregistrypriv = &padapter->registrypriv;
 297         u32                     outEPNum        = (u32)pHalData->OutEpNumber;
 298         u32                     numHQ           = 0;
 299         u32                     numLQ           = 0;
 300         u32                     numNQ           = 0;
 301         u32                     numPubQ;
 302         u32                     value32;
 303         u8                      value8;
 304         BOOLEAN                 bWiFiConfig     = pregistrypriv->wifi_spec;
 305
 306         if (pHalData->OutEpQueueSel & TX_SELE_HQ)
 307         {
 308                 numHQ = bWiFiConfig ? WMM_NORMAL_PAGE_NUM_HPQ_8723B : NORMAL_PAGE_NUM_HPQ_8723B;
 309         }
 310
 311         if (pHalData->OutEpQueueSel & TX_SELE_LQ)
 312         {
 313                 numLQ = bWiFiConfig ? WMM_NORMAL_PAGE_NUM_LPQ_8723B : NORMAL_PAGE_NUM_LPQ_8723B;
 314         }
 315
 316         // NOTE: This step shall be proceed before writting REG_RQPN.
 317         if (pHalData->OutEpQueueSel & TX_SELE_NQ) {
 318                 numNQ = bWiFiConfig ? WMM_NORMAL_PAGE_NUM_NPQ_8723B : NORMAL_PAGE_NUM_NPQ_8723B;
 319         }
 320
 321         numPubQ = TX_TOTAL_PAGE_NUMBER_8723B - numHQ - numLQ - numNQ;
 322
 323         value8 = (u8)_NPQ(numNQ);
 324         rtw_write8(padapter, REG_RQPN_NPQ, value8);
 325
 326         // TX DMA
 327         value32 = _HPQ(numHQ) | _LPQ(numLQ) | _PUBQ(numPubQ) | LD_RQPN;
 328         rtw_write32(padapter, REG_RQPN, value32);
 329
 330         rtw_hal_set_sdio_tx_max_length(padapter, numHQ, numNQ, numLQ, numPubQ);
 331
 332 #ifdef CONFIG_SDIO_TX_ENABLE_AVAL_INT
 333         _init_available_page_threshold(padapter, numHQ, numNQ, numLQ, numPubQ);
 334 #endif
 335 }
 336
 337 static void _InitTxBufferBoundary(PADAPTER padapter)
 338 {
 339         struct registry_priv *pregistrypriv = &padapter->registrypriv;
 340 #ifdef CONFIG_CONCURRENT_MODE
 341         u8 val8;
 342 #endif // CONFIG_CONCURRENT_MODE
 343
 344         //u16   txdmactrl;
 345         u8      txpktbuf_bndy;
 346
 347         if (!pregistrypriv->wifi_spec) {
 348                 txpktbuf_bndy = TX_PAGE_BOUNDARY_8723B;
 349         } else {
 350                 //for WMM
 351                 txpktbuf_bndy = WMM_NORMAL_TX_PAGE_BOUNDARY_8723B;
 352         }
 353
 354         rtw_write8(padapter, REG_TXPKTBUF_BCNQ_BDNY_8723B, txpktbuf_bndy);
 355         rtw_write8(padapter, REG_TXPKTBUF_MGQ_BDNY_8723B, txpktbuf_bndy);
 356         rtw_write8(padapter, REG_TXPKTBUF_WMAC_LBK_BF_HD_8723B, txpktbuf_bndy);
 357         rtw_write8(padapter, REG_TRXFF_BNDY, txpktbuf_bndy);
 358         rtw_write8(padapter, REG_TDECTRL+1, txpktbuf_bndy);
 359
 360 #ifdef CONFIG_CONCURRENT_MODE
 361         val8 = txpktbuf_bndy + BCNQ_PAGE_NUM_8723B + WOWLAN_PAGE_NUM_8723B;
 362         rtw_write8(padapter, REG_BCNQ1_BDNY, val8);
 363         rtw_write8(padapter, REG_DWBCN1_CTRL_8723B+1, val8); // BCN1_HEAD
 364
 365         val8 = rtw_read8(padapter, REG_DWBCN1_CTRL_8723B+2);
 366         val8 |= BIT(1); // BIT1- BIT_SW_BCN_SEL_EN
 367         rtw_write8(padapter, REG_DWBCN1_CTRL_8723B+2, val8);
 368 #endif // CONFIG_CONCURRENT_MODE
 369 }
 370
 371 static VOID
 372 _InitNormalChipRegPriority(
 373         IN      PADAPTER        Adapter,
 374         IN      u16             beQ,
 375         IN      u16             bkQ,
 376         IN      u16             viQ,
 377         IN      u16             voQ,
 378         IN      u16             mgtQ,
 379         IN      u16             hiQ
 380         )
 381 {
 382         u16 value16             = (rtw_read16(Adapter, REG_TRXDMA_CTRL) & 0x7);
 383
 384         value16 |=      _TXDMA_BEQ_MAP(beQ)     | _TXDMA_BKQ_MAP(bkQ) |
 385                                 _TXDMA_VIQ_MAP(viQ)     | _TXDMA_VOQ_MAP(voQ) |
 386                                 _TXDMA_MGQ_MAP(mgtQ)| _TXDMA_HIQ_MAP(hiQ);
 387
 388         rtw_write16(Adapter, REG_TRXDMA_CTRL, value16);
 389 }
 390
 391 static VOID
 392 _InitNormalChipOneOutEpPriority(
 393         IN      PADAPTER Adapter
 394         )
 395 {
 396         HAL_DATA_TYPE   *pHalData       = GET_HAL_DATA(Adapter);
 397
 398         u16     value = 0;
 399         switch(pHalData->OutEpQueueSel)
 400         {
 401                 case TX_SELE_HQ:
 402                         value = QUEUE_HIGH;
 403                         break;
 404                 case TX_SELE_LQ:
 405                         value = QUEUE_LOW;
 406                         break;
 407                 case TX_SELE_NQ:
 408                         value = QUEUE_NORMAL;
 409                         break;
 410                 default:
 411                         //RT_ASSERT(FALSE,("Shall not reach here!\n"));
 412                         break;
 413         }
 414
 415         _InitNormalChipRegPriority(Adapter,
 416                                                                 value,
 417                                                                 value,
 418                                                                 value,
 419                                                                 value,
 420                                                                 value,
 421                                                                 value
 422                                                                 );
 423
 424 }
 425
 426 static VOID
 427 _InitNormalChipTwoOutEpPriority(
 428         IN      PADAPTER Adapter
 429         )
 430 {
 431         HAL_DATA_TYPE   *pHalData       = GET_HAL_DATA(Adapter);
 432         struct registry_priv *pregistrypriv = &Adapter->registrypriv;
 433         u16                     beQ,bkQ,viQ,voQ,mgtQ,hiQ;
 434
 435
 436         u16     valueHi = 0;
 437         u16     valueLow = 0;
 438
 439         switch(pHalData->OutEpQueueSel)
 440         {
 441                 case (TX_SELE_HQ | TX_SELE_LQ):
 442                         valueHi = QUEUE_HIGH;
 443                         valueLow = QUEUE_LOW;
 444                         break;
 445                 case (TX_SELE_NQ | TX_SELE_LQ):
 446                         valueHi = QUEUE_NORMAL;
 447                         valueLow = QUEUE_LOW;
 448                         break;
 449                 case (TX_SELE_HQ | TX_SELE_NQ):
 450                         valueHi = QUEUE_HIGH;
 451                         valueLow = QUEUE_NORMAL;
 452                         break;
 453                 default:
 454                         //RT_ASSERT(FALSE,("Shall not reach here!\n"));
 455                         break;
 456         }
 457
 458         if(!pregistrypriv->wifi_spec ){
 459                 beQ             = valueLow;
 460                 bkQ             = valueLow;
 461                 viQ             = valueHi;
 462                 voQ             = valueHi;
 463                 mgtQ    = valueHi;
 464                 hiQ             = valueHi;
 465         }
 466         else{//for WMM ,CONFIG_OUT_EP_WIFI_MODE
 467                 beQ             = valueLow;
 468                 bkQ             = valueHi;
 469                 viQ             = valueHi;
 470                 voQ             = valueLow;
 471                 mgtQ    = valueHi;
 472                 hiQ             = valueHi;
 473         }
 474
 475         _InitNormalChipRegPriority(Adapter,beQ,bkQ,viQ,voQ,mgtQ,hiQ);
 476
 477 }
 478
 479 static VOID
 480 _InitNormalChipThreeOutEpPriority(
 481         IN      PADAPTER padapter
 482         )
 483 {
 484         struct registry_priv *pregistrypriv = &padapter->registrypriv;
 485         u16                     beQ, bkQ, viQ, voQ, mgtQ, hiQ;
 486
 487         if (!pregistrypriv->wifi_spec){// typical setting
 488                 beQ             = QUEUE_LOW;
 489                 bkQ             = QUEUE_LOW;
 490                 viQ             = QUEUE_NORMAL;
 491                 voQ             = QUEUE_HIGH;
 492                 mgtQ    = QUEUE_HIGH;
 493                 hiQ             = QUEUE_HIGH;
 494         }
 495         else {// for WMM
 496                 beQ             = QUEUE_LOW;
 497                 bkQ             = QUEUE_NORMAL;
 498                 viQ             = QUEUE_NORMAL;
 499                 voQ             = QUEUE_HIGH;
 500                 mgtQ    = QUEUE_HIGH;
 501                 hiQ             = QUEUE_HIGH;
 502         }
 503         _InitNormalChipRegPriority(padapter,beQ,bkQ,viQ,voQ,mgtQ,hiQ);
 504 }
 505
 506 static VOID
 507 _InitNormalChipQueuePriority(
 508         IN      PADAPTER Adapter
 509         )
 510 {
 511         HAL_DATA_TYPE   *pHalData       = GET_HAL_DATA(Adapter);
 512
 513         switch(pHalData->OutEpNumber)
 514         {
 515                 case 1:
 516                         _InitNormalChipOneOutEpPriority(Adapter);
 517                         break;
 518                 case 2:
 519                         _InitNormalChipTwoOutEpPriority(Adapter);
 520                         break;
 521                 case 3:
 522                         _InitNormalChipThreeOutEpPriority(Adapter);
 523                         break;
 524                 default:
 525                         //RT_ASSERT(FALSE,("Shall not reach here!\n"));
 526                         break;
 527         }
 528
 529
 530 }
 531
 532 static void _InitQueuePriority(PADAPTER padapter)
 533 {
 534         _InitNormalChipQueuePriority(padapter);
 535 }
 536
 537 static void _InitPageBoundary(PADAPTER padapter)
 538 {
 539         // RX Page Boundary
 540         u16 rxff_bndy = RX_DMA_BOUNDARY_8723B;
 541
 542         rtw_write16(padapter, (REG_TRXFF_BNDY + 2), rxff_bndy);
 543 }
 544
 545 static void _InitTransferPageSize(PADAPTER padapter)
 546 {
 547         // Tx page size is always 128.
 548
 549         u8 value8;
 550         value8 = _PSRX(PBP_128) | _PSTX(PBP_128);
 551         rtw_write8(padapter, REG_PBP, value8);
 552 }
 553
 554 void _InitDriverInfoSize(PADAPTER padapter, u8 drvInfoSize)
 555 {
 556         rtw_write8(padapter, REG_RX_DRVINFO_SZ, drvInfoSize);
 557 }
 558
 559 void _InitNetworkType(PADAPTER padapter)
 560 {
 561         u32 value32;
 562
 563         value32 = rtw_read32(padapter, REG_CR);
 564
 565         // TODO: use the other function to set network type
 566 //      value32 = (value32 & ~MASK_NETTYPE) | _NETTYPE(NT_LINK_AD_HOC);
 567         value32 = (value32 & ~MASK_NETTYPE) | _NETTYPE(NT_LINK_AP);
 568
 569         rtw_write32(padapter, REG_CR, value32);
 570 }
 571
 572 void _InitWMACSetting(PADAPTER padapter)
 573 {
 574         PHAL_DATA_TYPE pHalData;
 575         u16 value16;
 576
 577
 578         pHalData = GET_HAL_DATA(padapter);
 579
 580         pHalData->ReceiveConfig = 0;
 581         pHalData->ReceiveConfig |= RCR_APM | RCR_AM | RCR_AB;
 582         pHalData->ReceiveConfig |= RCR_CBSSID_DATA | RCR_CBSSID_BCN | RCR_AMF;
 583         pHalData->ReceiveConfig |= RCR_HTC_LOC_CTRL;
 584         pHalData->ReceiveConfig |= RCR_APP_PHYST_RXFF | RCR_APP_ICV | RCR_APP_MIC;
 585 #ifdef CONFIG_MAC_LOOPBACK_DRIVER
 586         pHalData->ReceiveConfig |= RCR_AAP;
 587         pHalData->ReceiveConfig |= RCR_ADD3 | RCR_APWRMGT | RCR_ACRC32 | RCR_ADF;
 588 #endif
 589         rtw_write32(padapter, REG_RCR, pHalData->ReceiveConfig);
 590
 591         // Accept all multicast address
 592         rtw_write32(padapter, REG_MAR, 0xFFFFFFFF);
 593         rtw_write32(padapter, REG_MAR + 4, 0xFFFFFFFF);
 594
 595         // Accept all data frames
 596         value16 = 0xFFFF;
 597         rtw_write16(padapter, REG_RXFLTMAP2, value16);
 598
 599         // 2010.09.08 hpfan
 600         // Since ADF is removed from RCR, ps-poll will not be indicate to driver,
 601         // RxFilterMap should mask ps-poll to gurantee AP mode can rx ps-poll.
 602         value16 = 0x400;
 603         rtw_write16(padapter, REG_RXFLTMAP1, value16);
 604
 605         // Accept all management frames
 606         value16 = 0xFFFF;
 607         rtw_write16(padapter, REG_RXFLTMAP0, value16);
 608 }
 609
 610 void _InitAdaptiveCtrl(PADAPTER padapter)
 611 {
 612         u16     value16;
 613         u32     value32;
 614
 615         // Response Rate Set
 616         value32 = rtw_read32(padapter, REG_RRSR);
 617         value32 &= ~RATE_BITMAP_ALL;
 618         value32 |= RATE_RRSR_CCK_ONLY_1M;
 619         rtw_write32(padapter, REG_RRSR, value32);
 620
 621         // CF-END Threshold
 622         //m_spIoBase->rtw_write8(REG_CFEND_TH, 0x1);
 623
 624         // SIFS (used in NAV)
 625         value16 = _SPEC_SIFS_CCK(0x10) | _SPEC_SIFS_OFDM(0x10);
 626         rtw_write16(padapter, REG_SPEC_SIFS, value16);
 627
 628         // Retry Limit
 629         value16 = _LRL(0x30) | _SRL(0x30);
 630         rtw_write16(padapter, REG_RL, value16);
 631 }
 632
 633 void _InitEDCA(PADAPTER padapter)
 634 {
 635         // Set Spec SIFS (used in NAV)
 636         rtw_write16(padapter, REG_SPEC_SIFS, 0x100a);
 637         rtw_write16(padapter, REG_MAC_SPEC_SIFS, 0x100a);
 638
 639         // Set SIFS for CCK
 640         rtw_write16(padapter, REG_SIFS_CTX, 0x100a);
 641
 642         // Set SIFS for OFDM
 643         rtw_write16(padapter, REG_SIFS_TRX, 0x100a);
 644
 645         // TXOP
 646         rtw_write32(padapter, REG_EDCA_BE_PARAM, 0x005EA42B);
 647         rtw_write32(padapter, REG_EDCA_BK_PARAM, 0x0000A44F);
 648         rtw_write32(padapter, REG_EDCA_VI_PARAM, 0x005EA324);
 649         rtw_write32(padapter, REG_EDCA_VO_PARAM, 0x002FA226);
 650 }
 651
 652 void _InitRateFallback(PADAPTER padapter)
 653 {
 654         // Set Data Auto Rate Fallback Retry Count register.
 655         rtw_write32(padapter, REG_DARFRC, 0x00000000);
 656         rtw_write32(padapter, REG_DARFRC+4, 0x10080404);
 657         rtw_write32(padapter, REG_RARFRC, 0x04030201);
 658         rtw_write32(padapter, REG_RARFRC+4, 0x08070605);
 659
 660 }
 661
 662 void _InitRetryFunction(PADAPTER padapter)
 663 {
 664         u8      value8;
 665
 666         value8 = rtw_read8(padapter, REG_FWHW_TXQ_CTRL);
 667         value8 |= EN_AMPDU_RTY_NEW;
 668         rtw_write8(padapter, REG_FWHW_TXQ_CTRL, value8);
 669
 670         // Set ACK timeout
 671         rtw_write8(padapter, REG_ACKTO, 0x40);
 672 }
 673
 674 static void HalRxAggr8723BSdio(PADAPTER padapter)
 675 {
 676         struct registry_priv *pregistrypriv;
 677         u8      valueDMATimeout;
 678         u8      valueDMAPageCount;
 679
 680
 681         pregistrypriv = &padapter->registrypriv;
 682
 683         if (pregistrypriv->wifi_spec)
 684         {
 685                 // 2010.04.27 hpfan
 686                 // Adjust RxAggrTimeout to close to zero disable RxAggr, suggested by designer
 687                 // Timeout value is calculated by 34 / (2^n)
 688                 valueDMATimeout = 0x06;
 689                 valueDMAPageCount = 0x06;
 690         }
 691         else
 692         {
 693                 // 20130530, Isaac@SD1 suggest 3 kinds of parameter
 694 #if 1
 695                 // TX/RX Balance
 696                 valueDMATimeout = 0x06;
 697                 valueDMAPageCount = 0x06;
 698 #endif
 699 #if 0
 700                 // TX/RX Balance, but TCP ack may be late
 701                 valueDMATimeout = 0x16;
 702                 valueDMAPageCount = 0x06;
 703 #endif
 704 #if 0
 705                 // RX Best
 706                 valueDMATimeout = 0x16;
 707                 valueDMAPageCount = 0x08;
 708 #endif
 709         }
 710
 711 #ifdef CONFIG_DONT_CARE_TP
 712         valueDMATimeout = 0x0f;
 713         valueDMAPageCount = 0x04;  //RxAggUpthreshold = [4]*1K bytes+1.5k.  since RxAggUpthreshold+SzAmsdu(3839)<MaxRxBuffSize(8k), MaxvalueDMAPageCount=4.
 714 #endif
 715         rtw_write8(padapter, REG_RXDMA_AGG_PG_TH+1, valueDMATimeout);
 716         rtw_write8(padapter, REG_RXDMA_AGG_PG_TH, valueDMAPageCount);
 717 }
 718
 719 void sdio_AggSettingRxUpdate(PADAPTER padapter)
 720 {
 721         HAL_DATA_TYPE *pHalData;
 722         u8 valueDMA;
 723         u8 valueRxAggCtrl = 0;
 724         u8 aggBurstNum = 3;  //0:1, 1:2, 2:3, 3:4
 725         u8 aggBurstSize = 0;  //0:1K, 1:512Byte, 2:256Byte...
 726
 727         pHalData = GET_HAL_DATA(padapter);
 728
 729         valueDMA = rtw_read8(padapter, REG_TRXDMA_CTRL);
 730         valueDMA |= RXDMA_AGG_EN;
 731         rtw_write8(padapter, REG_TRXDMA_CTRL, valueDMA);
 732
 733         valueRxAggCtrl |= RXDMA_AGG_MODE_EN;
 734         valueRxAggCtrl |= ((aggBurstNum<<2) & 0x0C);
 735         valueRxAggCtrl |= ((aggBurstSize<<4) & 0x30);
 736         rtw_write8(padapter, REG_RXDMA_MODE_CTRL_8723B, valueRxAggCtrl);//RxAggLowThresh = 4*1K
 737 }
 738
 739 void _initSdioAggregationSetting(PADAPTER padapter)
 740 {
 741         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(padapter);
 742
 743         // Tx aggregation setting
 744 //      sdio_AggSettingTxUpdate(padapter);
 745
 746         // Rx aggregation setting
 747         HalRxAggr8723BSdio(padapter);
 748
 749         sdio_AggSettingRxUpdate(padapter);
 750
 751         // 201/12/10 MH Add for USB agg mode dynamic switch.
 752         pHalData->UsbRxHighSpeedMode = _FALSE;
 753 }
 754
 755 static void _RXAggrSwitch(PADAPTER padapter, u8 enable)
 756 {
 757         PHAL_DATA_TYPE pHalData;
 758         u8 valueDMA;
 759         u8 valueRxAggCtrl;
 760
 761
 762         pHalData = GET_HAL_DATA(padapter);
 763
 764         valueDMA = rtw_read8(padapter, REG_TRXDMA_CTRL);
 765         valueRxAggCtrl = rtw_read8(padapter, REG_RXDMA_MODE_CTRL_8723B);
 766
 767         if (_TRUE == enable)
 768         {
 769                 valueDMA |= RXDMA_AGG_EN;
 770                 valueRxAggCtrl |= RXDMA_AGG_MODE_EN;
 771         }
 772         else
 773         {
 774                 valueDMA &= ~RXDMA_AGG_EN;
 775                 valueRxAggCtrl &= ~RXDMA_AGG_MODE_EN;
 776         }
 777
 778         rtw_write8(padapter, REG_TRXDMA_CTRL, valueDMA);
 779         rtw_write8(padapter, REG_RXDMA_MODE_CTRL_8723B, valueRxAggCtrl);
 780 }
 781
 782 void _InitOperationMode(PADAPTER padapter)
 783 {
 784         PHAL_DATA_TYPE pHalData;
 785         struct mlme_ext_priv *pmlmeext;
 786         u8                              regBwOpMode = 0;
 787         u32                             regRATR = 0, regRRSR = 0;
 788         u8                              MinSpaceCfg = 0;
 789
 790
 791         pHalData = GET_HAL_DATA(padapter);
 792         pmlmeext = &padapter->mlmeextpriv;
 793
 794         //1 This part need to modified according to the rate set we filtered!!
 795         //
 796         // Set RRSR, RATR, and REG_BWOPMODE registers
 797         //
 798         switch(pmlmeext->cur_wireless_mode)
 799         {
 800                 case WIRELESS_MODE_B:
 801                         regBwOpMode = BW_OPMODE_20MHZ;
 802                         regRATR = RATE_ALL_CCK;
 803                         regRRSR = RATE_ALL_CCK;
 804                         break;
 805                 case WIRELESS_MODE_A:
 806 //                      RT_ASSERT(FALSE,("Error wireless a mode\n"));
 807 #if 0
 808                         regBwOpMode = BW_OPMODE_5G |BW_OPMODE_20MHZ;
 809                         regRATR = RATE_ALL_OFDM_AG;
 810                         regRRSR = RATE_ALL_OFDM_AG;
 811 #endif
 812                         break;
 813                 case WIRELESS_MODE_G:
 814                         regBwOpMode = BW_OPMODE_20MHZ;
 815                         regRATR = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
 816                         regRRSR = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
 817                         break;
 818                 case WIRELESS_MODE_AUTO:
 819 #if 0
 820                         if (padapter->bInHctTest)
 821                         {
 822                                 regBwOpMode = BW_OPMODE_20MHZ;
 823                                 regRATR = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
 824                                 regRRSR = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
 825                         }
 826                         else
 827 #endif
 828                         {
 829                                 regBwOpMode = BW_OPMODE_20MHZ;
 830                                 regRATR = RATE_ALL_CCK | RATE_ALL_OFDM_AG | RATE_ALL_OFDM_1SS | RATE_ALL_OFDM_2SS;
 831                                 regRRSR = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
 832                         }
 833                         break;
 834                 case WIRELESS_MODE_N_24G:
 835                         // It support CCK rate by default.
 836                         // CCK rate will be filtered out only when associated AP does not support it.
 837                         regBwOpMode = BW_OPMODE_20MHZ;
 838                         regRATR = RATE_ALL_CCK | RATE_ALL_OFDM_AG | RATE_ALL_OFDM_1SS | RATE_ALL_OFDM_2SS;
 839                         regRRSR = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
 840                         break;
 841                 case WIRELESS_MODE_N_5G:
 842 //                      RT_ASSERT(FALSE,("Error wireless mode"));
 843 #if 0
 844                         regBwOpMode = BW_OPMODE_5G;
 845                         regRATR = RATE_ALL_OFDM_AG | RATE_ALL_OFDM_1SS | RATE_ALL_OFDM_2SS;
 846                         regRRSR = RATE_ALL_OFDM_AG;
 847 #endif
 848                         break;
 849
 850                 default: //for MacOSX compiler warning.
 851                         break;
 852         }
 853
 854         rtw_write8(padapter, REG_BWOPMODE, regBwOpMode);
 855
 856 }
 857
 858 void _InitInterrupt(PADAPTER padapter)
 859 {
 860         // HISR - turn all off
 861         rtw_write32(padapter, REG_HISR, 0);
 862
 863         // HIMR - turn all off
 864         rtw_write32(padapter, REG_HIMR, 0);
 865
 866         //
 867         // Initialize and enable SDIO Host Interrupt.
 868         //
 869         InitInterrupt8723BSdio(padapter);
 870
 871         //
 872         // Initialize system Host Interrupt.
 873         //
 874         InitSysInterrupt8723BSdio(padapter);
 875 }
 876
 877 void _InitRDGSetting(PADAPTER padapter)
 878 {
 879         rtw_write8(padapter, REG_RD_CTRL, 0xFF);
 880         rtw_write16(padapter, REG_RD_NAV_NXT, 0x200);
 881         rtw_write8(padapter, REG_RD_RESP_PKT_TH, 0x05);
 882 }
 883
 884 #if (MP_DRIVER == 1  )
 885 static void _InitRxSetting(PADAPTER padapter)
 886 {
 887         rtw_write32(padapter, REG_MACID, 0x87654321);
 888         rtw_write32(padapter, 0x0700, 0x87654321);
 889 }
 890 #endif
 891
 892 static void _InitRFType(PADAPTER padapter)
 893 {
 894         struct registry_priv *pregpriv = &padapter->registrypriv;
 895         HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
 896         BOOLEAN is92CU = IS_92C_SERIAL(pHalData->VersionID);
 897
 898
 899 #if     DISABLE_BB_RF
 900         pHalData->rf_chip       = RF_PSEUDO_11N;
 901         return;
 902 #endif
 903
 904         pHalData->rf_chip       = RF_6052;
 905
 906         if (_FALSE == is92CU) {
 907                 pHalData->rf_type = RF_1T1R;
 908                 DBG_8192C("Set RF Chip ID to RF_6052 and RF type to 1T1R.\n");
 909                 return;
 910         }
 911
 912         // TODO: Consider that EEPROM set 92CU to 1T1R later.
 913         // Force to overwrite setting according to chip version. Ignore EEPROM setting.
 914         //pHalData->RF_Type = is92CU ? RF_2T2R : RF_1T1R;
 915         MSG_8192C("Set RF Chip ID to RF_6052 and RF type to %d.\n", pHalData->rf_type);
 916 }
 917
 918 // Set CCK and OFDM Block "ON"
 919 static void _BBTurnOnBlock(PADAPTER padapter)
 920 {
 921 #if (DISABLE_BB_RF)
 922         return;
 923 #endif
 924
 925         PHY_SetBBReg(padapter, rFPGA0_RFMOD, bCCKEn, 0x1);
 926         PHY_SetBBReg(padapter, rFPGA0_RFMOD, bOFDMEn, 0x1);
 927 }
 928
 929 static void _RfPowerSave(PADAPTER padapter)
 930 {
 931 //YJ,TODO
 932 }
 933
 934 static void _InitAntenna_Selection(PADAPTER padapter)
 935 {
 936         rtw_write8(padapter, REG_LEDCFG2, 0x82);
 937 }
 938
 939 static void _InitPABias(PADAPTER padapter)
 940 {
 941         HAL_DATA_TYPE           *pHalData = GET_HAL_DATA(padapter);
 942         u8                      pa_setting;
 943         BOOLEAN         is92C = IS_92C_SERIAL(pHalData->VersionID);
 944
 945         //FIXED PA current issue
 946         //efuse_one_byte_read(padapter, 0x1FA, &pa_setting);
 947         pa_setting = EFUSE_Read1Byte(padapter, 0x1FA);
 948
 949         //RT_TRACE(COMP_INIT, DBG_LOUD, ("_InitPABias 0x1FA 0x%x \n",pa_setting));
 950
 951         if(!(pa_setting & BIT0))
 952         {
 953                 PHY_SetRFReg(padapter, RF_PATH_A, 0x15, 0x0FFFFF, 0x0F406);
 954                 PHY_SetRFReg(padapter, RF_PATH_A, 0x15, 0x0FFFFF, 0x4F406);
 955                 PHY_SetRFReg(padapter, RF_PATH_A, 0x15, 0x0FFFFF, 0x8F406);
 956                 PHY_SetRFReg(padapter, RF_PATH_A, 0x15, 0x0FFFFF, 0xCF406);
 957                 //RT_TRACE(COMP_INIT, DBG_LOUD, ("PA BIAS path A\n"));
 958         }
 959
 960         if(!(pa_setting & BIT1) && is92C)
 961         {
 962                 PHY_SetRFReg(padapter, RF_PATH_B, 0x15, 0x0FFFFF, 0x0F406);
 963                 PHY_SetRFReg(padapter, RF_PATH_B, 0x15, 0x0FFFFF, 0x4F406);
 964                 PHY_SetRFReg(padapter, RF_PATH_B, 0x15, 0x0FFFFF, 0x8F406);
 965                 PHY_SetRFReg(padapter, RF_PATH_B, 0x15, 0x0FFFFF, 0xCF406);
 966                 //RT_TRACE(COMP_INIT, DBG_LOUD, ("PA BIAS path B\n"));
 967         }
 968
 969         if(!(pa_setting & BIT4))
 970         {
 971                 pa_setting = rtw_read8(padapter, 0x16);
 972                 pa_setting &= 0x0F;
 973                 rtw_write8(padapter, 0x16, pa_setting | 0x80);
 974                 rtw_write8(padapter, 0x16, pa_setting | 0x90);
 975         }
 976 }
 977
 978 //
 979 // 2010/08/09 MH Add for power down check.
 980 //
 981 static BOOLEAN HalDetectPwrDownMode(PADAPTER Adapter)
 982 {
 983         u8 tmpvalue;
 984         HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
 985         struct pwrctrl_priv *pwrctrlpriv = adapter_to_pwrctl(Adapter);
 986
 987
 988         EFUSE_ShadowRead(Adapter, 1, 0x7B/*EEPROM_RF_OPT3_92C*/, (u32 *)&tmpvalue);
 989
 990         // 2010/08/25 MH INF priority > PDN Efuse value.
 991         if(tmpvalue & BIT4 && pwrctrlpriv->reg_pdnmode)
 992         {
 993                 pHalData->pwrdown = _TRUE;
 994         }
 995         else
 996         {
 997                 pHalData->pwrdown = _FALSE;
 998         }
 999
1000         DBG_8192C("HalDetectPwrDownMode(): PDN=%d\n", pHalData->pwrdown);
1001
1002         return pHalData->pwrdown;
1003 }       // HalDetectPwrDownMode
1004
1005 static u32 rtl8723bs_hal_init(PADAPTER padapter)
1006 {
1007         s32 ret;
1008         PHAL_DATA_TYPE pHalData;
1009         struct pwrctrl_priv *pwrctrlpriv;
1010         struct registry_priv *pregistrypriv;
1011         struct sreset_priv *psrtpriv;
1012         struct dvobj_priv *psdpriv = padapter->dvobj;
1013         struct debug_priv *pdbgpriv = &psdpriv->drv_dbg;
1014         u8 is92C;
1015         rt_rf_power_state eRfPowerStateToSet;
1016         u32 NavUpper = WiFiNavUpperUs;
1017         u8 u1bTmp;
1018         u16 value16;
1019         u8 typeid;
1020         u32 u4Tmp;
1021
1022         pHalData = GET_HAL_DATA(padapter);
1023         psrtpriv = &pHalData->srestpriv;
1024         pwrctrlpriv = adapter_to_pwrctl(padapter);
1025         pregistrypriv = &padapter->registrypriv;
1026         is92C = IS_92C_SERIAL(pHalData->VersionID);
1027
1028 #ifdef CONFIG_SWLPS_IN_IPS
1029         if (adapter_to_pwrctl(padapter)->bips_processing == _TRUE)
1030         {
1031                 u8 val8, bMacPwrCtrlOn = _TRUE;
1032
1033                 DBG_871X("%s: run LPS flow in IPS\n", __FUNCTION__);
1034
1035                 //ser rpwm
1036                 val8 = rtw_read8(padapter, SDIO_LOCAL_BASE|SDIO_REG_HRPWM1);
1037                 val8 &= 0x80;
1038                 val8 += 0x80;
1039                 val8 |= BIT(6);
1040                 rtw_write8(padapter, SDIO_LOCAL_BASE|SDIO_REG_HRPWM1, val8);
1041
1042                 adapter_to_pwrctl(padapter)->tog = (val8 + 0x80) & 0x80;
1043
1044                 rtw_mdelay_os(5); //wait set rpwm already
1045
1046                 ret = HalPwrSeqCmdParsing(padapter, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, rtl8723B_leave_swlps_flow);
1047                 if (ret == _FALSE) {
1048                         DBG_8192C("%s: run LPS flow in IPS fail!\n", __FUNCTION__);
1049                         return _FAIL;
1050                 }
1051
1052                 rtw_hal_set_hwreg(padapter, HW_VAR_APFM_ON_MAC, &bMacPwrCtrlOn);
1053
1054                 pHalData->LastHMEBoxNum = 0;
1055
1056 #ifdef CONFIG_BT_COEXIST
1057                 rtw_btcoex_HAL_Initialize(padapter, _FALSE);
1058 #else
1059                 rtw_btcoex_HAL_Initialize(padapter, _TRUE);
1060 #endif // CONFIG_BT_COEXIST
1061
1062                 return _SUCCESS;
1063         }
1064 #elif defined(CONFIG_FWLPS_IN_IPS)
1065         if (adapter_to_pwrctl(padapter)->bips_processing == _TRUE && psrtpriv->silent_reset_inprogress == _FALSE
1066                 && adapter_to_pwrctl(padapter)->pre_ips_type == 0)
1067         {
1068                 u32 start_time;
1069                 u8 cpwm_orig, cpwm_now;
1070                 u8 val8, bMacPwrCtrlOn = _TRUE;
1071
1072                 DBG_871X("%s: Leaving IPS in FWLPS state\n", __FUNCTION__);
1073
1074                 //for polling cpwm
1075                 cpwm_orig = 0;
1076                 rtw_hal_get_hwreg(padapter, HW_VAR_CPWM, &cpwm_orig);
1077
1078                 //ser rpwm
1079                 val8 = rtw_read8(padapter, SDIO_LOCAL_BASE|SDIO_REG_HRPWM1);
1080                 val8 &= 0x80;
1081                 val8 += 0x80;
1082                 val8 |= BIT(6);
1083                 rtw_write8(padapter, SDIO_LOCAL_BASE|SDIO_REG_HRPWM1, val8);
1084                 DBG_871X("%s: write rpwm=%02x\n", __FUNCTION__, val8);
1085                 adapter_to_pwrctl(padapter)->tog = (val8 + 0x80) & 0x80;
1086
1087                 //do polling cpwm
1088                 start_time = rtw_get_current_time();
1089                 do {
1090
1091                         rtw_mdelay_os(1);
1092
1093                         rtw_hal_get_hwreg(padapter, HW_VAR_CPWM, &cpwm_now);
1094                         if ((cpwm_orig ^ cpwm_now) & 0x80)
1095                         {
1096 #ifdef DBG_CHECK_FW_PS_STATE
1097                                 DBG_871X("%s: polling cpwm ok when leaving IPS in FWLPS state, cpwm_orig=%02x, cpwm_now=%02x, 0x100=0x%x \n"
1098                                 , __FUNCTION__, cpwm_orig, cpwm_now, rtw_read8(padapter, REG_CR));
1099 #endif //DBG_CHECK_FW_PS_STATE
1100                                 break;
1101                         }
1102
1103                         if (rtw_get_passing_time_ms(start_time) > 100)
1104                         {
1105                                 DBG_871X("%s: polling cpwm timeout when leaving IPS in FWLPS state\n", __FUNCTION__);
1106                                 break;
1107                         }
1108                 } while (1);
1109
1110                 rtl8723b_set_FwPwrModeInIPS_cmd(padapter, 0);
1111
1112                 rtw_hal_set_hwreg(padapter, HW_VAR_APFM_ON_MAC, &bMacPwrCtrlOn);
1113
1114 #ifdef CONFIG_BT_COEXIST
1115                 rtw_btcoex_HAL_Initialize(padapter, _FALSE);
1116 #else
1117                 rtw_btcoex_HAL_Initialize(padapter, _TRUE);
1118 #endif // CONFIG_BT_COEXIST
1119
1120 #ifdef DBG_CHECK_FW_PS_STATE
1121                 if(rtw_fw_ps_state(padapter) == _FAIL)
1122                 {
1123                         DBG_871X("after hal init, fw ps state in 32k\n");
1124                         pdbgpriv->dbg_ips_drvopen_fail_cnt++;
1125                 }
1126 #endif //DBG_CHECK_FW_PS_STATE
1127                 return _SUCCESS;
1128         }
1129 #endif //CONFIG_SWLPS_IN_IPS
1130
1131 #ifdef CONFIG_WOWLAN
1132         if(rtw_read8(padapter, REG_MCUFWDL)&BIT7) {
1133                 u8 reg_val=0;
1134                 DBG_871X("+Reset Entry+\n");
1135                 rtw_write8(padapter, REG_MCUFWDL, 0x00);
1136                 _8051Reset8723(padapter);
1137                 //reset BB
1138                 reg_val = rtw_read8(padapter, REG_SYS_FUNC_EN);
1139                 reg_val &= ~(BIT(0) | BIT(1));
1140                 rtw_write8(padapter, REG_SYS_FUNC_EN, reg_val);
1141                 //reset RF
1142                 rtw_write8(padapter, REG_RF_CTRL, 0);
1143                 //reset TRX path
1144                 rtw_write16(padapter, REG_CR, 0);
1145                 //reset MAC, Digital Core
1146                 reg_val = rtw_read8(padapter, REG_SYS_FUNC_EN+1);
1147                 reg_val &= ~(BIT(4) | BIT(7));
1148                 rtw_write8(padapter, REG_SYS_FUNC_EN+1, reg_val);
1149                 reg_val = rtw_read8(padapter, REG_SYS_FUNC_EN+1);
1150                 reg_val |= BIT(4) | BIT(7);
1151                 rtw_write8(padapter, REG_SYS_FUNC_EN+1, reg_val);
1152                 DBG_871X("-Reset Entry-\n");
1153         }
1154 #endif //CONFIG_WOWLAN
1155         // Disable Interrupt first.
1156 //      rtw_hal_disable_interrupt(padapter);
1157
1158         if(rtw_read8(padapter, REG_MCUFWDL) == 0xc6) {
1159                 DBG_871X("FW exist before power on!!\n");
1160         } else {
1161                 DBG_871X("FW does not exist before power on!!\n");
1162         }
1163
1164         if(rtw_fw_ps_state(padapter) == _FAIL)
1165         {
1166                 DBG_871X("check fw_ps_state fail before PowerOn!\n");
1167                 pdbgpriv->dbg_ips_drvopen_fail_cnt++;
1168         }
1169
1170         ret = _InitPowerOn_8723BS(padapter);
1171         if (_FAIL == ret) {
1172                 RT_TRACE(_module_hci_hal_init_c_, _drv_err_, ("Failed to init Power On!\n"));
1173                 return _FAIL;
1174         }
1175         DBG_871X("Power on ok!\n");
1176
1177         if(rtw_fw_ps_state(padapter) == _FAIL)
1178         {
1179                 DBG_871X("check fw_ps_state fail after PowerOn!\n");
1180                 pdbgpriv->dbg_ips_drvopen_fail_cnt++;
1181         }
1182
1183
1184         rtw_write8(padapter, REG_EARLY_MODE_CONTROL, 0);
1185
1186 #if (MP_DRIVER == 1)
1187         if (padapter->registrypriv.mp_mode == 1)
1188         {
1189                 _InitRxSetting(padapter);
1190         }
1191
1192 #endif
1193
1194                 ret = rtl8723b_FirmwareDownload(padapter, _FALSE);
1195                 if (ret != _SUCCESS) {
1196                         RT_TRACE(_module_hci_hal_init_c_, _drv_err_, ("%s: Download Firmware failed!!\n", __FUNCTION__));
1197                         padapter->bFWReady = _FALSE;
1198                         pHalData->fw_ractrl = _FALSE;
1199                         return ret;
1200                 } else {
1201                         RT_TRACE(_module_hci_hal_init_c_, _drv_notice_, ("rtl8723bs_hal_init(): Download Firmware Success!!\n"));
1202                         padapter->bFWReady = _TRUE;
1203                         pHalData->fw_ractrl = _TRUE;
1204                 }
1205
1206         rtl8723b_InitializeFirmwareVars(padapter);
1207
1208 //      SIC_Init(padapter);
1209
1210         if (pwrctrlpriv->reg_rfoff == _TRUE) {
1211                 pwrctrlpriv->rf_pwrstate = rf_off;
1212         }
1213
1214         // 2010/08/09 MH We need to check if we need to turnon or off RF after detecting
1215         // HW GPIO pin. Before PHY_RFConfig8192C.
1216         HalDetectPwrDownMode(padapter);
1217
1218         // Set RF type for BB/RF configuration
1219         _InitRFType(padapter);
1220
1221         // Save target channel
1222         // <Roger_Notes> Current Channel will be updated again later.
1223         pHalData->CurrentChannel = 6;
1224
1225 #if (HAL_MAC_ENABLE == 1)
1226         ret = PHY_MACConfig8723B(padapter);
1227         if(ret != _SUCCESS){
1228                 RT_TRACE(_module_hci_hal_init_c_, _drv_info_, ("Initializepadapter8192CSdio(): Fail to configure MAC!!\n"));
1229                 return ret;
1230         }
1231 #endif
1232         //
1233         //d. Initialize BB related configurations.
1234         //
1235 #if (HAL_BB_ENABLE == 1)
1236         ret = PHY_BBConfig8723B(padapter);
1237         if(ret != _SUCCESS){
1238                 RT_TRACE(_module_hci_hal_init_c_, _drv_info_, ("Initializepadapter8192CSdio(): Fail to configure BB!!\n"));
1239                 return ret;
1240         }
1241 #endif
1242
1243         // If RF is on, we need to init RF. Otherwise, skip the procedure.
1244         // We need to follow SU method to change the RF cfg.txt. Default disable RF TX/RX mode.
1245         //if(pHalData->eRFPowerState == eRfOn)
1246         {
1247 #if (HAL_RF_ENABLE == 1)
1248                 ret = PHY_RFConfig8723B(padapter);
1249                 if(ret != _SUCCESS){
1250                         RT_TRACE(_module_hci_hal_init_c_, _drv_info_, ("Initializepadapter8192CSdio(): Fail to configure RF!!\n"));
1251                         return ret;
1252                 }
1253 #endif
1254         }
1255
1256         //
1257         // Joseph Note: Keep RfRegChnlVal for later use.
1258         //
1259         pHalData->RfRegChnlVal[0] = PHY_QueryRFReg(padapter, (RF_PATH)0, RF_CHNLBW, bRFRegOffsetMask);
1260         pHalData->RfRegChnlVal[1] = PHY_QueryRFReg(padapter, (RF_PATH)1, RF_CHNLBW, bRFRegOffsetMask);
1261
1262
1263         //if (!pHalData->bMACFuncEnable) {
1264                 _InitQueueReservedPage(padapter);
1265                 _InitTxBufferBoundary(padapter);
1266
1267                 // init LLT after tx buffer boundary is defined
1268                 ret = rtl8723b_InitLLTTable(padapter);
1269                 if (_SUCCESS != ret)
1270                 {
1271                         DBG_8192C("%s: Failed to init LLT Table!\n", __FUNCTION__);
1272                         return _FAIL;
1273                 }
1274         //}
1275         _InitQueuePriority(padapter);
1276         _InitPageBoundary(padapter);
1277         _InitTransferPageSize(padapter);
1278
1279         // Get Rx PHY status in order to report RSSI and others.
1280         _InitDriverInfoSize(padapter, DRVINFO_SZ);
1281         hal_init_macaddr(padapter);
1282         _InitNetworkType(padapter);
1283         _InitWMACSetting(padapter);
1284         _InitAdaptiveCtrl(padapter);
1285         _InitEDCA(padapter);
1286         //_InitRateFallback(padapter);
1287         _InitRetryFunction(padapter);
1288         _initSdioAggregationSetting(padapter);
1289         _InitOperationMode(padapter);
1290         rtl8723b_InitBeaconParameters(padapter);
1291         rtl8723b_InitBeaconMaxError(padapter, _TRUE);
1292         _InitInterrupt(padapter);
1293         _InitBurstPktLen_8723BS(padapter);
1294
1295         //YJ,TODO
1296         rtw_write8(padapter, REG_SECONDARY_CCA_CTRL_8723B, 0x3);        // CCA
1297         rtw_write8(padapter, 0x976, 0); // hpfan_todo: 2nd CCA related
1298
1299 #if defined(CONFIG_CONCURRENT_MODE) || defined(CONFIG_TX_MCAST2UNI)
1300
1301 #ifdef CONFIG_CHECK_AC_LIFETIME
1302         // Enable lifetime check for the four ACs
1303         rtw_write8(padapter, REG_LIFETIME_EN, 0x0F);
1304 #endif  // CONFIG_CHECK_AC_LIFETIME
1305
1306 #ifdef CONFIG_TX_MCAST2UNI
1307         rtw_write16(padapter, REG_PKT_VO_VI_LIFE_TIME, 0x0400); // unit: 256us. 256ms
1308         rtw_write16(padapter, REG_PKT_BE_BK_LIFE_TIME, 0x0400); // unit: 256us. 256ms
1309 #else   // CONFIG_TX_MCAST2UNI
1310         rtw_write16(padapter, REG_PKT_VO_VI_LIFE_TIME, 0x3000); // unit: 256us. 3s
1311         rtw_write16(padapter, REG_PKT_BE_BK_LIFE_TIME, 0x3000); // unit: 256us. 3s
1312 #endif  // CONFIG_TX_MCAST2UNI
1313 #endif  // CONFIG_CONCURRENT_MODE || CONFIG_TX_MCAST2UNI
1314
1315
1316         invalidate_cam_all(padapter);
1317
1318         rtw_hal_set_chnl_bw(padapter, padapter->registrypriv.channel,
1319                 CHANNEL_WIDTH_20, HAL_PRIME_CHNL_OFFSET_DONT_CARE, HAL_PRIME_CHNL_OFFSET_DONT_CARE);
1320
1321         // Record original value for template. This is arough data, we can only use the data
1322         // for power adjust. The value can not be adjustde according to different power!!!
1323 //      pHalData->OriginalCckTxPwrIdx = pHalData->CurrentCckTxPwrIdx;
1324 //      pHalData->OriginalOfdm24GTxPwrIdx = pHalData->CurrentOfdm24GTxPwrIdx;
1325
1326         rtl8723b_InitAntenna_Selection(padapter);
1327
1328         //
1329         // Disable BAR, suggested by Scott
1330         // 2010.04.09 add by hpfan
1331         //
1332         rtw_write32(padapter, REG_BAR_MODE_CTRL, 0x0201ffff);
1333
1334         // HW SEQ CTRL
1335         // set 0x0 to 0xFF by tynli. Default enable HW SEQ NUM.
1336         rtw_write8(padapter, REG_HWSEQ_CTRL, 0xFF);
1337
1338
1339 #ifdef CONFIG_MAC_LOOPBACK_DRIVER
1340         u1bTmp = rtw_read8(padapter, REG_SYS_FUNC_EN);
1341         u1bTmp &= ~(FEN_BBRSTB|FEN_BB_GLB_RSTn);
1342         rtw_write8(padapter, REG_SYS_FUNC_EN,u1bTmp);
1343
1344         rtw_write8(padapter, REG_RD_CTRL, 0x0F);
1345         rtw_write8(padapter, REG_RD_CTRL+1, 0xCF);
1346         rtw_write8(padapter, REG_TXPKTBUF_WMAC_LBK_BF_HD, 0x80);
1347         rtw_write32(padapter, REG_CR, 0x0b0202ff);
1348 #endif
1349
1350         //
1351         // Configure SDIO TxRx Control to enable Rx DMA timer masking.
1352         // 2010.02.24.
1353         //
1354         rtw_write32(padapter, SDIO_LOCAL_BASE|SDIO_REG_TX_CTRL, 0);
1355
1356         _RfPowerSave(padapter);
1357
1358
1359         rtl8723b_InitHalDm(padapter);
1360
1361         //DbgPrint("pHalData->DefaultTxPwrDbm = %d\n", pHalData->DefaultTxPwrDbm);
1362
1363 //      if(pHalData->SwBeaconType < HAL92CSDIO_DEFAULT_BEACON_TYPE) // The lowest Beacon Type that HW can support
1364 //              pHalData->SwBeaconType = HAL92CSDIO_DEFAULT_BEACON_TYPE;
1365
1366         //
1367         // Update current Tx FIFO page status.
1368         //
1369         HalQueryTxBufferStatus8723BSdio(padapter);
1370         HalQueryTxOQTBufferStatus8723BSdio(padapter);
1371         pHalData->SdioTxOQTMaxFreeSpace = pHalData->SdioTxOQTFreeSpace;
1372
1373         // Enable MACTXEN/MACRXEN block
1374         u1bTmp = rtw_read8(padapter, REG_CR);
1375         u1bTmp |= (MACTXEN | MACRXEN);
1376         rtw_write8(padapter, REG_CR, u1bTmp);
1377
1378         rtw_hal_set_hwreg(padapter, HW_VAR_NAV_UPPER, (u8*)&NavUpper);
1379
1380 #ifdef CONFIG_XMIT_ACK
1381         //ack for xmit mgmt frames.
1382         rtw_write32(padapter, REG_FWHW_TXQ_CTRL, rtw_read32(padapter, REG_FWHW_TXQ_CTRL)|BIT(12));
1383 #endif //CONFIG_XMIT_ACK
1384
1385 //      pHalData->PreRpwmVal = SdioLocalCmd52Read1Byte(padapter, SDIO_REG_HRPWM1) & 0x80;
1386
1387 #if (MP_DRIVER == 1)
1388         if (padapter->registrypriv.mp_mode == 1)
1389         {
1390                 padapter->mppriv.channel = pHalData->CurrentChannel;
1391                 MPT_InitializeAdapter(padapter, padapter->mppriv.channel);
1392         }
1393         else
1394 #endif //#if (MP_DRIVER == 1)
1395         {
1396                 pwrctrlpriv->rf_pwrstate = rf_on;
1397
1398                 if(pwrctrlpriv->rf_pwrstate == rf_on)
1399                 {
1400                         struct pwrctrl_priv *pwrpriv;
1401                         u32 start_time;
1402                         u8 restore_iqk_rst;
1403                         u8 b2Ant;
1404                         u8 h2cCmdBuf;
1405
1406                         pwrpriv = adapter_to_pwrctl(padapter);
1407
1408                         PHY_LCCalibrate_8723B(&pHalData->odmpriv);
1409
1410                         /* Inform WiFi FW that it is the beginning of IQK */
1411                         h2cCmdBuf = 1;
1412                         FillH2CCmd8723B(padapter, H2C_8723B_BT_WLAN_CALIBRATION, 1, &h2cCmdBuf);
1413
1414                         start_time = rtw_get_current_time();
1415                         do {
1416                                 if (rtw_read8(padapter, 0x1e7) & 0x01)
1417                                         break;
1418
1419                                 rtw_msleep_os(50);
1420                         } while (rtw_get_passing_time_ms(start_time) <= 400);
1421
1422 #ifdef CONFIG_BT_COEXIST
1423                         rtw_btcoex_IQKNotify(padapter, _TRUE);
1424 #endif
1425                         restore_iqk_rst = (pwrpriv->bips_processing==_TRUE)?_TRUE:_FALSE;
1426                         b2Ant = pHalData->EEPROMBluetoothAntNum==Ant_x2?_TRUE:_FALSE;
1427                         PHY_IQCalibrate_8723B(padapter, _FALSE, restore_iqk_rst, b2Ant, pHalData->ant_path);
1428                         pHalData->odmpriv.RFCalibrateInfo.bIQKInitialized = _TRUE;
1429 #ifdef CONFIG_BT_COEXIST
1430                         rtw_btcoex_IQKNotify(padapter, _FALSE);
1431 #endif
1432
1433                         /* Inform WiFi FW that it is the finish of IQK */
1434                         h2cCmdBuf = 0;
1435                         FillH2CCmd8723B(padapter, H2C_8723B_BT_WLAN_CALIBRATION, 1, &h2cCmdBuf);
1436
1437                         ODM_TXPowerTrackingCheck(&pHalData->odmpriv);
1438                 }
1439         }
1440
1441 #ifdef CONFIG_BT_COEXIST
1442         // Init BT hw config.
1443         rtw_btcoex_HAL_Initialize(padapter, _FALSE);
1444 #else
1445         rtw_btcoex_HAL_Initialize(padapter, _TRUE);
1446 #endif
1447
1448         RT_TRACE(_module_hci_hal_init_c_, _drv_info_, ("-%s\n", __FUNCTION__));
1449
1450         return _SUCCESS;
1451 }
1452
1453 //
1454 // Description:
1455 //      RTL8723e card disable power sequence v003 which suggested by Scott.
1456 //
1457 // First created by tynli. 2011.01.28.
1458 //
1459 static void CardDisableRTL8723BSdio(PADAPTER padapter)
1460 {
1461         u8              u1bTmp;
1462         u16             u2bTmp;
1463         u32             u4bTmp;
1464         u8              bMacPwrCtrlOn;
1465         u8              ret = _FAIL;
1466
1467         // Run LPS WL RFOFF flow
1468         ret = HalPwrSeqCmdParsing(padapter, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, rtl8723B_enter_lps_flow);
1469         if (ret == _FAIL) {
1470                 DBG_8192C(KERN_ERR "%s: run RF OFF flow fail!\n", __func__);
1471         }
1472
1473         //      ==== Reset digital sequence   ======
1474
1475         u1bTmp = rtw_read8(padapter, REG_MCUFWDL);
1476         if ((u1bTmp & RAM_DL_SEL) && padapter->bFWReady) //8051 RAM code
1477                 rtl8723b_FirmwareSelfReset(padapter);
1478
1479         // Reset MCU 0x2[10]=0. Suggested by Filen. 2011.01.26. by tynli.
1480         u1bTmp = rtw_read8(padapter, REG_SYS_FUNC_EN+1);
1481         u1bTmp &= ~BIT(2);      // 0x2[10], FEN_CPUEN
1482         rtw_write8(padapter, REG_SYS_FUNC_EN+1, u1bTmp);
1483
1484         // MCUFWDL 0x80[1:0]=0
1485         // reset MCU ready status
1486         rtw_write8(padapter, REG_MCUFWDL, 0);
1487
1488         // Reset MCU IO Wrapper, added by Roger, 2011.08.30
1489         u1bTmp = rtw_read8(padapter, REG_RSV_CTRL+1);
1490         u1bTmp &= ~BIT(0);
1491         rtw_write8(padapter, REG_RSV_CTRL+1, u1bTmp);
1492         u1bTmp = rtw_read8(padapter, REG_RSV_CTRL+1);
1493         u1bTmp |= BIT(0);
1494         rtw_write8(padapter, REG_RSV_CTRL+1, u1bTmp);
1495
1496         //      ==== Reset digital sequence end ======
1497
1498         bMacPwrCtrlOn = _FALSE; // Disable CMD53 R/W
1499         ret = _FALSE;
1500         rtw_hal_set_hwreg(padapter, HW_VAR_APFM_ON_MAC, &bMacPwrCtrlOn);
1501         ret = HalPwrSeqCmdParsing(padapter, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, rtl8723B_card_disable_flow);
1502         if (ret == _FALSE) {
1503                 DBG_8192C(KERN_ERR "%s: run CARD DISABLE flow fail!\n", __func__);
1504         }
1505 }
1506
1507 static u32 rtl8723bs_hal_deinit(PADAPTER padapter)
1508 {
1509         PHAL_DATA_TYPE pHalData = GET_HAL_DATA(padapter);
1510         struct sreset_priv *psrtpriv = &pHalData->srestpriv;
1511         struct dvobj_priv *psdpriv = padapter->dvobj;
1512         struct debug_priv *pdbgpriv = &psdpriv->drv_dbg;
1513
1514 #ifdef CONFIG_MP_INCLUDED
1515         if (padapter->registrypriv.mp_mode == 1)
1516                 MPT_DeInitAdapter(padapter);
1517 #endif
1518
1519         if (padapter->hw_init_completed == _TRUE)
1520         {
1521 #ifdef CONFIG_SWLPS_IN_IPS
1522                 if (adapter_to_pwrctl(padapter)->bips_processing == _TRUE)
1523                 {
1524                         u8      bMacPwrCtrlOn;
1525                         u8 ret =  _TRUE;
1526
1527                         DBG_871X("%s: run LPS flow in IPS\n", __FUNCTION__);
1528
1529                         rtw_write32(padapter, 0x130, 0x0);
1530                         rtw_write32(padapter, 0x138, 0x100);
1531                         rtw_write8(padapter, 0x13d, 0x1);
1532
1533
1534                         bMacPwrCtrlOn = _FALSE; // Disable CMD53 R/W
1535                         rtw_hal_set_hwreg(padapter, HW_VAR_APFM_ON_MAC, &bMacPwrCtrlOn);
1536
1537                         ret = HalPwrSeqCmdParsing(padapter, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, rtl8723B_enter_swlps_flow);
1538                         if (ret == _FALSE) {
1539                                 DBG_8192C("%s: run LPS flow in IPS fail!\n", __FUNCTION__);
1540                                 return _FAIL;
1541                         }
1542                 }
1543                 else
1544 #elif defined(CONFIG_FWLPS_IN_IPS)
1545                 if (adapter_to_pwrctl(padapter)->bips_processing == _TRUE && psrtpriv->silent_reset_inprogress == _FALSE)
1546                 {
1547                         if(padapter->netif_up == _TRUE)
1548                         {
1549                                 int cnt=0;
1550                                 u8 val8 = 0;
1551
1552                                 DBG_871X("%s: issue H2C to FW when entering IPS\n", __FUNCTION__);
1553
1554                                 rtl8723b_set_FwPwrModeInIPS_cmd(padapter, 0x3);
1555                                 //poll 0x1cc to make sure H2C command already finished by FW; MAC_0x1cc=0 means H2C done by FW.
1556                                 do{
1557                                         val8 = rtw_read8(padapter, REG_HMETFR);
1558                                         cnt++;
1559                                         DBG_871X("%s  polling REG_HMETFR=0x%x, cnt=%d \n", __FUNCTION__, val8, cnt);
1560                                         rtw_mdelay_os(10);
1561                                 }while(cnt<100 && (val8!=0));
1562                                 //H2C done, enter 32k
1563                                 if(val8 == 0)
1564                                 {
1565                                         //ser rpwm to enter 32k
1566                                         val8 = rtw_read8(padapter, SDIO_LOCAL_BASE|SDIO_REG_HRPWM1);
1567                                         val8 += 0x80;
1568                                         val8 |= BIT(0);
1569                                         rtw_write8(padapter, SDIO_LOCAL_BASE|SDIO_REG_HRPWM1, val8);
1570                                         DBG_871X("%s: write rpwm=%02x\n", __FUNCTION__, val8);
1571                                         adapter_to_pwrctl(padapter)->tog = (val8 + 0x80) & 0x80;
1572                                         cnt = val8 = 0;
1573                                         do{
1574                                                 val8 = rtw_read8(padapter, REG_CR);
1575                                                 cnt++;
1576                                                 DBG_871X("%s  polling 0x100=0x%x, cnt=%d \n", __FUNCTION__, val8, cnt);
1577                                                 rtw_mdelay_os(10);
1578                                         }while(cnt<100 && (val8!=0xEA));
1579 #ifdef DBG_CHECK_FW_PS_STATE
1580                                 if(val8 != 0xEA)
1581                                         DBG_871X("MAC_1C0=%08x, MAC_1C4=%08x, MAC_1C8=%08x, MAC_1CC=%08x\n", rtw_read32(padapter, 0x1c0), rtw_read32(padapter, 0x1c4)
1582                                         , rtw_read32(padapter, 0x1c8), rtw_read32(padapter, 0x1cc));
1583 #endif //DBG_CHECK_FW_PS_STATE
1584                                 }
1585                                 else
1586                                 {
1587                                         DBG_871X("MAC_1C0=%08x, MAC_1C4=%08x, MAC_1C8=%08x, MAC_1CC=%08x\n", rtw_read32(padapter, 0x1c0), rtw_read32(padapter, 0x1c4)
1588                                         , rtw_read32(padapter, 0x1c8), rtw_read32(padapter, 0x1cc));
1589                                 }
1590
1591                                 DBG_871X("polling done when entering IPS, check result : 0x100=0x%x, cnt=%d, MAC_1cc=0x%02x\n"
1592                                 , rtw_read8(padapter, REG_CR), cnt, rtw_read8(padapter, REG_HMETFR));
1593
1594                                 adapter_to_pwrctl(padapter)->pre_ips_type = 0;
1595
1596                         }
1597                         else
1598                         {
1599                                 pdbgpriv->dbg_carddisable_cnt++;
1600 #ifdef DBG_CHECK_FW_PS_STATE
1601                                 if(rtw_fw_ps_state(padapter) == _FAIL)
1602                                 {
1603                                         DBG_871X("card disable should leave 32k\n");
1604                                         pdbgpriv->dbg_carddisable_error_cnt++;
1605                                 }
1606 #endif //DBG_CHECK_FW_PS_STATE
1607                                 CardDisableRTL8723BSdio(padapter);
1608
1609                                 adapter_to_pwrctl(padapter)->pre_ips_type = 1;
1610                         }
1611
1612                 }
1613                 else
1614 #endif //CONFIG_SWLPS_IN_IPS
1615                 {
1616                         pdbgpriv->dbg_carddisable_cnt++;
1617 #ifdef DBG_CHECK_FW_PS_STATE
1618                         if(rtw_fw_ps_state(padapter) == _FAIL)
1619                         {
1620                                 DBG_871X("card disable should leave 32k\n");
1621                                 pdbgpriv->dbg_carddisable_error_cnt++;
1622                         }
1623 #endif //DBG_CHECK_FW_PS_STATE
1624                         CardDisableRTL8723BSdio(padapter);
1625                 }
1626         }
1627         else
1628         {
1629                 pdbgpriv->dbg_deinit_fail_cnt++;
1630         }
1631
1632         return _SUCCESS;
1633 }
1634
1635 static u32 rtl8723bs_inirp_init(PADAPTER padapter)
1636 {
1637         u32 status;
1638
1639 _func_enter_;
1640
1641         status = _SUCCESS;
1642
1643 _func_exit_;
1644
1645         return status;
1646 }
1647
1648 static u32 rtl8723bs_inirp_deinit(PADAPTER padapter)
1649 {
1650         RT_TRACE(_module_hci_hal_init_c_,_drv_info_,("+rtl8723bs_inirp_deinit\n"));
1651
1652         RT_TRACE(_module_hci_hal_init_c_,_drv_info_,("-rtl8723bs_inirp_deinit\n"));
1653
1654         return _SUCCESS;
1655 }
1656
1657 static void rtl8723bs_init_default_value(PADAPTER padapter)
1658 {
1659         PHAL_DATA_TYPE pHalData;
1660
1661
1662         pHalData = GET_HAL_DATA(padapter);
1663
1664         rtl8723b_init_default_value(padapter);
1665
1666         // interface related variable
1667         pHalData->SdioRxFIFOCnt = 0;
1668 }
1669
1670 static void rtl8723bs_interface_configure(PADAPTER padapter)
1671 {
1672         HAL_DATA_TYPE           *pHalData = GET_HAL_DATA(padapter);
1673         struct dvobj_priv               *pdvobjpriv = adapter_to_dvobj(padapter);
1674         struct registry_priv    *pregistrypriv = &padapter->registrypriv;
1675         BOOLEAN         bWiFiConfig     = pregistrypriv->wifi_spec;
1676
1677
1678         pdvobjpriv->RtOutPipe[0] = WLAN_TX_HIQ_DEVICE_ID;
1679         pdvobjpriv->RtOutPipe[1] = WLAN_TX_MIQ_DEVICE_ID;
1680         pdvobjpriv->RtOutPipe[2] = WLAN_TX_LOQ_DEVICE_ID;
1681
1682         if (bWiFiConfig)
1683                 pHalData->OutEpNumber = 2;
1684         else
1685                 pHalData->OutEpNumber = SDIO_MAX_TX_QUEUE;
1686
1687         switch(pHalData->OutEpNumber){
1688                 case 3:
1689                         pHalData->OutEpQueueSel=TX_SELE_HQ| TX_SELE_LQ|TX_SELE_NQ;
1690                         break;
1691                 case 2:
1692                         pHalData->OutEpQueueSel=TX_SELE_HQ| TX_SELE_NQ;
1693                         break;
1694                 case 1:
1695                         pHalData->OutEpQueueSel=TX_SELE_HQ;
1696                         break;
1697                 default:
1698                         break;
1699         }
1700
1701         Hal_MappingOutPipe(padapter, pHalData->OutEpNumber);
1702 }
1703
1704 //
1705 //      Description:
1706 //              We should set Efuse cell selection to WiFi cell in default.
1707 //
1708 //      Assumption:
1709 //              PASSIVE_LEVEL
1710 //
1711 //      Added by Roger, 2010.11.23.
1712 //
1713 static void
1714 _EfuseCellSel(
1715         IN      PADAPTER        padapter
1716         )
1717 {
1718         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(padapter);
1719
1720         u32                     value32;
1721
1722         //if(INCLUDE_MULTI_FUNC_BT(padapter))
1723         {
1724                 value32 = rtw_read32(padapter, EFUSE_TEST);
1725                 value32 = (value32 & ~EFUSE_SEL_MASK) | EFUSE_SEL(EFUSE_WIFI_SEL_0);
1726                 rtw_write32(padapter, EFUSE_TEST, value32);
1727         }
1728 }
1729
1730 static VOID
1731 _ReadRFType(
1732         IN      PADAPTER        Adapter
1733         )
1734 {
1735         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(Adapter);
1736
1737 #if DISABLE_BB_RF
1738         pHalData->rf_chip = RF_PSEUDO_11N;
1739 #else
1740         pHalData->rf_chip = RF_6052;
1741 #endif
1742 }
1743
1744
1745 static void
1746 Hal_EfuseParseMACAddr_8723BS(
1747         IN      PADAPTER                padapter,
1748         IN      u8*                     hwinfo,
1749         IN      BOOLEAN                 AutoLoadFail
1750         )
1751 {
1752         u16                     i, usValue;
1753         u8                      sMacAddr[6] = {0x00, 0xE0, 0x4C, 0xb7, 0x23, 0x00};
1754         EEPROM_EFUSE_PRIV *pEEPROM = GET_EEPROM_EFUSE_PRIV(padapter);
1755
1756         if (AutoLoadFail)
1757         {
1758 //              sMacAddr[5] = (u1Byte)GetRandomNumber(1, 254);
1759                 for (i=0; i<6; i++)
1760                         pEEPROM->mac_addr[i] = sMacAddr[i];
1761         }
1762         else
1763         {
1764                 //Read Permanent MAC address
1765 #if 1
1766                 _rtw_memcpy(pEEPROM->mac_addr, &hwinfo[EEPROM_MAC_ADDR_8723BS], ETH_ALEN);
1767 #else
1768                 for(i=0; i<6; i+=2)
1769                 {
1770                         usValue = *(u16*)&hwinfo[EEPROM_MAC_ADDR_8723S+i];
1771                         *((u16*)(&pEEPROM->mac_addr[i])) = usValue;
1772                 }
1773 #endif
1774         }
1775 //      NicIFSetMacAddress(pAdapter, pAdapter->PermanentAddress);
1776
1777         RT_TRACE(_module_hci_hal_init_c_, _drv_notice_,
1778                  ("Hal_EfuseParseMACAddr_8723BS: Permanent Address = %02x-%02x-%02x-%02x-%02x-%02x\n",
1779                   pEEPROM->mac_addr[0], pEEPROM->mac_addr[1],
1780                   pEEPROM->mac_addr[2], pEEPROM->mac_addr[3],
1781                   pEEPROM->mac_addr[4], pEEPROM->mac_addr[5]));
1782 }
1783
1784 static void
1785 Hal_EfuseParseBoardType_8723BS(
1786         IN      PADAPTER                pAdapter,
1787         IN      u8*                     hwinfo,
1788         IN      BOOLEAN                 AutoLoadFail
1789         )
1790 {
1791         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(pAdapter);
1792
1793         if (!AutoLoadFail)
1794         {
1795                 pHalData->BoardType = (hwinfo[EEPROM_RF_BOARD_OPTION_8723B] & 0xE0) >> 5;
1796                 if(pHalData->BoardType == 0xFF)
1797                         pHalData->BoardType = (EEPROM_DEFAULT_BOARD_OPTION&0xE0)>>5;
1798         }
1799         else
1800                 pHalData->BoardType = 0;
1801         RT_TRACE(_module_hci_hal_init_c_, _drv_info_, ("Board Type: 0x%2x\n", pHalData->BoardType));
1802 }
1803
1804 #ifdef CONFIG_EFUSE_CONFIG_FILE
1805 static void
1806 Hal_ReadMACAddrFromFile_8723BS(
1807         PADAPTER                padapter
1808         )
1809 {
1810         u32 i;
1811         struct file *fp;
1812         mm_segment_t fs;
1813         u8 source_addr[18];
1814         loff_t pos = 0;
1815         u32     curtime = rtw_get_current_time();
1816         EEPROM_EFUSE_PRIV *pEEPROM = GET_EEPROM_EFUSE_PRIV(padapter);
1817         u8 *head, *end;
1818
1819         u8 null_mac_addr[ETH_ALEN] = {0, 0, 0,0, 0, 0};
1820         u8 multi_mac_addr[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
1821
1822         _rtw_memset(source_addr, 0, 18);
1823         _rtw_memset(pEEPROM->mac_addr, 0, ETH_ALEN);
1824
1825         fp = filp_open("/data/wifimac.txt", O_RDWR,  0644);
1826         if (IS_ERR(fp)) {
1827                 RT_TRACE(_module_hci_hal_init_c_, _drv_err_, ("Error, wifi mac address file doesn't exist.\n"));
1828         } else {
1829                 fs = get_fs();
1830                 set_fs(KERNEL_DS);
1831
1832                 DBG_871X("wifi mac address:\n");
1833                 vfs_read(fp, source_addr, 18, &pos);
1834                 source_addr[17] = ':';
1835
1836                 head = end = source_addr;
1837                 for (i=0; i<ETH_ALEN; i++) {
1838                         while (end && (*end != ':') )
1839                                 end++;
1840
1841                         if (end && (*end == ':') )
1842                                 *end = '\0';
1843
1844                         pEEPROM->mac_addr[i] = simple_strtoul(head, NULL, 16 );
1845
1846                         if (end) {
1847                                 end++;
1848                                 head = end;
1849                         }
1850                         DBG_871X("%02x \n", pEEPROM->mac_addr[i]);
1851                 }
1852                 DBG_871X("\n");
1853                 set_fs(fs);
1854
1855                 filp_close(fp, NULL);
1856         }
1857
1858         if ( (_rtw_memcmp(pEEPROM->mac_addr, null_mac_addr, ETH_ALEN)) ||
1859                 (_rtw_memcmp(pEEPROM->mac_addr, multi_mac_addr, ETH_ALEN)) ) {
1860                 pEEPROM->mac_addr[0] = 0x00;
1861                 pEEPROM->mac_addr[1] = 0xe0;
1862                 pEEPROM->mac_addr[2] = 0x4c;
1863                 pEEPROM->mac_addr[3] = (u8)(curtime & 0xff) ;
1864                 pEEPROM->mac_addr[4] = (u8)((curtime>>8) & 0xff) ;
1865                 pEEPROM->mac_addr[5] = (u8)((curtime>>16) & 0xff) ;
1866         }
1867
1868         RT_TRACE(_module_hci_hal_init_c_, _drv_notice_,
1869                  ("Hal_ReadMACAddrFromFile_8723BS: Permanent Address = %02x-%02x-%02x-%02x-%02x-%02x\n",
1870                   pEEPROM->mac_addr[0], pEEPROM->mac_addr[1],
1871                   pEEPROM->mac_addr[2], pEEPROM->mac_addr[3],
1872                   pEEPROM->mac_addr[4], pEEPROM->mac_addr[5]));
1873 }
1874 #endif
1875
1876 static VOID
1877 _ReadEfuseInfo8723BS(
1878         IN PADAPTER                     padapter
1879         )
1880 {
1881         EEPROM_EFUSE_PRIV *pEEPROM = GET_EEPROM_EFUSE_PRIV(padapter);
1882         u8*                     hwinfo = NULL;
1883 #ifdef CONFIG_EFUSE_CONFIG_FILE
1884         struct file *fp;
1885 #endif //CONFIG_EFUSE_CONFIG_FILE
1886
1887         RT_TRACE(_module_hci_hal_init_c_, _drv_info_, ("====>_ReadEfuseInfo8723BS()\n"));
1888
1889         //
1890         // This part read and parse the eeprom/efuse content
1891         //
1892
1893         if (sizeof(pEEPROM->efuse_eeprom_data) < HWSET_MAX_SIZE_8723B)
1894                 DBG_871X("[WARNING] size of efuse_eeprom_data is less than HWSET_MAX_SIZE_8723B!\n");
1895
1896         hwinfo = pEEPROM->efuse_eeprom_data;
1897
1898         Hal_InitPGData(padapter, hwinfo);
1899
1900 #ifdef CONFIG_EFUSE_CONFIG_FILE
1901         if (check_phy_efuse_tx_power_info_valid(padapter) == _FALSE) {
1902                 fp = filp_open(EFUSE_MAP_PATH, O_RDONLY, 0);
1903                 if (fp == NULL || IS_ERR(fp)) {
1904                         DBG_871X("[WARNING] invalid phy efuse and no efuse file, use driver default!!\n");
1905                 } else {
1906                         Hal_readPGDataFromConfigFile(padapter, fp);
1907                         filp_close(fp, NULL);
1908                 }
1909         }
1910 #endif //CONFIG_EFUSE_CONFIG_FILE
1911
1912         Hal_EfuseParseIDCode(padapter, hwinfo);
1913         Hal_EfuseParseEEPROMVer_8723B(padapter, hwinfo, pEEPROM->bautoload_fail_flag);
1914
1915 #ifdef CONFIG_EFUSE_CONFIG_FILE
1916         if (check_phy_efuse_macaddr_info_valid(padapter) == _TRUE) {
1917                 DBG_871X("using phy efuse mac\n");
1918                 Hal_GetPhyEfuseMACAddr(padapter, pEEPROM->mac_addr);
1919         } else {
1920                 fp = filp_open(WIFIMAC_PATH, O_RDONLY, 0);
1921                 if (fp == NULL || IS_ERR(fp)) {
1922                         DBG_871X("wifimac does not exist!!\n");
1923                         Hal_GetPhyEfuseMACAddr(padapter, pEEPROM->mac_addr);
1924                 } else {
1925                         Hal_ReadMACAddrFromFile(padapter, fp);
1926                         filp_close(fp, NULL);
1927                 }
1928         }
1929 #else //CONFIG_EFUSE_CONFIG_FILE
1930         Hal_EfuseParseMACAddr_8723BS(padapter, hwinfo, pEEPROM->bautoload_fail_flag);
1931 #endif
1932
1933         Hal_EfuseParseTxPowerInfo_8723B(padapter, hwinfo, pEEPROM->bautoload_fail_flag);
1934         Hal_EfuseParseBoardType_8723BS(padapter, hwinfo, pEEPROM->bautoload_fail_flag);
1935
1936         //
1937         // Read Bluetooth co-exist and initialize
1938         //
1939         Hal_EfuseParseBTCoexistInfo_8723B(padapter, hwinfo, pEEPROM->bautoload_fail_flag);
1940         Hal_EfuseParseChnlPlan_8723B(padapter, hwinfo, pEEPROM->bautoload_fail_flag);
1941         Hal_EfuseParseXtal_8723B(padapter, hwinfo, pEEPROM->bautoload_fail_flag);
1942         Hal_EfuseParsePackageType_8723B(padapter, hwinfo, pEEPROM->bautoload_fail_flag);
1943         Hal_EfuseParseThermalMeter_8723B(padapter, hwinfo, pEEPROM->bautoload_fail_flag);
1944         Hal_EfuseParseAntennaDiversity_8723B(padapter, hwinfo, pEEPROM->bautoload_fail_flag);
1945         Hal_EfuseParseCustomerID_8723B(padapter, hwinfo, pEEPROM->bautoload_fail_flag);
1946
1947         Hal_EfuseParseVoltage_8723B(padapter, hwinfo, pEEPROM->bautoload_fail_flag);
1948
1949 #ifdef CONFIG_WOWLAN
1950         Hal_DetectWoWMode(padapter);
1951 #endif
1952
1953 #ifdef CONFIG_RF_GAIN_OFFSET
1954                 Hal_ReadRFGainOffset(padapter, hwinfo, pEEPROM->bautoload_fail_flag);
1955 #endif  //CONFIG_RF_GAIN_OFFSET
1956
1957         RT_TRACE(_module_hci_hal_init_c_, _drv_info_, ("<==== _ReadEfuseInfo8723BS()\n"));
1958 }
1959
1960 static void _ReadPROMContent(
1961         IN PADAPTER             padapter
1962         )
1963 {
1964         EEPROM_EFUSE_PRIV *pEEPROM = GET_EEPROM_EFUSE_PRIV(padapter);
1965         u8                      eeValue;
1966
1967         eeValue = rtw_read8(padapter, REG_9346CR);
1968         // To check system boot selection.
1969         pEEPROM->EepromOrEfuse = (eeValue & BOOT_FROM_EEPROM) ? _TRUE : _FALSE;
1970         pEEPROM->bautoload_fail_flag = (eeValue & EEPROM_EN) ? _FALSE : _TRUE;
1971
1972         RT_TRACE(_module_hci_hal_init_c_, _drv_info_,
1973                  ("%s: 9346CR=0x%02X, Boot from %s, Autoload %s\n",
1974                   __FUNCTION__, eeValue,
1975                   (pEEPROM->EepromOrEfuse ? "EEPROM" : "EFUSE"),
1976                   (pEEPROM->bautoload_fail_flag ? "Fail" : "OK")));
1977
1978 //      pHalData->EEType = IS_BOOT_FROM_EEPROM(Adapter) ? EEPROM_93C46 : EEPROM_BOOT_EFUSE;
1979
1980         _ReadEfuseInfo8723BS(padapter);
1981 }
1982
1983 static VOID
1984 _InitOtherVariable(
1985         IN PADAPTER             Adapter
1986         )
1987 {
1988         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(Adapter);
1989
1990
1991         //if(Adapter->bInHctTest){
1992         //      pMgntInfo->PowerSaveControl.bInactivePs = FALSE;
1993         //      pMgntInfo->PowerSaveControl.bIPSModeBackup = FALSE;
1994         //      pMgntInfo->PowerSaveControl.bLeisurePs = FALSE;
1995         //      pMgntInfo->keepAliveLevel = 0;
1996         //}
1997
1998
1999
2000 }
2001
2002 //
2003 //      Description:
2004 //              Read HW adapter information by E-Fuse or EEPROM according CR9346 reported.
2005 //
2006 //      Assumption:
2007 //              PASSIVE_LEVEL (SDIO interface)
2008 //
2009 //
2010 static s32 _ReadAdapterInfo8723BS(PADAPTER padapter)
2011 {
2012     u8 val8;
2013         u32 start;
2014
2015         RT_TRACE(_module_hci_hal_init_c_, _drv_info_, ("+_ReadAdapterInfo8723BS\n"));
2016
2017         // before access eFuse, make sure card enable has been called
2018         if(padapter->hw_init_completed == _FALSE)
2019                 _InitPowerOn_8723BS(padapter);
2020
2021
2022         val8 = rtw_read8(padapter, 0x4e);
2023         MSG_8192C("%s, 0x4e=0x%x\n", __func__, val8);
2024         val8 |= BIT(6);
2025         rtw_write8(padapter, 0x4e, val8);
2026
2027
2028         start = rtw_get_current_time();
2029
2030         _EfuseCellSel(padapter);
2031         _ReadRFType(padapter);
2032         _ReadPROMContent(padapter);
2033         _InitOtherVariable(padapter);
2034
2035 #ifdef CONFIG_PLATFORM_INTEL_BYT
2036 { //for BT, let BT can control ANT when wifi disable
2037         u32 val32;
2038         MSG_8192C("%s, 0x4c=0x%x\n", __func__, rtw_read32(padapter, 0x4c));
2039         val32 = rtw_read32(padapter, 0x64);
2040         MSG_8192C("%s, 0x64=0x%x\n", __func__, val32);
2041         val32 |= BIT(13);
2042         rtw_write32(padapter, 0x64, val32);
2043         MSG_8192C("%s, 0x64=0x%x\n", __func__, rtw_read32(padapter, 0x64));
2044 }
2045 #endif //CONFIG_PLATFORM_INTEL_BYT
2046
2047         if(padapter->hw_init_completed == _FALSE)
2048         {
2049                 rtw_write8(padapter, 0x67, 0x00); // for BT, Switch Ant control to BT
2050                 CardDisableRTL8723BSdio(padapter);//for the power consumption issue,  wifi ko module is loaded during booting, but wifi GUI is off
2051         }
2052
2053
2054         MSG_8192C("<==== _ReadAdapterInfo8723BS in %d ms\n", rtw_get_passing_time_ms(start));
2055
2056         return _SUCCESS;
2057 }
2058
2059 static void ReadAdapterInfo8723BS(PADAPTER padapter)
2060 {
2061         // Read EEPROM size before call any EEPROM function
2062         padapter->EepromAddressSize = GetEEPROMSize8723B(padapter);
2063
2064         _ReadAdapterInfo8723BS(padapter);
2065 }
2066
2067 /*
2068  * If variable not handled here,
2069  * some variables will be processed in SetHwReg8723B()
2070  */
2071 void SetHwReg8723BS(PADAPTER padapter, u8 variable, u8 *val)
2072 {
2073         PHAL_DATA_TYPE pHalData;
2074         u8 val8;
2075
2076 _func_enter_;
2077
2078         pHalData = GET_HAL_DATA(padapter);
2079
2080         switch (variable)
2081         {
2082                 case HW_VAR_SET_RPWM:
2083                         // rpwm value only use BIT0(clock bit) ,BIT6(Ack bit), and BIT7(Toggle bit)
2084                         // BIT0 value - 1: 32k, 0:40MHz.
2085                         // BIT6 value - 1: report cpwm value after success set, 0:do not report.
2086                         // BIT7 value - Toggle bit change.
2087                         {
2088                                 val8 = *val;
2089                                 val8 &= 0xC1;
2090                                 rtw_write8(padapter, SDIO_LOCAL_BASE|SDIO_REG_HRPWM1, val8);
2091                         }
2092                         break;
2093                 case HW_VAR_SET_REQ_FW_PS:
2094                         //1. driver write 0x8f[4]=1  //request fw ps state (only can write bit4)
2095                         {
2096                                 u8 req_fw_ps=0;
2097                                 req_fw_ps = rtw_read8(padapter, 0x8f);
2098                                 req_fw_ps |= 0x10;
2099                                 rtw_write8(padapter, 0x8f, req_fw_ps);
2100                         }
2101                         break;
2102                 case HW_VAR_RXDMA_AGG_PG_TH:
2103                         val8 = *val;
2104
2105                         // TH=1 => invalidate RX DMA aggregation
2106                         // TH=0 => validate RX DMA aggregation, use init value.
2107                         if (val8 == 0)
2108                         {
2109                                 // enable RXDMA aggregation
2110                                 //_RXAggrSwitch(padapter, _TRUE);
2111                         }
2112                         else
2113                         {
2114                                 // disable RXDMA aggregation
2115                                 //_RXAggrSwitch(padapter, _FALSE);
2116                         }
2117                         break;
2118                 case HW_VAR_DM_IN_LPS:
2119                         rtl8723b_hal_dm_in_lps(padapter);
2120                         break;
2121                 default:
2122                         SetHwReg8723B(padapter, variable, val);
2123                         break;
2124         }
2125
2126 _func_exit_;
2127 }
2128
2129 /*
2130  * If variable not handled here,
2131  * some variables will be processed in GetHwReg8723B()
2132  */
2133 void GetHwReg8723BS(PADAPTER padapter, u8 variable, u8 *val)
2134 {
2135         PHAL_DATA_TYPE pHalData = GET_HAL_DATA(padapter);
2136
2137 _func_enter_;
2138
2139         switch (variable)
2140         {
2141                 case HW_VAR_CPWM:
2142                         *val = rtw_read8(padapter, SDIO_LOCAL_BASE|SDIO_REG_HCPWM1_8723B);
2143                         break;
2144
2145                 case HW_VAR_FW_PS_STATE:
2146                         {
2147                                 //3. read dword 0x88               //driver read fw ps state
2148                                 *((u16*)val) = rtw_read16(padapter, 0x88);
2149                         }
2150                         break;
2151                 default:
2152                         GetHwReg8723B(padapter, variable, val);
2153                         break;
2154         }
2155
2156 _func_exit_;
2157 }
2158
2159 //
2160 //      Description:
2161 //              Query setting of specified variable.
2162 //
2163 u8
2164 GetHalDefVar8723BSDIO(
2165         IN      PADAPTER                                Adapter,
2166         IN      HAL_DEF_VARIABLE                eVariable,
2167         IN      PVOID                                   pValue
2168         )
2169 {
2170         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(Adapter);
2171         u8                      bResult = _SUCCESS;
2172
2173         switch(eVariable)
2174         {
2175                 case HAL_DEF_IS_SUPPORT_ANT_DIV:
2176 #ifdef CONFIG_ANTENNA_DIVERSITY
2177                         *((u8 *)pValue) = (IS_92C_SERIAL(pHalData->VersionID) ||(pHalData->AntDivCfg==0))?_FALSE:_TRUE;
2178 #endif
2179                         break;
2180                 case HAL_DEF_CURRENT_ANTENNA:
2181 #ifdef CONFIG_ANTENNA_DIVERSITY
2182                         *(( u8*)pValue) = pHalData->CurAntenna;
2183 #endif
2184                         break;
2185                 case HW_VAR_MAX_RX_AMPDU_FACTOR:
2186                         // Stanley@BB.SD3 suggests 16K can get stable performance
2187                         // coding by Lucas@20130730
2188                         *(HT_CAP_AMPDU_FACTOR*)pValue = MAX_AMPDU_FACTOR_16K;
2189                         break;
2190                 default:
2191                         bResult = GetHalDefVar8723B(Adapter, eVariable, pValue);
2192                         break;
2193         }
2194
2195         return bResult;
2196 }
2197
2198 //
2199 //      Description:
2200 //              Change default setting of specified variable.
2201 //
2202 u8
2203 SetHalDefVar8723BSDIO(
2204         IN      PADAPTER                                Adapter,
2205         IN      HAL_DEF_VARIABLE                eVariable,
2206         IN      PVOID                                   pValue
2207         )
2208 {
2209         PHAL_DATA_TYPE  pHalData = GET_HAL_DATA(Adapter);
2210         u8                      bResult = _SUCCESS;
2211
2212         switch(eVariable)
2213         {
2214                 default:
2215                         bResult = SetHalDefVar8723B(Adapter, eVariable, pValue);
2216                         break;
2217         }
2218
2219         return bResult;
2220 }
2221
2222 void rtl8723bs_set_hal_ops(PADAPTER padapter)
2223 {
2224         struct hal_ops *pHalFunc = &padapter->HalFunc;
2225
2226 _func_enter_;
2227
2228         rtl8723b_set_hal_ops(pHalFunc);
2229
2230         pHalFunc->hal_init = &rtl8723bs_hal_init;
2231         pHalFunc->hal_deinit = &rtl8723bs_hal_deinit;
2232
2233         pHalFunc->inirp_init = &rtl8723bs_inirp_init;
2234         pHalFunc->inirp_deinit = &rtl8723bs_inirp_deinit;
2235
2236         pHalFunc->init_xmit_priv = &rtl8723bs_init_xmit_priv;
2237         pHalFunc->free_xmit_priv = &rtl8723bs_free_xmit_priv;
2238
2239         pHalFunc->init_recv_priv = &rtl8723bs_init_recv_priv;
2240         pHalFunc->free_recv_priv = &rtl8723bs_free_recv_priv;
2241
2242         pHalFunc->InitSwLeds = &rtl8723bs_InitSwLeds;
2243         pHalFunc->DeInitSwLeds = &rtl8723bs_DeInitSwLeds;
2244
2245         pHalFunc->init_default_value = &rtl8723bs_init_default_value;
2246         pHalFunc->intf_chip_configure = &rtl8723bs_interface_configure;
2247         pHalFunc->read_adapter_info = &ReadAdapterInfo8723BS;
2248
2249         pHalFunc->enable_interrupt = &EnableInterrupt8723BSdio;
2250         pHalFunc->disable_interrupt = &DisableInterrupt8723BSdio;
2251         pHalFunc->check_ips_status = &CheckIPSStatus;
2252 #ifdef CONFIG_WOWLAN
2253         pHalFunc->clear_interrupt = &ClearInterrupt8723BSdio;
2254 #endif
2255         pHalFunc->SetHwRegHandler = &SetHwReg8723BS;
2256         pHalFunc->GetHwRegHandler = &GetHwReg8723BS;
2257         pHalFunc->GetHalDefVarHandler = &GetHalDefVar8723BSDIO;
2258         pHalFunc->SetHalDefVarHandler = &SetHalDefVar8723BSDIO;
2259
2260         pHalFunc->hal_xmit = &rtl8723bs_hal_xmit;
2261         pHalFunc->mgnt_xmit = &rtl8723bs_mgnt_xmit;
2262         pHalFunc->hal_xmitframe_enqueue = &rtl8723bs_hal_xmitframe_enqueue;
2263
2264 #ifdef CONFIG_HOSTAPD_MLME
2265         pHalFunc->hostap_mgnt_xmit_entry = NULL;
2266 //      pHalFunc->hostap_mgnt_xmit_entry = &rtl8192cu_hostap_mgnt_xmit_entry;
2267 #endif
2268
2269 #if defined(CONFIG_CHECK_BT_HANG) && defined(CONFIG_BT_COEXIST)
2270         pHalFunc->hal_init_checkbthang_workqueue = &rtl8723bs_init_checkbthang_workqueue;
2271         pHalFunc->hal_free_checkbthang_workqueue = &rtl8723bs_free_checkbthang_workqueue;
2272         pHalFunc->hal_cancle_checkbthang_workqueue = &rtl8723bs_cancle_checkbthang_workqueue;
2273         pHalFunc->hal_checke_bt_hang = &rtl8723bs_hal_check_bt_hang;
2274 #endif
2275
2276 _func_exit_;
2277 }
2278
2279