1 /******************************************************************************
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3 * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
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5 * This program is free software; you can redistribute it and/or modify it
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6 * under the terms of version 2 of the GNU General Public License as
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7 * published by the Free Software Foundation.
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9 * This program is distributed in the hope that it will be useful, but WITHOUT
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10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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14 * You should have received a copy of the GNU General Public License along with
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15 * this program; if not, write to the Free Software Foundation, Inc.,
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16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
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19 ******************************************************************************/
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20 #ifndef __INC_HAL8188EPHYREG_H__
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21 #define __INC_HAL8188EPHYREG_H__
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22 /*--------------------------Define Parameters-------------------------------*/
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24 // BB-PHY register PMAC 0x100 PHY 0x800 - 0xEFF
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25 // 1. PMAC duplicate register due to connection: RF_Mode, TRxRN, NumOf L-STF
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26 // 2. 0x800/0x900/0xA00/0xC00/0xD00/0xE00
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27 // 3. RF register 0x00-2E
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28 // 4. Bit Mask for BB/RF register
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29 // 5. Other defintion for BB/RF R/W
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34 // 1. PMAC duplicate register due to connection: RF_Mode, TRxRN, NumOf L-STF
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37 #define rPMAC_Reset 0x100
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38 #define rPMAC_TxStart 0x104
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39 #define rPMAC_TxLegacySIG 0x108
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40 #define rPMAC_TxHTSIG1 0x10c
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41 #define rPMAC_TxHTSIG2 0x110
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42 #define rPMAC_PHYDebug 0x114
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43 #define rPMAC_TxPacketNum 0x118
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44 #define rPMAC_TxIdle 0x11c
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45 #define rPMAC_TxMACHeader0 0x120
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46 #define rPMAC_TxMACHeader1 0x124
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47 #define rPMAC_TxMACHeader2 0x128
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48 #define rPMAC_TxMACHeader3 0x12c
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49 #define rPMAC_TxMACHeader4 0x130
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50 #define rPMAC_TxMACHeader5 0x134
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51 #define rPMAC_TxDataType 0x138
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52 #define rPMAC_TxRandomSeed 0x13c
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53 #define rPMAC_CCKPLCPPreamble 0x140
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54 #define rPMAC_CCKPLCPHeader 0x144
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55 #define rPMAC_CCKCRC16 0x148
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56 #define rPMAC_OFDMRxCRC32OK 0x170
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57 #define rPMAC_OFDMRxCRC32Er 0x174
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58 #define rPMAC_OFDMRxParityEr 0x178
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59 #define rPMAC_OFDMRxCRC8Er 0x17c
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60 #define rPMAC_CCKCRxRC16Er 0x180
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61 #define rPMAC_CCKCRxRC32Er 0x184
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62 #define rPMAC_CCKCRxRC32OK 0x188
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63 #define rPMAC_TxStatus 0x18c
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68 // The following two definition are only used for USB interface.
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69 #define RF_BB_CMD_ADDR 0x02c0 // RF/BB read/write command address.
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70 #define RF_BB_CMD_DATA 0x02c4 // RF/BB read/write command data.
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75 #define rFPGA0_RFMOD 0x800 //RF mode & CCK TxSC // RF BW Setting??
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77 #define rFPGA0_TxInfo 0x804 // Status report??
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78 #define rFPGA0_PSDFunction 0x808
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80 #define rFPGA0_TxGainStage 0x80c // Set TX PWR init gain?
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82 #define rFPGA0_RFTiming1 0x810 // Useless now
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83 #define rFPGA0_RFTiming2 0x814
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85 #define rFPGA0_XA_HSSIParameter1 0x820 // RF 3 wire register
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86 #define rFPGA0_XA_HSSIParameter2 0x824
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87 #define rFPGA0_XB_HSSIParameter1 0x828
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88 #define rFPGA0_XB_HSSIParameter2 0x82c
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90 #define rFPGA0_XA_LSSIParameter 0x840
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91 #define rFPGA0_XB_LSSIParameter 0x844
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93 #define rFPGA0_RFWakeUpParameter 0x850 // Useless now
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94 #define rFPGA0_RFSleepUpParameter 0x854
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96 #define rFPGA0_XAB_SwitchControl 0x858 // RF Channel switch
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97 #define rFPGA0_XCD_SwitchControl 0x85c
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99 #define rFPGA0_XA_RFInterfaceOE 0x860 // RF Channel switch
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100 #define rFPGA0_XB_RFInterfaceOE 0x864
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101 #define rFPGA0_XAB_RFInterfaceSW 0x870 // RF Interface Software Control
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102 #define rFPGA0_XCD_RFInterfaceSW 0x874
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104 #define rFPGA0_XAB_RFParameter 0x878 // RF Parameter
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105 #define rFPGA0_XCD_RFParameter 0x87c
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107 #define rFPGA0_AnalogParameter1 0x880 // Crystal cap setting RF-R/W protection for parameter4??
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108 #define rFPGA0_AnalogParameter2 0x884
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109 #define rFPGA0_AnalogParameter3 0x888
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110 #define rFPGA0_AdDaClockEn 0x888 // enable ad/da clock1 for dual-phy
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111 #define rFPGA0_AnalogParameter4 0x88c
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113 #define rFPGA0_XA_LSSIReadBack 0x8a0 // Tranceiver LSSI Readback
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114 #define rFPGA0_XB_LSSIReadBack 0x8a4
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115 #define rFPGA0_XC_LSSIReadBack 0x8a8
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116 #define rFPGA0_XD_LSSIReadBack 0x8ac
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118 #define rFPGA0_PSDReport 0x8b4 // Useless now
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119 #define TransceiverA_HSPI_Readback 0x8b8 // Transceiver A HSPI Readback
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120 #define TransceiverB_HSPI_Readback 0x8bc // Transceiver B HSPI Readback
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121 #define rFPGA0_XAB_RFInterfaceRB 0x8e0 // Useless now // RF Interface Readback Value
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122 #define rFPGA0_XCD_RFInterfaceRB 0x8e4 // Useless now
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127 #define rFPGA1_RFMOD 0x900 //RF mode & OFDM TxSC // RF BW Setting??
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129 #define rFPGA1_TxBlock 0x904 // Useless now
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130 #define rFPGA1_DebugSelect 0x908 // Useless now
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131 #define rFPGA1_TxInfo 0x90c // Useless now // Status report??
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136 // Set Control channel to upper or lower. These settings are required only for 40MHz
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137 #define rCCK0_System 0xa00
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139 #define rCCK0_AFESetting 0xa04 // Disable init gain now // Select RX path by RSSI
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140 #define rCCK0_CCA 0xa08 // Disable init gain now // Init gain
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142 #define rCCK0_RxAGC1 0xa0c //AGC default value, saturation level // Antenna Diversity, RX AGC, LNA Threshold, RX LNA Threshold useless now. Not the same as 90 series
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143 #define rCCK0_RxAGC2 0xa10 //AGC & DAGC
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145 #define rCCK0_RxHP 0xa14
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147 #define rCCK0_DSPParameter1 0xa18 //Timing recovery & Channel estimation threshold
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148 #define rCCK0_DSPParameter2 0xa1c //SQ threshold
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150 #define rCCK0_TxFilter1 0xa20
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151 #define rCCK0_TxFilter2 0xa24
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152 #define rCCK0_DebugPort 0xa28 //debug port and Tx filter3
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153 #define rCCK0_FalseAlarmReport 0xa2c //0xa2d useless now 0xa30-a4f channel report
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154 #define rCCK0_TRSSIReport 0xa50
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155 #define rCCK0_RxReport 0xa54 //0xa57
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156 #define rCCK0_FACounterLower 0xa5c //0xa5b
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157 #define rCCK0_FACounterUpper 0xa58 //0xa5c
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162 #define rPdp_AntA 0xb00
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163 #define rPdp_AntA_4 0xb04
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164 #define rConfig_Pmpd_AntA 0xb28
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165 #define rConfig_ram64x16 0xb2c
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166 #define rConfig_AntA 0xb68
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167 #define rConfig_AntB 0xb6c
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168 #define rPdp_AntB 0xb70
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169 #define rPdp_AntB_4 0xb74
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170 #define rConfig_Pmpd_AntB 0xb98
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178 #define rOFDM0_LSTF 0xc00
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180 #define rOFDM0_TRxPathEnable 0xc04
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181 #define rOFDM0_TRMuxPar 0xc08
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182 #define rOFDM0_TRSWIsolation 0xc0c
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184 #define rOFDM0_XARxAFE 0xc10 //RxIQ DC offset, Rx digital filter, DC notch filter
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185 #define rOFDM0_XARxIQImbalance 0xc14 //RxIQ imblance matrix
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186 #define rOFDM0_XBRxAFE 0xc18
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187 #define rOFDM0_XBRxIQImbalance 0xc1c
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188 #define rOFDM0_XCRxAFE 0xc20
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189 #define rOFDM0_XCRxIQImbalance 0xc24
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190 #define rOFDM0_XDRxAFE 0xc28
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191 #define rOFDM0_XDRxIQImbalance 0xc2c
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193 #define rOFDM0_RxDetector1 0xc30 //PD,BW & SBD // DM tune init gain
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194 #define rOFDM0_RxDetector2 0xc34 //SBD & Fame Sync.
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195 #define rOFDM0_RxDetector3 0xc38 //Frame Sync.
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196 #define rOFDM0_RxDetector4 0xc3c //PD, SBD, Frame Sync & Short-GI
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198 #define rOFDM0_RxDSP 0xc40 //Rx Sync Path
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199 #define rOFDM0_CFOandDAGC 0xc44 //CFO & DAGC
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200 #define rOFDM0_CCADropThreshold 0xc48 //CCA Drop threshold
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201 #define rOFDM0_ECCAThreshold 0xc4c // energy CCA
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203 #define rOFDM0_XAAGCCore1 0xc50 // DIG
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204 #define rOFDM0_XAAGCCore2 0xc54
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205 #define rOFDM0_XBAGCCore1 0xc58
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206 #define rOFDM0_XBAGCCore2 0xc5c
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207 #define rOFDM0_XCAGCCore1 0xc60
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208 #define rOFDM0_XCAGCCore2 0xc64
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209 #define rOFDM0_XDAGCCore1 0xc68
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210 #define rOFDM0_XDAGCCore2 0xc6c
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212 #define rOFDM0_AGCParameter1 0xc70
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213 #define rOFDM0_AGCParameter2 0xc74
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214 #define rOFDM0_AGCRSSITable 0xc78
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215 #define rOFDM0_HTSTFAGC 0xc7c
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217 #define rOFDM0_XATxIQImbalance 0xc80 // TX PWR TRACK and DIG
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218 #define rOFDM0_XATxAFE 0xc84
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219 #define rOFDM0_XBTxIQImbalance 0xc88
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220 #define rOFDM0_XBTxAFE 0xc8c
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221 #define rOFDM0_XCTxIQImbalance 0xc90
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222 #define rOFDM0_XCTxAFE 0xc94
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223 #define rOFDM0_XDTxIQImbalance 0xc98
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224 #define rOFDM0_XDTxAFE 0xc9c
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226 #define rOFDM0_RxIQExtAnta 0xca0
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227 #define rOFDM0_TxCoeff1 0xca4
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228 #define rOFDM0_TxCoeff2 0xca8
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229 #define rOFDM0_TxCoeff3 0xcac
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230 #define rOFDM0_TxCoeff4 0xcb0
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231 #define rOFDM0_TxCoeff5 0xcb4
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232 #define rOFDM0_TxCoeff6 0xcb8
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233 #define rOFDM0_RxHPParameter 0xce0
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234 #define rOFDM0_TxPseudoNoiseWgt 0xce4
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235 #define rOFDM0_FrameSync 0xcf0
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236 #define rOFDM0_DFSReport 0xcf4
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242 #define rOFDM1_LSTF 0xd00
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243 #define rOFDM1_TRxPathEnable 0xd04
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245 #define rOFDM1_CFO 0xd08 // No setting now
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246 #define rOFDM1_CSI1 0xd10
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247 #define rOFDM1_SBD 0xd14
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248 #define rOFDM1_CSI2 0xd18
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249 #define rOFDM1_CFOTracking 0xd2c
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250 #define rOFDM1_TRxMesaure1 0xd34
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251 #define rOFDM1_IntfDet 0xd3c
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252 #define rOFDM1_csi_fix_mask1 0xd40
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253 #define rOFDM1_csi_fix_mask2 0xd44
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254 #define rOFDM1_PseudoNoiseStateAB 0xd50
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255 #define rOFDM1_PseudoNoiseStateCD 0xd54
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256 #define rOFDM1_RxPseudoNoiseWgt 0xd58
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258 #define rOFDM_PHYCounter1 0xda0 //cca, parity fail
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259 #define rOFDM_PHYCounter2 0xda4 //rate illegal, crc8 fail
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260 #define rOFDM_PHYCounter3 0xda8 //MCS not support
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262 #define rOFDM_ShortCFOAB 0xdac // No setting now
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263 #define rOFDM_ShortCFOCD 0xdb0
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264 #define rOFDM_LongCFOAB 0xdb4
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265 #define rOFDM_LongCFOCD 0xdb8
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266 #define rOFDM_TailCFOAB 0xdbc
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267 #define rOFDM_TailCFOCD 0xdc0
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268 #define rOFDM_PWMeasure1 0xdc4
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269 #define rOFDM_PWMeasure2 0xdc8
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270 #define rOFDM_BWReport 0xdcc
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271 #define rOFDM_AGCReport 0xdd0
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272 #define rOFDM_RxSNR 0xdd4
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273 #define rOFDM_RxEVMCSI 0xdd8
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274 #define rOFDM_SIGReport 0xddc
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280 #define rTxAGC_A_Rate18_06 0xe00
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281 #define rTxAGC_A_Rate54_24 0xe04
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282 #define rTxAGC_A_CCK1_Mcs32 0xe08
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283 #define rTxAGC_A_Mcs03_Mcs00 0xe10
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284 #define rTxAGC_A_Mcs07_Mcs04 0xe14
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285 #define rTxAGC_A_Mcs11_Mcs08 0xe18
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286 #define rTxAGC_A_Mcs15_Mcs12 0xe1c
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288 #define rTxAGC_B_Rate18_06 0x830
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289 #define rTxAGC_B_Rate54_24 0x834
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290 #define rTxAGC_B_CCK1_55_Mcs32 0x838
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291 #define rTxAGC_B_Mcs03_Mcs00 0x83c
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292 #define rTxAGC_B_Mcs07_Mcs04 0x848
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293 #define rTxAGC_B_Mcs11_Mcs08 0x84c
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294 #define rTxAGC_B_Mcs15_Mcs12 0x868
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295 #define rTxAGC_B_CCK11_A_CCK2_11 0x86c
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297 #define rFPGA0_IQK 0xe28
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298 #define rTx_IQK_Tone_A 0xe30
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299 #define rRx_IQK_Tone_A 0xe34
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300 #define rTx_IQK_PI_A 0xe38
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301 #define rRx_IQK_PI_A 0xe3c
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303 #define rTx_IQK 0xe40
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304 #define rRx_IQK 0xe44
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305 #define rIQK_AGC_Pts 0xe48
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306 #define rIQK_AGC_Rsp 0xe4c
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307 #define rTx_IQK_Tone_B 0xe50
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308 #define rRx_IQK_Tone_B 0xe54
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309 #define rTx_IQK_PI_B 0xe58
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310 #define rRx_IQK_PI_B 0xe5c
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311 #define rIQK_AGC_Cont 0xe60
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313 #define rBlue_Tooth 0xe6c
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314 #define rRx_Wait_CCA 0xe70
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315 #define rTx_CCK_RFON 0xe74
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316 #define rTx_CCK_BBON 0xe78
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317 #define rTx_OFDM_RFON 0xe7c
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318 #define rTx_OFDM_BBON 0xe80
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319 #define rTx_To_Rx 0xe84
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320 #define rTx_To_Tx 0xe88
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321 #define rRx_CCK 0xe8c
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323 #define rTx_Power_Before_IQK_A 0xe94
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324 #define rTx_Power_After_IQK_A 0xe9c
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326 #define rRx_Power_Before_IQK_A 0xea0
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327 #define rRx_Power_Before_IQK_A_2 0xea4
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328 #define rRx_Power_After_IQK_A 0xea8
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329 #define rRx_Power_After_IQK_A_2 0xeac
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331 #define rTx_Power_Before_IQK_B 0xeb4
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332 #define rTx_Power_After_IQK_B 0xebc
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334 #define rRx_Power_Before_IQK_B 0xec0
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335 #define rRx_Power_Before_IQK_B_2 0xec4
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336 #define rRx_Power_After_IQK_B 0xec8
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337 #define rRx_Power_After_IQK_B_2 0xecc
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339 #define rRx_OFDM 0xed0
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340 #define rRx_Wait_RIFS 0xed4
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341 #define rRx_TO_Rx 0xed8
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342 #define rStandby 0xedc
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343 #define rSleep 0xee0
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344 #define rPMPD_ANAEN 0xeec
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347 // 7. RF Register 0x00-0x2E (RF 8256)
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348 // RF-0222D 0x00-3F
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351 #define rZebra1_HSSIEnable 0x0 // Useless now
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352 #define rZebra1_TRxEnable1 0x1
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353 #define rZebra1_TRxEnable2 0x2
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354 #define rZebra1_AGC 0x4
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355 #define rZebra1_ChargePump 0x5
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356 #define rZebra1_Channel 0x7 // RF channel switch
\r
359 #define rZebra1_TxGain 0x8 // Useless now
\r
360 #define rZebra1_TxLPF 0x9
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361 #define rZebra1_RxLPF 0xb
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362 #define rZebra1_RxHPFCorner 0xc
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365 #define rGlobalCtrl 0 // Useless now
\r
366 #define rRTL8256_TxLPF 19
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367 #define rRTL8256_RxLPF 11
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370 #define rRTL8258_TxLPF 0x11 // Useless now
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371 #define rRTL8258_RxLPF 0x13
\r
372 #define rRTL8258_RSSILPF 0xa
\r
375 // RL6052 Register definition
\r
377 #define RF_AC 0x00 //
\r
379 #define RF_IQADJ_G1 0x01 //
\r
380 #define RF_IQADJ_G2 0x02 //
\r
382 #define RF_POW_TRSW 0x05 //
\r
384 #define RF_GAIN_RX 0x06 //
\r
385 #define RF_GAIN_TX 0x07 //
\r
387 #define RF_TXM_IDAC 0x08 //
\r
388 #define RF_IPA_G 0x09 //
\r
389 #define RF_TXBIAS_G 0x0A
\r
390 #define RF_TXPA_AG 0x0B
\r
391 #define RF_IPA_A 0x0C //
\r
392 #define RF_TXBIAS_A 0x0D
\r
393 #define RF_BS_PA_APSET_G9_G11 0x0E
\r
394 #define RF_BS_IQGEN 0x0F //
\r
396 #define RF_MODE1 0x10 //
\r
397 #define RF_MODE2 0x11 //
\r
399 #define RF_RX_AGC_HP 0x12 //
\r
400 #define RF_TX_AGC 0x13 //
\r
401 #define RF_BIAS 0x14 //
\r
402 #define RF_IPA 0x15 //
\r
403 #define RF_TXBIAS 0x16
\r
404 #define RF_POW_ABILITY 0x17 //
\r
405 #define RF_CHNLBW 0x18 // RF channel and BW switch
\r
406 #define RF_TOP 0x19 //
\r
408 #define RF_RX_G1 0x1A //
\r
409 #define RF_RX_G2 0x1B //
\r
411 #define RF_RX_BB2 0x1C //
\r
412 #define RF_RX_BB1 0x1D //
\r
414 #define RF_RCK1 0x1E //
\r
415 #define RF_RCK2 0x1F //
\r
417 #define RF_TX_G1 0x20 //
\r
418 #define RF_TX_G2 0x21 //
\r
419 #define RF_TX_G3 0x22 //
\r
421 #define RF_TX_BB1 0x23 //
\r
423 //#if HARDWARE_TYPE_IS_RTL8192D == 1
\r
424 #define RF_T_METER_92D 0x42 //
\r
426 #define RF_T_METER_88E 0x42 //
\r
427 #define RF_T_METER 0x24 //
\r
431 #define RF_SYN_G1 0x25 // RF TX Power control
\r
432 #define RF_SYN_G2 0x26 // RF TX Power control
\r
433 #define RF_SYN_G3 0x27 // RF TX Power control
\r
434 #define RF_SYN_G4 0x28 // RF TX Power control
\r
435 #define RF_SYN_G5 0x29 // RF TX Power control
\r
436 #define RF_SYN_G6 0x2A // RF TX Power control
\r
437 #define RF_SYN_G7 0x2B // RF TX Power control
\r
438 #define RF_SYN_G8 0x2C // RF TX Power control
\r
440 #define RF_RCK_OS 0x30 // RF TX PA control
\r
441 #define RF_TXPA_G1 0x31 // RF TX PA control
\r
442 #define RF_TXPA_G2 0x32 // RF TX PA control
\r
443 #define RF_TXPA_G3 0x33 // RF TX PA control
\r
444 #define RF_TX_BIAS_A 0x35
\r
445 #define RF_TX_BIAS_D 0x36
\r
446 #define RF_LOBF_9 0x38
\r
447 #define RF_RXRF_A3 0x3C //
\r
448 #define RF_TRSW 0x3F
\r
450 #define RF_TXRF_A2 0x41
\r
451 #define RF_TXPA_G4 0x46
\r
452 #define RF_TXPA_A4 0x4B
\r
453 #define RF_0x52 0x52
\r
454 #define RF_WE_LUT 0xEF
\r
461 #define bBBResetB 0x100 // Useless now?
\r
462 #define bGlobalResetB 0x200
\r
463 #define bOFDMTxStart 0x4
\r
464 #define bCCKTxStart 0x8
\r
465 #define bCRC32Debug 0x100
\r
466 #define bPMACLoopback 0x10
\r
467 #define bTxLSIG 0xffffff
\r
468 #define bOFDMTxRate 0xf
\r
469 #define bOFDMTxReserved 0x10
\r
470 #define bOFDMTxLength 0x1ffe0
\r
471 #define bOFDMTxParity 0x20000
\r
472 #define bTxHTSIG1 0xffffff
\r
473 #define bTxHTMCSRate 0x7f
\r
474 #define bTxHTBW 0x80
\r
475 #define bTxHTLength 0xffff00
\r
476 #define bTxHTSIG2 0xffffff
\r
477 #define bTxHTSmoothing 0x1
\r
478 #define bTxHTSounding 0x2
\r
479 #define bTxHTReserved 0x4
\r
480 #define bTxHTAggreation 0x8
\r
481 #define bTxHTSTBC 0x30
\r
482 #define bTxHTAdvanceCoding 0x40
\r
483 #define bTxHTShortGI 0x80
\r
484 #define bTxHTNumberHT_LTF 0x300
\r
485 #define bTxHTCRC8 0x3fc00
\r
486 #define bCounterReset 0x10000
\r
487 #define bNumOfOFDMTx 0xffff
\r
488 #define bNumOfCCKTx 0xffff0000
\r
489 #define bTxIdleInterval 0xffff
\r
490 #define bOFDMService 0xffff0000
\r
491 #define bTxMACHeader 0xffffffff
\r
492 #define bTxDataInit 0xff
\r
493 #define bTxHTMode 0x100
\r
494 #define bTxDataType 0x30000
\r
495 #define bTxRandomSeed 0xffffffff
\r
496 #define bCCKTxPreamble 0x1
\r
497 #define bCCKTxSFD 0xffff0000
\r
498 #define bCCKTxSIG 0xff
\r
499 #define bCCKTxService 0xff00
\r
500 #define bCCKLengthExt 0x8000
\r
501 #define bCCKTxLength 0xffff0000
\r
502 #define bCCKTxCRC16 0xffff
\r
503 #define bCCKTxStatus 0x1
\r
504 #define bOFDMTxStatus 0x2
\r
506 #define IS_BB_REG_OFFSET_92S(_Offset) ((_Offset >= 0x800) && (_Offset <= 0xfff))
\r
509 #define bRFMOD 0x1 // Reg 0x800 rFPGA0_RFMOD
\r
510 #define bJapanMode 0x2
\r
511 #define bCCKTxSC 0x30
\r
512 #define bCCKEn 0x1000000
\r
513 #define bOFDMEn 0x2000000
\r
515 #define bOFDMRxADCPhase 0x10000 // Useless now
\r
516 #define bOFDMTxDACPhase 0x40000
\r
517 #define bXATxAGC 0x3f
\r
519 #define bAntennaSelect 0x0300
\r
521 #define bXBTxAGC 0xf00 // Reg 80c rFPGA0_TxGainStage
\r
522 #define bXCTxAGC 0xf000
\r
523 #define bXDTxAGC 0xf0000
\r
525 #define bPAStart 0xf0000000 // Useless now
\r
526 #define bTRStart 0x00f00000
\r
527 #define bRFStart 0x0000f000
\r
528 #define bBBStart 0x000000f0
\r
529 #define bBBCCKStart 0x0000000f
\r
530 #define bPAEnd 0xf //Reg0x814
\r
531 #define bTREnd 0x0f000000
\r
532 #define bRFEnd 0x000f0000
\r
533 #define bCCAMask 0x000000f0 //T2R
\r
534 #define bR2RCCAMask 0x00000f00
\r
535 #define bHSSI_R2TDelay 0xf8000000
\r
536 #define bHSSI_T2RDelay 0xf80000
\r
537 #define bContTxHSSI 0x400 //chane gain at continue Tx
\r
538 #define bIGFromCCK 0x200
\r
539 #define bAGCAddress 0x3f
\r
540 #define bRxHPTx 0x7000
\r
541 #define bRxHPT2R 0x38000
\r
542 #define bRxHPCCKIni 0xc0000
\r
543 #define bAGCTxCode 0xc00000
\r
544 #define bAGCRxCode 0x300000
\r
546 #define b3WireDataLength 0x800 // Reg 0x820~84f rFPGA0_XA_HSSIParameter1
\r
547 #define b3WireAddressLength 0x400
\r
549 #define b3WireRFPowerDown 0x1 // Useless now
\r
550 //#define bHWSISelect 0x8
\r
551 #define b5GPAPEPolarity 0x40000000
\r
552 #define b2GPAPEPolarity 0x80000000
\r
553 #define bRFSW_TxDefaultAnt 0x3
\r
554 #define bRFSW_TxOptionAnt 0x30
\r
555 #define bRFSW_RxDefaultAnt 0x300
\r
556 #define bRFSW_RxOptionAnt 0x3000
\r
557 #define bRFSI_3WireData 0x1
\r
558 #define bRFSI_3WireClock 0x2
\r
559 #define bRFSI_3WireLoad 0x4
\r
560 #define bRFSI_3WireRW 0x8
\r
561 #define bRFSI_3Wire 0xf
\r
563 #define bRFSI_RFENV 0x10 // Reg 0x870 rFPGA0_XAB_RFInterfaceSW
\r
565 #define bRFSI_TRSW 0x20 // Useless now
\r
566 #define bRFSI_TRSWB 0x40
\r
567 #define bRFSI_ANTSW 0x100
\r
568 #define bRFSI_ANTSWB 0x200
\r
569 #define bRFSI_PAPE 0x400
\r
570 #define bRFSI_PAPE5G 0x800
\r
571 #define bBandSelect 0x1
\r
572 #define bHTSIG2_GI 0x80
\r
573 #define bHTSIG2_Smoothing 0x01
\r
574 #define bHTSIG2_Sounding 0x02
\r
575 #define bHTSIG2_Aggreaton 0x08
\r
576 #define bHTSIG2_STBC 0x30
\r
577 #define bHTSIG2_AdvCoding 0x40
\r
578 #define bHTSIG2_NumOfHTLTF 0x300
\r
579 #define bHTSIG2_CRC8 0x3fc
\r
580 #define bHTSIG1_MCS 0x7f
\r
581 #define bHTSIG1_BandWidth 0x80
\r
582 #define bHTSIG1_HTLength 0xffff
\r
583 #define bLSIG_Rate 0xf
\r
584 #define bLSIG_Reserved 0x10
\r
585 #define bLSIG_Length 0x1fffe
\r
586 #define bLSIG_Parity 0x20
\r
587 #define bCCKRxPhase 0x4
\r
589 #define bLSSIReadAddress 0x7f800000 // T65 RF
\r
591 #define bLSSIReadEdge 0x80000000 //LSSI "Read" edge signal
\r
593 #define bLSSIReadBackData 0xfffff // T65 RF
\r
595 #define bLSSIReadOKFlag 0x1000 // Useless now
\r
596 #define bCCKSampleRate 0x8 //0: 44MHz, 1:88MHz
\r
597 #define bRegulator0Standby 0x1
\r
598 #define bRegulatorPLLStandby 0x2
\r
599 #define bRegulator1Standby 0x4
\r
600 #define bPLLPowerUp 0x8
\r
601 #define bDPLLPowerUp 0x10
\r
602 #define bDA10PowerUp 0x20
\r
603 #define bAD7PowerUp 0x200
\r
604 #define bDA6PowerUp 0x2000
\r
605 #define bXtalPowerUp 0x4000
\r
606 #define b40MDClkPowerUP 0x8000
\r
607 #define bDA6DebugMode 0x20000
\r
608 #define bDA6Swing 0x380000
\r
610 #define bADClkPhase 0x4000000 // Reg 0x880 rFPGA0_AnalogParameter1 20/40 CCK support switch 40/80 BB MHZ
\r
612 #define b80MClkDelay 0x18000000 // Useless
\r
613 #define bAFEWatchDogEnable 0x20000000
\r
615 #define bXtalCap01 0xc0000000 // Reg 0x884 rFPGA0_AnalogParameter2 Crystal cap
\r
616 #define bXtalCap23 0x3
\r
617 #define bXtalCap92x 0x0f000000
\r
618 #define bXtalCap 0x0f000000
\r
620 #define bIntDifClkEnable 0x400 // Useless
\r
621 #define bExtSigClkEnable 0x800
\r
622 #define bBandgapMbiasPowerUp 0x10000
\r
623 #define bAD11SHGain 0xc0000
\r
624 #define bAD11InputRange 0x700000
\r
625 #define bAD11OPCurrent 0x3800000
\r
626 #define bIPathLoopback 0x4000000
\r
627 #define bQPathLoopback 0x8000000
\r
628 #define bAFELoopback 0x10000000
\r
629 #define bDA10Swing 0x7e0
\r
630 #define bDA10Reverse 0x800
\r
631 #define bDAClkSource 0x1000
\r
632 #define bAD7InputRange 0x6000
\r
633 #define bAD7Gain 0x38000
\r
634 #define bAD7OutputCMMode 0x40000
\r
635 #define bAD7InputCMMode 0x380000
\r
636 #define bAD7Current 0xc00000
\r
637 #define bRegulatorAdjust 0x7000000
\r
638 #define bAD11PowerUpAtTx 0x1
\r
639 #define bDA10PSAtTx 0x10
\r
640 #define bAD11PowerUpAtRx 0x100
\r
641 #define bDA10PSAtRx 0x1000
\r
642 #define bCCKRxAGCFormat 0x200
\r
643 #define bPSDFFTSamplepPoint 0xc000
\r
644 #define bPSDAverageNum 0x3000
\r
645 #define bIQPathControl 0xc00
\r
646 #define bPSDFreq 0x3ff
\r
647 #define bPSDAntennaPath 0x30
\r
648 #define bPSDIQSwitch 0x40
\r
649 #define bPSDRxTrigger 0x400000
\r
650 #define bPSDTxTrigger 0x80000000
\r
651 #define bPSDSineToneScale 0x7f000000
\r
652 #define bPSDReport 0xffff
\r
655 #define bOFDMTxSC 0x30000000 // Useless
\r
656 #define bCCKTxOn 0x1
\r
657 #define bOFDMTxOn 0x2
\r
658 #define bDebugPage 0xfff //reset debug page and also HWord, LWord
\r
659 #define bDebugItem 0xff //reset debug page and LWord
\r
661 #define bAntNonHT 0x100
\r
662 #define bAntHT1 0x1000
\r
663 #define bAntHT2 0x10000
\r
664 #define bAntHT1S1 0x100000
\r
665 #define bAntNonHTS1 0x1000000
\r
668 #define bCCKBBMode 0x3 // Useless
\r
669 #define bCCKTxPowerSaving 0x80
\r
670 #define bCCKRxPowerSaving 0x40
\r
672 #define bCCKSideBand 0x10 // Reg 0xa00 rCCK0_System 20/40 switch
\r
674 #define bCCKScramble 0x8 // Useless
\r
675 #define bCCKAntDiversity 0x8000
\r
676 #define bCCKCarrierRecovery 0x4000
\r
677 #define bCCKTxRate 0x3000
\r
678 #define bCCKDCCancel 0x0800
\r
679 #define bCCKISICancel 0x0400
\r
680 #define bCCKMatchFilter 0x0200
\r
681 #define bCCKEqualizer 0x0100
\r
682 #define bCCKPreambleDetect 0x800000
\r
683 #define bCCKFastFalseCCA 0x400000
\r
684 #define bCCKChEstStart 0x300000
\r
685 #define bCCKCCACount 0x080000
\r
686 #define bCCKcs_lim 0x070000
\r
687 #define bCCKBistMode 0x80000000
\r
688 #define bCCKCCAMask 0x40000000
\r
689 #define bCCKTxDACPhase 0x4
\r
690 #define bCCKRxADCPhase 0x20000000 //r_rx_clk
\r
691 #define bCCKr_cp_mode0 0x0100
\r
692 #define bCCKTxDCOffset 0xf0
\r
693 #define bCCKRxDCOffset 0xf
\r
694 #define bCCKCCAMode 0xc000
\r
695 #define bCCKFalseCS_lim 0x3f00
\r
696 #define bCCKCS_ratio 0xc00000
\r
697 #define bCCKCorgBit_sel 0x300000
\r
698 #define bCCKPD_lim 0x0f0000
\r
699 #define bCCKNewCCA 0x80000000
\r
700 #define bCCKRxHPofIG 0x8000
\r
701 #define bCCKRxIG 0x7f00
\r
702 #define bCCKLNAPolarity 0x800000
\r
703 #define bCCKRx1stGain 0x7f0000
\r
704 #define bCCKRFExtend 0x20000000 //CCK Rx Iinital gain polarity
\r
705 #define bCCKRxAGCSatLevel 0x1f000000
\r
706 #define bCCKRxAGCSatCount 0xe0
\r
707 #define bCCKRxRFSettle 0x1f //AGCsamp_dly
\r
708 #define bCCKFixedRxAGC 0x8000
\r
709 //#define bCCKRxAGCFormat 0x4000 //remove to HSSI register 0x824
\r
710 #define bCCKAntennaPolarity 0x2000
\r
711 #define bCCKTxFilterType 0x0c00
\r
712 #define bCCKRxAGCReportType 0x0300
\r
713 #define bCCKRxDAGCEn 0x80000000
\r
714 #define bCCKRxDAGCPeriod 0x20000000
\r
715 #define bCCKRxDAGCSatLevel 0x1f000000
\r
716 #define bCCKTimingRecovery 0x800000
\r
717 #define bCCKTxC0 0x3f0000
\r
718 #define bCCKTxC1 0x3f000000
\r
719 #define bCCKTxC2 0x3f
\r
720 #define bCCKTxC3 0x3f00
\r
721 #define bCCKTxC4 0x3f0000
\r
722 #define bCCKTxC5 0x3f000000
\r
723 #define bCCKTxC6 0x3f
\r
724 #define bCCKTxC7 0x3f00
\r
725 #define bCCKDebugPort 0xff0000
\r
726 #define bCCKDACDebug 0x0f000000
\r
727 #define bCCKFalseAlarmEnable 0x8000
\r
728 #define bCCKFalseAlarmRead 0x4000
\r
729 #define bCCKTRSSI 0x7f
\r
730 #define bCCKRxAGCReport 0xfe
\r
731 #define bCCKRxReport_AntSel 0x80000000
\r
732 #define bCCKRxReport_MFOff 0x40000000
\r
733 #define bCCKRxRxReport_SQLoss 0x20000000
\r
734 #define bCCKRxReport_Pktloss 0x10000000
\r
735 #define bCCKRxReport_Lockedbit 0x08000000
\r
736 #define bCCKRxReport_RateError 0x04000000
\r
737 #define bCCKRxReport_RxRate 0x03000000
\r
738 #define bCCKRxFACounterLower 0xff
\r
739 #define bCCKRxFACounterUpper 0xff000000
\r
740 #define bCCKRxHPAGCStart 0xe000
\r
741 #define bCCKRxHPAGCFinal 0x1c00
\r
742 #define bCCKRxFalseAlarmEnable 0x8000
\r
743 #define bCCKFACounterFreeze 0x4000
\r
744 #define bCCKTxPathSel 0x10000000
\r
745 #define bCCKDefaultRxPath 0xc000000
\r
746 #define bCCKOptionRxPath 0x3000000
\r
749 #define bNumOfSTF 0x3 // Useless
\r
750 #define bShift_L 0xc0
\r
752 #define bRxPathA 0x1
\r
753 #define bRxPathB 0x2
\r
754 #define bRxPathC 0x4
\r
755 #define bRxPathD 0x8
\r
756 #define bTxPathA 0x1
\r
757 #define bTxPathB 0x2
\r
758 #define bTxPathC 0x4
\r
759 #define bTxPathD 0x8
\r
760 #define bTRSSIFreq 0x200
\r
761 #define bADCBackoff 0x3000
\r
762 #define bDFIRBackoff 0xc000
\r
763 #define bTRSSILatchPhase 0x10000
\r
764 #define bRxIDCOffset 0xff
\r
765 #define bRxQDCOffset 0xff00
\r
766 #define bRxDFIRMode 0x1800000
\r
767 #define bRxDCNFType 0xe000000
\r
768 #define bRXIQImb_A 0x3ff
\r
769 #define bRXIQImb_B 0xfc00
\r
770 #define bRXIQImb_C 0x3f0000
\r
771 #define bRXIQImb_D 0xffc00000
\r
772 #define bDC_dc_Notch 0x60000
\r
773 #define bRxNBINotch 0x1f000000
\r
775 #define bPD_TH_Opt2 0xc000
\r
776 #define bPWED_TH 0x700
\r
777 #define bIfMF_Win_L 0x800
\r
778 #define bPD_Option 0x1000
\r
779 #define bMF_Win_L 0xe000
\r
780 #define bBW_Search_L 0x30000
\r
781 #define bwin_enh_L 0xc0000
\r
782 #define bBW_TH 0x700000
\r
783 #define bED_TH2 0x3800000
\r
784 #define bBW_option 0x4000000
\r
785 #define bRatio_TH 0x18000000
\r
786 #define bWindow_L 0xe0000000
\r
787 #define bSBD_Option 0x1
\r
788 #define bFrame_TH 0x1c
\r
789 #define bFS_Option 0x60
\r
790 #define bDC_Slope_check 0x80
\r
791 #define bFGuard_Counter_DC_L 0xe00
\r
792 #define bFrame_Weight_Short 0x7000
\r
793 #define bSub_Tune 0xe00000
\r
794 #define bFrame_DC_Length 0xe000000
\r
795 #define bSBD_start_offset 0x30000000
\r
796 #define bFrame_TH_2 0x7
\r
797 #define bFrame_GI2_TH 0x38
\r
798 #define bGI2_Sync_en 0x40
\r
799 #define bSarch_Short_Early 0x300
\r
800 #define bSarch_Short_Late 0xc00
\r
801 #define bSarch_GI2_Late 0x70000
\r
802 #define bCFOAntSum 0x1
\r
803 #define bCFOAcc 0x2
\r
804 #define bCFOStartOffset 0xc
\r
805 #define bCFOLookBack 0x70
\r
806 #define bCFOSumWeight 0x80
\r
807 #define bDAGCEnable 0x10000
\r
808 #define bTXIQImb_A 0x3ff
\r
809 #define bTXIQImb_B 0xfc00
\r
810 #define bTXIQImb_C 0x3f0000
\r
811 #define bTXIQImb_D 0xffc00000
\r
812 #define bTxIDCOffset 0xff
\r
813 #define bTxQDCOffset 0xff00
\r
814 #define bTxDFIRMode 0x10000
\r
815 #define bTxPesudoNoiseOn 0x4000000
\r
816 #define bTxPesudoNoise_A 0xff
\r
817 #define bTxPesudoNoise_B 0xff00
\r
818 #define bTxPesudoNoise_C 0xff0000
\r
819 #define bTxPesudoNoise_D 0xff000000
\r
820 #define bCCADropOption 0x20000
\r
821 #define bCCADropThres 0xfff00000
\r
822 #define bEDCCA_H 0xf
\r
823 #define bEDCCA_L 0xf0
\r
824 #define bLambda_ED 0x300
\r
825 #define bRxInitialGain 0x7f
\r
826 #define bRxAntDivEn 0x80
\r
827 #define bRxAGCAddressForLNA 0x7f00
\r
828 #define bRxHighPowerFlow 0x8000
\r
829 #define bRxAGCFreezeThres 0xc0000
\r
830 #define bRxFreezeStep_AGC1 0x300000
\r
831 #define bRxFreezeStep_AGC2 0xc00000
\r
832 #define bRxFreezeStep_AGC3 0x3000000
\r
833 #define bRxFreezeStep_AGC0 0xc000000
\r
834 #define bRxRssi_Cmp_En 0x10000000
\r
835 #define bRxQuickAGCEn 0x20000000
\r
836 #define bRxAGCFreezeThresMode 0x40000000
\r
837 #define bRxOverFlowCheckType 0x80000000
\r
838 #define bRxAGCShift 0x7f
\r
839 #define bTRSW_Tri_Only 0x80
\r
840 #define bPowerThres 0x300
\r
841 #define bRxAGCEn 0x1
\r
842 #define bRxAGCTogetherEn 0x2
\r
843 #define bRxAGCMin 0x4
\r
844 #define bRxHP_Ini 0x7
\r
845 #define bRxHP_TRLNA 0x70
\r
846 #define bRxHP_RSSI 0x700
\r
847 #define bRxHP_BBP1 0x7000
\r
848 #define bRxHP_BBP2 0x70000
\r
849 #define bRxHP_BBP3 0x700000
\r
850 #define bRSSI_H 0x7f0000 //the threshold for high power
\r
851 #define bRSSI_Gen 0x7f000000 //the threshold for ant diversity
\r
852 #define bRxSettle_TRSW 0x7
\r
853 #define bRxSettle_LNA 0x38
\r
854 #define bRxSettle_RSSI 0x1c0
\r
855 #define bRxSettle_BBP 0xe00
\r
856 #define bRxSettle_RxHP 0x7000
\r
857 #define bRxSettle_AntSW_RSSI 0x38000
\r
858 #define bRxSettle_AntSW 0xc0000
\r
859 #define bRxProcessTime_DAGC 0x300000
\r
860 #define bRxSettle_HSSI 0x400000
\r
861 #define bRxProcessTime_BBPPW 0x800000
\r
862 #define bRxAntennaPowerShift 0x3000000
\r
863 #define bRSSITableSelect 0xc000000
\r
864 #define bRxHP_Final 0x7000000
\r
865 #define bRxHTSettle_BBP 0x7
\r
866 #define bRxHTSettle_HSSI 0x8
\r
867 #define bRxHTSettle_RxHP 0x70
\r
868 #define bRxHTSettle_BBPPW 0x80
\r
869 #define bRxHTSettle_Idle 0x300
\r
870 #define bRxHTSettle_Reserved 0x1c00
\r
871 #define bRxHTRxHPEn 0x8000
\r
872 #define bRxHTAGCFreezeThres 0x30000
\r
873 #define bRxHTAGCTogetherEn 0x40000
\r
874 #define bRxHTAGCMin 0x80000
\r
875 #define bRxHTAGCEn 0x100000
\r
876 #define bRxHTDAGCEn 0x200000
\r
877 #define bRxHTRxHP_BBP 0x1c00000
\r
878 #define bRxHTRxHP_Final 0xe0000000
\r
879 #define bRxPWRatioTH 0x3
\r
880 #define bRxPWRatioEn 0x4
\r
881 #define bRxMFHold 0x3800
\r
882 #define bRxPD_Delay_TH1 0x38
\r
883 #define bRxPD_Delay_TH2 0x1c0
\r
884 #define bRxPD_DC_COUNT_MAX 0x600
\r
885 //#define bRxMF_Hold 0x3800
\r
886 #define bRxPD_Delay_TH 0x8000
\r
887 #define bRxProcess_Delay 0xf0000
\r
888 #define bRxSearchrange_GI2_Early 0x700000
\r
889 #define bRxFrame_Guard_Counter_L 0x3800000
\r
890 #define bRxSGI_Guard_L 0xc000000
\r
891 #define bRxSGI_Search_L 0x30000000
\r
892 #define bRxSGI_TH 0xc0000000
\r
893 #define bDFSCnt0 0xff
\r
894 #define bDFSCnt1 0xff00
\r
895 #define bDFSFlag 0xf0000
\r
896 #define bMFWeightSum 0x300000
\r
897 #define bMinIdxTH 0x7f000000
\r
898 #define bDAFormat 0x40000
\r
899 #define bTxChEmuEnable 0x01000000
\r
900 #define bTRSWIsolation_A 0x7f
\r
901 #define bTRSWIsolation_B 0x7f00
\r
902 #define bTRSWIsolation_C 0x7f0000
\r
903 #define bTRSWIsolation_D 0x7f000000
\r
904 #define bExtLNAGain 0x7c00
\r
907 #define bSTBCEn 0x4 // Useless
\r
908 #define bAntennaMapping 0x10
\r
910 #define bCFOAntSumD 0x200
\r
911 #define bPHYCounterReset 0x8000000
\r
912 #define bCFOReportGet 0x4000000
\r
913 #define bOFDMContinueTx 0x10000000
\r
914 #define bOFDMSingleCarrier 0x20000000
\r
915 #define bOFDMSingleTone 0x40000000
\r
916 //#define bRxPath1 0x01
\r
917 //#define bRxPath2 0x02
\r
918 //#define bRxPath3 0x04
\r
919 //#define bRxPath4 0x08
\r
920 //#define bTxPath1 0x10
\r
921 //#define bTxPath2 0x20
\r
922 #define bHTDetect 0x100
\r
923 #define bCFOEn 0x10000
\r
924 #define bCFOValue 0xfff00000
\r
925 #define bSigTone_Re 0x3f
\r
926 #define bSigTone_Im 0x7f00
\r
927 #define bCounter_CCA 0xffff
\r
928 #define bCounter_ParityFail 0xffff0000
\r
929 #define bCounter_RateIllegal 0xffff
\r
930 #define bCounter_CRC8Fail 0xffff0000
\r
931 #define bCounter_MCSNoSupport 0xffff
\r
932 #define bCounter_FastSync 0xffff
\r
933 #define bShortCFO 0xfff
\r
934 #define bShortCFOTLength 12 //total
\r
935 #define bShortCFOFLength 11 //fraction
\r
936 #define bLongCFO 0x7ff
\r
937 #define bLongCFOTLength 11
\r
938 #define bLongCFOFLength 11
\r
939 #define bTailCFO 0x1fff
\r
940 #define bTailCFOTLength 13
\r
941 #define bTailCFOFLength 12
\r
942 #define bmax_en_pwdB 0xffff
\r
943 #define bCC_power_dB 0xffff0000
\r
944 #define bnoise_pwdB 0xffff
\r
945 #define bPowerMeasTLength 10
\r
946 #define bPowerMeasFLength 3
\r
947 #define bRx_HT_BW 0x1
\r
949 #define bRx_HT 0x8
\r
950 #define bNB_intf_det_on 0x1
\r
951 #define bIntf_win_len_cfg 0x30
\r
952 #define bNB_Intf_TH_cfg 0x1c0
\r
953 #define bRFGain 0x3f
\r
954 #define bTableSel 0x40
\r
955 #define bTRSW 0x80
\r
956 #define bRxSNR_A 0xff
\r
957 #define bRxSNR_B 0xff00
\r
958 #define bRxSNR_C 0xff0000
\r
959 #define bRxSNR_D 0xff000000
\r
960 #define bSNREVMTLength 8
\r
961 #define bSNREVMFLength 1
\r
962 #define bCSI1st 0xff
\r
963 #define bCSI2nd 0xff00
\r
964 #define bRxEVM1st 0xff0000
\r
965 #define bRxEVM2nd 0xff000000
\r
966 #define bSIGEVM 0xff
\r
967 #define bPWDB 0xff00
\r
968 #define bSGIEN 0x10000
\r
970 #define bSFactorQAM1 0xf // Useless
\r
971 #define bSFactorQAM2 0xf0
\r
972 #define bSFactorQAM3 0xf00
\r
973 #define bSFactorQAM4 0xf000
\r
974 #define bSFactorQAM5 0xf0000
\r
975 #define bSFactorQAM6 0xf0000
\r
976 #define bSFactorQAM7 0xf00000
\r
977 #define bSFactorQAM8 0xf000000
\r
978 #define bSFactorQAM9 0xf0000000
\r
979 #define bCSIScheme 0x100000
\r
981 #define bNoiseLvlTopSet 0x3 // Useless
\r
982 #define bChSmooth 0x4
\r
983 #define bChSmoothCfg1 0x38
\r
984 #define bChSmoothCfg2 0x1c0
\r
985 #define bChSmoothCfg3 0xe00
\r
986 #define bChSmoothCfg4 0x7000
\r
987 #define bMRCMode 0x800000
\r
988 #define bTHEVMCfg 0x7000000
\r
990 #define bLoopFitType 0x1 // Useless
\r
991 #define bUpdCFO 0x40
\r
992 #define bUpdCFOOffData 0x80
\r
993 #define bAdvUpdCFO 0x100
\r
994 #define bAdvTimeCtrl 0x800
\r
995 #define bUpdClko 0x1000
\r
997 #define bTrackingMode 0x8000
\r
998 #define bPhCmpEnable 0x10000
\r
999 #define bUpdClkoLTF 0x20000
\r
1000 #define bComChCFO 0x40000
\r
1001 #define bCSIEstiMode 0x80000
\r
1002 #define bAdvUpdEqz 0x100000
\r
1003 #define bUChCfg 0x7000000
\r
1004 #define bUpdEqz 0x8000000
\r
1007 #define bRxPesudoNoiseOn 0x20000000 // Useless
\r
1008 #define bRxPesudoNoise_A 0xff
\r
1009 #define bRxPesudoNoise_B 0xff00
\r
1010 #define bRxPesudoNoise_C 0xff0000
\r
1011 #define bRxPesudoNoise_D 0xff000000
\r
1012 #define bPesudoNoiseState_A 0xffff
\r
1013 #define bPesudoNoiseState_B 0xffff0000
\r
1014 #define bPesudoNoiseState_C 0xffff
\r
1015 #define bPesudoNoiseState_D 0xffff0000
\r
1019 #define bZebra1_HSSIEnable 0x8 // Useless
\r
1020 #define bZebra1_TRxControl 0xc00
\r
1021 #define bZebra1_TRxGainSetting 0x07f
\r
1022 #define bZebra1_RxCorner 0xc00
\r
1023 #define bZebra1_TxChargePump 0x38
\r
1024 #define bZebra1_RxChargePump 0x7
\r
1025 #define bZebra1_ChannelNum 0xf80
\r
1026 #define bZebra1_TxLPFBW 0x400
\r
1027 #define bZebra1_RxLPFBW 0x600
\r
1030 #define bRTL8256RegModeCtrl1 0x100 // Useless
\r
1031 #define bRTL8256RegModeCtrl0 0x40
\r
1032 #define bRTL8256_TxLPFBW 0x18
\r
1033 #define bRTL8256_RxLPFBW 0x600
\r
1036 #define bRTL8258_TxLPFBW 0xc // Useless
\r
1037 #define bRTL8258_RxLPFBW 0xc00
\r
1038 #define bRTL8258_RSSILPFBW 0xc0
\r
1042 // Other Definition
\r
1045 //byte endable for sb_write
\r
1046 #define bByte0 0x1 // Useless
\r
1047 #define bByte1 0x2
\r
1048 #define bByte2 0x4
\r
1049 #define bByte3 0x8
\r
1050 #define bWord0 0x3
\r
1051 #define bWord1 0xc
\r
1052 #define bDWord 0xf
\r
1054 //for PutRegsetting & GetRegSetting BitMask
\r
1055 #define bMaskByte0 0xff // Reg 0xc50 rOFDM0_XAAGCCore~0xC6f
\r
1056 #define bMaskByte1 0xff00
\r
1057 #define bMaskByte2 0xff0000
\r
1058 #define bMaskByte3 0xff000000
\r
1059 #define bMaskHWord 0xffff0000
\r
1060 #define bMaskLWord 0x0000ffff
\r
1061 #define bMaskDWord 0xffffffff
\r
1062 #define bMaskH3Bytes 0xffffff00
\r
1063 #define bMask12Bits 0xfff
\r
1064 #define bMaskH4Bits 0xf0000000
\r
1065 #define bMaskOFDM_D 0xffc00000
\r
1066 #define bMaskCCK 0x3f3f3f3f
\r
1070 #define bEnable 0x1 // Useless
\r
1071 #define bDisable 0x0
\r
1073 #define LeftAntenna 0x0 // Useless
\r
1074 #define RightAntenna 0x1
\r
1076 #define tCheckTxStatus 500 //500ms // Useless
\r
1077 #define tUpdateRxCounter 100 //100ms
\r
1079 #define rateCCK 0 // Useless
\r
1080 #define rateOFDM 1
\r
1083 //define Register-End
\r
1084 #define bPMAC_End 0x1ff // Useless
\r
1085 #define bFPGAPHY0_End 0x8ff
\r
1086 #define bFPGAPHY1_End 0x9ff
\r
1087 #define bCCKPHY0_End 0xaff
\r
1088 #define bOFDMPHY0_End 0xcff
\r
1089 #define bOFDMPHY1_End 0xdff
\r
1091 //define max debug item in each debug page
\r
1092 //#define bMaxItem_FPGA_PHY0 0x9
\r
1093 //#define bMaxItem_FPGA_PHY1 0x3
\r
1094 //#define bMaxItem_PHY_11B 0x16
\r
1095 //#define bMaxItem_OFDM_PHY0 0x29
\r
1096 //#define bMaxItem_OFDM_PHY1 0x0
\r
1098 #define bPMACControl 0x0 // Useless
\r
1099 #define bWMACControl 0x1
\r
1100 #define bWNICControl 0x2
\r
1102 #define PathA 0x0 // Useless
\r
1107 /*--------------------------Define Parameters-------------------------------*/
\r
projects / firefly-linux-kernel-4.4.55.git / blob