1 /******************************************************************************
3 * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
19 ******************************************************************************/
20 /*****************************************************************************
22 * Module: __INC_HAL8192CPHYREG_H
25 * Note: 1. Define PMAC/BB register map
26 * 2. Define RF register map
27 * 3. PMAC/BB register bit mask.
29 * 5. Other BB/RF relative definition.
32 * Export: Constants, macro, functions(API), global variables(None).
38 * 08/07/2007 MHC 1. Porting from 9x series PHYCFG.h.
39 * 2. Reorganize code architecture.
40 * 09/25/2008 MH 1. Add RL6052 register definition
42 *****************************************************************************/
43 #ifndef __INC_HAL8192CPHYREG_H
44 #define __INC_HAL8192CPHYREG_H
47 /*--------------------------Define Parameters-------------------------------*/
49 //============================================================
50 // 8192S Regsiter offset definition
51 //============================================================
54 // BB-PHY register PMAC 0x100 PHY 0x800 - 0xEFF
55 // 1. PMAC duplicate register due to connection: RF_Mode, TRxRN, NumOf L-STF
56 // 2. 0x800/0x900/0xA00/0xC00/0xD00/0xE00
57 // 3. RF register 0x00-2E
58 // 4. Bit Mask for BB/RF register
59 // 5. Other defintion for BB/RF R/W
64 // 1. PMAC duplicate register due to connection: RF_Mode, TRxRN, NumOf L-STF
67 #define rPMAC_Reset 0x100
68 #define rPMAC_TxStart 0x104
69 #define rPMAC_TxLegacySIG 0x108
70 #define rPMAC_TxHTSIG1 0x10c
71 #define rPMAC_TxHTSIG2 0x110
72 #define rPMAC_PHYDebug 0x114
73 #define rPMAC_TxPacketNum 0x118
74 #define rPMAC_TxIdle 0x11c
75 #define rPMAC_TxMACHeader0 0x120
76 #define rPMAC_TxMACHeader1 0x124
77 #define rPMAC_TxMACHeader2 0x128
78 #define rPMAC_TxMACHeader3 0x12c
79 #define rPMAC_TxMACHeader4 0x130
80 #define rPMAC_TxMACHeader5 0x134
81 #define rPMAC_TxDataType 0x138
82 #define rPMAC_TxRandomSeed 0x13c
83 #define rPMAC_CCKPLCPPreamble 0x140
84 #define rPMAC_CCKPLCPHeader 0x144
85 #define rPMAC_CCKCRC16 0x148
86 #define rPMAC_OFDMRxCRC32OK 0x170
87 #define rPMAC_OFDMRxCRC32Er 0x174
88 #define rPMAC_OFDMRxParityEr 0x178
89 #define rPMAC_OFDMRxCRC8Er 0x17c
90 #define rPMAC_CCKCRxRC16Er 0x180
91 #define rPMAC_CCKCRxRC32Er 0x184
92 #define rPMAC_CCKCRxRC32OK 0x188
93 #define rPMAC_TxStatus 0x18c
98 // The following two definition are only used for USB interface.
99 #define RF_BB_CMD_ADDR 0x02c0 // RF/BB read/write command address.
100 #define RF_BB_CMD_DATA 0x02c4 // RF/BB read/write command data.
105 #define rFPGA0_RFMOD 0x800 //RF mode & CCK TxSC // RF BW Setting??
107 #define rFPGA0_TxInfo 0x804 // Status report??
108 #define rFPGA0_PSDFunction 0x808
110 #define rFPGA0_TxGainStage 0x80c // Set TX PWR init gain?
112 #define rFPGA0_RFTiming1 0x810 // Useless now
113 #define rFPGA0_RFTiming2 0x814
115 #define rFPGA0_XA_HSSIParameter1 0x820 // RF 3 wire register
116 #define rFPGA0_XA_HSSIParameter2 0x824
117 #define rFPGA0_XB_HSSIParameter1 0x828
118 #define rFPGA0_XB_HSSIParameter2 0x82c
119 #define rTxAGC_B_Rate18_06 0x830
120 #define rTxAGC_B_Rate54_24 0x834
121 #define rTxAGC_B_CCK1_55_Mcs32 0x838
122 #define rTxAGC_B_Mcs03_Mcs00 0x83c
124 #define rTxAGC_B_Mcs07_Mcs04 0x848
125 #define rTxAGC_B_Mcs11_Mcs08 0x84c
127 #define rFPGA0_XA_LSSIParameter 0x840
128 #define rFPGA0_XB_LSSIParameter 0x844
130 #define rFPGA0_RFWakeUpParameter 0x850 // Useless now
131 #define rFPGA0_RFSleepUpParameter 0x854
133 #define rFPGA0_XAB_SwitchControl 0x858 // RF Channel switch
134 #define rFPGA0_XCD_SwitchControl 0x85c
136 #define rFPGA0_XA_RFInterfaceOE 0x860 // RF Channel switch
137 #define rFPGA0_XB_RFInterfaceOE 0x864
139 #define rTxAGC_B_Mcs15_Mcs12 0x868
140 #define rTxAGC_B_CCK11_A_CCK2_11 0x86c
142 #define rFPGA0_XAB_RFInterfaceSW 0x870 // RF Interface Software Control
143 #define rFPGA0_XCD_RFInterfaceSW 0x874
145 #define rFPGA0_XAB_RFParameter 0x878 // RF Parameter
146 #define rFPGA0_XCD_RFParameter 0x87c
148 #define rFPGA0_AnalogParameter1 0x880 // Crystal cap setting RF-R/W protection for parameter4??
149 #define rFPGA0_AnalogParameter2 0x884
150 #define rFPGA0_AnalogParameter3 0x888 // Useless now
151 #define rFPGA0_AnalogParameter4 0x88c
153 #define rFPGA0_XA_LSSIReadBack 0x8a0 // Tranceiver LSSI Readback
154 #define rFPGA0_XB_LSSIReadBack 0x8a4
155 #define rFPGA0_XC_LSSIReadBack 0x8a8
156 #define rFPGA0_XD_LSSIReadBack 0x8ac
158 #define rFPGA0_PSDReport 0x8b4 // Useless now
159 #define TransceiverA_HSPI_Readback 0x8b8 // Transceiver A HSPI Readback
160 #define TransceiverB_HSPI_Readback 0x8bc // Transceiver B HSPI Readback
161 #define rFPGA0_XAB_RFInterfaceRB 0x8e0 // Useless now // RF Interface Readback Value
162 #define rFPGA0_XCD_RFInterfaceRB 0x8e4 // Useless now
167 #define rFPGA1_RFMOD 0x900 //RF mode & OFDM TxSC // RF BW Setting??
169 #define rFPGA1_TxBlock 0x904 // Useless now
170 #define rFPGA1_DebugSelect 0x908 // Useless now
171 #define rFPGA1_TxInfo 0x90c // Useless now // Status report??
172 #define rS0S1_PathSwitch 0x948
177 // Set Control channel to upper or lower. These settings are required only for 40MHz
178 #define rCCK0_System 0xa00
180 #define rCCK0_AFESetting 0xa04 // Disable init gain now // Select RX path by RSSI
181 #define rCCK0_CCA 0xa08 // Disable init gain now // Init gain
183 #define rCCK0_RxAGC1 0xa0c //AGC default value, saturation level // Antenna Diversity, RX AGC, LNA Threshold, RX LNA Threshold useless now. Not the same as 90 series
184 #define rCCK0_RxAGC2 0xa10 //AGC & DAGC
186 #define rCCK0_RxHP 0xa14
188 #define rCCK0_DSPParameter1 0xa18 //Timing recovery & Channel estimation threshold
189 #define rCCK0_DSPParameter2 0xa1c //SQ threshold
191 #define rCCK0_TxFilter1 0xa20
192 #define rCCK0_TxFilter2 0xa24
193 #define rCCK0_DebugPort 0xa28 //debug port and Tx filter3
194 #define rCCK0_FalseAlarmReport 0xa2c //0xa2d useless now 0xa30-a4f channel report
195 #define rCCK0_TRSSIReport 0xa50
196 #define rCCK0_RxReport 0xa54 //0xa57
197 #define rCCK0_FACounterLower 0xa5c //0xa5b
198 #define rCCK0_FACounterUpper 0xa58 //0xa5c
202 #define rPdp_AntA 0xb00
203 #define rPdp_AntA_4 0xb04
204 #define rConfig_Pmpd_AntA 0xb28
205 #define rConfig_AntA 0xb68
206 #define rConfig_AntB 0xb6c
207 #define rPdp_AntB 0xb70
208 #define rPdp_AntB_4 0xb74
209 #define rConfig_Pmpd_AntB 0xb98
215 #define rOFDM0_LSTF 0xc00
217 #define rOFDM0_TRxPathEnable 0xc04
218 #define rOFDM0_TRMuxPar 0xc08
219 #define rOFDM0_TRSWIsolation 0xc0c
221 #define rOFDM0_XARxAFE 0xc10 //RxIQ DC offset, Rx digital filter, DC notch filter
222 #define rOFDM0_XARxIQImbalance 0xc14 //RxIQ imblance matrix
223 #define rOFDM0_XBRxAFE 0xc18
224 #define rOFDM0_XBRxIQImbalance 0xc1c
225 #define rOFDM0_XCRxAFE 0xc20
226 #define rOFDM0_XCRxIQImbalance 0xc24
227 #define rOFDM0_XDRxAFE 0xc28
228 #define rOFDM0_XDRxIQImbalance 0xc2c
230 #define rOFDM0_RxDetector1 0xc30 //PD,BW & SBD // DM tune init gain
231 #define rOFDM0_RxDetector2 0xc34 //SBD & Fame Sync.
232 #define rOFDM0_RxDetector3 0xc38 //Frame Sync.
233 #define rOFDM0_RxDetector4 0xc3c //PD, SBD, Frame Sync & Short-GI
235 #define rOFDM0_RxDSP 0xc40 //Rx Sync Path
236 #define rOFDM0_CFOandDAGC 0xc44 //CFO & DAGC
237 #define rOFDM0_CCADropThreshold 0xc48 //CCA Drop threshold
238 #define rOFDM0_ECCAThreshold 0xc4c // energy CCA
240 #define rOFDM0_XAAGCCore1 0xc50 // DIG
241 #define rOFDM0_XAAGCCore2 0xc54
242 #define rOFDM0_XBAGCCore1 0xc58
243 #define rOFDM0_XBAGCCore2 0xc5c
244 #define rOFDM0_XCAGCCore1 0xc60
245 #define rOFDM0_XCAGCCore2 0xc64
246 #define rOFDM0_XDAGCCore1 0xc68
247 #define rOFDM0_XDAGCCore2 0xc6c
249 #define rOFDM0_AGCParameter1 0xc70
250 #define rOFDM0_AGCParameter2 0xc74
251 #define rOFDM0_AGCRSSITable 0xc78
252 #define rOFDM0_HTSTFAGC 0xc7c
254 #define rOFDM0_XATxIQImbalance 0xc80 // TX PWR TRACK and DIG
255 #define rOFDM0_XATxAFE 0xc84
256 #define rOFDM0_XBTxIQImbalance 0xc88
257 #define rOFDM0_XBTxAFE 0xc8c
258 #define rOFDM0_XCTxIQImbalance 0xc90
259 #define rOFDM0_XCTxAFE 0xc94
260 #define rOFDM0_XDTxIQImbalance 0xc98
261 #define rOFDM0_XDTxAFE 0xc9c
263 #define rOFDM0_RxIQExtAnta 0xca0
264 #define rOFDM0_TxCoeff1 0xca4
265 #define rOFDM0_TxCoeff2 0xca8
266 #define rOFDM0_TxCoeff3 0xcac
267 #define rOFDM0_TxCoeff4 0xcb0
268 #define rOFDM0_TxCoeff5 0xcb4
269 #define rOFDM0_TxCoeff6 0xcb8
270 #define rOFDM0_RxHPParameter 0xce0
271 #define rOFDM0_TxPseudoNoiseWgt 0xce4
272 #define rOFDM0_FrameSync 0xcf0
273 #define rOFDM0_DFSReport 0xcf4
278 #define rOFDM1_LSTF 0xd00
279 #define rOFDM1_TRxPathEnable 0xd04
281 #define rOFDM1_CFO 0xd08 // No setting now
282 #define rOFDM1_CSI1 0xd10
283 #define rOFDM1_SBD 0xd14
284 #define rOFDM1_CSI2 0xd18
285 #define rOFDM1_CFOTracking 0xd2c
286 #define rOFDM1_TRxMesaure1 0xd34
287 #define rOFDM1_IntfDet 0xd3c
288 #define rOFDM1_PseudoNoiseStateAB 0xd50
289 #define rOFDM1_PseudoNoiseStateCD 0xd54
290 #define rOFDM1_RxPseudoNoiseWgt 0xd58
292 #define rOFDM_PHYCounter1 0xda0 //cca, parity fail
293 #define rOFDM_PHYCounter2 0xda4 //rate illegal, crc8 fail
294 #define rOFDM_PHYCounter3 0xda8 //MCS not support
296 #define rOFDM_ShortCFOAB 0xdac // No setting now
297 #define rOFDM_ShortCFOCD 0xdb0
298 #define rOFDM_LongCFOAB 0xdb4
299 #define rOFDM_LongCFOCD 0xdb8
300 #define rOFDM_TailCFOAB 0xdbc
301 #define rOFDM_TailCFOCD 0xdc0
302 #define rOFDM_PWMeasure1 0xdc4
303 #define rOFDM_PWMeasure2 0xdc8
304 #define rOFDM_BWReport 0xdcc
305 #define rOFDM_AGCReport 0xdd0
306 #define rOFDM_RxSNR 0xdd4
307 #define rOFDM_RxEVMCSI 0xdd8
308 #define rOFDM_SIGReport 0xddc
314 #define rTxAGC_A_Rate18_06 0xe00
315 #define rTxAGC_A_Rate54_24 0xe04
316 #define rTxAGC_A_CCK1_Mcs32 0xe08
317 #define rTxAGC_A_Mcs03_Mcs00 0xe10
318 #define rTxAGC_A_Mcs07_Mcs04 0xe14
319 #define rTxAGC_A_Mcs11_Mcs08 0xe18
320 #define rTxAGC_A_Mcs15_Mcs12 0xe1c
322 #define rFPGA0_IQK 0xe28
323 #define rTx_IQK_Tone_A 0xe30
324 #define rRx_IQK_Tone_A 0xe34
325 #define rTx_IQK_PI_A 0xe38
326 #define rRx_IQK_PI_A 0xe3c
328 #define rTx_IQK 0xe40
329 #define rRx_IQK 0xe44
330 #define rIQK_AGC_Pts 0xe48
331 #define rIQK_AGC_Rsp 0xe4c
332 #define rTx_IQK_Tone_B 0xe50
333 #define rRx_IQK_Tone_B 0xe54
334 #define rTx_IQK_PI_B 0xe58
335 #define rRx_IQK_PI_B 0xe5c
336 #define rIQK_AGC_Cont 0xe60
338 #define rBlue_Tooth 0xe6c
339 #define rRx_Wait_CCA 0xe70
340 #define rTx_CCK_RFON 0xe74
341 #define rTx_CCK_BBON 0xe78
342 #define rTx_OFDM_RFON 0xe7c
343 #define rTx_OFDM_BBON 0xe80
344 #define rTx_To_Rx 0xe84
345 #define rTx_To_Tx 0xe88
346 #define rRx_CCK 0xe8c
348 #define rTx_Power_Before_IQK_A 0xe94
349 #define rTx_Power_After_IQK_A 0xe9c
351 #define rRx_Power_Before_IQK_A 0xea0
352 #define rRx_Power_Before_IQK_A_2 0xea4
353 #define rRx_Power_After_IQK_A 0xea8
354 #define rRx_Power_After_IQK_A_2 0xeac
356 #define rTx_Power_Before_IQK_B 0xeb4
357 #define rTx_Power_After_IQK_B 0xebc
359 #define rRx_Power_Before_IQK_B 0xec0
360 #define rRx_Power_Before_IQK_B_2 0xec4
361 #define rRx_Power_After_IQK_B 0xec8
362 #define rRx_Power_After_IQK_B_2 0xecc
364 #define rRx_OFDM 0xed0
365 #define rRx_Wait_RIFS 0xed4
366 #define rRx_TO_Rx 0xed8
367 #define rStandby 0xedc
369 #define rPMPD_ANAEN 0xeec
372 // 7. RF Register 0x00-0x2E (RF 8256)
376 #define rZebra1_HSSIEnable 0x0 // Useless now
377 #define rZebra1_TRxEnable1 0x1
378 #define rZebra1_TRxEnable2 0x2
379 #define rZebra1_AGC 0x4
380 #define rZebra1_ChargePump 0x5
381 #define rZebra1_Channel 0x7 // RF channel switch
384 #define rZebra1_TxGain 0x8 // Useless now
385 #define rZebra1_TxLPF 0x9
386 #define rZebra1_RxLPF 0xb
387 #define rZebra1_RxHPFCorner 0xc
390 #define rGlobalCtrl 0 // Useless now
391 #define rRTL8256_TxLPF 19
392 #define rRTL8256_RxLPF 11
395 #define rRTL8258_TxLPF 0x11 // Useless now
396 #define rRTL8258_RxLPF 0x13
397 #define rRTL8258_RSSILPF 0xa
400 // RL6052 Register definition
402 #define RF_AC 0x00 //
404 #define RF_IQADJ_G1 0x01 //
405 #define RF_IQADJ_G2 0x02 //
406 #define RF_BS_PA_APSET_G1_G4 0x03
407 #define RF_BS_PA_APSET_G5_G8 0x04
408 #define RF_POW_TRSW 0x05 //
410 #define RF_GAIN_RX 0x06 //
411 #define RF_GAIN_TX 0x07 //
413 #define RF_TXM_IDAC 0x08 //
414 #define RF_IPA_G 0x09 //
415 #define RF_TXBIAS_G 0x0A
416 #define RF_TXPA_AG 0x0B
417 #define RF_IPA_A 0x0C //
418 #define RF_TXBIAS_A 0x0D
419 #define RF_BS_PA_APSET_G9_G11 0x0E
420 #define RF_BS_IQGEN 0x0F //
422 #define RF_MODE1 0x10 //
423 #define RF_MODE2 0x11 //
425 #define RF_RX_AGC_HP 0x12 //
426 #define RF_TX_AGC 0x13 //
427 #define RF_BIAS 0x14 //
428 #define RF_IPA 0x15 //
429 #define RF_TXBIAS 0x16 //
430 #define RF_POW_ABILITY 0x17 //
431 #define RF_MODE_AG 0x18 //
432 #define rRfChannel 0x18 // RF channel and BW switch
433 #define RF_CHNLBW 0x18 // RF channel and BW switch
434 #define RF_TOP 0x19 //
436 #define RF_RX_G1 0x1A //
437 #define RF_RX_G2 0x1B //
439 #define RF_RX_BB2 0x1C //
440 #define RF_RX_BB1 0x1D //
442 #define RF_RCK1 0x1E //
443 #define RF_RCK2 0x1F //
445 #define RF_TX_G1 0x20 //
446 #define RF_TX_G2 0x21 //
447 #define RF_TX_G3 0x22 //
449 #define RF_TX_BB1 0x23 //
451 #define RF_T_METER 0x24 //
453 #define RF_SYN_G1 0x25 // RF TX Power control
454 #define RF_SYN_G2 0x26 // RF TX Power control
455 #define RF_SYN_G3 0x27 // RF TX Power control
456 #define RF_SYN_G4 0x28 // RF TX Power control
457 #define RF_SYN_G5 0x29 // RF TX Power control
458 #define RF_SYN_G6 0x2A // RF TX Power control
459 #define RF_SYN_G7 0x2B // RF TX Power control
460 #define RF_SYN_G8 0x2C // RF TX Power control
462 #define RF_RCK_OS 0x30 // RF TX PA control
464 #define RF_TXPA_G1 0x31 // RF TX PA control
465 #define RF_TXPA_G2 0x32 // RF TX PA control
466 #define RF_TXPA_G3 0x33 // RF TX PA control
467 #define RF_TX_BIAS_A 0x35
468 #define RF_TX_BIAS_D 0x36
469 #define RF_LOBF_9 0x38
470 #define RF_RXRF_A3 0x3C //
473 #define RF_TXRF_A2 0x41
474 #define RF_TXPA_G4 0x46
475 #define RF_TXPA_A4 0x4B
477 #define RF_WE_LUT 0xEF
484 #define bBBResetB 0x100 // Useless now?
485 #define bGlobalResetB 0x200
486 #define bOFDMTxStart 0x4
487 #define bCCKTxStart 0x8
488 #define bCRC32Debug 0x100
489 #define bPMACLoopback 0x10
490 #define bTxLSIG 0xffffff
491 #define bOFDMTxRate 0xf
492 #define bOFDMTxReserved 0x10
493 #define bOFDMTxLength 0x1ffe0
494 #define bOFDMTxParity 0x20000
495 #define bTxHTSIG1 0xffffff
496 #define bTxHTMCSRate 0x7f
498 #define bTxHTLength 0xffff00
499 #define bTxHTSIG2 0xffffff
500 #define bTxHTSmoothing 0x1
501 #define bTxHTSounding 0x2
502 #define bTxHTReserved 0x4
503 #define bTxHTAggreation 0x8
504 #define bTxHTSTBC 0x30
505 #define bTxHTAdvanceCoding 0x40
506 #define bTxHTShortGI 0x80
507 #define bTxHTNumberHT_LTF 0x300
508 #define bTxHTCRC8 0x3fc00
509 #define bCounterReset 0x10000
510 #define bNumOfOFDMTx 0xffff
511 #define bNumOfCCKTx 0xffff0000
512 #define bTxIdleInterval 0xffff
513 #define bOFDMService 0xffff0000
514 #define bTxMACHeader 0xffffffff
515 #define bTxDataInit 0xff
516 #define bTxHTMode 0x100
517 #define bTxDataType 0x30000
518 #define bTxRandomSeed 0xffffffff
519 #define bCCKTxPreamble 0x1
520 #define bCCKTxSFD 0xffff0000
521 #define bCCKTxSIG 0xff
522 #define bCCKTxService 0xff00
523 #define bCCKLengthExt 0x8000
524 #define bCCKTxLength 0xffff0000
525 #define bCCKTxCRC16 0xffff
526 #define bCCKTxStatus 0x1
527 #define bOFDMTxStatus 0x2
529 #define IS_BB_REG_OFFSET_92S(_Offset) ((_Offset >= 0x800) && (_Offset <= 0xfff))
532 #define bRFMOD 0x1 // Reg 0x800 rFPGA0_RFMOD
533 #define bJapanMode 0x2
534 #define bCCKTxSC 0x30
535 #define bCCKEn 0x1000000
536 #define bOFDMEn 0x2000000
538 #define bOFDMRxADCPhase 0x10000 // Useless now
539 #define bOFDMTxDACPhase 0x40000
540 #define bXATxAGC 0x3f
542 #define bAntennaSelect 0x0300
544 #define bXBTxAGC 0xf00 // Reg 80c rFPGA0_TxGainStage
545 #define bXCTxAGC 0xf000
546 #define bXDTxAGC 0xf0000
548 #define bPAStart 0xf0000000 // Useless now
549 #define bTRStart 0x00f00000
550 #define bRFStart 0x0000f000
551 #define bBBStart 0x000000f0
552 #define bBBCCKStart 0x0000000f
553 #define bPAEnd 0xf //Reg0x814
554 #define bTREnd 0x0f000000
555 #define bRFEnd 0x000f0000
556 #define bCCAMask 0x000000f0 //T2R
557 #define bR2RCCAMask 0x00000f00
558 #define bHSSI_R2TDelay 0xf8000000
559 #define bHSSI_T2RDelay 0xf80000
560 #define bContTxHSSI 0x400 //chane gain at continue Tx
561 #define bIGFromCCK 0x200
562 #define bAGCAddress 0x3f
563 #define bRxHPTx 0x7000
564 #define bRxHPT2R 0x38000
565 #define bRxHPCCKIni 0xc0000
566 #define bAGCTxCode 0xc00000
567 #define bAGCRxCode 0x300000
569 #define b3WireDataLength 0x800 // Reg 0x820~84f rFPGA0_XA_HSSIParameter1
570 #define b3WireAddressLength 0x400
572 #define b3WireRFPowerDown 0x1 // Useless now
573 //#define bHWSISelect 0x8
574 #define b5GPAPEPolarity 0x40000000
575 #define b2GPAPEPolarity 0x80000000
576 #define bRFSW_TxDefaultAnt 0x3
577 #define bRFSW_TxOptionAnt 0x30
578 #define bRFSW_RxDefaultAnt 0x300
579 #define bRFSW_RxOptionAnt 0x3000
580 #define bRFSI_3WireData 0x1
581 #define bRFSI_3WireClock 0x2
582 #define bRFSI_3WireLoad 0x4
583 #define bRFSI_3WireRW 0x8
584 #define bRFSI_3Wire 0xf
586 #define bRFSI_RFENV 0x10 // Reg 0x870 rFPGA0_XAB_RFInterfaceSW
588 #define bRFSI_TRSW 0x20 // Useless now
589 #define bRFSI_TRSWB 0x40
590 #define bRFSI_ANTSW 0x100
591 #define bRFSI_ANTSWB 0x200
592 #define bRFSI_PAPE 0x400
593 #define bRFSI_PAPE5G 0x800
594 #define bBandSelect 0x1
595 #define bHTSIG2_GI 0x80
596 #define bHTSIG2_Smoothing 0x01
597 #define bHTSIG2_Sounding 0x02
598 #define bHTSIG2_Aggreaton 0x08
599 #define bHTSIG2_STBC 0x30
600 #define bHTSIG2_AdvCoding 0x40
601 #define bHTSIG2_NumOfHTLTF 0x300
602 #define bHTSIG2_CRC8 0x3fc
603 #define bHTSIG1_MCS 0x7f
604 #define bHTSIG1_BandWidth 0x80
605 #define bHTSIG1_HTLength 0xffff
606 #define bLSIG_Rate 0xf
607 #define bLSIG_Reserved 0x10
608 #define bLSIG_Length 0x1fffe
609 #define bLSIG_Parity 0x20
610 #define bCCKRxPhase 0x4
612 #define bLSSIReadAddress 0x7f800000 // T65 RF
614 #define bLSSIReadEdge 0x80000000 //LSSI "Read" edge signal
616 #define bLSSIReadBackData 0xfffff // T65 RF
618 #define bLSSIReadOKFlag 0x1000 // Useless now
619 #define bCCKSampleRate 0x8 //0: 44MHz, 1:88MHz
620 #define bRegulator0Standby 0x1
621 #define bRegulatorPLLStandby 0x2
622 #define bRegulator1Standby 0x4
623 #define bPLLPowerUp 0x8
624 #define bDPLLPowerUp 0x10
625 #define bDA10PowerUp 0x20
626 #define bAD7PowerUp 0x200
627 #define bDA6PowerUp 0x2000
628 #define bXtalPowerUp 0x4000
629 #define b40MDClkPowerUP 0x8000
630 #define bDA6DebugMode 0x20000
631 #define bDA6Swing 0x380000
633 #define bADClkPhase 0x4000000 // Reg 0x880 rFPGA0_AnalogParameter1 20/40 CCK support switch 40/80 BB MHZ
635 #define b80MClkDelay 0x18000000 // Useless
636 #define bAFEWatchDogEnable 0x20000000
638 #define bXtalCap01 0xc0000000 // Reg 0x884 rFPGA0_AnalogParameter2 Crystal cap
639 #define bXtalCap23 0x3
640 #define bXtalCap92x 0x0f000000
641 #define bXtalCap 0x0f000000
643 #define bIntDifClkEnable 0x400 // Useless
644 #define bExtSigClkEnable 0x800
645 #define bBandgapMbiasPowerUp 0x10000
646 #define bAD11SHGain 0xc0000
647 #define bAD11InputRange 0x700000
648 #define bAD11OPCurrent 0x3800000
649 #define bIPathLoopback 0x4000000
650 #define bQPathLoopback 0x8000000
651 #define bAFELoopback 0x10000000
652 #define bDA10Swing 0x7e0
653 #define bDA10Reverse 0x800
654 #define bDAClkSource 0x1000
655 #define bAD7InputRange 0x6000
656 #define bAD7Gain 0x38000
657 #define bAD7OutputCMMode 0x40000
658 #define bAD7InputCMMode 0x380000
659 #define bAD7Current 0xc00000
660 #define bRegulatorAdjust 0x7000000
661 #define bAD11PowerUpAtTx 0x1
662 #define bDA10PSAtTx 0x10
663 #define bAD11PowerUpAtRx 0x100
664 #define bDA10PSAtRx 0x1000
665 #define bCCKRxAGCFormat 0x200
666 #define bPSDFFTSamplepPoint 0xc000
667 #define bPSDAverageNum 0x3000
668 #define bIQPathControl 0xc00
669 #define bPSDFreq 0x3ff
670 #define bPSDAntennaPath 0x30
671 #define bPSDIQSwitch 0x40
672 #define bPSDRxTrigger 0x400000
673 #define bPSDTxTrigger 0x80000000
674 #define bPSDSineToneScale 0x7f000000
675 #define bPSDReport 0xffff
678 #define bOFDMTxSC 0x30000000 // Useless
680 #define bOFDMTxOn 0x2
681 #define bDebugPage 0xfff //reset debug page and also HWord, LWord
682 #define bDebugItem 0xff //reset debug page and LWord
684 #define bAntNonHT 0x100
685 #define bAntHT1 0x1000
686 #define bAntHT2 0x10000
687 #define bAntHT1S1 0x100000
688 #define bAntNonHTS1 0x1000000
691 #define bCCKBBMode 0x3 // Useless
692 #define bCCKTxPowerSaving 0x80
693 #define bCCKRxPowerSaving 0x40
695 #define bCCKSideBand 0x10 // Reg 0xa00 rCCK0_System 20/40 switch
697 #define bCCKScramble 0x8 // Useless
698 #define bCCKAntDiversity 0x8000
699 #define bCCKCarrierRecovery 0x4000
700 #define bCCKTxRate 0x3000
701 #define bCCKDCCancel 0x0800
702 #define bCCKISICancel 0x0400
703 #define bCCKMatchFilter 0x0200
704 #define bCCKEqualizer 0x0100
705 #define bCCKPreambleDetect 0x800000
706 #define bCCKFastFalseCCA 0x400000
707 #define bCCKChEstStart 0x300000
708 #define bCCKCCACount 0x080000
709 #define bCCKcs_lim 0x070000
710 #define bCCKBistMode 0x80000000
711 #define bCCKCCAMask 0x40000000
712 #define bCCKTxDACPhase 0x4
713 #define bCCKRxADCPhase 0x20000000 //r_rx_clk
714 #define bCCKr_cp_mode0 0x0100
715 #define bCCKTxDCOffset 0xf0
716 #define bCCKRxDCOffset 0xf
717 #define bCCKCCAMode 0xc000
718 #define bCCKFalseCS_lim 0x3f00
719 #define bCCKCS_ratio 0xc00000
720 #define bCCKCorgBit_sel 0x300000
721 #define bCCKPD_lim 0x0f0000
722 #define bCCKNewCCA 0x80000000
723 #define bCCKRxHPofIG 0x8000
724 #define bCCKRxIG 0x7f00
725 #define bCCKLNAPolarity 0x800000
726 #define bCCKRx1stGain 0x7f0000
727 #define bCCKRFExtend 0x20000000 //CCK Rx Iinital gain polarity
728 #define bCCKRxAGCSatLevel 0x1f000000
729 #define bCCKRxAGCSatCount 0xe0
730 #define bCCKRxRFSettle 0x1f //AGCsamp_dly
731 #define bCCKFixedRxAGC 0x8000
732 //#define bCCKRxAGCFormat 0x4000 //remove to HSSI register 0x824
733 #define bCCKAntennaPolarity 0x2000
734 #define bCCKTxFilterType 0x0c00
735 #define bCCKRxAGCReportType 0x0300
736 #define bCCKRxDAGCEn 0x80000000
737 #define bCCKRxDAGCPeriod 0x20000000
738 #define bCCKRxDAGCSatLevel 0x1f000000
739 #define bCCKTimingRecovery 0x800000
740 #define bCCKTxC0 0x3f0000
741 #define bCCKTxC1 0x3f000000
742 #define bCCKTxC2 0x3f
743 #define bCCKTxC3 0x3f00
744 #define bCCKTxC4 0x3f0000
745 #define bCCKTxC5 0x3f000000
746 #define bCCKTxC6 0x3f
747 #define bCCKTxC7 0x3f00
748 #define bCCKDebugPort 0xff0000
749 #define bCCKDACDebug 0x0f000000
750 #define bCCKFalseAlarmEnable 0x8000
751 #define bCCKFalseAlarmRead 0x4000
752 #define bCCKTRSSI 0x7f
753 #define bCCKRxAGCReport 0xfe
754 #define bCCKRxReport_AntSel 0x80000000
755 #define bCCKRxReport_MFOff 0x40000000
756 #define bCCKRxRxReport_SQLoss 0x20000000
757 #define bCCKRxReport_Pktloss 0x10000000
758 #define bCCKRxReport_Lockedbit 0x08000000
759 #define bCCKRxReport_RateError 0x04000000
760 #define bCCKRxReport_RxRate 0x03000000
761 #define bCCKRxFACounterLower 0xff
762 #define bCCKRxFACounterUpper 0xff000000
763 #define bCCKRxHPAGCStart 0xe000
764 #define bCCKRxHPAGCFinal 0x1c00
765 #define bCCKRxFalseAlarmEnable 0x8000
766 #define bCCKFACounterFreeze 0x4000
767 #define bCCKTxPathSel 0x10000000
768 #define bCCKDefaultRxPath 0xc000000
769 #define bCCKOptionRxPath 0x3000000
772 #define bNumOfSTF 0x3 // Useless
773 #define bShift_L 0xc0
783 #define bTRSSIFreq 0x200
784 #define bADCBackoff 0x3000
785 #define bDFIRBackoff 0xc000
786 #define bTRSSILatchPhase 0x10000
787 #define bRxIDCOffset 0xff
788 #define bRxQDCOffset 0xff00
789 #define bRxDFIRMode 0x1800000
790 #define bRxDCNFType 0xe000000
791 #define bRXIQImb_A 0x3ff
792 #define bRXIQImb_B 0xfc00
793 #define bRXIQImb_C 0x3f0000
794 #define bRXIQImb_D 0xffc00000
795 #define bDC_dc_Notch 0x60000
796 #define bRxNBINotch 0x1f000000
798 #define bPD_TH_Opt2 0xc000
799 #define bPWED_TH 0x700
800 #define bIfMF_Win_L 0x800
801 #define bPD_Option 0x1000
802 #define bMF_Win_L 0xe000
803 #define bBW_Search_L 0x30000
804 #define bwin_enh_L 0xc0000
805 #define bBW_TH 0x700000
806 #define bED_TH2 0x3800000
807 #define bBW_option 0x4000000
808 #define bRatio_TH 0x18000000
809 #define bWindow_L 0xe0000000
810 #define bSBD_Option 0x1
811 #define bFrame_TH 0x1c
812 #define bFS_Option 0x60
813 #define bDC_Slope_check 0x80
814 #define bFGuard_Counter_DC_L 0xe00
815 #define bFrame_Weight_Short 0x7000
816 #define bSub_Tune 0xe00000
817 #define bFrame_DC_Length 0xe000000
818 #define bSBD_start_offset 0x30000000
819 #define bFrame_TH_2 0x7
820 #define bFrame_GI2_TH 0x38
821 #define bGI2_Sync_en 0x40
822 #define bSarch_Short_Early 0x300
823 #define bSarch_Short_Late 0xc00
824 #define bSarch_GI2_Late 0x70000
825 #define bCFOAntSum 0x1
827 #define bCFOStartOffset 0xc
828 #define bCFOLookBack 0x70
829 #define bCFOSumWeight 0x80
830 #define bDAGCEnable 0x10000
831 #define bTXIQImb_A 0x3ff
832 #define bTXIQImb_B 0xfc00
833 #define bTXIQImb_C 0x3f0000
834 #define bTXIQImb_D 0xffc00000
835 #define bTxIDCOffset 0xff
836 #define bTxQDCOffset 0xff00
837 #define bTxDFIRMode 0x10000
838 #define bTxPesudoNoiseOn 0x4000000
839 #define bTxPesudoNoise_A 0xff
840 #define bTxPesudoNoise_B 0xff00
841 #define bTxPesudoNoise_C 0xff0000
842 #define bTxPesudoNoise_D 0xff000000
843 #define bCCADropOption 0x20000
844 #define bCCADropThres 0xfff00000
846 #define bEDCCA_L 0xf0
847 #define bLambda_ED 0x300
848 #define bRxInitialGain 0x7f
849 #define bRxAntDivEn 0x80
850 #define bRxAGCAddressForLNA 0x7f00
851 #define bRxHighPowerFlow 0x8000
852 #define bRxAGCFreezeThres 0xc0000
853 #define bRxFreezeStep_AGC1 0x300000
854 #define bRxFreezeStep_AGC2 0xc00000
855 #define bRxFreezeStep_AGC3 0x3000000
856 #define bRxFreezeStep_AGC0 0xc000000
857 #define bRxRssi_Cmp_En 0x10000000
858 #define bRxQuickAGCEn 0x20000000
859 #define bRxAGCFreezeThresMode 0x40000000
860 #define bRxOverFlowCheckType 0x80000000
861 #define bRxAGCShift 0x7f
862 #define bTRSW_Tri_Only 0x80
863 #define bPowerThres 0x300
865 #define bRxAGCTogetherEn 0x2
866 #define bRxAGCMin 0x4
867 #define bRxHP_Ini 0x7
868 #define bRxHP_TRLNA 0x70
869 #define bRxHP_RSSI 0x700
870 #define bRxHP_BBP1 0x7000
871 #define bRxHP_BBP2 0x70000
872 #define bRxHP_BBP3 0x700000
873 #define bRSSI_H 0x7f0000 //the threshold for high power
874 #define bRSSI_Gen 0x7f000000 //the threshold for ant diversity
875 #define bRxSettle_TRSW 0x7
876 #define bRxSettle_LNA 0x38
877 #define bRxSettle_RSSI 0x1c0
878 #define bRxSettle_BBP 0xe00
879 #define bRxSettle_RxHP 0x7000
880 #define bRxSettle_AntSW_RSSI 0x38000
881 #define bRxSettle_AntSW 0xc0000
882 #define bRxProcessTime_DAGC 0x300000
883 #define bRxSettle_HSSI 0x400000
884 #define bRxProcessTime_BBPPW 0x800000
885 #define bRxAntennaPowerShift 0x3000000
886 #define bRSSITableSelect 0xc000000
887 #define bRxHP_Final 0x7000000
888 #define bRxHTSettle_BBP 0x7
889 #define bRxHTSettle_HSSI 0x8
890 #define bRxHTSettle_RxHP 0x70
891 #define bRxHTSettle_BBPPW 0x80
892 #define bRxHTSettle_Idle 0x300
893 #define bRxHTSettle_Reserved 0x1c00
894 #define bRxHTRxHPEn 0x8000
895 #define bRxHTAGCFreezeThres 0x30000
896 #define bRxHTAGCTogetherEn 0x40000
897 #define bRxHTAGCMin 0x80000
898 #define bRxHTAGCEn 0x100000
899 #define bRxHTDAGCEn 0x200000
900 #define bRxHTRxHP_BBP 0x1c00000
901 #define bRxHTRxHP_Final 0xe0000000
902 #define bRxPWRatioTH 0x3
903 #define bRxPWRatioEn 0x4
904 #define bRxMFHold 0x3800
905 #define bRxPD_Delay_TH1 0x38
906 #define bRxPD_Delay_TH2 0x1c0
907 #define bRxPD_DC_COUNT_MAX 0x600
908 //#define bRxMF_Hold 0x3800
909 #define bRxPD_Delay_TH 0x8000
910 #define bRxProcess_Delay 0xf0000
911 #define bRxSearchrange_GI2_Early 0x700000
912 #define bRxFrame_Guard_Counter_L 0x3800000
913 #define bRxSGI_Guard_L 0xc000000
914 #define bRxSGI_Search_L 0x30000000
915 #define bRxSGI_TH 0xc0000000
916 #define bDFSCnt0 0xff
917 #define bDFSCnt1 0xff00
918 #define bDFSFlag 0xf0000
919 #define bMFWeightSum 0x300000
920 #define bMinIdxTH 0x7f000000
921 #define bDAFormat 0x40000
922 #define bTxChEmuEnable 0x01000000
923 #define bTRSWIsolation_A 0x7f
924 #define bTRSWIsolation_B 0x7f00
925 #define bTRSWIsolation_C 0x7f0000
926 #define bTRSWIsolation_D 0x7f000000
927 #define bExtLNAGain 0x7c00
930 #define bSTBCEn 0x4 // Useless
931 #define bAntennaMapping 0x10
933 #define bCFOAntSumD 0x200
934 #define bPHYCounterReset 0x8000000
935 #define bCFOReportGet 0x4000000
936 #define bOFDMContinueTx 0x10000000
937 #define bOFDMSingleCarrier 0x20000000
938 #define bOFDMSingleTone 0x40000000
939 //#define bRxPath1 0x01
940 //#define bRxPath2 0x02
941 //#define bRxPath3 0x04
942 //#define bRxPath4 0x08
943 //#define bTxPath1 0x10
944 //#define bTxPath2 0x20
945 #define bHTDetect 0x100
946 #define bCFOEn 0x10000
947 #define bCFOValue 0xfff00000
948 #define bSigTone_Re 0x3f
949 #define bSigTone_Im 0x7f00
950 #define bCounter_CCA 0xffff
951 #define bCounter_ParityFail 0xffff0000
952 #define bCounter_RateIllegal 0xffff
953 #define bCounter_CRC8Fail 0xffff0000
954 #define bCounter_MCSNoSupport 0xffff
955 #define bCounter_FastSync 0xffff
956 #define bShortCFO 0xfff
957 #define bShortCFOTLength 12 //total
958 #define bShortCFOFLength 11 //fraction
959 #define bLongCFO 0x7ff
960 #define bLongCFOTLength 11
961 #define bLongCFOFLength 11
962 #define bTailCFO 0x1fff
963 #define bTailCFOTLength 13
964 #define bTailCFOFLength 12
965 #define bmax_en_pwdB 0xffff
966 #define bCC_power_dB 0xffff0000
967 #define bnoise_pwdB 0xffff
968 #define bPowerMeasTLength 10
969 #define bPowerMeasFLength 3
970 #define bRx_HT_BW 0x1
973 #define bNB_intf_det_on 0x1
974 #define bIntf_win_len_cfg 0x30
975 #define bNB_Intf_TH_cfg 0x1c0
977 #define bTableSel 0x40
979 #define bRxSNR_A 0xff
980 #define bRxSNR_B 0xff00
981 #define bRxSNR_C 0xff0000
982 #define bRxSNR_D 0xff000000
983 #define bSNREVMTLength 8
984 #define bSNREVMFLength 1
986 #define bCSI2nd 0xff00
987 #define bRxEVM1st 0xff0000
988 #define bRxEVM2nd 0xff000000
991 #define bSGIEN 0x10000
993 #define bSFactorQAM1 0xf // Useless
994 #define bSFactorQAM2 0xf0
995 #define bSFactorQAM3 0xf00
996 #define bSFactorQAM4 0xf000
997 #define bSFactorQAM5 0xf0000
998 #define bSFactorQAM6 0xf0000
999 #define bSFactorQAM7 0xf00000
1000 #define bSFactorQAM8 0xf000000
1001 #define bSFactorQAM9 0xf0000000
1002 #define bCSIScheme 0x100000
1004 #define bNoiseLvlTopSet 0x3 // Useless
1005 #define bChSmooth 0x4
1006 #define bChSmoothCfg1 0x38
1007 #define bChSmoothCfg2 0x1c0
1008 #define bChSmoothCfg3 0xe00
1009 #define bChSmoothCfg4 0x7000
1010 #define bMRCMode 0x800000
1011 #define bTHEVMCfg 0x7000000
1013 #define bLoopFitType 0x1 // Useless
1014 #define bUpdCFO 0x40
1015 #define bUpdCFOOffData 0x80
1016 #define bAdvUpdCFO 0x100
1017 #define bAdvTimeCtrl 0x800
1018 #define bUpdClko 0x1000
1020 #define bTrackingMode 0x8000
1021 #define bPhCmpEnable 0x10000
1022 #define bUpdClkoLTF 0x20000
1023 #define bComChCFO 0x40000
1024 #define bCSIEstiMode 0x80000
1025 #define bAdvUpdEqz 0x100000
1026 #define bUChCfg 0x7000000
1027 #define bUpdEqz 0x8000000
1030 #define bRxPesudoNoiseOn 0x20000000 // Useless
1031 #define bRxPesudoNoise_A 0xff
1032 #define bRxPesudoNoise_B 0xff00
1033 #define bRxPesudoNoise_C 0xff0000
1034 #define bRxPesudoNoise_D 0xff000000
1035 #define bPesudoNoiseState_A 0xffff
1036 #define bPesudoNoiseState_B 0xffff0000
1037 #define bPesudoNoiseState_C 0xffff
1038 #define bPesudoNoiseState_D 0xffff0000
1042 #define bZebra1_HSSIEnable 0x8 // Useless
1043 #define bZebra1_TRxControl 0xc00
1044 #define bZebra1_TRxGainSetting 0x07f
1045 #define bZebra1_RxCorner 0xc00
1046 #define bZebra1_TxChargePump 0x38
1047 #define bZebra1_RxChargePump 0x7
1048 #define bZebra1_ChannelNum 0xf80
1049 #define bZebra1_TxLPFBW 0x400
1050 #define bZebra1_RxLPFBW 0x600
1053 #define bRTL8256RegModeCtrl1 0x100 // Useless
1054 #define bRTL8256RegModeCtrl0 0x40
1055 #define bRTL8256_TxLPFBW 0x18
1056 #define bRTL8256_RxLPFBW 0x600
1059 #define bRTL8258_TxLPFBW 0xc // Useless
1060 #define bRTL8258_RxLPFBW 0xc00
1061 #define bRTL8258_RSSILPFBW 0xc0
1068 //byte endable for sb_write
1069 #define bByte0 0x1 // Useless
1077 //for PutRegsetting & GetRegSetting BitMask
1078 #define bMaskByte0 0xff // Reg 0xc50 rOFDM0_XAAGCCore~0xC6f
1079 #define bMaskByte1 0xff00
1080 #define bMaskByte2 0xff0000
1081 #define bMaskByte3 0xff000000
1082 #define bMaskHWord 0xffff0000
1083 #define bMaskLWord 0x0000ffff
1084 #define bMaskDWord 0xffffffff
1085 #define bMaskH3Bytes 0xffffff00
1086 #define bMask12Bits 0xfff
1087 #define bMaskH4Bits 0xf0000000
1088 #define bMaskOFDM_D 0xffc00000
1089 #define bMaskCCK 0x3f3f3f3f
1092 #define bEnable 0x1 // Useless
1093 #define bDisable 0x0
1095 #define LeftAntenna 0x0 // Useless
1096 #define RightAntenna 0x1
1098 #define tCheckTxStatus 500 //500ms // Useless
1099 #define tUpdateRxCounter 100 //100ms
1101 #define rateCCK 0 // Useless
1105 //define Register-End
1106 #define bPMAC_End 0x1ff // Useless
1107 #define bFPGAPHY0_End 0x8ff
1108 #define bFPGAPHY1_End 0x9ff
1109 #define bCCKPHY0_End 0xaff
1110 #define bOFDMPHY0_End 0xcff
1111 #define bOFDMPHY1_End 0xdff
1113 //define max debug item in each debug page
1114 //#define bMaxItem_FPGA_PHY0 0x9
1115 //#define bMaxItem_FPGA_PHY1 0x3
1116 //#define bMaxItem_PHY_11B 0x16
1117 //#define bMaxItem_OFDM_PHY0 0x29
1118 //#define bMaxItem_OFDM_PHY1 0x0
1120 #define bPMACControl 0x0 // Useless
1121 #define bWMACControl 0x1
1122 #define bWNICControl 0x2
1124 #define PathA 0x0 // Useless
1129 /*--------------------------Define Parameters-------------------------------*/
1132 #endif //__INC_HAL8192SPHYREG_H