1 /******************************************************************************
3 * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
19 ******************************************************************************/
20 /*****************************************************************************
22 * Module: __INC_HAL8192DPHYCFG_H
28 * Export: Constants, macro, functions(API), global variables(None).
34 * 08/07/2007 MHC 1. Porting from 9x series PHYCFG.h.
35 * 2. Reorganize code architecture.
37 *****************************************************************************/
38 /* Check to see if the file has been included already. */
39 #ifndef __INC_HAL8192DPHYCFG_H
40 #define __INC_HAL8192DPHYCFG_H
43 /*--------------------------Define Parameters-------------------------------*/
45 #define MAX_STALL_TIME 50 //us
46 #define AntennaDiversityValue 0x80 //(Adapter->bSoftwareAntennaDiversity ? 0x00:0x80)
47 #define MAX_TXPWR_IDX_NMODE_92S 63
48 #define Reset_Cnt_Limit 3
52 #define SET_RTL8192SE_RF_SLEEP(_pAdapter) \
55 u1bTmp = PlatformEFIORead1Byte(_pAdapter, REG_LDOV12D_CTRL); \
57 PlatformEFIOWrite1Byte(_pAdapter, REG_LDOV12D_CTRL, u1bTmp); \
58 PlatformEFIOWrite1Byte(_pAdapter, REG_SPS_OCP_CFG, 0x0); \
59 PlatformEFIOWrite1Byte(_pAdapter, TXPAUSE, 0xFF); \
60 PlatformEFIOWrite2Byte(_pAdapter, CMDR, 0x57FC); \
62 PlatformEFIOWrite2Byte(_pAdapter, CMDR, 0x77FC); \
63 PlatformEFIOWrite1Byte(_pAdapter, PHY_CCA, 0x0); \
65 PlatformEFIOWrite2Byte(_pAdapter, CMDR, 0x37FC); \
67 PlatformEFIOWrite2Byte(_pAdapter, CMDR, 0x77FC); \
69 PlatformEFIOWrite2Byte(_pAdapter, CMDR, 0x57FC); \
74 /*--------------------------Define Parameters-------------------------------*/
77 /*------------------------------Define structure----------------------------*/
79 #define CHANNEL_GROUP_MAX_2G 3
80 #define CHANNEL_GROUP_IDX_5GL 3
81 #define CHANNEL_GROUP_IDX_5GM 6
82 #define CHANNEL_GROUP_IDX_5GH 9
83 #define CHANNEL_GROUP_MAX_5G 9
84 #define CHANNEL_MAX_NUMBER_2G 14
86 typedef enum _MACPHY_MODE_CHANGE_ACTION{
94 }MACPHY_MODE_CHANGE_ACTION,*PMACPHY_MODE_CHANGE_ACTION;
100 /*------------------------------Define structure----------------------------*/
103 /*------------------------Export global variable----------------------------*/
104 /*------------------------Export global variable----------------------------*/
107 /*------------------------Export Marco Definition---------------------------*/
109 /*--------------------------Exported Function prototype---------------------*/
111 // BB and RF register read/write
113 void PHY_SetBBReg1Byte8192D( IN PADAPTER Adapter,
117 u32 PHY_QueryBBReg8192D( IN PADAPTER Adapter,
120 void PHY_SetBBReg8192D( IN PADAPTER Adapter,
124 u32 PHY_QueryRFReg8192D( IN PADAPTER Adapter,
128 void PHY_SetRFReg8192D( IN PADAPTER Adapter,
135 // Initialization related function
137 /* MAC/BB/RF HAL config */
138 extern int PHY_MACConfig8192D( IN PADAPTER Adapter );
139 extern int PHY_BBConfig8192D( IN PADAPTER Adapter );
140 extern int PHY_RFConfig8192D( IN PADAPTER Adapter );
142 int rtl8192d_PHY_ConfigRFWithParaFile( IN PADAPTER Adapter,
145 int rtl8192d_PHY_ConfigRFWithHeaderFile( IN PADAPTER Adapter,
146 IN RF_CONTENT Content,
148 /* BB/RF readback check for making sure init OK */
149 int rtl8192d_PHY_CheckBBAndRFOK( IN PADAPTER Adapter,
150 IN HW_BLOCK_E CheckBlock,
152 /* Read initi reg value for tx power setting. */
153 void rtl8192d_PHY_GetHWRegOriginalValue( IN PADAPTER Adapter );
158 //extern BOOLEAN PHY_SetRFPowerState(IN PADAPTER Adapter,
159 // IN RT_RF_POWER_STATE eRFPowerState);
164 void PHY_GetTxPowerLevel8192D( IN PADAPTER Adapter,
165 OUT s32* powerlevel );
166 void PHY_SetTxPowerLevel8192D( IN PADAPTER Adapter,
168 BOOLEAN PHY_UpdateTxPowerDbm8192D( IN PADAPTER Adapter,
173 PHY_ScanOperationBackup8192D(IN PADAPTER Adapter,
177 // Switch bandwidth for 8192S
179 //void PHY_SetBWModeCallback8192C( IN PRT_TIMER pTimer );
180 void PHY_SetBWMode8192D( IN PADAPTER pAdapter,
181 IN CHANNEL_WIDTH ChnlWidth,
182 IN unsigned char Offset );
185 // Set FW CMD IO for 8192S.
187 //extern BOOLEAN HalSetIO8192C( IN PADAPTER Adapter,
188 // IN IO_TYPE IOType);
191 // Set A2 entry to fw for 8192S
193 extern void FillA2Entry8192C( IN PADAPTER Adapter,
199 // channel switch related funciton
201 //extern void PHY_SwChnlCallback8192C( IN PRT_TIMER pTimer );
202 void PHY_SwChnl8192D( IN PADAPTER pAdapter,
206 PHY_SetSwChnlBWMode8192D(
209 IN CHANNEL_WIDTH Bandwidth,
215 // BB/MAC/RF other monitor API
217 void PHY_SetMonitorMode8192D(IN PADAPTER pAdapter,
218 IN BOOLEAN bEnableMonitorMode );
220 BOOLEAN PHY_CheckIsLegalRfPath8192D(IN PADAPTER pAdapter,
225 // Modify the value of the hw register when beacon interval be changed.
228 rtl8192d_PHY_SetBeaconHwReg( IN PADAPTER Adapter,
229 IN u16 BeaconInterval );
233 PHY_SwitchEphyParameter(
238 PHY_EnableHostClkReq(
249 PHY_UpdateBBRFConfiguration8192D(
251 IN BOOLEAN bisBandSwitch
254 VOID PHY_ReadMacPhyMode92D(
256 IN BOOLEAN AutoloadFail
259 VOID PHY_ConfigMacPhyMode92D(
263 VOID PHY_ConfigMacPhyModeInfo92D(
267 VOID PHY_ConfigMacCoexist_RFPage92D(
272 rtl8192d_PHY_InitRxSetting(
278 rtl8192d_PHY_SetRFPathSwitch(IN PADAPTER pAdapter, IN BOOLEAN bMain);
281 HalChangeCCKStatus8192D(
283 IN BOOLEAN bCCKDisable
287 PHY_InitPABias92D(IN PADAPTER Adapter);
289 /*--------------------------Exported Function prototype---------------------*/
291 #define PHY_SetBBReg1Byte(Adapter, RegAddr, BitMask, Data) PHY_SetBBReg1Byte8192D((Adapter), (RegAddr), (BitMask), (Data))
292 #endif // __INC_HAL8192SPHYCFG_H