1 /******************************************************************************
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3 * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
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5 * This program is free software; you can redistribute it and/or modify it
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6 * under the terms of version 2 of the GNU General Public License as
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7 * published by the Free Software Foundation.
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9 * This program is distributed in the hope that it will be useful, but WITHOUT
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10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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14 * You should have received a copy of the GNU General Public License along with
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15 * this program; if not, write to the Free Software Foundation, Inc.,
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16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
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19 ******************************************************************************/
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20 #ifndef __HALPWRSEQCMD_H__
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21 #define __HALPWRSEQCMD_H__
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23 #include <drv_types.h>
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25 /*---------------------------------------------*/
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26 //3 The value of cmd: 4 bits
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27 /*---------------------------------------------*/
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28 #define PWR_CMD_READ 0x00
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29 // offset: the read register offset
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30 // msk: the mask of the read value
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31 // value: N/A, left by 0
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32 // note: dirver shall implement this function by read & msk
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34 #define PWR_CMD_WRITE 0x01
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35 // offset: the read register offset
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36 // msk: the mask of the write bits
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37 // value: write value
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38 // note: driver shall implement this cmd by read & msk after write
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40 #define PWR_CMD_POLLING 0x02
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41 // offset: the read register offset
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42 // msk: the mask of the polled value
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43 // value: the value to be polled, masked by the msd field.
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44 // note: driver shall implement this cmd by
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46 // if( (Read(offset) & msk) == (value & msk) )
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48 // } while(not timeout);
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50 #define PWR_CMD_DELAY 0x03
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51 // offset: the value to delay
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53 // value: the unit of delay, 0: us, 1: ms
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55 #define PWR_CMD_END 0x04
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60 /*---------------------------------------------*/
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61 //3 The value of base: 4 bits
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62 /*---------------------------------------------*/
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63 // define the base address of each block
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64 #define PWR_BASEADDR_MAC 0x00
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65 #define PWR_BASEADDR_USB 0x01
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66 #define PWR_BASEADDR_PCIE 0x02
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67 #define PWR_BASEADDR_SDIO 0x03
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69 /*---------------------------------------------*/
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70 //3 The value of interface_msk: 4 bits
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71 /*---------------------------------------------*/
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72 #define PWR_INTF_SDIO_MSK BIT(0)
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73 #define PWR_INTF_USB_MSK BIT(1)
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74 #define PWR_INTF_PCI_MSK BIT(2)
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75 #define PWR_INTF_ALL_MSK (BIT(0)|BIT(1)|BIT(2)|BIT(3))
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77 /*---------------------------------------------*/
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78 //3 The value of fab_msk: 4 bits
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79 /*---------------------------------------------*/
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80 #define PWR_FAB_TSMC_MSK BIT(0)
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81 #define PWR_FAB_UMC_MSK BIT(1)
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82 #define PWR_FAB_ALL_MSK (BIT(0)|BIT(1)|BIT(2)|BIT(3))
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84 /*---------------------------------------------*/
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85 //3 The value of cut_msk: 8 bits
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86 /*---------------------------------------------*/
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87 #define PWR_CUT_TESTCHIP_MSK BIT(0)
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88 #define PWR_CUT_A_MSK BIT(1)
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89 #define PWR_CUT_B_MSK BIT(2)
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90 #define PWR_CUT_C_MSK BIT(3)
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91 #define PWR_CUT_D_MSK BIT(4)
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92 #define PWR_CUT_E_MSK BIT(5)
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93 #define PWR_CUT_F_MSK BIT(6)
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94 #define PWR_CUT_G_MSK BIT(7)
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95 #define PWR_CUT_ALL_MSK 0xFF
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98 typedef enum _PWRSEQ_CMD_DELAY_UNIT_
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102 } PWRSEQ_DELAY_UNIT;
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104 typedef struct _WL_PWR_CFG_
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109 u8 interface_msk:4;
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114 } WLAN_PWR_CFG, *PWLAN_PWR_CFG;
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117 #define GET_PWR_CFG_OFFSET(__PWR_CMD) __PWR_CMD.offset
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118 #define GET_PWR_CFG_CUT_MASK(__PWR_CMD) __PWR_CMD.cut_msk
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119 #define GET_PWR_CFG_FAB_MASK(__PWR_CMD) __PWR_CMD.fab_msk
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120 #define GET_PWR_CFG_INTF_MASK(__PWR_CMD) __PWR_CMD.interface_msk
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121 #define GET_PWR_CFG_BASE(__PWR_CMD) __PWR_CMD.base
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122 #define GET_PWR_CFG_CMD(__PWR_CMD) __PWR_CMD.cmd
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123 #define GET_PWR_CFG_MASK(__PWR_CMD) __PWR_CMD.msk
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124 #define GET_PWR_CFG_VALUE(__PWR_CMD) __PWR_CMD.value
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127 //================================================================================
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128 // Prototype of protected function.
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129 //================================================================================
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130 u8 HalPwrSeqCmdParsing(
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135 WLAN_PWR_CFG PwrCfgCmd[]);
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