drivers/net/wireless/rockchip_wlan/rtl8723bs/include/drv_types_pci.h

   1 /******************************************************************************\r
   2  *\r
   3  * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.\r
   4  *                                        \r
   5  * This program is free software; you can redistribute it and/or modify it\r
   6  * under the terms of version 2 of the GNU General Public License as\r
   7  * published by the Free Software Foundation.\r
   8  *\r
   9  * This program is distributed in the hope that it will be useful, but WITHOUT\r
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\r
  11  * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\r
  12  * more details.\r
  13  *\r
  14  * You should have received a copy of the GNU General Public License along with\r
  15  * this program; if not, write to the Free Software Foundation, Inc.,\r
  16  * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA\r
  17  *\r
  18  *\r
  19  ******************************************************************************/\r
  20 #ifndef __DRV_TYPES_PCI_H__\r
  21 #define __DRV_TYPES_PCI_H__\r
  22 \r
  23 \r
  24 #ifdef PLATFORM_LINUX\r
  25 #include <linux/pci.h>\r
  26 #endif\r
  27 \r
  28 \r
  29 #define INTEL_VENDOR_ID                         0x8086\r
  30 #define SIS_VENDOR_ID                                   0x1039\r
  31 #define ATI_VENDOR_ID                                   0x1002\r
  32 #define ATI_DEVICE_ID                                   0x7914\r
  33 #define AMD_VENDOR_ID                                   0x1022\r
  34 \r
  35 #define PCI_MAX_BRIDGE_NUMBER                   255\r
  36 #define PCI_MAX_DEVICES                         32\r
  37 #define PCI_MAX_FUNCTION                                8\r
  38 \r
  39 #define PCI_CONF_ADDRESS                                0x0CF8   // PCI Configuration Space Address \r
  40 #define PCI_CONF_DATA                                   0x0CFC   // PCI Configuration Space Data \r
  41 \r
  42 #define PCI_CLASS_BRIDGE_DEV                    0x06\r
  43 #define PCI_SUBCLASS_BR_PCI_TO_PCI      0x04\r
  44 \r
  45 #define         PCI_CAPABILITY_ID_PCI_EXPRESS   0x10\r
  46 \r
  47 #define U1DONTCARE                                      0xFF    \r
  48 #define U2DONTCARE                                      0xFFFF  \r
  49 #define U4DONTCARE                                      0xFFFFFFFF\r
  50 \r
  51 #define PCI_VENDER_ID_REALTEK           0x10ec\r
  52 \r
  53 #define HAL_HW_PCI_8180_DEVICE_ID               0x8180\r
  54 #define HAL_HW_PCI_8185_DEVICE_ID               0x8185  //8185 or 8185b\r
  55 #define HAL_HW_PCI_8188_DEVICE_ID               0x8188  //8185b         \r
  56 #define HAL_HW_PCI_8198_DEVICE_ID               0x8198  //8185b         \r
  57 #define HAL_HW_PCI_8190_DEVICE_ID               0x8190  //8190\r
  58 #define HAL_HW_PCI_8723E_DEVICE_ID              0x8723  //8723E\r
  59 #define HAL_HW_PCI_8192_DEVICE_ID               0x8192  //8192 PCI-E\r
  60 #define HAL_HW_PCI_8192SE_DEVICE_ID             0x8192  //8192 SE\r
  61 #define HAL_HW_PCI_8174_DEVICE_ID               0x8174  //8192 SE \r
  62 #define HAL_HW_PCI_8173_DEVICE_ID               0x8173  //8191 SE Crab\r
  63 #define HAL_HW_PCI_8172_DEVICE_ID               0x8172  //8191 SE RE\r
  64 #define HAL_HW_PCI_8171_DEVICE_ID               0x8171  //8191 SE Unicron\r
  65 #define HAL_HW_PCI_0045_DEVICE_ID                       0x0045  //8190 PCI for Ceraga\r
  66 #define HAL_HW_PCI_0046_DEVICE_ID                       0x0046  //8190 Cardbus for Ceraga\r
  67 #define HAL_HW_PCI_0044_DEVICE_ID                       0x0044  //8192e PCIE for Ceraga\r
  68 #define HAL_HW_PCI_0047_DEVICE_ID                       0x0047  //8192e Express Card for Ceraga\r
  69 #define HAL_HW_PCI_700F_DEVICE_ID                       0x700F\r
  70 #define HAL_HW_PCI_701F_DEVICE_ID                       0x701F\r
  71 #define HAL_HW_PCI_DLINK_DEVICE_ID              0x3304\r
  72 #define HAL_HW_PCI_8192CET_DEVICE_ID            0x8191  //8192ce\r
  73 #define HAL_HW_PCI_8192CE_DEVICE_ID             0x8178  //8192ce\r
  74 #define HAL_HW_PCI_8191CE_DEVICE_ID             0x8177  //8192ce\r
  75 #define HAL_HW_PCI_8188CE_DEVICE_ID             0x8176  //8192ce\r
  76 #define HAL_HW_PCI_8192CU_DEVICE_ID             0x8191  //8192ce\r
  77 #define HAL_HW_PCI_8192DE_DEVICE_ID             0x8193  //8192de\r
  78 #define HAL_HW_PCI_002B_DEVICE_ID                       0x002B  //8192de, provided by HW SD\r
  79 #define HAL_HW_PCI_8188EE_DEVICE_ID             0x8179\r
  80 \r
  81 #define HAL_MEMORY_MAPPED_IO_RANGE_8190PCI              0x1000     //8190 support 16 pages of IO registers\r
  82 #define HAL_HW_PCI_REVISION_ID_8190PCI                  0x00\r
  83 #define HAL_MEMORY_MAPPED_IO_RANGE_8192PCIE     0x4000  //8192 support 16 pages of IO registers\r
  84 #define HAL_HW_PCI_REVISION_ID_8192PCIE                 0x01\r
  85 #define HAL_MEMORY_MAPPED_IO_RANGE_8192SE               0x4000  //8192 support 16 pages of IO registers\r
  86 #define HAL_HW_PCI_REVISION_ID_8192SE                   0x10\r
  87 #define HAL_HW_PCI_REVISION_ID_8192CE                   0x1\r
  88 #define HAL_MEMORY_MAPPED_IO_RANGE_8192CE               0x4000  //8192 support 16 pages of IO registers\r
  89 #define HAL_HW_PCI_REVISION_ID_8192DE                   0x0\r
  90 #define HAL_MEMORY_MAPPED_IO_RANGE_8192DE               0x4000  //8192 support 16 pages of IO registers\r
  91 \r
  92 enum pci_bridge_vendor {\r
  93         PCI_BRIDGE_VENDOR_INTEL = 0x0,//0b'0000,0001\r
  94         PCI_BRIDGE_VENDOR_ATI, //= 0x02,//0b'0000,0010\r
  95         PCI_BRIDGE_VENDOR_AMD, //= 0x04,//0b'0000,0100\r
  96         PCI_BRIDGE_VENDOR_SIS ,//= 0x08,//0b'0000,1000\r
  97         PCI_BRIDGE_VENDOR_UNKNOWN, //= 0x40,//0b'0100,0000\r
  98         PCI_BRIDGE_VENDOR_MAX ,//= 0x80\r
  99 } ;\r
 100 \r
 101 // copy this data structor defination from MSDN SDK\r
 102 typedef struct _PCI_COMMON_CONFIG {\r
 103         u16     VendorID;\r
 104         u16     DeviceID;\r
 105         u16     Command;\r
 106         u16     Status;\r
 107         u8      RevisionID;\r
 108         u8      ProgIf;\r
 109         u8      SubClass;\r
 110         u8      BaseClass;\r
 111         u8      CacheLineSize;\r
 112         u8      LatencyTimer;\r
 113         u8      HeaderType;\r
 114         u8      BIST;\r
 115 \r
 116         union {\r
 117         struct _PCI_HEADER_TYPE_0 {\r
 118                 u32     BaseAddresses[6];\r
 119                 u32     CIS;\r
 120                 u16     SubVendorID;\r
 121                 u16     SubSystemID;\r
 122                 u32     ROMBaseAddress;\r
 123                 u8      CapabilitiesPtr;\r
 124                 u8      Reserved1[3];\r
 125                 u32     Reserved2;\r
 126 \r
 127                 u8      InterruptLine;\r
 128                 u8      InterruptPin;\r
 129                 u8      MinimumGrant;\r
 130                 u8      MaximumLatency;\r
 131         } type0;\r
 132 #if 0\r
 133         struct _PCI_HEADER_TYPE_1 {\r
 134                 ULONG BaseAddresses[PCI_TYPE1_ADDRESSES];\r
 135                 UCHAR PrimaryBusNumber;\r
 136                 UCHAR SecondaryBusNumber;\r
 137                 UCHAR SubordinateBusNumber;\r
 138                 UCHAR SecondaryLatencyTimer;\r
 139                 UCHAR IOBase;\r
 140                 UCHAR IOLimit;\r
 141                 USHORT SecondaryStatus;\r
 142                 USHORT MemoryBase;\r
 143                 USHORT MemoryLimit;\r
 144                 USHORT PrefetchableMemoryBase;\r
 145                 USHORT PrefetchableMemoryLimit;\r
 146                 ULONG PrefetchableMemoryBaseUpper32;\r
 147                 ULONG PrefetchableMemoryLimitUpper32;\r
 148                 USHORT IOBaseUpper;\r
 149                 USHORT IOLimitUpper;\r
 150                 ULONG Reserved2;\r
 151                 ULONG ExpansionROMBase;\r
 152                 UCHAR InterruptLine;\r
 153                 UCHAR InterruptPin;\r
 154                 USHORT BridgeControl;\r
 155         } type1;\r
 156 \r
 157         struct _PCI_HEADER_TYPE_2 {\r
 158                 ULONG BaseAddress;\r
 159                 UCHAR CapabilitiesPtr;\r
 160                 UCHAR Reserved2;\r
 161                 USHORT SecondaryStatus;\r
 162                 UCHAR PrimaryBusNumber;\r
 163                 UCHAR CardbusBusNumber;\r
 164                 UCHAR SubordinateBusNumber;\r
 165                 UCHAR CardbusLatencyTimer;\r
 166                 ULONG MemoryBase0;\r
 167                 ULONG MemoryLimit0;\r
 168                 ULONG MemoryBase1;\r
 169                 ULONG MemoryLimit1;\r
 170                 USHORT IOBase0_LO;\r
 171                 USHORT IOBase0_HI;\r
 172                 USHORT IOLimit0_LO;\r
 173                 USHORT IOLimit0_HI;\r
 174                 USHORT IOBase1_LO;\r
 175                 USHORT IOBase1_HI;\r
 176                 USHORT IOLimit1_LO;\r
 177                 USHORT IOLimit1_HI;\r
 178                 UCHAR InterruptLine;\r
 179                 UCHAR InterruptPin;\r
 180                 USHORT BridgeControl;\r
 181                 USHORT SubVendorID;\r
 182                 USHORT SubSystemID;\r
 183                 ULONG LegacyBaseAddress;\r
 184                 UCHAR Reserved3[56];\r
 185                 ULONG SystemControl;\r
 186                 UCHAR MultiMediaControl;\r
 187                 UCHAR GeneralStatus;\r
 188                 UCHAR Reserved4[2];\r
 189                 UCHAR GPIO0Control;\r
 190                 UCHAR GPIO1Control;\r
 191                 UCHAR GPIO2Control;\r
 192                 UCHAR GPIO3Control;\r
 193                 ULONG IRQMuxRouting;\r
 194                 UCHAR RetryStatus;\r
 195                 UCHAR CardControl;\r
 196                 UCHAR DeviceControl;\r
 197                 UCHAR Diagnostic;\r
 198         } type2;\r
 199 #endif\r
 200         } u;\r
 201 \r
 202         u8      DeviceSpecific[108];\r
 203 } PCI_COMMON_CONFIG , *PPCI_COMMON_CONFIG;\r
 204 \r
 205 typedef struct _RT_PCI_CAPABILITIES_HEADER {\r
 206     u8   CapabilityID;\r
 207     u8   Next;\r
 208 } RT_PCI_CAPABILITIES_HEADER, *PRT_PCI_CAPABILITIES_HEADER;\r
 209 \r
 210 struct pci_priv{\r
 211         BOOLEAN         pci_clk_req;\r
 212         \r
 213         u8      pciehdr_offset;\r
 214         //  PCIeCap is only differece between B-cut and C-cut.\r
 215         //  Configuration Space offset 72[7:4] \r
 216         //  0: A/B cut \r
 217         //  1: C cut and later.\r
 218         u8      pcie_cap;\r
 219         u8      linkctrl_reg;\r
 220         \r
 221         u8      busnumber;\r
 222         u8      devnumber;      \r
 223         u8      funcnumber;     \r
 224 \r
 225         u8      pcibridge_busnum;\r
 226         u8      pcibridge_devnum;\r
 227         u8      pcibridge_funcnum;\r
 228         u8      pcibridge_vendor;\r
 229         u16     pcibridge_vendorid;\r
 230         u16     pcibridge_deviceid;\r
 231         u8      pcibridge_pciehdr_offset;\r
 232         u8      pcibridge_linkctrlreg;  \r
 233 \r
 234         u8      amd_l1_patch;\r
 235 };\r
 236 \r
 237 typedef struct _RT_ISR_CONTENT\r
 238 {\r
 239         union{\r
 240                 u32                     IntArray[2];\r
 241                 u32                     IntReg4Byte;\r
 242                 u16                     IntReg2Byte;\r
 243         };\r
 244 }RT_ISR_CONTENT, *PRT_ISR_CONTENT;\r
 245 \r
 246 //#define RegAddr(addr)           (addr + 0xB2000000UL)\r
 247 //some platform macros will def here\r
 248 static inline void NdisRawWritePortUlong(u32 port,  u32 val)            \r
 249 {\r
 250         outl(val, port);\r
 251         //writel(val, (u8 *)RegAddr(port));     \r
 252 }\r
 253 \r
 254 static inline void NdisRawWritePortUchar(u32 port,  u8 val)\r
 255 {\r
 256         outb(val, port);\r
 257         //writeb(val, (u8 *)RegAddr(port));\r
 258 }\r
 259 \r
 260 static inline void NdisRawReadPortUchar(u32 port, u8 *pval)\r
 261 {\r
 262         *pval = inb(port);\r
 263         //*pval = readb((u8 *)RegAddr(port));\r
 264 }\r
 265 \r
 266 static inline void NdisRawReadPortUshort(u32 port, u16 *pval)\r
 267 {\r
 268         *pval = inw(port);\r
 269         //*pval = readw((u8 *)RegAddr(port));\r
 270 }\r
 271 \r
 272 static inline void NdisRawReadPortUlong(u32 port, u32 *pval)\r
 273 {\r
 274         *pval = inl(port);\r
 275         //*pval = readl((u8 *)RegAddr(port));\r
 276 }\r
 277 \r
 278 \r
 279 #endif\r
 280 \r