1 /******************************************************************************
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3 * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
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5 * This program is free software; you can redistribute it and/or modify it
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6 * under the terms of version 2 of the GNU General Public License as
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7 * published by the Free Software Foundation.
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9 * This program is distributed in the hope that it will be useful, but WITHOUT
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10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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14 * You should have received a copy of the GNU General Public License along with
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15 * this program; if not, write to the Free Software Foundation, Inc.,
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16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
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19 ******************************************************************************/
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20 #ifndef __DRV_TYPES_PCI_H__
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21 #define __DRV_TYPES_PCI_H__
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24 #ifdef PLATFORM_LINUX
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25 #include <linux/pci.h>
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29 #define INTEL_VENDOR_ID 0x8086
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30 #define SIS_VENDOR_ID 0x1039
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31 #define ATI_VENDOR_ID 0x1002
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32 #define ATI_DEVICE_ID 0x7914
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33 #define AMD_VENDOR_ID 0x1022
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35 #define PCI_MAX_BRIDGE_NUMBER 255
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36 #define PCI_MAX_DEVICES 32
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37 #define PCI_MAX_FUNCTION 8
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39 #define PCI_CONF_ADDRESS 0x0CF8 // PCI Configuration Space Address
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40 #define PCI_CONF_DATA 0x0CFC // PCI Configuration Space Data
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42 #define PCI_CLASS_BRIDGE_DEV 0x06
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43 #define PCI_SUBCLASS_BR_PCI_TO_PCI 0x04
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45 #define PCI_CAPABILITY_ID_PCI_EXPRESS 0x10
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47 #define U1DONTCARE 0xFF
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48 #define U2DONTCARE 0xFFFF
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49 #define U4DONTCARE 0xFFFFFFFF
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51 #define PCI_VENDER_ID_REALTEK 0x10ec
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53 #define HAL_HW_PCI_8180_DEVICE_ID 0x8180
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54 #define HAL_HW_PCI_8185_DEVICE_ID 0x8185 //8185 or 8185b
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55 #define HAL_HW_PCI_8188_DEVICE_ID 0x8188 //8185b
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56 #define HAL_HW_PCI_8198_DEVICE_ID 0x8198 //8185b
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57 #define HAL_HW_PCI_8190_DEVICE_ID 0x8190 //8190
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58 #define HAL_HW_PCI_8723E_DEVICE_ID 0x8723 //8723E
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59 #define HAL_HW_PCI_8192_DEVICE_ID 0x8192 //8192 PCI-E
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60 #define HAL_HW_PCI_8192SE_DEVICE_ID 0x8192 //8192 SE
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61 #define HAL_HW_PCI_8174_DEVICE_ID 0x8174 //8192 SE
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62 #define HAL_HW_PCI_8173_DEVICE_ID 0x8173 //8191 SE Crab
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63 #define HAL_HW_PCI_8172_DEVICE_ID 0x8172 //8191 SE RE
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64 #define HAL_HW_PCI_8171_DEVICE_ID 0x8171 //8191 SE Unicron
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65 #define HAL_HW_PCI_0045_DEVICE_ID 0x0045 //8190 PCI for Ceraga
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66 #define HAL_HW_PCI_0046_DEVICE_ID 0x0046 //8190 Cardbus for Ceraga
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67 #define HAL_HW_PCI_0044_DEVICE_ID 0x0044 //8192e PCIE for Ceraga
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68 #define HAL_HW_PCI_0047_DEVICE_ID 0x0047 //8192e Express Card for Ceraga
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69 #define HAL_HW_PCI_700F_DEVICE_ID 0x700F
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70 #define HAL_HW_PCI_701F_DEVICE_ID 0x701F
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71 #define HAL_HW_PCI_DLINK_DEVICE_ID 0x3304
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72 #define HAL_HW_PCI_8188EE_DEVICE_ID 0x8179
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74 #define HAL_MEMORY_MAPPED_IO_RANGE_8190PCI 0x1000 //8190 support 16 pages of IO registers
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75 #define HAL_HW_PCI_REVISION_ID_8190PCI 0x00
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76 #define HAL_MEMORY_MAPPED_IO_RANGE_8192PCIE 0x4000 //8192 support 16 pages of IO registers
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77 #define HAL_HW_PCI_REVISION_ID_8192PCIE 0x01
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78 #define HAL_MEMORY_MAPPED_IO_RANGE_8192SE 0x4000 //8192 support 16 pages of IO registers
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79 #define HAL_HW_PCI_REVISION_ID_8192SE 0x10
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80 #define HAL_HW_PCI_REVISION_ID_8192CE 0x1
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81 #define HAL_MEMORY_MAPPED_IO_RANGE_8192CE 0x4000 //8192 support 16 pages of IO registers
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82 #define HAL_HW_PCI_REVISION_ID_8192DE 0x0
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83 #define HAL_MEMORY_MAPPED_IO_RANGE_8192DE 0x4000 //8192 support 16 pages of IO registers
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85 enum pci_bridge_vendor {
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86 PCI_BRIDGE_VENDOR_INTEL = 0x0,//0b'0000,0001
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87 PCI_BRIDGE_VENDOR_ATI, //= 0x02,//0b'0000,0010
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88 PCI_BRIDGE_VENDOR_AMD, //= 0x04,//0b'0000,0100
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89 PCI_BRIDGE_VENDOR_SIS ,//= 0x08,//0b'0000,1000
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90 PCI_BRIDGE_VENDOR_UNKNOWN, //= 0x40,//0b'0100,0000
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91 PCI_BRIDGE_VENDOR_MAX ,//= 0x80
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94 // copy this data structor defination from MSDN SDK
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95 typedef struct _PCI_COMMON_CONFIG {
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110 struct _PCI_HEADER_TYPE_0 {
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111 u32 BaseAddresses[6];
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115 u32 ROMBaseAddress;
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116 u8 CapabilitiesPtr;
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126 struct _PCI_HEADER_TYPE_1 {
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127 ULONG BaseAddresses[PCI_TYPE1_ADDRESSES];
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128 UCHAR PrimaryBusNumber;
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129 UCHAR SecondaryBusNumber;
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130 UCHAR SubordinateBusNumber;
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131 UCHAR SecondaryLatencyTimer;
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134 USHORT SecondaryStatus;
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136 USHORT MemoryLimit;
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137 USHORT PrefetchableMemoryBase;
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138 USHORT PrefetchableMemoryLimit;
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139 ULONG PrefetchableMemoryBaseUpper32;
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140 ULONG PrefetchableMemoryLimitUpper32;
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141 USHORT IOBaseUpper;
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142 USHORT IOLimitUpper;
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144 ULONG ExpansionROMBase;
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145 UCHAR InterruptLine;
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146 UCHAR InterruptPin;
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147 USHORT BridgeControl;
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150 struct _PCI_HEADER_TYPE_2 {
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152 UCHAR CapabilitiesPtr;
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154 USHORT SecondaryStatus;
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155 UCHAR PrimaryBusNumber;
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156 UCHAR CardbusBusNumber;
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157 UCHAR SubordinateBusNumber;
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158 UCHAR CardbusLatencyTimer;
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160 ULONG MemoryLimit0;
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162 ULONG MemoryLimit1;
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165 USHORT IOLimit0_LO;
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166 USHORT IOLimit0_HI;
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169 USHORT IOLimit1_LO;
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170 USHORT IOLimit1_HI;
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171 UCHAR InterruptLine;
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172 UCHAR InterruptPin;
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173 USHORT BridgeControl;
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174 USHORT SubVendorID;
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175 USHORT SubSystemID;
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176 ULONG LegacyBaseAddress;
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177 UCHAR Reserved3[56];
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178 ULONG SystemControl;
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179 UCHAR MultiMediaControl;
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180 UCHAR GeneralStatus;
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181 UCHAR Reserved4[2];
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182 UCHAR GPIO0Control;
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183 UCHAR GPIO1Control;
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184 UCHAR GPIO2Control;
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185 UCHAR GPIO3Control;
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186 ULONG IRQMuxRouting;
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189 UCHAR DeviceControl;
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195 u8 DeviceSpecific[108];
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196 } PCI_COMMON_CONFIG , *PPCI_COMMON_CONFIG;
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198 typedef struct _RT_PCI_CAPABILITIES_HEADER {
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201 } RT_PCI_CAPABILITIES_HEADER, *PRT_PCI_CAPABILITIES_HEADER;
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204 BOOLEAN pci_clk_req;
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207 // PCIeCap is only differece between B-cut and C-cut.
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208 // Configuration Space offset 72[7:4]
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210 // 1: C cut and later.
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218 u8 pcibridge_busnum;
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219 u8 pcibridge_devnum;
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220 u8 pcibridge_funcnum;
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221 u8 pcibridge_vendor;
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222 u16 pcibridge_vendorid;
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223 u16 pcibridge_deviceid;
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224 u8 pcibridge_pciehdr_offset;
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225 u8 pcibridge_linkctrlreg;
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230 typedef struct _RT_ISR_CONTENT
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237 }RT_ISR_CONTENT, *PRT_ISR_CONTENT;
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239 //#define RegAddr(addr) (addr + 0xB2000000UL)
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240 //some platform macros will def here
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241 static inline void NdisRawWritePortUlong(u32 port, u32 val)
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244 //writel(val, (u8 *)RegAddr(port));
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247 static inline void NdisRawWritePortUchar(u32 port, u8 val)
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250 //writeb(val, (u8 *)RegAddr(port));
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253 static inline void NdisRawReadPortUchar(u32 port, u8 *pval)
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256 //*pval = readb((u8 *)RegAddr(port));
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259 static inline void NdisRawReadPortUshort(u32 port, u16 *pval)
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262 //*pval = readw((u8 *)RegAddr(port));
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265 static inline void NdisRawReadPortUlong(u32 port, u32 *pval)
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268 //*pval = readl((u8 *)RegAddr(port));
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