1 /******************************************************************************
3 * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
19 ******************************************************************************/
20 #ifndef __HAL_DATA_H__
21 #define __HAL_DATA_H__
23 #if 1//def CONFIG_SINGLE_IMG
25 #include "../hal/OUTSRC/phydm_precomp.h"
26 #ifdef CONFIG_BT_COEXIST
27 #include <hal_btcoex.h>
30 #ifdef CONFIG_SDIO_HCI
33 #ifdef CONFIG_GSPI_HCI
37 // <Roger_Notes> For RTL8723 WiFi/BT/GPS multi-function configuration. 2010.10.06.
39 typedef enum _RT_MULTI_FUNC{
40 RT_MULTI_FUNC_NONE = 0x00,
41 RT_MULTI_FUNC_WIFI = 0x01,
42 RT_MULTI_FUNC_BT = 0x02,
43 RT_MULTI_FUNC_GPS = 0x04,
44 }RT_MULTI_FUNC,*PRT_MULTI_FUNC;
46 // <Roger_Notes> For RTL8723 WiFi PDn/GPIO polarity control configuration. 2010.10.08.
48 typedef enum _RT_POLARITY_CTL {
49 RT_POLARITY_LOW_ACT = 0,
50 RT_POLARITY_HIGH_ACT = 1,
51 } RT_POLARITY_CTL, *PRT_POLARITY_CTL;
53 // For RTL8723 regulator mode. by tynli. 2011.01.14.
54 typedef enum _RT_REGULATOR_MODE {
55 RT_SWITCHING_REGULATOR = 0,
57 } RT_REGULATOR_MODE, *PRT_REGULATOR_MODE;
62 typedef enum _INTERFACE_SELECT_PCIE{
63 INTF_SEL0_SOLO_MINICARD = 0, // WiFi solo-mCard
64 INTF_SEL1_BT_COMBO_MINICARD = 1, // WiFi+BT combo-mCard
65 INTF_SEL2_PCIe = 2, // PCIe Card
66 } INTERFACE_SELECT_PCIE, *PINTERFACE_SELECT_PCIE;
69 typedef enum _INTERFACE_SELECT_USB{
70 INTF_SEL0_USB = 0, // USB
71 INTF_SEL1_USB_High_Power = 1, // USB with high power PA
72 INTF_SEL2_MINICARD = 2, // Minicard
73 INTF_SEL3_USB_Solo = 3, // USB solo-Slim module
74 INTF_SEL4_USB_Combo = 4, // USB Combo-Slim module
75 INTF_SEL5_USB_Combo_MF = 5, // USB WiFi+BT Multi-Function Combo, i.e., Proprietary layout(AS-VAU) which is the same as SDIO card
76 } INTERFACE_SELECT_USB, *PINTERFACE_SELECT_USB;
79 //should be sync with INTERFACE_SELECT_USB
80 typedef enum _BOARD_TYPE_8192CUSB{
81 BOARD_USB_DONGLE = 0, // USB dongle
82 BOARD_USB_High_PA = 1, // USB dongle with high power PA
83 BOARD_MINICARD = 2, // Minicard
84 BOARD_USB_SOLO = 3, // USB solo-Slim module
85 BOARD_USB_COMBO = 4, // USB Combo-Slim module
86 } BOARD_TYPE_8192CUSB, *PBOARD_TYPE_8192CUSB;
88 #define SUPPORT_HW_RADIO_DETECT(pHalData) \
89 (pHalData->BoardType == BOARD_MINICARD||\
90 pHalData->BoardType == BOARD_USB_SOLO||\
91 pHalData->BoardType == BOARD_USB_COMBO)
94 typedef enum _RT_AMPDU_BRUST_MODE{
95 RT_AMPDU_BRUST_NONE = 0,
96 RT_AMPDU_BRUST_92D = 1,
97 RT_AMPDU_BRUST_88E = 2,
98 RT_AMPDU_BRUST_8812_4 = 3,
99 RT_AMPDU_BRUST_8812_8 = 4,
100 RT_AMPDU_BRUST_8812_12 = 5,
101 RT_AMPDU_BRUST_8812_15 = 6,
102 RT_AMPDU_BRUST_8723B = 7,
103 }RT_AMPDU_BRUST,*PRT_AMPDU_BRUST_MODE;
105 #define CHANNEL_MAX_NUMBER 14+24+21 // 14 is the max channel number
106 #define CHANNEL_MAX_NUMBER_2G 14
107 #define CHANNEL_MAX_NUMBER_5G 54 // Please refer to "phy_GetChnlGroup8812A" and "Hal_ReadTxPowerInfo8812A"
108 #define CHANNEL_MAX_NUMBER_5G_80M 7
109 #define CHANNEL_GROUP_MAX 3+9 // ch1~3, ch4~9, ch10~14 total three groups
110 #define MAX_PG_GROUP 13
112 // Tx Power Limit Table Size
113 #define MAX_REGULATION_NUM 4
114 #define MAX_RF_PATH_NUM_IN_POWER_LIMIT_TABLE 4
115 #define MAX_2_4G_BANDWITH_NUM 2
116 #define MAX_RATE_SECTION_NUM 10
117 #define MAX_5G_BANDWITH_NUM 4
119 #define MAX_BASE_NUM_IN_PHY_REG_PG_2_4G 10 // CCK:1,OFDM:1, HT:4, VHT:4
120 #define MAX_BASE_NUM_IN_PHY_REG_PG_5G 9 // OFDM:1, HT:4, VHT:4
123 //###### duplicate code,will move to ODM #########
124 //#define IQK_MAC_REG_NUM 4
125 //#define IQK_ADDA_REG_NUM 16
127 //#define IQK_BB_REG_NUM 10
128 #define IQK_BB_REG_NUM_92C 9
129 #define IQK_BB_REG_NUM_92D 10
130 #define IQK_BB_REG_NUM_test 6
132 #define IQK_Matrix_Settings_NUM_92D 1+24+21
134 //#define HP_THERMAL_NUM 8
135 //###### duplicate code,will move to ODM #########
137 #if defined(CONFIG_RTL8192D) || defined(CONFIG_BT_COEXIST)
138 typedef enum _MACPHY_MODE_8192D{
139 SINGLEMAC_SINGLEPHY, //SMSP
140 DUALMAC_DUALPHY, //DMDP
141 DUALMAC_SINGLEPHY, //DMSP
142 }MACPHY_MODE_8192D,*PMACPHY_MODE_8192D;
145 #ifdef CONFIG_USB_RX_AGGREGATION
146 typedef enum _USB_RX_AGG_MODE{
153 //#define MAX_RX_DMA_BUFFER_SIZE 10240 // 10K for 8192C RX DMA buffer
157 #define PAGE_SIZE_128 128
158 #define PAGE_SIZE_256 256
159 #define PAGE_SIZE_512 512
165 #define DYNAMIC_FUNC_BT BIT0
172 //* Upper and Lower Signal threshold for Rate Adaptive*/
173 int UndecoratedSmoothedPWDB;
174 int UndecoratedSmoothedCCK;
175 int EntryMinUndecoratedSmoothedPWDB;
176 int EntryMaxUndecoratedSmoothedPWDB;
177 int MinUndecoratedPWDBForDM;
178 int LastMinUndecoratedPWDBForDM;
180 s32 UndecoratedSmoothedBeacon;
182 //###### duplicate code,will move to ODM #########
184 u8 bDynamicTxPowerEnable;
186 u8 DynamicTxHighPowerLvl;//Add by Jacken Tx Power Control for Near/Far Range 2008/03/06
188 //for tx power tracking
191 u8 bTXPowerTrackingInit;
192 u8 TxPowerTrackControl; //for mp mode, turn off txpwrtracking as default
195 u8 ThermalMeter[2]; // ThermalMeter, index 0 for RFIC0, and 1 for RFIC1
204 u32 APKoutput[2][2]; //path A/B; output1_1a/output1_2a
206 u8 bAPKThermalMeterIgnore;
215 u32 ADDA_backup[IQK_ADDA_REG_NUM];
216 u32 IQK_MAC_backup[IQK_MAC_REG_NUM];
217 u32 IQK_BB_backup_recover[9];
218 u32 IQK_BB_backup[IQK_BB_REG_NUM];
220 u8 PowerIndex_backup[6];
229 u8 ThermalValue_HP[HP_THERMAL_NUM];
230 u8 ThermalValue_HP_index;
239 u32 TXPowerTrackingCallbackCnt; //cosa add for debug
241 u32 prv_traffic_idx; // edca turbo
242 #ifdef CONFIG_RTL8192D
243 u8 ThermalValue_AVG[AVG_THERMAL_NUM];
244 u8 ThermalValue_AVG_index;
245 u8 ThermalValue_RxGain;
246 u8 ThermalValue_Crystal;
247 u8 bReloadtxpowerindex;
260 u32 RegRF3C[2]; //pathA / pathB
262 //###### duplicate code,will move to ODM #########
264 // Add for Reading Initial Data Rate SEL Register 0x484 during watchdog. Using for fill tx desc. 2011.3.21 by Thomas
270 typedef struct hal_com_data
272 HAL_VERSION VersionID;
273 RT_MULTI_FUNC MultiFunc; // For multi-function consideration.
274 RT_POLARITY_CTL PolarityCtl; // For Wifi PDn Polarity control.
275 RT_REGULATOR_MODE RegulatorMode; // switching regulator or LDO
278 u16 FirmwareVersionRev;
279 u16 FirmwareSubVersion;
280 u16 FirmwareSignature;
282 //current WIFI_PHY values
283 WIRELESS_MODE CurrentWirelessMode;
284 CHANNEL_WIDTH CurrentChannelBW;
285 BAND_TYPE CurrentBandType; //0:2.4G, 1:5G
288 u8 CurrentCenterFrequencyIndex1;
289 u8 nCur40MhzPrimeSC;// Control channel sub-carrier
290 u8 nCur80MhzPrimeSC; //used for primary 40MHz of 80MHz mode
294 u16 ForcedDataRate;// Force Data Rate. 0: Auto, 0x02: 1M ~ 0x6C: 54M.
307 u8 DefaultInitialGain[4];
313 #ifdef CONFIG_USB_HCI
317 #ifdef CONFIG_PCI_HCI
323 u8 EEPROMSubCustomerID;
326 u8 EEPROMThermalMeter;
327 u8 EEPROMBluetoothCoexist;
328 u8 EEPROMBluetoothType;
329 u8 EEPROMBluetoothAntNum;
330 u8 EEPROMBluetoothAntIsolation;
331 u8 EEPROMBluetoothRadioShared;
332 u8 bTXPowerDataReadFromEEPORM;
333 u8 bAPKThermalMeterIgnore;
334 u8 bDisableSWChannelPlan; // flag of disable software change channel plan
336 BOOLEAN EepromOrEfuse;
337 u8 EfuseUsedPercentage;
339 //u8 EfuseMap[2][HWSET_MAX_SIZE_JAGUAR];
342 //---------------------------------------------------------------------------------//
344 u8 Index24G_CCK_Base[MAX_RF_PATH][CHANNEL_MAX_NUMBER];
345 u8 Index24G_BW40_Base[MAX_RF_PATH][CHANNEL_MAX_NUMBER];
346 //If only one tx, only BW20 and OFDM are used.
347 s8 CCK_24G_Diff[MAX_RF_PATH][MAX_TX_COUNT];
348 s8 OFDM_24G_Diff[MAX_RF_PATH][MAX_TX_COUNT];
349 s8 BW20_24G_Diff[MAX_RF_PATH][MAX_TX_COUNT];
350 s8 BW40_24G_Diff[MAX_RF_PATH][MAX_TX_COUNT];
352 u8 Index5G_BW40_Base[MAX_RF_PATH][CHANNEL_MAX_NUMBER];
353 u8 Index5G_BW80_Base[MAX_RF_PATH][CHANNEL_MAX_NUMBER_5G_80M];
354 s8 OFDM_5G_Diff[MAX_RF_PATH][MAX_TX_COUNT];
355 s8 BW20_5G_Diff[MAX_RF_PATH][MAX_TX_COUNT];
356 s8 BW40_5G_Diff[MAX_RF_PATH][MAX_TX_COUNT];
357 s8 BW80_5G_Diff[MAX_RF_PATH][MAX_TX_COUNT];
362 u8 TxPwrInPercentage;
364 u8 TxPwrCalibrateRate;
366 // TX power by rate table at most 4RF path.
369 // VHT TX power by rate off setArray =
370 // Band:-2G&5G = 0 / 1
371 // RF: at most 4*4 = ABCD=0/1/2/3
372 // CCK=0 OFDM=1/2 HT-MCS 0-15=3/4/56 VHT=7/8/9/10/11
376 s8 TxPwrByRateOffset[TX_PWR_BY_RATE_NUM_BAND]
377 [TX_PWR_BY_RATE_NUM_RF]
378 [TX_PWR_BY_RATE_NUM_RF]
379 [TX_PWR_BY_RATE_NUM_RATE];
380 //---------------------------------------------------------------------------------//
382 //2 Power Limit Table
383 u8 TxPwrLevelCck[RF_PATH_MAX_92C_88E][CHANNEL_MAX_NUMBER];
384 u8 TxPwrLevelHT40_1S[RF_PATH_MAX_92C_88E][CHANNEL_MAX_NUMBER]; // For HT 40MHZ pwr
385 u8 TxPwrLevelHT40_2S[RF_PATH_MAX_92C_88E][CHANNEL_MAX_NUMBER]; // For HT 40MHZ pwr
386 s8 TxPwrHt20Diff[RF_PATH_MAX_92C_88E][CHANNEL_MAX_NUMBER];// HT 20<->40 Pwr diff
387 u8 TxPwrLegacyHtDiff[RF_PATH_MAX_92C_88E][CHANNEL_MAX_NUMBER];// For HT<->legacy pwr diff
389 // Power Limit Table for 2.4G
390 s8 TxPwrLimit_2_4G[MAX_REGULATION_NUM]
391 [MAX_2_4G_BANDWITH_NUM]
392 [MAX_RATE_SECTION_NUM]
393 [CHANNEL_MAX_NUMBER_2G]
396 // Power Limit Table for 5G
397 s8 TxPwrLimit_5G[MAX_REGULATION_NUM]
398 [MAX_5G_BANDWITH_NUM]
399 [MAX_RATE_SECTION_NUM]
400 [CHANNEL_MAX_NUMBER_5G]
404 // Store the original power by rate value of the base of each rate section of rf path A & B
405 u8 TxPwrByRateBase2_4G[TX_PWR_BY_RATE_NUM_RF]
406 [TX_PWR_BY_RATE_NUM_RF]
407 [MAX_BASE_NUM_IN_PHY_REG_PG_2_4G];
408 u8 TxPwrByRateBase5G[TX_PWR_BY_RATE_NUM_RF]
409 [TX_PWR_BY_RATE_NUM_RF]
410 [MAX_BASE_NUM_IN_PHY_REG_PG_5G];
413 u8 PwrGroupHT20[RF_PATH_MAX_92C_88E][CHANNEL_MAX_NUMBER];
414 u8 PwrGroupHT40[RF_PATH_MAX_92C_88E][CHANNEL_MAX_NUMBER];
420 u8 LegacyHTTxPowerDiff;// Legacy to HT rate power diff
421 // The current Tx Power Level
422 u8 CurrentCckTxPwrIdx;
423 u8 CurrentOfdm24GTxPwrIdx;
424 u8 CurrentBW2024GTxPwrIdx;
425 u8 CurrentBW4024GTxPwrIdx;
427 // Read/write are allow for following hardware information variables
429 u32 MCSTxPowerLevelOriginalOffset[MAX_PG_GROUP][16];
430 u32 CCKTxPowerLevelOriginalOffset;
433 u32 AntennaTxPath; // Antenna path Tx
434 u32 AntennaRxPath; // Antenna path Rx
452 BOOLEAN bLCKInProgress;
456 BOOLEAN bChnlBWInitialized;
459 u8 bLedOpenDrain; // Support Open-drain arrangement for controlling the LED. Added by Roger, 2009.10.16.
460 u8 TxPowerTrackControl; //for mp mode, turn off txpwrtracking as default
461 u8 b1x1RecvCombine; // for 1T1R receive combining
463 u32 AcParam_BE; //Original parameter for BE, use for EDCA turbo.
465 BB_REGISTER_DEFINITION_T PHYRegDef[4]; //Radio A/B/C/D
472 //for host message to fw
477 // Beacon function related global variable.
489 u8 ant_path; //for 8723B s0/s1 selection
491 u8 u1ForcedIgiLb; // forced IGI lower bound
493 u8 bDumpRxPkt;//for debug
494 u8 bDumpTxPkt;//for debug
495 u8 FwRsvdPageStartOffset; //2010.06.23. Added by tynli. Reserve page start offset except beacon in TxQ.
497 // 2010/08/09 MH Add CU power down mode.
500 // Add for dual MAC 0--Mac0 1--Mac1
506 // 2010/12/10 MH Add for USB aggreation mode dynamic shceme.
507 BOOLEAN UsbRxHighSpeedMode;
509 // 2010/11/22 MH Add for slim combo debug mode selective.
510 // This is used for fix the drawback of CU TSMC-A/UMC-A cut. HW auto suspend ability. Close BT clock.
511 BOOLEAN SlimComboDbg;
519 // Auto FSM to Turn On, include clock, isolation, power control for MAC only
521 u8 bDisableTXPowerTraining;
523 struct submit_ctx iqk_sctx;
525 RT_AMPDU_BRUST AMPDUBurstMode; //92C maybe not use, but for compile successfully
527 #if defined (CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
529 // For SDIO Interface HAL related
536 // u32 IntrMaskToSet[1];
537 // LOG_INTERRUPT InterruptLog;
542 // SDIO Tx FIFO related.
544 // HIQ, MID, LOW, PUB free pages; padapter->xmitpriv.free_txpg
545 u8 SdioTxFIFOFreePage[SDIO_TX_FREE_PG_QUEUE];
546 _lock SdioTxFIFOFreePageLock;
547 u8 SdioTxOQTMaxFreeSpace;
548 u8 SdioTxOQTFreeSpace;
552 // SDIO Rx FIFO related.
557 u32 sdio_tx_max_len[SDIO_MAX_TX_QUEUE];// H, N, L, used for sdio tx aggregation max length per queue
558 #endif //CONFIG_SDIO_HCI
560 #ifdef CONFIG_USB_HCI
562 BOOLEAN bSupportUSB3;
564 // Interrupt relatd register information.
565 u32 IntArray[3];//HISR0,HISR1,HSISR
568 #ifdef CONFIG_USB_TX_AGGREGATION
571 #endif // CONFIG_USB_TX_AGGREGATION
573 #ifdef CONFIG_USB_RX_AGGREGATION
574 u16 HwRxPageSize; // Hardware setting
575 u32 MaxUsbRxAggBlock;
577 USB_RX_AGG_MODE UsbRxAggMode;
578 u8 UsbRxAggBlockCount; //FOR USB Mode, USB Block count. Block size is 512-byte in hight speed and 64-byte in full speed
579 u8 UsbRxAggBlockTimeout;
580 u8 UsbRxAggPageCount; //FOR DMA Mode, 8192C DMA page count
581 u8 UsbRxAggPageTimeout;
585 #endif//CONFIG_USB_RX_AGGREGATION
586 #endif //CONFIG_USB_HCI
589 #ifdef CONFIG_PCI_HCI
593 u16 EEPROMChannelPlan;
599 u32 IntrMaskToSet[2];
605 u32 IntrMaskDefault[2];
607 BOOLEAN bL1OffSupport;
608 BOOLEAN bSupportBackDoor;
611 //u8 bIQKInitialized;
613 u8 bInterruptMigration;
617 #endif //CONFIG_PCI_HCI
619 struct dm_priv dmpriv;
621 #ifdef DBG_CONFIG_ERROR_DETECT
622 struct sreset_priv srestpriv;
623 #endif //#ifdef DBG_CONFIG_ERROR_DETECT
625 #ifdef CONFIG_BT_COEXIST
626 // For bluetooth co-existance
627 BT_COEXIST bt_coexist;
628 #ifdef CONFIG_RTL8723A
630 #endif // CONFIG_RTL8723A
631 #endif // CONFIG_BT_COEXIST
633 #if defined(CONFIG_RTL8723A) || defined(CONFIG_RTL8723B)
634 #ifndef CONFIG_PCI_HCI // mutual exclusive with PCI -- so they're SDIO and GSPI
635 // Interrupt relatd register information.
639 #endif //endif CONFIG_RTL8723A
642 #if defined(CONFIG_RTL8192C) ||defined(CONFIG_RTL8192D)
646 u8 EEPROMChnlAreaTxPwrCCK[2][3];
647 u8 EEPROMChnlAreaTxPwrHT40_1S[2][3];
648 u8 EEPROMChnlAreaTxPwrHT40_2SDiff[2][3];
649 u8 EEPROMPwrLimitHT20[3];
650 u8 EEPROMPwrLimitHT40[3];
651 #ifdef CONFIG_RTL8192D
652 MACPHY_MODE_8192D MacPhyMode92D;
653 BAND_TYPE CurrentBandType92D; //0:2.4G, 1:5G
654 BAND_TYPE BandSet92D;
655 BOOLEAN bMasterOfDMSP;
656 BOOLEAN bSlaveOfDMSP;
658 IQK_MATRIX_REGS_SETTING IQKMatrixRegSetting[IQK_Matrix_Settings_NUM_92D];
659 #ifdef CONFIG_DUALMAC_CONCURRENT
660 BOOLEAN bInModeSwitchProcess;
662 u8 AutoLoadStatusFor8192D;
666 u8 InternalPA5G[2]; //pathA / pathB
667 BOOLEAN bPhyValueInitReady;
668 BOOLEAN bLoadIMRandIQKSettingFor2G;// True if IMR or IQK have done for 2.4G in scan progress
673 BOOLEAN bEarlyModeEnable;
674 BOOLEAN bSupportRemoteWakeUp;
676 u8 RTSInitRate; // 2010.11.24.by tynli.
677 #endif //CONFIG_RTL8192D
679 #endif //defined(CONFIG_RTL8192C) ||defined(CONFIG_RTL8192D)
681 #ifdef CONFIG_LOAD_PHY_PARA_FROM_FILE
682 char para_file_buf[MAX_PARA_FILE_BUF_LEN];
690 u32 bb_phy_reg_pg_len;
692 u32 bb_phy_reg_mp_len;
697 char *rf_tx_pwr_track;
698 u32 rf_tx_pwr_track_len;
700 u32 rf_tx_pwr_lmt_len;
703 #ifdef CONFIG_BACKGROUND_NOISE_MONITOR
704 s16 noise[ODM_MAX_CHANNEL_NUM];
710 } HAL_DATA_COMMON, *PHAL_DATA_COMMON;
713 typedef struct hal_com_data HAL_DATA_TYPE, *PHAL_DATA_TYPE;
714 #define GET_HAL_DATA(__pAdapter) ((HAL_DATA_TYPE *)((__pAdapter)->HalData))
715 #define GET_HAL_RFPATH_NUM(__pAdapter) (((HAL_DATA_TYPE *)((__pAdapter)->HalData))->NumTotalRFPath )
716 #define RT_GetInterfaceSelection(_Adapter) (GET_HAL_DATA(_Adapter)->InterfaceSel)
717 #define GET_RF_TYPE(__pAdapter) (GET_HAL_DATA(__pAdapter)->rf_type)
721 #endif //__HAL_DATA_H__