drivers/net/wireless/rockchip_wlan/rtl8723bs/include/hal_data.h

   1 /******************************************************************************
   2  *
   3  * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of version 2 of the GNU General Public License as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program; if not, write to the Free Software Foundation, Inc.,
  16  * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  17  *
  18  *
  19  ******************************************************************************/
  20 #ifndef __HAL_DATA_H__
  21 #define __HAL_DATA_H__
  22
  23 #if 1//def  CONFIG_SINGLE_IMG
  24
  25 #include "../hal/OUTSRC/odm_precomp.h"
  26 #ifdef CONFIG_BT_COEXIST
  27 #include <hal_btcoex.h>
  28 #endif
  29
  30 //
  31 // <Roger_Notes> For RTL8723 WiFi/BT/GPS multi-function configuration. 2010.10.06.
  32 //
  33 typedef enum _RT_MULTI_FUNC{
  34         RT_MULTI_FUNC_NONE      = 0x00,
  35         RT_MULTI_FUNC_WIFI      = 0x01,
  36         RT_MULTI_FUNC_BT                = 0x02,
  37         RT_MULTI_FUNC_GPS       = 0x04,
  38 }RT_MULTI_FUNC,*PRT_MULTI_FUNC;
  39 //
  40 // <Roger_Notes> For RTL8723 WiFi PDn/GPIO polarity control configuration. 2010.10.08.
  41 //
  42 typedef enum _RT_POLARITY_CTL {
  43         RT_POLARITY_LOW_ACT     = 0,
  44         RT_POLARITY_HIGH_ACT    = 1,
  45 } RT_POLARITY_CTL, *PRT_POLARITY_CTL;
  46
  47 // For RTL8723 regulator mode. by tynli. 2011.01.14.
  48 typedef enum _RT_REGULATOR_MODE {
  49         RT_SWITCHING_REGULATOR  = 0,
  50         RT_LDO_REGULATOR                        = 1,
  51 } RT_REGULATOR_MODE, *PRT_REGULATOR_MODE;
  52
  53 //
  54 // Interface type.
  55 //
  56 typedef enum _INTERFACE_SELECT_PCIE{
  57         INTF_SEL0_SOLO_MINICARD                 = 0,            // WiFi solo-mCard
  58         INTF_SEL1_BT_COMBO_MINICARD             = 1,            // WiFi+BT combo-mCard
  59         INTF_SEL2_PCIe                                          = 2,            // PCIe Card
  60 } INTERFACE_SELECT_PCIE, *PINTERFACE_SELECT_PCIE;
  61
  62
  63 typedef enum _INTERFACE_SELECT_USB{
  64         INTF_SEL0_USB                           = 0,            // USB
  65         INTF_SEL1_USB_High_Power        = 1,            // USB with high power PA
  66         INTF_SEL2_MINICARD                      = 2,            // Minicard
  67         INTF_SEL3_USB_Solo              = 3,            // USB solo-Slim module
  68         INTF_SEL4_USB_Combo             = 4,            // USB Combo-Slim module
  69         INTF_SEL5_USB_Combo_MF  = 5,            // USB WiFi+BT Multi-Function Combo, i.e., Proprietary layout(AS-VAU) which is the same as SDIO card
  70 } INTERFACE_SELECT_USB, *PINTERFACE_SELECT_USB;
  71
  72 typedef enum _RT_AMPDU_BRUST_MODE{
  73         RT_AMPDU_BRUST_NONE             = 0,
  74         RT_AMPDU_BRUST_92D              = 1,
  75         RT_AMPDU_BRUST_88E              = 2,
  76         RT_AMPDU_BRUST_8812_4   = 3,
  77         RT_AMPDU_BRUST_8812_8   = 4,
  78         RT_AMPDU_BRUST_8812_12  = 5,
  79         RT_AMPDU_BRUST_8812_15  = 6,
  80         RT_AMPDU_BRUST_8723B            = 7,
  81 }RT_AMPDU_BRUST,*PRT_AMPDU_BRUST_MODE;
  82
  83 #define CHANNEL_MAX_NUMBER                      14+24+21        // 14 is the max channel number
  84 #define CHANNEL_MAX_NUMBER_2G           14
  85 #define CHANNEL_MAX_NUMBER_5G           54                      // Please refer to "phy_GetChnlGroup8812A" and "Hal_ReadTxPowerInfo8812A"
  86 #define CHANNEL_MAX_NUMBER_5G_80M       7
  87 #define CHANNEL_GROUP_MAX                               3+9     // ch1~3, ch4~9, ch10~14 total three groups
  88 #define MAX_PG_GROUP                                    13
  89
  90 // Tx Power Limit Table Size
  91 #define MAX_REGULATION_NUM                                              4
  92 #define MAX_RF_PATH_NUM_IN_POWER_LIMIT_TABLE    4
  93 #define MAX_2_4G_BANDWITH_NUM                                   2
  94 #define MAX_RATE_SECTION_NUM                                            10
  95 #define MAX_5G_BANDWITH_NUM                                             4
  96
  97 #define MAX_BASE_NUM_IN_PHY_REG_PG_2_4G                 10 //  CCK:1,OFDM:1, HT:4, VHT:4
  98 #define MAX_BASE_NUM_IN_PHY_REG_PG_5G                   9 // OFDM:1, HT:4, VHT:4
  99
 100
 101 //###### duplicate code,will move to ODM #########
 102 //#define IQK_MAC_REG_NUM               4
 103 //#define IQK_ADDA_REG_NUM              16
 104
 105 //#define IQK_BB_REG_NUM                        10
 106 #define IQK_BB_REG_NUM_92C      9
 107 #define IQK_BB_REG_NUM_92D      10
 108 #define IQK_BB_REG_NUM_test     6
 109
 110 #define IQK_Matrix_Settings_NUM_92D     1+24+21
 111
 112 //#define HP_THERMAL_NUM                8
 113 //###### duplicate code,will move to ODM #########
 114
 115 #if defined(CONFIG_RTL8192D) || defined(CONFIG_BT_COEXIST)
 116 typedef enum _MACPHY_MODE_8192D{
 117         SINGLEMAC_SINGLEPHY,    //SMSP
 118         DUALMAC_DUALPHY,                //DMDP
 119         DUALMAC_SINGLEPHY,      //DMSP
 120 }MACPHY_MODE_8192D,*PMACPHY_MODE_8192D;
 121 #endif
 122
 123 #ifdef CONFIG_USB_RX_AGGREGATION
 124 typedef enum _USB_RX_AGG_MODE{
 125         USB_RX_AGG_DISABLE,
 126         USB_RX_AGG_DMA,
 127         USB_RX_AGG_USB,
 128         USB_RX_AGG_MIX
 129 }USB_RX_AGG_MODE;
 130
 131 //#define MAX_RX_DMA_BUFFER_SIZE        10240           // 10K for 8192C RX DMA buffer
 132
 133 #endif
 134
 135 struct dm_priv
 136 {
 137         u8      DM_Type;
 138
 139 #define DYNAMIC_FUNC_BT BIT0
 140
 141         u8      DMFlag;
 142         u8      InitDMFlag;
 143         //u8   RSVD_1;
 144
 145         u32     InitODMFlag;
 146         //* Upper and Lower Signal threshold for Rate Adaptive*/
 147         int     UndecoratedSmoothedPWDB;
 148         int     UndecoratedSmoothedCCK;
 149         int     EntryMinUndecoratedSmoothedPWDB;
 150         int     EntryMaxUndecoratedSmoothedPWDB;
 151         int     MinUndecoratedPWDBForDM;
 152         int     LastMinUndecoratedPWDBForDM;
 153
 154         s32     UndecoratedSmoothedBeacon;
 155
 156 //###### duplicate code,will move to ODM #########
 157         //for High Power
 158         u8      bDynamicTxPowerEnable;
 159         u8      LastDTPLvl;
 160         u8      DynamicTxHighPowerLvl;//Add by Jacken Tx Power Control for Near/Far Range 2008/03/06
 161
 162         //for tx power tracking
 163         u8      bTXPowerTracking;
 164         u8      TXPowercount;
 165         u8      bTXPowerTrackingInit;
 166         u8      TxPowerTrackControl;    //for mp mode, turn off txpwrtracking as default
 167         u8      TM_Trigger;
 168
 169         u8      ThermalMeter[2];                                // ThermalMeter, index 0 for RFIC0, and 1 for RFIC1
 170         u8      ThermalValue;
 171         u8      ThermalValue_LCK;
 172         u8      ThermalValue_IQK;
 173         u8      ThermalValue_DPK;
 174         u8      bRfPiEnable;
 175         //u8   RSVD_2;
 176
 177         //for APK
 178         u32     APKoutput[2][2];        //path A/B; output1_1a/output1_2a
 179         u8      bAPKdone;
 180         u8      bAPKThermalMeterIgnore;
 181         u8      bDPdone;
 182         u8      bDPPathAOK;
 183         u8      bDPPathBOK;
 184         //u8   RSVD_3;
 185         //u8   RSVD_4;
 186         //u8   RSVD_5;
 187
 188         //for IQK
 189         u32     ADDA_backup[IQK_ADDA_REG_NUM];
 190         u32     IQK_MAC_backup[IQK_MAC_REG_NUM];
 191         u32     IQK_BB_backup_recover[9];
 192         u32     IQK_BB_backup[IQK_BB_REG_NUM];
 193
 194         u8      PowerIndex_backup[6];
 195         u8      OFDM_index[2];
 196
 197         u8      bCCKinCH14;
 198         u8      CCK_index;
 199         u8      bDoneTxpower;
 200         u8      CCK_index_HP;
 201
 202         u8      OFDM_index_HP[2];
 203         u8      ThermalValue_HP[HP_THERMAL_NUM];
 204         u8      ThermalValue_HP_index;
 205         //u8   RSVD_6;
 206
 207         //for TxPwrTracking2
 208         s32     RegE94;
 209         s32  RegE9C;
 210         s32     RegEB4;
 211         s32     RegEBC;
 212
 213         u32     TXPowerTrackingCallbackCnt;     //cosa add for debug
 214
 215         u32     prv_traffic_idx; // edca turbo
 216 #ifdef CONFIG_RTL8192D
 217         u8      ThermalValue_AVG[AVG_THERMAL_NUM];
 218         u8      ThermalValue_AVG_index;
 219         u8      ThermalValue_RxGain;
 220         u8      ThermalValue_Crystal;
 221         u8      bReloadtxpowerindex;
 222
 223         u32     RegD04_MP;
 224
 225         u8      RegC04_MP;
 226         u8      Delta_IQK;
 227         u8      Delta_LCK;
 228         //u8   RSVD_7;
 229
 230         BOOLEAN bDPKdone[2];
 231         //u16 RSVD_8;
 232
 233         u32     RegA24;
 234         u32     RegRF3C[2];     //pathA / pathB
 235 #endif
 236 //###### duplicate code,will move to ODM #########
 237
 238         // Add for Reading Initial Data Rate SEL Register 0x484 during watchdog. Using for fill tx desc. 2011.3.21 by Thomas
 239         u8      INIDATA_RATE[32];
 240 };
 241
 242
 243 typedef struct hal_com_data
 244 {
 245         HAL_VERSION                     VersionID;
 246         RT_MULTI_FUNC           MultiFunc; // For multi-function consideration.
 247         RT_POLARITY_CTL         PolarityCtl; // For Wifi PDn Polarity control.
 248         RT_REGULATOR_MODE       RegulatorMode; // switching regulator or LDO
 249
 250         u16     FirmwareVersion;
 251         u16     FirmwareVersionRev;
 252         u16     FirmwareSubVersion;
 253         u16     FirmwareSignature;
 254
 255         //current WIFI_PHY values
 256         WIRELESS_MODE           CurrentWirelessMode;
 257         CHANNEL_WIDTH   CurrentChannelBW;
 258         BAND_TYPE                       CurrentBandType;        //0:2.4G, 1:5G
 259         BAND_TYPE                       BandSet;
 260         u8      CurrentChannel;
 261         u8      CurrentCenterFrequencyIndex1;
 262         u8      nCur40MhzPrimeSC;// Control channel sub-carrier
 263         u8      nCur80MhzPrimeSC;   //used for primary 40MHz of 80MHz mode
 264
 265         u16     CustomerID;
 266         u16     BasicRateSet;
 267         u16 ForcedDataRate;// Force Data Rate. 0: Auto, 0x02: 1M ~ 0x6C: 54M.
 268         u32     ReceiveConfig;
 269
 270         //rf_ctrl
 271         u8      rf_chip;
 272         u8      rf_type;
 273         u8      PackageType;
 274         u8      NumTotalRFPath;
 275
 276         u8      InterfaceSel;
 277         u8      framesync;
 278         u32     framesyncC34;
 279         u8      framesyncMonitor;
 280         u8      DefaultInitialGain[4];
 281         //
 282         // EEPROM setting.
 283         //
 284         u16     EEPROMVID;
 285         u16     EEPROMSVID;
 286 #ifdef CONFIG_USB_HCI
 287         u16     EEPROMPID;
 288         u16     EEPROMSDID;
 289 #endif
 290 #ifdef CONFIG_PCI_HCI
 291         u16     EEPROMDID;
 292         u16     EEPROMSMID;
 293 #endif
 294
 295         u8      EEPROMCustomerID;
 296         u8      EEPROMSubCustomerID;
 297         u8      EEPROMVersion;
 298         u8      EEPROMRegulatory;
 299         u8      EEPROMThermalMeter;
 300         u8      EEPROMBluetoothCoexist;
 301         u8      EEPROMBluetoothType;
 302         u8      EEPROMBluetoothAntNum;
 303         u8      EEPROMBluetoothAntIsolation;
 304         u8      EEPROMBluetoothRadioShared;
 305         u8      bTXPowerDataReadFromEEPORM;
 306         u8      bAPKThermalMeterIgnore;
 307         u8      bDisableSWChannelPlan; // flag of disable software change channel plan
 308
 309         BOOLEAN                 EepromOrEfuse;
 310         u8                              EfuseUsedPercentage;
 311         u16                             EfuseUsedBytes;
 312         //u8                            EfuseMap[2][HWSET_MAX_SIZE_JAGUAR];
 313         EFUSE_HAL               EfuseHal;
 314
 315         //---------------------------------------------------------------------------------//
 316         //3 [2.4G]
 317         u8      Index24G_CCK_Base[MAX_RF_PATH][CHANNEL_MAX_NUMBER];
 318         u8      Index24G_BW40_Base[MAX_RF_PATH][CHANNEL_MAX_NUMBER];
 319         //If only one tx, only BW20 and OFDM are used.
 320         s8      CCK_24G_Diff[MAX_RF_PATH][MAX_TX_COUNT];
 321         s8      OFDM_24G_Diff[MAX_RF_PATH][MAX_TX_COUNT];
 322         s8      BW20_24G_Diff[MAX_RF_PATH][MAX_TX_COUNT];
 323         s8      BW40_24G_Diff[MAX_RF_PATH][MAX_TX_COUNT];
 324         //3 [5G]
 325         u8      Index5G_BW40_Base[MAX_RF_PATH][CHANNEL_MAX_NUMBER];
 326         u8      Index5G_BW80_Base[MAX_RF_PATH][CHANNEL_MAX_NUMBER_5G_80M];
 327         s8      OFDM_5G_Diff[MAX_RF_PATH][MAX_TX_COUNT];
 328         s8      BW20_5G_Diff[MAX_RF_PATH][MAX_TX_COUNT];
 329         s8      BW40_5G_Diff[MAX_RF_PATH][MAX_TX_COUNT];
 330         s8      BW80_5G_Diff[MAX_RF_PATH][MAX_TX_COUNT];
 331
 332         u8      Regulation2_4G;
 333         u8      Regulation5G;
 334
 335         u8      TxPwrInPercentage;
 336
 337         u8      TxPwrCalibrateRate;
 338         //
 339         // TX power by rate table at most 4RF path.
 340         // The register is
 341         //
 342         // VHT TX power by rate off setArray =
 343         // Band:-2G&5G = 0 / 1
 344         // RF: at most 4*4 = ABCD=0/1/2/3
 345         // CCK=0 OFDM=1/2 HT-MCS 0-15=3/4/56 VHT=7/8/9/10/11
 346         //
 347         u8      TxPwrByRateTable;
 348         u8      TxPwrByRateBand;
 349         s8      TxPwrByRateOffset[TX_PWR_BY_RATE_NUM_BAND]
 350                                                  [TX_PWR_BY_RATE_NUM_RF]
 351                                                  [TX_PWR_BY_RATE_NUM_RF]
 352                                                  [TX_PWR_BY_RATE_NUM_RATE];
 353         //---------------------------------------------------------------------------------//
 354
 355         //2 Power Limit Table
 356         u8      TxPwrLevelCck[RF_PATH_MAX_92C_88E][CHANNEL_MAX_NUMBER];
 357         u8      TxPwrLevelHT40_1S[RF_PATH_MAX_92C_88E][CHANNEL_MAX_NUMBER];     // For HT 40MHZ pwr
 358         u8      TxPwrLevelHT40_2S[RF_PATH_MAX_92C_88E][CHANNEL_MAX_NUMBER];     // For HT 40MHZ pwr
 359         u8      TxPwrHt20Diff[RF_PATH_MAX_92C_88E][CHANNEL_MAX_NUMBER];// HT 20<->40 Pwr diff
 360         u8      TxPwrLegacyHtDiff[RF_PATH_MAX_92C_88E][CHANNEL_MAX_NUMBER];// For HT<->legacy pwr diff
 361
 362         // Power Limit Table for 2.4G
 363         u8      TxPwrLimit_2_4G[MAX_REGULATION_NUM]
 364                                                 [MAX_2_4G_BANDWITH_NUM]
 365                                         [MAX_RATE_SECTION_NUM]
 366                                         [CHANNEL_MAX_NUMBER_2G]
 367                                                 [MAX_RF_PATH_NUM];
 368
 369         // Power Limit Table for 5G
 370         u8      TxPwrLimit_5G[MAX_REGULATION_NUM]
 371                                                 [MAX_5G_BANDWITH_NUM]
 372                                                 [MAX_RATE_SECTION_NUM]
 373                                                 [CHANNEL_MAX_NUMBER_5G]
 374                                                 [MAX_RF_PATH_NUM];
 375
 376
 377         // Store the original power by rate value of the base of each rate section of rf path A & B
 378         u8      TxPwrByRateBase2_4G[TX_PWR_BY_RATE_NUM_RF]
 379                                                 [TX_PWR_BY_RATE_NUM_RF]
 380                                                 [MAX_BASE_NUM_IN_PHY_REG_PG_2_4G];
 381         u8      TxPwrByRateBase5G[TX_PWR_BY_RATE_NUM_RF]
 382                                                 [TX_PWR_BY_RATE_NUM_RF]
 383                                                 [MAX_BASE_NUM_IN_PHY_REG_PG_5G];
 384
 385         // For power group
 386         u8      PwrGroupHT20[RF_PATH_MAX_92C_88E][CHANNEL_MAX_NUMBER];
 387         u8      PwrGroupHT40[RF_PATH_MAX_92C_88E][CHANNEL_MAX_NUMBER];
 388
 389
 390
 391
 392         u8      PGMaxGroup;
 393         u8      LegacyHTTxPowerDiff;// Legacy to HT rate power diff
 394         // The current Tx Power Level
 395         u8      CurrentCckTxPwrIdx;
 396         u8      CurrentOfdm24GTxPwrIdx;
 397         u8      CurrentBW2024GTxPwrIdx;
 398         u8      CurrentBW4024GTxPwrIdx;
 399
 400         // Read/write are allow for following hardware information variables
 401         u8      pwrGroupCnt;
 402         u32     MCSTxPowerLevelOriginalOffset[MAX_PG_GROUP][16];
 403         u32     CCKTxPowerLevelOriginalOffset;
 404
 405         u8      CrystalCap;
 406         u32     AntennaTxPath;                                  // Antenna path Tx
 407         u32     AntennaRxPath;                                  // Antenna path Rx
 408
 409         u8      PAType_2G;
 410         u8      PAType_5G;
 411         u8      LNAType_2G;
 412         u8      LNAType_5G;
 413         u8      ExternalPA_2G;
 414         u8      ExternalLNA_2G;
 415         u8      ExternalPA_5G;
 416         u8      ExternalLNA_5G;
 417         u8      TypeGLNA;
 418         u8      TypeGPA;
 419         u8      TypeALNA;
 420         u8      TypeAPA;
 421         u8      RFEType;
 422         u8      BoardType;
 423         u8      ExternalPA;
 424         u8      bIQKInitialized;
 425         BOOLEAN         bLCKInProgress;
 426
 427         BOOLEAN         bSwChnl;
 428         BOOLEAN         bSetChnlBW;
 429         BOOLEAN         bChnlBWInitialized;
 430         BOOLEAN         bNeedIQK;
 431
 432         u8      bLedOpenDrain; // Support Open-drain arrangement for controlling the LED. Added by Roger, 2009.10.16.
 433         u8      TxPowerTrackControl; //for mp mode, turn off txpwrtracking as default
 434         u8      b1x1RecvCombine;        // for 1T1R receive combining
 435
 436         u32     AcParam_BE; //Original parameter for BE, use for EDCA turbo.
 437
 438         BB_REGISTER_DEFINITION_T        PHYRegDef[4];   //Radio A/B/C/D
 439
 440         u32     RfRegChnlVal[2];
 441
 442         //RDG enable
 443         BOOLEAN  bRDGEnable;
 444
 445         //for host message to fw
 446         u8      LastHMEBoxNum;
 447
 448         u8      fw_ractrl;
 449         u8      RegTxPause;
 450         // Beacon function related global variable.
 451         u8      RegBcnCtrlVal;
 452         u8      RegFwHwTxQCtrl;
 453         u8      RegReg542;
 454         u8      RegCR_1;
 455         u8      Reg837;
 456         u8      RegRFPathS1;
 457         u16     RegRRSR;
 458
 459         u8      CurAntenna;
 460         u8      AntDivCfg;
 461         u8      AntDetection;
 462         u8      TRxAntDivType;
 463
 464         u8      u1ForcedIgiLb;                  // forced IGI lower bound
 465
 466         u8      bDumpRxPkt;//for debug
 467         u8      bDumpTxPkt;//for debug
 468         u8      FwRsvdPageStartOffset; //2010.06.23. Added by tynli. Reserve page start offset except beacon in TxQ.
 469
 470         // 2010/08/09 MH Add CU power down mode.
 471         BOOLEAN         pwrdown;
 472
 473         // Add for dual MAC  0--Mac0 1--Mac1
 474         u32     interfaceIndex;
 475
 476         u8      OutEpQueueSel;
 477         u8      OutEpNumber;
 478
 479         // 2010/12/10 MH Add for USB aggreation mode dynamic shceme.
 480         BOOLEAN         UsbRxHighSpeedMode;
 481
 482         // 2010/11/22 MH Add for slim combo debug mode selective.
 483         // This is used for fix the drawback of CU TSMC-A/UMC-A cut. HW auto suspend ability. Close BT clock.
 484         BOOLEAN         SlimComboDbg;
 485
 486 #ifdef CONFIG_P2P
 487         u8      p2p_ps_offload;
 488 #endif
 489
 490         u8      AMPDUDensity;
 491
 492         // Auto FSM to Turn On, include clock, isolation, power control for MAC only
 493         u8      bMacPwrCtrlOn;
 494
 495         u8      RegIQKFWOffload;
 496         struct submit_ctx       iqk_sctx;
 497
 498         RT_AMPDU_BRUST          AMPDUBurstMode; //92C maybe not use, but for compile successfully
 499
 500 #ifdef CONFIG_SDIO_HCI
 501         //
 502         // For SDIO Interface HAL related
 503         //
 504
 505         //
 506         // SDIO ISR Related
 507         //
 508 //      u32                     IntrMask[1];
 509 //      u32                     IntrMaskToSet[1];
 510 //      LOG_INTERRUPT           InterruptLog;
 511         u32                     sdio_himr;
 512         u32                     sdio_hisr;
 513
 514         //
 515         // SDIO Tx FIFO related.
 516         //
 517         // HIQ, MID, LOW, PUB free pages; padapter->xmitpriv.free_txpg
 518         u8                      SdioTxFIFOFreePage[SDIO_TX_FREE_PG_QUEUE];
 519         _lock           SdioTxFIFOFreePageLock;
 520
 521         //
 522         // SDIO Rx FIFO related.
 523         //
 524         u8                      SdioRxFIFOCnt;
 525         u16                     SdioRxFIFOSize;
 526 #endif //CONFIG_SDIO_HCI
 527
 528 #ifdef CONFIG_USB_HCI
 529         u32     UsbBulkOutSize;
 530         BOOLEAN         bSupportUSB3;
 531
 532         // Interrupt relatd register information.
 533         u32     IntArray[3];//HISR0,HISR1,HSISR
 534         u32     IntrMask[3];
 535         u8      C2hArray[16];
 536         #ifdef CONFIG_USB_TX_AGGREGATION
 537         u8      UsbTxAggMode;
 538         u8      UsbTxAggDescNum;
 539         #endif // CONFIG_USB_TX_AGGREGATION
 540
 541         #ifdef CONFIG_USB_RX_AGGREGATION
 542         u16     HwRxPageSize;                           // Hardware setting
 543         u32     MaxUsbRxAggBlock;
 544
 545         USB_RX_AGG_MODE UsbRxAggMode;
 546         u8      UsbRxAggBlockCount;             //FOR USB Mode, USB Block count. Block size is 512-byte in hight speed and 64-byte in full speed
 547         u8      UsbRxAggBlockTimeout;
 548         u8      UsbRxAggPageCount;                      //FOR DMA Mode, 8192C DMA page count
 549         u8      UsbRxAggPageTimeout;
 550
 551         u8      RegAcUsbDmaSize;
 552         u8      RegAcUsbDmaTime;
 553         #endif//CONFIG_USB_RX_AGGREGATION
 554 #endif //CONFIG_USB_HCI
 555
 556
 557 #ifdef CONFIG_PCI_HCI
 558         //
 559         // EEPROM setting.
 560         //
 561         u16     EEPROMChannelPlan;
 562
 563         u8      EEPROMTSSI[2];
 564         u8      EEPROMBoardType;
 565         u32     TransmitConfig;
 566
 567         u32     IntrMaskToSet[2];
 568         u32     IntArray[2];
 569         u32     IntrMask[2];
 570         u32     SysIntArray[1];
 571         u32     SysIntrMask[1];
 572         u32     IntrMaskReg[2];
 573         u32     IntrMaskDefault[2];
 574
 575         BOOLEAN  bL1OffSupport;
 576         BOOLEAN bSupportBackDoor;
 577
 578         u8      bDefaultAntenna;
 579         //u8    bIQKInitialized;
 580
 581         u8      bInterruptMigration;
 582         u8      bDisableTxInt;
 583         u8      bGpioHwWpsPbc;
 584 #endif //CONFIG_PCI_HCI
 585
 586         struct dm_priv  dmpriv;
 587         DM_ODM_T                odmpriv;
 588 #ifdef DBG_CONFIG_ERROR_DETECT
 589         struct sreset_priv srestpriv;
 590 #endif //#ifdef DBG_CONFIG_ERROR_DETECT
 591
 592 #ifdef CONFIG_BT_COEXIST
 593         // For bluetooth co-existance
 594         BT_COEXIST              bt_coexist;
 595 #ifdef CONFIG_RTL8723A
 596         u8                              bAntennaDetected;
 597 #endif // CONFIG_RTL8723A
 598 #endif // CONFIG_BT_COEXIST
 599
 600 #if defined(CONFIG_RTL8723A) || defined(CONFIG_RTL8723B)
 601         // Interrupt relatd register information.
 602         u32                     SysIntrStatus;
 603         u32                     SysIntrMask;
 604 #endif //endif CONFIG_RTL8723A
 605
 606
 607 #if defined(CONFIG_RTL8192C) ||defined(CONFIG_RTL8192D)
 608
 609         u8      BluetoothCoexist;
 610
 611         u8      EEPROMChnlAreaTxPwrCCK[2][3];
 612         u8      EEPROMChnlAreaTxPwrHT40_1S[2][3];
 613         u8      EEPROMChnlAreaTxPwrHT40_2SDiff[2][3];
 614         u8      EEPROMPwrLimitHT20[3];
 615         u8      EEPROMPwrLimitHT40[3];
 616         #ifdef CONFIG_RTL8192D
 617         MACPHY_MODE_8192D       MacPhyMode92D;
 618         BAND_TYPE       CurrentBandType92D;     //0:2.4G, 1:5G
 619         BAND_TYPE       BandSet92D;
 620         BOOLEAN       bMasterOfDMSP;
 621         BOOLEAN       bSlaveOfDMSP;
 622
 623         IQK_MATRIX_REGS_SETTING IQKMatrixRegSetting[IQK_Matrix_Settings_NUM_92D];
 624         #ifdef CONFIG_DUALMAC_CONCURRENT
 625         BOOLEAN         bInModeSwitchProcess;
 626         #endif
 627         u8      AutoLoadStatusFor8192D;
 628         u8      EEPROMC9;
 629         u8      EEPROMCC;
 630         u8      PAMode;
 631         u8      InternalPA5G[2];        //pathA / pathB
 632         BOOLEAN         bPhyValueInitReady;
 633         BOOLEAN         bLoadIMRandIQKSettingFor2G;// True if IMR or IQK  have done  for 2.4G in scan progress
 634         BOOLEAN         bNOPG;
 635         BOOLEAN         bIsVS;
 636         //Query RF by FW
 637         BOOLEAN         bReadRFbyFW;
 638         BOOLEAN         bEarlyModeEnable;
 639         BOOLEAN         bSupportRemoteWakeUp;
 640         BOOLEAN         bInSetPower;
 641         u8      RTSInitRate;     // 2010.11.24.by tynli.
 642         #endif //CONFIG_RTL8192D
 643
 644 #endif //defined(CONFIG_RTL8192C) ||defined(CONFIG_RTL8192D)
 645
 646 #ifdef CONFIG_LOAD_PHY_PARA_FROM_FILE
 647         char    para_file_buf[MAX_PARA_FILE_BUF_LEN];
 648         char *mac_reg;
 649         u32     mac_reg_len;
 650         char *bb_phy_reg;
 651         u32     bb_phy_reg_len;
 652         char *bb_agc_tab;
 653         u32     bb_agc_tab_len;
 654         char *bb_phy_reg_pg;
 655         u32     bb_phy_reg_pg_len;
 656         char *bb_phy_reg_mp;
 657         u32     bb_phy_reg_mp_len;
 658         char *rf_radio_a;
 659         u32     rf_radio_a_len;
 660         char *rf_radio_b;
 661         u32     rf_radio_b_len;
 662         char *rf_tx_pwr_track;
 663         u32     rf_tx_pwr_track_len;
 664         char *rf_tx_pwr_lmt;
 665         u32     rf_tx_pwr_lmt_len;
 666 #endif
 667 } HAL_DATA_COMMON, *PHAL_DATA_COMMON;
 668
 669
 670 typedef struct hal_com_data HAL_DATA_TYPE, *PHAL_DATA_TYPE;
 671 #define GET_HAL_DATA(__pAdapter)        ((HAL_DATA_TYPE *)((__pAdapter)->HalData))
 672 #define GET_HAL_RFPATH_NUM(__pAdapter) (((HAL_DATA_TYPE *)((__pAdapter)->HalData))->NumTotalRFPath )
 673 #define RT_GetInterfaceSelection(_Adapter)      (GET_HAL_DATA(_Adapter)->InterfaceSel)
 674 #define GET_RF_TYPE(__pAdapter)         (GET_HAL_DATA(__pAdapter)->rf_type)
 675 #endif
 676
 677
 678 #endif //__HAL_DATA_H__
 679