1 /******************************************************************************
3 * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
19 ******************************************************************************/
20 #ifndef __RTL8192D_HAL_H__
21 #define __RTL8192D_HAL_H__
23 //#include "hal_com.h"
28 #include "../hal/OUTSRC/odm_precomp.h"
31 #include "rtl8192d_spec.h"
32 #include "Hal8192DPhyReg.h"
33 #include "Hal8192DPhyCfg.h"
34 #include "rtl8192d_rf.h"
35 #include "rtl8192d_dm.h"
36 #include "rtl8192d_recv.h"
37 #include "rtl8192d_xmit.h"
38 #include "rtl8192d_cmd.h"
39 #include "rtl8192d_led.h"
43 #define RTL819X_DEFAULT_RF_TYPE RF_2T2R
45 //---------------------------------------------------------------------
46 // RTL8192DE From file
47 //---------------------------------------------------------------------
48 #define RTL8192D_FW_IMG "rtl8192DE\\rtl8192dfw.bin"
50 #define RTL8192D_PHY_REG "rtl8192DE\\PHY_REG.txt"
51 #define RTL8192D_PHY_REG_PG "rtl8192DE\\PHY_REG_PG.txt"
52 #define RTL8192D_PHY_REG_MP "rtl8192DE\\PHY_REG_MP.txt"
54 #define RTL8192D_AGC_TAB "rtl8192DE\\AGC_TAB.txt"
55 #define RTL8192D_AGC_TAB_2G "rtl8192DE\\AGC_TAB_2G.txt"
56 #define RTL8192D_AGC_TAB_5G "rtl8192DE\\AGC_TAB_5G.txt"
57 #define RTL8192D_PHY_RADIO_A "rtl8192DE\\radio_a.txt"
58 #define RTL8192D_PHY_RADIO_B "rtl8192DE\\radio_b.txt"
59 #define RTL8192D_PHY_RADIO_A_intPA "rtl8192DE\\radio_a_intPA.txt"
60 #define RTL8192D_PHY_RADIO_B_intPA "rtl8192DE\\radio_b_intPA.txt"
61 #define RTL8192D_PHY_MACREG "rtl8192DE\\MAC_REG.txt"
63 //---------------------------------------------------------------------
64 // RTL8192DE From header
65 //---------------------------------------------------------------------
67 #define Rtl8192D_FwImageArray Rtl8192DEFwImgArray
70 #define Rtl8192D_MAC_Array Rtl8192DEMAC_2T_Array
71 #define Rtl8192D_AGCTAB_Array Rtl8192DEAGCTAB_Array
72 #define Rtl8192D_AGCTAB_5GArray Rtl8192DEAGCTAB_5GArray
73 #define Rtl8192D_AGCTAB_2GArray Rtl8192DEAGCTAB_2GArray
74 #define Rtl8192D_AGCTAB_2TArray Rtl8192DEAGCTAB_2TArray
75 #define Rtl8192D_AGCTAB_1TArray Rtl8192DEAGCTAB_1TArray
76 #define Rtl8192D_PHY_REG_2TArray Rtl8192DEPHY_REG_2TArray
77 #define Rtl8192D_PHY_REG_1TArray Rtl8192DEPHY_REG_1TArray
78 #define Rtl8192D_PHY_REG_Array_PG Rtl8192DEPHY_REG_Array_PG
79 #define Rtl8192D_PHY_REG_Array_MP Rtl8192DEPHY_REG_Array_MP
80 #define Rtl8192D_RadioA_2TArray Rtl8192DERadioA_2TArray
81 #define Rtl8192D_RadioA_1TArray Rtl8192DERadioA_1TArray
82 #define Rtl8192D_RadioB_2TArray Rtl8192DERadioB_2TArray
83 #define Rtl8192D_RadioB_1TArray Rtl8192DERadioB_1TArray
84 #define Rtl8192D_RadioA_2T_intPAArray Rtl8192DERadioA_2T_intPAArray
85 #define Rtl8192D_RadioB_2T_intPAArray Rtl8192DERadioB_2T_intPAArray
88 #define Rtl8192D_FwImageArrayLength Rtl8192DEImgArrayLength
89 #define Rtl8192D_MAC_ArrayLength Rtl8192DEMAC_2T_ArrayLength
90 #define Rtl8192D_AGCTAB_5GArrayLength Rtl8192DEAGCTAB_5GArrayLength
91 #define Rtl8192D_AGCTAB_2GArrayLength Rtl8192DEAGCTAB_2GArrayLength
92 #define Rtl8192D_AGCTAB_2TArrayLength Rtl8192DEAGCTAB_2TArrayLength
93 #define Rtl8192D_AGCTAB_1TArrayLength Rtl8192DEAGCTAB_1TArrayLength
94 #define Rtl8192D_AGCTAB_ArrayLength Rtl8192DEAGCTAB_ArrayLength
95 #define Rtl8192D_PHY_REG_2TArrayLength Rtl8192DEPHY_REG_2TArrayLength
96 #define Rtl8192D_PHY_REG_1TArrayLength Rtl8192DEPHY_REG_1TArrayLength
97 #define Rtl8192D_PHY_REG_Array_PGLength Rtl8192DEPHY_REG_Array_PGLength
98 #define Rtl8192D_PHY_REG_Array_MPLength Rtl8192DEPHY_REG_Array_MPLength
99 #define Rtl8192D_RadioA_2TArrayLength Rtl8192DERadioA_2TArrayLength
100 #define Rtl8192D_RadioB_2TArrayLength Rtl8192DERadioB_2TArrayLength
101 #define Rtl8192D_RadioA_2T_intPAArrayLength Rtl8192DERadioA_2T_intPAArrayLength
102 #define Rtl8192D_RadioB_2T_intPAArrayLength Rtl8192DERadioB_2T_intPAArrayLength
104 #elif defined(CONFIG_USB_HCI)
107 #define RTL819X_DEFAULT_RF_TYPE RF_1T2R
109 //---------------------------------------------------------------------
110 // RTL8192DU From file
111 //---------------------------------------------------------------------
112 #define RTL8192D_FW_IMG "rtl8192DU\\rtl8192dfw.bin"
114 #define RTL8192D_PHY_REG "rtl8192DU\\PHY_REG.txt"
115 #define RTL8192D_PHY_REG_PG "rtl8192DU\\PHY_REG_PG.txt"
116 #define RTL8192D_PHY_REG_MP "rtl8192DU\\PHY_REG_MP.txt"
118 #define RTL8192D_AGC_TAB "rtl8192DU\\AGC_TAB.txt"
119 #define RTL8192D_AGC_TAB_2G "rtl8192DU\\AGC_TAB_2G.txt"
120 #define RTL8192D_AGC_TAB_5G "rtl8192DU\\AGC_TAB_5G.txt"
121 #define RTL8192D_PHY_RADIO_A "rtl8192DU\\radio_a.txt"
122 #define RTL8192D_PHY_RADIO_B "rtl8192DU\\radio_b.txt"
123 #define RTL8192D_PHY_RADIO_A_intPA "rtl8192DU\\radio_a_intPA.txt"
124 #define RTL8192D_PHY_RADIO_B_intPA "rtl8192DU\\radio_b_intPA.txt"
125 #define RTL8192D_PHY_MACREG "rtl8192DU\\MAC_REG.txt"
127 //---------------------------------------------------------------------
128 // RTL8192DU From header
129 //---------------------------------------------------------------------
132 #define Rtl8192D_FwImageArray Rtl8192DUFwImgArray
135 #define Rtl8192D_MAC_Array Rtl8192DUMAC_2T_Array
136 #define Rtl8192D_AGCTAB_Array Rtl8192DUAGCTAB_Array
137 #define Rtl8192D_AGCTAB_5GArray Rtl8192DUAGCTAB_5GArray
138 #define Rtl8192D_AGCTAB_2GArray Rtl8192DUAGCTAB_2GArray
139 #define Rtl8192D_AGCTAB_2TArray Rtl8192DUAGCTAB_2TArray
140 #define Rtl8192D_AGCTAB_1TArray Rtl8192DUAGCTAB_1TArray
141 #define Rtl8192D_PHY_REG_2TArray Rtl8192DUPHY_REG_2TArray
142 #define Rtl8192D_PHY_REG_1TArray Rtl8192DUPHY_REG_1TArray
143 #define Rtl8192D_PHY_REG_Array_PG Rtl8192DUPHY_REG_Array_PG
144 #define Rtl8192D_PHY_REG_Array_MP Rtl8192DUPHY_REG_Array_MP
145 #define Rtl8192D_RadioA_2TArray Rtl8192DURadioA_2TArray
146 #define Rtl8192D_RadioA_1TArray Rtl8192DURadioA_1TArray
147 #define Rtl8192D_RadioB_2TArray Rtl8192DURadioB_2TArray
148 #define Rtl8192D_RadioB_1TArray Rtl8192DURadioB_1TArray
149 #define Rtl8192D_RadioA_2T_intPAArray Rtl8192DURadioA_2T_intPAArray
150 #define Rtl8192D_RadioB_2T_intPAArray Rtl8192DURadioB_2T_intPAArray
153 #define Rtl8192D_FwImageArrayLength Rtl8192DUImgArrayLength
154 #define Rtl8192D_MAC_ArrayLength Rtl8192DUMAC_2T_ArrayLength
155 #define Rtl8192D_AGCTAB_5GArrayLength Rtl8192DUAGCTAB_5GArrayLength
156 #define Rtl8192D_AGCTAB_2GArrayLength Rtl8192DUAGCTAB_2GArrayLength
157 #define Rtl8192D_AGCTAB_2TArrayLength Rtl8192DUAGCTAB_2TArrayLength
158 #define Rtl8192D_AGCTAB_1TArrayLength Rtl8192DUAGCTAB_1TArrayLength
159 #define Rtl8192D_AGCTAB_ArrayLength Rtl8192DUAGCTAB_ArrayLength
160 #define Rtl8192D_PHY_REG_2TArrayLength Rtl8192DUPHY_REG_2TArrayLength
161 #define Rtl8192D_PHY_REG_1TArrayLength Rtl8192DUPHY_REG_1TArrayLength
162 #define Rtl8192D_PHY_REG_Array_PGLength Rtl8192DUPHY_REG_Array_PGLength
163 #define Rtl8192D_PHY_REG_Array_MPLength Rtl8192DUPHY_REG_Array_MPLength
164 #define Rtl8192D_RadioA_2TArrayLength Rtl8192DURadioA_2TArrayLength
165 #define Rtl8192D_RadioB_2TArrayLength Rtl8192DURadioB_2TArrayLength
166 #define Rtl8192D_RadioA_2T_intPAArrayLength Rtl8192DURadioA_2T_intPAArrayLength
167 #define Rtl8192D_RadioB_2T_intPAArrayLength Rtl8192DURadioB_2T_intPAArrayLength
169 // The file name "_2T" is for 92CU, "_1T" is for 88CU. Modified by tynli. 2009.11.24.
170 /* #define Rtl819XFwImageArray Rtl8192DUFwImgArray
171 #define Rtl819XMAC_Array Rtl8192DUMAC_2TArray
172 #define Rtl819XAGCTAB_Array Rtl8192DUAGCTAB_Array
173 #define Rtl819XAGCTAB_5GArray Rtl8192DUAGCTAB_5GArray
174 #define Rtl819XAGCTAB_2GArray Rtl8192DUAGCTAB_2GArray
175 #define Rtl819XPHY_REG_2TArray Rtl8192DUPHY_REG_2TArray
176 #define Rtl819XPHY_REG_1TArray Rtl8192DUPHY_REG_1TArray
177 #define Rtl819XRadioA_2TArray Rtl8192DURadioA_2TArray
178 #define Rtl819XRadioA_1TArray Rtl8192DURadioA_1TArray
179 #define Rtl819XRadioA_2T_intPAArray Rtl8192DURadioA_2T_intPAArray
180 #define Rtl819XRadioB_2TArray Rtl8192DURadioB_2TArray
181 #define Rtl819XRadioB_1TArray Rtl8192DURadioB_1TArray
182 #define Rtl819XRadioB_2T_intPAArray Rtl8192DURadioB_2T_intPAArray
183 #define Rtl819XPHY_REG_Array_PG Rtl8192DUPHY_REG_Array_PG
184 #define Rtl819XPHY_REG_Array_MP Rtl8192DUPHY_REG_Array_MP
186 #define Rtl819XAGCTAB_2TArray Rtl8192DUAGCTAB_2TArray
187 #define Rtl819XAGCTAB_1TArray Rtl8192DUAGCTAB_1TArray*/
192 // Check if FW header exists. We do not consider the lower 4 bits in this case.
193 // By tynli. 2009.12.04.
195 #define IS_FW_HEADER_EXIST_92D(_pFwHdr) ((le16_to_cpu(_pFwHdr->Signature)&0xFFF0) == 0x92C0 ||\
196 (le16_to_cpu(_pFwHdr->Signature)&0xFFF0) == 0x88C0 ||\
197 (le16_to_cpu(_pFwHdr->Signature)&0xFFFF) == 0x92D0 ||\
198 (le16_to_cpu(_pFwHdr->Signature)&0xFFFF) == 0x92D1 ||\
199 (le16_to_cpu(_pFwHdr->Signature)&0xFFFF) == 0x92D2 ||\
200 (le16_to_cpu(_pFwHdr->Signature)&0xFFFF) == 0x92D3 )
202 #define FW_8192D_SIZE 0x8020 // Max FW len = 32k + 32(FW header length).
203 #define FW_8192D_START_ADDRESS 0x1000
204 #define FW_8192D_END_ADDRESS 0x1FFF
208 typedef struct _RT_FIRMWARE_8192D{
209 FIRMWARE_SOURCE eFWSource;
212 } RT_FIRMWARE_8192D, *PRT_FIRMWARE_8192D;
215 // This structure must be cared byte-ordering
217 // Added by tynli. 2009.12.04.
218 typedef struct _RT_8192D_FIRMWARE_HDR {//8-byte alinment required
220 //--- LONG WORD 0 ----
221 u16 Signature; // 92C0: test chip; 92C, 88C0: test chip; 88C1: MP A-cut; 92C1: MP A-cut
222 u8 Category; // AP/NIC and USB/PCI
223 u8 Function; // Reserved for different FW function indcation, for further use when driver needs to download different FW in different conditions
224 u16 Version; // FW Version
225 u8 Subversion; // FW Subversion, default 0x00
229 //--- LONG WORD 1 ----
230 u8 Month; // Release time Month field
231 u8 Date; // Release time Date field
232 u8 Hour; // Release time Hour field
233 u8 Minute; // Release time Minute field
234 u16 RamCodeSize; // The size of RAM code
237 //--- LONG WORD 2 ----
238 u32 SvnIdx; // The SVN entry index
241 //--- LONG WORD 3 ----
245 }RT_8192D_FIRMWARE_HDR, *PRT_8192D_FIRMWARE_HDR;
247 #define DRIVER_EARLY_INT_TIME_8192D 0x05
248 #define BCN_DMA_ATIME_INT_TIME_8192D 0x02
250 typedef enum _BT_CurState{
253 } BT_CurState, *PBT_CurState;
255 typedef enum _BT_ServiceType{
265 } BT_ServiceType, *PBT_ServiceType;
267 typedef struct _BT_COEXIST_STR{
272 u8 BT_CUR_State; //0:on, 1:off
273 u8 BT_Ant_isolation; //0:good, 1:bad
274 u8 BT_PapeCtrl; //0:SW, 1:SW/HW dynamic
276 u8 BT_RadioSharedType;
279 }BT_COEXIST_STR, *PBT_COEXIST_STR;
285 // Note: We will divide number of page equally for each queue other than public queue!
287 #define TX_TOTAL_PAGE_NUMBER_8192D 0xF8
288 #define TX_PAGE_BOUNDARY (TX_TOTAL_PAGE_NUMBER_8192D + 1)
290 // For Normal Chip Setting
291 // (HPQ + LPQ + NPQ + PUBQ) shall be TX_TOTAL_PAGE_NUMBER_8192D
292 #define NORMAL_PAGE_NUM_PUBQ 0x56
295 // For Test Chip Setting
296 // (HPQ + LPQ + PUBQ) shall be TX_TOTAL_PAGE_NUMBER_8192D
297 #define TEST_PAGE_NUM_PUBQ 0x89
298 #define TX_TOTAL_PAGE_NUMBER_92D_DUAL_MAC 0x7A
299 #define NORMAL_PAGE_NUM_PUBQ_92D_DUAL_MAC 0x5A
300 #define NORMAL_PAGE_NUM_HPQ_92D_DUAL_MAC 0x10
301 #define NORMAL_PAGE_NUM_LPQ_92D_DUAL_MAC 0x10
302 #define NORMAL_PAGE_NUM_NORMALQ_92D_DUAL_MAC 0
304 #define TX_PAGE_BOUNDARY_DUAL_MAC (TX_TOTAL_PAGE_NUMBER_92D_DUAL_MAC + 1)
306 // For Test Chip Setting
307 #define WMM_TEST_TX_TOTAL_PAGE_NUMBER 0xF5
308 #define WMM_TEST_TX_PAGE_BOUNDARY (WMM_TEST_TX_TOTAL_PAGE_NUMBER + 1) //F6
310 #define WMM_TEST_PAGE_NUM_PUBQ 0xA3
311 #define WMM_TEST_PAGE_NUM_HPQ 0x29
312 #define WMM_TEST_PAGE_NUM_LPQ 0x29
315 //Note: For Normal Chip Setting ,modify later
316 #define WMM_NORMAL_TX_TOTAL_PAGE_NUMBER 0xF5
317 #define WMM_NORMAL_TX_PAGE_BOUNDARY (WMM_TEST_TX_TOTAL_PAGE_NUMBER + 1) //F6
319 #define WMM_NORMAL_PAGE_NUM_PUBQ 0xB0
320 #define WMM_NORMAL_PAGE_NUM_HPQ 0x29
321 #define WMM_NORMAL_PAGE_NUM_LPQ 0x1C
322 #define WMM_NORMAL_PAGE_NUM_NPQ 0x1C
324 #define WMM_NORMAL_PAGE_NUM_PUBQ_92D 0X65//0x82
325 #define WMM_NORMAL_PAGE_NUM_HPQ_92D 0X30//0x29
326 #define WMM_NORMAL_PAGE_NUM_LPQ_92D 0X30
327 #define WMM_NORMAL_PAGE_NUM_NPQ_92D 0X30
329 //-------------------------------------------------------------------------
331 //-------------------------------------------------------------------------
333 #define CHIP_BONDING_IDENTIFIER(_value) (((_value)>>22)&0x3)
334 #define CHIP_BONDING_92C_1T2R 0x1
335 #define CHIP_BONDING_88C_USB_MCARD 0x2
336 #define CHIP_BONDING_88C_USB_HP 0x1
338 //-------------------------------------------------------------------------
340 //-------------------------------------------------------------------------
343 #define EFUSE_REAL_CONTENT_LEN 1024
344 #define EFUSE_MAP_LEN 256
345 #define EFUSE_MAX_SECTION 32
346 #define EFUSE_MAX_SECTION_BASE 16
347 // <Roger_Notes> To prevent out of boundary programming case, leave 1byte and program full section
348 // 9bytes + 1byt + 5bytes and pre 1byte.
350 // | 2byte|----8bytes----|1byte|--7bytes--| //92D
351 #define EFUSE_OOB_PROTECT_BYTES 18 // PG data exclude header, dummy 7 bytes frome CP test and reserved 1byte.
353 typedef enum _PA_MODE {
354 PA_MODE_EXTERNAL = 0x00,
355 PA_MODE_INTERNAL_SP3T = 0x01,
356 PA_MODE_INTERNAL_SPDT = 0x02
359 /* Copy from rtl8192c */
368 C2H_HW_INFO_EXCH = 10,
369 C2H_C2H_H2C_TEST = 11,
375 #ifdef CONFIG_PCI_HCI
377 // Function disabled.
379 #define DF_TX_BIT BIT0
380 #define DF_RX_BIT BIT1
381 #define DF_IO_BIT BIT2
382 #define DF_IO_D3_BIT BIT3
384 #define RT_DF_TYPE u32
385 //#define RT_DISABLE_FUNC(__pAdapter, __FuncBits) ((__pAdapter)->DisabledFunctions |= ((RT_DF_TYPE)(__FuncBits)))
386 //#define RT_ENABLE_FUNC(__pAdapter, __FuncBits) ((__pAdapter)->DisabledFunctions &= (~((RT_DF_TYPE)(__FuncBits))))
387 //#define RT_IS_FUNC_DISABLED(__pAdapter, __FuncBits) ( (__pAdapter)->DisabledFunctions & (__FuncBits) )
389 void InterruptRecognized8192DE(PADAPTER Adapter, PRT_ISR_CONTENT pIsrContent);
390 VOID UpdateInterruptMask8192DE(PADAPTER Adapter, u32 AddMSR, u32 RemoveMSR);
393 int FirmwareDownload92D(IN PADAPTER Adapter);
394 VOID rtl8192d_FirmwareSelfReset(IN PADAPTER Adapter);
395 void rtl8192d_ReadChipVersion(IN PADAPTER Adapter);
396 VOID rtl8192d_EfuseParseChnlPlan(PADAPTER Adapter, u8 *hwinfo, BOOLEAN AutoLoadFail);
397 VOID rtl8192d_ReadTxPowerInfo(PADAPTER Adapter, u8* PROMContent, BOOLEAN AutoLoadFail);
398 VOID rtl8192d_ResetDualMacSwitchVariables(IN PADAPTER Adapter);
399 u8 GetEEPROMSize8192D(PADAPTER Adapter);
400 BOOLEAN PHY_CheckPowerOffFor8192D(PADAPTER Adapter);
401 VOID PHY_SetPowerOnFor8192D(PADAPTER Adapter);
402 //void PHY_ConfigMacPhyMode92D(PADAPTER Adapter);
403 void rtl8192d_free_hal_data(_adapter * padapter);
404 void rtl8192d_set_hal_ops(struct hal_ops *pHalFunc);
406 void SetHwReg8192D(_adapter *adapter, u8 variable, u8 *val);
407 void GetHwReg8192D(_adapter *adapter, u8 variable, u8 *val);