drivers/net/wireless/rockchip_wlan/rtl8723bs/include/rtl8812a_spec.h

   1 /******************************************************************************\r
   2  *\r
   3  * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.\r
   4  *\r
   5  * This program is free software; you can redistribute it and/or modify it\r
   6  * under the terms of version 2 of the GNU General Public License as\r
   7  * published by the Free Software Foundation.\r
   8  *\r
   9  * This program is distributed in the hope that it will be useful, but WITHOUT\r
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\r
  11  * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\r
  12  * more details.\r
  13  *\r
  14  * You should have received a copy of the GNU General Public License along with\r
  15  * this program; if not, write to the Free Software Foundation, Inc.,\r
  16  * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA\r
  17  *\r
  18  *******************************************************************************/\r
  19 #ifndef __RTL8812A_SPEC_H__\r
  20 #define __RTL8812A_SPEC_H__\r
  21 \r
  22 #include <drv_conf.h>\r
  23 \r
  24 \r
  25 //============================================================\r
  26 //       8812 Regsiter offset definition\r
  27 //============================================================\r
  28 \r
  29 //============================================================\r
  30 //\r
  31 //============================================================\r
  32 \r
  33 //-----------------------------------------------------\r
  34 //\r
  35 //      0x0000h ~ 0x00FFh       System Configuration\r
  36 //\r
  37 //-----------------------------------------------------\r
  38 #define REG_SYS_CLKR_8812A                              0x0008\r
  39 #define REG_AFE_PLL_CTRL_8812A          0x0028\r
  40 #define REG_HSIMR_8812                                  0x0058\r
  41 #define REG_HSISR_8812                                  0x005c\r
  42 #define REG_GPIO_EXT_CTRL                               0x0060\r
  43 #define REG_GPIO_STATUS_8812                    0x006C\r
  44 #define REG_SDIO_CTRL_8812                              0x0070\r
  45 #define REG_OPT_CTRL_8812                               0x0074\r
  46 #define REG_RF_B_CTRL_8812                              0x0076\r
  47 #define REG_FW_DRV_MSG_8812                     0x0088\r
  48 #define REG_HMEBOX_E2_E3_8812                   0x008C\r
  49 #define REG_HIMR0_8812                                  0x00B0\r
  50 #define REG_HISR0_8812                                  0x00B4\r
  51 #define REG_HIMR1_8812                                  0x00B8\r
  52 #define REG_HISR1_8812                                  0x00BC\r
  53 #define REG_EFUSE_BURN_GNT_8812         0x00CF\r
  54 #define REG_SYS_CFG1_8812                               0x00FC\r
  55 \r
  56 //-----------------------------------------------------\r
  57 //\r
  58 //      0x0100h ~ 0x01FFh       MACTOP General Configuration\r
  59 //\r
  60 //-----------------------------------------------------\r
  61 #define REG_CR_8812A                                    0x100\r
  62 #define REG_PKTBUF_DBG_ADDR                     (REG_PKTBUF_DBG_CTRL)\r
  63 #define REG_RXPKTBUF_DBG                                (REG_PKTBUF_DBG_CTRL+2)\r
  64 #define REG_TXPKTBUF_DBG                                (REG_PKTBUF_DBG_CTRL+3)\r
  65 #define REG_WOWLAN_WAKE_REASON                  REG_MCUTST_WOWLAN\r
  66 \r
  67 #define REG_RSVD3_8812                                  0x0168\r
  68 #define REG_C2HEVT_CMD_SEQ_88XX         0x01A1\r
  69 #define REG_C2hEVT_CMD_CONTENT_88XX     0x01A2\r
  70 #define REG_C2HEVT_CMD_LEN_88XX         0x01AE\r
  71 \r
  72 #define REG_HMEBOX_EXT0_8812                    0x01F0\r
  73 #define REG_HMEBOX_EXT1_8812                    0x01F4\r
  74 #define REG_HMEBOX_EXT2_8812                    0x01F8\r
  75 #define REG_HMEBOX_EXT3_8812                    0x01FC\r
  76 \r
  77 //-----------------------------------------------------\r
  78 //\r
  79 //      0x0200h ~ 0x027Fh       TXDMA Configuration\r
  80 //\r
  81 //-----------------------------------------------------\r
  82 #define REG_DWBCN0_CTRL_8812                            REG_TDECTRL\r
  83 #define REG_DWBCN1_CTRL_8812                            0x0228\r
  84 \r
  85 //-----------------------------------------------------\r
  86 //\r
  87 //      0x0280h ~ 0x02FFh       RXDMA Configuration\r
  88 //\r
  89 //-----------------------------------------------------\r
  90 #define REG_TDECTRL_8812A                               0x0208\r
  91 #define REG_RXDMA_CONTROL_8812A         0x0286          /*Control the RX DMA.*/\r
  92 #define REG_RXDMA_PRO_8812                      0x0290\r
  93 #define REG_EARLY_MODE_CONTROL_8812     0x02BC\r
  94 #define REG_RSVD5_8812                                  0x02F0\r
  95 #define REG_RSVD6_8812                                  0x02F4\r
  96 #define REG_RSVD7_8812                                  0x02F8\r
  97 #define REG_RSVD8_8812                                  0x02FC\r
  98 \r
  99 \r
 100 //-----------------------------------------------------\r
 101 //\r
 102 //      0x0300h ~ 0x03FFh       PCIe\r
 103 //\r
 104 //-----------------------------------------------------\r
 105 #define REG_PCIE_CTRL_REG_8812A         0x0300\r
 106 #define REG_DBI_WDATA_8812                      0x0348  // DBI Write Data\r
 107 #define REG_DBI_RDATA_8812                      0x034C  // DBI Read Data\r
 108 #define REG_DBI_ADDR_8812                               0x0350  // DBI Address\r
 109 #define REG_DBI_FLAG_8812                               0x0352  // DBI Read/Write Flag\r
 110 #define REG_MDIO_WDATA_8812                     0x0354  // MDIO for Write PCIE PHY\r
 111 #define REG_MDIO_RDATA_8812                     0x0356  // MDIO for Reads PCIE PHY\r
 112 #define REG_MDIO_CTL_8812                               0x0358  // MDIO for Control \r
 113 #define REG_PCIE_MULTIFET_CTRL_8812     0x036A  //PCIE Multi-Fethc Control\r
 114 \r
 115 //-----------------------------------------------------\r
 116 //\r
 117 //      0x0400h ~ 0x047Fh       Protocol Configuration\r
 118 //\r
 119 //-----------------------------------------------------\r
 120 #define REG_TXPKT_EMPTY_8812A                   0x041A\r
 121 #define REG_FWHW_TXQ_CTRL_8812A         0x0420\r
 122 #define REG_TXBF_CTRL_8812A                     0x042C\r
 123 #define REG_ARFR0_8812                                  0x0444\r
 124 #define REG_ARFR1_8812                                  0x044C\r
 125 #define REG_CCK_CHECK_8812                              0x0454\r
 126 #define REG_AMPDU_MAX_TIME_8812         0x0456\r
 127 #define REG_TXPKTBUF_BCNQ_BDNY1_8812    0x0457\r
 128 \r
 129 #define REG_AMPDU_MAX_LENGTH_8812       0x0458\r
 130 #define REG_TXPKTBUF_WMAC_LBK_BF_HD_8812        0x045D\r
 131 #define REG_NDPA_OPT_CTRL_8812A         0x045F\r
 132 #define REG_DATA_SC_8812                                0x0483\r
 133 #ifdef CONFIG_WOWLAN\r
 134 #define REG_TXPKTBUF_IV_LOW             0x0484\r
 135 #define REG_TXPKTBUF_IV_HIGH            0x0488\r
 136 #endif\r
 137 #define REG_ARFR2_8812                                  0x048C\r
 138 #define REG_ARFR3_8812                                  0x0494\r
 139 #define REG_TXRPT_START_OFFSET          0x04AC\r
 140 #define REG_AMPDU_BURST_MODE_8812       0x04BC\r
 141 #define REG_HT_SINGLE_AMPDU_8812                0x04C7\r
 142 #define REG_MACID_PKT_DROP0_8812                0x04D0\r
 143 \r
 144 //-----------------------------------------------------\r
 145 //\r
 146 //      0x0500h ~ 0x05FFh       EDCA Configuration\r
 147 //\r
 148 //-----------------------------------------------------\r
 149 #define REG_TXPAUSE_8812A                               0x0522\r
 150 #define REG_CTWND_8812                                  0x0572\r
 151 #define REG_SECONDARY_CCA_CTRL_8812     0x0577\r
 152 #define REG_SCH_TXCMD_8812A                     0x05F8\r
 153 \r
 154 //-----------------------------------------------------\r
 155 //\r
 156 //      0x0600h ~ 0x07FFh       WMAC Configuration\r
 157 //\r
 158 //-----------------------------------------------------\r
 159 #define REG_MAC_CR_8812                         0x0600\r
 160 \r
 161 #define REG_MAC_TX_SM_STATE_8812                0x06B4\r
 162 \r
 163 // Power\r
 164 #define REG_BFMER0_INFO_8812A                   0x06E4\r
 165 #define REG_BFMER1_INFO_8812A                   0x06EC\r
 166 #define REG_CSI_RPT_PARAM_BW20_8812A    0x06F4\r
 167 #define REG_CSI_RPT_PARAM_BW40_8812A    0x06F8\r
 168 #define REG_CSI_RPT_PARAM_BW80_8812A    0x06FC\r
 169 \r
 170 // Hardware Port 2\r
 171 #define REG_BFMEE_SEL_8812A                     0x0714\r
 172 #define REG_SND_PTCL_CTRL_8812A         0x0718\r
 173 \r
 174 \r
 175 //-----------------------------------------------------\r
 176 //\r
 177 //      Redifine register definition for compatibility\r
 178 //\r
 179 //-----------------------------------------------------\r
 180 \r
 181 // TODO: use these definition when using REG_xxx naming rule.\r
 182 // NOTE: DO NOT Remove these definition. Use later.\r
 183 #define ISR_8812                                                        REG_HISR0_8812\r
 184 \r
 185 //----------------------------------------------------------------------------\r
 186 //       8195 IMR/ISR bits                                              (offset 0xB0,  8bits)\r
 187 //----------------------------------------------------------------------------\r
 188 #define IMR_DISABLED_8812                                       0\r
 189 // IMR DW0(0x00B0-00B3) Bit 0-31\r
 190 #define IMR_TIMER2_8812                                 BIT31           // Timeout interrupt 2\r
 191 #define IMR_TIMER1_8812                                 BIT30           // Timeout interrupt 1  \r
 192 #define IMR_PSTIMEOUT_8812                              BIT29           // Power Save Time Out Interrupt\r
 193 #define IMR_GTINT4_8812                                 BIT28           // When GTIMER4 expires, this bit is set to 1   \r
 194 #define IMR_GTINT3_8812                                 BIT27           // When GTIMER3 expires, this bit is set to 1   \r
 195 #define IMR_TXBCN0ERR_8812                              BIT26           // Transmit Beacon0 Error                       \r
 196 #define IMR_TXBCN0OK_8812                                       BIT25           // Transmit Beacon0 OK                  \r
 197 #define IMR_TSF_BIT32_TOGGLE_8812               BIT24           // TSF Timer BIT32 toggle indication interrupt                  \r
 198 #define IMR_BCNDMAINT0_8812                             BIT20           // Beacon DMA Interrupt 0                       \r
 199 #define IMR_BCNDERR0_8812                                       BIT16           // Beacon Queue DMA OK0                 \r
 200 #define IMR_HSISR_IND_ON_INT_8812               BIT15           // HSISR Indicator (HSIMR & HSISR is true, this bit is set to 1)\r
 201 #define IMR_BCNDMAINT_E_8812                            BIT14           // Beacon DMA Interrupt Extension for Win7                      \r
 202 #define IMR_ATIMEND_8812                                        BIT12           // CTWidnow End or ATIM Window End\r
 203 #define IMR_C2HCMD_8812                                 BIT10           // CPU to Host Command INT Status, Write 1 clear        \r
 204 #define IMR_CPWM2_8812                                  BIT9                    // CPU power Mode exchange INT Status, Write 1 clear    \r
 205 #define IMR_CPWM_8812                                           BIT8                    // CPU power Mode exchange INT Status, Write 1 clear    \r
 206 #define IMR_HIGHDOK_8812                                        BIT7                    // High Queue DMA OK    \r
 207 #define IMR_MGNTDOK_8812                                        BIT6                    // Management Queue DMA OK      \r
 208 #define IMR_BKDOK_8812                                  BIT5                    // AC_BK DMA OK         \r
 209 #define IMR_BEDOK_8812                                  BIT4                    // AC_BE DMA OK \r
 210 #define IMR_VIDOK_8812                                  BIT3                    // AC_VI DMA OK         \r
 211 #define IMR_VODOK_8812                                  BIT2                    // AC_VO DMA OK \r
 212 #define IMR_RDU_8812                                            BIT1                    // Rx Descriptor Unavailable    \r
 213 #define IMR_ROK_8812                                            BIT0                    // Receive DMA OK\r
 214 \r
 215 // IMR DW1(0x00B4-00B7) Bit 0-31\r
 216 #define IMR_BCNDMAINT7_8812                             BIT27           // Beacon DMA Interrupt 7\r
 217 #define IMR_BCNDMAINT6_8812                             BIT26           // Beacon DMA Interrupt 6\r
 218 #define IMR_BCNDMAINT5_8812                             BIT25           // Beacon DMA Interrupt 5\r
 219 #define IMR_BCNDMAINT4_8812                             BIT24           // Beacon DMA Interrupt 4\r
 220 #define IMR_BCNDMAINT3_8812                             BIT23           // Beacon DMA Interrupt 3\r
 221 #define IMR_BCNDMAINT2_8812                             BIT22           // Beacon DMA Interrupt 2\r
 222 #define IMR_BCNDMAINT1_8812                             BIT21           // Beacon DMA Interrupt 1\r
 223 #define IMR_BCNDOK7_8812                                        BIT20           // Beacon Queue DMA OK Interrup 7\r
 224 #define IMR_BCNDOK6_8812                                        BIT19           // Beacon Queue DMA OK Interrup 6\r
 225 #define IMR_BCNDOK5_8812                                        BIT18           // Beacon Queue DMA OK Interrup 5\r
 226 #define IMR_BCNDOK4_8812                                        BIT17           // Beacon Queue DMA OK Interrup 4\r
 227 #define IMR_BCNDOK3_8812                                        BIT16           // Beacon Queue DMA OK Interrup 3\r
 228 #define IMR_BCNDOK2_8812                                        BIT15           // Beacon Queue DMA OK Interrup 2\r
 229 #define IMR_BCNDOK1_8812                                        BIT14           // Beacon Queue DMA OK Interrup 1\r
 230 #define IMR_ATIMEND_E_8812                              BIT13           // ATIM Window End Extension for Win7\r
 231 #define IMR_TXERR_8812                                  BIT11           // Tx Error Flag Interrupt Status, write 1 clear.\r
 232 #define IMR_RXERR_8812                                  BIT10           // Rx Error Flag INT Status, Write 1 clear\r
 233 #define IMR_TXFOVW_8812                                 BIT9                    // Transmit FIFO Overflow\r
 234 #define IMR_RXFOVW_8812                                 BIT8                    // Receive FIFO Overflow\r
 235 \r
 236 \r
 237 #ifdef CONFIG_PCI_HCI\r
 238 //#define IMR_RX_MASK           (IMR_ROK_8812|IMR_RDU_8812|IMR_RXFOVW_8812)\r
 239 #define IMR_TX_MASK                     (IMR_VODOK_8812|IMR_VIDOK_8812|IMR_BEDOK_8812|IMR_BKDOK_8812|IMR_MGNTDOK_8812|IMR_HIGHDOK_8812)\r
 240 \r
 241 #define RT_BCN_INT_MASKS        (IMR_BCNDMAINT0_8812 | IMR_TXBCN0OK_8812 | IMR_TXBCN0ERR_8812 | IMR_BCNDERR0_8812)\r
 242 \r
 243 #define RT_AC_INT_MASKS (IMR_VIDOK_8812 | IMR_VODOK_8812 | IMR_BEDOK_8812|IMR_BKDOK_8812)\r
 244 #endif\r
 245 \r
 246 \r
 247 //============================================================================\r
 248 //       Regsiter Bit and Content definition \r
 249 //============================================================================\r
 250 \r
 251 //2 ACMHWCTRL 0x05C0\r
 252 #define AcmHw_HwEn_8812                         BIT(0)\r
 253 #define AcmHw_VoqEn_8812                                BIT(1)\r
 254 #define AcmHw_ViqEn_8812                                BIT(2)\r
 255 #define AcmHw_BeqEn_8812                                BIT(3)\r
 256 #define AcmHw_VoqStatus_8812                    BIT(5)\r
 257 #define AcmHw_ViqStatus_8812                    BIT(6)\r
 258 #define AcmHw_BeqStatus_8812                    BIT(7)\r
 259 \r
 260 //========================================================\r
 261 // General definitions\r
 262 //========================================================\r
 263 \r
 264 #define MACID_NUM_8812A 128\r
 265 #define SEC_CAM_ENT_NUM_8812A 64\r
 266 #define NSS_NUM_8812A 2\r
 267 #define BAND_CAP_8812A (BAND_CAP_2G | BAND_CAP_5G)\r
 268 #define BW_CAP_8812A (BW_CAP_20M | BW_CAP_40M | BW_CAP_80M)\r
 269 #define PROTO_CAP_8812A (PROTO_CAP_11B|PROTO_CAP_11G|PROTO_CAP_11N|PROTO_CAP_11AC)\r
 270 \r
 271 #endif /* __RTL8812A_SPEC_H__ */\r
 272 \r
 273 #ifdef CONFIG_RTL8821A\r
 274 #include "rtl8821a_spec.h"\r
 275 #endif /* CONFIG_RTL8821A */\r
 276 \r