1 /******************************************************************************
\r
3 * Copyright(c) 2013 Realtek Corporation. All rights reserved.
\r
5 * This program is free software; you can redistribute it and/or modify it
\r
6 * under the terms of version 2 of the GNU General Public License as
\r
7 * published by the Free Software Foundation.
\r
9 * This program is distributed in the hope that it will be useful, but WITHOUT
\r
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
\r
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
\r
14 * You should have received a copy of the GNU General Public License along with
\r
15 * this program; if not, write to the Free Software Foundation, Inc.,
\r
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
\r
18 *******************************************************************************/
\r
19 #ifndef __RTL8821A_SPEC_H__
\r
20 #define __RTL8821A_SPEC_H__
\r
22 #include <drv_conf.h>
\r
23 // This file should based on "hal_com_reg.h"
\r
24 #include <hal_com_reg.h>
\r
25 // Because 8812a and 8821a is the same serial,
\r
26 // most of 8821a register definitions are the same as 8812a.
\r
27 #include <rtl8812a_spec.h>
\r
30 //============================================================
\r
31 // 8821A Regsiter offset definition
\r
32 //============================================================
\r
34 //============================================================
\r
36 //============================================================
\r
38 //-----------------------------------------------------
\r
39 // 0x0000h ~ 0x00FFh System Configuration
\r
40 //-----------------------------------------------------
\r
42 //-----------------------------------------------------
\r
43 // 0x0100h ~ 0x01FFh MACTOP General Configuration
\r
44 //-----------------------------------------------------
\r
46 //-----------------------------------------------------
\r
47 // 0x0200h ~ 0x027Fh TXDMA Configuration
\r
48 //-----------------------------------------------------
\r
50 //-----------------------------------------------------
\r
51 // 0x0280h ~ 0x02FFh RXDMA Configuration
\r
52 //-----------------------------------------------------
\r
54 //-----------------------------------------------------
\r
55 // 0x0300h ~ 0x03FFh PCIe
\r
56 //-----------------------------------------------------
\r
58 //-----------------------------------------------------
\r
59 // 0x0400h ~ 0x047Fh Protocol Configuration
\r
60 //-----------------------------------------------------
\r
62 //-----------------------------------------------------
\r
63 // 0x0500h ~ 0x05FFh EDCA Configuration
\r
64 //-----------------------------------------------------
\r
66 //-----------------------------------------------------
\r
67 // 0x0600h ~ 0x07FFh WMAC Configuration
\r
68 //-----------------------------------------------------
\r
71 //============================================================
\r
72 // SDIO Bus Specification
\r
73 //============================================================
\r
75 //-----------------------------------------------------
\r
76 // SDIO CMD Address Mapping
\r
77 //-----------------------------------------------------
\r
79 //-----------------------------------------------------
\r
80 // I/O bus domain (Host)
\r
81 //-----------------------------------------------------
\r
83 //-----------------------------------------------------
\r
85 //-----------------------------------------------------
\r
86 #undef SDIO_REG_HCPWM1
\r
87 #define SDIO_REG_FREE_TXPG2 0x024
\r
88 #define SDIO_REG_HCPWM1 0x025
\r
91 //============================================================
\r
92 // Regsiter Bit and Content definition
\r
93 //============================================================
\r
96 #endif // __RTL8821A_SPEC_H__
\r