drivers/net/wireless/rockchip_wlan/rtl8723bu/core/rtw_odm.c

   1 /******************************************************************************
   2  *
   3  * Copyright(c) 2013 Realtek Corporation. All rights reserved.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of version 2 of the GNU General Public License as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program; if not, write to the Free Software Foundation, Inc.,
  16  * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  17  *
  18  *
  19  ******************************************************************************/
  20
  21 #include <rtw_odm.h>
  22 #include <hal_data.h>
  23
  24 const char *odm_comp_str[] = {
  25         /* BIT0 */"ODM_COMP_DIG",
  26         /* BIT1 */"ODM_COMP_RA_MASK",
  27         /* BIT2 */"ODM_COMP_DYNAMIC_TXPWR",
  28         /* BIT3 */"ODM_COMP_FA_CNT",
  29         /* BIT4 */"ODM_COMP_RSSI_MONITOR",
  30         /* BIT5 */"ODM_COMP_CCK_PD",
  31         /* BIT6 */"ODM_COMP_ANT_DIV",
  32         /* BIT7 */"ODM_COMP_PWR_SAVE",
  33         /* BIT8 */"ODM_COMP_PWR_TRAIN",
  34         /* BIT9 */"ODM_COMP_RATE_ADAPTIVE",
  35         /* BIT10 */"ODM_COMP_PATH_DIV",
  36         /* BIT11 */"ODM_COMP_PSD",
  37         /* BIT12 */"ODM_COMP_DYNAMIC_PRICCA",
  38         /* BIT13 */"ODM_COMP_RXHP",
  39         /* BIT14 */"ODM_COMP_MP",
  40         /* BIT15 */"ODM_COMP_CFO_TRACKING",
  41         /* BIT16 */"ODM_COMP_ACS",
  42         /* BIT17 */"PHYDM_COMP_ADAPTIVITY",
  43         /* BIT18 */NULL,
  44         /* BIT19 */NULL,
  45         /* BIT20 */"ODM_COMP_EDCA_TURBO",
  46         /* BIT21 */"ODM_COMP_EARLY_MODE",
  47         /* BIT22 */NULL,
  48         /* BIT23 */NULL,
  49         /* BIT24 */"ODM_COMP_TX_PWR_TRACK",
  50         /* BIT25 */"ODM_COMP_RX_GAIN_TRACK",
  51         /* BIT26 */"ODM_COMP_CALIBRATION",
  52         /* BIT27 */NULL,
  53         /* BIT28 */NULL,
  54         /* BIT29 */NULL,
  55         /* BIT30 */"ODM_COMP_COMMON",
  56         /* BIT31 */"ODM_COMP_INIT",
  57 };
  58
  59 #define RTW_ODM_COMP_MAX 32
  60
  61 const char *odm_ability_str[] = {
  62         /* BIT0 */"ODM_BB_DIG",
  63         /* BIT1 */"ODM_BB_RA_MASK",
  64         /* BIT2 */"ODM_BB_DYNAMIC_TXPWR",
  65         /* BIT3 */"ODM_BB_FA_CNT",
  66         /* BIT4 */"ODM_BB_RSSI_MONITOR",
  67         /* BIT5 */"ODM_BB_CCK_PD",
  68         /* BIT6 */"ODM_BB_ANT_DIV",
  69         /* BIT7 */"ODM_BB_PWR_SAVE",
  70         /* BIT8 */"ODM_BB_PWR_TRAIN",
  71         /* BIT9 */"ODM_BB_RATE_ADAPTIVE",
  72         /* BIT10 */"ODM_BB_PATH_DIV",
  73         /* BIT11 */"ODM_BB_PSD",
  74         /* BIT12 */"ODM_BB_RXHP",
  75         /* BIT13 */"ODM_BB_ADAPTIVITY",
  76         /* BIT14 */"ODM_BB_CFO_TRACKING",
  77         /* BIT15 */"ODM_BB_NHM_CNT",
  78         /* BIT16 */"ODM_BB_PRIMARY_CCA",
  79         /* BIT17 */NULL,
  80         /* BIT18 */NULL,
  81         /* BIT19 */NULL,
  82         /* BIT20 */"ODM_MAC_EDCA_TURBO",
  83         /* BIT21 */"ODM_MAC_EARLY_MODE",
  84         /* BIT22 */NULL,
  85         /* BIT23 */NULL,
  86         /* BIT24 */"ODM_RF_TX_PWR_TRACK",
  87         /* BIT25 */"ODM_RF_RX_GAIN_TRACK",
  88         /* BIT26 */"ODM_RF_CALIBRATION",
  89 };
  90
  91 #define RTW_ODM_ABILITY_MAX 27
  92
  93 const char *odm_dbg_level_str[] = {
  94         NULL,
  95         "ODM_DBG_OFF",
  96         "ODM_DBG_SERIOUS",
  97         "ODM_DBG_WARNING",
  98         "ODM_DBG_LOUD",
  99         "ODM_DBG_TRACE",
 100 };
 101
 102 #define RTW_ODM_DBG_LEVEL_NUM 6
 103
 104 void rtw_odm_dbg_comp_msg(void *sel, _adapter *adapter)
 105 {
 106         HAL_DATA_TYPE *pHalData = GET_HAL_DATA(adapter);
 107         DM_ODM_T *odm = &pHalData->odmpriv;
 108         int cnt = 0;
 109         u64 dbg_comp;
 110         int i;
 111
 112         rtw_hal_get_def_var(adapter, HW_DEF_ODM_DBG_FLAG, &dbg_comp);
 113         DBG_871X_SEL_NL(sel, "odm.DebugComponents = 0x%016llx \n", dbg_comp);
 114         for (i=0;i<RTW_ODM_COMP_MAX;i++) {
 115                 if (odm_comp_str[i])
 116                 DBG_871X_SEL_NL(sel, "%cBIT%-2d %s\n",
 117                         (BIT0 << i) & dbg_comp ? '+' : ' ', i, odm_comp_str[i]);
 118         }
 119 }
 120
 121 inline void rtw_odm_dbg_comp_set(_adapter *adapter, u64 comps)
 122 {
 123         rtw_hal_set_def_var(adapter, HW_DEF_ODM_DBG_FLAG, &comps);
 124 }
 125
 126 void rtw_odm_dbg_level_msg(void *sel, _adapter *adapter)
 127 {
 128         HAL_DATA_TYPE *pHalData = GET_HAL_DATA(adapter);
 129         DM_ODM_T *odm = &pHalData->odmpriv;
 130         int cnt = 0;
 131         u32 dbg_level;
 132         int i;
 133
 134         rtw_hal_get_def_var(adapter, HW_DEF_ODM_DBG_LEVEL, &dbg_level);
 135         DBG_871X_SEL_NL(sel, "odm.DebugLevel = %u\n", dbg_level);
 136         for (i=0;i<RTW_ODM_DBG_LEVEL_NUM;i++) {
 137                 if (odm_dbg_level_str[i])
 138                         DBG_871X_SEL_NL(sel, "%u %s\n", i, odm_dbg_level_str[i]);
 139         }
 140 }
 141
 142 inline void rtw_odm_dbg_level_set(_adapter *adapter, u32 level)
 143 {
 144         rtw_hal_set_def_var(adapter, HW_DEF_ODM_DBG_LEVEL, &level);
 145 }
 146
 147 void rtw_odm_ability_msg(void *sel, _adapter *adapter)
 148 {
 149         HAL_DATA_TYPE *pHalData = GET_HAL_DATA(adapter);
 150         DM_ODM_T *odm = &pHalData->odmpriv;
 151         int cnt = 0;
 152         u32 ability = 0;
 153         int i;
 154
 155         rtw_hal_get_hwreg(adapter, HW_VAR_DM_FLAG, (u8*)&ability);
 156         DBG_871X_SEL_NL(sel, "odm.SupportAbility = 0x%08x\n", ability);
 157         for (i=0;i<RTW_ODM_ABILITY_MAX;i++) {
 158                 if (odm_ability_str[i])
 159                 DBG_871X_SEL_NL(sel, "%cBIT%-2d %s\n",
 160                         (BIT0 << i) & ability ? '+' : ' ', i, odm_ability_str[i]);
 161         }
 162 }
 163
 164 inline void rtw_odm_ability_set(_adapter *adapter, u32 ability)
 165 {
 166         rtw_hal_set_hwreg(adapter, HW_VAR_DM_FLAG, (u8*)&ability);
 167 }
 168
 169 void rtw_odm_adaptivity_ver_msg(void *sel, _adapter *adapter)
 170 {
 171         DBG_871X_SEL_NL(sel, "ADAPTIVITY_VERSION "ADAPTIVITY_VERSION"\n");
 172 }
 173
 174 #define RTW_ADAPTIVITY_EN_DISABLE 0
 175 #define RTW_ADAPTIVITY_EN_ENABLE 1
 176 #define RTW_ADAPTIVITY_EN_AUTO 2
 177
 178 void rtw_odm_adaptivity_en_msg(void *sel, _adapter *adapter)
 179 {
 180         struct registry_priv *regsty = &adapter->registrypriv;
 181         struct mlme_priv *mlme = &adapter->mlmepriv;
 182         HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
 183         DM_ODM_T *odm = &hal_data->odmpriv;
 184
 185         DBG_871X_SEL_NL(sel, "RTW_ADAPTIVITY_EN_");
 186
 187         if (regsty->adaptivity_en == RTW_ADAPTIVITY_EN_DISABLE) {
 188                 DBG_871X_SEL(sel, "DISABLE\n");
 189         } else if (regsty->adaptivity_en == RTW_ADAPTIVITY_EN_ENABLE) {
 190                 DBG_871X_SEL(sel, "ENABLE\n");
 191         } else if (regsty->adaptivity_en == RTW_ADAPTIVITY_EN_AUTO) {
 192                 DBG_871X_SEL(sel, "AUTO, chplan:0x%02x, Regulation:%u,%u\n"
 193                         , mlme->ChannelPlan, odm->odm_Regulation2_4G, odm->odm_Regulation5G);
 194         } else {
 195                 DBG_871X_SEL(sel, "INVALID\n");
 196         }
 197 }
 198
 199 #define RTW_ADAPTIVITY_MODE_NORMAL 0
 200 #define RTW_ADAPTIVITY_MODE_CARRIER_SENSE 1
 201
 202 void rtw_odm_adaptivity_mode_msg(void *sel, _adapter *adapter)
 203 {
 204         struct registry_priv *regsty = &adapter->registrypriv;
 205
 206         DBG_871X_SEL_NL(sel, "RTW_ADAPTIVITY_MODE_");
 207
 208         if (regsty->adaptivity_mode == RTW_ADAPTIVITY_MODE_NORMAL) {
 209                 DBG_871X_SEL(sel, "NORMAL\n");
 210         } else if (regsty->adaptivity_mode == RTW_ADAPTIVITY_MODE_CARRIER_SENSE) {
 211                 DBG_871X_SEL(sel, "CARRIER_SENSE\n");
 212         } else {
 213                 DBG_871X_SEL(sel, "INVALID\n");
 214         }
 215 }
 216
 217 #define RTW_NHM_EN_DISABLE 0
 218 #define RTW_NHM_EN_ENABLE 1
 219
 220 void rtw_odm_nhm_en_msg(void *sel, _adapter *adapter)
 221 {
 222         struct registry_priv *regsty = &adapter->registrypriv;
 223
 224         DBG_871X_SEL_NL(sel, "RTW_NHM_EN_");
 225
 226         if (regsty->nhm_en == RTW_NHM_EN_DISABLE) {
 227                 DBG_871X_SEL(sel, "DISABLE\n");
 228         } else if (regsty->nhm_en == RTW_NHM_EN_ENABLE) {
 229                 DBG_871X_SEL(sel, "ENABLE\n");
 230         } else {
 231                 DBG_871X_SEL(sel, "INVALID\n");
 232         }
 233 }
 234
 235 bool rtw_odm_adaptivity_needed(_adapter *adapter)
 236 {
 237         struct registry_priv *regsty = &adapter->registrypriv;
 238         struct mlme_priv *mlme = &adapter->mlmepriv;
 239         bool ret = _FALSE;
 240
 241         if (regsty->adaptivity_en == RTW_ADAPTIVITY_EN_ENABLE
 242                 || regsty->adaptivity_en == RTW_ADAPTIVITY_EN_AUTO)
 243                 ret = _TRUE;
 244
 245         if (ret == _TRUE) {
 246                 rtw_odm_adaptivity_ver_msg(RTW_DBGDUMP, adapter);
 247                 rtw_odm_adaptivity_en_msg(RTW_DBGDUMP, adapter);
 248                 rtw_odm_adaptivity_mode_msg(RTW_DBGDUMP, adapter);
 249                 rtw_odm_nhm_en_msg(RTW_DBGDUMP, adapter);
 250         }
 251
 252         return ret;
 253 }
 254
 255 void rtw_odm_adaptivity_parm_msg(void *sel, _adapter *adapter)
 256 {
 257         HAL_DATA_TYPE *pHalData = GET_HAL_DATA(adapter);
 258         DM_ODM_T *odm = &pHalData->odmpriv;
 259
 260         rtw_odm_adaptivity_ver_msg(sel, adapter);
 261         rtw_odm_adaptivity_en_msg(sel, adapter);
 262         rtw_odm_adaptivity_mode_msg(sel, adapter);
 263         rtw_odm_nhm_en_msg(sel, adapter);
 264
 265         DBG_871X_SEL_NL(sel, "%10s %16s %8s %10s %11s %14s\n"
 266                 , "TH_L2H_ini", "TH_EDCCA_HL_diff", "IGI_Base", "ForceEDCCA", "AdapEn_RSSI", "IGI_LowerBound");
 267         DBG_871X_SEL_NL(sel, "0x%-8x %-16d 0x%-6x %-10d %-11u %-14u\n"
 268                 , (u8)odm->TH_L2H_ini
 269                 , odm->TH_EDCCA_HL_diff
 270                 , odm->IGI_Base
 271                 , odm->ForceEDCCA
 272                 , odm->AdapEn_RSSI
 273                 , odm->IGI_LowerBound
 274         );
 275
 276         DBG_871X_SEL_NL(sel, "%8s %9s\n", "EDCCA_ES","Adap_Flag");
 277         DBG_871X_SEL_NL(sel, "%-8x %-9x \n"
 278                 , odm->EDCCA_enable_state
 279                 , odm->adaptivity_flag
 280         );
 281
 282
 283 }
 284
 285 void rtw_odm_adaptivity_parm_set(_adapter *adapter, s8 TH_L2H_ini, s8 TH_EDCCA_HL_diff,
 286         s8 IGI_Base, bool ForceEDCCA, u8 AdapEn_RSSI, u8 IGI_LowerBound)
 287 {
 288         HAL_DATA_TYPE *pHalData = GET_HAL_DATA(adapter);
 289         DM_ODM_T *odm = &pHalData->odmpriv;
 290
 291         odm->TH_L2H_ini = TH_L2H_ini;
 292         odm->TH_EDCCA_HL_diff = TH_EDCCA_HL_diff;
 293         odm->IGI_Base = IGI_Base;
 294         odm->ForceEDCCA = ForceEDCCA;
 295         odm->AdapEn_RSSI = AdapEn_RSSI;
 296         odm->IGI_LowerBound = IGI_LowerBound;
 297 }
 298
 299 void rtw_odm_get_perpkt_rssi(void *sel, _adapter *adapter)
 300 {
 301         HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
 302         DM_ODM_T *odm = &(hal_data->odmpriv);
 303
 304         DBG_871X_SEL_NL(sel,"RxRate = %s, RSSI_A = %d(%%), RSSI_B = %d(%%)\n",
 305         HDATA_RATE(odm->RxRate), odm->RSSI_A, odm->RSSI_B);
 306 }
 307
 308
 309 void rtw_odm_acquirespinlock(_adapter *adapter, RT_SPINLOCK_TYPE type)
 310 {
 311         PHAL_DATA_TYPE  pHalData = GET_HAL_DATA(adapter);
 312         struct dm_priv  *pdmpriv = &pHalData->dmpriv;
 313         _irqL irqL;
 314
 315         switch(type)
 316         {
 317                 case RT_IQK_SPINLOCK:
 318                         _enter_critical_bh(&pdmpriv->IQKSpinLock, &irqL);
 319                 default:
 320                         break;
 321         }
 322 }
 323
 324 void rtw_odm_releasespinlock(_adapter *adapter, RT_SPINLOCK_TYPE type)
 325 {
 326         PHAL_DATA_TYPE  pHalData = GET_HAL_DATA(adapter);
 327         struct dm_priv  *pdmpriv = &pHalData->dmpriv;
 328         _irqL irqL;
 329
 330         switch(type)
 331         {
 332                 case RT_IQK_SPINLOCK:
 333                         _exit_critical_bh(&pdmpriv->IQKSpinLock, &irqL);
 334                 default:
 335                         break;
 336         }
 337 }
 338