1 /******************************************************************************
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3 * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
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5 * This program is free software; you can redistribute it and/or modify it
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6 * under the terms of version 2 of the GNU General Public License as
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7 * published by the Free Software Foundation.
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9 * This program is distributed in the hope that it will be useful, but WITHOUT
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10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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14 * You should have received a copy of the GNU General Public License along with
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15 * this program; if not, write to the Free Software Foundation, Inc.,
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16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
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19 ******************************************************************************/
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21 //============================================================
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23 //============================================================
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24 #include "Mp_Precomp.h"
\r
25 #include "phydm_precomp.h"
\r
29 Phydm_CheckAdaptivity(
\r
33 PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
\r
34 if(pDM_Odm->SupportAbility & ODM_BB_ADAPTIVITY)
\r
36 if(pDM_Odm->bAdaOn == TRUE)
\r
38 if(pDM_Odm->DynamicLinkAdaptivity == TRUE)
\r
40 if(pDM_Odm->bLinked && pDM_Odm->bCheck == FALSE)
\r
42 Phydm_NHMCounterStatistics(pDM_Odm);
\r
43 Phydm_CheckEnvironment(pDM_Odm);
\r
45 else if(!pDM_Odm->bLinked)
\r
47 pDM_Odm->bCheck = FALSE;
\r
52 Phydm_MACEDCCAState(pDM_Odm, PhyDM_DONT_IGNORE_EDCCA);
\r
53 pDM_Odm->adaptivity_flag = TRUE;
\r
58 Phydm_MACEDCCAState(pDM_Odm, PhyDM_IGNORE_EDCCA);
\r
59 pDM_Odm->adaptivity_flag = FALSE;
\r
65 Phydm_NHMCounterStatisticsInit(
\r
69 PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
\r
71 if(pDM_Odm->SupportICType & ODM_IC_11AC_SERIES)
\r
73 //PHY parameters initialize for ac series
\r
74 ODM_Write2Byte(pDM_Odm, ODM_REG_NHM_TIMER_11AC+2, 0xC350); //0x990[31:16]=0xC350 Time duration for NHM unit: us, 0xc350=200ms
\r
75 ODM_Write2Byte(pDM_Odm, ODM_REG_NHM_TH9_TH10_11AC+2, 0xffff); //0x994[31:16]=0xffff th_9, th_10
\r
76 //ODM_Write4Byte(pDM_Odm, ODM_REG_NHM_TH3_TO_TH0_11AC, 0xffffff5c); //0x998=0xffffff5c th_3, th_2, th_1, th_0
\r
77 ODM_Write4Byte(pDM_Odm, ODM_REG_NHM_TH3_TO_TH0_11AC, 0xffffff50); //0x998=0xffffff52 th_3, th_2, th_1, th_0
\r
78 ODM_Write4Byte(pDM_Odm, ODM_REG_NHM_TH7_TO_TH4_11AC, 0xffffffff); //0x99c=0xffffffff th_7, th_6, th_5, th_4
\r
79 ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH8_11AC, bMaskByte0, 0xff); //0x9a0[7:0]=0xff th_8
\r
80 //ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH9_TH10_11AC, BIT8|BIT9|BIT10, 0x7); //0x994[9:8]=3 enable CCX
\r
81 ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH9_TH10_11AC, BIT8|BIT9|BIT10, 0x1); //0x994[10:8]=1 ignoreCCA ignore PHYTXON enable CCX
\r
82 ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_9E8_11AC, BIT0, 0x1); //0x9e8[7]=1 max power among all RX ants
\r
85 else if (pDM_Odm->SupportICType & ODM_IC_11N_SERIES)
\r
87 //PHY parameters initialize for n series
\r
88 ODM_Write2Byte(pDM_Odm, ODM_REG_NHM_TIMER_11N+2, 0xC350); //0x894[31:16]=0x0xC350 Time duration for NHM unit: us, 0xc350=200ms
\r
89 //ODM_Write2Byte(pDM_Odm, ODM_REG_NHM_TIMER_11N+2, 0x4e20); //0x894[31:16]=0x4e20 Time duration for NHM unit: 4us, 0x4e20=80ms
\r
90 ODM_Write2Byte(pDM_Odm, ODM_REG_NHM_TH9_TH10_11N+2, 0xffff); //0x890[31:16]=0xffff th_9, th_10
\r
91 //ODM_Write4Byte(pDM_Odm, ODM_REG_NHM_TH3_TO_TH0_11N, 0xffffff5c); //0x898=0xffffff5c th_3, th_2, th_1, th_0
\r
92 ODM_Write4Byte(pDM_Odm, ODM_REG_NHM_TH3_TO_TH0_11N, 0xffffff50); //0x898=0xffffff52 th_3, th_2, th_1, th_0
\r
93 ODM_Write4Byte(pDM_Odm, ODM_REG_NHM_TH7_TO_TH4_11N, 0xffffffff); //0x89c=0xffffffff th_7, th_6, th_5, th_4
\r
94 ODM_SetBBReg(pDM_Odm, ODM_REG_FPGA0_IQK_11N, bMaskByte0, 0xff); //0xe28[7:0]=0xff th_8
\r
95 //ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH9_TH10_11N, BIT10|BIT9|BIT8, 0x7); //0x890[9:8]=3 enable CCX
\r
96 ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH9_TH10_11N, BIT10|BIT9|BIT8, 0x1); //0x890[10:8]=1 ignoreCCA ignore PHYTXON enable CCX
\r
97 ODM_SetBBReg(pDM_Odm, ODM_REG_OFDM_FA_RSTC_11N, BIT7, 0x1); //0xc0c[7]=1 max power among all RX ants
\r
102 Phydm_NHMCounterStatistics(
\r
106 PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
\r
108 if(!(pDM_Odm->SupportAbility & ODM_BB_NHM_CNT))
\r
112 Phydm_GetNHMCounterStatistics(pDM_Odm);
\r
114 // Reset NHM counter
\r
115 Phydm_NHMCounterStatisticsReset(pDM_Odm);
\r
119 Phydm_GetNHMCounterStatistics(
\r
123 PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
\r
124 u4Byte value32 = 0;
\r
126 if (pDM_Odm->SupportICType & ODM_IC_11AC_SERIES)
\r
127 value32 = ODM_GetBBReg(pDM_Odm, ODM_REG_NHM_CNT_11AC, bMaskDWord);
\r
128 else if (pDM_Odm->SupportICType & ODM_IC_11N_SERIES)
\r
129 value32 = ODM_GetBBReg(pDM_Odm, ODM_REG_NHM_CNT_11N, bMaskDWord);
\r
131 pDM_Odm->NHM_cnt_0 = (u1Byte)(value32 & bMaskByte0);
\r
132 pDM_Odm->NHM_cnt_1 = (u1Byte)((value32 & bMaskByte1)>>8);
\r
137 Phydm_NHMCounterStatisticsReset(
\r
141 PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
\r
143 if (pDM_Odm->SupportICType & ODM_IC_11AC_SERIES)
\r
145 ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH9_TH10_11AC, BIT1, 0);
\r
146 ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH9_TH10_11AC, BIT1, 1);
\r
148 else if (pDM_Odm->SupportICType & ODM_IC_11N_SERIES)
\r
150 ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH9_TH10_11N, BIT1, 0);
\r
151 ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH9_TH10_11N, BIT1, 1);
\r
160 PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
\r
162 pDM_Odm->adaptivity_flag = FALSE;
\r
163 pDM_Odm->tolerance_cnt = 3;
\r
164 pDM_Odm->NHMLastTxOkcnt = 0;
\r
165 pDM_Odm->NHMLastRxOkcnt = 0;
\r
166 pDM_Odm->NHMCurTxOkcnt = 0;
\r
167 pDM_Odm->NHMCurRxOkcnt = 0;
\r
171 Phydm_SetEDCCAThreshold(
\r
177 PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
\r
179 if(pDM_Odm->SupportICType & ODM_IC_11N_SERIES)
\r
181 ODM_SetBBReg(pDM_Odm,rOFDM0_ECCAThreshold, bMaskByte0, (u1Byte)L2H);
\r
182 ODM_SetBBReg(pDM_Odm,rOFDM0_ECCAThreshold, bMaskByte2, (u1Byte)H2L);
\r
184 else if(pDM_Odm->SupportICType & ODM_IC_11AC_SERIES)
\r
186 ODM_SetBBReg(pDM_Odm, rFPGA0_XB_LSSIReadBack, bMaskByte0, (u1Byte)L2H);
\r
187 ODM_SetBBReg(pDM_Odm, rFPGA0_XB_LSSIReadBack, bMaskByte1, (u1Byte)H2L);
\r
194 IN PhyDM_Trx_MUX_Type txMode,
\r
195 IN PhyDM_Trx_MUX_Type rxMode
\r
198 PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
\r
200 if (pDM_Odm->SupportICType & ODM_IC_11N_SERIES)
\r
202 ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_RPT_FORMAT_11N, BIT3|BIT2|BIT1, txMode); // set TXmod to standby mode to remove outside noise affect
\r
203 ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_RPT_FORMAT_11N, BIT22|BIT21|BIT20, rxMode); // set RXmod to standby mode to remove outside noise affect
\r
204 if(pDM_Odm->RFType > ODM_1T1R)
\r
206 ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_RPT_FORMAT_11N_B, BIT3|BIT2|BIT1, txMode); // set TXmod to standby mode to remove outside noise affect
\r
207 ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_RPT_FORMAT_11N_B, BIT22|BIT21|BIT20, rxMode); // set RXmod to standby mode to remove outside noise affect
\r
210 else if(pDM_Odm->SupportICType & ODM_IC_11AC_SERIES)
\r
212 ODM_SetBBReg(pDM_Odm, ODM_REG_TRMUX_11AC, BIT11|BIT10|BIT9|BIT8, txMode); // set TXmod to standby mode to remove outside noise affect
\r
213 ODM_SetBBReg(pDM_Odm, ODM_REG_TRMUX_11AC, BIT7|BIT6|BIT5|BIT4, rxMode); // set RXmod to standby mode to remove outside noise affect
\r
214 if(pDM_Odm->RFType > ODM_1T1R)
\r
216 ODM_SetBBReg(pDM_Odm, ODM_REG_TRMUX_11AC_B, BIT11|BIT10|BIT9|BIT8, txMode); // set TXmod to standby mode to remove outside noise affect
\r
217 ODM_SetBBReg(pDM_Odm, ODM_REG_TRMUX_11AC_B, BIT7|BIT6|BIT5|BIT4, rxMode); // set RXmod to standby mode to remove outside noise affect
\r
224 Phydm_MACEDCCAState(
\r
226 IN PhyDM_MACEDCCA_Type State
\r
229 PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
\r
230 if(State == PhyDM_IGNORE_EDCCA)
\r
232 ODM_SetMACReg(pDM_Odm, REG_TX_PTCL_CTRL, BIT15, 1); //ignore EDCCA reg520[15]=1
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233 ODM_SetMACReg(pDM_Odm, REG_RD_CTRL, BIT11, 0); //reg524[11]=0
\r
235 else // don't set MAC ignore EDCCA signal
\r
237 ODM_SetMACReg(pDM_Odm, REG_TX_PTCL_CTRL, BIT15, 0); //don't ignore EDCCA reg520[15]=0
\14\r
238 ODM_SetMACReg(pDM_Odm, REG_RD_CTRL, BIT11, 1); //reg524[11]=1
\r
241 pDM_Odm->EDCCA_enable_state = State;
\r
243 ODM_RT_TRACE(pDM_Odm,PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("EDCCA enable State = %d \n", State));
\r
252 PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
\r
255 Base = pDM_Odm->NHM_cnt_0 + pDM_Odm->NHM_cnt_1;
\r
259 pDM_Odm->NHM_cnt_0 = ((pDM_Odm->NHM_cnt_0) << 8) / Base;
\r
260 pDM_Odm->NHM_cnt_1 = ((pDM_Odm->NHM_cnt_1) << 8) / Base;
\r
262 if((pDM_Odm->NHM_cnt_0 - pDM_Odm->NHM_cnt_1) >= 100)
\r
263 return TRUE; // clean environment
\r
265 return FALSE; //noisy environment
\r
271 Phydm_CheckEnvironment(
\r
275 PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
\r
276 BOOLEAN isCleanEnvironment = FALSE;
\r
277 u1Byte i, clean = 0;
\r
279 if(pDM_Odm->bFirstLink == TRUE)
\r
281 pDM_Odm->adaptivity_flag = TRUE;
\r
282 pDM_Odm->bFirstLink = FALSE;
\r
287 if(pDM_Odm->NHMWait < 3) // Start enter NHM after 4 NHMWait
\r
289 pDM_Odm->NHMWait ++;
\r
290 Phydm_NHMCounterStatistics(pDM_Odm);
\r
295 Phydm_NHMCounterStatistics(pDM_Odm);
\r
296 isCleanEnvironment = Phydm_CalNHMcnt(pDM_Odm);
\r
297 if(isCleanEnvironment == TRUE)
\r
299 Phydm_MACEDCCAState(pDM_Odm, PhyDM_DONT_IGNORE_EDCCA);
\r
300 #if(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL))
\r
301 pDM_Odm->TH_L2H_ini = pDM_Odm->TH_L2H_ini_backup; //mode 1
\r
302 pDM_Odm->TH_EDCCA_HL_diff= pDM_Odm->TH_EDCCA_HL_diff_backup;
\r
304 pDM_Odm->adaptivity_flag = TRUE;
\r
308 #if(DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE))
\r
309 Phydm_MACEDCCAState(pDM_Odm, PhyDM_IGNORE_EDCCA);
\r
311 Phydm_MACEDCCAState(pDM_Odm, PhyDM_DONT_IGNORE_EDCCA);
\r
312 pDM_Odm->TH_L2H_ini = pDM_Odm->TH_L2H_ini_mode2; // for AP mode 2
\r
313 pDM_Odm->TH_EDCCA_HL_diff= pDM_Odm->TH_EDCCA_HL_diff_mode2;
\r
315 pDM_Odm->adaptivity_flag = FALSE;
\r
318 pDM_Odm->bFirstLink = TRUE;
\r
319 pDM_Odm->bCheck = TRUE;
\r
333 PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
\r
334 BOOLEAN bCleanEnvironment;
\r
336 bCleanEnvironment = Phydm_CalNHMcnt(pDM_Odm);
\r
338 pDM_Odm->NHMCurTxOkcnt = *(pDM_Odm->pNumTxBytesUnicast) - pDM_Odm->NHMLastTxOkcnt;
\r
339 pDM_Odm->NHMCurRxOkcnt = *(pDM_Odm->pNumRxBytesUnicast) - pDM_Odm->NHMLastRxOkcnt;
\r
340 pDM_Odm->NHMLastTxOkcnt = *(pDM_Odm->pNumTxBytesUnicast);
\r
341 pDM_Odm->NHMLastRxOkcnt = *(pDM_Odm->pNumRxBytesUnicast);
\r
342 ODM_RT_TRACE(pDM_Odm,PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("cnt_0=%d, cnt_1=%d, bCleanEnvironment = %d, NHMCurTxOkcnt = %llu, NHMCurRxOkcnt = %llu\n",
\r
343 pDM_Odm->NHM_cnt_0, pDM_Odm->NHM_cnt_1, bCleanEnvironment, pDM_Odm->NHMCurTxOkcnt, pDM_Odm->NHMCurRxOkcnt));
\r
345 if(pDM_Odm->NHMWait < 4) // Start enter NHM after 4 NHMWait
\r
347 pDM_Odm->NHMWait ++;
\r
348 Phydm_MACEDCCAState(pDM_Odm, PhyDM_IGNORE_EDCCA);
\r
350 else if ( ((pDM_Odm->NHMCurTxOkcnt>>10) > 2) && ((pDM_Odm->NHMCurTxOkcnt) + 1 > (u8Byte)(pDM_Odm->NHMCurRxOkcnt<<2) + 1)) //Tx > 4*Rx and Tx > 2Mb possible for adaptivity test
\r
352 if(bCleanEnvironment == TRUE || pDM_Odm->adaptivity_flag == TRUE)
\r
354 //Enable EDCCA since it is possible running Adaptivity testing
\r
355 pDM_Odm->adaptivity_flag = TRUE;
\r
356 Phydm_MACEDCCAState(pDM_Odm, PhyDM_DONT_IGNORE_EDCCA);
\r
357 pDM_Odm->tolerance_cnt = 0;
\r
358 #if(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL))
\r
359 pDM_Odm->TH_L2H_ini = pDM_Odm->TH_L2H_ini_backup;
\r
360 pDM_Odm->TH_EDCCA_HL_diff = pDM_Odm->TH_EDCCA_HL_diff_backup ;
\r
365 if(pDM_Odm->tolerance_cnt < 3)
\r
366 pDM_Odm->tolerance_cnt ++;
\r
369 #if(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL))
\r
370 pDM_Odm->TH_L2H_ini = pDM_Odm->TH_L2H_ini_mode2;
\r
371 pDM_Odm->TH_EDCCA_HL_diff = pDM_Odm->TH_EDCCA_HL_diff_mode2 ;
\r
373 Phydm_MACEDCCAState(pDM_Odm, PhyDM_IGNORE_EDCCA);
\r
375 pDM_Odm->adaptivity_flag = FALSE;
\r
381 if(pDM_Odm->adaptivity_flag == TRUE && bCleanEnvironment == FALSE)
\r
383 Phydm_MACEDCCAState(pDM_Odm, PhyDM_DONT_IGNORE_EDCCA);
\r
384 pDM_Odm->tolerance_cnt = 0;
\r
385 #if(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL))
\r
386 pDM_Odm->TH_L2H_ini = pDM_Odm->TH_L2H_ini_backup;
\r
387 pDM_Odm->TH_EDCCA_HL_diff = pDM_Odm->TH_EDCCA_HL_diff_backup ;
\r
390 #if(DM_ODM_SUPPORT_TYPE & ODM_AP) // for repeater mode add by YuChen 2014.06.23
\r
391 #ifdef UNIVERSAL_REPEATER
\r
392 else if((bCleanEnvironment == TRUE) && (pDM_Odm->VXD_bLinked) && ((pDM_Odm->NHMCurTxOkcnt>>10) > 1)) // clean environment and VXD linked and Tx TP>1Mb
\r
394 pDM_Odm->adaptivity_flag = TRUE;
\r
395 Phydm_MACEDCCAState(pDM_Odm, PhyDM_DONT_IGNORE_EDCCA);
\r
396 pDM_Odm->tolerance_cnt = 0;
\r
397 pDM_Odm->TH_L2H_ini = pDM_Odm->TH_L2H_ini_backup;
\r
398 pDM_Odm->TH_EDCCA_HL_diff = pDM_Odm->TH_EDCCA_HL_diff_backup ;
\r
401 #endif // for repeater mode add by YuChen 2014.06.23
\r
404 if(pDM_Odm->tolerance_cnt < 3)
\r
405 pDM_Odm->tolerance_cnt ++;
\r
408 #if(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL))
\r
409 pDM_Odm->TH_L2H_ini = pDM_Odm->TH_L2H_ini_mode2;
\r
410 pDM_Odm->TH_EDCCA_HL_diff = pDM_Odm->TH_EDCCA_HL_diff_mode2 ;
\r
412 Phydm_MACEDCCAState(pDM_Odm, PhyDM_IGNORE_EDCCA);
\r
414 pDM_Odm->adaptivity_flag = FALSE;
\r
419 ODM_RT_TRACE(pDM_Odm,PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("adaptivity_flag = %d\n ", pDM_Odm->adaptivity_flag));
\r
423 Phydm_SearchPwdBLowerBound(
\r
427 PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
\r
429 u1Byte cnt, IGI_Pause = 0x7f, IGI_Resume = 0x20, IGI = 0x50; //IGI = 0x50 for cal EDCCA lower bound
\r
430 u1Byte txEdcca1 = 0, txEdcca0 = 0;
\r
431 BOOLEAN bAdjust=TRUE;
\r
432 s1Byte TH_L2H_dmc, TH_H2L_dmc, IGI_target = 0x32;
\r
435 Phydm_SetTRxMux(pDM_Odm, PhyDM_STANDBY_MODE, PhyDM_STANDBY_MODE);
\r
436 ODM_Write_DIG(pDM_Odm, IGI_Pause);
\r
438 Diff = IGI_target -(s1Byte)IGI;
\r
439 TH_L2H_dmc = pDM_Odm->TH_L2H_ini + Diff;
\r
440 if(TH_L2H_dmc > 10)
\r
442 TH_H2L_dmc = TH_L2H_dmc - pDM_Odm->TH_EDCCA_HL_diff;
\r
444 Phydm_SetEDCCAThreshold(pDM_Odm, TH_H2L_dmc, TH_L2H_dmc);
\r
449 for(cnt=0; cnt<20; cnt ++)
\r
451 if (pDM_Odm->SupportICType & ODM_IC_11N_SERIES)
\r
452 value32 = ODM_GetBBReg(pDM_Odm,ODM_REG_RPT_11N, bMaskDWord);
\r
453 else if(pDM_Odm->SupportICType & ODM_IC_11AC_SERIES)
\r
454 value32 = ODM_GetBBReg(pDM_Odm,ODM_REG_RPT_11AC, bMaskDWord);
\r
456 if (value32 & BIT30 && (pDM_Odm->SupportICType & (ODM_RTL8723A|ODM_RTL8723B|ODM_RTL8188E)))
\r
457 txEdcca1 = txEdcca1 + 1;
\r
458 else if(value32 & BIT29)
\r
459 txEdcca1 = txEdcca1 + 1;
\r
461 txEdcca0 = txEdcca0 + 1;
\r
467 TH_L2H_dmc = TH_L2H_dmc + 1;
\r
468 if(TH_L2H_dmc > 10)
\r
470 TH_H2L_dmc = TH_L2H_dmc - pDM_Odm->TH_EDCCA_HL_diff;
\r
472 Phydm_SetEDCCAThreshold(pDM_Odm, TH_H2L_dmc, TH_L2H_dmc);
\r
477 if(TH_L2H_dmc == 10)
\r
480 pDM_Odm->H2L_lb = TH_H2L_dmc;
\r
481 pDM_Odm->L2H_lb = TH_L2H_dmc;
\r
482 pDM_Odm->Adaptivity_IGI_upper = IGI;
\r
488 pDM_Odm->H2L_lb = TH_H2L_dmc;
\r
489 pDM_Odm->L2H_lb = TH_L2H_dmc;
\r
490 pDM_Odm->Adaptivity_IGI_upper = IGI;
\r
494 Phydm_SetTRxMux(pDM_Odm, PhyDM_TX_MODE, PhyDM_RX_MODE);
\r
495 ODM_Write_DIG(pDM_Odm, IGI_Resume);
\r
496 Phydm_SetEDCCAThreshold(pDM_Odm, 0x7f, 0x7f); // resume to no link state
\r
500 Phydm_AdaptivityInit(
\r
504 PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
\r
505 #if(DM_ODM_SUPPORT_TYPE == ODM_WIN)
\r
506 PADAPTER pAdapter = pDM_Odm->Adapter;
\r
507 PMGNT_INFO pMgntInfo = &(pAdapter->MgntInfo);
\r
508 pDM_Odm->Carrier_Sense_enable = (BOOLEAN)pMgntInfo->RegEnableCarrierSense;
\r
509 pDM_Odm->NHM_enable = (BOOLEAN)pMgntInfo->RegNHMEnable;
\r
510 pDM_Odm->DynamicLinkAdaptivity = (BOOLEAN)pMgntInfo->RegDmLinkAdaptivity;
\r
511 #elif(DM_ODM_SUPPORT_TYPE == ODM_CE)
\r
512 pDM_Odm->Carrier_Sense_enable = (pDM_Odm->Adapter->registrypriv.adaptivity_mode!=0)?TRUE:FALSE;
\r
513 pDM_Odm->NHM_enable = (BOOLEAN)pDM_Odm->Adapter->registrypriv.nhm_en;
\r
514 pDM_Odm->DynamicLinkAdaptivity = FALSE; // Jeff please add this
\r
517 #if(DM_ODM_SUPPORT_TYPE & (ODM_CE|ODM_WIN))
\r
519 if(pDM_Odm->Carrier_Sense_enable == FALSE)
\r
521 #if(DM_ODM_SUPPORT_TYPE == ODM_WIN)
\r
522 if( pMgntInfo->RegL2HForAdaptivity != 0 )
\r
523 pDM_Odm->TH_L2H_ini = pMgntInfo->RegL2HForAdaptivity;
\r
526 pDM_Odm->TH_L2H_ini = 0xf5; // -7
\r
530 #if(DM_ODM_SUPPORT_TYPE == ODM_WIN)
\r
531 if( pMgntInfo->RegL2HForAdaptivity != 0 )
\r
532 pDM_Odm->TH_L2H_ini = pMgntInfo->RegL2HForAdaptivity;
\r
535 pDM_Odm->TH_L2H_ini = 0xa;
\r
538 pDM_Odm->AdapEn_RSSI = 20;
\r
540 #if(DM_ODM_SUPPORT_TYPE == ODM_WIN)
\r
541 if( pMgntInfo->RegHLDiffForAdaptivity != 0 )
\r
542 pDM_Odm->TH_EDCCA_HL_diff = pMgntInfo->RegHLDiffForAdaptivity;
\r
545 pDM_Odm->TH_EDCCA_HL_diff = 7;
\r
547 ODM_RT_TRACE(pDM_Odm,PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("TH_L2H_ini = 0x%x, TH_EDCCA_HL_diff = 0x%x\n", pDM_Odm->TH_L2H_ini, pDM_Odm->TH_EDCCA_HL_diff));
\r
549 #elif (DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL))
\r
550 prtl8192cd_priv priv = pDM_Odm->priv;
\r
552 if(pDM_Odm->Carrier_Sense_enable){
\r
553 pDM_Odm->TH_L2H_ini = 10;
\r
554 pDM_Odm->TH_EDCCA_HL_diff = 7;
\r
555 pDM_Odm->AdapEn_RSSI = 30;
\r
559 pDM_Odm->TH_L2H_ini = pDM_Odm->TH_L2H_ini_backup; //set by mib
\r
560 pDM_Odm->TH_EDCCA_HL_diff = 7;
\r
561 pDM_Odm->AdapEn_RSSI = 20;
\r
564 pDM_Odm->TH_L2H_ini_mode2 = 20;
\r
565 pDM_Odm->TH_EDCCA_HL_diff_mode2 = 8;
\r
566 //pDM_Odm->TH_L2H_ini_backup = pDM_Odm->TH_L2H_ini;
\r
567 pDM_Odm->TH_EDCCA_HL_diff_backup = pDM_Odm->TH_EDCCA_HL_diff ;
\r
568 if(priv->pshare->rf_ft_var.adaptivity_enable == 2)
\r
569 pDM_Odm->DynamicLinkAdaptivity = TRUE;
\r
571 pDM_Odm->DynamicLinkAdaptivity = FALSE;
\r
572 // pDM_Odm->NHM_enable = FALSE;
\r
575 pDM_Odm->IGI_Base = 0x32;
\r
576 pDM_Odm->IGI_target = 0x1c;
\r
577 pDM_Odm->ForceEDCCA = 0;
\r
578 pDM_Odm->H2L_lb= 0;
\r
579 pDM_Odm->L2H_lb= 0;
\r
580 pDM_Odm->Adaptivity_IGI_upper = 0;
\r
581 pDM_Odm->NHMWait = 0;
\r
582 Phydm_NHMBBInit(pDM_Odm);
\r
583 pDM_Odm->bCheck = FALSE;
\r
584 pDM_Odm->bFirstLink = TRUE;
\r
585 pDM_Odm->bAdaOn = TRUE;
\r
587 ODM_SetBBReg(pDM_Odm, REG_RD_CTRL, BIT11, 1); // stop counting if EDCCA is asserted
\r
589 //Search pwdB lower bound
\r
591 if (pDM_Odm->SupportICType & ODM_IC_11N_SERIES)
\r
592 ODM_SetBBReg(pDM_Odm,ODM_REG_DBG_RPT_11N, bMaskDWord, 0x208);
\r
593 else if(pDM_Odm->SupportICType & ODM_IC_11AC_SERIES)
\r
594 ODM_SetBBReg(pDM_Odm,ODM_REG_DBG_RPT_11AC, bMaskDWord, 0x209);
\r
595 Phydm_SearchPwdBLowerBound(pDM_Odm);
\r
597 Phydm_MACEDCCAState(pDM_Odm, PhyDM_IGNORE_EDCCA);
\r
607 PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
\r
608 s1Byte TH_L2H_dmc, TH_H2L_dmc, L2H_nolink_Band4 = 0x7f, H2L_nolink_Band4 = 0x7f;
\r
609 s1Byte Diff, IGI_target;
\r
610 BOOLEAN EDCCA_State = FALSE;
\r
612 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
\r
613 PADAPTER pAdapter = pDM_Odm->Adapter;
\r
614 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
\r
615 BOOLEAN bFwCurrentInPSMode=FALSE;
\r
616 PMGNT_INFO pMgntInfo = &(pAdapter->MgntInfo);
\r
618 pAdapter->HalFunc.GetHwRegHandler(pAdapter, HW_VAR_FW_PSMODE_STATUS, (pu1Byte)(&bFwCurrentInPSMode));
\r
620 // Disable EDCCA mode while under LPS mode, added by Roger, 2012.09.14.
\r
621 if(bFwCurrentInPSMode)
\r
625 if(!(pDM_Odm->SupportAbility & ODM_BB_ADAPTIVITY))
\r
627 ODM_RT_TRACE(pDM_Odm,PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("Go to odm_DynamicEDCCA() \n"));
\r
628 // Add by Neil Chen to enable edcca to MP Platform
\r
629 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
\r
631 if(pDM_Odm->SupportICType & ODM_IC_11N_SERIES)
\r
632 Phydm_DynamicEDCCA(pDM_Odm);
\r
637 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE))
\r
638 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
\r
639 if(pMgntInfo->RegEnableAdaptivity== 2)
\r
641 if (pDM_Odm->Adapter->registrypriv.adaptivity_en == 2)
\r
644 if(pDM_Odm->Carrier_Sense_enable == FALSE) // check domain Code for Adaptivity or CarrierSense
\r
646 if ((*pDM_Odm->pBandType == ODM_BAND_5G) &&
\r
647 !(pDM_Odm->odm_Regulation5G == REGULATION_ETSI || pDM_Odm->odm_Regulation5G == REGULATION_WW))
\r
649 ODM_RT_TRACE(pDM_Odm,PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("Adaptivity skip 5G domain code : %d \n", pDM_Odm->odm_Regulation5G));
\r
653 else if((*pDM_Odm->pBandType == ODM_BAND_2_4G) &&
\r
654 !(pDM_Odm->odm_Regulation2_4G == REGULATION_ETSI || pDM_Odm->odm_Regulation2_4G == REGULATION_WW))
\r
656 ODM_RT_TRACE(pDM_Odm,PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("Adaptivity skip 2.4G domain code : %d \n", pDM_Odm->odm_Regulation2_4G));
\r
660 else if ((*pDM_Odm->pBandType != ODM_BAND_2_4G) && (*pDM_Odm->pBandType != ODM_BAND_5G))
\r
662 ODM_RT_TRACE(pDM_Odm,PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("Adaptivity neither 2G nor 5G band, return\n"));
\r
668 if ((*pDM_Odm->pBandType == ODM_BAND_5G) &&
\r
669 !(pDM_Odm->odm_Regulation5G == REGULATION_ETSI || pDM_Odm->odm_Regulation5G == REGULATION_WW))
\r
671 ODM_RT_TRACE(pDM_Odm,PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("CarrierSense skip 5G domain code : %d\n", pDM_Odm->odm_Regulation5G));
\r
675 else if((*pDM_Odm->pBandType == ODM_BAND_2_4G) &&
\r
676 !(pDM_Odm->odm_Regulation2_4G == REGULATION_ETSI || pDM_Odm->odm_Regulation2_4G == REGULATION_WW))
\r
678 ODM_RT_TRACE(pDM_Odm,PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("CarrierSense skip 2.4G domain code : %d\n", pDM_Odm->odm_Regulation2_4G));
\r
682 else if ((*pDM_Odm->pBandType != ODM_BAND_2_4G) && (*pDM_Odm->pBandType != ODM_BAND_5G))
\r
684 ODM_RT_TRACE(pDM_Odm,PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("CarrierSense neither 2G nor 5G band, return\n"));
\r
692 ODM_RT_TRACE(pDM_Odm,PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("odm_Adaptivity() =====> \n"));
\r
693 ODM_RT_TRACE(pDM_Odm,PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("ForceEDCCA=%d, IGI_Base=0x%x, TH_L2H_ini = %d, TH_EDCCA_HL_diff = %d, AdapEn_RSSI = %d\n",
\r
694 pDM_Odm->ForceEDCCA, pDM_Odm->IGI_Base, pDM_Odm->TH_L2H_ini, pDM_Odm->TH_EDCCA_HL_diff, pDM_Odm->AdapEn_RSSI));
\r
696 if(pDM_Odm->SupportICType & ODM_IC_11AC_SERIES)
\r
697 ODM_SetBBReg(pDM_Odm, 0x800, BIT10, 0); //ADC_mask enable
\r
699 if(*pDM_Odm->pBandWidth == ODM_BW20M) //CHANNEL_WIDTH_20
\r
700 IGI_target = pDM_Odm->IGI_Base;
\r
701 else if(*pDM_Odm->pBandWidth == ODM_BW40M)
\r
702 IGI_target = pDM_Odm->IGI_Base + 2;
\r
703 else if(*pDM_Odm->pBandWidth == ODM_BW80M)
\r
704 IGI_target = pDM_Odm->IGI_Base + 2;
\r
706 IGI_target = pDM_Odm->IGI_Base;
\r
707 pDM_Odm->IGI_target = (u1Byte) IGI_target;
\r
709 if(*pDM_Odm->pChannel >= 149) // Band4 -> for AP : mode2, for sd4 and sd7 : turnoff adaptivity
\r
711 #if (DM_ODM_SUPPORT_TYPE & ODM_AP)
\r
712 if(pDM_Odm->bLinked)
\r
714 Diff = IGI_target -(s1Byte)IGI;
\r
715 L2H_nolink_Band4 = pDM_Odm->TH_L2H_ini_mode2 + Diff;
\r
716 if(L2H_nolink_Band4 > 10)
\r
717 L2H_nolink_Band4 = 10;
\r
718 H2L_nolink_Band4 = L2H_nolink_Band4 - pDM_Odm->TH_EDCCA_HL_diff_mode2;
\r
721 Phydm_SetEDCCAThreshold(pDM_Odm, H2L_nolink_Band4, L2H_nolink_Band4);
\r
725 if(!pDM_Odm->ForceEDCCA)
\r
727 if(pDM_Odm->RSSI_Min > pDM_Odm->AdapEn_RSSI)
\r
729 else if(pDM_Odm->RSSI_Min < (pDM_Odm->AdapEn_RSSI - 5))
\r
735 if(pDM_Odm->Carrier_Sense_enable == FALSE && pDM_Odm->NHM_enable == TRUE)
\r
736 Phydm_NHMBB(pDM_Odm);
\r
738 ODM_RT_TRACE(pDM_Odm,PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("BandWidth=%s, IGI_target=0x%x, EDCCA_State=%d, EDCCA_enable_state = %d\n",
\r
739 (*pDM_Odm->pBandWidth==ODM_BW80M)?"80M":((*pDM_Odm->pBandWidth==ODM_BW40M)?"40M":"20M"), IGI_target, EDCCA_State, pDM_Odm->EDCCA_enable_state));
\r
740 ODM_RT_TRACE(pDM_Odm,PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("RSSI_min = %d, AdapIGIUpper= 0x %x\n", pDM_Odm->RSSI_Min, pDM_Odm->Adaptivity_IGI_upper));
\r
743 if(EDCCA_State == 1)
\r
745 Diff = IGI_target -(s1Byte)IGI;
\r
746 TH_L2H_dmc = pDM_Odm->TH_L2H_ini + Diff;
\r
747 if(TH_L2H_dmc > 10)
\r
750 TH_H2L_dmc = TH_L2H_dmc - pDM_Odm->TH_EDCCA_HL_diff;
\r
752 //replace lower bound to prevent EDCCA always equal 1
\r
753 if(TH_H2L_dmc < pDM_Odm->H2L_lb)
\r
754 TH_H2L_dmc = pDM_Odm->H2L_lb;
\r
755 if(TH_L2H_dmc < pDM_Odm->L2H_lb)
\r
756 TH_L2H_dmc = pDM_Odm->L2H_lb;
\r
763 ODM_RT_TRACE(pDM_Odm,PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("IGI=0x%x, TH_L2H_dmc = %d, TH_H2L_dmc = %d, adaptivity_flg = %d, bAdaOn = %d, DynamicLinkAdaptivity = %d, NHM_enable = %d\n",
\r
764 IGI, TH_L2H_dmc, TH_H2L_dmc, pDM_Odm->adaptivity_flag, pDM_Odm->bAdaOn, pDM_Odm->DynamicLinkAdaptivity, pDM_Odm->NHM_enable));
\r
766 Phydm_SetEDCCAThreshold(pDM_Odm, TH_H2L_dmc, TH_L2H_dmc);
\r
771 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
\r
778 // This should be moved out of OUTSRC
\r
779 PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
\r
780 PADAPTER pAdapter = pDM_Odm->Adapter;
\r
781 // Enable EDCCA. The value is suggested by SD3 Wilson.
\r
784 // Revised for ASUS 11b/g performance issues, suggested by BB Neil, 2012.04.13.
\r
786 if((pDM_Odm->SupportICType == ODM_RTL8723A)&&(IS_WIRELESS_MODE_G(pAdapter)))
\r
788 //PlatformEFIOWrite1Byte(Adapter, rOFDM0_ECCAThreshold, 0x00);
\r
789 ODM_Write1Byte(pDM_Odm,rOFDM0_ECCAThreshold,0x00);
\r
790 ODM_Write1Byte(pDM_Odm,rOFDM0_ECCAThreshold+2,0xFD);
\r
795 //PlatformEFIOWrite1Byte(Adapter, rOFDM0_ECCAThreshold, 0x03);
\r
796 ODM_Write1Byte(pDM_Odm,rOFDM0_ECCAThreshold,0x03);
\r
797 ODM_Write1Byte(pDM_Odm,rOFDM0_ECCAThreshold+2,0x00);
\r
800 //PlatformEFIOWrite1Byte(Adapter, rOFDM0_ECCAThreshold+2, 0x00);
\r
804 Phydm_DisableEDCCA(
\r
809 PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
\r
810 ODM_Write1Byte(pDM_Odm, rOFDM0_ECCAThreshold, 0x7f);
\r
811 ODM_Write1Byte(pDM_Odm, rOFDM0_ECCAThreshold+2, 0x7f);
\r
815 // Description: According to initial gain value to determine to enable or disable EDCCA.
\r
817 // Suggested by SD3 Wilson. Added by tynli. 2011.11.25.
\r
820 Phydm_DynamicEDCCA(
\r
824 PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
\r
825 PADAPTER pAdapter = pDM_Odm->Adapter;
\r
826 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
\r
827 u1Byte RegC50, RegC58;
\r
828 BOOLEAN bEDCCAenable = FALSE;
\r
830 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN))
\r
831 BOOLEAN bFwCurrentInPSMode=FALSE;
\r
833 pAdapter->HalFunc.GetHwRegHandler(pAdapter, HW_VAR_FW_PSMODE_STATUS, (pu1Byte)(&bFwCurrentInPSMode));
\r
835 // Disable EDCCA mode while under LPS mode, added by Roger, 2012.09.14.
\r
836 if(bFwCurrentInPSMode)
\r
840 // 2013/11/14 Ken According to BB team Jame's suggestion, we need to disable soft AP mode EDCCA.
\r
841 // 2014/01/08 MH For Miracst AP mode test. We need to disable EDCCA. Otherwise, we may stop
\r
842 // to send beacon in noisy environment or platform.
\r
844 if(ACTING_AS_AP(pAdapter) || ACTING_AS_AP(GetFirstAPAdapter(pAdapter)))
\r
845 //if(ACTING_AS_AP(pAdapter))
\r
847 ODM_RT_TRACE(pDM_Odm,PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("At least One Port as AP disable EDCCA\n"));
\r
848 Phydm_DisableEDCCA(pDM_Odm);
\r
849 if(pHalData->bPreEdccaEnable)
\r
850 Phydm_DisableEDCCA(pDM_Odm);
\r
851 pHalData->bPreEdccaEnable = FALSE;
\r
855 RegC50 = (u1Byte)ODM_GetBBReg(pDM_Odm, rOFDM0_XAAGCCore1, bMaskByte0);
\r
856 RegC58 = (u1Byte)ODM_GetBBReg(pDM_Odm, rOFDM0_XBAGCCore1, bMaskByte0);
\r
859 if((RegC50 > 0x28 && RegC58 > 0x28) ||
\r
860 ((pDM_Odm->SupportICType == ODM_RTL8723A && IS_WIRELESS_MODE_G(pAdapter) && RegC50>0x26)) ||
\r
861 (pDM_Odm->SupportICType == ODM_RTL8188E && RegC50 > 0x28))
\r
863 if(!pHalData->bPreEdccaEnable)
\r
865 Phydm_EnableEDCCA(pDM_Odm);
\r
866 pHalData->bPreEdccaEnable = TRUE;
\r
870 else if((RegC50 < 0x25 && RegC58 < 0x25) || (pDM_Odm->SupportICType == ODM_RTL8188E && RegC50 < 0x25))
\r
872 if(pHalData->bPreEdccaEnable)
\r
874 Phydm_DisableEDCCA(pDM_Odm);
\r
875 pHalData->bPreEdccaEnable = FALSE;
\r