1 /******************************************************************************
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3 * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
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5 * This program is free software; you can redistribute it and/or modify it
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6 * under the terms of version 2 of the GNU General Public License as
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7 * published by the Free Software Foundation.
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9 * This program is distributed in the hope that it will be useful, but WITHOUT
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10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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14 * You should have received a copy of the GNU General Public License along with
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15 * this program; if not, write to the Free Software Foundation, Inc.,
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16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
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19 ******************************************************************************/
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22 #ifndef __HALDMOUTSRC_H__
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23 #define __HALDMOUTSRC_H__
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26 #include "odm_EdcaTurboCheck.h"
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27 #include "odm_DIG.h"
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28 #include "odm_PathDiv.h"
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29 #include "odm_RaInfo.h"
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30 #include "odm_DynamicBBPowerSaving.h"
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31 #include "odm_DynamicTxPower.h"
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32 #include "odm_CfoTracking.h"
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33 #include "odm_NoiseMonitor.h"
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35 //============================================================
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37 //============================================================
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39 // 2011/09/22 MH Define all team supprt ability.
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43 // 2011/09/22 MH Define for all teams. Please Define the constan in your precomp header.
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45 //#define DM_ODM_SUPPORT_AP 0
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46 //#define DM_ODM_SUPPORT_ADSL 0
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47 //#define DM_ODM_SUPPORT_CE 0
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48 //#define DM_ODM_SUPPORT_MP 1
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51 // 2011/09/28 MH Define ODM SW team support flag.
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57 // Antenna Switch Relative Definition.
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62 // Add new function SwAntDivCheck8192C().
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63 // This is the main function of Antenna diversity function before link.
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64 // Mainly, it just retains last scan result and scan again.
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65 // After that, it compares the scan result to see which one gets better RSSI.
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66 // It selects antenna with better receiving power and returns better scan result.
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70 #define TRAFFIC_LOW 0
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71 #define TRAFFIC_HIGH 1
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74 //============================================================
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75 //3 Tx Power Tracking
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76 //3============================================================
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77 #define DPK_DELTA_MAPPING_NUM 13
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78 #define index_mapping_HP_NUM 15
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79 #define OFDM_TABLE_SIZE 43
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80 #define CCK_TABLE_SIZE 33
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81 #define TXSCALE_TABLE_SIZE 37
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82 #define TXPWR_TRACK_TABLE_SIZE 30
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83 #define DELTA_SWINGIDX_SIZE 30
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86 //============================================================
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88 //3============================================================
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90 #define AFH_PSD 1 //0:normal PSD scan, 1: only do 20 pts PSD
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91 #define MODE_40M 0 //0:20M, 1:40M
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93 #define PSD_CHMIN 20 // Minimum channel number for BT AFH
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94 #define SIR_STEP_SIZE 3
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95 #define Smooth_Size_1 5
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96 #define Smooth_TH_1 3
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97 #define Smooth_Size_2 10
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98 #define Smooth_TH_2 4
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99 #define Smooth_Size_3 20
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100 #define Smooth_TH_3 4
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101 #define Smooth_Step_Size 5
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102 #define Adaptive_SIR 1
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103 #if(RTL8723_FPGA_VERIFICATION == 1)
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104 #define PSD_RESCAN 1
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106 #define PSD_RESCAN 4
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108 #define PSD_SCAN_INTERVAL 700 //ms
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112 //8723A High Power IGI Setting
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113 #define DM_DIG_HIGH_PWR_IGI_LOWER_BOUND 0x22
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114 #define DM_DIG_Gmode_HIGH_PWR_IGI_LOWER_BOUND 0x28
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115 #define DM_DIG_HIGH_PWR_THRESHOLD 0x3a
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116 #define DM_DIG_LOW_PWR_THRESHOLD 0x14
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119 #define ANTTESTALL 0x00 //Ant A or B will be Testing
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120 #define ANTTESTA 0x01 //Ant A will be Testing
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121 #define ANTTESTB 0x02 //Ant B will be testing
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123 //for 8723A Ant Definition--2012--06--07 due to different IC may be different ANT define
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124 #define MAIN_ANT 1 //Ant A or Ant Main
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125 #define AUX_ANT 2 //AntB or Ant Aux
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126 #define MAX_ANT 3 // 3 for AP using
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129 //Antenna Diversity Type
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130 #define SW_ANTDIV 0
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131 #define HW_ANTDIV 1
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132 //============================================================
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133 // structure and define
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134 //============================================================
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137 // 2011/09/20 MH Add for AP/ADSLpseudo DM structuer requirement.
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138 // We need to remove to other position???
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140 #if(DM_ODM_SUPPORT_TYPE & (ODM_CE|ODM_WIN))
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141 typedef struct rtl8192cd_priv {
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144 }rtl8192cd_priv, *prtl8192cd_priv;
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148 #if(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL))
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149 typedef struct _ADAPTER{
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151 #ifdef AP_BUILD_WORKAROUND
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152 HAL_DATA_TYPE* temp2;
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153 prtl8192cd_priv priv;
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155 }ADAPTER, *PADAPTER;
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158 #if (DM_ODM_SUPPORT_TYPE == ODM_AP)
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160 typedef struct _WLAN_STA{
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162 } WLAN_STA, *PRT_WLAN_STA;
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166 //Remove DIG by Yuchen
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168 //Remoce BB power saving by Yuchn
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170 //Remove DIG by yuchen
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172 typedef struct _Dynamic_Primary_CCA{
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173 u1Byte PriCCA_flag;
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176 u1Byte DupRTS_flag;
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177 u1Byte Monitor_flag;
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180 }Pri_CCA_T, *pPri_CCA_T;
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182 //Remove RA_T,*pRA_T by RS_James
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184 typedef struct _RX_High_Power_
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187 u1Byte PSD_func_trigger;
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188 u1Byte PSD_bitmap_RXHP[80];
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193 BOOLEAN First_time_enter;
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194 BOOLEAN RXHP_enable;
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197 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
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199 RT_WORK_ITEM PSDTimeWorkitem;
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205 #if(DM_ODM_SUPPORT_TYPE & (ODM_CE))
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206 #define ASSOCIATE_ENTRY_NUM 32 // Max size of AsocEntry[].
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207 #define ODM_ASSOCIATE_ENTRY_NUM ASSOCIATE_ENTRY_NUM
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209 #elif(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL))
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210 #define ASSOCIATE_ENTRY_NUM NUM_STAT
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211 #define ODM_ASSOCIATE_ENTRY_NUM ASSOCIATE_ENTRY_NUM+1
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215 // 2012/01/12 MH Revise for compatiable with other SW team.
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216 // 0 is for STA 1-n is for AP clients.
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218 #define ODM_ASSOCIATE_ENTRY_NUM ASSOCIATE_ENTRY_NUM+1// Default port only one
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221 //#ifdef CONFIG_ANTENNA_DIVERSITY
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222 // This indicates two different the steps.
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223 // In SWAW_STEP_PEAK, driver needs to switch antenna and listen to the signal on the air.
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224 // In SWAW_STEP_DETERMINE, driver just compares the signal captured in SWAW_STEP_PEAK
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225 // with original RSSI to determine if it is necessary to switch antenna.
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226 #define SWAW_STEP_PEAK 0
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227 #define SWAW_STEP_DETERMINE 1
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230 #define RSSI_MODE 1
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231 #define TRAFFIC_LOW 0
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232 #define TRAFFIC_HIGH 1
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233 #define TRAFFIC_UltraLOW 2
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235 typedef struct _SW_Antenna_Switch_
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237 u1Byte Double_chk_flag;
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242 u1Byte RSSI_Trying;
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244 u1Byte bTriggerAntennaSwitch;
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245 u1Byte SelectAntennaMap;
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246 u1Byte RSSI_target;
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249 // Before link Antenna Switch check
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250 u1Byte SWAS_NoLink_State;
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251 u4Byte SWAS_NoLink_BK_Reg860;
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252 u4Byte SWAS_NoLink_BK_Reg92c;
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253 BOOLEAN ANTA_ON; //To indicate Ant A is or not
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254 BOOLEAN ANTB_ON; //To indicate Ant B is on or not
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263 u8Byte lastTxOkCnt;
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264 u8Byte lastRxOkCnt;
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265 u8Byte TXByteCnt_A;
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266 u8Byte TXByteCnt_B;
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267 u8Byte RXByteCnt_A;
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268 u8Byte RXByteCnt_B;
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269 u1Byte TrafficLoad;
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271 u1Byte Train_time_flag;
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272 RT_TIMER SwAntennaSwitchTimer;
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273 RT_TIMER SwAntennaSwitchTimer_8723B;
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274 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
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276 RT_WORK_ITEM SwAntennaSwitchWorkitem;
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277 RT_WORK_ITEM SwAntennaSwitchWorkitem_8723B;
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281 #ifdef CONFIG_SW_ANTENNA_DIVERSITY
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282 _timer SwAntennaSwitchTimer;
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283 u8Byte lastTxOkCnt;
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284 u8Byte lastRxOkCnt;
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285 u8Byte TXByteCnt_A;
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286 u8Byte TXByteCnt_B;
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287 u8Byte RXByteCnt_A;
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288 u8Byte RXByteCnt_B;
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289 u1Byte DoubleComfirm;
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290 u1Byte TrafficLoad;
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291 //SW Antenna Switch
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296 #ifdef CONFIG_HW_ANTENNA_DIVERSITY
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297 //Hybrid Antenna Diversity
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298 u4Byte CCK_Ant1_Cnt[ASSOCIATE_ENTRY_NUM+1];
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299 u4Byte CCK_Ant2_Cnt[ASSOCIATE_ENTRY_NUM+1];
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300 u4Byte OFDM_Ant1_Cnt[ASSOCIATE_ENTRY_NUM+1];
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301 u4Byte OFDM_Ant2_Cnt[ASSOCIATE_ENTRY_NUM+1];
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302 u4Byte RSSI_Ant1_Sum[ASSOCIATE_ENTRY_NUM+1];
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303 u4Byte RSSI_Ant2_Sum[ASSOCIATE_ENTRY_NUM+1];
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304 u1Byte TxAnt[ASSOCIATE_ENTRY_NUM+1];
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314 //Remove Edca by YuChen
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316 //Remove ODM_RATE_ADAPTIVE by RS_James
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318 #if(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL))
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321 #ifdef ADSL_AP_BUILD_WORKAROUND
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322 #define MAX_TOLERANCE 5
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323 #define IQK_DELAY_TIME 1 //ms
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327 // Indicate different AP vendor for IOT issue.
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329 typedef enum _HT_IOT_PEER
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331 HT_IOT_PEER_UNKNOWN = 0,
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332 HT_IOT_PEER_REALTEK = 1,
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333 HT_IOT_PEER_REALTEK_92SE = 2,
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334 HT_IOT_PEER_BROADCOM = 3,
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335 HT_IOT_PEER_RALINK = 4,
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336 HT_IOT_PEER_ATHEROS = 5,
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337 HT_IOT_PEER_CISCO = 6,
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338 HT_IOT_PEER_MERU = 7,
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339 HT_IOT_PEER_MARVELL = 8,
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340 HT_IOT_PEER_REALTEK_SOFTAP = 9,// peer is RealTek SOFT_AP, by Bohn, 2009.12.17
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341 HT_IOT_PEER_SELF_SOFTAP = 10, // Self is SoftAP
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342 HT_IOT_PEER_AIRGO = 11,
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343 HT_IOT_PEER_INTEL = 12,
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344 HT_IOT_PEER_RTK_APCLIENT = 13,
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345 HT_IOT_PEER_REALTEK_81XX = 14,
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346 HT_IOT_PEER_REALTEK_WOW = 15,
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347 HT_IOT_PEER_MAX = 16
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348 }HT_IOT_PEER_E, *PHTIOT_PEER_E;
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349 #endif//#if(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL))
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353 #define IQK_MAC_REG_NUM 4
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354 #define IQK_ADDA_REG_NUM 16
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355 #define IQK_BB_REG_NUM_MAX 10
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356 #if (RTL8192D_SUPPORT==1)
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357 #define IQK_BB_REG_NUM 10
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359 #define IQK_BB_REG_NUM 9
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361 #define HP_THERMAL_NUM 8
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363 #define AVG_THERMAL_NUM 8
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364 #define IQK_Matrix_REG_NUM 8
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365 #define IQK_Matrix_Settings_NUM 14+24+21 // Channels_2_4G_NUM + Channels_5G_20M_NUM + Channels_5G
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367 #define DM_Type_ByFW 0
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368 #define DM_Type_ByDriver 1
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371 // Declare for common info
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373 #define MAX_PATH_NUM_92CS 2
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374 #define MAX_PATH_NUM_8188E 1
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375 #define MAX_PATH_NUM_8192E 2
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376 #define MAX_PATH_NUM_8723B 1
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377 #define MAX_PATH_NUM_8812A 2
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378 #define MAX_PATH_NUM_8821A 1
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380 #define IQK_THRESHOLD 8
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382 typedef struct _ODM_Phy_Status_Info_
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385 // Be care, if you want to add any element please insert between
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386 // RxPWDBAll & SignalStrength.
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388 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN))
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394 u1Byte SignalQuality; // in 0-100 index.
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395 s1Byte RxMIMOSignalQuality[4]; //per-path's EVM
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396 u1Byte RxMIMOEVMdbm[4]; //per-path's EVM dbm
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398 u1Byte RxMIMOSignalStrength[4];// in 0~100 index
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400 u2Byte Cfo_short[4]; // per-path's Cfo_short
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401 u2Byte Cfo_tail[4]; // per-path's Cfo_tail
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403 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE))
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404 s1Byte RxPower; // in dBm Translate from PWdB
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405 s1Byte RecvSignalPower; // Real power in dBm for this packet, no beautification and aggregation. Keep this raw info to be used for the other procedures.
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406 u1Byte BTRxRSSIPercentage;
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407 u1Byte SignalStrength; // in 0-100 index.
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409 s1Byte RxPwr[4]; //per-path's pwdb
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411 u1Byte RxSNR[4]; //per-path's SNR
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413 u1Byte btCoexPwrAdjust;
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414 }ODM_PHY_INFO_T,*PODM_PHY_INFO_T;
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417 typedef struct _ODM_Per_Pkt_Info_
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422 BOOLEAN bPacketMatchBSSID;
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423 BOOLEAN bPacketToSelf;
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424 BOOLEAN bPacketBeacon;
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425 }ODM_PACKET_INFO_T,*PODM_PACKET_INFO_T;
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428 typedef struct _ODM_Phy_Dbg_Info_
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430 //ODM Write,debug info
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432 u4Byte NumQryPhyStatus;
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433 u4Byte NumQryPhyStatusCCK;
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434 u4Byte NumQryPhyStatusOFDM;
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435 u1Byte NumQryBeaconPkt;
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439 }ODM_PHY_DBG_INFO_T;
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442 typedef struct _ODM_Mac_Status_Info_
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449 typedef enum tag_Dynamic_ODM_Support_Ability_Type
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452 ODM_DIG = 0x00000001,
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453 ODM_HIGH_POWER = 0x00000002,
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454 ODM_CCK_CCA_TH = 0x00000004,
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455 ODM_FA_STATISTICS = 0x00000008,
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456 ODM_RAMASK = 0x00000010,
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457 ODM_RSSI_MONITOR = 0x00000020,
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458 ODM_SW_ANTDIV = 0x00000040,
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459 ODM_HW_ANTDIV = 0x00000080,
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460 ODM_BB_PWRSV = 0x00000100,
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461 ODM_2TPATHDIV = 0x00000200,
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462 ODM_1TPATHDIV = 0x00000400,
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463 ODM_PSD2AFH = 0x00000800
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467 // 2011/20/20 MH For MP driver RT_WLAN_STA = STA_INFO_T
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468 // Please declare below ODM relative info in your STA info structure.
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471 typedef struct _ODM_STA_INFO{
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473 BOOLEAN bUsed; // record the sta status link or not?
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474 //u1Byte WirelessMode; //
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475 u1Byte IOTPeer; // Enum value. HT_IOT_PEER_E
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478 //1 PHY_STATUS_INFO
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479 u1Byte RSSI_Path[4]; //
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485 //1 TX_INFO (may changed by IC)
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486 //TX_INFO_T pTxInfo; // Define in IC folder. Move lower layer.
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488 u1Byte ANTSEL_A; //in Jagar: 4bit; others: 2bit
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489 u1Byte ANTSEL_B; //in Jagar: 4bit; others: 2bit
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490 u1Byte ANTSEL_C; //only in Jagar: 4bit
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491 u1Byte ANTSEL_D; //only in Jagar: 4bit
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492 u1Byte TX_ANTL; //not in Jagar: 2bit
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493 u1Byte TX_ANT_HT; //not in Jagar: 2bit
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494 u1Byte TX_ANT_CCK; //not in Jagar: 2bit
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495 u1Byte TXAGC_A; //not in Jagar: 4bit
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496 u1Byte TXAGC_B; //not in Jagar: 4bit
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497 u1Byte TXPWR_OFFSET; //only in Jagar: 3bit
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498 u1Byte TX_ANT; //only in Jagar: 4bit for TX_ANTL/TX_ANTHT/TX_ANT_CCK
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502 // Please use compile flag to disabe the strcutrue for other IC except 88E.
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503 // Move To lower layer.
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505 // ODM Write Wilson will handle this part(said by Luke.Lee)
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506 //TX_RPT_T pTxRpt; // Define in IC folder. Move lower layer.
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508 //1 For 88E RA (don't redefine the naming)
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511 u1Byte rssi_sta_ra;
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513 u1Byte Decision_rate;
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517 // Driver write Wilson handle.
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518 //1 TX_RPT (don't redefine the naming)
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519 u2Byte RTY[4]; // ???
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520 u2Byte TOTAL; // ???
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521 u2Byte DROP; // ???
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523 // Please use compile flag to disabe the strcutrue for other IC except 88E.
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527 }ODM_STA_INFO_T, *PODM_STA_INFO_T;
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531 // 2011/10/20 MH Define Common info enum for all team.
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533 typedef enum _ODM_Common_Info_Definition
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535 //-------------REMOVED CASE-----------//
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536 //ODM_CMNINFO_CCK_HP,
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537 //ODM_CMNINFO_RFPATH_ENABLE, // Define as ODM write???
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538 //ODM_CMNINFO_BT_COEXIST, // ODM_BT_COEXIST_E
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539 //ODM_CMNINFO_OP_MODE, // ODM_OPERATION_MODE_E
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540 //-------------REMOVED CASE-----------//
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546 //-----------HOOK BEFORE REG INIT-----------//
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547 ODM_CMNINFO_PLATFORM = 0,
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548 ODM_CMNINFO_ABILITY, // ODM_ABILITY_E
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549 ODM_CMNINFO_INTERFACE, // ODM_INTERFACE_E
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550 ODM_CMNINFO_MP_TEST_CHIP,
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551 ODM_CMNINFO_IC_TYPE, // ODM_IC_TYPE_E
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552 ODM_CMNINFO_CUT_VER, // ODM_CUT_VERSION_E
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553 ODM_CMNINFO_FAB_VER, // ODM_FAB_E
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554 ODM_CMNINFO_RF_TYPE, // ODM_RF_PATH_E or ODM_RF_TYPE_E?
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555 ODM_CMNINFO_RFE_TYPE,
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556 ODM_CMNINFO_BOARD_TYPE, // ODM_BOARD_TYPE_E
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557 ODM_CMNINFO_PACKAGE_TYPE,
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558 ODM_CMNINFO_EXT_LNA, // TRUE
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559 ODM_CMNINFO_5G_EXT_LNA,
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560 ODM_CMNINFO_EXT_PA,
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561 ODM_CMNINFO_5G_EXT_PA,
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566 ODM_CMNINFO_EXT_TRSW,
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567 ODM_CMNINFO_PATCH_ID, //CUSTOMER ID
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568 ODM_CMNINFO_BINHCT_TEST,
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569 ODM_CMNINFO_BWIFI_TEST,
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570 ODM_CMNINFO_SMART_CONCURRENT,
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571 ODM_CMNINFO_DOMAIN_CODE_2G,
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572 ODM_CMNINFO_DOMAIN_CODE_5G,
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573 //-----------HOOK BEFORE REG INIT-----------//
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579 //--------- POINTER REFERENCE-----------//
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580 ODM_CMNINFO_MAC_PHY_MODE, // ODM_MAC_PHY_MODE_E
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581 ODM_CMNINFO_TX_UNI,
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582 ODM_CMNINFO_RX_UNI,
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583 ODM_CMNINFO_WM_MODE, // ODM_WIRELESS_MODE_E
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584 ODM_CMNINFO_BAND, // ODM_BAND_TYPE_E
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585 ODM_CMNINFO_SEC_CHNL_OFFSET, // ODM_SEC_CHNL_OFFSET_E
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586 ODM_CMNINFO_SEC_MODE, // ODM_SECURITY_E
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587 ODM_CMNINFO_BW, // ODM_BW_E
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589 ODM_CMNINFO_FORCED_RATE,
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591 ODM_CMNINFO_DMSP_GET_VALUE,
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592 ODM_CMNINFO_BUDDY_ADAPTOR,
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593 ODM_CMNINFO_DMSP_IS_MASTER,
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595 ODM_CMNINFO_POWER_SAVING,
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596 ODM_CMNINFO_ONE_PATH_CCA, // ODM_CCA_PATH_E
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597 ODM_CMNINFO_DRV_STOP,
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598 ODM_CMNINFO_PNP_IN,
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599 ODM_CMNINFO_INIT_ON,
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600 ODM_CMNINFO_ANT_TEST,
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601 ODM_CMNINFO_NET_CLOSED,
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602 ODM_CMNINFO_MP_MODE,
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603 //ODM_CMNINFO_RTSTA_AID, // For win driver only?
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604 ODM_CMNINFO_FORCED_IGI_LB,
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605 //--------- POINTER REFERENCE-----------//
\r
607 //------------CALL BY VALUE-------------//
\r
608 ODM_CMNINFO_WIFI_DIRECT,
\r
609 ODM_CMNINFO_WIFI_DISPLAY,
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610 ODM_CMNINFO_LINK_IN_PROGRESS,
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612 ODM_CMNINFO_STATION_STATE,
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613 ODM_CMNINFO_RSSI_MIN,
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614 ODM_CMNINFO_DBG_COMP, // u8Byte
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615 ODM_CMNINFO_DBG_LEVEL, // u4Byte
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616 ODM_CMNINFO_RA_THRESHOLD_HIGH, // u1Byte
\r
617 ODM_CMNINFO_RA_THRESHOLD_LOW, // u1Byte
\r
618 ODM_CMNINFO_RF_ANTENNA_TYPE, // u1Byte
\r
619 ODM_CMNINFO_BT_ENABLED,
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620 ODM_CMNINFO_BT_HS_CONNECT_PROCESS,
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621 ODM_CMNINFO_BT_HS_RSSI,
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622 ODM_CMNINFO_BT_OPERATION,
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623 ODM_CMNINFO_BT_LIMITED_DIG, //Need to Limited Dig or not
\r
624 ODM_CMNINFO_BT_DISABLE_EDCA,
\r
625 //------------CALL BY VALUE-------------//
\r
628 // Dynamic ptr array hook itms.
\r
630 ODM_CMNINFO_STA_STATUS,
\r
631 ODM_CMNINFO_PHY_STATUS,
\r
632 ODM_CMNINFO_MAC_STATUS,
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640 // 2011/10/20 MH Define ODM support ability. ODM_CMNINFO_ABILITY
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642 typedef enum _ODM_Support_Ability_Definition
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645 // BB ODM section BIT 0-15
\r
648 ODM_BB_RA_MASK = BIT1,
\r
649 ODM_BB_DYNAMIC_TXPWR = BIT2,
\r
650 ODM_BB_FA_CNT = BIT3,
\r
651 ODM_BB_RSSI_MONITOR = BIT4,
\r
652 ODM_BB_CCK_PD = BIT5,
\r
653 ODM_BB_ANT_DIV = BIT6,
\r
654 ODM_BB_PWR_SAVE = BIT7,
\r
655 ODM_BB_PWR_TRAIN = BIT8,
\r
656 ODM_BB_RATE_ADAPTIVE = BIT9,
\r
657 ODM_BB_PATH_DIV = BIT10,
\r
658 ODM_BB_PSD = BIT11,
\r
659 ODM_BB_RXHP = BIT12,
\r
660 ODM_BB_ADAPTIVITY = BIT13,
\r
661 ODM_BB_CFO_TRACKING = BIT14,
\r
664 // MAC DM section BIT 16-23
\r
666 ODM_MAC_EDCA_TURBO = BIT16,
\r
667 ODM_MAC_EARLY_MODE = BIT17,
\r
670 // RF ODM section BIT 24-31
\r
672 ODM_RF_TX_PWR_TRACK = BIT24,
\r
673 ODM_RF_RX_GAIN_TRACK = BIT25,
\r
674 ODM_RF_CALIBRATION = BIT26,
\r
678 // ODM_CMNINFO_INTERFACE
\r
679 typedef enum tag_ODM_Support_Interface_Definition
\r
681 ODM_ITRF_PCIE = 0x1,
\r
682 ODM_ITRF_USB = 0x2,
\r
683 ODM_ITRF_SDIO = 0x4,
\r
684 ODM_ITRF_ALL = 0x7,
\r
687 // ODM_CMNINFO_IC_TYPE
\r
688 typedef enum tag_ODM_Support_IC_Type_Definition
\r
690 ODM_RTL8192S = BIT0,
\r
691 ODM_RTL8192C = BIT1,
\r
692 ODM_RTL8192D = BIT2,
\r
693 ODM_RTL8723A = BIT3,
\r
694 ODM_RTL8188E = BIT4,
\r
695 ODM_RTL8812 = BIT5,
\r
696 ODM_RTL8821 = BIT6,
\r
697 ODM_RTL8192E = BIT7,
\r
698 ODM_RTL8723B = BIT8,
\r
699 ODM_RTL8814A = BIT9,
\r
700 ODM_RTL8881A = BIT10,
\r
701 ODM_RTL8821B = BIT11
\r
704 #define ODM_IC_11N_SERIES (ODM_RTL8192S|ODM_RTL8192C|ODM_RTL8192D|ODM_RTL8723A|ODM_RTL8188E|ODM_RTL8192E|ODM_RTL8723B)
\r
705 #define ODM_IC_11AC_SERIES (ODM_RTL8812|ODM_RTL8821|ODM_RTL8814A|ODM_RTL8881A)
\r
707 #if (DM_ODM_SUPPORT_TYPE == ODM_AP)
\r
708 #ifdef RTK_AC_SUPPORT
\r
709 #define ODM_IC_11AC_SERIES_SUPPORT 1
\r
711 #define ODM_IC_11AC_SERIES_SUPPORT 0
\r
714 #define ODM_IC_11AC_SERIES_SUPPORT 1
\r
717 //ODM_CMNINFO_CUT_VER
\r
718 typedef enum tag_ODM_Cut_Version_Definition
\r
729 }ODM_CUT_VERSION_E;
\r
731 // ODM_CMNINFO_FAB_VER
\r
732 typedef enum tag_ODM_Fab_Version_Definition
\r
738 // ODM_CMNINFO_RF_TYPE
\r
740 // For example 1T2R (A+AB = BIT0|BIT4|BIT5)
\r
742 typedef enum tag_ODM_RF_Path_Bit_Definition
\r
744 ODM_RF_TX_A = BIT0,
\r
745 ODM_RF_TX_B = BIT1,
\r
746 ODM_RF_TX_C = BIT2,
\r
747 ODM_RF_TX_D = BIT3,
\r
748 ODM_RF_RX_A = BIT4,
\r
749 ODM_RF_RX_B = BIT5,
\r
750 ODM_RF_RX_C = BIT6,
\r
751 ODM_RF_RX_D = BIT7,
\r
755 typedef enum tag_ODM_RF_Type_Definition
\r
769 // ODM Dynamic common info value definition
\r
772 //typedef enum _MACPHY_MODE_8192D{
\r
773 // SINGLEMAC_SINGLEPHY,
\r
774 // DUALMAC_DUALPHY,
\r
775 // DUALMAC_SINGLEPHY,
\r
776 //}MACPHY_MODE_8192D,*PMACPHY_MODE_8192D;
\r
777 // Above is the original define in MP driver. Please use the same define. THX.
\r
778 typedef enum tag_ODM_MAC_PHY_Mode_Definition
\r
783 }ODM_MAC_PHY_MODE_E;
\r
786 typedef enum tag_BT_Coexist_Definition
\r
794 // ODM_CMNINFO_OP_MODE
\r
795 typedef enum tag_Operation_Mode_Definition
\r
797 ODM_NO_LINK = BIT0,
\r
800 ODM_POWERSAVE = BIT3,
\r
801 ODM_AP_MODE = BIT4,
\r
802 ODM_CLIENT_MODE = BIT5,
\r
804 ODM_WIFI_DIRECT = BIT7,
\r
805 ODM_WIFI_DISPLAY = BIT8,
\r
806 }ODM_OPERATION_MODE_E;
\r
808 // ODM_CMNINFO_WM_MODE
\r
809 #if (DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_CE))
\r
810 typedef enum tag_Wireless_Mode_Definition
\r
812 ODM_WM_UNKNOW = 0x0,
\r
816 ODM_WM_N24G = BIT3,
\r
818 ODM_WM_AUTO = BIT5,
\r
820 }ODM_WIRELESS_MODE_E;
\r
822 typedef enum tag_Wireless_Mode_Definition
\r
824 ODM_WM_UNKNOWN = 0x00,
\r
828 ODM_WM_AUTO = BIT3,
\r
829 ODM_WM_N24G = BIT4,
\r
831 ODM_WM_AC_5G = BIT6,
\r
832 ODM_WM_AC_24G = BIT7,
\r
833 ODM_WM_AC_ONLY = BIT8,
\r
835 }ODM_WIRELESS_MODE_E;
\r
838 // ODM_CMNINFO_BAND
\r
839 typedef enum tag_Band_Type_Definition
\r
848 // ODM_CMNINFO_SEC_CHNL_OFFSET
\r
849 typedef enum tag_Secondary_Channel_Offset_Definition
\r
854 }ODM_SEC_CHNL_OFFSET_E;
\r
856 // ODM_CMNINFO_SEC_MODE
\r
857 typedef enum tag_Security_Definition
\r
862 ODM_SEC_RESERVE = 3,
\r
863 ODM_SEC_AESCCMP = 4,
\r
864 ODM_SEC_WEP104 = 5,
\r
865 ODM_WEP_WPA_MIXED = 6, // WEP + WPA
\r
870 typedef enum tag_Bandwidth_Definition
\r
880 // ODM_CMNINFO_BOARD_TYPE
\r
881 // For non-AC-series IC , ODM_BOARD_5G_EXT_PA and ODM_BOARD_5G_EXT_LNA are ignored
\r
882 // For AC-series IC, external PA & LNA can be indivisuallly added on 2.4G and/or 5G
\r
883 typedef enum tag_Board_Definition
\r
885 ODM_BOARD_DEFAULT = 0, // The DEFAULT case.
\r
886 ODM_BOARD_MINICARD = BIT(0), // 0 = non-mini card, 1= mini card.
\r
887 ODM_BOARD_SLIM = BIT(1), // 0 = non-slim card, 1 = slim card
\r
888 ODM_BOARD_BT = BIT(2), // 0 = without BT card, 1 = with BT
\r
889 ODM_BOARD_EXT_PA = BIT(3), // 0 = no 2G ext-PA, 1 = existing 2G ext-PA
\r
890 ODM_BOARD_EXT_LNA = BIT(4), // 0 = no 2G ext-LNA, 1 = existing 2G ext-LNA
\r
891 ODM_BOARD_EXT_TRSW = BIT(5), // 0 = no ext-TRSW, 1 = existing ext-TRSW
\r
892 ODM_BOARD_EXT_PA_5G = BIT(6), // 0 = no 5G ext-PA, 1 = existing 5G ext-PA
\r
893 ODM_BOARD_EXT_LNA_5G= BIT(7), // 0 = no 5G ext-LNA, 1 = existing 5G ext-LNA
\r
896 typedef enum tag_ODM_Package_Definition
\r
898 ODM_PACKAGE_DEFAULT = 0,
\r
899 ODM_PACKAGE_QFN68 = BIT(0),
\r
900 ODM_PACKAGE_TFBGA90 = BIT(1),
\r
901 ODM_PACKAGE_TFBGA79 = BIT(2),
\r
902 }ODM_Package_TYPE_E;
\r
904 typedef enum tag_ODM_TYPE_GPA_Definition
\r
907 TYPE_GPA1 = BIT(1)|BIT(0)
\r
910 typedef enum tag_ODM_TYPE_APA_Definition
\r
913 TYPE_APA1 = BIT(1)|BIT(0)
\r
916 typedef enum tag_ODM_TYPE_GLNA_Definition
\r
919 TYPE_GLNA1 = BIT(2)|BIT(0),
\r
920 TYPE_GLNA2 = BIT(3)|BIT(1),
\r
921 TYPE_GLNA3 = BIT(3)|BIT(2)|BIT(1)|BIT(0)
\r
924 typedef enum tag_ODM_TYPE_ALNA_Definition
\r
927 TYPE_ALNA1 = BIT(2)|BIT(0),
\r
928 TYPE_ALNA2 = BIT(3)|BIT(1),
\r
929 TYPE_ALNA3 = BIT(3)|BIT(2)|BIT(1)|BIT(0)
\r
932 // ODM_CMNINFO_ONE_PATH_CCA
\r
933 typedef enum tag_CCA_Path
\r
941 typedef struct _ODM_RA_Info_
\r
948 u1Byte PreRssiStaRA;
\r
950 u1Byte DecisionRate;
\r
952 u1Byte HighestRate;
\r
961 u1Byte RAWaitingCounter;
\r
962 u1Byte RAPendingCounter;
\r
963 #if 1 //POWER_TRAINING_ACTIVE == 1 // For compile pass only~!
\r
964 u1Byte PTActive; // on or off
\r
965 u1Byte PTTryState; // 0 trying state, 1 for decision state
\r
966 u1Byte PTStage; // 0~6
\r
967 u1Byte PTStopCount; //Stop PT counter
\r
968 u1Byte PTPreRate; // if rate change do PT
\r
969 u1Byte PTPreRssi; // if RSSI change 5% do PT
\r
970 u1Byte PTModeSS; // decide whitch rate should do PT
\r
971 u1Byte RAstage; // StageRA, decide how many times RA will be done between PT
\r
972 u1Byte PTSmoothFactor;
\r
974 } ODM_RA_INFO_T,*PODM_RA_INFO_T;
\r
976 typedef struct _IQK_MATRIX_REGS_SETTING{
\r
978 s4Byte Value[3][IQK_Matrix_REG_NUM];
\r
979 BOOLEAN bBWIqkResultSaved[3];
\r
980 }IQK_MATRIX_REGS_SETTING,*PIQK_MATRIX_REGS_SETTING;
\r
983 //Remove PATHDIV_PARA struct to odm_PathDiv.h
\r
985 typedef struct ODM_RF_Calibration_Structure
\r
987 //for tx power tracking
\r
989 u4Byte RegA24; // for TempCCK
\r
995 u1Byte TXPowercount;
\r
996 BOOLEAN bTXPowerTrackingInit;
\r
997 BOOLEAN bTXPowerTracking;
\r
998 u1Byte TxPowerTrackControl; //for mp mode, turn off txpwrtracking as default
\r
1000 u1Byte InternalPA5G[2]; //pathA / pathB
\r
1002 u1Byte ThermalMeter[2]; // ThermalMeter, index 0 for RFIC0, and 1 for RFIC1
\r
1003 u1Byte ThermalValue;
\r
1004 u1Byte ThermalValue_LCK;
\r
1005 u1Byte ThermalValue_IQK;
\r
1006 u1Byte ThermalValue_DPK;
\r
1007 u1Byte ThermalValue_AVG[AVG_THERMAL_NUM];
\r
1008 u1Byte ThermalValue_AVG_index;
\r
1009 u1Byte ThermalValue_RxGain;
\r
1010 u1Byte ThermalValue_Crystal;
\r
1011 u1Byte ThermalValue_DPKstore;
\r
1012 u1Byte ThermalValue_DPKtrack;
\r
1013 BOOLEAN TxPowerTrackingInProgress;
\r
1015 BOOLEAN bReloadtxpowerindex;
\r
1016 u1Byte bRfPiEnable;
\r
1017 u4Byte TXPowerTrackingCallbackCnt; //cosa add for debug
\r
1020 //------------------------- Tx power Tracking -------------------------//
\r
1021 u1Byte bCCKinCH14;
\r
1023 u1Byte OFDM_index[MAX_RF_PATH];
\r
1024 s1Byte PowerIndexOffset[MAX_RF_PATH];
\r
1025 s1Byte DeltaPowerIndex[MAX_RF_PATH];
\r
1026 s1Byte DeltaPowerIndexLast[MAX_RF_PATH];
\r
1027 BOOLEAN bTxPowerChanged;
\r
1029 u1Byte ThermalValue_HP[HP_THERMAL_NUM];
\r
1030 u1Byte ThermalValue_HP_index;
\r
1031 IQK_MATRIX_REGS_SETTING IQKMatrixRegSetting[IQK_Matrix_Settings_NUM];
\r
1033 BOOLEAN bIQKInProgress;
\r
1036 s1Byte BBSwingDiff2G, BBSwingDiff5G; // Unit: dB
\r
1037 u1Byte DeltaSwingTableIdx_2GCCKA_P[DELTA_SWINGIDX_SIZE];
\r
1038 u1Byte DeltaSwingTableIdx_2GCCKA_N[DELTA_SWINGIDX_SIZE];
\r
1039 u1Byte DeltaSwingTableIdx_2GCCKB_P[DELTA_SWINGIDX_SIZE];
\r
1040 u1Byte DeltaSwingTableIdx_2GCCKB_N[DELTA_SWINGIDX_SIZE];
\r
1041 u1Byte DeltaSwingTableIdx_2GA_P[DELTA_SWINGIDX_SIZE];
\r
1042 u1Byte DeltaSwingTableIdx_2GA_N[DELTA_SWINGIDX_SIZE];
\r
1043 u1Byte DeltaSwingTableIdx_2GB_P[DELTA_SWINGIDX_SIZE];
\r
1044 u1Byte DeltaSwingTableIdx_2GB_N[DELTA_SWINGIDX_SIZE];
\r
1045 u1Byte DeltaSwingTableIdx_5GA_P[BAND_NUM][DELTA_SWINGIDX_SIZE];
\r
1046 u1Byte DeltaSwingTableIdx_5GA_N[BAND_NUM][DELTA_SWINGIDX_SIZE];
\r
1047 u1Byte DeltaSwingTableIdx_5GB_P[BAND_NUM][DELTA_SWINGIDX_SIZE];
\r
1048 u1Byte DeltaSwingTableIdx_5GB_N[BAND_NUM][DELTA_SWINGIDX_SIZE];
\r
1049 u1Byte DeltaSwingTableIdx_2GA_P_8188E[DELTA_SWINGIDX_SIZE];
\r
1050 u1Byte DeltaSwingTableIdx_2GA_N_8188E[DELTA_SWINGIDX_SIZE];
\r
1052 //--------------------------------------------------------------------//
\r
1064 BOOLEAN bIQKInitialized;
\r
1065 BOOLEAN bLCKInProgress;
\r
1066 BOOLEAN bAntennaDetected;
\r
1067 u4Byte ADDA_backup[IQK_ADDA_REG_NUM];
\r
1068 u4Byte IQK_MAC_backup[IQK_MAC_REG_NUM];
\r
1069 u4Byte IQK_BB_backup_recover[9];
\r
1070 u4Byte IQK_BB_backup[IQK_BB_REG_NUM];
\r
1073 u4Byte APKoutput[2][2]; //path A/B; output1_1a/output1_2a
\r
1075 u1Byte bAPKThermalMeterIgnore;
\r
1077 u1Byte bDPPathAOK;
\r
1078 u1Byte bDPPathBOK;
\r
1080 u4Byte TxIQC_8723B[2][3][2]; // { {S1: 0xc94, 0xc80, 0xc4c} , {S0: 0xc9c, 0xc88, 0xc4c}}
\r
1081 u4Byte RxIQC_8723B[2][2][2]; // { {S1: 0xc14, 0xca0} , {S0: 0xc14, 0xca0}}
\r
1084 }ODM_RF_CAL_T,*PODM_RF_CAL_T;
\r
1086 // ODM Dynamic common info value definition
\r
1089 typedef struct _FAST_ANTENNA_TRAINNING_
\r
1092 u1Byte antsel_rx_keep_0;
\r
1093 u1Byte antsel_rx_keep_1;
\r
1094 u1Byte antsel_rx_keep_2;
\r
1095 u4Byte antSumRSSI[7];
\r
1096 u4Byte antRSSIcnt[7];
\r
1097 u4Byte antAveRSSI[7];
\r
1100 u1Byte antsel_a[ODM_ASSOCIATE_ENTRY_NUM];
\r
1101 u1Byte antsel_b[ODM_ASSOCIATE_ENTRY_NUM];
\r
1102 u1Byte antsel_c[ODM_ASSOCIATE_ENTRY_NUM];
\r
1103 u4Byte MainAnt_Sum[ODM_ASSOCIATE_ENTRY_NUM];
\r
1104 u4Byte AuxAnt_Sum[ODM_ASSOCIATE_ENTRY_NUM];
\r
1105 u4Byte MainAnt_Cnt[ODM_ASSOCIATE_ENTRY_NUM];
\r
1106 u4Byte AuxAnt_Cnt[ODM_ASSOCIATE_ENTRY_NUM];
\r
1108 BOOLEAN bBecomeLinked;
\r
1109 u4Byte MinMaxRSSI;
\r
1110 u1Byte idx_AntDiv_counter_2G;
\r
1111 u1Byte idx_AntDiv_counter_5G;
\r
1112 u4Byte AntDiv_2G_5G;
\r
1113 u4Byte CCK_counter_main;
\r
1114 u4Byte CCK_counter_aux;
\r
1115 u4Byte OFDM_counter_main;
\r
1116 u4Byte OFDM_counter_aux;
\r
1120 typedef enum _FAT_STATE
\r
1122 FAT_NORMAL_STATE = 0,
\r
1123 FAT_TRAINING_STATE = 1,
\r
1124 }FAT_STATE_E, *PFAT_STATE_E;
\r
1126 typedef enum _ANT_DIV_TYPE
\r
1128 NO_ANTDIV = 0xFF,
\r
1129 CG_TRX_HW_ANTDIV = 0x01,
\r
1130 CGCS_RX_HW_ANTDIV = 0x02,
\r
1131 FIXED_HW_ANTDIV = 0x03,
\r
1132 CG_TRX_SMART_ANTDIV = 0x04,
\r
1133 CGCS_RX_SW_ANTDIV = 0x05,
\r
1134 S0S1_SW_ANTDIV = 0x06 //8723B intrnal switch S0 S1
\r
1135 }ANT_DIV_TYPE_E, *PANT_DIV_TYPE_E;
\r
1137 typedef struct _ODM_PATH_DIVERSITY_
\r
1139 u1Byte RespTxPath;
\r
1140 u1Byte PathSel[ODM_ASSOCIATE_ENTRY_NUM];
\r
1141 u4Byte PathA_Sum[ODM_ASSOCIATE_ENTRY_NUM];
\r
1142 u4Byte PathB_Sum[ODM_ASSOCIATE_ENTRY_NUM];
\r
1143 u4Byte PathA_Cnt[ODM_ASSOCIATE_ENTRY_NUM];
\r
1144 u4Byte PathB_Cnt[ODM_ASSOCIATE_ENTRY_NUM];
\r
1145 }PATHDIV_T, *pPATHDIV_T;
\r
1148 typedef enum _BASEBAND_CONFIG_PHY_REG_PG_VALUE_TYPE{
\r
1149 PHY_REG_PG_RELATIVE_VALUE = 0,
\r
1150 PHY_REG_PG_EXACT_VALUE = 1
\r
1151 } PHY_REG_PG_TYPE;
\r
1155 // Antenna detection information from single tone mechanism, added by Roger, 2012.11.27.
\r
1157 typedef struct _ANT_DETECTED_INFO{
\r
1158 BOOLEAN bAntDetected;
\r
1162 }ANT_DETECTED_INFO, *PANT_DETECTED_INFO;
\r
1165 // 2011/09/22 MH Copy from SD4 defined structure. We use to support PHY DM integration.
\r
1167 #if(DM_ODM_SUPPORT_TYPE & ODM_WIN)
\r
1168 #if (RT_PLATFORM != PLATFORM_LINUX)
\r
1171 struct DM_Out_Source_Dynamic_Mechanism_Structure
\r
1172 #else// for AP,ADSL,CE Team
\r
1173 typedef struct DM_Out_Source_Dynamic_Mechanism_Structure
\r
1176 //RT_TIMER FastAntTrainingTimer;
\r
1178 // Add for different team use temporarily
\r
1180 PADAPTER Adapter; // For CE/NIC team
\r
1181 prtl8192cd_priv priv; // For AP/ADSL team
\r
1182 // WHen you use Adapter or priv pointer, you must make sure the pointer is ready.
\r
1183 BOOLEAN odm_ready;
\r
1185 #if(DM_ODM_SUPPORT_TYPE & (ODM_CE|ODM_WIN))
\r
1186 rtl8192cd_priv fake_priv;
\r
1188 #if(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL))
\r
1189 // ADSL_AP_BUILD_WORKAROUND
\r
1190 ADAPTER fake_adapter;
\r
1193 PHY_REG_PG_TYPE PhyRegPgValueType;
\r
1194 u1Byte PhyRegPgVersion;
\r
1196 u8Byte DebugComponents;
\r
1197 u4Byte DebugLevel;
\r
1199 u4Byte NumQryPhyStatusAll; //CCK + OFDM
\r
1200 u4Byte LastNumQryPhyStatusAll;
\r
1202 BOOLEAN MPDIG_2G; //off MPDIG
\r
1205 //------ ODM HANDLE, DRIVER NEEDS NOT TO HOOK------//
\r
1206 BOOLEAN bCckHighPower;
\r
1207 u1Byte RFPathRxEnable; // ODM_CMNINFO_RFPATH_ENABLE
\r
1208 u1Byte ControlChannel;
\r
1209 //------ ODM HANDLE, DRIVER NEEDS NOT TO HOOK------//
\r
1211 //--------REMOVED COMMON INFO----------//
\r
1212 //u1Byte PseudoMacPhyMode;
\r
1213 //BOOLEAN *BTCoexist;
\r
1214 //BOOLEAN PseudoBtCoexist;
\r
1216 //BOOLEAN bAPMode;
\r
1217 //BOOLEAN bClientMode;
\r
1218 //BOOLEAN bAdHocMode;
\r
1219 //BOOLEAN bSlaveOfDMSP;
\r
1220 //--------REMOVED COMMON INFO----------//
\r
1223 //1 COMMON INFORMATION
\r
1228 //-----------HOOK BEFORE REG INIT-----------//
\r
1229 // ODM Platform info AP/ADSL/CE/MP = 1/2/3/4
\r
1230 u1Byte SupportPlatform;
\r
1231 // ODM Support Ability DIG/RATR/TX_PWR_TRACK/ ¡K¡K = 1/2/3/¡K
\r
1232 u4Byte SupportAbility;
\r
1233 // ODM PCIE/USB/SDIO = 1/2/3
\r
1234 u1Byte SupportInterface;
\r
1235 // ODM composite or independent. Bit oriented/ 92C+92D+ .... or any other type = 1/2/3/...
\r
1236 u4Byte SupportICType;
\r
1237 // Cut Version TestChip/A-cut/B-cut... = 0/1/2/3/...
\r
1238 u1Byte CutVersion;
\r
1239 // Fab Version TSMC/UMC = 0/1
\r
1240 u1Byte FabVersion;
\r
1241 // RF Type 4T4R/3T3R/2T2R/1T2R/1T1R/...
\r
1244 // Board Type Normal/HighPower/MiniCard/SLIM/Combo/... = 0/1/2/3/4/...
\r
1246 u1Byte PackageType;
\r
1251 // with external LNA NO/Yes = 0/1
\r
1254 // with external PA NO/Yes = 0/1
\r
1257 // with external TRSW NO/Yes = 0/1
\r
1259 u1Byte PatchID; //Customer ID
\r
1260 BOOLEAN bInHctTest;
\r
1261 BOOLEAN bWIFITest;
\r
1263 BOOLEAN bDualMacSmartConcurrent;
\r
1264 u4Byte BK_SupportAbility;
\r
1265 u1Byte AntDivType;
\r
1267 u1Byte odm_Regulation2_4G;
\r
1268 u1Byte odm_Regulation5G;
\r
1269 //-----------HOOK BEFORE REG INIT-----------//
\r
1274 //--------- POINTER REFERENCE-----------//
\r
1276 u1Byte u1Byte_temp;
\r
1277 BOOLEAN BOOLEAN_temp;
\r
1278 PADAPTER PADAPTER_temp;
\r
1280 // MAC PHY Mode SMSP/DMSP/DMDP = 0/1/2
\r
1281 u1Byte *pMacPhyMode;
\r
1282 //TX Unicast byte count
\r
1283 u8Byte *pNumTxBytesUnicast;
\r
1284 //RX Unicast byte count
\r
1285 u8Byte *pNumRxBytesUnicast;
\r
1286 // Wireless mode B/G/A/N = BIT0/BIT1/BIT2/BIT3
\r
1287 u1Byte *pWirelessMode; //ODM_WIRELESS_MODE_E
\r
1288 // Frequence band 2.4G/5G = 0/1
\r
1289 u1Byte *pBandType;
\r
1290 // Secondary channel offset don't_care/below/above = 0/1/2
\r
1291 u1Byte *pSecChOffset;
\r
1292 // Security mode Open/WEP/AES/TKIP = 0/1/2/3
\r
1293 u1Byte *pSecurity;
\r
1294 // BW info 20M/40M/80M = 0/1/2
\r
1295 u1Byte *pBandWidth;
\r
1296 // Central channel location Ch1/Ch2/....
\r
1297 u1Byte *pChannel; //central channel number
\r
1299 // Common info for 92D DMSP
\r
1301 BOOLEAN *pbGetValueFromOtherMac;
\r
1302 PADAPTER *pBuddyAdapter;
\r
1303 BOOLEAN *pbMasterOfDMSP; //MAC0: master, MAC1: slave
\r
1304 // Common info for Status
\r
1305 BOOLEAN *pbScanInProcess;
\r
1306 BOOLEAN *pbPowerSaving;
\r
1307 // CCA Path 2-path/path-A/path-B = 0/1/2; using ODM_CCA_PATH_E.
\r
1308 u1Byte *pOnePathCCA;
\r
1309 //pMgntInfo->AntennaTest
\r
1310 u1Byte *pAntennaTest;
\r
1311 BOOLEAN *pbNet_closed;
\r
1313 //u1Byte *pAidMap;
\r
1314 u1Byte *pu1ForcedIgiLb;
\r
1315 //--------- POINTER REFERENCE-----------//
\r
1316 pu2Byte pForcedDataRate;
\r
1317 //------------CALL BY VALUE-------------//
\r
1318 BOOLEAN bLinkInProcess;
\r
1319 BOOLEAN bWIFI_Direct;
\r
1320 BOOLEAN bWIFI_Display;
\r
1323 BOOLEAN bsta_state;
\r
1325 u1Byte InterfaceIndex; // Add for 92D dual MAC: 0--Mac0 1--Mac1
\r
1326 BOOLEAN bIsMPChip;
\r
1327 BOOLEAN bOneEntryOnly;
\r
1328 // Common info for BTDM
\r
1329 BOOLEAN bBtEnabled; // BT is disabled
\r
1330 BOOLEAN bBtConnectProcess; // BT HS is under connection progress.
\r
1331 u1Byte btHsRssi; // BT HS mode wifi rssi value.
\r
1332 BOOLEAN bBtHsOperation; // BT HS mode is under progress
\r
1333 BOOLEAN bBtDisableEdcaTurbo; // Under some condition, don't enable the EDCA Turbo
\r
1334 BOOLEAN bBtLimitedDig; // BT is busy.
\r
1335 //------------CALL BY VALUE-------------//
\r
1338 u8Byte RSSI_TRSW;
\r
1339 u8Byte RSSI_TRSW_H;
\r
1340 u8Byte RSSI_TRSW_L;
\r
1341 u8Byte RSSI_TRSW_iso;
\r
1344 BOOLEAN bNoisyState;
\r
1346 u1Byte LinkedInterval;
\r
1347 u1Byte preChannel;
\r
1348 u4Byte TxagcOffsetValueA;
\r
1349 BOOLEAN IsTxagcOffsetPositiveA;
\r
1350 u4Byte TxagcOffsetValueB;
\r
1351 BOOLEAN IsTxagcOffsetPositiveB;
\r
1352 u8Byte lastTxOkCnt;
\r
1353 u8Byte lastRxOkCnt;
\r
1354 u4Byte BbSwingOffsetA;
\r
1355 BOOLEAN IsBbSwingOffsetPositiveA;
\r
1356 u4Byte BbSwingOffsetB;
\r
1357 BOOLEAN IsBbSwingOffsetPositiveB;
\r
1358 s1Byte TH_L2H_ini;
\r
1359 s1Byte TH_EDCCA_HL_diff;
\r
1361 u1Byte IGI_target;
\r
1362 BOOLEAN ForceEDCCA;
\r
1363 u1Byte AdapEn_RSSI;
\r
1364 s1Byte Force_TH_H;
\r
1365 s1Byte Force_TH_L;
\r
1366 u1Byte IGI_LowerBound;
\r
1367 u1Byte antdiv_rssi;
\r
1369 u1Byte pre_AntType;
\r
1370 u1Byte antdiv_period;
\r
1371 u1Byte antdiv_select;
\r
1372 u1Byte NdpaPeriod;
\r
1374 // add by Yu Cehn for adaptivtiy
\r
1375 BOOLEAN adaptivity_flag;
\r
1376 BOOLEAN NHM_disable;
\r
1377 BOOLEAN TxHangFlg;
\r
1378 BOOLEAN Carrier_Sense_enable;
\r
1379 u1Byte tolerance_cnt;
\r
1380 u8Byte NHMCurTxOkcnt;
\r
1381 u8Byte NHMCurRxOkcnt;
\r
1382 u8Byte NHMLastTxOkcnt;
\r
1383 u8Byte NHMLastRxOkcnt;
\r
1388 u1Byte Adaptivity_IGI_upper;
\r
1392 ODM_NOISE_MONITOR noise_level;//[ODM_MAX_CHANNEL_NUM];
\r
1394 //2 Define STA info.
\r
1396 // 2012/01/12 MH For MP, we need to reduce one array pointer for default port.??
\r
1397 PSTA_INFO_T pODM_StaInfo[ODM_ASSOCIATE_ENTRY_NUM];
\r
1399 #if (RATE_ADAPTIVE_SUPPORT == 1)
\r
1400 u2Byte CurrminRptTime;
\r
1401 ODM_RA_INFO_T RAInfo[ODM_ASSOCIATE_ENTRY_NUM]; //See HalMacID support
\r
1404 // 2012/02/14 MH Add to share 88E ra with other SW team.
\r
1405 // We need to colelct all support abilit to a proper area.
\r
1407 BOOLEAN RaSupport88E;
\r
1409 // Define ...........
\r
1411 // Latest packet phy info (ODM write)
\r
1412 ODM_PHY_DBG_INFO_T PhyDbgInfo;
\r
1413 //PHY_INFO_88E PhyInfo;
\r
1415 // Latest packet phy info (ODM write)
\r
1416 ODM_MAC_INFO *pMacInfo;
\r
1417 //MAC_INFO_88E MacInfo;
\r
1419 // Different Team independt structure??
\r
1422 //TX_RTP_CMN TX_retrpo;
\r
1423 //TX_RTP_88E TX_retrpo;
\r
1424 //TX_RTP_8195 TX_retrpo;
\r
1429 FAT_T DM_FatTable;
\r
1430 DIG_T DM_DigTable;
\r
1432 Pri_CCA_T DM_PriCCA;
\r
1433 RXHP_T DM_RXHP_Table;
\r
1434 RA_T DM_RA_Table;
\r
1435 FALSE_ALARM_STATISTICS FalseAlmCnt;
\r
1436 FALSE_ALARM_STATISTICS FlaseAlmCntBuddyAdapter;
\r
1437 //#ifdef CONFIG_ANTENNA_DIVERSITY
\r
1438 SWAT_T DM_SWAT_Table;
\r
1439 BOOLEAN RSSI_test;
\r
1440 CFO_TRACKING DM_CfoTrack;
\r
1443 #if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
\r
1445 PATHDIV_PARA pathIQK;
\r
1448 EDCA_T DM_EDCA_Table;
\r
1449 u4Byte WMMEDCA_BE;
\r
1450 PATHDIV_T DM_PathDiv;
\r
1451 // Copy from SD4 structure
\r
1453 // ==================================================
\r
1457 //u1Byte DM_Type;
\r
1458 //u1Byte PSD_Report_RXHP[80]; // Add By Gary
\r
1459 //u1Byte PSD_func_flag; // Add By Gary
\r
1461 //u1Byte bDMInitialGainEnable;
\r
1462 //u1Byte binitialized; // for dm_initial_gain_Multi_STA use.
\r
1463 //for Antenna diversity
\r
1464 //u8 AntDivCfg;// 0:OFF , 1:ON, 2:by efuse
\r
1465 //PSTA_INFO_T RSSI_target;
\r
1467 BOOLEAN *pbDriverStopped;
\r
1468 BOOLEAN *pbDriverIsGoingToPnpSetPowerSleep;
\r
1469 BOOLEAN *pinit_adpt_in_progress;
\r
1472 BOOLEAN bUserAssignLevel;
\r
1473 RT_TIMER PSDTimer;
\r
1474 u1Byte RSSI_BT; //come from BT
\r
1475 BOOLEAN bPSDinProcess;
\r
1476 BOOLEAN bPSDactive;
\r
1477 BOOLEAN bDMInitialGainEnable;
\r
1480 RT_TIMER MPT_DIGTimer;
\r
1482 //for rate adaptive, in fact, 88c/92c fw will handle this
\r
1483 u1Byte bUseRAMask;
\r
1485 ODM_RATE_ADAPTIVE RateAdaptive;
\r
1487 ANT_DETECTED_INFO AntDetectedInfo; // Antenna detected information for RSSI tool
\r
1489 ODM_RF_CAL_T RFCalibrateInfo;
\r
1492 // TX power tracking
\r
1494 u1Byte BbSwingIdxOfdm[MAX_RF_PATH];
\r
1495 u1Byte BbSwingIdxOfdmCurrent;
\r
1496 u1Byte BbSwingIdxOfdmBase[MAX_RF_PATH];
\r
1497 BOOLEAN BbSwingFlagOfdm;
\r
1498 u1Byte BbSwingIdxCck;
\r
1499 u1Byte BbSwingIdxCckCurrent;
\r
1500 u1Byte BbSwingIdxCckBase;
\r
1501 u1Byte DefaultOfdmIndex;
\r
1502 u1Byte DefaultCckIndex;
\r
1503 BOOLEAN BbSwingFlagCck;
\r
1505 s1Byte Absolute_OFDMSwingIdx[MAX_RF_PATH];
\r
1506 s1Byte Remnant_OFDMSwingIdx[MAX_RF_PATH];
\r
1507 s1Byte Remnant_CCKSwingIdx;
\r
1508 s1Byte Modify_TxAGC_Value; //Remnat compensate value at TxAGC
\r
1509 BOOLEAN Modify_TxAGC_Flag_PathA;
\r
1510 BOOLEAN Modify_TxAGC_Flag_PathB;
\r
1511 BOOLEAN Modify_TxAGC_Flag_PathA_CCK;
\r
1514 // ODM system resource.
\r
1517 // ODM relative time.
\r
1518 RT_TIMER PathDivSwitchTimer;
\r
1519 //2011.09.27 add for Path Diversity
\r
1520 RT_TIMER CCKPathDiversityTimer;
\r
1521 RT_TIMER FastAntTrainingTimer;
\r
1523 // ODM relative workitem.
\r
1524 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
\r
1526 RT_WORK_ITEM PathDivSwitchWorkitem;
\r
1527 RT_WORK_ITEM CCKPathDiversityWorkitem;
\r
1528 RT_WORK_ITEM FastAntTrainingWorkitem;
\r
1529 RT_WORK_ITEM MPT_DIGWorkitem;
\r
1530 RT_WORK_ITEM RaRptWorkitem;
\r
1534 #if(DM_ODM_SUPPORT_TYPE & ODM_WIN)
\r
1536 #if (RT_PLATFORM != PLATFORM_LINUX)
\r
1537 } DM_ODM_T, *PDM_ODM_T; // DM_Dynamic_Mechanism_Structure
\r
1542 #else// for AP,ADSL,CE Team
\r
1543 } DM_ODM_T, *PDM_ODM_T; // DM_Dynamic_Mechanism_Structure
\r
1548 #if 1 //92c-series
\r
1549 #define ODM_RF_PATH_MAX 2
\r
1550 #else //jaguar - series
\r
1551 #define ODM_RF_PATH_MAX 4
\r
1554 typedef enum _ODM_RF_RADIO_PATH {
\r
1555 ODM_RF_PATH_A = 0, //Radio Path A
\r
1556 ODM_RF_PATH_B = 1, //Radio Path B
\r
1557 ODM_RF_PATH_C = 2, //Radio Path C
\r
1558 ODM_RF_PATH_D = 3, //Radio Path D
\r
1569 // ODM_RF_PATH_MAX, //Max RF number 90 support
\r
1570 } ODM_RF_RADIO_PATH_E, *PODM_RF_RADIO_PATH_E;
\r
1572 typedef enum _ODM_RF_CONTENT{
\r
1573 odm_radioa_txt = 0x1000,
\r
1574 odm_radiob_txt = 0x1001,
\r
1575 odm_radioc_txt = 0x1002,
\r
1576 odm_radiod_txt = 0x1003
\r
1579 typedef enum _ODM_BB_Config_Type{
\r
1580 CONFIG_BB_PHY_REG,
\r
1581 CONFIG_BB_AGC_TAB,
\r
1582 CONFIG_BB_AGC_TAB_2G,
\r
1583 CONFIG_BB_AGC_TAB_5G,
\r
1584 CONFIG_BB_PHY_REG_PG,
\r
1585 CONFIG_BB_PHY_REG_MP,
\r
1586 CONFIG_BB_AGC_TAB_DIFF,
\r
1587 } ODM_BB_Config_Type, *PODM_BB_Config_Type;
\r
1589 typedef enum _ODM_RF_Config_Type{
\r
1591 CONFIG_RF_TXPWR_LMT,
\r
1592 } ODM_RF_Config_Type, *PODM_RF_Config_Type;
\r
1594 typedef enum _ODM_FW_Config_Type{
\r
1600 CONFIG_FW_WoWLAN_2,
\r
1601 CONFIG_FW_AP_WoWLAN,
\r
1603 } ODM_FW_Config_Type;
\r
1606 #if (DM_ODM_SUPPORT_TYPE != ODM_WIN)
\r
1607 typedef enum _RT_STATUS{
\r
1608 RT_STATUS_SUCCESS,
\r
1609 RT_STATUS_FAILURE,
\r
1610 RT_STATUS_PENDING,
\r
1611 RT_STATUS_RESOURCE,
\r
1612 RT_STATUS_INVALID_CONTEXT,
\r
1613 RT_STATUS_INVALID_PARAMETER,
\r
1614 RT_STATUS_NOT_SUPPORT,
\r
1615 RT_STATUS_OS_API_FAILED,
\r
1616 }RT_STATUS,*PRT_STATUS;
\r
1617 #endif // end of RT_STATUS definition
\r
1619 #ifdef REMOVE_PACK
\r
1623 //#include "odm_function.h"
\r
1625 //3===========================================================
\r
1627 //3===========================================================
\r
1629 //Remove DIG by Yuchen
\r
1631 //3===========================================================
\r
1632 //3 AGC RX High Power Mode
\r
1633 //3===========================================================
\r
1634 #define LNA_Low_Gain_1 0x64
\r
1635 #define LNA_Low_Gain_2 0x5A
\r
1636 #define LNA_Low_Gain_3 0x58
\r
1638 #define FA_RXHP_TH1 5000
\r
1639 #define FA_RXHP_TH2 1500
\r
1640 #define FA_RXHP_TH3 800
\r
1641 #define FA_RXHP_TH4 600
\r
1642 #define FA_RXHP_TH5 500
\r
1644 //3===========================================================
\r
1646 //3===========================================================
\r
1648 //3===========================================================
\r
1649 //3 Dynamic Tx Power
\r
1650 //3===========================================================
\r
1651 //Dynamic Tx Power Control Threshold
\r
1653 //Remove By YuChen
\r
1655 //3===========================================================
\r
1656 //3 Tx Power Tracking
\r
1657 //3===========================================================
\r
1658 #if 0 //mask this, since these have been defined in typdef.h, vivi
\r
1659 #define OFDM_TABLE_SIZE 43
\r
1660 #define CCK_TABLE_SIZE 33
\r
1664 //3===========================================================
\r
1666 //3===========================================================
\r
1667 //Remove to odm_RaInfo.h by RS_James
\r
1669 //3===========================================================
\r
1671 //3===========================================================
\r
1673 typedef enum tag_1R_CCA_Type_Definition
\r
1680 typedef enum tag_RF_Type_Definition
\r
1687 //3===========================================================
\r
1688 //3 Antenna Diversity
\r
1689 //3===========================================================
\r
1690 typedef enum tag_SW_Antenna_Switch_Definition
\r
1698 // Maximal number of antenna detection mechanism needs to perform, added by Roger, 2011.12.28.
\r
1699 #define MAX_ANTENNA_DETECTION_CNT 10
\r
1702 // Extern Global Variables.
\r
1704 extern u4Byte OFDMSwingTable[OFDM_TABLE_SIZE];
\r
1705 extern u1Byte CCKSwingTable_Ch1_Ch13[CCK_TABLE_SIZE][8];
\r
1706 extern u1Byte CCKSwingTable_Ch14 [CCK_TABLE_SIZE][8];
\r
1708 extern u4Byte OFDMSwingTable_New[OFDM_TABLE_SIZE];
\r
1709 extern u1Byte CCKSwingTable_Ch1_Ch13_New[CCK_TABLE_SIZE][8];
\r
1710 extern u1Byte CCKSwingTable_Ch14_New [CCK_TABLE_SIZE][8];
\r
1712 extern u4Byte TxScalingTable_Jaguar[TXSCALE_TABLE_SIZE];
\r
1714 // <20121018, Kordan> In case fail to read TxPowerTrack.txt, we use the table of 88E as the default table.
\r
1715 static u1Byte DeltaSwingTableIdx_2GA_P_8188E[] = {0, 0, 0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 4, 4, 4, 4, 4, 4, 5, 5, 7, 7, 8, 8, 8, 9, 9, 9, 9, 9};
\r
1716 static u1Byte DeltaSwingTableIdx_2GA_N_8188E[] = {0, 0, 0, 2, 2, 3, 3, 4, 4, 4, 4, 5, 5, 6, 6, 7, 7, 7, 7, 8, 8, 9, 9, 10, 10, 10, 11, 11, 11, 11};
\r
1719 // check Sta pointer valid or not
\r
1721 #if (DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL))
\r
1722 #define IS_STA_VALID(pSta) (pSta && pSta->expire_to)
\r
1723 #elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)
\r
1724 #define IS_STA_VALID(pSta) (pSta && pSta->bUsed)
\r
1726 #define IS_STA_VALID(pSta) (pSta)
\r
1728 // 20100514 Joseph: Add definition for antenna switching test after link.
\r
1729 // This indicates two different the steps.
\r
1730 // In SWAW_STEP_PEAK, driver needs to switch antenna and listen to the signal on the air.
\r
1731 // In SWAW_STEP_DETERMINE, driver just compares the signal captured in SWAW_STEP_PEAK
\r
1732 // with original RSSI to determine if it is necessary to switch antenna.
\r
1733 #define SWAW_STEP_PEAK 0
\r
1734 #define SWAW_STEP_DETERMINE 1
\r
1736 //Remove DIG by yuchen
\r
1740 IN PDM_ODM_T pDM_Odm,
\r
1741 IN u1Byte Antenna);
\r
1744 //Remove BB power saving by Yuchen
\r
1746 #define SwAntDivRestAfterLink ODM_SwAntDivRestAfterLink
\r
1747 VOID ODM_SwAntDivRestAfterLink( IN PDM_ODM_T pDM_Odm);
\r
1749 #define dm_CheckTXPowerTracking ODM_TXPowerTrackingCheck
\r
1751 ODM_TXPowerTrackingCheck(
\r
1752 IN PDM_ODM_T pDM_Odm
\r
1755 //Remove ODM_RAStateCheck() by RS_James
\r
1757 #if(DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_AP|ODM_ADSL))
\r
1758 //============================================================
\r
1759 // function prototype
\r
1760 //============================================================
\r
1761 //#define DM_ChangeDynamicInitGainThresh ODM_ChangeDynamicInitGainThresh
\r
1762 //void ODM_ChangeDynamicInitGainThresh(IN PADAPTER pAdapter,
\r
1763 // IN INT32 DM_Type,
\r
1764 // IN INT32 DM_Value);
\r
1766 //Remove DIG by yuchen
\r
1770 ODM_CheckPowerStatus(
\r
1771 IN PADAPTER Adapter
\r
1775 //Remove ODM_RateAdaptiveStateApInit() by RS_James
\r
1777 //Remove Edca by Yuchen
\r
1779 #if(DM_ODM_SUPPORT_TYPE==ODM_AP)
\r
1780 #ifdef HW_ANT_SWITCH
\r
1782 ODM_Diversity_AntennaSelect(
\r
1783 IN PDM_ODM_T pDM_Odm,
\r
1789 #define SwAntDivResetBeforeLink ODM_SwAntDivResetBeforeLink
\r
1790 VOID ODM_SwAntDivResetBeforeLink(IN PDM_ODM_T pDM_Odm);
\r
1792 #define SwAntDivCheckBeforeLink ODM_SwAntDivCheckBeforeLink
\r
1795 ODM_SwAntDivCheckBeforeLink(
\r
1796 IN PDM_ODM_T pDM_Odm
\r
1802 #define dm_SWAW_RSSI_Check ODM_SwAntDivChkPerPktRssi
\r
1803 VOID ODM_SwAntDivChkPerPktRssi(
\r
1804 IN PDM_ODM_T pDM_Odm,
\r
1805 IN u1Byte StationID,
\r
1806 IN PODM_PHY_INFO_T pPhyInfo
\r
1809 #if((DM_ODM_SUPPORT_TYPE==ODM_WIN)||(DM_ODM_SUPPORT_TYPE==ODM_CE))
\r
1811 u4Byte ConvertTo_dB(u4Byte Value);
\r
1815 PDM_ODM_T pDM_Odm,
\r
1816 unsigned int point,
\r
1817 u1Byte initial_gain_psd);
\r
1821 //Remove ODM_Get_Rate_Bitmap() by RS_James
\r
1823 #if(DM_ODM_SUPPORT_TYPE & (ODM_WIN))
\r
1824 #define dm_PSDMonitorCallback odm_PSDMonitorCallback
\r
1825 VOID odm_PSDMonitorCallback(PRT_TIMER pTimer);
\r
1828 odm_PSDMonitorWorkItemCallback(
\r
1834 IN PDM_ODM_T pDM_Odm,
\r
1835 pu4Byte PSD_report,
\r
1836 u1Byte initial_gain_psd
\r
1840 IN PDM_ODM_T pDM_Odm
\r
1842 VOID odm_PSD_Monitor(PDM_ODM_T pDM_Odm);
\r
1843 VOID odm_PSDMonitorInit(PDM_ODM_T pDM_Odm);
\r
1846 ODM_PSDDbgControl(
\r
1847 IN PADAPTER Adapter,
\r
1852 #endif // DM_ODM_SUPPORT_TYPE
\r
1855 #if (BEAMFORMING_SUPPORT == 1)
\r
1857 Beamforming_GetEntryBeamCapByMacId(
\r
1858 IN PMGNT_INFO pMgntInfo,
\r
1864 odm_TXPowerTrackingInit(
\r
1865 IN PDM_ODM_T pDM_Odm
\r
1868 VOID ODM_DMInit( IN PDM_ODM_T pDM_Odm);
\r
1872 IN PDM_ODM_T pDM_Odm // For common use in the future
\r
1877 IN PDM_ODM_T pDM_Odm,
\r
1878 IN ODM_CMNINFO_E CmnInfo,
\r
1884 IN PDM_ODM_T pDM_Odm,
\r
1885 IN ODM_CMNINFO_E CmnInfo,
\r
1890 ODM_CmnInfoPtrArrayHook(
\r
1891 IN PDM_ODM_T pDM_Odm,
\r
1892 IN ODM_CMNINFO_E CmnInfo,
\r
1898 ODM_CmnInfoUpdate(
\r
1899 IN PDM_ODM_T pDM_Odm,
\r
1900 IN u4Byte CmnInfo,
\r
1905 ODM_InitAllTimers(
\r
1906 IN PDM_ODM_T pDM_Odm
\r
1910 ODM_CancelAllTimers(
\r
1911 IN PDM_ODM_T pDM_Odm
\r
1915 ODM_ReleaseAllTimers(
\r
1916 IN PDM_ODM_T pDM_Odm
\r
1920 ODM_ResetIQKResult(
\r
1921 IN PDM_ODM_T pDM_Odm
\r
1925 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
\r
1926 VOID ODM_InitAllWorkItems(IN PDM_ODM_T pDM_Odm );
\r
1927 VOID ODM_FreeAllWorkItems(IN PDM_ODM_T pDM_Odm );
\r
1930 //===========================================//
\r
1931 // Neil Chen----2011--06--15--
\r
1933 //3 Path Diversity
\r
1934 //===========================================================
\r
1937 #define RSSI_MODE 1
\r
1938 #define TRAFFIC_LOW 0
\r
1939 #define TRAFFIC_HIGH 1
\r
1941 //#define PATHDIV_ENABLE 1
\r
1942 //#define dm_PathDiv_RSSI_Check ODM_PathDivChkPerPktRssi
\r
1945 PlatformDivision64(
\r
1951 // 20100514 Joseph: Add definition for antenna switching test after link.
\r
1952 // This indicates two different the steps.
\r
1953 // In SWAW_STEP_PEAK, driver needs to switch antenna and listen to the signal on the air.
\r
1954 // In SWAW_STEP_DETERMINE, driver just compares the signal captured in SWAW_STEP_PEAK
\r
1955 // with original RSSI to determine if it is necessary to switch antenna.
\r
1956 #define SWAW_STEP_PEAK 0
\r
1957 #define SWAW_STEP_DETERMINE 1
\r
1959 //====================================================
\r
1961 //====================================================
\r
1963 //#define PathDivCheckBeforeLink8192C ODM_PathDiversityBeforeLink92C
\r
1965 #define DM_ChangeDynamicInitGainThresh ODM_ChangeDynamicInitGainThresh
\r
1966 //void ODM_ChangeDynamicInitGainThresh(IN PADAPTER pAdapter,
\r
1967 // IN INT32 DM_Type,
\r
1968 // IN INT32 DM_Value);
\r
1972 typedef enum tag_DIG_Connect_Definition
\r
1974 DIG_STA_DISCONNECT = 0,
\r
1975 DIG_STA_CONNECT = 1,
\r
1976 DIG_STA_BEFORE_CONNECT = 2,
\r
1977 DIG_MultiSTA_DISCONNECT = 3,
\r
1978 DIG_MultiSTA_CONNECT = 4,
\r
1980 }DM_DIG_CONNECT_E;
\r
1983 #define dm_SWAW_RSSI_Check ODM_SwAntDivChkPerPktRssi
\r
1986 // 2012/01/12 MH Check afapter status. Temp fix BSOD.
\r
1988 #define HAL_ADAPTER_STS_CHK(pDM_Odm)\
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1989 if (pDM_Odm->Adapter == NULL)\
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1996 // For new definition in MP temporarily fro power tracking,
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1998 #define odm_TXPowerTrackingDirectCall(_Adapter) \
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1999 IS_HARDWARE_TYPE_8192D(_Adapter) ? odm_TXPowerTrackingCallback_ThermalMeter_92D(_Adapter) : \
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2000 IS_HARDWARE_TYPE_8192C(_Adapter) ? odm_TXPowerTrackingCallback_ThermalMeter_92C(_Adapter) : \
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2001 IS_HARDWARE_TYPE_8723A(_Adapter) ? odm_TXPowerTrackingCallback_ThermalMeter_8723A(_Adapter) :\
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2002 ODM_TXPowerTrackingCallback_ThermalMeter(_Adapter)
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2005 ODM_SetTxAntByTxInfo_88C_92D(
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2006 IN PDM_ODM_T pDM_Odm,
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2011 #endif // #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
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2013 ODM_AntselStatistics_88C(
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2014 IN PDM_ODM_T pDM_Odm,
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2016 IN u4Byte PWDBAll,
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2017 IN BOOLEAN isCCKrate
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2020 #if( DM_ODM_SUPPORT_TYPE & (ODM_WIN |ODM_CE))
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2023 ODM_SingleDualAntennaDefaultSetting(
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2024 IN PDM_ODM_T pDM_Odm
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2028 ODM_SingleDualAntennaDetection(
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2029 IN PDM_ODM_T pDM_Odm,
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2033 #endif // #if((DM_ODM_SUPPORT_TYPE==ODM_WIN)||(DM_ODM_SUPPORT_TYPE==ODM_CE))
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2035 ODM_UpdateNoisyState(
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2036 IN PDM_ODM_T pDM_Odm,
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2037 IN BOOLEAN bNoisyStateFromC2H
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2041 Set_RA_DM_Ratrbitmap_by_Noisy(
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2042 IN PDM_ODM_T pDM_Odm,
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2043 IN WIRELESS_MODE WirelessMode,
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2044 IN u4Byte ratr_bitmap,
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2045 IN u1Byte rssi_level
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2049 ODM_UpdateInitRate(
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2050 IN PDM_ODM_T pDM_Odm,
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2054 //Remove ODM_DynamicARFBSelect() by RS_James
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2056 #if (DM_ODM_SUPPORT_TYPE == ODM_CE)
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2057 void odm_dtc(PDM_ODM_T pDM_Odm);
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2058 #endif /* #if (DM_ODM_SUPPORT_TYPE == ODM_CE) */
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