1 /******************************************************************************
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3 * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
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5 * This program is free software; you can redistribute it and/or modify it
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6 * under the terms of version 2 of the GNU General Public License as
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7 * published by the Free Software Foundation.
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9 * This program is distributed in the hope that it will be useful, but WITHOUT
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10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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14 * You should have received a copy of the GNU General Public License along with
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15 * this program; if not, write to the Free Software Foundation, Inc.,
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16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
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19 ******************************************************************************/
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21 //============================================================
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23 //============================================================
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25 #include "odm_precomp.h"
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27 #if (defined(CONFIG_HW_ANTENNA_DIVERSITY))
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29 odm_AntDiv_on_off( IN PDM_ODM_T pDM_Odm ,IN u1Byte swch)
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31 if(pDM_Odm->AntDivType==S0S1_SW_ANTDIV || pDM_Odm->AntDivType==CGCS_RX_SW_ANTDIV)
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34 if(pDM_Odm->SupportICType & ODM_N_ANTDIV_SUPPORT)
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36 ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("(( Turn %s )) N-Series AntDiv Function\n",(swch==ANTDIV_ON)?"ON" : "OFF"));
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37 ODM_SetBBReg(pDM_Odm, 0xc50 , BIT7, swch); //OFDM AntDiv function block enable
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38 ODM_SetBBReg(pDM_Odm, 0xa00 , BIT15, swch); //CCK AntDiv function block enable
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40 else if(pDM_Odm->SupportICType & ODM_AC_ANTDIV_SUPPORT)
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42 ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("(( Turn %s )) AC-Series AntDiv Function\n",(swch==ANTDIV_ON)?"ON" : "OFF"));
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43 if(pDM_Odm->SupportICType == ODM_RTL8812)
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45 ODM_SetBBReg(pDM_Odm, 0xc50 , BIT7, swch); //OFDM AntDiv function block enable
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46 ODM_SetBBReg(pDM_Odm, 0xa00 , BIT15, swch); //CCK AntDiv function block enable
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50 ODM_SetBBReg(pDM_Odm, 0x8D4 , BIT24, swch); //OFDM AntDiv function block enable
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51 ODM_SetBBReg(pDM_Odm, 0x800 , BIT25, swch); //CCK AntDiv function block enable
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57 ODM_UpdateRxIdleAnt(IN PDM_ODM_T pDM_Odm, IN u1Byte Ant)
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59 pFAT_T pDM_FatTable = &pDM_Odm->DM_FatTable;
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60 u4Byte DefaultAnt, OptionalAnt,value32;
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62 #if (DM_ODM_SUPPORT_TYPE & (ODM_CE|ODM_WIN))
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63 PADAPTER pAdapter = pDM_Odm->Adapter;
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64 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
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67 if(pDM_FatTable->RxIdleAnt != Ant)
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69 ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ Update Rx-Idle-Ant ] RxIdleAnt =%s\n",(Ant==MAIN_ANT)?"MAIN_ANT":"AUX_ANT"));
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70 pDM_FatTable->RxIdleAnt = Ant;
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74 DefaultAnt = ANT1_2G;
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75 OptionalAnt = ANT2_2G;
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79 DefaultAnt = ANT2_2G;
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80 OptionalAnt = ANT1_2G;
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83 if(pDM_Odm->SupportICType & ODM_N_ANTDIV_SUPPORT)
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85 if(pDM_Odm->SupportICType==ODM_RTL8192E)
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87 ODM_SetBBReg(pDM_Odm, 0xB38 , BIT5|BIT4|BIT3, DefaultAnt); //Default RX
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88 ODM_SetBBReg(pDM_Odm, 0xB38 , BIT8|BIT7|BIT6, OptionalAnt);//Optional RX
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92 ODM_SetBBReg(pDM_Odm, 0x864 , BIT5|BIT4|BIT3, DefaultAnt); //Default RX
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93 ODM_SetBBReg(pDM_Odm, 0x864 , BIT8|BIT7|BIT6, OptionalAnt); //Optional RX
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95 if(pDM_Odm->SupportICType == ODM_RTL8723B)
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97 value32 = ODM_GetBBReg(pDM_Odm, 0x948, 0xFFF);
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99 if (value32 !=0x280)
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100 ODM_SetBBReg(pDM_Odm, 0x948 , BIT9, DefaultAnt);
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102 rtw_hal_set_tx_power_level(pAdapter, pHalData->CurrentChannel);
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106 ODM_SetBBReg(pDM_Odm, 0x860, BIT14|BIT13|BIT12, DefaultAnt); //Default TX
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108 else if(pDM_Odm->SupportICType & ODM_AC_ANTDIV_SUPPORT)
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110 ODM_SetBBReg(pDM_Odm, 0xC08 , BIT21|BIT20|BIT19, DefaultAnt); //Default RX
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111 ODM_SetBBReg(pDM_Odm, 0xC08 , BIT24|BIT23|BIT22, OptionalAnt);//Optional RX
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112 ODM_SetBBReg(pDM_Odm, 0xC08 , BIT27|BIT26|BIT25, DefaultAnt); //Default TX
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114 ODM_SetMACReg(pDM_Odm, 0x6D8 , BIT10|BIT9|BIT8, DefaultAnt); //
\14PathA Resp Tx
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116 else// pDM_FatTable->RxIdleAnt == Ant
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118 ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ Stay in Ori-Ant ] RxIdleAnt =%s\n",(Ant==MAIN_ANT)?"MAIN_ANT":"AUX_ANT"));
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119 pDM_FatTable->RxIdleAnt = Ant;
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125 odm_UpdateTxAnt(IN PDM_ODM_T pDM_Odm, IN u1Byte Ant, IN u4Byte MacId)
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127 pFAT_T pDM_FatTable = &pDM_Odm->DM_FatTable;
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130 if(Ant == MAIN_ANT)
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135 pDM_FatTable->antsel_a[MacId] = TxAnt&BIT0;
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136 pDM_FatTable->antsel_b[MacId] = (TxAnt&BIT1)>>1;
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137 pDM_FatTable->antsel_c[MacId] = (TxAnt&BIT2)>>2;
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138 #if (DM_ODM_SUPPORT_TYPE == ODM_AP)
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139 if (pDM_Odm->antdiv_rssi)
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141 //panic_printk("[Tx from TxInfo]: MacID:(( %d )), TxAnt = (( %s ))\n",MacId,(Ant==MAIN_ANT)?"MAIN_ANT":"AUX_ANT");
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142 //panic_printk("antsel_tr_mux=(( 3'b%d%d%d ))\n", pDM_FatTable->antsel_c[MacId] , pDM_FatTable->antsel_b[MacId] , pDM_FatTable->antsel_a[MacId] );
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145 //ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[Tx from TxInfo]: MacID:(( %d )), TxAnt = (( %s ))\n",
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146 // MacId,(Ant==MAIN_ANT)?"MAIN_ANT":"AUX_ANT"));
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147 //ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD,("antsel_tr_mux=(( 3'b%d%d%d ))\n",
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148 //pDM_FatTable->antsel_c[MacId] , pDM_FatTable->antsel_b[MacId] , pDM_FatTable->antsel_a[MacId] ));
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154 #if (RTL8188E_SUPPORT == 1)
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158 odm_RX_HWAntDiv_Init_88E(
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159 IN PDM_ODM_T pDM_Odm
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164 pDM_Odm->AntType = ODM_AUTO_ANT;
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166 #if (MP_DRIVER == 1)
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167 pDM_Odm->AntDivType = CGCS_RX_SW_ANTDIV;
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168 ODM_SetBBReg(pDM_Odm, ODM_REG_IGI_A_11N , BIT7, 0); // disable HW AntDiv
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169 ODM_SetBBReg(pDM_Odm, ODM_REG_LNA_SWITCH_11N , BIT31, 1); // 1:CG, 0:CS
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173 ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("***8188E AntDiv_Init => AntDivType=[CGCS_RX_HW_ANTDIV]\n"));
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176 value32 = ODM_GetMACReg(pDM_Odm, ODM_REG_ANTSEL_PIN_11N, bMaskDWord);
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177 ODM_SetMACReg(pDM_Odm, ODM_REG_ANTSEL_PIN_11N, bMaskDWord, value32|(BIT23|BIT25)); //Reg4C[25]=1, Reg4C[23]=1 for pin output
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179 ODM_SetBBReg(pDM_Odm, ODM_REG_PIN_CTRL_11N , BIT9|BIT8, 0);//Reg870[8]=1'b0, Reg870[9]=1'b0 //antsel antselb by HW
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180 ODM_SetBBReg(pDM_Odm, ODM_REG_RX_ANT_CTRL_11N , BIT10, 0); //Reg864[10]=1'b0 //antsel2 by HW
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181 ODM_SetBBReg(pDM_Odm, ODM_REG_LNA_SWITCH_11N , BIT22, 1); //Regb2c[22]=1'b0 //disable CS/CG switch
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182 ODM_SetBBReg(pDM_Odm, ODM_REG_LNA_SWITCH_11N , BIT31, 1); //Regb2c[31]=1'b1 //output at CG only
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184 ODM_SetBBReg(pDM_Odm, ODM_REG_ANTDIV_PARA1_11N , bMaskDWord, 0x000000a0);
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186 ODM_SetBBReg(pDM_Odm, ODM_REG_BB_PWR_SAV4_11N , BIT7, 1); //Fix CCK PHY status report issue
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187 ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_ANTDIV_PARA2_11N , BIT4, 1); //CCK complete HW AntDiv within 64 samples
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189 ODM_SetBBReg(pDM_Odm, ODM_REG_ANT_MAPPING1_11N , 0xFFFF, 0x0102); //antenna mapping table
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195 odm_TRX_HWAntDiv_Init_88E(
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196 IN PDM_ODM_T pDM_Odm
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201 #if (MP_DRIVER == 1)
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202 pDM_Odm->AntDivType = CGCS_RX_SW_ANTDIV;
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203 ODM_SetBBReg(pDM_Odm, ODM_REG_IGI_A_11N , BIT7, 0); // disable HW AntDiv
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204 ODM_SetBBReg(pDM_Odm, ODM_REG_RX_ANT_CTRL_11N , BIT5|BIT4|BIT3, 0); //Default RX (0/1)
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208 ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("***8188E AntDiv_Init => AntDivType=[CG_TRX_HW_ANTDIV (SPDT)]\n"));
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211 value32 = ODM_GetMACReg(pDM_Odm, ODM_REG_ANTSEL_PIN_11N, bMaskDWord);
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212 ODM_SetMACReg(pDM_Odm, ODM_REG_ANTSEL_PIN_11N, bMaskDWord, value32|(BIT23|BIT25)); //Reg4C[25]=1, Reg4C[23]=1 for pin output
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214 ODM_SetBBReg(pDM_Odm, ODM_REG_PIN_CTRL_11N , BIT9|BIT8, 0);//Reg870[8]=1'b0, Reg870[9]=1'b0 //antsel antselb by HW
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215 ODM_SetBBReg(pDM_Odm, ODM_REG_RX_ANT_CTRL_11N , BIT10, 0); //Reg864[10]=1'b0 //antsel2 by HW
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216 ODM_SetBBReg(pDM_Odm, ODM_REG_LNA_SWITCH_11N , BIT22, 0); //Regb2c[22]=1'b0 //disable CS/CG switch
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217 ODM_SetBBReg(pDM_Odm, ODM_REG_LNA_SWITCH_11N , BIT31, 1); //Regb2c[31]=1'b1 //output at CG only
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219 ODM_SetBBReg(pDM_Odm, ODM_REG_ANTDIV_PARA1_11N , bMaskDWord, 0x000000a0);
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221 ODM_SetBBReg(pDM_Odm, ODM_REG_BB_PWR_SAV4_11N , BIT7, 1); //Fix CCK PHY status report issue
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222 ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_ANTDIV_PARA2_11N , BIT4, 1); //CCK complete HW AntDiv within 64 samples
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224 //antenna mapping table
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225 if(!pDM_Odm->bIsMPChip) //testchip
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227 ODM_SetBBReg(pDM_Odm, ODM_REG_RX_DEFUALT_A_11N , BIT10|BIT9|BIT8, 1); //Reg858[10:8]=3'b001
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228 ODM_SetBBReg(pDM_Odm, ODM_REG_RX_DEFUALT_A_11N , BIT13|BIT12|BIT11, 2); //Reg858[13:11]=3'b010
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231 ODM_SetBBReg(pDM_Odm, ODM_REG_ANT_MAPPING1_11N , bMaskDWord, 0x0201); //Reg914=3'b010, Reg915=3'b001
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236 odm_Smart_HWAntDiv_Init_88E(
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237 IN PDM_ODM_T pDM_Odm
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241 pFAT_T pDM_FatTable = &pDM_Odm->DM_FatTable;
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242 u4Byte AntCombination = 2;
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244 ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("***8188E AntDiv_Init => AntDivType=[CG_TRX_SMART_ANTDIV]\n"));
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246 #if (MP_DRIVER == 1)
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247 ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("pDM_Odm->AntDivType: %d\n", pDM_Odm->AntDivType));
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253 pDM_FatTable->Bssid[i] = 0;
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254 pDM_FatTable->antSumRSSI[i] = 0;
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255 pDM_FatTable->antRSSIcnt[i] = 0;
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256 pDM_FatTable->antAveRSSI[i] = 0;
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258 pDM_FatTable->TrainIdx = 0;
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259 pDM_FatTable->FAT_State = FAT_NORMAL_STATE;
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262 value32 = ODM_GetMACReg(pDM_Odm, 0x4c, bMaskDWord);
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263 ODM_SetMACReg(pDM_Odm, 0x4c, bMaskDWord, value32|(BIT23|BIT25)); //Reg4C[25]=1, Reg4C[23]=1 for pin output
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264 value32 = ODM_GetMACReg(pDM_Odm, 0x7B4, bMaskDWord);
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265 ODM_SetMACReg(pDM_Odm, 0x7b4, bMaskDWord, value32|(BIT16|BIT17)); //Reg7B4[16]=1 enable antenna training, Reg7B4[17]=1 enable A2 match
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266 //value32 = PlatformEFIORead4Byte(Adapter, 0x7B4);
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267 //PlatformEFIOWrite4Byte(Adapter, 0x7b4, value32|BIT18); //append MACID in reponse packet
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270 ODM_SetMACReg(pDM_Odm, 0x7b4, 0xFFFF, 0);
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271 ODM_SetMACReg(pDM_Odm, 0x7b0, bMaskDWord, 0);
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273 ODM_SetBBReg(pDM_Odm, 0x870 , BIT9|BIT8, 0);//Reg870[8]=1'b0, Reg870[9]=1'b0 //antsel antselb by HW
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274 ODM_SetBBReg(pDM_Odm, 0x864 , BIT10, 0); //Reg864[10]=1'b0 //antsel2 by HW
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275 ODM_SetBBReg(pDM_Odm, 0xb2c , BIT22, 0); //Regb2c[22]=1'b0 //disable CS/CG switch
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276 ODM_SetBBReg(pDM_Odm, 0xb2c , BIT31, 1); //Regb2c[31]=1'b1 //output at CG only
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277 ODM_SetBBReg(pDM_Odm, 0xca4 , bMaskDWord, 0x000000a0);
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279 //antenna mapping table
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280 if(AntCombination == 2)
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282 if(!pDM_Odm->bIsMPChip) //testchip
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284 ODM_SetBBReg(pDM_Odm, 0x858 , BIT10|BIT9|BIT8, 1); //Reg858[10:8]=3'b001
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285 ODM_SetBBReg(pDM_Odm, 0x858 , BIT13|BIT12|BIT11, 2); //Reg858[13:11]=3'b010
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289 ODM_SetBBReg(pDM_Odm, 0x914 , bMaskByte0, 1);
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290 ODM_SetBBReg(pDM_Odm, 0x914 , bMaskByte1, 2);
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293 else if(AntCombination == 7)
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295 if(!pDM_Odm->bIsMPChip) //testchip
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297 ODM_SetBBReg(pDM_Odm, 0x858 , BIT10|BIT9|BIT8, 0); //Reg858[10:8]=3'b000
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298 ODM_SetBBReg(pDM_Odm, 0x858 , BIT13|BIT12|BIT11, 1); //Reg858[13:11]=3'b001
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299 ODM_SetBBReg(pDM_Odm, 0x878 , BIT16, 0);
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300 ODM_SetBBReg(pDM_Odm, 0x858 , BIT15|BIT14, 2); //(Reg878[0],Reg858[14:15])=3'b010
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301 ODM_SetBBReg(pDM_Odm, 0x878 , BIT19|BIT18|BIT17, 3);//Reg878[3:1]=3b'011
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302 ODM_SetBBReg(pDM_Odm, 0x878 , BIT22|BIT21|BIT20, 4);//Reg878[6:4]=3b'100
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303 ODM_SetBBReg(pDM_Odm, 0x878 , BIT25|BIT24|BIT23, 5);//Reg878[9:7]=3b'101
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304 ODM_SetBBReg(pDM_Odm, 0x878 , BIT28|BIT27|BIT26, 6);//Reg878[12:10]=3b'110
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305 ODM_SetBBReg(pDM_Odm, 0x878 , BIT31|BIT30|BIT29, 7);//Reg878[15:13]=3b'111
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309 ODM_SetBBReg(pDM_Odm, 0x914 , bMaskByte0, 0);
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310 ODM_SetBBReg(pDM_Odm, 0x914 , bMaskByte1, 1);
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311 ODM_SetBBReg(pDM_Odm, 0x914 , bMaskByte2, 2);
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312 ODM_SetBBReg(pDM_Odm, 0x914 , bMaskByte3, 3);
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313 ODM_SetBBReg(pDM_Odm, 0x918 , bMaskByte0, 4);
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314 ODM_SetBBReg(pDM_Odm, 0x918 , bMaskByte1, 5);
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315 ODM_SetBBReg(pDM_Odm, 0x918 , bMaskByte2, 6);
\r
316 ODM_SetBBReg(pDM_Odm, 0x918 , bMaskByte3, 7);
\r
320 //Default Ant Setting when no fast training
\r
321 ODM_SetBBReg(pDM_Odm, 0x80c , BIT21, 1); //Reg80c[21]=1'b1 //from TX Info
\r
322 ODM_SetBBReg(pDM_Odm, 0x864 , BIT5|BIT4|BIT3, 0); //Default RX
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323 ODM_SetBBReg(pDM_Odm, 0x864 , BIT8|BIT7|BIT6, 1); //Optional RX
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324 //ODM_SetBBReg(pDM_Odm, 0x860 , BIT14|BIT13|BIT12, 1); //Default TX
\r
326 //Enter Traing state
\r
327 ODM_SetBBReg(pDM_Odm, 0x864 , BIT2|BIT1|BIT0, (AntCombination-1)); //Reg864[2:0]=3'd6 //ant combination=reg864[2:0]+1
\r
328 //ODM_SetBBReg(pDM_Odm, 0xc50 , BIT7, 0); //RegC50[7]=1'b0 //disable HW AntDiv
\r
329 //ODM_SetBBReg(pDM_Odm, 0xe08 , BIT16, 0); //RegE08[16]=1'b0 //disable fast training
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330 //ODM_SetBBReg(pDM_Odm, 0xe08 , BIT16, 1); //RegE08[16]=1'b1 //enable fast training
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331 ODM_SetBBReg(pDM_Odm, 0xc50 , BIT7, 1); //RegC50[7]=1'b1 //enable HW AntDiv
\r
334 //PHY_SetBBReg(Adapter, 0x864 , BIT10, 1);
\r
335 //PHY_SetBBReg(Adapter, 0x870 , BIT9, 1);
\r
336 //PHY_SetBBReg(Adapter, 0x870 , BIT8, 1);
\r
337 //PHY_SetBBReg(Adapter, 0x864 , BIT11, 1);
\r
338 //PHY_SetBBReg(Adapter, 0x860 , BIT9, 0);
\r
339 //PHY_SetBBReg(Adapter, 0x860 , BIT8, 0);
\r
343 #endif //#if (RTL8188E_SUPPORT == 1)
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346 #if (RTL8192E_SUPPORT == 1)
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348 odm_RX_HWAntDiv_Init_92E(
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349 IN PDM_ODM_T pDM_Odm
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353 #if (MP_DRIVER == 1)
\r
354 //pDM_Odm->AntDivType = CGCS_RX_SW_ANTDIV;
\r
355 odm_AntDiv_on_off(pDM_Odm, ANTDIV_OFF);
\r
356 ODM_SetBBReg(pDM_Odm, 0xc50 , BIT8, 0); //r_rxdiv_enable_anta Regc50[8]=1'b0 0: control by c50[9]
\r
357 ODM_SetBBReg(pDM_Odm, 0xc50 , BIT9, 1); // 1:CG, 0:CS
\r
361 ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("***8192E AntDiv_Init => AntDivType=[CGCS_RX_HW_ANTDIV]\n"));
\r
364 ODM_SetBBReg(pDM_Odm, 0x870 , BIT8, 0);//Reg870[8]=1'b0, // "antsel" is controled by HWs
\r
365 ODM_SetBBReg(pDM_Odm, 0xc50 , BIT8, 1); //Regc50[8]=1'b1 //" CS/CG switching" is controled by HWs
\r
368 ODM_SetBBReg(pDM_Odm, 0x914 , 0xFFFF, 0x0100); //antenna mapping table
\r
371 ODM_SetBBReg(pDM_Odm, 0xca4 , 0x7FF, 0xA0); //thershold
\r
372 ODM_SetBBReg(pDM_Odm, 0xca4 , 0x7FF000, 0x0); //bias
\r
375 ODM_SetBBReg(pDM_Odm, 0xa04 , 0xF000000, 0); //Select which path to receive for CCK_1 & CCK_2
\r
376 ODM_SetBBReg(pDM_Odm, 0xb34 , BIT30, 1); //(92E) ANTSEL_CCK_opt = r_en_antsel_cck? ANTSEL_CCK: 1'b0
\r
377 ODM_SetBBReg(pDM_Odm, 0xa74 , BIT7, 1); //Fix CCK PHY status report issue
\r
378 ODM_SetBBReg(pDM_Odm, 0xa0c , BIT4, 1); //CCK complete HW AntDiv within 64 samples
\r
382 odm_TRX_HWAntDiv_Init_92E(
\r
383 IN PDM_ODM_T pDM_Odm
\r
387 #if (MP_DRIVER == 1)
\r
388 //pDM_Odm->AntDivType = CGCS_RX_SW_ANTDIV;
\r
389 odm_AntDiv_on_off(pDM_Odm, ANTDIV_OFF);
\r
390 ODM_SetBBReg(pDM_Odm, 0xc50 , BIT8, 0); //r_rxdiv_enable_anta Regc50[8]=1'b0 0: control by c50[9]
\r
391 ODM_SetBBReg(pDM_Odm, 0xc50 , BIT9, 1); // 1:CG, 0:CS
\r
395 #if (DM_ODM_SUPPORT_TYPE & ODM_AP)
\r
396 pDM_Odm->antdiv_rssi=0;
\r
399 ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("***8192E AntDiv_Init => AntDivType=[CG_TRX_HW_ANTDIV]\n"));
\r
401 //3 --RFE pin setting---------
\r
403 ODM_SetMACReg(pDM_Odm, 0x38, BIT11, 1); //DBG PAD Driving control (GPIO 8)
\r
404 ODM_SetMACReg(pDM_Odm, 0x4c, BIT23, 0); //path-A , RFE_CTRL_3 & RFE_CTRL_4
\r
406 ODM_SetBBReg(pDM_Odm, 0x944 , BIT4|BIT3, 0x3); //RFE_buffer
\r
407 ODM_SetBBReg(pDM_Odm, 0x940 , BIT7|BIT6, 0x0); // r_rfe_path_sel_ (RFE_CTRL_3)
\r
408 ODM_SetBBReg(pDM_Odm, 0x940 , BIT9|BIT8, 0x0); // r_rfe_path_sel_ (RFE_CTRL_4)
\r
409 ODM_SetBBReg(pDM_Odm, 0x944 , BIT31, 0); //RFE_buffer
\r
410 ODM_SetBBReg(pDM_Odm, 0x92C , BIT3, 0); //rfe_inv (RFE_CTRL_3)
\r
411 ODM_SetBBReg(pDM_Odm, 0x92C , BIT4, 1); //rfe_inv (RFE_CTRL_4)
\r
412 ODM_SetBBReg(pDM_Odm, 0x930 , 0xFF000, 0x88); //path-A , RFE_CTRL_3 & 4=> ANTSEL[0]
\r
413 //3 -------------------------
\r
416 ODM_SetBBReg(pDM_Odm, 0xC50 , BIT8, 0); //path-A //disable CS/CG switch
\r
417 ODM_SetBBReg(pDM_Odm, 0xC50 , BIT9, 1); //path-A //output at CG only
\r
418 ODM_SetBBReg(pDM_Odm, 0x870 , BIT9|BIT8, 0); //path-A //antsel antselb by HW
\r
419 ODM_SetBBReg(pDM_Odm, 0xB38 , BIT10, 0); //path-A //antsel2 by HW
\r
422 ODM_SetBBReg(pDM_Odm, 0x914 , 0xFFFF, 0x0100); //antenna mapping table
\r
425 ODM_SetBBReg(pDM_Odm, 0xca4 , 0x7FF, 0xA0); //thershold
\r
426 ODM_SetBBReg(pDM_Odm, 0xca4 , 0x7FF000, 0x0); //bias
\r
429 ODM_SetBBReg(pDM_Odm, 0xa04 , 0xF000000, 0); //Select which path to receive for CCK_1 & CCK_2
\r
430 ODM_SetBBReg(pDM_Odm, 0xb34 , BIT30, 1); //(92E) ANTSEL_CCK_opt = r_en_antsel_cck? ANTSEL_CCK: 1'b0
\r
431 ODM_SetBBReg(pDM_Odm, 0xa74 , BIT7, 1); //Fix CCK PHY status report issue
\r
432 ODM_SetBBReg(pDM_Odm, 0xa0c , BIT4, 1); //CCK complete HW AntDiv within 64 samples
\r
435 ODM_SetBBReg(pDM_Odm, 0xE20 , BIT23|BIT22|BIT21|BIT20, 8); //keep antidx after tx for ACK ( unit x 32 mu sec)
\r
439 odm_Smart_HWAntDiv_Init_92E(
\r
440 IN PDM_ODM_T pDM_Odm
\r
443 ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("***8188E AntDiv_Init => AntDivType=[CG_TRX_SMART_ANTDIV]\n"));
\r
445 #endif //#if (RTL8192E_SUPPORT == 1)
\r
448 #if (RTL8723B_SUPPORT == 1)
\r
450 odm_TRX_HWAntDiv_Init_8723B(
\r
451 IN PDM_ODM_T pDM_Odm
\r
454 ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("***8723B AntDiv_Init => AntDivType=[CG_TRX_HW_ANTDIV(DPDT)]\n"));
\r
457 ODM_SetBBReg(pDM_Odm, 0x914 , bMaskByte0, 0);
\r
458 ODM_SetBBReg(pDM_Odm, 0x914 , bMaskByte1, 1);
\r
460 //OFDM HW AntDiv Parameters
\r
461 ODM_SetBBReg(pDM_Odm, 0xCA4 , 0x7FF, 0xa0); //thershold
\r
462 ODM_SetBBReg(pDM_Odm, 0xCA4 , 0x7FF000, 0x00); //bias
\r
464 //CCK HW AntDiv Parameters
\r
465 ODM_SetBBReg(pDM_Odm, 0xA74 , BIT7, 1); //patch for clk from 88M to 80M
\r
466 ODM_SetBBReg(pDM_Odm, 0xA0C , BIT4, 1); //do 64 samples
\r
469 ODM_SetBBReg(pDM_Odm, 0x864, BIT12, 0); //keep antsel_map when GNT_BT = 1
\r
470 ODM_SetBBReg(pDM_Odm, 0x874 , BIT23, 0); //Disable hw antsw & fast_train.antsw when GNT_BT=1
\r
472 //Output Pin Settings
\r
473 ODM_SetBBReg(pDM_Odm, 0x870 , BIT8, 0); //
\r
475 ODM_SetBBReg(pDM_Odm, 0x948 , BIT6, 0); //WL_BB_SEL_BTG_TRXG_anta, (1: HW CTRL 0: SW CTRL)
\r
476 ODM_SetBBReg(pDM_Odm, 0x948 , BIT7, 0);
\r
478 ODM_SetMACReg(pDM_Odm, 0x40 , BIT3, 1);
\r
479 ODM_SetMACReg(pDM_Odm, 0x38 , BIT11, 1);
\r
480 ODM_SetMACReg(pDM_Odm, 0x4C , BIT24|BIT23, 2); //select DPDT_P and DPDT_N as output pin
\r
482 ODM_SetBBReg(pDM_Odm, 0x944 , BIT0|BIT1, 3); //in/out
\r
483 ODM_SetBBReg(pDM_Odm, 0x944 , BIT31, 0); //
\r
485 ODM_SetBBReg(pDM_Odm, 0x92C , BIT1, 0); //DPDT_P non-inverse
\r
486 ODM_SetBBReg(pDM_Odm, 0x92C , BIT0, 1); //DPDT_N inverse
\r
488 ODM_SetBBReg(pDM_Odm, 0x930 , 0xF0, 8); // DPDT_P = ANTSEL[0]
\r
489 ODM_SetBBReg(pDM_Odm, 0x930 , 0xF, 8); // DPDT_N = ANTSEL[0]
\r
492 ODM_SetBBReg(pDM_Odm, 0xE20 , BIT23|BIT22|BIT21|BIT20, 8); //keep antidx after tx for ACK ( unit x 32 mu sec)
\r
494 //2 [--For HW Bug Setting]
\r
495 if(pDM_Odm->AntType == ODM_AUTO_ANT)
\r
496 ODM_SetBBReg(pDM_Odm, 0xA00 , BIT15, 0); //CCK AntDiv function block enable
\r
498 //ODM_SetBBReg(pDM_Odm, 0x80C , BIT21, 0); //TX Ant by Reg
\r
506 odm_S0S1_SWAntDiv_Init_8723B(
\r
507 IN PDM_ODM_T pDM_Odm
\r
510 pSWAT_T pDM_SWAT_Table = &pDM_Odm->DM_SWAT_Table;
\r
511 pFAT_T pDM_FatTable = &pDM_Odm->DM_FatTable;
\r
513 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("***8723B AntDiv_Init => AntDivType=[ S0S1_SW_AntDiv] \n"));
\r
516 ODM_SetBBReg(pDM_Odm, 0x914 , bMaskByte0, 0);
\r
517 ODM_SetBBReg(pDM_Odm, 0x914 , bMaskByte1, 1);
\r
519 //Output Pin Settings
\r
520 //ODM_SetBBReg(pDM_Odm, 0x948 , BIT6, 0x1);
\r
521 ODM_SetBBReg(pDM_Odm, 0x870 , BIT9|BIT8, 0);
\r
523 pDM_FatTable->bBecomeLinked =FALSE;
\r
524 pDM_SWAT_Table->try_flag = 0xff;
\r
525 pDM_SWAT_Table->Double_chk_flag = 0;
\r
526 pDM_SWAT_Table->TrafficLoad = TRAFFIC_LOW;
\r
529 ODM_SetBBReg(pDM_Odm, 0xE20 , BIT23|BIT22|BIT21|BIT20, 8); //keep antidx after tx for ACK ( unit x 32 mu sec)
\r
531 //2 [--For HW Bug Setting]
\r
532 ODM_SetBBReg(pDM_Odm, 0x80C , BIT21, 0); //TX Ant by Reg
\r
535 #endif //#if (RTL8723B_SUPPORT == 1)
\r
538 #if (RTL8821A_SUPPORT == 1)
\r
540 odm_TRX_HWAntDiv_Init_8821A(
\r
541 IN PDM_ODM_T pDM_Odm
\r
545 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
\r
547 PADAPTER pAdapter = pDM_Odm->Adapter;
\r
548 pAdapter->HalFunc.GetHalDefVarHandler(pAdapter, HAL_DEF_5G_ANT_SELECT, (pu1Byte)(&pDM_Odm->AntType));
\r
550 pDM_Odm->AntType = ODM_AUTO_ANT;
\r
552 pAdapter->HalFunc.GetHalDefVarHandler(pAdapter, HAL_DEF_5G_ANT_SELECT, (pu1Byte)(&pDM_Odm->AntType));
\r
554 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("***8821A AntDiv_Init => AntDivType=[ CG_TRX_HW_ANTDIV (DPDT)] \n"));
\r
556 //Output Pin Settings
\r
557 ODM_SetMACReg(pDM_Odm, 0x4C , BIT25, 0);
\r
559 ODM_SetMACReg(pDM_Odm, 0x64 , BIT29, 1); //PAPE by WLAN control
\r
560 ODM_SetMACReg(pDM_Odm, 0x64 , BIT28, 1); //LNAON by WLAN control
\r
562 ODM_SetBBReg(pDM_Odm, 0xCB0 , bMaskDWord, 0x77775745);
\r
563 ODM_SetBBReg(pDM_Odm, 0xCB8 , BIT16, 0);
\r
565 ODM_SetMACReg(pDM_Odm, 0x4C , BIT23, 0); //select DPDT_P and DPDT_N as output pin
\r
566 ODM_SetMACReg(pDM_Odm, 0x4C , BIT24, 1); //by WLAN control
\r
567 ODM_SetBBReg(pDM_Odm, 0xCB4 , 0xF, 8); // DPDT_P = ANTSEL[0]
\r
568 ODM_SetBBReg(pDM_Odm, 0xCB4 , 0xF0, 8); // DPDT_N = ANTSEL[0]
\r
569 ODM_SetBBReg(pDM_Odm, 0xCB4 , BIT29, 0); //DPDT_P non-inverse
\r
570 ODM_SetBBReg(pDM_Odm, 0xCB4 , BIT28, 1); //DPDT_N inverse
\r
573 ODM_SetBBReg(pDM_Odm, 0xCA4 , bMaskByte0, 0);
\r
574 ODM_SetBBReg(pDM_Odm, 0xCA4 , bMaskByte1, 1);
\r
576 //Set ANT1_8821A as MAIN_ANT
\r
577 if((pDM_Odm->AntType == ODM_FIX_MAIN_ANT) || (pDM_Odm->AntType == ODM_AUTO_ANT))
\r
578 ODM_UpdateRxIdleAnt(pDM_Odm, MAIN_ANT);
\r
580 ODM_UpdateRxIdleAnt(pDM_Odm, AUX_ANT);
\r
582 //OFDM HW AntDiv Parameters
\r
583 ODM_SetBBReg(pDM_Odm, 0x8D4 , 0x7FF, 0xA0); //thershold
\r
584 ODM_SetBBReg(pDM_Odm, 0x8D4 , 0x7FF000, 0x10); //bias
\r
586 //CCK HW AntDiv Parameters
\r
587 ODM_SetBBReg(pDM_Odm, 0xA74 , BIT7, 1); //patch for clk from 88M to 80M
\r
588 ODM_SetBBReg(pDM_Odm, 0xA0C , BIT4, 1); //do 64 samples
\r
590 ODM_SetBBReg(pDM_Odm, 0x800 , BIT25, 0); //CCK AntDiv function block enable
\r
593 ODM_SetBBReg(pDM_Odm, 0xCAC , BIT9, 1); //keep antsel_map when GNT_BT = 1
\r
594 ODM_SetBBReg(pDM_Odm, 0x804 , BIT4, 1); //Disable hw antsw & fast_train.antsw when GNT_BT=1
\r
597 ODM_SetBBReg(pDM_Odm, 0x818 , BIT23|BIT22|BIT21|BIT20, 8); //keep antidx after tx for ACK ( unit x 32 mu sec)
\r
598 ODM_SetBBReg(pDM_Odm, 0x8CC , BIT20|BIT19|BIT18, 3); //settling time of antdiv by RF LNA = 100ns
\r
600 //response TX ant by RX ant
\r
601 ODM_SetMACReg(pDM_Odm, 0x668 , BIT3, 1);
\r
603 //2 [--For HW Bug Setting]
\r
604 if(pDM_Odm->AntType == ODM_AUTO_ANT)
\r
605 ODM_SetBBReg(pDM_Odm, 0x800 , BIT25, 0); //CCK AntDiv function block enable
\r
610 odm_S0S1_SWAntDiv_Init_8821A(
\r
611 IN PDM_ODM_T pDM_Odm
\r
614 pSWAT_T pDM_SWAT_Table = &pDM_Odm->DM_SWAT_Table;
\r
615 pFAT_T pDM_FatTable = &pDM_Odm->DM_FatTable;
\r
619 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
\r
621 PADAPTER pAdapter = pDM_Odm->Adapter;
\r
622 pAdapter->HalFunc.GetHalDefVarHandler(pAdapter, HAL_DEF_5G_ANT_SELECT, (pu1Byte)(&pDM_Odm->AntType));
\r
624 pDM_Odm->AntType = ODM_AUTO_ANT;
\r
627 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("***8821A AntDiv_Init => AntDivType=[ S0S1_SW_AntDiv] \n"));
\r
629 //Output Pin Settings
\r
630 ODM_SetMACReg(pDM_Odm, 0x4C , BIT25, 0);
\r
632 ODM_SetMACReg(pDM_Odm, 0x64 , BIT29, 1); //PAPE by WLAN control
\r
633 ODM_SetMACReg(pDM_Odm, 0x64 , BIT28, 1); //LNAON by WLAN control
\r
635 ODM_SetBBReg(pDM_Odm, 0xCB0 , bMaskDWord, 0x77775745);
\r
636 ODM_SetBBReg(pDM_Odm, 0xCB8 , BIT16, 0);
\r
638 ODM_SetMACReg(pDM_Odm, 0x4C , BIT23, 0); //select DPDT_P and DPDT_N as output pin
\r
639 ODM_SetMACReg(pDM_Odm, 0x4C , BIT24, 1); //by WLAN control
\r
640 ODM_SetBBReg(pDM_Odm, 0xCB4 , 0xF, 8); // DPDT_P = ANTSEL[0]
\r
641 ODM_SetBBReg(pDM_Odm, 0xCB4 , 0xF0, 8); // DPDT_N = ANTSEL[0]
\r
642 ODM_SetBBReg(pDM_Odm, 0xCB4 , BIT29, 0); //DPDT_P non-inverse
\r
643 ODM_SetBBReg(pDM_Odm, 0xCB4 , BIT28, 1); //DPDT_N inverse
\r
646 ODM_SetBBReg(pDM_Odm, 0xCA4 , bMaskByte0, 0);
\r
647 ODM_SetBBReg(pDM_Odm, 0xCA4 , bMaskByte1, 1);
\r
649 //Set ANT1_8821A as MAIN_ANT
\r
650 if((pDM_Odm->AntType == ODM_FIX_MAIN_ANT) || (pDM_Odm->AntType == ODM_AUTO_ANT))
\r
651 ODM_UpdateRxIdleAnt(pDM_Odm, MAIN_ANT);
\r
653 ODM_UpdateRxIdleAnt(pDM_Odm, AUX_ANT);
\r
655 //OFDM HW AntDiv Parameters
\r
656 ODM_SetBBReg(pDM_Odm, 0x8D4 , 0x7FF, 0xA0); //thershold
\r
657 ODM_SetBBReg(pDM_Odm, 0x8D4 , 0x7FF000, 0x10); //bias
\r
659 //CCK HW AntDiv Parameters
\r
660 ODM_SetBBReg(pDM_Odm, 0xA74 , BIT7, 1); //patch for clk from 88M to 80M
\r
661 ODM_SetBBReg(pDM_Odm, 0xA0C , BIT4, 1); //do 64 samples
\r
663 ODM_SetBBReg(pDM_Odm, 0x800 , BIT25, 0); //CCK AntDiv function block enable
\r
666 ODM_SetBBReg(pDM_Odm, 0xCAC , BIT9, 1); //keep antsel_map when GNT_BT = 1
\r
667 ODM_SetBBReg(pDM_Odm, 0x804 , BIT4, 1); //Disable hw antsw & fast_train.antsw when GNT_BT=1
\r
670 ODM_SetBBReg(pDM_Odm, 0x818 , BIT23|BIT22|BIT21|BIT20, 8); //keep antidx after tx for ACK ( unit x 32 mu sec)
\r
671 ODM_SetBBReg(pDM_Odm, 0x8CC , BIT20|BIT19|BIT18, 3); //settling time of antdiv by RF LNA = 100ns
\r
673 //response TX ant by RX ant
\r
674 ODM_SetMACReg(pDM_Odm, 0x668 , BIT3, 1);
\r
676 //2 [--For HW Bug Setting]
\r
677 if(pDM_Odm->AntType == ODM_AUTO_ANT)
\r
678 ODM_SetBBReg(pDM_Odm, 0x800 , BIT25, 0); //CCK AntDiv function block enable
\r
681 ODM_SetBBReg(pDM_Odm, 0x900 , BIT18, 0);
\r
683 pDM_SWAT_Table->try_flag = 0xff;
\r
684 pDM_SWAT_Table->Double_chk_flag = 0;
\r
685 pDM_SWAT_Table->TrafficLoad = TRAFFIC_LOW;
\r
686 pDM_SWAT_Table->CurAntenna = MAIN_ANT;
\r
687 pDM_SWAT_Table->PreAntenna = MAIN_ANT;
\r
688 pDM_SWAT_Table->SWAS_NoLink_State = 0;
\r
691 #endif //#if (RTL8821A_SUPPORT == 1)
\r
693 #if (RTL8881A_SUPPORT == 1)
\r
695 odm_RX_HWAntDiv_Init_8881A(
\r
696 IN PDM_ODM_T pDM_Odm
\r
699 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("***8881A AntDiv_Init => AntDivType=[ CGCS_RX_HW_ANTDIV] \n"));
\r
704 odm_TRX_HWAntDiv_Init_8881A(
\r
705 IN PDM_ODM_T pDM_Odm
\r
709 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("***8881A AntDiv_Init => AntDivType=[ CG_TRX_HW_ANTDIV (SPDT)] \n"));
\r
711 //Output Pin Settings
\r
713 ODM_SetMACReg(pDM_Odm, 0x4C , BIT25, 0);
\r
714 ODM_SetMACReg(pDM_Odm, 0x4C , BIT26, 0);
\r
715 ODM_SetBBReg(pDM_Odm, 0xCB4 , BIT31, 0); //delay buffer
\r
716 ODM_SetBBReg(pDM_Odm, 0xCB4 , BIT22, 0);
\r
717 ODM_SetBBReg(pDM_Odm, 0xCB4 , BIT24, 1);
\r
718 ODM_SetBBReg(pDM_Odm, 0xCB0 , 0xF00, 8); // DPDT_P = ANTSEL[0]
\r
719 ODM_SetBBReg(pDM_Odm, 0xCB0 , 0xF0000, 8); // DPDT_N = ANTSEL[0]
\r
722 ODM_SetBBReg(pDM_Odm, 0xCA4 , bMaskByte0, 0);
\r
723 ODM_SetBBReg(pDM_Odm, 0xCA4 , bMaskByte1, 1);
\r
725 //OFDM HW AntDiv Parameters
\r
726 ODM_SetBBReg(pDM_Odm, 0x8D4 , 0x7FF, 0xA0); //thershold
\r
727 ODM_SetBBReg(pDM_Odm, 0x8D4 , 0x7FF000, 0x0); //bias
\r
728 ODM_SetBBReg(pDM_Odm, 0x8CC , BIT20|BIT19|BIT18, 3); //settling time of antdiv by RF LNA = 100ns
\r
730 //CCK HW AntDiv Parameters
\r
731 ODM_SetBBReg(pDM_Odm, 0xA74 , BIT7, 1); //patch for clk from 88M to 80M
\r
732 ODM_SetBBReg(pDM_Odm, 0xA0C , BIT4, 1); //do 64 samples
\r
735 ODM_SetBBReg(pDM_Odm, 0x818 , BIT23|BIT22|BIT21|BIT20, 8); //keep antidx after tx for ACK ( unit x 32 mu sec)
\r
737 //2 [--For HW Bug Setting]
\r
739 ODM_SetBBReg(pDM_Odm, 0x900 , BIT18, 0); //TX Ant by Reg // A-cut bug
\r
742 #endif //#if (RTL8881A_SUPPORT == 1)
\r
745 #if (RTL8812A_SUPPORT == 1)
\r
747 odm_TRX_HWAntDiv_Init_8812A(
\r
748 IN PDM_ODM_T pDM_Odm
\r
751 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("***8812A AntDiv_Init => AntDivType=[ CG_TRX_HW_ANTDIV (SPDT)] \n"));
\r
753 //3 //3 --RFE pin setting---------
\r
755 ODM_SetBBReg(pDM_Odm, 0x900 , BIT10|BIT9|BIT8, 0x0); //disable SW switch
\r
756 ODM_SetBBReg(pDM_Odm, 0x900 , BIT17|BIT16, 0x0);
\r
757 ODM_SetBBReg(pDM_Odm, 0x974 , BIT7|BIT6, 0x3); // in/out
\r
758 ODM_SetBBReg(pDM_Odm, 0xCB4 , BIT31, 0); //delay buffer
\r
759 ODM_SetBBReg(pDM_Odm, 0xCB4 , BIT26, 0);
\r
760 ODM_SetBBReg(pDM_Odm, 0xCB4 , BIT27, 1);
\r
761 ODM_SetBBReg(pDM_Odm, 0xCB0 , 0xF000000, 8); // DPDT_P = ANTSEL[0]
\r
762 ODM_SetBBReg(pDM_Odm, 0xCB0 , 0xF0000000, 8); // DPDT_N = ANTSEL[0]
\r
763 //3 -------------------------
\r
766 ODM_SetBBReg(pDM_Odm, 0xCA4 , bMaskByte0, 0);
\r
767 ODM_SetBBReg(pDM_Odm, 0xCA4 , bMaskByte1, 1);
\r
769 //OFDM HW AntDiv Parameters
\r
770 ODM_SetBBReg(pDM_Odm, 0x8D4 , 0x7FF, 0xA0); //thershold
\r
771 ODM_SetBBReg(pDM_Odm, 0x8D4 , 0x7FF000, 0x0); //bias
\r
772 ODM_SetBBReg(pDM_Odm, 0x8CC , BIT20|BIT19|BIT18, 3); //settling time of antdiv by RF LNA = 100ns
\r
774 //CCK HW AntDiv Parameters
\r
775 ODM_SetBBReg(pDM_Odm, 0xA74 , BIT7, 1); //patch for clk from 88M to 80M
\r
776 ODM_SetBBReg(pDM_Odm, 0xA0C , BIT4, 1); //do 64 samples
\r
779 ODM_SetBBReg(pDM_Odm, 0x818 , BIT23|BIT22|BIT21|BIT20, 8); //keep antidx after tx for ACK ( unit x 32 mu sec)
\r
781 //2 [--For HW Bug Setting]
\r
783 ODM_SetBBReg(pDM_Odm, 0x900 , BIT18, 0); //TX Ant by Reg // A-cut bug
\r
787 #endif //#if (RTL8812A_SUPPORT == 1)
\r
791 IN PDM_ODM_T pDM_Odm
\r
794 u4Byte i,MinMaxRSSI=0xFF, AntDivMaxRSSI=0, MaxRSSI=0, LocalMaxRSSI;
\r
795 u4Byte Main_RSSI, Aux_RSSI, pkt_ratio_m=0, pkt_ratio_a=0,pkt_threshold=10;
\r
796 u1Byte RxIdleAnt=0, TargetAnt=7;
\r
797 pFAT_T pDM_FatTable = &pDM_Odm->DM_FatTable;
\r
798 pDIG_T pDM_DigTable = &pDM_Odm->DM_DigTable;
\r
799 PSTA_INFO_T pEntry;
\r
801 if(!pDM_Odm->bLinked) //bLinked==False
\r
803 ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[No Link!!!]\n"));
\r
805 #if(DM_ODM_SUPPORT_TYPE == ODM_AP)
\r
806 if (pDM_Odm->antdiv_rssi)
\r
807 panic_printk("[No Link!!!]\n");
\r
810 if(pDM_FatTable->bBecomeLinked == TRUE)
\r
812 odm_AntDiv_on_off(pDM_Odm, ANTDIV_OFF);
\r
813 ODM_UpdateRxIdleAnt(pDM_Odm, MAIN_ANT);
\r
815 pDM_FatTable->bBecomeLinked = pDM_Odm->bLinked;
\r
821 if(pDM_FatTable->bBecomeLinked ==FALSE)
\r
823 ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[Linked !!!]\n"));
\r
824 odm_AntDiv_on_off(pDM_Odm, ANTDIV_ON);
\r
825 if(pDM_Odm->SupportICType == ODM_RTL8821 )
\r
826 ODM_SetBBReg(pDM_Odm, 0x800 , BIT25, 0); //CCK AntDiv function disable
\r
828 #if(DM_ODM_SUPPORT_TYPE == ODM_AP)
\r
829 else if(pDM_Odm->SupportICType == ODM_RTL8881 )
\r
830 ODM_SetBBReg(pDM_Odm, 0x800 , BIT25, 0); //CCK AntDiv function disable
\r
833 else if(pDM_Odm->SupportICType == ODM_RTL8723B ||pDM_Odm->SupportICType == ODM_RTL8812)
\r
834 ODM_SetBBReg(pDM_Odm, 0xA00 , BIT15, 0); //CCK AntDiv function disable
\r
836 pDM_FatTable->bBecomeLinked = pDM_Odm->bLinked;
\r
838 if(pDM_Odm->SupportICType==ODM_RTL8723B && pDM_Odm->AntDivType == CG_TRX_HW_ANTDIV)
\r
840 ODM_SetBBReg(pDM_Odm, 0x930 , 0xF0, 8); // DPDT_P = ANTSEL[0] // for 8723B AntDiv function patch. BB Dino 130412
\r
841 ODM_SetBBReg(pDM_Odm, 0x930 , 0xF, 8); // DPDT_N = ANTSEL[0]
\r
846 ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("\n[HW AntDiv] Start =>\n"));
\r
848 for (i=0; i<ODM_ASSOCIATE_ENTRY_NUM; i++)
\r
850 pEntry = pDM_Odm->pODM_StaInfo[i];
\r
851 if(IS_STA_VALID(pEntry))
\r
853 //2 Caculate RSSI per Antenna
\r
854 Main_RSSI = (pDM_FatTable->MainAnt_Cnt[i]!=0)?(pDM_FatTable->MainAnt_Sum[i]/pDM_FatTable->MainAnt_Cnt[i]):0;
\r
855 Aux_RSSI = (pDM_FatTable->AuxAnt_Cnt[i]!=0)?(pDM_FatTable->AuxAnt_Sum[i]/pDM_FatTable->AuxAnt_Cnt[i]):0;
\r
856 TargetAnt = (Main_RSSI==Aux_RSSI)?pDM_FatTable->RxIdleAnt:((Main_RSSI>=Aux_RSSI)?MAIN_ANT:AUX_ANT);
\r
858 if( pDM_FatTable->MainAnt_Cnt[i]!=0 && pDM_FatTable->AuxAnt_Cnt[i]!=0 )
\r
860 pkt_ratio_m=( pDM_FatTable->MainAnt_Cnt[i] / pDM_FatTable->AuxAnt_Cnt[i] );
\r
861 pkt_ratio_a=( pDM_FatTable->AuxAnt_Cnt[i] / pDM_FatTable->MainAnt_Cnt[i] );
\r
863 if (pkt_ratio_m >= pkt_threshold)
\r
864 TargetAnt=MAIN_ANT;
\r
866 else if(pkt_ratio_a >= pkt_threshold)
\r
870 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV,ODM_DBG_LOUD,("*** SupportICType=[%u] \n",pDM_Odm->SupportICType));
\r
871 ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("*** Main_Cnt = (( %u )) , Main_RSSI= (( %u )) \n", pDM_FatTable->MainAnt_Cnt[i], Main_RSSI));
\r
872 ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("*** Aux_Cnt = (( %u )) , Aux_RSSI = (( %u )) \n", pDM_FatTable->AuxAnt_Cnt[i] , Aux_RSSI ));
\r
873 ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("*** MAC ID:[ %u ] , TargetAnt = (( %s )) \n", i ,( TargetAnt ==MAIN_ANT)?"MAIN_ANT":"AUX_ANT"));
\r
875 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV,ODM_DBG_LOUD,("*** Phy_AntSel_A=[ %d, %d, %d] \n",((pDM_Odm->DM_FatTable.antsel_rx_keep_0)&BIT2)>>2,
\r
876 ((pDM_Odm->DM_FatTable.antsel_rx_keep_0)&BIT1) >>1, ((pDM_Odm->DM_FatTable.antsel_rx_keep_0)&BIT0)));
\r
877 #if(DM_ODM_SUPPORT_TYPE == ODM_AP)
\r
878 if (pDM_Odm->antdiv_rssi)
\r
880 panic_printk("*** SupportICType=[%lu] \n",pDM_Odm->SupportICType);
\r
881 //panic_printk("*** Phy_AntSel_A=[ %d, %d, %d] \n",((pDM_Odm->DM_FatTable.antsel_rx_keep_0)&BIT2)>>2,
\r
882 // ((pDM_Odm->DM_FatTable.antsel_rx_keep_0)&BIT1) >>1, ((pDM_Odm->DM_FatTable.antsel_rx_keep_0)&BIT0));
\r
883 //panic_printk("*** Phy_AntSel_B=[ %d, %d, %d] \n",((pDM_Odm->DM_FatTable.antsel_rx_keep_1)&BIT2)>>2,
\r
884 // ((pDM_Odm->DM_FatTable.antsel_rx_keep_1)&BIT1) >>1, ((pDM_Odm->DM_FatTable.antsel_rx_keep_1)&BIT0))
\r
885 panic_printk("*** Client[ %lu ] , Main_Cnt = (( %lu )) , Main_RSSI= (( %lu )) \n",i, pDM_FatTable->MainAnt_Cnt[i], Main_RSSI);
\r
886 panic_printk("*** Client[ %lu ] , Aux_Cnt = (( %lu )) , Aux_RSSI = (( %lu )) \n" ,i, pDM_FatTable->AuxAnt_Cnt[i] , Aux_RSSI);
\r
891 LocalMaxRSSI = (Main_RSSI>Aux_RSSI)?Main_RSSI:Aux_RSSI;
\r
892 //2 Select MaxRSSI for DIG
\r
893 if((LocalMaxRSSI > AntDivMaxRSSI) && (LocalMaxRSSI < 40))
\r
894 AntDivMaxRSSI = LocalMaxRSSI;
\r
895 if(LocalMaxRSSI > MaxRSSI)
\r
896 MaxRSSI = LocalMaxRSSI;
\r
898 //2 Select RX Idle Antenna
\r
899 if ( (LocalMaxRSSI != 0) && (LocalMaxRSSI < MinMaxRSSI) )
\r
901 RxIdleAnt = TargetAnt;
\r
902 MinMaxRSSI = LocalMaxRSSI;
\r
905 if((pDM_FatTable->RxIdleAnt == MAIN_ANT) && (Main_RSSI == 0))
\r
906 Main_RSSI = Aux_RSSI;
\r
907 else if((pDM_FatTable->RxIdleAnt == AUX_ANT) && (Aux_RSSI == 0))
\r
908 Aux_RSSI = Main_RSSI;
\r
910 LocalMinRSSI = (Main_RSSI>Aux_RSSI)?Aux_RSSI:Main_RSSI;
\r
911 if(LocalMinRSSI < MinRSSI)
\r
913 MinRSSI = LocalMinRSSI;
\r
914 RxIdleAnt = TargetAnt;
\r
917 //2 Select TX Antenna
\r
922 if(pDM_Odm->AntDivType != CGCS_RX_HW_ANTDIV)
\r
923 odm_UpdateTxAnt(pDM_Odm, TargetAnt, i);
\r
927 pDM_FatTable->MainAnt_Sum[i] = 0;
\r
928 pDM_FatTable->AuxAnt_Sum[i] = 0;
\r
929 pDM_FatTable->MainAnt_Cnt[i] = 0;
\r
930 pDM_FatTable->AuxAnt_Cnt[i] = 0;
\r
933 //2 Set RX Idle Antenna
\r
934 ODM_UpdateRxIdleAnt(pDM_Odm, RxIdleAnt);
\r
936 #if(DM_ODM_SUPPORT_TYPE == ODM_AP)
\r
937 if (pDM_Odm->antdiv_rssi)
\r
938 panic_printk("*** RxIdleAnt = (( %s )) \n \n", ( RxIdleAnt ==MAIN_ANT)?"MAIN_ANT":"AUX_ANT");
\r
941 pDM_DigTable->AntDiv_RSSI_max = AntDivMaxRSSI;
\r
942 pDM_DigTable->RSSI_max = MaxRSSI;
\r
947 #if (RTL8723B_SUPPORT == 1)||(RTL8821A_SUPPORT == 1)
\r
950 IN PDM_ODM_T pDM_Odm,
\r
954 u4Byte i,MinMaxRSSI=0xFF, LocalMaxRSSI,LocalMinRSSI;
\r
955 u4Byte Main_RSSI, Aux_RSSI;
\r
956 u1Byte reset_period=10, SWAntDiv_threshold=35;
\r
957 u1Byte HighTraffic_TrainTime_U=0x32,HighTraffic_TrainTime_L,Train_time_temp;
\r
958 u1Byte LowTraffic_TrainTime_U=200,LowTraffic_TrainTime_L;
\r
959 u1Byte RxIdleAnt, TargetAnt, nextAnt;
\r
960 pSWAT_T pDM_SWAT_Table = &pDM_Odm->DM_SWAT_Table;
\r
961 pFAT_T pDM_FatTable = &pDM_Odm->DM_FatTable;
\r
962 PSTA_INFO_T pEntry=NULL;
\r
963 //static u1Byte reset_idx;
\r
965 PADAPTER Adapter = pDM_Odm->Adapter;
\r
966 u8Byte curTxOkCnt=0, curRxOkCnt=0,TxCntOffset, RxCntOffset;
\r
968 if(!pDM_Odm->bLinked) //bLinked==False
\r
970 ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[No Link!!!]\n"));
\r
971 if(pDM_FatTable->bBecomeLinked == TRUE)
\r
973 ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Set REG 948[9:6]=0x0 \n"));
\r
974 if(pDM_Odm->SupportICType == ODM_RTL8723B)
\r
975 ODM_SetBBReg(pDM_Odm, 0x948 , BIT9|BIT8|BIT7|BIT6, 0x0);
\r
977 pDM_FatTable->bBecomeLinked = pDM_Odm->bLinked;
\r
983 if(pDM_FatTable->bBecomeLinked ==FALSE)
\r
985 ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[Linked !!!]\n"));
\r
987 if(pDM_Odm->SupportICType == ODM_RTL8723B)
\r
989 value32 = ODM_GetBBReg(pDM_Odm, 0x864, BIT5|BIT4|BIT3);
\r
992 ODM_UpdateRxIdleAnt(pDM_Odm, MAIN_ANT);
\r
993 else if (value32==0x1)
\r
994 ODM_UpdateRxIdleAnt(pDM_Odm, AUX_ANT);
\r
996 ODM_SetBBReg(pDM_Odm, 0x948 , BIT6, 0x1);
\r
997 ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Set REG 948[6]=0x1 , Set REG 864[5:3]=0x%x \n",value32 ));
\r
1000 pDM_SWAT_Table->lastTxOkCnt = 0;
\r
1001 pDM_SWAT_Table->lastRxOkCnt =0;
\r
1002 TxCntOffset = Adapter->TxStats.NumTxBytesUnicast;
\r
1003 RxCntOffset = Adapter->RxStats.NumRxBytesUnicast;
\r
1005 pDM_FatTable->bBecomeLinked = pDM_Odm->bLinked;
\r
1014 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[%d] { try_flag=(( %d )), Step=(( %d )), Double_chk_flag = (( %d )) }\n",
\r
1015 __LINE__,pDM_SWAT_Table->try_flag,Step,pDM_SWAT_Table->Double_chk_flag));
\r
1017 // Handling step mismatch condition.
\r
1018 // Peak step is not finished at last time. Recover the variable and check again.
\r
1019 if( Step != pDM_SWAT_Table->try_flag )
\r
1021 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[Step != try_flag] Need to Reset After Link\n"));
\r
1022 ODM_SwAntDivRestAfterLink(pDM_Odm);
\r
1025 if(pDM_SWAT_Table->try_flag == 0xff)
\r
1027 pDM_SWAT_Table->try_flag = 0;
\r
1028 pDM_SWAT_Table->Train_time_flag=0;
\r
1029 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD,("[set try_flag = 0] Prepare for peak!\n\n"));
\r
1032 else//if( try_flag != 0xff )
\r
1034 //1 Normal State (Begin Trying)
\r
1035 if(pDM_SWAT_Table->try_flag == 0)
\r
1038 //---trafic decision---
\r
1039 curTxOkCnt = Adapter->TxStats.NumTxBytesUnicast - pDM_SWAT_Table->lastTxOkCnt - TxCntOffset;
\r
1040 curRxOkCnt =Adapter->RxStats.NumRxBytesUnicast - pDM_SWAT_Table->lastRxOkCnt - RxCntOffset;
\r
1041 pDM_SWAT_Table->lastTxOkCnt = Adapter->TxStats.NumTxBytesUnicast;
\r
1042 pDM_SWAT_Table->lastRxOkCnt = Adapter->RxStats.NumRxBytesUnicast;
\r
1044 if (curTxOkCnt > 1875000 || curRxOkCnt > 1875000)//if(PlatformDivision64(curTxOkCnt+curRxOkCnt, 2) > 1875000) ( 1.875M * 8bit ) / 2= 7.5M bits /sec )
\r
1046 pDM_SWAT_Table->TrafficLoad = TRAFFIC_HIGH;
\r
1047 Train_time_temp=pDM_SWAT_Table->Train_time ;
\r
1049 if(pDM_SWAT_Table->Train_time_flag==3)
\r
1051 HighTraffic_TrainTime_L=0xa;
\r
1053 if(Train_time_temp<=16)
\r
1054 Train_time_temp=HighTraffic_TrainTime_L;
\r
1056 Train_time_temp-=16;
\r
1059 else if(pDM_SWAT_Table->Train_time_flag==2)
\r
1061 Train_time_temp-=8;
\r
1062 HighTraffic_TrainTime_L=0xf;
\r
1064 else if(pDM_SWAT_Table->Train_time_flag==1)
\r
1066 Train_time_temp-=4;
\r
1067 HighTraffic_TrainTime_L=0x1e;
\r
1069 else if(pDM_SWAT_Table->Train_time_flag==0)
\r
1071 Train_time_temp+=8;
\r
1072 HighTraffic_TrainTime_L=0x28;
\r
1076 //ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("*** Train_time_temp = ((%d))\n",Train_time_temp));
\r
1079 if(Train_time_temp > HighTraffic_TrainTime_U)
\r
1080 Train_time_temp=HighTraffic_TrainTime_U;
\r
1082 else if(Train_time_temp < HighTraffic_TrainTime_L)
\r
1083 Train_time_temp=HighTraffic_TrainTime_L;
\r
1085 pDM_SWAT_Table->Train_time = Train_time_temp; //50ms~10ms
\r
1087 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD,(" Train_time_flag=((%d)) , Train_time=((%d)) \n",pDM_SWAT_Table->Train_time_flag, pDM_SWAT_Table->Train_time));
\r
1088 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, (" [HIGH Traffic] \n" ));
\r
1090 else if (curTxOkCnt > 125000 || curRxOkCnt > 125000) // ( 0.125M * 8bit ) / 2 = 0.5M bits /sec )
\r
1092 pDM_SWAT_Table->TrafficLoad = TRAFFIC_LOW;
\r
1093 Train_time_temp=pDM_SWAT_Table->Train_time ;
\r
1095 if(pDM_SWAT_Table->Train_time_flag==3)
\r
1097 LowTraffic_TrainTime_L=10;
\r
1098 if(Train_time_temp<50)
\r
1099 Train_time_temp=LowTraffic_TrainTime_L;
\r
1101 Train_time_temp-=50;
\r
1103 else if(pDM_SWAT_Table->Train_time_flag==2)
\r
1105 Train_time_temp-=30;
\r
1106 LowTraffic_TrainTime_L=36;
\r
1108 else if(pDM_SWAT_Table->Train_time_flag==1)
\r
1110 Train_time_temp-=10;
\r
1111 LowTraffic_TrainTime_L=40;
\r
1114 Train_time_temp+=10;
\r
1117 if(Train_time_temp >= LowTraffic_TrainTime_U)
\r
1118 Train_time_temp=LowTraffic_TrainTime_U;
\r
1120 else if(Train_time_temp <= LowTraffic_TrainTime_L)
\r
1121 Train_time_temp=LowTraffic_TrainTime_L;
\r
1123 pDM_SWAT_Table->Train_time = Train_time_temp; //50ms~20ms
\r
1125 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD,(" Train_time_flag=((%d)) , Train_time=((%d)) \n",pDM_SWAT_Table->Train_time_flag, pDM_SWAT_Table->Train_time));
\r
1126 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, (" [Low Traffic] \n" ));
\r
1130 pDM_SWAT_Table->TrafficLoad = TRAFFIC_UltraLOW;
\r
1131 pDM_SWAT_Table->Train_time = 0xc8; //200ms
\r
1132 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, (" [Ultra-Low Traffic] \n" ));
\r
1134 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("TxOkCnt=(( %llu )), RxOkCnt=(( %llu )) \n",
\r
1135 curTxOkCnt ,curRxOkCnt ));
\r
1137 //-----------------
\r
1139 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD,(" Current MinMaxRSSI is ((%d)) \n",pDM_FatTable->MinMaxRSSI));
\r
1141 //---reset index---
\r
1142 if(pDM_SWAT_Table->reset_idx>=reset_period)
\r
1144 pDM_FatTable->MinMaxRSSI=0; //
\r
1145 pDM_SWAT_Table->reset_idx=0;
\r
1147 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("reset_idx = (( %d )) \n",pDM_SWAT_Table->reset_idx ));
\r
1148 //ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD,("reset_idx=%d\n",pDM_SWAT_Table->reset_idx));
\r
1149 pDM_SWAT_Table->reset_idx++;
\r
1151 //---double check flag---
\r
1152 if(pDM_FatTable->MinMaxRSSI > SWAntDiv_threshold && pDM_SWAT_Table->Double_chk_flag== 0)
\r
1154 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD,(" MinMaxRSSI is ((%d)), and > %d \n",
\r
1155 pDM_FatTable->MinMaxRSSI,SWAntDiv_threshold));
\r
1157 pDM_SWAT_Table->Double_chk_flag =1;
\r
1158 pDM_SWAT_Table->try_flag = 1;
\r
1159 pDM_SWAT_Table->RSSI_Trying = 0;
\r
1161 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, (" Test the current Ant for (( %d )) ms again \n", pDM_SWAT_Table->Train_time));
\r
1162 ODM_UpdateRxIdleAnt(pDM_Odm, pDM_FatTable->RxIdleAnt);
\r
1163 ODM_SetTimer(pDM_Odm,&pDM_SWAT_Table->SwAntennaSwitchTimer_8723B, pDM_SWAT_Table->Train_time ); //ms
\r
1167 nextAnt = (pDM_FatTable->RxIdleAnt == MAIN_ANT)? AUX_ANT : MAIN_ANT;
\r
1169 pDM_SWAT_Table->try_flag = 1;
\r
1171 if(pDM_SWAT_Table->reset_idx<=1)
\r
1172 pDM_SWAT_Table->RSSI_Trying = 2;
\r
1174 pDM_SWAT_Table->RSSI_Trying = 1;
\r
1176 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD,("[set try_flag=1] Normal State: Begin Trying!! \n"));
\r
1180 else if(pDM_SWAT_Table->try_flag == 1 && pDM_SWAT_Table->Double_chk_flag== 0)
\r
1182 nextAnt = (pDM_FatTable->RxIdleAnt == MAIN_ANT)? AUX_ANT : MAIN_ANT;
\r
1183 pDM_SWAT_Table->RSSI_Trying--;
\r
1186 //1 Decision State
\r
1187 if((pDM_SWAT_Table->try_flag == 1)&&(pDM_SWAT_Table->RSSI_Trying == 0) )
\r
1190 for (i=0; i<ODM_ASSOCIATE_ENTRY_NUM; i++)
\r
1192 pEntry = pDM_Odm->pODM_StaInfo[i];
\r
1193 if(IS_STA_VALID(pEntry))
\r
1195 //2 Caculate RSSI per Antenna
\r
1196 Main_RSSI = (pDM_FatTable->MainAnt_Cnt[i]!=0)?(pDM_FatTable->MainAnt_Sum[i]/pDM_FatTable->MainAnt_Cnt[i]):0;
\r
1197 Aux_RSSI = (pDM_FatTable->AuxAnt_Cnt[i]!=0)?(pDM_FatTable->AuxAnt_Sum[i]/pDM_FatTable->AuxAnt_Cnt[i]):0;
\r
1199 if(pDM_FatTable->MainAnt_Cnt[i]<=1 && pDM_FatTable->CCK_counter_main>=1)
\r
1202 if(pDM_FatTable->AuxAnt_Cnt[i]<=1 && pDM_FatTable->CCK_counter_aux>=1)
\r
1205 TargetAnt = (Main_RSSI==Aux_RSSI)?pDM_SWAT_Table->PreAntenna:((Main_RSSI>=Aux_RSSI)?MAIN_ANT:AUX_ANT);
\r
1206 LocalMaxRSSI = (Main_RSSI>=Aux_RSSI) ? Main_RSSI : Aux_RSSI;
\r
1207 LocalMinRSSI = (Main_RSSI>=Aux_RSSI) ? Aux_RSSI : Main_RSSI;
\r
1209 ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("*** CCK_counter_main = (( %d )) , CCK_counter_aux= (( %d )) \n", pDM_FatTable->CCK_counter_main, pDM_FatTable->CCK_counter_aux));
\r
1210 ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("*** OFDM_counter_main = (( %d )) , OFDM_counter_aux= (( %d )) \n", pDM_FatTable->OFDM_counter_main, pDM_FatTable->OFDM_counter_aux));
\r
1211 ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("*** Main_Cnt = (( %d )) , Main_RSSI= (( %d )) \n", pDM_FatTable->MainAnt_Cnt[i], Main_RSSI));
\r
1212 ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("*** Aux_Cnt = (( %d )) , Aux_RSSI = (( %d )) \n", pDM_FatTable->AuxAnt_Cnt[i] , Aux_RSSI ));
\r
1213 ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("*** MAC ID:[ %d ] , TargetAnt = (( %s )) \n", i ,( TargetAnt ==MAIN_ANT)?"MAIN_ANT":"AUX_ANT"));
\r
1215 //2 Select RX Idle Antenna
\r
1217 if (LocalMaxRSSI != 0 && LocalMaxRSSI < MinMaxRSSI)
\r
1219 RxIdleAnt = TargetAnt;
\r
1220 MinMaxRSSI = LocalMaxRSSI;
\r
1221 ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("*** LocalMaxRSSI-LocalMinRSSI = ((%d))\n",(LocalMaxRSSI-LocalMinRSSI)));
\r
1223 if((LocalMaxRSSI-LocalMinRSSI)>8)
\r
1225 if(LocalMinRSSI != 0)
\r
1226 pDM_SWAT_Table->Train_time_flag=3;
\r
1229 if(MinMaxRSSI > SWAntDiv_threshold)
\r
1230 pDM_SWAT_Table->Train_time_flag=0;
\r
1232 pDM_SWAT_Table->Train_time_flag=3;
\r
1235 else if((LocalMaxRSSI-LocalMinRSSI)>5)
\r
1236 pDM_SWAT_Table->Train_time_flag=2;
\r
1237 else if((LocalMaxRSSI-LocalMinRSSI)>2)
\r
1238 pDM_SWAT_Table->Train_time_flag=1;
\r
1240 pDM_SWAT_Table->Train_time_flag=0;
\r
1244 //2 Select TX Antenna
\r
1245 if(TargetAnt == MAIN_ANT)
\r
1246 pDM_FatTable->antsel_a[i] = ANT1_2G;
\r
1248 pDM_FatTable->antsel_a[i] = ANT2_2G;
\r
1251 pDM_FatTable->MainAnt_Sum[i] = 0;
\r
1252 pDM_FatTable->AuxAnt_Sum[i] = 0;
\r
1253 pDM_FatTable->MainAnt_Cnt[i] = 0;
\r
1254 pDM_FatTable->AuxAnt_Cnt[i] = 0;
\r
1255 pDM_FatTable->CCK_counter_main=0;
\r
1256 pDM_FatTable->CCK_counter_aux=0;
\r
1257 pDM_FatTable->OFDM_counter_main=0;
\r
1258 pDM_FatTable->OFDM_counter_aux=0;
\r
1263 pDM_FatTable->MinMaxRSSI=MinMaxRSSI;
\r
1264 pDM_SWAT_Table->try_flag = 0;
\r
1266 if( pDM_SWAT_Table->Double_chk_flag==1)
\r
1268 pDM_SWAT_Table->Double_chk_flag=0;
\r
1269 if(pDM_FatTable->MinMaxRSSI > SWAntDiv_threshold)
\r
1271 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD,(" [Double check] MinMaxRSSI ((%d)) > %d again!! \n",
\r
1272 pDM_FatTable->MinMaxRSSI,SWAntDiv_threshold));
\r
1274 ODM_UpdateRxIdleAnt(pDM_Odm, RxIdleAnt);
\r
1276 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD,("[reset try_flag = 0] Training accomplished !!!] \n\n\n"));
\r
1281 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD,(" [Double check] MinMaxRSSI ((%d)) <= %d !! \n",
\r
1282 pDM_FatTable->MinMaxRSSI,SWAntDiv_threshold));
\r
1284 nextAnt = (pDM_FatTable->RxIdleAnt == MAIN_ANT)? AUX_ANT : MAIN_ANT;
\r
1285 pDM_SWAT_Table->try_flag = 0;
\r
1286 pDM_SWAT_Table->reset_idx=reset_period;
\r
1287 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD,("[set try_flag=0] Normal State: Need to tryg again!! \n\n\n"));
\r
1293 pDM_SWAT_Table->PreAntenna =RxIdleAnt;
\r
1294 ODM_UpdateRxIdleAnt(pDM_Odm, RxIdleAnt );
\r
1295 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD,("[reset try_flag = 0] Training accomplished !!!] \n\n\n"));
\r
1303 //1 4.Change TRX antenna
\r
1305 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("RSSI_Trying = (( %d )), Ant: (( %s )) >>> (( %s )) \n",
\r
1306 pDM_SWAT_Table->RSSI_Trying, (pDM_FatTable->RxIdleAnt == MAIN_ANT?"MAIN":"AUX"),(nextAnt == MAIN_ANT?"MAIN":"AUX")));
\r
1308 ODM_UpdateRxIdleAnt(pDM_Odm, nextAnt);
\r
1310 //1 5.Reset Statistics
\r
1312 pDM_FatTable->RxIdleAnt = nextAnt;
\r
1314 //1 6.Set next timer (Trying State)
\r
1316 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, (" Test ((%s)) Ant for (( %d )) ms \n", (nextAnt == MAIN_ANT?"MAIN":"AUX"), pDM_SWAT_Table->Train_time));
\r
1317 ODM_SetTimer(pDM_Odm,&pDM_SWAT_Table->SwAntennaSwitchTimer_8723B, pDM_SWAT_Table->Train_time ); //ms
\r
1321 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
\r
1323 ODM_SW_AntDiv_Callback(
\r
1327 PADAPTER Adapter = (PADAPTER)pTimer->Adapter;
\r
1328 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
\r
1329 pSWAT_T pDM_SWAT_Table = &pHalData->DM_OutSrc.DM_SWAT_Table;
\r
1331 #if DEV_BUS_TYPE==RT_PCI_INTERFACE
\r
1333 ODM_ScheduleWorkItem(&pDM_SWAT_Table->SwAntennaSwitchWorkitem_8723B);
\r
1336 //DbgPrint("SW_antdiv_Callback");
\r
1337 odm_S0S1_SwAntDiv(&pHalData->DM_OutSrc, SWAW_STEP_DETERMINE);
\r
1341 ODM_ScheduleWorkItem(&pDM_SWAT_Table->SwAntennaSwitchWorkitem_8723B);
\r
1345 ODM_SW_AntDiv_WorkitemCallback(
\r
1349 PADAPTER pAdapter = (PADAPTER)pContext;
\r
1350 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
\r
1352 //DbgPrint("SW_antdiv_Workitem_Callback");
\r
1353 odm_S0S1_SwAntDiv(&pHalData->DM_OutSrc, SWAW_STEP_DETERMINE);
\r
1355 #endif //#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
\r
1357 #if (DM_ODM_SUPPORT_TYPE == ODM_CE)
\r
1359 ODM_SW_AntDiv_Callback(void *FunctionContext)
\r
1361 PDM_ODM_T pDM_Odm= (PDM_ODM_T)FunctionContext;
\r
1362 PADAPTER padapter = pDM_Odm->Adapter;
\r
1363 if(padapter->net_closed == _TRUE)
\r
1365 //odm_S0S1_SwAntDiv(pDM_Odm, SWAW_STEP_DETERMINE);
\r
1367 #endif //#if (DM_ODM_SUPPORT_TYPE == ODM_CE)
\r
1369 #endif //#if (RTL8723B_SUPPORT == 1)
\r
1372 #if(RTL8188E_SUPPORT == 1 || RTL8192E_SUPPORT == 1)
\r
1373 #if (!(DM_ODM_SUPPORT_TYPE == ODM_CE))
\r
1375 odm_SetNextMACAddrTarget(
\r
1376 IN PDM_ODM_T pDM_Odm
\r
1379 pFAT_T pDM_FatTable = &pDM_Odm->DM_FatTable;
\r
1380 PSTA_INFO_T pEntry;
\r
1381 //u1Byte Bssid[6];
\r
1382 u4Byte value32, i;
\r
1385 //2012.03.26 LukeLee: The MAC address is changed according to MACID in turn
\r
1387 ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("odm_SetNextMACAddrTarget() ==>\n"));
\r
1388 if(pDM_Odm->bLinked)
\r
1390 for (i=0; i<ODM_ASSOCIATE_ENTRY_NUM; i++)
\r
1392 if((pDM_FatTable->TrainIdx+1) == ODM_ASSOCIATE_ENTRY_NUM)
\r
1393 pDM_FatTable->TrainIdx = 0;
\r
1395 pDM_FatTable->TrainIdx++;
\r
1397 pEntry = pDM_Odm->pODM_StaInfo[pDM_FatTable->TrainIdx];
\r
1398 if(IS_STA_VALID(pEntry))
\r
1401 #if (DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL))
\r
1402 value32 = (pEntry->hwaddr[5]<<8)|pEntry->hwaddr[4];
\r
1404 value32 = (pEntry->MacAddr[5]<<8)|pEntry->MacAddr[4];
\r
1406 ODM_SetMACReg(pDM_Odm, 0x7b4, 0xFFFF, value32);
\r
1407 #if (DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL))
\r
1408 value32 = (pEntry->hwaddr[3]<<24)|(pEntry->hwaddr[2]<<16) |(pEntry->hwaddr[1]<<8) |pEntry->hwaddr[0];
\r
1410 value32 = (pEntry->MacAddr[3]<<24)|(pEntry->MacAddr[2]<<16) |(pEntry->MacAddr[1]<<8) |pEntry->MacAddr[0];
\r
1412 ODM_SetMACReg(pDM_Odm, 0x7b0, bMaskDWord, value32);
\r
1414 ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("pDM_FatTable->TrainIdx=%lu\n",pDM_FatTable->TrainIdx));
\r
1415 #if (DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL))
\r
1416 ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Training MAC Addr = %x:%x:%x:%x:%x:%x\n",
\r
1417 pEntry->hwaddr[5],pEntry->hwaddr[4],pEntry->hwaddr[3],pEntry->hwaddr[2],pEntry->hwaddr[1],pEntry->hwaddr[0]));
\r
1419 ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Training MAC Addr = %x:%x:%x:%x:%x:%x\n",
\r
1420 pEntry->MacAddr[5],pEntry->MacAddr[4],pEntry->MacAddr[3],pEntry->MacAddr[2],pEntry->MacAddr[1],pEntry->MacAddr[0]));
\r
1431 //2012.03.26 LukeLee: This should be removed later, the MAC address is changed according to MACID in turn
\r
1433 #if( DM_ODM_SUPPORT_TYPE & ODM_WIN)
\r
1435 PADAPTER Adapter = pDM_Odm->Adapter;
\r
1436 PMGNT_INFO pMgntInfo = &Adapter->MgntInfo;
\r
1438 for (i=0; i<6; i++)
\r
1440 Bssid[i] = pMgntInfo->Bssid[i];
\r
1441 //DbgPrint("Bssid[%d]=%x\n", i, Bssid[i]);
\r
1446 //odm_SetNextMACAddrTarget(pDM_Odm);
\r
1448 //1 Select MAC Address Filter
\r
1449 for (i=0; i<6; i++)
\r
1451 if(Bssid[i] != pDM_FatTable->Bssid[i])
\r
1453 bMatchBSSID = FALSE;
\r
1457 if(bMatchBSSID == FALSE)
\r
1460 value32 = (Bssid[5]<<8)|Bssid[4];
\r
1461 ODM_SetMACReg(pDM_Odm, 0x7b4, 0xFFFF, value32);
\r
1462 value32 = (Bssid[3]<<24)|(Bssid[2]<<16) |(Bssid[1]<<8) |Bssid[0];
\r
1463 ODM_SetMACReg(pDM_Odm, 0x7b0, bMaskDWord, value32);
\r
1466 return bMatchBSSID;
\r
1472 odm_FastAntTraining(
\r
1473 IN PDM_ODM_T pDM_Odm
\r
1476 u4Byte i, MaxRSSI=0;
\r
1477 u1Byte TargetAnt=2;
\r
1478 pFAT_T pDM_FatTable = &pDM_Odm->DM_FatTable;
\r
1479 BOOLEAN bPktFilterMacth = FALSE;
\r
1481 ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("==>odm_FastAntTraining()\n"));
\r
1483 //1 TRAINING STATE
\r
1484 if(pDM_FatTable->FAT_State == FAT_TRAINING_STATE)
\r
1486 ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Enter FAT_TRAINING_STATE\n"));
\r
1487 //2 Caculate RSSI per Antenna
\r
1488 for (i=0; i<7; i++)
\r
1490 if(pDM_FatTable->antRSSIcnt[i] == 0)
\r
1491 pDM_FatTable->antAveRSSI[i] = 0;
\r
1494 pDM_FatTable->antAveRSSI[i] = pDM_FatTable->antSumRSSI[i] /pDM_FatTable->antRSSIcnt[i];
\r
1495 bPktFilterMacth = TRUE;
\r
1497 if(pDM_FatTable->antAveRSSI[i] > MaxRSSI)
\r
1499 MaxRSSI = pDM_FatTable->antAveRSSI[i];
\r
1500 TargetAnt = (u1Byte) i;
\r
1503 ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("pDM_FatTable->antAveRSSI[%lu] = %lu, pDM_FatTable->antRSSIcnt[%lu] = %lu\n",
\r
1504 i, pDM_FatTable->antAveRSSI[i], i, pDM_FatTable->antRSSIcnt[i]));
\r
1507 //2 Select TRX Antenna
\r
1508 if(bPktFilterMacth == FALSE)
\r
1510 ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("None Packet is matched\n"));
\r
1512 ODM_SetBBReg(pDM_Odm, 0xe08 , BIT16, 0); //RegE08[16]=1'b0 //disable fast training
\r
1513 ODM_SetBBReg(pDM_Odm, 0xc50 , BIT7, 0); //RegC50[7]=1'b0 //disable HW AntDiv
\r
1517 ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("TargetAnt=%d, MaxRSSI=%lu\n",TargetAnt,MaxRSSI));
\r
1519 ODM_SetBBReg(pDM_Odm, 0xe08 , BIT16, 0); //RegE08[16]=1'b0 //disable fast training
\r
1520 //ODM_SetBBReg(pDM_Odm, 0xc50 , BIT7, 0); //RegC50[7]=1'b0 //disable HW AntDiv
\r
1521 ODM_SetBBReg(pDM_Odm, 0x864 , BIT8|BIT7|BIT6, TargetAnt); //Default RX is Omni, Optional RX is the best decision by FAT
\r
1522 //ODM_SetBBReg(pDM_Odm, 0x860 , BIT14|BIT13|BIT12, TargetAnt); //Default TX
\r
1523 ODM_SetBBReg(pDM_Odm, 0x80c , BIT21, 1); //Reg80c[21]=1'b1 //from TX Info
\r
1526 pEntry = pDM_Odm->pODM_StaInfo[pDM_FatTable->TrainIdx];
\r
1528 if(IS_STA_VALID(pEntry))
\r
1530 pEntry->antsel_a = TargetAnt&BIT0;
\r
1531 pEntry->antsel_b = (TargetAnt&BIT1)>>1;
\r
1532 pEntry->antsel_c = (TargetAnt&BIT2)>>2;
\r
1535 pDM_FatTable->antsel_a[pDM_FatTable->TrainIdx] = TargetAnt&BIT0;
\r
1536 pDM_FatTable->antsel_b[pDM_FatTable->TrainIdx] = (TargetAnt&BIT1)>>1;
\r
1537 pDM_FatTable->antsel_c[pDM_FatTable->TrainIdx] = (TargetAnt&BIT2)>>2;
\r
1541 if(TargetAnt == 0)
\r
1542 ODM_SetBBReg(pDM_Odm, 0xc50 , BIT7, 0); //RegC50[7]=1'b0 //disable HW AntDiv
\r
1547 for(i=0; i<7; i++)
\r
1549 pDM_FatTable->antSumRSSI[i] = 0;
\r
1550 pDM_FatTable->antRSSIcnt[i] = 0;
\r
1553 pDM_FatTable->FAT_State = FAT_NORMAL_STATE;
\r
1558 if(pDM_FatTable->FAT_State == FAT_NORMAL_STATE)
\r
1560 ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Enter FAT_NORMAL_STATE\n"));
\r
1562 odm_SetNextMACAddrTarget(pDM_Odm);
\r
1565 pEntry = pDM_Odm->pODM_StaInfo[pDM_FatTable->TrainIdx];
\r
1566 if(IS_STA_VALID(pEntry))
\r
1568 pEntry->antsel_a = TargetAnt&BIT0;
\r
1569 pEntry->antsel_b = (TargetAnt&BIT1)>>1;
\r
1570 pEntry->antsel_c = (TargetAnt&BIT2)>>2;
\r
1574 //2 Prepare Training
\r
1575 pDM_FatTable->FAT_State = FAT_TRAINING_STATE;
\r
1576 ODM_SetBBReg(pDM_Odm, 0xe08 , BIT16, 1); //RegE08[16]=1'b1 //enable fast training
\r
1577 ODM_SetBBReg(pDM_Odm, 0xc50 , BIT7, 1); //RegC50[7]=1'b1 //enable HW AntDiv
\r
1578 ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Start FAT_TRAINING_STATE\n"));
\r
1579 ODM_SetTimer(pDM_Odm,&pDM_Odm->FastAntTrainingTimer, 500 ); //ms
\r
1586 odm_FastAntTrainingCallback(
\r
1587 IN PDM_ODM_T pDM_Odm
\r
1591 #if (DM_ODM_SUPPORT_TYPE == ODM_CE)
\r
1592 PADAPTER padapter = pDM_Odm->Adapter;
\r
1593 if(padapter->net_closed == _TRUE)
\r
1595 //if(*pDM_Odm->pbNet_closed == TRUE)
\r
1600 ODM_ScheduleWorkItem(&pDM_Odm->FastAntTrainingWorkitem);
\r
1602 odm_FastAntTraining(pDM_Odm);
\r
1607 odm_FastAntTrainingWorkItemCallback(
\r
1608 IN PDM_ODM_T pDM_Odm
\r
1611 odm_FastAntTraining(pDM_Odm);
\r
1620 IN PDM_ODM_T pDM_Odm
\r
1623 pFAT_T pDM_FatTable = &pDM_Odm->DM_FatTable;
\r
1624 pSWAT_T pDM_SWAT_Table = &pDM_Odm->DM_SWAT_Table;
\r
1627 if(!(pDM_Odm->SupportAbility & ODM_BB_ANT_DIV))
\r
1629 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV,ODM_DBG_LOUD,("[Return!!!] Not Support Antenna Diversity Function\n"));
\r
1633 #if (DM_ODM_SUPPORT_TYPE == ODM_AP)
\r
1634 if(pDM_FatTable->AntDiv_2G_5G == ODM_ANTDIV_2G)
\r
1636 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV,ODM_DBG_LOUD,("[2G AntDiv Init]: Only Support 2G Antenna Diversity Function\n"));
\r
1637 if(!(pDM_Odm->SupportICType & ODM_ANTDIV_2G_SUPPORT_IC))
\r
1640 else if(pDM_FatTable->AntDiv_2G_5G == ODM_ANTDIV_5G)
\r
1642 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV,ODM_DBG_LOUD,("[5G AntDiv Init]: Only Support 5G Antenna Diversity Function\n"));
\r
1643 if(!(pDM_Odm->SupportICType & ODM_ANTDIV_5G_SUPPORT_IC))
\r
1646 else if(pDM_FatTable->AntDiv_2G_5G == (ODM_ANTDIV_2G|ODM_ANTDIV_5G))
\r
1648 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV,ODM_DBG_LOUD,("[2G & 5G AntDiv Init]:Support Both 2G & 5G Antenna Diversity Function\n"));
\r
1651 pDM_Odm->antdiv_rssi=0;
\r
1656 //2 [--General---]
\r
1657 pDM_Odm->antdiv_period=0;
\r
1658 pDM_Odm->antdiv_select=0;
\r
1659 pDM_SWAT_Table->Ant5G = MAIN_ANT;
\r
1660 pDM_SWAT_Table->Ant2G = MAIN_ANT;
\r
1661 pDM_FatTable->CCK_counter_main=0;
\r
1662 pDM_FatTable->CCK_counter_aux=0;
\r
1663 pDM_FatTable->OFDM_counter_main=0;
\r
1664 pDM_FatTable->OFDM_counter_aux=0;
\r
1666 //3 [Set MAIN_ANT as default antenna if Auto-Ant enable]
\r
1667 if (pDM_Odm->antdiv_select==1)
\r
1668 pDM_Odm->AntType = ODM_FIX_MAIN_ANT;
\r
1669 else if (pDM_Odm->antdiv_select==2)
\r
1670 pDM_Odm->AntType = ODM_FIX_AUX_ANT;
\r
1671 else if(pDM_Odm->antdiv_select==0)
\r
1672 pDM_Odm->AntType = ODM_AUTO_ANT;
\r
1674 if(pDM_Odm->AntType == ODM_AUTO_ANT)
\r
1676 odm_AntDiv_on_off(pDM_Odm, ANTDIV_OFF);
\r
1677 ODM_UpdateRxIdleAnt(pDM_Odm, MAIN_ANT);
\r
1681 odm_AntDiv_on_off(pDM_Odm, ANTDIV_OFF);
\r
1683 if(pDM_Odm->AntType == ODM_FIX_MAIN_ANT)
\r
1685 ODM_UpdateRxIdleAnt(pDM_Odm, MAIN_ANT);
\r
1688 else if(pDM_Odm->AntType == ODM_FIX_AUX_ANT)
\r
1690 ODM_UpdateRxIdleAnt(pDM_Odm, AUX_ANT);
\r
1695 if(pDM_Odm->AntDivType != CGCS_RX_HW_ANTDIV)
\r
1697 if(pDM_Odm->SupportICType & ODM_N_ANTDIV_SUPPORT)
\r
1700 ODM_SetBBReg(pDM_Odm, 0x80c , BIT21, 0); //Reg80c[21]=1'b0 //from Reg
\r
1702 ODM_SetBBReg(pDM_Odm, 0x80c , BIT21, 1);
\r
1705 else if(pDM_Odm->SupportICType & ODM_AC_ANTDIV_SUPPORT)
\r
1708 ODM_SetBBReg(pDM_Odm, 0x900 , BIT18, 0);
\r
1710 ODM_SetBBReg(pDM_Odm, 0x900 , BIT18, 1);
\r
1716 if(pDM_Odm->SupportICType == ODM_RTL8188E)
\r
1718 #if (RTL8188E_SUPPORT == 1)
\r
1719 //pDM_Odm->AntDivType = CGCS_RX_HW_ANTDIV;
\r
1720 //pDM_Odm->AntDivType = CG_TRX_HW_ANTDIV;
\r
1721 //pDM_Odm->AntDivType = CG_TRX_SMART_ANTDIV;
\r
1723 if( (pDM_Odm->AntDivType != CGCS_RX_HW_ANTDIV) && (pDM_Odm->AntDivType != CG_TRX_HW_ANTDIV) && (pDM_Odm->AntDivType != CG_TRX_SMART_ANTDIV))
\r
1725 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV,ODM_DBG_LOUD,("[Return!!!] 88E Not Supprrt This AntDiv Type\n"));
\r
1726 pDM_Odm->SupportAbility &= ~(ODM_BB_ANT_DIV);
\r
1730 if(pDM_Odm->AntDivType == CGCS_RX_HW_ANTDIV)
\r
1731 odm_RX_HWAntDiv_Init_88E(pDM_Odm);
\r
1732 else if(pDM_Odm->AntDivType == CG_TRX_HW_ANTDIV)
\r
1733 odm_TRX_HWAntDiv_Init_88E(pDM_Odm);
\r
1734 else if(pDM_Odm->AntDivType == CG_TRX_SMART_ANTDIV)
\r
1735 odm_Smart_HWAntDiv_Init_88E(pDM_Odm);
\r
1740 #if (RTL8192E_SUPPORT == 1)
\r
1741 else if(pDM_Odm->SupportICType == ODM_RTL8192E)
\r
1743 //pDM_Odm->AntDivType = CGCS_RX_HW_ANTDIV;
\r
1744 //pDM_Odm->AntDivType = CG_TRX_HW_ANTDIV;
\r
1745 //pDM_Odm->AntDivType = CG_TRX_SMART_ANTDIV;
\r
1747 if( (pDM_Odm->AntDivType != CGCS_RX_HW_ANTDIV) && (pDM_Odm->AntDivType != CG_TRX_HW_ANTDIV) && (pDM_Odm->AntDivType != CG_TRX_SMART_ANTDIV))
\r
1749 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV,ODM_DBG_LOUD,("[Return!!!] 8192E Not Supprrt This AntDiv Type\n"));
\r
1750 pDM_Odm->SupportAbility &= ~(ODM_BB_ANT_DIV);
\r
1754 if(pDM_Odm->AntDivType == CGCS_RX_HW_ANTDIV)
\r
1755 odm_RX_HWAntDiv_Init_92E(pDM_Odm);
\r
1756 else if(pDM_Odm->AntDivType == CG_TRX_HW_ANTDIV)
\r
1757 odm_TRX_HWAntDiv_Init_92E(pDM_Odm);
\r
1758 else if(pDM_Odm->AntDivType == CG_TRX_SMART_ANTDIV)
\r
1759 odm_Smart_HWAntDiv_Init_92E(pDM_Odm);
\r
1765 #if (RTL8723B_SUPPORT == 1)
\r
1766 else if(pDM_Odm->SupportICType == ODM_RTL8723B)
\r
1768 //pDM_Odm->AntDivType = S0S1_SW_ANTDIV;
\r
1769 //pDM_Odm->AntDivType = CG_TRX_HW_ANTDIV;
\r
1771 if(pDM_Odm->AntDivType != S0S1_SW_ANTDIV && pDM_Odm->AntDivType != CG_TRX_HW_ANTDIV)
\r
1773 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV,ODM_DBG_LOUD,("[Return!!!] 8723B Not Supprrt This AntDiv Type\n"));
\r
1774 pDM_Odm->SupportAbility &= ~(ODM_BB_ANT_DIV);
\r
1778 if( pDM_Odm->AntDivType==S0S1_SW_ANTDIV)
\r
1779 odm_S0S1_SWAntDiv_Init_8723B(pDM_Odm);
\r
1780 else if(pDM_Odm->AntDivType==CG_TRX_HW_ANTDIV)
\r
1781 odm_TRX_HWAntDiv_Init_8723B(pDM_Odm);
\r
1785 //2 [--8811A 8821A---]
\r
1786 #if (RTL8821A_SUPPORT == 1)
\r
1787 else if(pDM_Odm->SupportICType == ODM_RTL8821)
\r
1789 //pDM_Odm->AntDivType = CG_TRX_HW_ANTDIV;
\r
1790 pDM_Odm->AntDivType = S0S1_SW_ANTDIV;
\r
1792 if( pDM_Odm->AntDivType != CG_TRX_HW_ANTDIV && pDM_Odm->AntDivType != S0S1_SW_ANTDIV)
\r
1794 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV,ODM_DBG_LOUD,("[Return!!!] 8821A & 8811A Not Supprrt This AntDiv Type\n"));
\r
1795 pDM_Odm->SupportAbility &= ~(ODM_BB_ANT_DIV);
\r
1798 if(pDM_Odm->AntDivType==CG_TRX_HW_ANTDIV)
\r
1799 odm_TRX_HWAntDiv_Init_8821A(pDM_Odm);
\r
1800 else if( pDM_Odm->AntDivType==S0S1_SW_ANTDIV)
\r
1801 odm_S0S1_SWAntDiv_Init_8821A(pDM_Odm);
\r
1806 #if (RTL8881A_SUPPORT == 1)
\r
1807 else if(pDM_Odm->SupportICType == ODM_RTL8881A)
\r
1809 //pDM_Odm->AntDivType = CGCS_RX_HW_ANTDIV;
\r
1810 //pDM_Odm->AntDivType = CG_TRX_HW_ANTDIV;
\r
1812 if(pDM_Odm->AntDivType != CGCS_RX_HW_ANTDIV && pDM_Odm->AntDivType != CG_TRX_HW_ANTDIV)
\r
1814 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV,ODM_DBG_LOUD,("[Return!!!] 8881A Not Supprrt This AntDiv Type\n"));
\r
1815 pDM_Odm->SupportAbility &= ~(ODM_BB_ANT_DIV);
\r
1818 if(pDM_Odm->AntDivType == CGCS_RX_HW_ANTDIV)
\r
1819 odm_RX_HWAntDiv_Init_8881A(pDM_Odm);
\r
1820 else if(pDM_Odm->AntDivType == CG_TRX_HW_ANTDIV)
\r
1821 odm_TRX_HWAntDiv_Init_8881A(pDM_Odm);
\r
1826 #if (RTL8812A_SUPPORT == 1)
\r
1827 else if(pDM_Odm->SupportICType == ODM_RTL8812)
\r
1829 //pDM_Odm->AntDivType = CG_TRX_HW_ANTDIV;
\r
1831 if( pDM_Odm->AntDivType != CG_TRX_HW_ANTDIV)
\r
1833 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV,ODM_DBG_LOUD,("[Return!!!] 8812A Not Supprrt This AntDiv Type\n"));
\r
1834 pDM_Odm->SupportAbility &= ~(ODM_BB_ANT_DIV);
\r
1837 odm_TRX_HWAntDiv_Init_8812A(pDM_Odm);
\r
1840 //ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV,ODM_DBG_LOUD,("*** SupportICType=[%lu] \n",pDM_Odm->SupportICType));
\r
1841 //ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV,ODM_DBG_LOUD,("*** AntDiv SupportAbility=[%lu] \n",(pDM_Odm->SupportAbility & ODM_BB_ANT_DIV)>>6));
\r
1842 //ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV,ODM_DBG_LOUD,("*** AntDiv Type=[%d] \n",pDM_Odm->AntDivType));
\r
1848 IN PDM_ODM_T pDM_Odm
\r
1851 PADAPTER pAdapter = pDM_Odm->Adapter;
\r
1852 pFAT_T pDM_FatTable = &pDM_Odm->DM_FatTable;
\r
1854 //#if (DM_ODM_SUPPORT_TYPE == ODM_AP)
\r
1855 if(*pDM_Odm->pBandType == ODM_BAND_5G )
\r
1857 if(pDM_FatTable->idx_AntDiv_counter_5G < pDM_Odm->antdiv_period )
\r
1859 pDM_FatTable->idx_AntDiv_counter_5G++;
\r
1863 pDM_FatTable->idx_AntDiv_counter_5G=0;
\r
1865 else if(*pDM_Odm->pBandType == ODM_BAND_2_4G )
\r
1867 if(pDM_FatTable->idx_AntDiv_counter_2G < pDM_Odm->antdiv_period )
\r
1869 pDM_FatTable->idx_AntDiv_counter_2G++;
\r
1873 pDM_FatTable->idx_AntDiv_counter_2G=0;
\r
1877 if(!(pDM_Odm->SupportAbility & ODM_BB_ANT_DIV))
\r
1879 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV,ODM_DBG_LOUD,("[Return!!!] Not Support Antenna Diversity Function\n"));
\r
1884 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
\r
1885 if(pAdapter->MgntInfo.AntennaTest)
\r
1889 #if (BEAMFORMING_SUPPORT == 1)
\r
1890 BEAMFORMING_CAP BeamformCap = (pAdapter->MgntInfo.BeamformingInfo.BeamformCap);
\r
1892 if( BeamformCap & BEAMFORMEE_CAP ) // BFmee On && Div On -> Div Off
\r
1894 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV,ODM_DBG_LOUD,("[ AntDiv : OFF ] BFmee ==1 \n"));
\r
1895 if(pDM_Odm->SupportAbility & ODM_BB_ANT_DIV)
\r
1897 odm_AntDiv_on_off(pDM_Odm, ANTDIV_OFF);
\r
1898 pDM_Odm->SupportAbility &= ~(ODM_BB_ANT_DIV);
\r
1902 else // BFmee Off && Div Off -> Div On
\r
1905 if(!(pDM_Odm->SupportAbility & ODM_BB_ANT_DIV) && pDM_Odm->bLinked)
\r
1907 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV,ODM_DBG_LOUD,("[ AntDiv : ON ] BFmee ==0 \n"));
\r
1908 if((pDM_Odm->AntDivType!=S0S1_SW_ANTDIV) )
\r
1909 odm_AntDiv_on_off(pDM_Odm, ANTDIV_ON);
\r
1911 pDM_Odm->SupportAbility |= (ODM_BB_ANT_DIV);
\r
1918 #if (DM_ODM_SUPPORT_TYPE == ODM_AP)
\r
1919 if(pDM_FatTable->AntDiv_2G_5G == ODM_ANTDIV_2G)
\r
1921 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV,ODM_DBG_LOUD,("[ 2G AntDiv Running ]\n"));
\r
1922 if(!(pDM_Odm->SupportICType & ODM_ANTDIV_2G_SUPPORT_IC))
\r
1925 else if(pDM_FatTable->AntDiv_2G_5G == ODM_ANTDIV_5G)
\r
1927 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV,ODM_DBG_LOUD,("[ 5G AntDiv Running ]\n"));
\r
1928 if(!(pDM_Odm->SupportICType & ODM_ANTDIV_5G_SUPPORT_IC))
\r
1931 else if(pDM_FatTable->AntDiv_2G_5G == (ODM_ANTDIV_2G|ODM_ANTDIV_5G))
\r
1933 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV,ODM_DBG_LOUD,("[ 2G & 5G AntDiv Running ]\n"));
\r
1939 if (pDM_Odm->antdiv_select==1)
\r
1940 pDM_Odm->AntType = ODM_FIX_MAIN_ANT;
\r
1941 else if (pDM_Odm->antdiv_select==2)
\r
1942 pDM_Odm->AntType = ODM_FIX_AUX_ANT;
\r
1943 else if (pDM_Odm->antdiv_select==0)
\r
1944 pDM_Odm->AntType = ODM_AUTO_ANT;
\r
1946 //ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV,ODM_DBG_LOUD,("AntType= (( %d )) , pre_AntType= (( %d )) \n",pDM_Odm->AntType,pDM_Odm->pre_AntType));
\r
1948 if(pDM_Odm->AntType != ODM_AUTO_ANT)
\r
1950 ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Fix Antenna at (( %s ))\n",(pDM_Odm->AntType == ODM_FIX_MAIN_ANT)?"MAIN":"AUX"));
\r
1952 if(pDM_Odm->AntType != pDM_Odm->pre_AntType)
\r
1954 odm_AntDiv_on_off(pDM_Odm, ANTDIV_OFF);
\r
1956 if(pDM_Odm->SupportICType & ODM_N_ANTDIV_SUPPORT)
\r
1957 ODM_SetBBReg(pDM_Odm, 0x80c , BIT21, 0);
\r
1958 else if(pDM_Odm->SupportICType & ODM_AC_ANTDIV_SUPPORT)
\r
1959 ODM_SetBBReg(pDM_Odm, 0x900 , BIT18, 0);
\r
1961 if(pDM_Odm->AntType == ODM_FIX_MAIN_ANT)
\r
1962 ODM_UpdateRxIdleAnt(pDM_Odm, MAIN_ANT);
\r
1963 else if(pDM_Odm->AntType == ODM_FIX_AUX_ANT)
\r
1964 ODM_UpdateRxIdleAnt(pDM_Odm, AUX_ANT);
\r
1966 pDM_Odm->pre_AntType=pDM_Odm->AntType;
\r
1971 if(pDM_Odm->AntType != pDM_Odm->pre_AntType)
\r
1973 odm_AntDiv_on_off(pDM_Odm, ANTDIV_ON);
\r
1974 if(pDM_Odm->SupportICType & ODM_N_ANTDIV_SUPPORT)
\r
1975 ODM_SetBBReg(pDM_Odm, 0x80c , BIT21, 1);
\r
1976 else if(pDM_Odm->SupportICType & ODM_AC_ANTDIV_SUPPORT)
\r
1977 ODM_SetBBReg(pDM_Odm, 0x900 , BIT18, 1);
\r
1979 pDM_Odm->pre_AntType=pDM_Odm->AntType;
\r
1983 //3 -----------------------------------------------------------------------------------------------------------
\r
1985 if(pDM_Odm->SupportICType == ODM_RTL8188E)
\r
1987 #if (RTL8188E_SUPPORT == 1)
\r
1988 if(pDM_Odm->AntDivType==CG_TRX_HW_ANTDIV ||pDM_Odm->AntDivType==CGCS_RX_HW_ANTDIV)
\r
1989 odm_HW_AntDiv(pDM_Odm);
\r
1990 #if (!(DM_ODM_SUPPORT_TYPE == ODM_CE))
\r
1991 else if (pDM_Odm->AntDivType==CG_TRX_SMART_ANTDIV)
\r
1992 odm_FastAntTraining(pDM_Odm);
\r
1997 #if (RTL8192E_SUPPORT == 1)
\r
1998 else if(pDM_Odm->SupportICType == ODM_RTL8192E)
\r
2000 if(pDM_Odm->AntDivType==CGCS_RX_HW_ANTDIV)
\r
2001 odm_HW_AntDiv(pDM_Odm);
\r
2002 #if (!(DM_ODM_SUPPORT_TYPE == ODM_CE))
\r
2003 else if (pDM_Odm->AntDivType==CG_TRX_SMART_ANTDIV)
\r
2004 odm_FastAntTraining(pDM_Odm);
\r
2009 #if (RTL8723B_SUPPORT == 1)
\r
2011 else if(pDM_Odm->SupportICType == ODM_RTL8723B)
\r
2013 if (pDM_Odm->AntDivType==S0S1_SW_ANTDIV)
\r
2014 odm_S0S1_SwAntDiv(pDM_Odm, SWAW_STEP_PEAK);
\r
2015 else if (pDM_Odm->AntDivType==CG_TRX_HW_ANTDIV)
\r
2016 odm_HW_AntDiv(pDM_Odm);
\r
2021 #if (RTL8821A_SUPPORT == 1)
\r
2022 else if(pDM_Odm->SupportICType == ODM_RTL8821)
\r
2024 if(!pDM_Odm->bBtEnabled) //BT disabled
\r
2026 if(pDM_Odm->AntDivType == S0S1_SW_ANTDIV)
\r
2028 pDM_Odm->AntDivType=CG_TRX_HW_ANTDIV;
\r
2029 ODM_SetBBReg(pDM_Odm, 0x8D4 , BIT24, 1);
\r
2034 if(pDM_Odm->AntDivType == CG_TRX_HW_ANTDIV)
\r
2036 pDM_Odm->AntDivType=S0S1_SW_ANTDIV;
\r
2037 ODM_SetBBReg(pDM_Odm, 0x8D4 , BIT24, 0);
\r
2041 if (pDM_Odm->AntDivType==S0S1_SW_ANTDIV)
\r
2042 odm_S0S1_SwAntDiv(pDM_Odm, SWAW_STEP_PEAK);
\r
2043 else if (pDM_Odm->AntDivType==CG_TRX_HW_ANTDIV)
\r
2044 odm_HW_AntDiv(pDM_Odm);
\r
2048 #if (RTL8881A_SUPPORT == 1)
\r
2049 else if(pDM_Odm->SupportICType == ODM_RTL8881A)
\r
2050 odm_HW_AntDiv(pDM_Odm);
\r
2053 #if (RTL8812A_SUPPORT == 1)
\r
2054 else if(pDM_Odm->SupportICType == ODM_RTL8812)
\r
2055 odm_HW_AntDiv(pDM_Odm);
\r
2061 odm_AntselStatistics(
\r
2062 IN PDM_ODM_T pDM_Odm,
\r
2063 IN u1Byte antsel_tr_mux,
\r
2065 IN u4Byte RxPWDBAll
\r
2068 pFAT_T pDM_FatTable = &pDM_Odm->DM_FatTable;
\r
2070 if(antsel_tr_mux == ANT1_2G)
\r
2072 pDM_FatTable->MainAnt_Sum[MacId]+=RxPWDBAll;
\r
2073 pDM_FatTable->MainAnt_Cnt[MacId]++;
\r
2077 pDM_FatTable->AuxAnt_Sum[MacId]+=RxPWDBAll;
\r
2078 pDM_FatTable->AuxAnt_Cnt[MacId]++;
\r
2084 ODM_Process_RSSIForAntDiv(
\r
2085 IN OUT PDM_ODM_T pDM_Odm,
\r
2086 IN PODM_PHY_INFO_T pPhyInfo,
\r
2087 IN PODM_PACKET_INFO_T pPktinfo
\r
2090 u1Byte isCCKrate=0,CCKMaxRate=DESC_RATE11M;
\r
2091 pFAT_T pDM_FatTable = &pDM_Odm->DM_FatTable;
\r
2093 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN))
\r
2094 u4Byte RxPower_Ant0, RxPower_Ant1;
\r
2096 u1Byte RxPower_Ant0, RxPower_Ant1;
\r
2099 if(pDM_Odm->SupportICType & ODM_N_ANTDIV_SUPPORT)
\r
2100 CCKMaxRate=DESC_RATE11M;
\r
2101 else if(pDM_Odm->SupportICType & ODM_AC_ANTDIV_SUPPORT)
\r
2102 CCKMaxRate=DESC_RATE11M;
\r
2103 isCCKrate = (pPktinfo->DataRate <= CCKMaxRate)?TRUE:FALSE;
\r
2105 #if ((RTL8192C_SUPPORT == 1) ||(RTL8192D_SUPPORT == 1))
\r
2106 if(pDM_Odm->SupportICType & ODM_RTL8192C|ODM_RTL8192D)
\r
2108 if(pPktinfo->bPacketToSelf || pPktinfo->bPacketBeacon)
\r
2110 //if(pPktinfo->bPacketBeacon)
\r
2112 // DbgPrint("This is beacon, isCCKrate=%d\n", isCCKrate);
\r
2114 ODM_AntselStatistics_88C(pDM_Odm, pPktinfo->StationID, pPhyInfo->RxPWDBAll, isCCKrate);
\r
2119 if( (pDM_Odm->SupportICType == ODM_RTL8192E||pDM_Odm->SupportICType == ODM_RTL8812) && (pPktinfo->DataRate > CCKMaxRate) )
\r
2121 RxPower_Ant0 = pPhyInfo->RxMIMOSignalStrength[0];
\r
2122 RxPower_Ant1= pPhyInfo->RxMIMOSignalStrength[1];
\r
2125 RxPower_Ant0=pPhyInfo->RxPWDBAll;
\r
2127 if(pDM_Odm->AntDivType == CG_TRX_SMART_ANTDIV)
\r
2129 if( (pDM_Odm->SupportICType & ODM_SMART_ANT_SUPPORT) && pPktinfo->bPacketToSelf && pDM_FatTable->FAT_State == FAT_TRAINING_STATE )//(pPktinfo->bPacketMatchBSSID && (!pPktinfo->bPacketBeacon))
\r
2131 u1Byte antsel_tr_mux;
\r
2132 antsel_tr_mux = (pDM_FatTable->antsel_rx_keep_2<<2) |(pDM_FatTable->antsel_rx_keep_1 <<1) |pDM_FatTable->antsel_rx_keep_0;
\r
2133 pDM_FatTable->antSumRSSI[antsel_tr_mux] += RxPower_Ant0;
\r
2134 pDM_FatTable->antRSSIcnt[antsel_tr_mux]++;
\r
2137 else //AntDivType != CG_TRX_SMART_ANTDIV
\r
2139 if( ( pDM_Odm->SupportICType & ODM_ANTDIV_SUPPORT ) && (pPktinfo->bPacketToSelf || pPktinfo->bPacketMatchBSSID) )
\r
2141 if(pDM_Odm->SupportICType == ODM_RTL8188E || pDM_Odm->SupportICType == ODM_RTL8192E)
\r
2142 odm_AntselStatistics(pDM_Odm, pDM_FatTable->antsel_rx_keep_0, pPktinfo->StationID,RxPower_Ant0);
\r
2143 else// SupportICType == ODM_RTL8821 and ODM_RTL8723B and ODM_RTL8812)
\r
2145 if(isCCKrate && (pDM_Odm->AntDivType == S0S1_SW_ANTDIV))
\r
2147 pDM_FatTable->antsel_rx_keep_0 = (pDM_FatTable->RxIdleAnt == MAIN_ANT) ? ANT1_2G : ANT2_2G;
\r
2150 if(pDM_FatTable->antsel_rx_keep_0==ANT1_2G)
\r
2151 pDM_FatTable->CCK_counter_main++;
\r
2152 else// if(pDM_FatTable->antsel_rx_keep_0==ANT2_2G)
\r
2153 pDM_FatTable->CCK_counter_aux++;
\r
2155 odm_AntselStatistics(pDM_Odm, pDM_FatTable->antsel_rx_keep_0, pPktinfo->StationID, RxPower_Ant0);
\r
2160 if(pDM_FatTable->antsel_rx_keep_0==ANT1_2G)
\r
2161 pDM_FatTable->OFDM_counter_main++;
\r
2162 else// if(pDM_FatTable->antsel_rx_keep_0==ANT2_2G)
\r
2163 pDM_FatTable->OFDM_counter_aux++;
\r
2164 odm_AntselStatistics(pDM_Odm, pDM_FatTable->antsel_rx_keep_0, pPktinfo->StationID, RxPower_Ant0);
\r
2169 //ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD,("isCCKrate=%d, PWDB_ALL=%d\n",isCCKrate, pPhyInfo->RxPWDBAll));
\r
2170 //ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD,("antsel_tr_mux=3'b%d%d%d\n",pDM_FatTable->antsel_rx_keep_2, pDM_FatTable->antsel_rx_keep_1, pDM_FatTable->antsel_rx_keep_0));
\r
2173 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE))
\r
2175 ODM_SetTxAntByTxInfo(
\r
2176 IN PDM_ODM_T pDM_Odm,
\r
2181 pFAT_T pDM_FatTable = &pDM_Odm->DM_FatTable;
\r
2183 if(!(pDM_Odm->SupportAbility & ODM_BB_ANT_DIV))
\r
2186 if(pDM_Odm->AntDivType==CGCS_RX_HW_ANTDIV)
\r
2190 if(pDM_Odm->SupportICType == ODM_RTL8723B)
\r
2192 #if (RTL8723B_SUPPORT == 1)
\r
2193 SET_TX_DESC_ANTSEL_A_8723B(pDesc, pDM_FatTable->antsel_a[macId]);
\r
2194 //ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[8723B] SetTxAntByTxInfo_WIN: MacID=%d, antsel_tr_mux=3'b%d%d%d\n",
\r
2195 //macId, pDM_FatTable->antsel_c[macId], pDM_FatTable->antsel_b[macId], pDM_FatTable->antsel_a[macId]));
\r
2198 else if(pDM_Odm->SupportICType == ODM_RTL8821)
\r
2200 #if (RTL8821A_SUPPORT == 1)
\r
2201 SET_TX_DESC_ANTSEL_A_8812(pDesc, pDM_FatTable->antsel_a[macId]);
\r
2202 //ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[8821A] SetTxAntByTxInfo_WIN: MacID=%d, antsel_tr_mux=3'b%d%d%d\n",
\r
2203 //macId, pDM_FatTable->antsel_c[macId], pDM_FatTable->antsel_b[macId], pDM_FatTable->antsel_a[macId]));
\r
2206 else if(pDM_Odm->SupportICType == ODM_RTL8188E)
\r
2208 #if (RTL8188E_SUPPORT == 1)
\r
2209 SET_TX_DESC_ANTSEL_A_88E(pDesc, pDM_FatTable->antsel_a[macId]);
\r
2210 SET_TX_DESC_ANTSEL_B_88E(pDesc, pDM_FatTable->antsel_b[macId]);
\r
2211 SET_TX_DESC_ANTSEL_C_88E(pDesc, pDM_FatTable->antsel_c[macId]);
\r
2212 //ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[8188E] SetTxAntByTxInfo_WIN: MacID=%d, antsel_tr_mux=3'b%d%d%d\n",
\r
2213 //macId, pDM_FatTable->antsel_c[macId], pDM_FatTable->antsel_b[macId], pDM_FatTable->antsel_a[macId]));
\r
2216 else if(pDM_Odm->SupportICType == ODM_RTL8192E)
\r
2222 #else// (DM_ODM_SUPPORT_TYPE == ODM_AP)
\r
2225 ODM_SetTxAntByTxInfo(
\r
2226 //IN PDM_ODM_T pDM_Odm,
\r
2227 struct rtl8192cd_priv *priv,
\r
2228 struct tx_desc *pdesc,
\r
2229 struct tx_insn *txcfg,
\r
2230 unsigned short aid
\r
2233 pFAT_T pDM_FatTable = &priv->pshare->_dmODM.DM_FatTable;
\r
2234 u4Byte SupportICType=priv->pshare->_dmODM.SupportICType;
\r
2236 if(SupportICType == ODM_RTL8881A)
\r
2238 //panic_printk("[%s] [%d] ******ODM_SetTxAntByTxInfo_8881E****** \n",__FUNCTION__,__LINE__);
\r
2239 pdesc->Dword6 &= set_desc(~ (BIT(18)|BIT(17)|BIT(16)));
\r
2240 pdesc->Dword6 |= set_desc(pDM_FatTable->antsel_a[aid]<<16);
\r
2242 else if(SupportICType == ODM_RTL8192E)
\r
2244 //panic_printk("[%s] [%d] ******ODM_SetTxAntByTxInfo_8192E****** \n",__FUNCTION__,__LINE__);
\r
2245 pdesc->Dword6 &= set_desc(~ (BIT(18)|BIT(17)|BIT(16)));
\r
2246 pdesc->Dword6 |= set_desc(pDM_FatTable->antsel_a[aid]<<16);
\r
2248 else if(SupportICType == ODM_RTL8812)
\r
2251 //panic_printk("[%s] [%d] ******ODM_SetTxAntByTxInfo_8881E****** \n",__FUNCTION__,__LINE__);
\r
2253 pdesc->Dword6 &= set_desc(~ BIT(16));
\r
2254 pdesc->Dword6 &= set_desc(~ BIT(17));
\r
2255 pdesc->Dword6 &= set_desc(~ BIT(18));
\r
2258 pdesc->Dword6 |= set_desc(pDM_FatTable->antsel_a[aid]<<16);
\r
2259 pdesc->Dword6 |= set_desc(pDM_FatTable->antsel_b[aid]<<17);
\r
2260 pdesc->Dword6 |= set_desc(pDM_FatTable->antsel_c[aid]<<18);
\r
2268 VOID ODM_AntDivInit( IN PDM_ODM_T pDM_Odm ){}
\r
2269 VOID ODM_AntDiv( IN PDM_ODM_T pDM_Odm){}
\r
2271 #endif //#if (defined(CONFIG_HW_ANTENNA_DIVERSITY))
\r