8fba8a264529336231d44dee66527bf1d38a1ce3
[firefly-linux-kernel-4.4.55.git] / drivers / net / wireless / rockchip_wlan / rtl8723bu / hal / OUTSRC / odm_EdcaTurboCheck.h
1 /******************************************************************************\r
2  *\r
3  * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.\r
4  *                                        \r
5  * This program is free software; you can redistribute it and/or modify it\r
6  * under the terms of version 2 of the GNU General Public License as\r
7  * published by the Free Software Foundation.\r
8  *\r
9  * This program is distributed in the hope that it will be useful, but WITHOUT\r
10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\r
11  * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\r
12  * more details.\r
13  *\r
14  * You should have received a copy of the GNU General Public License along with\r
15  * this program; if not, write to the Free Software Foundation, Inc.,\r
16  * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA\r
17  *\r
18  *\r
19  ******************************************************************************/\r
20  \r
21 #ifndef __ODMEDCATURBOCHECK_H__\r
22 #define    __ODMEDCATURBOCHECK_H__\r
23 \r
24 typedef struct _EDCA_TURBO_\r
25 {\r
26         BOOLEAN bCurrentTurboEDCA;\r
27         BOOLEAN bIsCurRDLState;\r
28 \r
29         #if(DM_ODM_SUPPORT_TYPE == ODM_CE       )\r
30         u4Byte  prv_traffic_idx; // edca turbo\r
31         #endif\r
32 \r
33 }EDCA_T,*pEDCA_T;\r
34 \r
35 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE))\r
36 static u4Byte edca_setting_UL[HT_IOT_PEER_MAX] = \r
37 // UNKNOWN              REALTEK_90      REALTEK_92SE    BROADCOM                RALINK          ATHEROS         CISCO           MERU        MARVELL     92U_AP          SELF_AP(DownLink/Tx)\r
38 { 0x5e4322,             0xa44f,                 0x5e4322,               0x5ea32b,               0x5ea422,       0x5ea322,       0x3ea430,       0x5ea42b, 0x5ea44f,     0x5e4322,       0x5e4322};\r
39 \r
40 \r
41 static u4Byte edca_setting_DL[HT_IOT_PEER_MAX] = \r
42 // UNKNOWN              REALTEK_90      REALTEK_92SE    BROADCOM                RALINK          ATHEROS         CISCO           MERU,       MARVELL     92U_AP          SELF_AP(UpLink/Rx)\r
43 { 0xa44f,               0x5ea44f,       0x5e4322,               0x5ea42b,               0xa44f,                 0xa630,                 0x5ea630,       0x5ea42b, 0xa44f,               0xa42b,         0xa42b};\r
44 \r
45 static u4Byte edca_setting_DL_GMode[HT_IOT_PEER_MAX] = \r
46 // UNKNOWN              REALTEK_90      REALTEK_92SE    BROADCOM                RALINK          ATHEROS         CISCO           MERU,       MARVELL     92U_AP          SELF_AP\r
47 { 0x4322,               0xa44f,                 0x5e4322,               0xa42b,                         0x5e4322,       0x4322,                 0xa42b,         0x5ea42b, 0xa44f,               0x5e4322,       0x5ea42b};\r
48 \r
49 \r
50 //============================================================\r
51 // EDCA Paramter for AP/ADSL   by Mingzhi 2011-11-22\r
52 //============================================================\r
53 #elif (DM_ODM_SUPPORT_TYPE &ODM_ADSL)\r
54 enum qos_prio { BK, BE, VI, VO, VI_AG, VO_AG };\r
55 \r
56 static const struct ParaRecord rtl_ap_EDCA[] =\r
57 {\r
58 //ACM,AIFSN, ECWmin, ECWmax, TXOplimit\r
59      {0,     7,      4,      10,     0},            //BK\r
60      {0,     3,      4,      6,      0},             //BE\r
61      {0,     1,      3,      4,      188},         //VI\r
62      {0,     1,      2,      3,      102},         //VO\r
63      {0,     1,      3,      4,      94},          //VI_AG\r
64      {0,     1,      2,      3,      47},          //VO_AG\r
65 };\r
66 \r
67 static const struct ParaRecord rtl_sta_EDCA[] =\r
68 {\r
69 //ACM,AIFSN, ECWmin, ECWmax, TXOplimit\r
70      {0,     7,      4,      10,     0},\r
71      {0,     3,      4,      10,     0},\r
72      {0,     2,      3,      4,      188},\r
73      {0,     2,      2,      3,      102},\r
74      {0,     2,      3,      4,      94},\r
75      {0,     2,      2,      3,      47},\r
76 };\r
77 #endif\r
78 \r
79 \r
80 #if(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL))\r
81 #ifdef WIFI_WMM\r
82 VOID\r
83 ODM_IotEdcaSwitch(\r
84         IN              PVOID                                   pDM_VOID,\r
85         IN      unsigned char           enable\r
86         );\r
87 #endif\r
88 \r
89 BOOLEAN\r
90 ODM_ChooseIotMainSTA(\r
91         IN              PVOID                                   pDM_VOID,\r
92         IN      PSTA_INFO_T             pstat\r
93         );\r
94 #endif\r
95 \r
96 VOID\r
97 odm_EdcaTurboCheck(\r
98         IN      PVOID           pDM_VOID\r
99         );\r
100 VOID\r
101 ODM_EdcaTurboInit(\r
102         IN      PVOID           pDM_VOID\r
103 );\r
104 \r
105 #if(DM_ODM_SUPPORT_TYPE==ODM_WIN)\r
106 VOID\r
107 odm_EdcaTurboCheckMP(\r
108         IN      PVOID           pDM_VOID\r
109         );\r
110 \r
111 //check if edca turbo is disabled\r
112 BOOLEAN\r
113 odm_IsEdcaTurboDisable(\r
114         IN      PVOID           pDM_VOID\r
115 );\r
116 //choose edca paramter for special IOT case\r
117 VOID \r
118 ODM_EdcaParaSelByIot(\r
119         IN              PVOID                                   pDM_VOID,\r
120         OUT     u4Byte          *EDCA_BE_UL,\r
121         OUT u4Byte              *EDCA_BE_DL\r
122         );\r
123 //check if it is UL or DL\r
124 VOID\r
125 odm_EdcaChooseTrafficIdx( \r
126         IN      PVOID           pDM_VOID,\r
127         IN      u8Byte                          cur_tx_bytes,  \r
128         IN      u8Byte                          cur_rx_bytes, \r
129         IN      BOOLEAN                 bBiasOnRx,\r
130         OUT BOOLEAN             *pbIsCurRDLState\r
131         );\r
132 \r
133 #elif (DM_ODM_SUPPORT_TYPE==ODM_CE)\r
134 VOID\r
135 odm_EdcaTurboCheckCE(\r
136         IN      PVOID           pDM_VOID\r
137         );\r
138 #else\r
139 VOID \r
140 odm_IotEngine(\r
141         IN      PVOID           pDM_VOID\r
142         );\r
143 \r
144 VOID\r
145 odm_EdcaParaInit(\r
146         IN      PVOID           pDM_VOID\r
147         );\r
148 #endif\r
149 \r
150 #endif\r