1 /******************************************************************************
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3 * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
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5 * This program is free software; you can redistribute it and/or modify it
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6 * under the terms of version 2 of the GNU General Public License as
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7 * published by the Free Software Foundation.
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9 * This program is distributed in the hope that it will be useful, but WITHOUT
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10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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14 * You should have received a copy of the GNU General Public License along with
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15 * this program; if not, write to the Free Software Foundation, Inc.,
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16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
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19 ******************************************************************************/
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22 #ifndef __HALDMOUTSRC_H__
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23 #define __HALDMOUTSRC_H__
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25 //============================================================
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27 //============================================================
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28 #include "phydm_DIG.h"
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29 #include "phydm_EdcaTurboCheck.h"
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30 #include "phydm_PathDiv.h"
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31 #include "phydm_DynamicBBPowerSaving.h"
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32 #include "phydm_RaInfo.h"
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33 #include "phydm_DynamicTxPower.h"
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34 #include "phydm_CfoTracking.h"
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35 #include "phydm_ACS.h"
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36 #include "phydm_PowerTracking.h"
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37 #include "PhyDM_Adaptivity.h"
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38 #include "phydm_NoiseMonitor.h"
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39 #if(DM_ODM_SUPPORT_TYPE & (ODM_WIN))
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40 #include "phydm_RXHP.h"
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43 //============================================================
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45 //============================================================
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47 // 2011/09/22 MH Define all team supprt ability.
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51 // 2011/09/22 MH Define for all teams. Please Define the constan in your precomp header.
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53 //#define DM_ODM_SUPPORT_AP 0
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54 //#define DM_ODM_SUPPORT_ADSL 0
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55 //#define DM_ODM_SUPPORT_CE 0
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56 //#define DM_ODM_SUPPORT_MP 1
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59 // 2011/09/28 MH Define ODM SW team support flag.
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65 // Antenna Switch Relative Definition.
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70 // Add new function SwAntDivCheck8192C().
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71 // This is the main function of Antenna diversity function before link.
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72 // Mainly, it just retains last scan result and scan again.
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73 // After that, it compares the scan result to see which one gets better RSSI.
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74 // It selects antenna with better receiving power and returns better scan result.
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78 #define TRAFFIC_LOW 0
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79 #define TRAFFIC_HIGH 1
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83 //============================================================
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84 //3 Tx Power Tracking
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85 //3============================================================
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88 //============================================================
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90 //3============================================================
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92 #define AFH_PSD 1 //0:normal PSD scan, 1: only do 20 pts PSD
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93 #define MODE_40M 0 //0:20M, 1:40M
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95 #define PSD_CHMIN 20 // Minimum channel number for BT AFH
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96 #define SIR_STEP_SIZE 3
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97 #define Smooth_Size_1 5
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98 #define Smooth_TH_1 3
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99 #define Smooth_Size_2 10
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100 #define Smooth_TH_2 4
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101 #define Smooth_Size_3 20
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102 #define Smooth_TH_3 4
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103 #define Smooth_Step_Size 5
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104 #define Adaptive_SIR 1
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105 #if(RTL8723_FPGA_VERIFICATION == 1)
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106 #define PSD_RESCAN 1
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108 #define PSD_RESCAN 4
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110 #define PSD_SCAN_INTERVAL 700 //ms
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114 //8723A High Power IGI Setting
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115 #define DM_DIG_HIGH_PWR_IGI_LOWER_BOUND 0x22
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116 #define DM_DIG_Gmode_HIGH_PWR_IGI_LOWER_BOUND 0x28
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117 #define DM_DIG_HIGH_PWR_THRESHOLD 0x3a
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118 #define DM_DIG_LOW_PWR_THRESHOLD 0x14
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121 #define ANTTESTALL 0x00 //Ant A or B will be Testing
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122 #define ANTTESTA 0x01 //Ant A will be Testing
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123 #define ANTTESTB 0x02 //Ant B will be testing
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125 //for 8723A Ant Definition--2012--06--07 due to different IC may be different ANT define
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126 #define MAIN_ANT 1 //Ant A or Ant Main
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127 #define AUX_ANT 2 //AntB or Ant Aux
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128 #define MAX_ANT 3 // 3 for AP using
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131 //Antenna Diversity Type
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132 #define SW_ANTDIV 0
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133 #define HW_ANTDIV 1
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134 //============================================================
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135 // structure and define
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136 //============================================================
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139 // 2011/09/20 MH Add for AP/ADSLpseudo DM structuer requirement.
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140 // We need to remove to other position???
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142 #if(DM_ODM_SUPPORT_TYPE & (ODM_CE|ODM_WIN))
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143 typedef struct rtl8192cd_priv {
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146 }rtl8192cd_priv, *prtl8192cd_priv;
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150 #if(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL))
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151 typedef struct _ADAPTER{
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153 #ifdef AP_BUILD_WORKAROUND
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154 HAL_DATA_TYPE* temp2;
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155 prtl8192cd_priv priv;
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157 }ADAPTER, *PADAPTER;
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160 #if (DM_ODM_SUPPORT_TYPE == ODM_AP)
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162 typedef struct _WLAN_STA{
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164 } WLAN_STA, *PRT_WLAN_STA;
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168 //Remove DIG by Yuchen
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170 //Remoce BB power saving by Yuchn
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172 //Remove DIG by yuchen
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174 typedef struct _Dynamic_Primary_CCA{
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175 u1Byte PriCCA_flag;
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178 u1Byte DupRTS_flag;
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179 u1Byte Monitor_flag;
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182 }Pri_CCA_T, *pPri_CCA_T;
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184 //Remove RA_T,*pRA_T by RS_James
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186 typedef struct _RX_High_Power_
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189 u1Byte PSD_func_trigger;
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190 u1Byte PSD_bitmap_RXHP[80];
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195 BOOLEAN First_time_enter;
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196 BOOLEAN RXHP_enable;
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199 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
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201 RT_WORK_ITEM PSDTimeWorkitem;
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207 #if(DM_ODM_SUPPORT_TYPE & (ODM_CE))
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208 #define ASSOCIATE_ENTRY_NUM 32 // Max size of AsocEntry[].
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209 #define ODM_ASSOCIATE_ENTRY_NUM ASSOCIATE_ENTRY_NUM
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211 #elif(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL))
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212 #define ASSOCIATE_ENTRY_NUM NUM_STAT
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213 #define ODM_ASSOCIATE_ENTRY_NUM ASSOCIATE_ENTRY_NUM+1
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217 // 2012/01/12 MH Revise for compatiable with other SW team.
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218 // 0 is for STA 1-n is for AP clients.
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220 #define ODM_ASSOCIATE_ENTRY_NUM ASSOCIATE_ENTRY_NUM+1// Default port only one
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223 //#ifdef CONFIG_ANTENNA_DIVERSITY
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224 // This indicates two different the steps.
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225 // In SWAW_STEP_PEAK, driver needs to switch antenna and listen to the signal on the air.
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226 // In SWAW_STEP_DETERMINE, driver just compares the signal captured in SWAW_STEP_PEAK
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227 // with original RSSI to determine if it is necessary to switch antenna.
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228 #define SWAW_STEP_PEAK 0
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229 #define SWAW_STEP_DETERMINE 1
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232 #define RSSI_MODE 1
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233 #define TRAFFIC_LOW 0
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234 #define TRAFFIC_HIGH 1
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235 #define TRAFFIC_UltraLOW 2
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237 typedef struct _SW_Antenna_Switch_
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239 u1Byte Double_chk_flag;
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244 u1Byte RSSI_Trying;
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246 u1Byte bTriggerAntennaSwitch;
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247 u1Byte SelectAntennaMap;
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248 u1Byte RSSI_target;
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250 u2Byte Single_Ant_Counter;
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251 u2Byte Dual_Ant_Counter;
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252 u2Byte Aux_FailDetec_Counter;
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253 u2Byte Retry_Counter;
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255 // Before link Antenna Switch check
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256 u1Byte SWAS_NoLink_State;
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257 u4Byte SWAS_NoLink_BK_Reg860;
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258 u4Byte SWAS_NoLink_BK_Reg92c;
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259 u4Byte SWAS_NoLink_BK_Reg948;
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260 BOOLEAN ANTA_ON; //To indicate Ant A is or not
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261 BOOLEAN ANTB_ON; //To indicate Ant B is on or not
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262 BOOLEAN Pre_Aux_FailDetec;
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263 BOOLEAN RSSI_AntDect_bResult;
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272 u8Byte lastTxOkCnt;
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273 u8Byte lastRxOkCnt;
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274 u8Byte TXByteCnt_A;
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275 u8Byte TXByteCnt_B;
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276 u8Byte RXByteCnt_A;
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277 u8Byte RXByteCnt_B;
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278 u1Byte TrafficLoad;
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280 u1Byte Train_time_flag;
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281 RT_TIMER SwAntennaSwitchTimer;
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282 #if (RTL8723B_SUPPORT == 1)||(RTL8821A_SUPPORT == 1)
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283 RT_TIMER SwAntennaSwitchTimer_8723B;
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284 u4Byte PktCnt_SWAntDivByCtrlFrame;
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285 BOOLEAN bSWAntDivByCtrlFrame;
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288 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
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290 RT_WORK_ITEM SwAntennaSwitchWorkitem;
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291 #if (RTL8723B_SUPPORT == 1)||(RTL8821A_SUPPORT == 1)
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292 RT_WORK_ITEM SwAntennaSwitchWorkitem_8723B;
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297 #ifdef CONFIG_SW_ANTENNA_DIVERSITY
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298 _timer SwAntennaSwitchTimer;
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299 u8Byte lastTxOkCnt;
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300 u8Byte lastRxOkCnt;
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301 u8Byte TXByteCnt_A;
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302 u8Byte TXByteCnt_B;
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303 u8Byte RXByteCnt_A;
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304 u8Byte RXByteCnt_B;
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305 u1Byte DoubleComfirm;
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306 u1Byte TrafficLoad;
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307 //SW Antenna Switch
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312 #ifdef CONFIG_HW_ANTENNA_DIVERSITY
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313 //Hybrid Antenna Diversity
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314 u4Byte CCK_Ant1_Cnt[ASSOCIATE_ENTRY_NUM+1];
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315 u4Byte CCK_Ant2_Cnt[ASSOCIATE_ENTRY_NUM+1];
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316 u4Byte OFDM_Ant1_Cnt[ASSOCIATE_ENTRY_NUM+1];
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317 u4Byte OFDM_Ant2_Cnt[ASSOCIATE_ENTRY_NUM+1];
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318 u4Byte RSSI_Ant1_Sum[ASSOCIATE_ENTRY_NUM+1];
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319 u4Byte RSSI_Ant2_Sum[ASSOCIATE_ENTRY_NUM+1];
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320 u1Byte TxAnt[ASSOCIATE_ENTRY_NUM+1];
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330 // Edca Remove by YuChen
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332 //ODM_RATE_ADAPTIVE Remove by RS_James
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335 #if(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL))
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338 #ifdef ADSL_AP_BUILD_WORKAROUND
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339 #define MAX_TOLERANCE 5
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340 #define IQK_DELAY_TIME 1 //ms
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344 // Indicate different AP vendor for IOT issue.
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346 typedef enum _HT_IOT_PEER
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348 HT_IOT_PEER_UNKNOWN = 0,
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349 HT_IOT_PEER_REALTEK = 1,
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350 HT_IOT_PEER_REALTEK_92SE = 2,
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351 HT_IOT_PEER_BROADCOM = 3,
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352 HT_IOT_PEER_RALINK = 4,
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353 HT_IOT_PEER_ATHEROS = 5,
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354 HT_IOT_PEER_CISCO = 6,
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355 HT_IOT_PEER_MERU = 7,
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356 HT_IOT_PEER_MARVELL = 8,
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357 HT_IOT_PEER_REALTEK_SOFTAP = 9,// peer is RealTek SOFT_AP, by Bohn, 2009.12.17
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358 HT_IOT_PEER_SELF_SOFTAP = 10, // Self is SoftAP
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359 HT_IOT_PEER_AIRGO = 11,
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360 HT_IOT_PEER_INTEL = 12,
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361 HT_IOT_PEER_RTK_APCLIENT = 13,
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362 HT_IOT_PEER_REALTEK_81XX = 14,
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363 HT_IOT_PEER_REALTEK_WOW = 15,
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364 HT_IOT_PEER_MAX = 16
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365 }HT_IOT_PEER_E, *PHTIOT_PEER_E;
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366 #endif//#if(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL))
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368 #define DM_Type_ByFW 0
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369 #define DM_Type_ByDriver 1
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372 // Declare for common info
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374 #define MAX_PATH_NUM_92CS 2
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375 #define MAX_PATH_NUM_8188E 1
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376 #define MAX_PATH_NUM_8192E 2
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377 #define MAX_PATH_NUM_8723B 1
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378 #define MAX_PATH_NUM_8812A 2
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379 #define MAX_PATH_NUM_8821A 1
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380 #define MAX_PATH_NUM_8814A 4
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381 #define MAX_PATH_NUM_8822B 2
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384 #define IQK_THRESHOLD 8
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385 #define DPK_THRESHOLD 4
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387 typedef struct _ODM_Phy_Status_Info_
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390 // Be care, if you want to add any element please insert between
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391 // RxPWDBAll & SignalStrength.
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393 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN))
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399 u1Byte SignalQuality; // in 0-100 index.
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400 s1Byte RxMIMOSignalQuality[4]; //per-path's EVM
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401 u1Byte RxMIMOEVMdbm[4]; //per-path's EVM dbm
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403 u1Byte RxMIMOSignalStrength[4];// in 0~100 index
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405 u2Byte Cfo_short[4]; // per-path's Cfo_short
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406 u2Byte Cfo_tail[4]; // per-path's Cfo_tail
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408 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE))
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409 s1Byte RxPower; // in dBm Translate from PWdB
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410 s1Byte RecvSignalPower; // Real power in dBm for this packet, no beautification and aggregation. Keep this raw info to be used for the other procedures.
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411 u1Byte BTRxRSSIPercentage;
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412 u1Byte SignalStrength; // in 0-100 index.
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414 s1Byte RxPwr[4]; //per-path's pwdb
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416 u1Byte RxSNR[4]; //per-path's SNR
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418 u1Byte btCoexPwrAdjust;
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419 }ODM_PHY_INFO_T,*PODM_PHY_INFO_T;
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422 typedef struct _ODM_Per_Pkt_Info_
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427 BOOLEAN bPacketMatchBSSID;
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428 BOOLEAN bPacketToSelf;
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429 BOOLEAN bPacketBeacon;
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431 }ODM_PACKET_INFO_T,*PODM_PACKET_INFO_T;
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434 typedef struct _ODM_Phy_Dbg_Info_
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436 //ODM Write,debug info
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438 u4Byte NumQryPhyStatus;
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439 u4Byte NumQryPhyStatusCCK;
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440 u4Byte NumQryPhyStatusOFDM;
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441 u1Byte NumQryBeaconPkt;
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445 }ODM_PHY_DBG_INFO_T;
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448 typedef struct _ODM_Mac_Status_Info_
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455 typedef enum tag_Dynamic_ODM_Support_Ability_Type
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458 ODM_DIG = 0x00000001,
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459 ODM_HIGH_POWER = 0x00000002,
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460 ODM_CCK_CCA_TH = 0x00000004,
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461 ODM_FA_STATISTICS = 0x00000008,
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462 ODM_RAMASK = 0x00000010,
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463 ODM_RSSI_MONITOR = 0x00000020,
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464 ODM_SW_ANTDIV = 0x00000040,
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465 ODM_HW_ANTDIV = 0x00000080,
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466 ODM_BB_PWRSV = 0x00000100,
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467 ODM_2TPATHDIV = 0x00000200,
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468 ODM_1TPATHDIV = 0x00000400,
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469 ODM_PSD2AFH = 0x00000800
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473 // 2011/20/20 MH For MP driver RT_WLAN_STA = STA_INFO_T
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474 // Please declare below ODM relative info in your STA info structure.
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477 typedef struct _ODM_STA_INFO{
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479 BOOLEAN bUsed; // record the sta status link or not?
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480 //u1Byte WirelessMode; //
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481 u1Byte IOTPeer; // Enum value. HT_IOT_PEER_E
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484 //1 PHY_STATUS_INFO
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485 u1Byte RSSI_Path[4]; //
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491 //1 TX_INFO (may changed by IC)
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492 //TX_INFO_T pTxInfo; // Define in IC folder. Move lower layer.
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494 u1Byte ANTSEL_A; //in Jagar: 4bit; others: 2bit
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495 u1Byte ANTSEL_B; //in Jagar: 4bit; others: 2bit
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496 u1Byte ANTSEL_C; //only in Jagar: 4bit
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497 u1Byte ANTSEL_D; //only in Jagar: 4bit
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498 u1Byte TX_ANTL; //not in Jagar: 2bit
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499 u1Byte TX_ANT_HT; //not in Jagar: 2bit
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500 u1Byte TX_ANT_CCK; //not in Jagar: 2bit
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501 u1Byte TXAGC_A; //not in Jagar: 4bit
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502 u1Byte TXAGC_B; //not in Jagar: 4bit
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503 u1Byte TXPWR_OFFSET; //only in Jagar: 3bit
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504 u1Byte TX_ANT; //only in Jagar: 4bit for TX_ANTL/TX_ANTHT/TX_ANT_CCK
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508 // Please use compile flag to disabe the strcutrue for other IC except 88E.
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509 // Move To lower layer.
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511 // ODM Write Wilson will handle this part(said by Luke.Lee)
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512 //TX_RPT_T pTxRpt; // Define in IC folder. Move lower layer.
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514 //1 For 88E RA (don't redefine the naming)
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517 u1Byte rssi_sta_ra;
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520 u1Byte Decision_rate;
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524 // Driver write Wilson handle.
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525 //1 TX_RPT (don't redefine the naming)
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526 u2Byte RTY[4]; // ???
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527 u2Byte TOTAL; // ???
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528 u2Byte DROP; // ???
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530 // Please use compile flag to disabe the strcutrue for other IC except 88E.
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534 }ODM_STA_INFO_T, *PODM_STA_INFO_T;
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538 // 2011/10/20 MH Define Common info enum for all team.
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540 typedef enum _ODM_Common_Info_Definition
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542 //-------------REMOVED CASE-----------//
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543 //ODM_CMNINFO_CCK_HP,
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544 //ODM_CMNINFO_RFPATH_ENABLE, // Define as ODM write???
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545 //ODM_CMNINFO_BT_COEXIST, // ODM_BT_COEXIST_E
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546 //ODM_CMNINFO_OP_MODE, // ODM_OPERATION_MODE_E
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547 //-------------REMOVED CASE-----------//
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553 //-----------HOOK BEFORE REG INIT-----------//
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554 ODM_CMNINFO_PLATFORM = 0,
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555 ODM_CMNINFO_ABILITY, // ODM_ABILITY_E
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556 ODM_CMNINFO_INTERFACE, // ODM_INTERFACE_E
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557 ODM_CMNINFO_MP_TEST_CHIP,
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558 ODM_CMNINFO_IC_TYPE, // ODM_IC_TYPE_E
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559 ODM_CMNINFO_CUT_VER, // ODM_CUT_VERSION_E
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560 ODM_CMNINFO_FAB_VER, // ODM_FAB_E
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561 ODM_CMNINFO_RF_TYPE, // ODM_RF_PATH_E or ODM_RF_TYPE_E?
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562 ODM_CMNINFO_RFE_TYPE,
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563 ODM_CMNINFO_BOARD_TYPE, // ODM_BOARD_TYPE_E
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564 ODM_CMNINFO_PACKAGE_TYPE,
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565 ODM_CMNINFO_EXT_LNA, // TRUE
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566 ODM_CMNINFO_5G_EXT_LNA,
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567 ODM_CMNINFO_EXT_PA,
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568 ODM_CMNINFO_5G_EXT_PA,
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573 ODM_CMNINFO_EXT_TRSW,
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574 ODM_CMNINFO_PATCH_ID, //CUSTOMER ID
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575 ODM_CMNINFO_BINHCT_TEST,
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576 ODM_CMNINFO_BWIFI_TEST,
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577 ODM_CMNINFO_SMART_CONCURRENT,
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578 ODM_CMNINFO_DOMAIN_CODE_2G,
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579 ODM_CMNINFO_DOMAIN_CODE_5G,
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580 ODM_CMNINFO_IQKFWOFFLOAD,
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581 //-----------HOOK BEFORE REG INIT-----------//
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587 //--------- POINTER REFERENCE-----------//
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588 ODM_CMNINFO_MAC_PHY_MODE, // ODM_MAC_PHY_MODE_E
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589 ODM_CMNINFO_TX_UNI,
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590 ODM_CMNINFO_RX_UNI,
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591 ODM_CMNINFO_WM_MODE, // ODM_WIRELESS_MODE_E
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592 ODM_CMNINFO_BAND, // ODM_BAND_TYPE_E
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593 ODM_CMNINFO_SEC_CHNL_OFFSET, // ODM_SEC_CHNL_OFFSET_E
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594 ODM_CMNINFO_SEC_MODE, // ODM_SECURITY_E
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595 ODM_CMNINFO_BW, // ODM_BW_E
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597 ODM_CMNINFO_FORCED_RATE,
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599 ODM_CMNINFO_DMSP_GET_VALUE,
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600 ODM_CMNINFO_BUDDY_ADAPTOR,
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601 ODM_CMNINFO_DMSP_IS_MASTER,
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603 ODM_CMNINFO_POWER_SAVING,
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604 ODM_CMNINFO_ONE_PATH_CCA, // ODM_CCA_PATH_E
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605 ODM_CMNINFO_DRV_STOP,
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606 ODM_CMNINFO_PNP_IN,
\r
607 ODM_CMNINFO_INIT_ON,
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608 ODM_CMNINFO_ANT_TEST,
\r
609 ODM_CMNINFO_NET_CLOSED,
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610 //ODM_CMNINFO_RTSTA_AID, // For win driver only?
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611 ODM_CMNINFO_FORCED_IGI_LB,
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612 ODM_CMNINFO_P2P_LINK,
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613 ODM_CMNINFO_FCS_MODE,
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614 ODM_CMNINFO_IS1ANTENNA,
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615 ODM_CMNINFO_RFDEFAULTPATH,
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616 //--------- POINTER REFERENCE-----------//
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618 //------------CALL BY VALUE-------------//
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619 ODM_CMNINFO_WIFI_DIRECT,
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620 ODM_CMNINFO_WIFI_DISPLAY,
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621 ODM_CMNINFO_LINK_IN_PROGRESS,
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623 ODM_CMNINFO_STATION_STATE,
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624 ODM_CMNINFO_RSSI_MIN,
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625 ODM_CMNINFO_DBG_COMP, // u8Byte
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626 ODM_CMNINFO_DBG_LEVEL, // u4Byte
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627 ODM_CMNINFO_RA_THRESHOLD_HIGH, // u1Byte
\r
628 ODM_CMNINFO_RA_THRESHOLD_LOW, // u1Byte
\r
629 ODM_CMNINFO_RF_ANTENNA_TYPE, // u1Byte
\r
630 ODM_CMNINFO_BT_ENABLED,
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631 ODM_CMNINFO_BT_HS_CONNECT_PROCESS,
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632 ODM_CMNINFO_BT_HS_RSSI,
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633 ODM_CMNINFO_BT_OPERATION,
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634 ODM_CMNINFO_BT_LIMITED_DIG, //Need to Limited Dig or not
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635 ODM_CMNINFO_BT_DISABLE_EDCA,
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636 #if(DM_ODM_SUPPORT_TYPE & ODM_AP) // for repeater mode add by YuChen 2014.06.
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637 #ifdef UNIVERSAL_REPEATER
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638 ODM_CMNINFO_VXD_LINK,
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642 //------------CALL BY VALUE-------------//
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645 // Dynamic ptr array hook itms.
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647 ODM_CMNINFO_STA_STATUS,
\r
648 ODM_CMNINFO_PHY_STATUS,
\r
649 ODM_CMNINFO_MAC_STATUS,
\r
657 // 2011/10/20 MH Define ODM support ability. ODM_CMNINFO_ABILITY
\r
659 typedef enum _ODM_Support_Ability_Definition
\r
662 // BB ODM section BIT 0-19
\r
665 ODM_BB_RA_MASK = BIT1,
\r
666 ODM_BB_DYNAMIC_TXPWR = BIT2,
\r
667 ODM_BB_FA_CNT = BIT3,
\r
668 ODM_BB_RSSI_MONITOR = BIT4,
\r
669 ODM_BB_CCK_PD = BIT5,
\r
670 ODM_BB_ANT_DIV = BIT6,
\r
671 ODM_BB_PWR_SAVE = BIT7,
\r
672 ODM_BB_PWR_TRAIN = BIT8,
\r
673 ODM_BB_RATE_ADAPTIVE = BIT9,
\r
674 ODM_BB_PATH_DIV = BIT10,
\r
675 ODM_BB_PSD = BIT11,
\r
676 ODM_BB_RXHP = BIT12,
\r
677 ODM_BB_ADAPTIVITY = BIT13,
\r
678 ODM_BB_CFO_TRACKING = BIT14,
\r
679 ODM_BB_NHM_CNT = BIT15,
\r
680 ODM_BB_PRIMARY_CCA = BIT16,
\r
683 // MAC DM section BIT 20-23
\r
685 ODM_MAC_EDCA_TURBO = BIT20,
\r
686 ODM_MAC_EARLY_MODE = BIT21,
\r
689 // RF ODM section BIT 24-31
\r
691 ODM_RF_TX_PWR_TRACK = BIT24,
\r
692 ODM_RF_RX_GAIN_TRACK = BIT25,
\r
693 ODM_RF_CALIBRATION = BIT26,
\r
697 // ODM_CMNINFO_INTERFACE
\r
698 typedef enum tag_ODM_Support_Interface_Definition
\r
700 ODM_ITRF_PCIE = 0x1,
\r
701 ODM_ITRF_USB = 0x2,
\r
702 ODM_ITRF_SDIO = 0x4,
\r
703 ODM_ITRF_ALL = 0x7,
\r
706 // ODM_CMNINFO_IC_TYPE
\r
707 typedef enum tag_ODM_Support_IC_Type_Definition
\r
709 ODM_RTL8192S = BIT0,
\r
710 ODM_RTL8192C = BIT1,
\r
711 ODM_RTL8192D = BIT2,
\r
712 ODM_RTL8723A = BIT3,
\r
713 ODM_RTL8188E = BIT4,
\r
714 ODM_RTL8812 = BIT5,
\r
715 ODM_RTL8821 = BIT6,
\r
716 ODM_RTL8192E = BIT7,
\r
717 ODM_RTL8723B = BIT8,
\r
718 ODM_RTL8814A = BIT9,
\r
719 ODM_RTL8881A = BIT10,
\r
720 ODM_RTL8821B = BIT11,
\r
721 ODM_RTL8822B = BIT12,
\r
722 ODM_RTL8703B = BIT13
\r
725 #define ODM_IC_11N_SERIES (ODM_RTL8192S|ODM_RTL8192C|ODM_RTL8192D|ODM_RTL8723A|ODM_RTL8188E|ODM_RTL8192E|ODM_RTL8723B|ODM_RTL8703B)
\r
726 #define ODM_IC_11AC_SERIES (ODM_RTL8812|ODM_RTL8821|ODM_RTL8814A|ODM_RTL8881A|ODM_RTL8821B|ODM_RTL8822B)
\r
728 #if (DM_ODM_SUPPORT_TYPE == ODM_AP)
\r
730 #ifdef RTK_AC_SUPPORT
\r
731 #define ODM_IC_11AC_SERIES_SUPPORT 1
\r
733 #define ODM_IC_11AC_SERIES_SUPPORT 0
\r
736 #define ODM_IC_11N_SERIES_SUPPORT 1
\r
737 #define ODM_CONFIG_BT_COEXIST 0
\r
739 #elif (DM_ODM_SUPPORT_TYPE == ODM_WIN)
\r
741 #define ODM_IC_11AC_SERIES_SUPPORT 1
\r
742 #define ODM_IC_11N_SERIES_SUPPORT 1
\r
743 #define ODM_CONFIG_BT_COEXIST 1
\r
747 #if((RTL8192C_SUPPORT == 1) || (RTL8192D_SUPPORT == 1) || (RTL8723A_SUPPORT == 1) || (RTL8188E_SUPPORT == 1) ||\
\r
748 (RTL8723B_SUPPORT == 1) || (RTL8192E_SUPPORT == 1) || (RTL8195A_SUPPORT == 1))
\r
749 #define ODM_IC_11N_SERIES_SUPPORT 1
\r
750 #define ODM_IC_11AC_SERIES_SUPPORT 0
\r
752 #define ODM_IC_11N_SERIES_SUPPORT 0
\r
753 #define ODM_IC_11AC_SERIES_SUPPORT 1
\r
756 #ifdef CONFIG_BT_COEXIST
\r
757 #define ODM_CONFIG_BT_COEXIST 1
\r
759 #define ODM_CONFIG_BT_COEXIST 0
\r
765 //ODM_CMNINFO_CUT_VER
\r
766 typedef enum tag_ODM_Cut_Version_Definition
\r
779 }ODM_CUT_VERSION_E;
\r
781 // ODM_CMNINFO_FAB_VER
\r
782 typedef enum tag_ODM_Fab_Version_Definition
\r
788 // ODM_CMNINFO_RF_TYPE
\r
790 // For example 1T2R (A+AB = BIT0|BIT4|BIT5)
\r
792 typedef enum tag_ODM_RF_Path_Bit_Definition
\r
794 ODM_RF_TX_A = BIT0,
\r
795 ODM_RF_TX_B = BIT1,
\r
796 ODM_RF_TX_C = BIT2,
\r
797 ODM_RF_TX_D = BIT3,
\r
798 ODM_RF_RX_A = BIT4,
\r
799 ODM_RF_RX_B = BIT5,
\r
800 ODM_RF_RX_C = BIT6,
\r
801 ODM_RF_RX_D = BIT7,
\r
805 typedef enum tag_ODM_RF_Type_Definition
\r
819 // ODM Dynamic common info value definition
\r
822 //typedef enum _MACPHY_MODE_8192D{
\r
823 // SINGLEMAC_SINGLEPHY,
\r
824 // DUALMAC_DUALPHY,
\r
825 // DUALMAC_SINGLEPHY,
\r
826 //}MACPHY_MODE_8192D,*PMACPHY_MODE_8192D;
\r
827 // Above is the original define in MP driver. Please use the same define. THX.
\r
828 typedef enum tag_ODM_MAC_PHY_Mode_Definition
\r
833 }ODM_MAC_PHY_MODE_E;
\r
836 typedef enum tag_BT_Coexist_Definition
\r
844 // ODM_CMNINFO_OP_MODE
\r
845 typedef enum tag_Operation_Mode_Definition
\r
847 ODM_NO_LINK = BIT0,
\r
850 ODM_POWERSAVE = BIT3,
\r
851 ODM_AP_MODE = BIT4,
\r
852 ODM_CLIENT_MODE = BIT5,
\r
854 ODM_WIFI_DIRECT = BIT7,
\r
855 ODM_WIFI_DISPLAY = BIT8,
\r
856 }ODM_OPERATION_MODE_E;
\r
858 // ODM_CMNINFO_WM_MODE
\r
859 #if (DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_CE))
\r
860 typedef enum tag_Wireless_Mode_Definition
\r
862 ODM_WM_UNKNOW = 0x0,
\r
866 ODM_WM_N24G = BIT3,
\r
868 ODM_WM_AUTO = BIT5,
\r
870 }ODM_WIRELESS_MODE_E;
\r
872 typedef enum tag_Wireless_Mode_Definition
\r
874 ODM_WM_UNKNOWN = 0x00,
\r
878 ODM_WM_AUTO = BIT3,
\r
879 ODM_WM_N24G = BIT4,
\r
881 ODM_WM_AC_5G = BIT6,
\r
882 ODM_WM_AC_24G = BIT7,
\r
883 ODM_WM_AC_ONLY = BIT8,
\r
885 }ODM_WIRELESS_MODE_E;
\r
888 // ODM_CMNINFO_BAND
\r
889 typedef enum tag_Band_Type_Definition
\r
898 // ODM_CMNINFO_SEC_CHNL_OFFSET
\r
899 typedef enum tag_Secondary_Channel_Offset_Definition
\r
904 }ODM_SEC_CHNL_OFFSET_E;
\r
906 // ODM_CMNINFO_SEC_MODE
\r
907 typedef enum tag_Security_Definition
\r
912 ODM_SEC_RESERVE = 3,
\r
913 ODM_SEC_AESCCMP = 4,
\r
914 ODM_SEC_WEP104 = 5,
\r
915 ODM_WEP_WPA_MIXED = 6, // WEP + WPA
\r
920 typedef enum tag_Bandwidth_Definition
\r
930 // ODM_CMNINFO_BOARD_TYPE
\r
931 // For non-AC-series IC , ODM_BOARD_5G_EXT_PA and ODM_BOARD_5G_EXT_LNA are ignored
\r
932 // For AC-series IC, external PA & LNA can be indivisuallly added on 2.4G and/or 5G
\r
933 typedef enum tag_Board_Definition
\r
935 ODM_BOARD_DEFAULT = 0, // The DEFAULT case.
\r
936 ODM_BOARD_MINICARD = BIT(0), // 0 = non-mini card, 1= mini card.
\r
937 ODM_BOARD_SLIM = BIT(1), // 0 = non-slim card, 1 = slim card
\r
938 ODM_BOARD_BT = BIT(2), // 0 = without BT card, 1 = with BT
\r
939 ODM_BOARD_EXT_PA = BIT(3), // 0 = no 2G ext-PA, 1 = existing 2G ext-PA
\r
940 ODM_BOARD_EXT_LNA = BIT(4), // 0 = no 2G ext-LNA, 1 = existing 2G ext-LNA
\r
941 ODM_BOARD_EXT_TRSW = BIT(5), // 0 = no ext-TRSW, 1 = existing ext-TRSW
\r
942 ODM_BOARD_EXT_PA_5G = BIT(6), // 0 = no 5G ext-PA, 1 = existing 5G ext-PA
\r
943 ODM_BOARD_EXT_LNA_5G= BIT(7), // 0 = no 5G ext-LNA, 1 = existing 5G ext-LNA
\r
946 typedef enum tag_ODM_Package_Definition
\r
948 ODM_PACKAGE_DEFAULT = 0,
\r
949 ODM_PACKAGE_QFN68 = BIT(0),
\r
950 ODM_PACKAGE_TFBGA90 = BIT(1),
\r
951 ODM_PACKAGE_TFBGA79 = BIT(2),
\r
952 }ODM_Package_TYPE_E;
\r
954 typedef enum tag_ODM_TYPE_GPA_Definition
\r
957 TYPE_GPA1 = BIT(1)|BIT(0)
\r
960 typedef enum tag_ODM_TYPE_APA_Definition
\r
963 TYPE_APA1 = BIT(1)|BIT(0)
\r
966 typedef enum tag_ODM_TYPE_GLNA_Definition
\r
969 TYPE_GLNA1 = BIT(2)|BIT(0),
\r
970 TYPE_GLNA2 = BIT(3)|BIT(1),
\r
971 TYPE_GLNA3 = BIT(3)|BIT(2)|BIT(1)|BIT(0)
\r
974 typedef enum tag_ODM_TYPE_ALNA_Definition
\r
977 TYPE_ALNA1 = BIT(2)|BIT(0),
\r
978 TYPE_ALNA2 = BIT(3)|BIT(1),
\r
979 TYPE_ALNA3 = BIT(3)|BIT(2)|BIT(1)|BIT(0)
\r
982 // ODM_CMNINFO_ONE_PATH_CCA
\r
983 typedef enum tag_CCA_Path
\r
991 typedef struct _ODM_RA_Info_
\r
998 u1Byte PreRssiStaRA;
\r
1000 u1Byte DecisionRate;
\r
1002 u1Byte HighestRate;
\r
1003 u1Byte LowestRate;
\r
1011 u1Byte RAWaitingCounter;
\r
1012 u1Byte RAPendingCounter;
\r
1013 #if 1 //POWER_TRAINING_ACTIVE == 1 // For compile pass only~!
\r
1014 u1Byte PTActive; // on or off
\r
1015 u1Byte PTTryState; // 0 trying state, 1 for decision state
\r
1016 u1Byte PTStage; // 0~6
\r
1017 u1Byte PTStopCount; //Stop PT counter
\r
1018 u1Byte PTPreRate; // if rate change do PT
\r
1019 u1Byte PTPreRssi; // if RSSI change 5% do PT
\r
1020 u1Byte PTModeSS; // decide whitch rate should do PT
\r
1021 u1Byte RAstage; // StageRA, decide how many times RA will be done between PT
\r
1022 u1Byte PTSmoothFactor;
\r
1024 } ODM_RA_INFO_T,*PODM_RA_INFO_T;
\r
1026 //Remove struct PATHDIV_PARA to odm_PathDiv.h
\r
1028 //move to PowerTracking.h by YuChen
\r
1031 // ODM Dynamic common info value definition
\r
1034 typedef struct _FAST_ANTENNA_TRAINNING_
\r
1037 u1Byte antsel_rx_keep_0;
\r
1038 u1Byte antsel_rx_keep_1;
\r
1039 u1Byte antsel_rx_keep_2;
\r
1040 u1Byte antsel_rx_keep_3;
\r
1041 u4Byte antSumRSSI[7];
\r
1042 u4Byte antRSSIcnt[7];
\r
1043 u4Byte antAveRSSI[7];
\r
1046 u1Byte antsel_a[ODM_ASSOCIATE_ENTRY_NUM];
\r
1047 u1Byte antsel_b[ODM_ASSOCIATE_ENTRY_NUM];
\r
1048 u1Byte antsel_c[ODM_ASSOCIATE_ENTRY_NUM];
\r
1049 u4Byte MainAnt_Sum[ODM_ASSOCIATE_ENTRY_NUM];
\r
1050 u4Byte AuxAnt_Sum[ODM_ASSOCIATE_ENTRY_NUM];
\r
1051 u4Byte MainAnt_Cnt[ODM_ASSOCIATE_ENTRY_NUM];
\r
1052 u4Byte AuxAnt_Cnt[ODM_ASSOCIATE_ENTRY_NUM];
\r
1054 BOOLEAN bBecomeLinked;
\r
1055 u4Byte MinMaxRSSI;
\r
1056 u1Byte idx_AntDiv_counter_2G;
\r
1057 u1Byte idx_AntDiv_counter_5G;
\r
1058 u4Byte AntDiv_2G_5G;
\r
1059 u4Byte CCK_counter_main;
\r
1060 u4Byte CCK_counter_aux;
\r
1061 u4Byte OFDM_counter_main;
\r
1062 u4Byte OFDM_counter_aux;
\r
1065 u4Byte CCK_CtrlFrame_Cnt_main;
\r
1066 u4Byte CCK_CtrlFrame_Cnt_aux;
\r
1067 u4Byte OFDM_CtrlFrame_Cnt_main;
\r
1068 u4Byte OFDM_CtrlFrame_Cnt_aux;
\r
1069 u4Byte MainAnt_CtrlFrame_Sum;
\r
1070 u4Byte AuxAnt_CtrlFrame_Sum;
\r
1071 u4Byte MainAnt_CtrlFrame_Cnt;
\r
1072 u4Byte AuxAnt_CtrlFrame_Cnt;
\r
1076 typedef enum _FAT_STATE
\r
1078 FAT_NORMAL_STATE = 0,
\r
1079 FAT_TRAINING_STATE = 1,
\r
1080 }FAT_STATE_E, *PFAT_STATE_E;
\r
1082 typedef enum _ANT_DIV_TYPE
\r
1084 NO_ANTDIV = 0xFF,
\r
1085 CG_TRX_HW_ANTDIV = 0x01,
\r
1086 CGCS_RX_HW_ANTDIV = 0x02,
\r
1087 FIXED_HW_ANTDIV = 0x03,
\r
1088 CG_TRX_SMART_ANTDIV = 0x04,
\r
1089 CGCS_RX_SW_ANTDIV = 0x05,
\r
1090 S0S1_SW_ANTDIV = 0x06 //8723B intrnal switch S0 S1
\r
1091 }ANT_DIV_TYPE_E, *PANT_DIV_TYPE_E;
\r
1094 typedef struct _ODM_PATH_DIVERSITY_
\r
1096 u1Byte RespTxPath;
\r
1097 u1Byte PathSel[ODM_ASSOCIATE_ENTRY_NUM];
\r
1098 u4Byte PathA_Sum[ODM_ASSOCIATE_ENTRY_NUM];
\r
1099 u4Byte PathB_Sum[ODM_ASSOCIATE_ENTRY_NUM];
\r
1100 u4Byte PathA_Cnt[ODM_ASSOCIATE_ENTRY_NUM];
\r
1101 u4Byte PathB_Cnt[ODM_ASSOCIATE_ENTRY_NUM];
\r
1102 }PATHDIV_T, *pPATHDIV_T;
\r
1105 typedef enum _BASEBAND_CONFIG_PHY_REG_PG_VALUE_TYPE{
\r
1106 PHY_REG_PG_RELATIVE_VALUE = 0,
\r
1107 PHY_REG_PG_EXACT_VALUE = 1
\r
1108 } PHY_REG_PG_TYPE;
\r
1112 // Antenna detection information from single tone mechanism, added by Roger, 2012.11.27.
\r
1114 typedef struct _ANT_DETECTED_INFO{
\r
1115 BOOLEAN bAntDetected;
\r
1119 }ANT_DETECTED_INFO, *PANT_DETECTED_INFO;
\r
1122 // 2011/09/22 MH Copy from SD4 defined structure. We use to support PHY DM integration.
\r
1124 #if(DM_ODM_SUPPORT_TYPE & ODM_WIN)
\r
1125 #if (RT_PLATFORM != PLATFORM_LINUX)
\r
1128 struct DM_Out_Source_Dynamic_Mechanism_Structure
\r
1129 #else// for AP,ADSL,CE Team
\r
1130 typedef struct DM_Out_Source_Dynamic_Mechanism_Structure
\r
1133 //RT_TIMER FastAntTrainingTimer;
\r
1135 // Add for different team use temporarily
\r
1137 PADAPTER Adapter; // For CE/NIC team
\r
1138 prtl8192cd_priv priv; // For AP/ADSL team
\r
1139 // WHen you use Adapter or priv pointer, you must make sure the pointer is ready.
\r
1140 BOOLEAN odm_ready;
\r
1142 #if(DM_ODM_SUPPORT_TYPE & (ODM_CE|ODM_WIN))
\r
1143 rtl8192cd_priv fake_priv;
\r
1145 #if(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL))
\r
1146 // ADSL_AP_BUILD_WORKAROUND
\r
1147 ADAPTER fake_adapter;
\r
1150 PHY_REG_PG_TYPE PhyRegPgValueType;
\r
1151 u1Byte PhyRegPgVersion;
\r
1153 u8Byte DebugComponents;
\r
1154 u4Byte DebugLevel;
\r
1156 u4Byte NumQryPhyStatusAll; //CCK + OFDM
\r
1157 u4Byte LastNumQryPhyStatusAll;
\r
1159 BOOLEAN MPDIG_2G; //off MPDIG
\r
1162 //------ ODM HANDLE, DRIVER NEEDS NOT TO HOOK------//
\r
1163 BOOLEAN bCckHighPower;
\r
1164 u1Byte RFPathRxEnable; // ODM_CMNINFO_RFPATH_ENABLE
\r
1165 u1Byte ControlChannel;
\r
1166 //------ ODM HANDLE, DRIVER NEEDS NOT TO HOOK------//
\r
1168 //--------REMOVED COMMON INFO----------//
\r
1169 //u1Byte PseudoMacPhyMode;
\r
1170 //BOOLEAN *BTCoexist;
\r
1171 //BOOLEAN PseudoBtCoexist;
\r
1173 //BOOLEAN bAPMode;
\r
1174 //BOOLEAN bClientMode;
\r
1175 //BOOLEAN bAdHocMode;
\r
1176 //BOOLEAN bSlaveOfDMSP;
\r
1177 //--------REMOVED COMMON INFO----------//
\r
1180 //1 COMMON INFORMATION
\r
1185 //-----------HOOK BEFORE REG INIT-----------//
\r
1186 // ODM Platform info AP/ADSL/CE/MP = 1/2/3/4
\r
1187 u1Byte SupportPlatform;
\r
1188 // ODM Support Ability DIG/RATR/TX_PWR_TRACK/ ¡K¡K = 1/2/3/¡K
\r
1189 u4Byte SupportAbility;
\r
1190 // ODM PCIE/USB/SDIO = 1/2/3
\r
1191 u1Byte SupportInterface;
\r
1192 // ODM composite or independent. Bit oriented/ 92C+92D+ .... or any other type = 1/2/3/...
\r
1193 u4Byte SupportICType;
\r
1194 // Cut Version TestChip/A-cut/B-cut... = 0/1/2/3/...
\r
1195 u1Byte CutVersion;
\r
1196 // Fab Version TSMC/UMC = 0/1
\r
1197 u1Byte FabVersion;
\r
1198 // RF Type 4T4R/3T3R/2T2R/1T2R/1T1R/...
\r
1201 // Board Type Normal/HighPower/MiniCard/SLIM/Combo/... = 0/1/2/3/4/...
\r
1203 u1Byte PackageType;
\r
1208 // with external LNA NO/Yes = 0/1
\r
1211 // with external PA NO/Yes = 0/1
\r
1214 // with external TRSW NO/Yes = 0/1
\r
1216 u1Byte PatchID; //Customer ID
\r
1217 BOOLEAN bInHctTest;
\r
1218 BOOLEAN bWIFITest;
\r
1220 BOOLEAN bDualMacSmartConcurrent;
\r
1221 u4Byte BK_SupportAbility;
\r
1222 u1Byte AntDivType;
\r
1224 u1Byte odm_Regulation2_4G;
\r
1225 u1Byte odm_Regulation5G;
\r
1226 u1Byte IQKFWOffload;
\r
1227 //-----------HOOK BEFORE REG INIT-----------//
\r
1232 //--------- POINTER REFERENCE-----------//
\r
1234 u1Byte u1Byte_temp;
\r
1235 BOOLEAN BOOLEAN_temp;
\r
1236 PADAPTER PADAPTER_temp;
\r
1238 // MAC PHY Mode SMSP/DMSP/DMDP = 0/1/2
\r
1239 u1Byte *pMacPhyMode;
\r
1240 //TX Unicast byte count
\r
1241 u8Byte *pNumTxBytesUnicast;
\r
1242 //RX Unicast byte count
\r
1243 u8Byte *pNumRxBytesUnicast;
\r
1244 // Wireless mode B/G/A/N = BIT0/BIT1/BIT2/BIT3
\r
1245 u1Byte *pWirelessMode; //ODM_WIRELESS_MODE_E
\r
1246 // Frequence band 2.4G/5G = 0/1
\r
1247 u1Byte *pBandType;
\r
1248 // Secondary channel offset don't_care/below/above = 0/1/2
\r
1249 u1Byte *pSecChOffset;
\r
1250 // Security mode Open/WEP/AES/TKIP = 0/1/2/3
\r
1251 u1Byte *pSecurity;
\r
1252 // BW info 20M/40M/80M = 0/1/2
\r
1253 u1Byte *pBandWidth;
\r
1254 // Central channel location Ch1/Ch2/....
\r
1255 u1Byte *pChannel; //central channel number
\r
1257 // Common info for 92D DMSP
\r
1259 BOOLEAN *pbGetValueFromOtherMac;
\r
1260 PADAPTER *pBuddyAdapter;
\r
1261 BOOLEAN *pbMasterOfDMSP; //MAC0: master, MAC1: slave
\r
1262 // Common info for Status
\r
1263 BOOLEAN *pbScanInProcess;
\r
1264 BOOLEAN *pbPowerSaving;
\r
1265 // CCA Path 2-path/path-A/path-B = 0/1/2; using ODM_CCA_PATH_E.
\r
1266 u1Byte *pOnePathCCA;
\r
1267 //pMgntInfo->AntennaTest
\r
1268 u1Byte *pAntennaTest;
\r
1269 BOOLEAN *pbNet_closed;
\r
1270 //u1Byte *pAidMap;
\r
1271 u1Byte *pu1ForcedIgiLb;
\r
1272 BOOLEAN *pIsFcsModeEnable;
\r
1273 //--------- For 8723B IQK-----------//
\r
1274 BOOLEAN *pIs1Antenna;
\r
1275 u1Byte *pRFDefaultPath;
\r
1278 //--------- POINTER REFERENCE-----------//
\r
1279 pu2Byte pForcedDataRate;
\r
1280 //------------CALL BY VALUE-------------//
\r
1281 BOOLEAN bLinkInProcess;
\r
1282 BOOLEAN bWIFI_Direct;
\r
1283 BOOLEAN bWIFI_Display;
\r
1285 BOOLEAN bsta_state;
\r
1287 u1Byte InterfaceIndex; // Add for 92D dual MAC: 0--Mac0 1--Mac1
\r
1288 BOOLEAN bIsMPChip;
\r
1289 BOOLEAN bOneEntryOnly;
\r
1291 // Common info for BTDM
\r
1292 BOOLEAN bBtEnabled; // BT is enabled
\r
1293 BOOLEAN bBtConnectProcess; // BT HS is under connection progress.
\r
1294 u1Byte btHsRssi; // BT HS mode wifi rssi value.
\r
1295 BOOLEAN bBtHsOperation; // BT HS mode is under progress
\r
1296 BOOLEAN bBtDisableEdcaTurbo; // Under some condition, don't enable the EDCA Turbo
\r
1297 BOOLEAN bBtLimitedDig; // BT is busy.
\r
1298 //------------CALL BY VALUE-------------//
\r
1303 u8Byte RSSI_TRSW;
\r
1304 u8Byte RSSI_TRSW_H;
\r
1305 u8Byte RSSI_TRSW_L;
\r
1306 u8Byte RSSI_TRSW_iso;
\r
1309 BOOLEAN bNoisyState;
\r
1311 u1Byte LinkedInterval;
\r
1312 u1Byte preChannel;
\r
1313 u4Byte TxagcOffsetValueA;
\r
1314 BOOLEAN IsTxagcOffsetPositiveA;
\r
1315 u4Byte TxagcOffsetValueB;
\r
1316 BOOLEAN IsTxagcOffsetPositiveB;
\r
1317 u8Byte lastTxOkCnt;
\r
1318 u8Byte lastRxOkCnt;
\r
1319 u4Byte BbSwingOffsetA;
\r
1320 BOOLEAN IsBbSwingOffsetPositiveA;
\r
1321 u4Byte BbSwingOffsetB;
\r
1322 BOOLEAN IsBbSwingOffsetPositiveB;
\r
1323 s1Byte TH_L2H_ini;
\r
1324 s1Byte TH_EDCCA_HL_diff;
\r
1326 u1Byte IGI_target;
\r
1327 BOOLEAN ForceEDCCA;
\r
1328 u1Byte AdapEn_RSSI;
\r
1329 s1Byte Force_TH_H;
\r
1330 s1Byte Force_TH_L;
\r
1331 u1Byte IGI_LowerBound;
\r
1332 u1Byte antdiv_rssi;
\r
1334 u1Byte pre_AntType;
\r
1335 u1Byte antdiv_period;
\r
1336 u1Byte antdiv_select;
\r
1337 u1Byte NdpaPeriod;
\r
1338 BOOLEAN H2C_RARpt_connect;
\r
1340 // add by Yu Cehn for adaptivtiy
\r
1341 BOOLEAN adaptivity_flag;
\r
1342 u1Byte tolerance_cnt;
\r
1343 u8Byte NHMCurTxOkcnt;
\r
1344 u8Byte NHMCurRxOkcnt;
\r
1345 u8Byte NHMLastTxOkcnt;
\r
1346 u8Byte NHMLastRxOkcnt;
\r
1350 u1Byte Adaptivity_IGI_upper;
\r
1353 BOOLEAN Carrier_Sense_enable;
\r
1354 BOOLEAN bFirstLink;
\r
1356 BOOLEAN EDCCA_enable_state;
\r
1357 BOOLEAN NHM_enable;
\r
1358 BOOLEAN DynamicLinkAdaptivity;
\r
1361 ODM_NOISE_MONITOR noise_level;//[ODM_MAX_CHANNEL_NUM];
\r
1363 //2 Define STA info.
\r
1365 // 2012/01/12 MH For MP, we need to reduce one array pointer for default port.??
\r
1366 PSTA_INFO_T pODM_StaInfo[ODM_ASSOCIATE_ENTRY_NUM];
\r
1368 #if (RATE_ADAPTIVE_SUPPORT == 1)
\r
1369 u2Byte CurrminRptTime;
\r
1370 ODM_RA_INFO_T RAInfo[ODM_ASSOCIATE_ENTRY_NUM]; //See HalMacID support
\r
1373 // 2012/02/14 MH Add to share 88E ra with other SW team.
\r
1374 // We need to colelct all support abilit to a proper area.
\r
1376 BOOLEAN RaSupport88E;
\r
1378 // Define ...........
\r
1380 // Latest packet phy info (ODM write)
\r
1381 ODM_PHY_DBG_INFO_T PhyDbgInfo;
\r
1382 //PHY_INFO_88E PhyInfo;
\r
1384 // Latest packet phy info (ODM write)
\r
1385 ODM_MAC_INFO *pMacInfo;
\r
1386 //MAC_INFO_88E MacInfo;
\r
1388 // Different Team independt structure??
\r
1391 //TX_RTP_CMN TX_retrpo;
\r
1392 //TX_RTP_88E TX_retrpo;
\r
1393 //TX_RTP_8195 TX_retrpo;
\r
1398 FAT_T DM_FatTable;
\r
1399 DIG_T DM_DigTable;
\r
1401 Pri_CCA_T DM_PriCCA;
\r
1402 #if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
\r
1403 RXHP_T DM_RXHP_Table;
\r
1405 RA_T DM_RA_Table;
\r
1406 FALSE_ALARM_STATISTICS FalseAlmCnt;
\r
1407 FALSE_ALARM_STATISTICS FlaseAlmCntBuddyAdapter;
\r
1408 //#ifdef CONFIG_ANTENNA_DIVERSITY
\r
1409 SWAT_T DM_SWAT_Table;
\r
1410 BOOLEAN RSSI_test;
\r
1411 CFO_TRACKING DM_CfoTrack;
\r
1415 #if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
\r
1417 PATHDIV_PARA pathIQK;
\r
1420 EDCA_T DM_EDCA_Table;
\r
1421 u4Byte WMMEDCA_BE;
\r
1422 PATHDIV_T DM_PathDiv;
\r
1423 // Copy from SD4 structure
\r
1425 // ==================================================
\r
1429 //u1Byte DM_Type;
\r
1430 //u1Byte PSD_Report_RXHP[80]; // Add By Gary
\r
1431 //u1Byte PSD_func_flag; // Add By Gary
\r
1433 //u1Byte bDMInitialGainEnable;
\r
1434 //u1Byte binitialized; // for dm_initial_gain_Multi_STA use.
\r
1435 //for Antenna diversity
\r
1436 //u8 AntDivCfg;// 0:OFF , 1:ON, 2:by efuse
\r
1437 //PSTA_INFO_T RSSI_target;
\r
1439 BOOLEAN *pbDriverStopped;
\r
1440 BOOLEAN *pbDriverIsGoingToPnpSetPowerSleep;
\r
1441 BOOLEAN *pinit_adpt_in_progress;
\r
1444 BOOLEAN bUserAssignLevel;
\r
1445 RT_TIMER PSDTimer;
\r
1446 u1Byte RSSI_BT; //come from BT
\r
1447 BOOLEAN bPSDinProcess;
\r
1448 BOOLEAN bPSDactive;
\r
1449 BOOLEAN bDMInitialGainEnable;
\r
1452 RT_TIMER MPT_DIGTimer;
\r
1454 //for rate adaptive, in fact, 88c/92c fw will handle this
\r
1455 u1Byte bUseRAMask;
\r
1457 ODM_RATE_ADAPTIVE RateAdaptive;
\r
1459 ANT_DETECTED_INFO AntDetectedInfo; // Antenna detected information for RSSI tool
\r
1461 ODM_RF_CAL_T RFCalibrateInfo;
\r
1464 // TX power tracking
\r
1466 u1Byte BbSwingIdxOfdm[MAX_RF_PATH];
\r
1467 u1Byte BbSwingIdxOfdmCurrent;
\r
1468 u1Byte BbSwingIdxOfdmBase[MAX_RF_PATH];
\r
1469 BOOLEAN BbSwingFlagOfdm;
\r
1470 u1Byte BbSwingIdxCck;
\r
1471 u1Byte BbSwingIdxCckCurrent;
\r
1472 u1Byte BbSwingIdxCckBase;
\r
1473 u1Byte DefaultOfdmIndex;
\r
1474 u1Byte DefaultCckIndex;
\r
1475 BOOLEAN BbSwingFlagCck;
\r
1477 s1Byte Absolute_OFDMSwingIdx[MAX_RF_PATH];
\r
1478 s1Byte Remnant_OFDMSwingIdx[MAX_RF_PATH];
\r
1479 s1Byte Remnant_CCKSwingIdx;
\r
1480 s1Byte Modify_TxAGC_Value; //Remnat compensate value at TxAGC
\r
1481 BOOLEAN Modify_TxAGC_Flag_PathA;
\r
1482 BOOLEAN Modify_TxAGC_Flag_PathB;
\r
1483 BOOLEAN Modify_TxAGC_Flag_PathC;
\r
1484 BOOLEAN Modify_TxAGC_Flag_PathD;
\r
1485 BOOLEAN Modify_TxAGC_Flag_PathA_CCK;
\r
1487 s1Byte KfreeOffset[MAX_RF_PATH];
\r
1490 // Dynamic ATC switch
\r
1493 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE))
\r
1497 BOOLEAN bDisablePowerTraining;
\r
1498 u1Byte ForcePowerTrainingState;
\r
1499 BOOLEAN bChangeState;
\r
1501 u8Byte OFDM_RX_Cnt;
\r
1502 u8Byte CCK_RX_Cnt;
\r
1506 // ODM system resource.
\r
1509 // ODM relative time.
\r
1510 RT_TIMER PathDivSwitchTimer;
\r
1511 //2011.09.27 add for Path Diversity
\r
1512 RT_TIMER CCKPathDiversityTimer;
\r
1513 RT_TIMER FastAntTrainingTimer;
\r
1515 // ODM relative workitem.
\r
1516 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
\r
1518 RT_WORK_ITEM PathDivSwitchWorkitem;
\r
1519 RT_WORK_ITEM CCKPathDiversityWorkitem;
\r
1520 RT_WORK_ITEM FastAntTrainingWorkitem;
\r
1521 RT_WORK_ITEM MPT_DIGWorkitem;
\r
1522 RT_WORK_ITEM RaRptWorkitem;
\r
1526 #if (BEAMFORMING_SUPPORT == 1)
\r
1527 RT_BEAMFORMING_INFO BeamformingInfo;
\r
1530 #if(DM_ODM_SUPPORT_TYPE & ODM_WIN)
\r
1532 #if (RT_PLATFORM != PLATFORM_LINUX)
\r
1533 } DM_ODM_T, *PDM_ODM_T; // DM_Dynamic_Mechanism_Structure
\r
1538 #else// for AP,ADSL,CE Team
\r
1539 } DM_ODM_T, *PDM_ODM_T; // DM_Dynamic_Mechanism_Structure
\r
1544 #if 1 //92c-series
\r
1545 #define ODM_RF_PATH_MAX 2
\r
1546 #else //jaguar - series
\r
1547 #define ODM_RF_PATH_MAX 4
\r
1550 typedef enum _PhyDM_Structure_Type{
\r
1551 PHYDM_FALSEALMCNT,
\r
1555 }PhyDM_Structure_Type;
\r
1557 typedef enum _ODM_RF_RADIO_PATH {
\r
1558 ODM_RF_PATH_A = 0, //Radio Path A
\r
1559 ODM_RF_PATH_B = 1, //Radio Path B
\r
1560 ODM_RF_PATH_C = 2, //Radio Path C
\r
1561 ODM_RF_PATH_D = 3, //Radio Path D
\r
1572 // ODM_RF_PATH_MAX, //Max RF number 90 support
\r
1573 } ODM_RF_RADIO_PATH_E, *PODM_RF_RADIO_PATH_E;
\r
1575 typedef enum _ODM_RF_CONTENT{
\r
1576 odm_radioa_txt = 0x1000,
\r
1577 odm_radiob_txt = 0x1001,
\r
1578 odm_radioc_txt = 0x1002,
\r
1579 odm_radiod_txt = 0x1003
\r
1582 typedef enum _ODM_BB_Config_Type{
\r
1583 CONFIG_BB_PHY_REG,
\r
1584 CONFIG_BB_AGC_TAB,
\r
1585 CONFIG_BB_AGC_TAB_2G,
\r
1586 CONFIG_BB_AGC_TAB_5G,
\r
1587 CONFIG_BB_PHY_REG_PG,
\r
1588 CONFIG_BB_PHY_REG_MP,
\r
1589 CONFIG_BB_AGC_TAB_DIFF,
\r
1590 } ODM_BB_Config_Type, *PODM_BB_Config_Type;
\r
1592 typedef enum _ODM_RF_Config_Type{
\r
1594 CONFIG_RF_TXPWR_LMT,
\r
1595 } ODM_RF_Config_Type, *PODM_RF_Config_Type;
\r
1597 typedef enum _ODM_FW_Config_Type{
\r
1603 CONFIG_FW_WoWLAN_2,
\r
1604 CONFIG_FW_AP_WoWLAN,
\r
1606 } ODM_FW_Config_Type;
\r
1609 #if (DM_ODM_SUPPORT_TYPE != ODM_WIN)
\r
1610 typedef enum _RT_STATUS{
\r
1611 RT_STATUS_SUCCESS,
\r
1612 RT_STATUS_FAILURE,
\r
1613 RT_STATUS_PENDING,
\r
1614 RT_STATUS_RESOURCE,
\r
1615 RT_STATUS_INVALID_CONTEXT,
\r
1616 RT_STATUS_INVALID_PARAMETER,
\r
1617 RT_STATUS_NOT_SUPPORT,
\r
1618 RT_STATUS_OS_API_FAILED,
\r
1619 }RT_STATUS,*PRT_STATUS;
\r
1620 #endif // end of RT_STATUS definition
\r
1622 #ifdef REMOVE_PACK
\r
1626 //#include "odm_function.h"
\r
1628 //3===========================================================
\r
1630 //3===========================================================
\r
1632 //Remove DIG by Yuchen
\r
1634 //3===========================================================
\r
1635 //3 AGC RX High Power Mode
\r
1636 //3===========================================================
\r
1637 #define LNA_Low_Gain_1 0x64
\r
1638 #define LNA_Low_Gain_2 0x5A
\r
1639 #define LNA_Low_Gain_3 0x58
\r
1641 #define FA_RXHP_TH1 5000
\r
1642 #define FA_RXHP_TH2 1500
\r
1643 #define FA_RXHP_TH3 800
\r
1644 #define FA_RXHP_TH4 600
\r
1645 #define FA_RXHP_TH5 500
\r
1647 //3===========================================================
\r
1649 //3===========================================================
\r
1651 //3===========================================================
\r
1652 //3 Dynamic Tx Power
\r
1653 //3===========================================================
\r
1654 //Dynamic Tx Power Control Threshold
\r
1656 //Remove By YuChen
\r
1658 //3===========================================================
\r
1659 //3 Tx Power Tracking
\r
1660 //3===========================================================
\r
1661 #if 0 //mask this, since these have been defined in typdef.h, vivi
\r
1662 #define OFDM_TABLE_SIZE 43
\r
1663 #define CCK_TABLE_SIZE 33
\r
1667 //3===========================================================
\r
1669 //3===========================================================
\r
1670 //Remove to odm_RaInfo.h by RS_James
\r
1672 //3===========================================================
\r
1674 //3===========================================================
\r
1676 typedef enum tag_1R_CCA_Type_Definition
\r
1683 typedef enum tag_RF_Type_Definition
\r
1690 //3===========================================================
\r
1691 //3 Antenna Diversity
\r
1692 //3===========================================================
\r
1693 typedef enum tag_SW_Antenna_Switch_Definition
\r
1701 // Maximal number of antenna detection mechanism needs to perform, added by Roger, 2011.12.28.
\r
1702 #define MAX_ANTENNA_DETECTION_CNT 10
\r
1705 // Extern Global Variables.
\r
1707 //remove PT by YuChen
\r
1709 // check Sta pointer valid or not
\r
1711 #if (DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL))
\r
1712 #define IS_STA_VALID(pSta) (pSta && pSta->expire_to)
\r
1713 #elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)
\r
1714 #define IS_STA_VALID(pSta) (pSta && pSta->bUsed)
\r
1716 #define IS_STA_VALID(pSta) (pSta)
\r
1718 // 20100514 Joseph: Add definition for antenna switching test after link.
\r
1719 // This indicates two different the steps.
\r
1720 // In SWAW_STEP_PEAK, driver needs to switch antenna and listen to the signal on the air.
\r
1721 // In SWAW_STEP_DETERMINE, driver just compares the signal captured in SWAW_STEP_PEAK
\r
1722 // with original RSSI to determine if it is necessary to switch antenna.
\r
1723 #define SWAW_STEP_PEAK 0
\r
1724 #define SWAW_STEP_DETERMINE 1
\r
1726 //Remove DIG by yuchen
\r
1731 //Remove BB power saving by Yuchen
\r
1737 //ODM_RAStateCheck() Remove by RS_James
\r
1739 #if(DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_AP|ODM_ADSL))
\r
1740 //============================================================
\r
1741 // function prototype
\r
1742 //============================================================
\r
1743 //#define DM_ChangeDynamicInitGainThresh ODM_ChangeDynamicInitGainThresh
\r
1744 //void ODM_ChangeDynamicInitGainThresh(IN PADAPTER pAdapter,
\r
1745 // IN INT32 DM_Type,
\r
1746 // IN INT32 DM_Value);
\r
1748 //Remove DIG by yuchen
\r
1752 ODM_CheckPowerStatus(
\r
1753 IN PADAPTER Adapter
\r
1757 //Remove ODM_RateAdaptiveStateApInit() by RS_James
\r
1759 //Remove Edca by YuChen
\r
1763 #if((DM_ODM_SUPPORT_TYPE==ODM_WIN)||(DM_ODM_SUPPORT_TYPE==ODM_CE))
\r
1765 u4Byte ConvertTo_dB(u4Byte Value);
\r
1769 PDM_ODM_T pDM_Odm,
\r
1770 unsigned int point,
\r
1771 u1Byte initial_gain_psd);
\r
1775 //Remove ODM_Get_Rate_Bitmap() by RS_James
\r
1778 #if (BEAMFORMING_SUPPORT == 1)
\r
1780 Beamforming_GetEntryBeamCapByMacId(
\r
1781 IN PMGNT_INFO pMgntInfo,
\r
1788 IN PDM_ODM_T pDM_Odm
\r
1793 IN PDM_ODM_T pDM_Odm
\r
1798 IN PDM_ODM_T pDM_Odm // For common use in the future
\r
1803 IN PDM_ODM_T pDM_Odm,
\r
1804 IN ODM_CMNINFO_E CmnInfo,
\r
1810 IN PDM_ODM_T pDM_Odm,
\r
1811 IN ODM_CMNINFO_E CmnInfo,
\r
1816 ODM_CmnInfoPtrArrayHook(
\r
1817 IN PDM_ODM_T pDM_Odm,
\r
1818 IN ODM_CMNINFO_E CmnInfo,
\r
1824 ODM_CmnInfoUpdate(
\r
1825 IN PDM_ODM_T pDM_Odm,
\r
1826 IN u4Byte CmnInfo,
\r
1831 ODM_InitAllTimers(
\r
1832 IN PDM_ODM_T pDM_Odm
\r
1836 ODM_CancelAllTimers(
\r
1837 IN PDM_ODM_T pDM_Odm
\r
1841 ODM_ReleaseAllTimers(
\r
1842 IN PDM_ODM_T pDM_Odm
\r
1846 ODM_ResetIQKResult(
\r
1847 IN PDM_ODM_T pDM_Odm
\r
1851 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
\r
1852 VOID ODM_InitAllWorkItems(IN PDM_ODM_T pDM_Odm );
\r
1853 VOID ODM_FreeAllWorkItems(IN PDM_ODM_T pDM_Odm );
\r
1856 //===========================================//
\r
1857 // Neil Chen----2011--06--15--
\r
1859 //3 Path Diversity
\r
1860 //===========================================================
\r
1863 #define RSSI_MODE 1
\r
1864 #define TRAFFIC_LOW 0
\r
1865 #define TRAFFIC_HIGH 1
\r
1867 //#define PATHDIV_ENABLE 1
\r
1869 //#define dm_PathDiv_RSSI_Check ODM_PathDivChkPerPktRssi
\r
1872 PlatformDivision64(
\r
1878 // 20100514 Joseph: Add definition for antenna switching test after link.
\r
1879 // This indicates two different the steps.
\r
1880 // In SWAW_STEP_PEAK, driver needs to switch antenna and listen to the signal on the air.
\r
1881 // In SWAW_STEP_DETERMINE, driver just compares the signal captured in SWAW_STEP_PEAK
\r
1882 // with original RSSI to determine if it is necessary to switch antenna.
\r
1883 #define SWAW_STEP_PEAK 0
\r
1884 #define SWAW_STEP_DETERMINE 1
\r
1886 //====================================================
\r
1888 //====================================================
\r
1890 //#define PathDivCheckBeforeLink8192C ODM_PathDiversityBeforeLink92C
\r
1892 #define DM_ChangeDynamicInitGainThresh ODM_ChangeDynamicInitGainThresh
\r
1893 //void ODM_ChangeDynamicInitGainThresh(IN PADAPTER pAdapter,
\r
1894 // IN INT32 DM_Type,
\r
1895 // IN INT32 DM_Value);
\r
1898 typedef enum tag_DIG_Connect_Definition
\r
1900 DIG_STA_DISCONNECT = 0,
\r
1901 DIG_STA_CONNECT = 1,
\r
1902 DIG_STA_BEFORE_CONNECT = 2,
\r
1903 DIG_MultiSTA_DISCONNECT = 3,
\r
1904 DIG_MultiSTA_CONNECT = 4,
\r
1906 }DM_DIG_CONNECT_E;
\r
1910 // 2012/01/12 MH Check afapter status. Temp fix BSOD.
\r
1912 #define HAL_ADAPTER_STS_CHK(pDM_Odm)\
\r
1913 if (pDM_Odm->Adapter == NULL)\
\r
1920 // For new definition in MP temporarily fro power tracking,
\r
1922 #define odm_TXPowerTrackingDirectCall(_Adapter) \
\r
1923 IS_HARDWARE_TYPE_8192D(_Adapter) ? odm_TXPowerTrackingCallback_ThermalMeter_92D(_Adapter) : \
\r
1924 IS_HARDWARE_TYPE_8192C(_Adapter) ? odm_TXPowerTrackingCallback_ThermalMeter_92C(_Adapter) : \
\r
1925 IS_HARDWARE_TYPE_8723A(_Adapter) ? odm_TXPowerTrackingCallback_ThermalMeter_8723A(_Adapter) :\
\r
1926 ODM_TXPowerTrackingCallback_ThermalMeter(_Adapter)
\r
1930 #endif // #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
\r
1933 #if( DM_ODM_SUPPORT_TYPE & (ODM_WIN |ODM_CE))
\r
1936 ODM_SingleDualAntennaDefaultSetting(
\r
1937 IN PDM_ODM_T pDM_Odm
\r
1941 ODM_SingleDualAntennaDetection(
\r
1942 IN PDM_ODM_T pDM_Odm,
\r
1946 #endif // #if((DM_ODM_SUPPORT_TYPE==ODM_WIN)||(DM_ODM_SUPPORT_TYPE==ODM_CE))
\r
1948 ODM_UpdateNoisyState(
\r
1949 IN PDM_ODM_T pDM_Odm,
\r
1950 IN BOOLEAN bNoisyStateFromC2H
\r
1954 Set_RA_DM_Ratrbitmap_by_Noisy(
\r
1955 IN PDM_ODM_T pDM_Odm,
\r
1956 IN WIRELESS_MODE WirelessMode,
\r
1957 IN u4Byte ratr_bitmap,
\r
1958 IN u1Byte rssi_level
\r
1962 ODM_UpdateInitRate(
\r
1963 IN PDM_ODM_T pDM_Odm,
\r
1968 ODM_InitializeTimer(
\r
1969 IN PDM_ODM_T pDM_Odm,
\r
1970 IN PRT_TIMER pTimer,
\r
1971 IN RT_TIMER_CALL_BACK CallBackFunc,
\r
1972 IN PVOID pContext,
\r
1973 IN const char* szID
\r
1977 ODM_CancelAllTimers(
\r
1978 IN PDM_ODM_T pDM_Odm
\r
1982 ODM_ReleaseAllTimers(
\r
1983 IN PDM_ODM_T pDM_Odm
\r
1986 //Remove ODM_DynamicARFBSelect() by RS_James
\r
1989 PhyDM_Get_Structure(
\r
1990 IN PDM_ODM_T pDM_Odm,
\r
1991 IN u1Byte Structure_Type
\r
1995 #if (DM_ODM_SUPPORT_TYPE == ODM_CE)
\r
1996 void odm_dtc(PDM_ODM_T pDM_Odm);
\r
1997 #endif /* #if (DM_ODM_SUPPORT_TYPE == ODM_CE) */
\r