1 /******************************************************************************
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3 * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
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5 * This program is free software; you can redistribute it and/or modify it
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6 * under the terms of version 2 of the GNU General Public License as
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7 * published by the Free Software Foundation.
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9 * This program is distributed in the hope that it will be useful, but WITHOUT
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10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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14 * You should have received a copy of the GNU General Public License along with
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15 * this program; if not, write to the Free Software Foundation, Inc.,
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16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
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19 ******************************************************************************/
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21 #ifndef __PHYDMANTDIV_H__
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22 #define __PHYDMANTDIV_H__
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24 /*#define ANTDIV_VERSION "2.0" //2014.11.04*/
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25 /*#define ANTDIV_VERSION "2.1" //2015.01.13 Dino*/
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26 #define ANTDIV_VERSION "2.2" /*2015.01.16 Dino*/
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28 //1 ============================================================
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30 //1 ============================================================
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32 #define ANTDIV_INIT 0xff
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33 #define MAIN_ANT 1 //Ant A or Ant Main
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34 #define AUX_ANT 2 //AntB or Ant Aux
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35 #define MAX_ANT 3 // 3 for AP using
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37 #define ANT1_2G 0 // = ANT2_5G
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38 #define ANT2_2G 1 // = ANT1_5G
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40 //Antenna Diversty Control Type
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41 #define ODM_AUTO_ANT 0
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42 #define ODM_FIX_MAIN_ANT 1
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43 #define ODM_FIX_AUX_ANT 2
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45 #define ODM_ANTDIV_SUPPORT (ODM_RTL8188E|ODM_RTL8192E|ODM_RTL8723B|ODM_RTL8821|ODM_RTL8881A|ODM_RTL8812)
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46 #define ODM_N_ANTDIV_SUPPORT (ODM_RTL8188E|ODM_RTL8192E|ODM_RTL8723B)
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47 #define ODM_AC_ANTDIV_SUPPORT (ODM_RTL8821|ODM_RTL8881A|ODM_RTL8812)
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48 #define ODM_SMART_ANT_SUPPORT (ODM_RTL8188E|ODM_RTL8192E)
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50 #define ODM_OLD_IC_ANTDIV_SUPPORT (ODM_RTL8723A|ODM_RTL8192C|ODM_RTL8192D)
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52 #define ODM_ANTDIV_2G_SUPPORT_IC (ODM_RTL8188E|ODM_RTL8192E|ODM_RTL8723B|ODM_RTL8881A)
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53 #define ODM_ANTDIV_5G_SUPPORT_IC (ODM_RTL8821|ODM_RTL8881A|ODM_RTL8812)
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55 #define ODM_EVM_ENHANCE_ANTDIV_SUPPORT_IC (ODM_RTL8192E)
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57 #define ODM_ANTDIV_2G BIT0
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58 #define ODM_ANTDIV_5G BIT1
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61 #define ANTDIV_OFF 0
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66 #define TX_BY_DESC 1
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69 #define RSSI_METHOD 0
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70 #define EVM_METHOD 1
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71 #define CRC32_METHOD 2
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73 #define INIT_ANTDIV_TIMMER 0
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74 #define CANCEL_ANTDIV_TIMMER 1
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75 #define RELEASE_ANTDIV_TIMMER 2
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77 #define CRC32_FAIL 1
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80 #define Evm_RSSI_TH_High 25
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81 #define Evm_RSSI_TH_Low 20
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83 #define NORMAL_STATE_MIAN 1
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84 #define NORMAL_STATE_AUX 2
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85 #define TRAINING_STATE 3
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87 #define FORCE_RSSI_DIFF 10
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92 #define DIVON_CSIOFF 1
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93 #define DIVOFF_CSION 2
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95 #define BDC_DIV_TRAIN_STATE 0
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96 #define BDC_BFer_TRAIN_STATE 1
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97 #define BDC_DECISION_STATE 2
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98 #define BDC_BF_HOLD_STATE 3
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99 #define BDC_DIV_HOLD_STATE 4
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101 #define BDC_MODE_1 1
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102 #define BDC_MODE_2 2
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103 #define BDC_MODE_3 3
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104 #define BDC_MODE_4 4
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105 #define BDC_MODE_NULL 0xff
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107 #define SWAW_STEP_PEAK 0
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108 #define SWAW_STEP_DETERMINE 1
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110 //1 ============================================================
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112 //1 ============================================================
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115 typedef struct _SW_Antenna_Switch_
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117 u1Byte Double_chk_flag;
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122 u1Byte RSSI_Trying;
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124 u1Byte bTriggerAntennaSwitch;
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125 u1Byte SelectAntennaMap;
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126 u1Byte RSSI_target;
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128 u2Byte Single_Ant_Counter;
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129 u2Byte Dual_Ant_Counter;
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130 u2Byte Aux_FailDetec_Counter;
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131 u2Byte Retry_Counter;
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133 // Before link Antenna Switch check
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134 u1Byte SWAS_NoLink_State;
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135 u4Byte SWAS_NoLink_BK_Reg860;
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136 u4Byte SWAS_NoLink_BK_Reg92c;
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137 u4Byte SWAS_NoLink_BK_Reg948;
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138 BOOLEAN ANTA_ON; //To indicate Ant A is or not
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139 BOOLEAN ANTB_ON; //To indicate Ant B is on or not
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140 BOOLEAN Pre_Aux_FailDetec;
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141 BOOLEAN RSSI_AntDect_bResult;
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150 u8Byte lastTxOkCnt;
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151 u8Byte lastRxOkCnt;
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152 u8Byte TXByteCnt_A;
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153 u8Byte TXByteCnt_B;
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154 u8Byte RXByteCnt_A;
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155 u8Byte RXByteCnt_B;
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156 u1Byte TrafficLoad;
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158 u1Byte Train_time_flag;
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159 RT_TIMER SwAntennaSwitchTimer;
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160 #if (RTL8723B_SUPPORT == 1)||(RTL8821A_SUPPORT == 1)
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161 RT_TIMER SwAntennaSwitchTimer_8723B;
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162 u4Byte PktCnt_SWAntDivByCtrlFrame;
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163 BOOLEAN bSWAntDivByCtrlFrame;
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166 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
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168 RT_WORK_ITEM SwAntennaSwitchWorkitem;
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169 #if (RTL8723B_SUPPORT == 1)||(RTL8821A_SUPPORT == 1)
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170 RT_WORK_ITEM SwAntennaSwitchWorkitem_8723B;
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175 #ifdef CONFIG_SW_ANTENNA_DIVERSITY
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176 _timer SwAntennaSwitchTimer;
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177 u8Byte lastTxOkCnt;
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178 u8Byte lastRxOkCnt;
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179 u8Byte TXByteCnt_A;
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180 u8Byte TXByteCnt_B;
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181 u8Byte RXByteCnt_A;
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182 u8Byte RXByteCnt_B;
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183 u1Byte DoubleComfirm;
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184 u1Byte TrafficLoad;
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185 //SW Antenna Switch
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190 #ifdef CONFIG_HW_ANTENNA_DIVERSITY
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191 //Hybrid Antenna Diversity
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192 u4Byte CCK_Ant1_Cnt[ODM_ASSOCIATE_ENTRY_NUM];
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193 u4Byte CCK_Ant2_Cnt[ODM_ASSOCIATE_ENTRY_NUM];
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194 u4Byte OFDM_Ant1_Cnt[ODM_ASSOCIATE_ENTRY_NUM];
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195 u4Byte OFDM_Ant2_Cnt[ODM_ASSOCIATE_ENTRY_NUM];
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196 u4Byte RSSI_Ant1_Sum[ODM_ASSOCIATE_ENTRY_NUM];
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197 u4Byte RSSI_Ant2_Sum[ODM_ASSOCIATE_ENTRY_NUM];
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198 u1Byte TxAnt[ODM_ASSOCIATE_ENTRY_NUM];
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208 #if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
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209 #if (defined(CONFIG_HW_ANTENNA_DIVERSITY))
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210 typedef struct _BF_DIV_COEX_
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212 BOOLEAN w_BFer_Client[ODM_ASSOCIATE_ENTRY_NUM];
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213 BOOLEAN w_BFee_Client[ODM_ASSOCIATE_ENTRY_NUM];
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214 u4Byte MA_rx_TP[ODM_ASSOCIATE_ENTRY_NUM];
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215 u4Byte MA_rx_TP_DIV[ODM_ASSOCIATE_ENTRY_NUM];
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217 u1Byte BDCcoexType_wBfer;
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218 u1Byte num_Txbfee_Client;
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219 u1Byte num_Txbfer_Client;
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220 u1Byte BDC_Try_counter;
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221 u1Byte BDC_Hold_counter;
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223 u1Byte BDC_active_Mode;
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225 u1Byte BDC_RxIdleUpdate_counter;
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227 u1Byte pre_num_Client;
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231 BOOLEAN bAll_DivSta_Idle;
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232 BOOLEAN bAll_BFSta_Idle;
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233 BOOLEAN BDC_Try_flag;
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241 typedef struct _FAST_ANTENNA_TRAINNING_
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244 u1Byte antsel_rx_keep_0;
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245 u1Byte antsel_rx_keep_1;
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246 u1Byte antsel_rx_keep_2;
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247 u1Byte antsel_rx_keep_3;
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248 u4Byte antSumRSSI[7];
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249 u4Byte antRSSIcnt[7];
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250 u4Byte antAveRSSI[7];
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253 u1Byte antsel_a[ODM_ASSOCIATE_ENTRY_NUM];
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254 u1Byte antsel_b[ODM_ASSOCIATE_ENTRY_NUM];
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255 u1Byte antsel_c[ODM_ASSOCIATE_ENTRY_NUM];
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256 u4Byte MainAnt_Sum[ODM_ASSOCIATE_ENTRY_NUM];
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257 u4Byte AuxAnt_Sum[ODM_ASSOCIATE_ENTRY_NUM];
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258 u4Byte MainAnt_Cnt[ODM_ASSOCIATE_ENTRY_NUM];
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259 u4Byte AuxAnt_Cnt[ODM_ASSOCIATE_ENTRY_NUM];
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261 u1Byte AntDiv_OnOff;
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262 BOOLEAN bBecomeLinked;
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264 u1Byte idx_AntDiv_counter_2G;
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265 u1Byte idx_AntDiv_counter_5G;
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266 u1Byte AntDiv_2G_5G;
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267 u4Byte CCK_counter_main;
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268 u4Byte CCK_counter_aux;
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269 u4Byte OFDM_counter_main;
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270 u4Byte OFDM_counter_aux;
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272 #ifdef ODM_EVM_ENHANCE_ANTDIV
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273 u4Byte MainAntEVM_Sum[ODM_ASSOCIATE_ENTRY_NUM];
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274 u4Byte AuxAntEVM_Sum[ODM_ASSOCIATE_ENTRY_NUM];
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275 u4Byte MainAntEVM_Cnt[ODM_ASSOCIATE_ENTRY_NUM];
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276 u4Byte AuxAntEVM_Cnt[ODM_ASSOCIATE_ENTRY_NUM];
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277 BOOLEAN EVM_method_enable;
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278 u1Byte TargetAnt_EVM;
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279 u1Byte TargetAnt_CRC32;
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280 u1Byte TargetAnt_enhance;
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281 u1Byte pre_TargetAnt_enhance;
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282 u2Byte Main_MPDU_OK_cnt;
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283 u2Byte Aux_MPDU_OK_cnt;
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285 u4Byte CRC32_Ok_Cnt;
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286 u4Byte CRC32_Fail_Cnt;
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287 u4Byte MainCRC32_Ok_Cnt;
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288 u4Byte AuxCRC32_Ok_Cnt;
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289 u4Byte MainCRC32_Fail_Cnt;
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290 u4Byte AuxCRC32_Fail_Cnt;
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292 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE))
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293 u4Byte CCK_CtrlFrame_Cnt_main;
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294 u4Byte CCK_CtrlFrame_Cnt_aux;
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295 u4Byte OFDM_CtrlFrame_Cnt_main;
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296 u4Byte OFDM_CtrlFrame_Cnt_aux;
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297 u4Byte MainAnt_CtrlFrame_Sum;
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298 u4Byte AuxAnt_CtrlFrame_Sum;
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299 u4Byte MainAnt_CtrlFrame_Cnt;
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300 u4Byte AuxAnt_CtrlFrame_Cnt;
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302 BOOLEAN fix_ant_bfee;
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306 //1 ============================================================
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308 //1 ============================================================
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312 typedef enum _FAT_STATE
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314 FAT_NORMAL_STATE = 0,
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315 FAT_TRAINING_STATE = 1,
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316 }FAT_STATE_E, *PFAT_STATE_E;
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319 typedef enum _ANT_DIV_TYPE
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322 CG_TRX_HW_ANTDIV = 0x01,
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323 CGCS_RX_HW_ANTDIV = 0x02,
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324 FIXED_HW_ANTDIV = 0x03,
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325 CG_TRX_SMART_ANTDIV = 0x04,
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326 CGCS_RX_SW_ANTDIV = 0x05,
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327 S0S1_SW_ANTDIV = 0x06 //8723B intrnal switch S0 S1
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328 }ANT_DIV_TYPE_E, *PANT_DIV_TYPE_E;
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331 //1 ============================================================
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332 //1 function prototype
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333 //1 ============================================================
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337 ODM_StopAntennaSwitchDm(
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343 IN u1Byte antSetting // 0=A, 1=B, 2=C, ....
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347 #define SwAntDivRestAfterLink ODM_SwAntDivRestAfterLink
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348 VOID ODM_SwAntDivRestAfterLink(
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352 #if (defined(CONFIG_HW_ANTENNA_DIVERSITY))
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355 ODM_UpdateRxIdleAnt(
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356 IN PVOID pDM_VOID,
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360 #if (RTL8723B_SUPPORT == 1)||(RTL8821A_SUPPORT == 1)
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361 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
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363 ODM_SW_AntDiv_Callback(
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364 IN PRT_TIMER pTimer
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368 ODM_SW_AntDiv_WorkitemCallback(
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373 #elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
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376 ODM_SW_AntDiv_Callback(
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377 void *FunctionContext
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382 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE))
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384 odm_S0S1_SwAntDivByCtrlFrame(
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390 odm_AntselStatisticsOfCtrlFrame(
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392 IN u1Byte antsel_tr_mux,
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393 IN u4Byte RxPWDBAll
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397 odm_S0S1_SwAntDivByCtrlFrame_ProcessRSSI(
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399 IN PVOID p_phy_info_void,
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400 IN PVOID p_pkt_info_void
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405 odm_S0S1_SwAntDivByCtrlFrame_ProcessRSSI(
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407 IN PVOID p_phy_info_void,
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408 IN PVOID p_pkt_info_void
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415 #ifdef ODM_EVM_ENHANCE_ANTDIV
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417 odm_EVM_FastAntTrainingCallback(
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427 #if( defined(CONFIG_5G_CG_SMART_ANT_DIVERSITY) ) ||( defined(CONFIG_2G_CG_SMART_ANT_DIVERSITY) )
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429 odm_FastAntTraining(
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434 odm_FastAntTrainingCallback(
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439 odm_FastAntTrainingWorkItemCallback(
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456 odm_AntselStatistics(
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458 IN u1Byte antsel_tr_mux,
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465 ODM_Process_RSSIForAntDiv(
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466 IN OUT PVOID pDM_VOID,
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467 IN PVOID p_phy_info_void,
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468 IN PVOID p_pkt_info_void
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474 ODM_Process_RSSIForAntDiv(
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475 IN OUT PVOID pDM_VOID,
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476 IN PVOID p_phy_info_void,
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477 IN PVOID p_pkt_info_void
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482 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE))
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484 ODM_SetTxAntByTxInfo(
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490 #elif(DM_ODM_SUPPORT_TYPE == ODM_AP)
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493 ODM_SetTxAntByTxInfo(
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494 struct rtl8192cd_priv *priv,
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495 struct tx_desc *pdesc,
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496 unsigned short aid
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509 ODM_UpdateRxIdleAnt_8723B(
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512 IN u4Byte DefaultAnt,
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513 IN u4Byte OptionalAnt
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522 #endif //#if (defined(CONFIG_HW_ANTENNA_DIVERSITY))
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530 odm_AntennaDiversityInit(
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535 odm_AntennaDiversity(
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540 #endif //#ifndef __ODMANTDIV_H__
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