drivers/net/wireless/rockchip_wlan/rtl8723bu/hal/OUTSRC/phydm_pre_define.h

   1 /******************************************************************************\r
   2  *\r
   3  * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.\r
   4  *                                        \r
   5  * This program is free software; you can redistribute it and/or modify it\r
   6  * under the terms of version 2 of the GNU General Public License as\r
   7  * published by the Free Software Foundation.\r
   8  *\r
   9  * This program is distributed in the hope that it will be useful, but WITHOUT\r
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\r
  11  * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\r
  12  * more details.\r
  13  *\r
  14  * You should have received a copy of the GNU General Public License along with\r
  15  * this program; if not, write to the Free Software Foundation, Inc.,\r
  16  * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA\r
  17  *\r
  18  *\r
  19  ******************************************************************************/\r
  20 \r
  21 \r
  22 #ifndef __PHYDMPREDEFINE_H__\r
  23 #define    __PHYDMPREDEFINE_H__\r
  24 \r
  25 //1 ============================================================\r
  26 //1  Definition \r
  27 //1 ============================================================\r
  28 \r
  29 //Max path of IC\r
  30 #define MAX_PATH_NUM_92CS               2\r
  31 #define MAX_PATH_NUM_8188E              1\r
  32 #define MAX_PATH_NUM_8192E              2\r
  33 #define MAX_PATH_NUM_8723B              1\r
  34 #define MAX_PATH_NUM_8812A              2\r
  35 #define MAX_PATH_NUM_8821A              1\r
  36 #define MAX_PATH_NUM_8814A              4\r
  37 #define MAX_PATH_NUM_8822B              2\r
  38 #define MAX_PATH_NUM_8821B              2\r
  39 \r
  40 //Max RF path\r
  41 #define ODM_RF_PATH_MAX 2\r
  42 #define ODM_RF_PATH_MAX_JAGUAR 4\r
  43 \r
  44 //number of entry\r
  45 #if(DM_ODM_SUPPORT_TYPE & (ODM_CE))\r
  46         #define ASSOCIATE_ENTRY_NUM                                     MACID_NUM_SW_LIMIT  /* Max size of AsocEntry[].*/\r
  47         #define ODM_ASSOCIATE_ENTRY_NUM                         ASSOCIATE_ENTRY_NUM\r
  48 #elif(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL))\r
  49         #define ASSOCIATE_ENTRY_NUM                                     NUM_STAT\r
  50         #define ODM_ASSOCIATE_ENTRY_NUM                         ASSOCIATE_ENTRY_NUM+1\r
  51 #else\r
  52         #define ODM_ASSOCIATE_ENTRY_NUM                         (ASSOCIATE_ENTRY_NUM*3)+1// Default port only one // 0 is for STA 1-n is for AP clients.\r
  53 #endif\r
  54 \r
  55 /* -----MGN rate--------------------------------- */\r
  56 \r
  57 #define ODM_MGN_1M                      0x02\r
  58 #define ODM_MGN_2M                      0x04\r
  59 #define ODM_MGN_5_5M                    0x0b\r
  60 #define ODM_MGN_11M                     0x16\r
  61 \r
  62 #define ODM_MGN_6M                      0x0c\r
  63 #define ODM_MGN_9M                      0x12\r
  64 #define ODM_MGN_12M                     0x18\r
  65 #define ODM_MGN_18M                     0x24\r
  66 #define ODM_MGN_24M                     0x30\r
  67 #define ODM_MGN_36M                     0x48\r
  68 #define ODM_MGN_48M                     0x60\r
  69 #define ODM_MGN_54M                     0x6c\r
  70 \r
  71 /*TxHT = 1*/\r
  72 #define ODM_MGN_MCS0                    0x80\r
  73 #define ODM_MGN_MCS1                    0x81\r
  74 #define ODM_MGN_MCS2                    0x82\r
  75 #define ODM_MGN_MCS3                    0x83\r
  76 #define ODM_MGN_MCS4                    0x84\r
  77 #define ODM_MGN_MCS5                    0x85\r
  78 #define ODM_MGN_MCS6                    0x86\r
  79 #define ODM_MGN_MCS7                    0x87\r
  80 #define ODM_MGN_MCS8                    0x88\r
  81 #define ODM_MGN_MCS9                    0x89\r
  82 #define ODM_MGN_MCS10           0x8a\r
  83 #define ODM_MGN_MCS11           0x8b\r
  84 #define ODM_MGN_MCS12           0x8c\r
  85 #define ODM_MGN_MCS13           0x8d\r
  86 #define ODM_MGN_MCS14           0x8e\r
  87 #define ODM_MGN_MCS15           0x8f\r
  88 #define ODM_MGN_VHT1SS_MCS0     0x90\r
  89 #define ODM_MGN_VHT1SS_MCS1     0x91\r
  90 #define ODM_MGN_VHT1SS_MCS2     0x92\r
  91 #define ODM_MGN_VHT1SS_MCS3     0x93\r
  92 #define ODM_MGN_VHT1SS_MCS4     0x94\r
  93 #define ODM_MGN_VHT1SS_MCS5     0x95\r
  94 #define ODM_MGN_VHT1SS_MCS6     0x96\r
  95 #define ODM_MGN_VHT1SS_MCS7     0x97\r
  96 #define ODM_MGN_VHT1SS_MCS8     0x98\r
  97 #define ODM_MGN_VHT1SS_MCS9     0x99\r
  98 #define ODM_MGN_VHT2SS_MCS0     0x9a\r
  99 #define ODM_MGN_VHT2SS_MCS1     0x9b\r
 100 #define ODM_MGN_VHT2SS_MCS2     0x9c\r
 101 #define ODM_MGN_VHT2SS_MCS3     0x9d\r
 102 #define ODM_MGN_VHT2SS_MCS4     0x9e\r
 103 #define ODM_MGN_VHT2SS_MCS5     0x9f\r
 104 #define ODM_MGN_VHT2SS_MCS6     0xa0\r
 105 #define ODM_MGN_VHT2SS_MCS7     0xa1\r
 106 #define ODM_MGN_VHT2SS_MCS8     0xa2\r
 107 #define ODM_MGN_VHT2SS_MCS9     0xa3\r
 108 \r
 109 #define ODM_MGN_MCS0_SG         0xc0\r
 110 #define ODM_MGN_MCS1_SG         0xc1\r
 111 #define ODM_MGN_MCS2_SG         0xc2\r
 112 #define ODM_MGN_MCS3_SG         0xc3\r
 113 #define ODM_MGN_MCS4_SG         0xc4\r
 114 #define ODM_MGN_MCS5_SG         0xc5\r
 115 #define ODM_MGN_MCS6_SG         0xc6\r
 116 #define ODM_MGN_MCS7_SG         0xc7\r
 117 #define ODM_MGN_MCS8_SG         0xc8\r
 118 #define ODM_MGN_MCS9_SG         0xc9\r
 119 #define ODM_MGN_MCS10_SG                0xca\r
 120 #define ODM_MGN_MCS11_SG                0xcb\r
 121 #define ODM_MGN_MCS12_SG                0xcc\r
 122 #define ODM_MGN_MCS13_SG                0xcd\r
 123 #define ODM_MGN_MCS14_SG                0xce\r
 124 #define ODM_MGN_MCS15_SG                0xcf\r
 125 \r
 126 /* -----DESC rate--------------------------------- */\r
 127 \r
 128 #define ODM_RATEMCS15_SG                0x1c\r
 129 #define ODM_RATEMCS32                   0x20\r
 130 \r
 131 \r
 132 // CCK Rates, TxHT = 0\r
 133 #define ODM_RATE1M                              0x00\r
 134 #define ODM_RATE2M                              0x01\r
 135 #define ODM_RATE5_5M                    0x02\r
 136 #define ODM_RATE11M                             0x03\r
 137 // OFDM Rates, TxHT = 0\r
 138 #define ODM_RATE6M                              0x04\r
 139 #define ODM_RATE9M                              0x05\r
 140 #define ODM_RATE12M                             0x06\r
 141 #define ODM_RATE18M                             0x07\r
 142 #define ODM_RATE24M                             0x08\r
 143 #define ODM_RATE36M                             0x09\r
 144 #define ODM_RATE48M                             0x0A\r
 145 #define ODM_RATE54M                             0x0B\r
 146 // MCS Rates, TxHT = 1\r
 147 #define ODM_RATEMCS0                    0x0C\r
 148 #define ODM_RATEMCS1                    0x0D\r
 149 #define ODM_RATEMCS2                    0x0E\r
 150 #define ODM_RATEMCS3                    0x0F\r
 151 #define ODM_RATEMCS4                    0x10\r
 152 #define ODM_RATEMCS5                    0x11\r
 153 #define ODM_RATEMCS6                    0x12\r
 154 #define ODM_RATEMCS7                    0x13\r
 155 #define ODM_RATEMCS8                    0x14\r
 156 #define ODM_RATEMCS9                    0x15\r
 157 #define ODM_RATEMCS10                   0x16\r
 158 #define ODM_RATEMCS11                   0x17\r
 159 #define ODM_RATEMCS12                   0x18\r
 160 #define ODM_RATEMCS13                   0x19\r
 161 #define ODM_RATEMCS14                   0x1A\r
 162 #define ODM_RATEMCS15                   0x1B\r
 163 #define ODM_RATEMCS16                   0x1C\r
 164 #define ODM_RATEMCS17                   0x1D\r
 165 #define ODM_RATEMCS18                   0x1E\r
 166 #define ODM_RATEMCS19                   0x1F\r
 167 #define ODM_RATEMCS20                   0x20\r
 168 #define ODM_RATEMCS21                   0x21\r
 169 #define ODM_RATEMCS22                   0x22\r
 170 #define ODM_RATEMCS23                   0x23\r
 171 #define ODM_RATEMCS24                   0x24\r
 172 #define ODM_RATEMCS25                   0x25\r
 173 #define ODM_RATEMCS26                   0x26\r
 174 #define ODM_RATEMCS27                   0x27\r
 175 #define ODM_RATEMCS28                   0x28\r
 176 #define ODM_RATEMCS29                   0x29\r
 177 #define ODM_RATEMCS30                   0x2A\r
 178 #define ODM_RATEMCS31                   0x2B\r
 179 #define ODM_RATEVHTSS1MCS0              0x2C\r
 180 #define ODM_RATEVHTSS1MCS1              0x2D\r
 181 #define ODM_RATEVHTSS1MCS2              0x2E\r
 182 #define ODM_RATEVHTSS1MCS3              0x2F\r
 183 #define ODM_RATEVHTSS1MCS4              0x30\r
 184 #define ODM_RATEVHTSS1MCS5              0x31\r
 185 #define ODM_RATEVHTSS1MCS6              0x32\r
 186 #define ODM_RATEVHTSS1MCS7              0x33\r
 187 #define ODM_RATEVHTSS1MCS8              0x34\r
 188 #define ODM_RATEVHTSS1MCS9              0x35\r
 189 #define ODM_RATEVHTSS2MCS0              0x36\r
 190 #define ODM_RATEVHTSS2MCS1              0x37\r
 191 #define ODM_RATEVHTSS2MCS2              0x38\r
 192 #define ODM_RATEVHTSS2MCS3              0x39\r
 193 #define ODM_RATEVHTSS2MCS4              0x3A\r
 194 #define ODM_RATEVHTSS2MCS5              0x3B\r
 195 #define ODM_RATEVHTSS2MCS6              0x3C\r
 196 #define ODM_RATEVHTSS2MCS7              0x3D\r
 197 #define ODM_RATEVHTSS2MCS8              0x3E\r
 198 #define ODM_RATEVHTSS2MCS9              0x3F\r
 199 #define ODM_RATEVHTSS3MCS0              0x40\r
 200 #define ODM_RATEVHTSS3MCS1              0x41\r
 201 #define ODM_RATEVHTSS3MCS2              0x42\r
 202 #define ODM_RATEVHTSS3MCS3              0x43\r
 203 #define ODM_RATEVHTSS3MCS4              0x44\r
 204 #define ODM_RATEVHTSS3MCS5              0x45\r
 205 #define ODM_RATEVHTSS3MCS6              0x46\r
 206 #define ODM_RATEVHTSS3MCS7              0x47\r
 207 #define ODM_RATEVHTSS3MCS8              0x48\r
 208 #define ODM_RATEVHTSS3MCS9              0x49\r
 209 #define ODM_RATEVHTSS4MCS0              0x4A\r
 210 #define ODM_RATEVHTSS4MCS1              0x4B\r
 211 #define ODM_RATEVHTSS4MCS2              0x4C\r
 212 #define ODM_RATEVHTSS4MCS3              0x4D\r
 213 #define ODM_RATEVHTSS4MCS4              0x4E\r
 214 #define ODM_RATEVHTSS4MCS5              0x4F\r
 215 #define ODM_RATEVHTSS4MCS6              0x50\r
 216 #define ODM_RATEVHTSS4MCS7              0x51\r
 217 #define ODM_RATEVHTSS4MCS8              0x52\r
 218 #define ODM_RATEVHTSS4MCS9              0x53\r
 219 \r
 220 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)\r
 221         #define ODM_NUM_RATE_IDX (ODM_RATEVHTSS4MCS9+1)\r
 222 #else\r
 223         #if (RTL8192E_SUPPORT == 1)\r
 224                 #define ODM_NUM_RATE_IDX (ODM_RATEMCS15+1)\r
 225         #elif (RTL8723B_SUPPORT == 1)|| (RTL8188E_SUPPORT == 1) \r
 226                 #define ODM_NUM_RATE_IDX (ODM_RATEMCS7+1)\r
 227         #elif (RTL8821A_SUPPORT == 1) || (RTL8881A_SUPPORT == 1) \r
 228                 #define ODM_NUM_RATE_IDX (ODM_RATEVHTSS1MCS9+1)\r
 229         #elif (RTL8812A_SUPPORT == 1)\r
 230                 #define ODM_NUM_RATE_IDX (ODM_RATEVHTSS2MCS9+1)\r
 231         #elif(RTL8814A_SUPPORT == 1)\r
 232                 #define ODM_NUM_RATE_IDX (ODM_RATEVHTSS3MCS9+1)\r
 233         #else\r
 234                 #define ODM_NUM_RATE_IDX (ODM_RATEVHTSS4MCS9+1)\r
 235         #endif\r
 236 #endif\r
 237 \r
 238 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)\r
 239 #define CONFIG_SFW_SUPPORTED\r
 240 #endif\r
 241 \r
 242 //1 ============================================================\r
 243 //1  enumeration\r
 244 //1 ============================================================\r
 245 \r
 246 \r
 247 //      ODM_CMNINFO_INTERFACE\r
 248 typedef enum tag_ODM_Support_Interface_Definition\r
 249 {\r
 250         ODM_ITRF_PCIE   =       0x1,\r
 251         ODM_ITRF_USB    =       0x2,\r
 252         ODM_ITRF_SDIO   =       0x4,\r
 253         ODM_ITRF_ALL    =       0x7,\r
 254 }ODM_INTERFACE_E;\r
 255 \r
 256 // ODM_CMNINFO_IC_TYPE\r
 257 typedef enum tag_ODM_Support_IC_Type_Definition\r
 258 {\r
 259         ODM_RTL8192S    =       BIT0,\r
 260         ODM_RTL8192C    =       BIT1,\r
 261         ODM_RTL8192D    =       BIT2,\r
 262         ODM_RTL8723A    =       BIT3,\r
 263         ODM_RTL8188E    =       BIT4,\r
 264         ODM_RTL8812     =       BIT5,\r
 265         ODM_RTL8821     =       BIT6,\r
 266         ODM_RTL8192E    =       BIT7,   \r
 267         ODM_RTL8723B    =       BIT8,\r
 268         ODM_RTL8814A    =       BIT9,   \r
 269         ODM_RTL8881A    =       BIT10,\r
 270         ODM_RTL8821B    =       BIT11,\r
 271         ODM_RTL8822B    =       BIT12,\r
 272         ODM_RTL8703B    =       BIT13,\r
 273         ODM_RTL8195A    =       BIT14,\r
 274         ODM_RTL8188F    =       BIT15\r
 275 }ODM_IC_TYPE_E;\r
 276 \r
 277 \r
 278 \r
 279 \r
 280 #define ODM_IC_11N_SERIES               (ODM_RTL8192S|ODM_RTL8192C|ODM_RTL8192D|ODM_RTL8723A|ODM_RTL8188E|ODM_RTL8192E|ODM_RTL8723B|ODM_RTL8703B|ODM_RTL8188F)\r
 281 #define ODM_IC_11AC_SERIES              (ODM_RTL8812|ODM_RTL8821|ODM_RTL8814A|ODM_RTL8881A|ODM_RTL8821B|ODM_RTL8822B)\r
 282 #define ODM_IC_TXBF_SUPPORT             (ODM_RTL8192E|ODM_RTL8812|ODM_RTL8821|ODM_RTL8814A|ODM_RTL8881A|ODM_RTL8822B)\r
 283 \r
 284 #if (DM_ODM_SUPPORT_TYPE == ODM_AP)\r
 285 \r
 286 #ifdef RTK_AC_SUPPORT\r
 287 #define ODM_IC_11AC_SERIES_SUPPORT              1\r
 288 #else\r
 289 #define ODM_IC_11AC_SERIES_SUPPORT              0\r
 290 #endif\r
 291 \r
 292 #define ODM_IC_11N_SERIES_SUPPORT                       1\r
 293 #define ODM_CONFIG_BT_COEXIST                           0\r
 294 \r
 295 #elif (DM_ODM_SUPPORT_TYPE == ODM_WIN)\r
 296 \r
 297 #define ODM_IC_11AC_SERIES_SUPPORT              1\r
 298 #define ODM_IC_11N_SERIES_SUPPORT                       1\r
 299 #define ODM_CONFIG_BT_COEXIST                           1\r
 300 \r
 301 #else \r
 302 \r
 303 #if((RTL8192C_SUPPORT == 1) || (RTL8192D_SUPPORT == 1) || (RTL8723A_SUPPORT == 1) || (RTL8188E_SUPPORT == 1) ||\\r
 304 (RTL8723B_SUPPORT == 1) || (RTL8192E_SUPPORT == 1) || (RTL8195A_SUPPORT == 1))\r
 305 #define ODM_IC_11N_SERIES_SUPPORT                       1\r
 306 #define ODM_IC_11AC_SERIES_SUPPORT              0\r
 307 #else\r
 308 #define ODM_IC_11N_SERIES_SUPPORT                       0\r
 309 #define ODM_IC_11AC_SERIES_SUPPORT              1\r
 310 #endif\r
 311 \r
 312 #ifdef CONFIG_BT_COEXIST\r
 313 #define ODM_CONFIG_BT_COEXIST                           1\r
 314 #else\r
 315 #define ODM_CONFIG_BT_COEXIST                           0\r
 316 #endif\r
 317 \r
 318 #endif\r
 319 \r
 320 \r
 321 //ODM_CMNINFO_CUT_VER\r
 322 typedef enum tag_ODM_Cut_Version_Definition\r
 323 {\r
 324         ODM_CUT_A               =       0,\r
 325         ODM_CUT_B               =       1,\r
 326         ODM_CUT_C               =       2,\r
 327         ODM_CUT_D               =       3,\r
 328         ODM_CUT_E               =       4,\r
 329         ODM_CUT_F               =       5,\r
 330 \r
 331         ODM_CUT_I               =       8,\r
 332         ODM_CUT_J               =       9,\r
 333         ODM_CUT_K               =       10,     \r
 334         ODM_CUT_TEST    =       15,\r
 335 }ODM_CUT_VERSION_E;\r
 336 \r
 337 // ODM_CMNINFO_FAB_VER\r
 338 typedef enum tag_ODM_Fab_Version_Definition\r
 339 {\r
 340         ODM_TSMC        =       0,\r
 341         ODM_UMC         =       1,\r
 342 }ODM_FAB_E;\r
 343 \r
 344 // ODM_CMNINFO_RF_TYPE\r
 345 //\r
 346 // For example 1T2R (A+AB = BIT0|BIT4|BIT5)\r
 347 //\r
 348 typedef enum tag_ODM_RF_Path_Bit_Definition\r
 349 {\r
 350         ODM_RF_TX_A     =       BIT0,\r
 351         ODM_RF_TX_B     =       BIT1,\r
 352         ODM_RF_TX_C     =       BIT2,\r
 353         ODM_RF_TX_D     =       BIT3,\r
 354         ODM_RF_RX_A     =       BIT4,\r
 355         ODM_RF_RX_B     =       BIT5,\r
 356         ODM_RF_RX_C     =       BIT6,\r
 357         ODM_RF_RX_D     =       BIT7,\r
 358 }ODM_RF_PATH_E;\r
 359 \r
 360 typedef enum tag_PHYDM_RF_TX_NUM {\r
 361         ODM_1T  =       1,\r
 362         ODM_2T  =       2,\r
 363         ODM_3T  =       3,\r
 364         ODM_4T  =       4,\r
 365 } ODM_RF_TX_NUM_E;\r
 366 \r
 367 typedef enum tag_ODM_RF_Type_Definition {\r
 368         ODM_1T1R,\r
 369         ODM_1T2R,\r
 370         ODM_2T2R,\r
 371         ODM_2T2R_GREEN,\r
 372         ODM_2T3R,\r
 373         ODM_2T4R,\r
 374         ODM_3T3R,\r
 375         ODM_3T4R,\r
 376         ODM_4T4R,\r
 377         ODM_XTXR\r
 378 }ODM_RF_TYPE_E;\r
 379 \r
 380 \r
 381 typedef enum tag_ODM_MAC_PHY_Mode_Definition\r
 382 {\r
 383         ODM_SMSP        = 0,\r
 384         ODM_DMSP        = 1,\r
 385         ODM_DMDP        = 2,\r
 386 }ODM_MAC_PHY_MODE_E;\r
 387 \r
 388 \r
 389 typedef enum tag_BT_Coexist_Definition\r
 390 {       \r
 391         ODM_BT_BUSY             = 1,\r
 392         ODM_BT_ON                       = 2,\r
 393         ODM_BT_OFF              = 3,\r
 394         ODM_BT_NONE             = 4,\r
 395 }ODM_BT_COEXIST_E;\r
 396 \r
 397 // ODM_CMNINFO_OP_MODE\r
 398 typedef enum tag_Operation_Mode_Definition\r
 399 {\r
 400         ODM_NO_LINK             = BIT0,\r
 401         ODM_LINK                        = BIT1,\r
 402         ODM_SCAN                        = BIT2,\r
 403         ODM_POWERSAVE   = BIT3,\r
 404         ODM_AP_MODE             = BIT4,\r
 405         ODM_CLIENT_MODE = BIT5,\r
 406         ODM_AD_HOC              = BIT6,\r
 407         ODM_WIFI_DIRECT = BIT7,\r
 408         ODM_WIFI_DISPLAY        = BIT8,\r
 409 }ODM_OPERATION_MODE_E;\r
 410 \r
 411 // ODM_CMNINFO_WM_MODE\r
 412 #if (DM_ODM_SUPPORT_TYPE & (ODM_CE))\r
 413 typedef enum tag_Wireless_Mode_Definition\r
 414 {\r
 415         ODM_WM_UNKNOW   = 0x0,\r
 416         ODM_WM_B                        = BIT0,\r
 417         ODM_WM_G                        = BIT1,\r
 418         ODM_WM_A                        = BIT2,\r
 419         ODM_WM_N24G             = BIT3,\r
 420         ODM_WM_N5G              = BIT4,\r
 421         ODM_WM_AUTO             = BIT5,\r
 422         ODM_WM_AC               = BIT6,\r
 423 }ODM_WIRELESS_MODE_E;\r
 424 #else\r
 425 typedef enum tag_Wireless_Mode_Definition\r
 426 {\r
 427         ODM_WM_UNKNOWN  = 0x00,/*0x0*/\r
 428         ODM_WM_A                        = BIT0, /* 0x1*/\r
 429         ODM_WM_B                        = BIT1, /* 0x2*/\r
 430         ODM_WM_G                        = BIT2,/* 0x4*/\r
 431         ODM_WM_AUTO             = BIT3,/* 0x8*/\r
 432         ODM_WM_N24G             = BIT4,/* 0x10*/\r
 433         ODM_WM_N5G              = BIT5,/* 0x20*/\r
 434         ODM_WM_AC_5G            = BIT6,/* 0x40*/\r
 435         ODM_WM_AC_24G   = BIT7,/* 0x80*/\r
 436         ODM_WM_AC_ONLY  = BIT8,/* 0x100*/\r
 437         ODM_WM_MAX              = BIT11/* 0x800*/\r
 438 \r
 439 }ODM_WIRELESS_MODE_E;\r
 440 #endif\r
 441 \r
 442 // ODM_CMNINFO_BAND\r
 443 typedef enum tag_Band_Type_Definition\r
 444 {\r
 445 #if (DM_ODM_SUPPORT_TYPE & (ODM_AP))\r
 446         ODM_BAND_2_4G   = BIT0,\r
 447         ODM_BAND_5G             = BIT1,\r
 448 #else\r
 449         ODM_BAND_2_4G = 0,\r
 450         ODM_BAND_5G,\r
 451         ODM_BAND_ON_BOTH,\r
 452         ODM_BANDMAX\r
 453 #endif\r
 454 }ODM_BAND_TYPE_E;\r
 455 \r
 456 \r
 457 // ODM_CMNINFO_SEC_CHNL_OFFSET\r
 458 typedef enum tag_Secondary_Channel_Offset_Definition\r
 459 {\r
 460         ODM_DONT_CARE   = 0,\r
 461         ODM_BELOW               = 1,\r
 462         ODM_ABOVE                       = 2\r
 463 }ODM_SEC_CHNL_OFFSET_E;\r
 464 \r
 465 // ODM_CMNINFO_SEC_MODE\r
 466 typedef enum tag_Security_Definition\r
 467 {\r
 468         ODM_SEC_OPEN                    = 0,\r
 469         ODM_SEC_WEP40           = 1,\r
 470         ODM_SEC_TKIP                    = 2,\r
 471         ODM_SEC_RESERVE                 = 3,\r
 472         ODM_SEC_AESCCMP                 = 4,\r
 473         ODM_SEC_WEP104          = 5,\r
 474         ODM_WEP_WPA_MIXED    = 6, // WEP + WPA\r
 475         ODM_SEC_SMS4                    = 7,\r
 476 }ODM_SECURITY_E;\r
 477 \r
 478 // ODM_CMNINFO_BW\r
 479 typedef enum tag_Bandwidth_Definition\r
 480 {       \r
 481         ODM_BW20M               = 0,\r
 482         ODM_BW40M               = 1,\r
 483         ODM_BW80M               = 2,\r
 484         ODM_BW160M              = 3,\r
 485         ODM_BW10M               = 4,\r
 486 }ODM_BW_E;\r
 487 \r
 488 // ODM_CMNINFO_CHNL\r
 489 \r
 490 // ODM_CMNINFO_BOARD_TYPE\r
 491 typedef enum tag_Board_Definition\r
 492 {\r
 493     ODM_BOARD_DEFAULT   = 0,      // The DEFAULT case.\r
 494     ODM_BOARD_MINICARD  = BIT(0), // 0 = non-mini card, 1= mini card.\r
 495     ODM_BOARD_SLIM      = BIT(1), // 0 = non-slim card, 1 = slim card\r
 496     ODM_BOARD_BT        = BIT(2), // 0 = without BT card, 1 = with BT\r
 497     ODM_BOARD_EXT_PA    = BIT(3), // 0 = no 2G ext-PA, 1 = existing 2G ext-PA\r
 498     ODM_BOARD_EXT_LNA   = BIT(4), // 0 = no 2G ext-LNA, 1 = existing 2G ext-LNA\r
 499     ODM_BOARD_EXT_TRSW  = BIT(5), // 0 = no ext-TRSW, 1 = existing ext-TRSW\r
 500     ODM_BOARD_EXT_PA_5G = BIT(6), // 0 = no 5G ext-PA, 1 = existing 5G ext-PA\r
 501     ODM_BOARD_EXT_LNA_5G= BIT(7), // 0 = no 5G ext-LNA, 1 = existing 5G ext-LNA\r
 502 }ODM_BOARD_TYPE_E;\r
 503 \r
 504 typedef enum tag_ODM_Package_Definition\r
 505 {\r
 506     ODM_PACKAGE_DEFAULT          = 0,     \r
 507     ODM_PACKAGE_QFN68        = BIT(0), \r
 508     ODM_PACKAGE_TFBGA90      = BIT(1), \r
 509     ODM_PACKAGE_TFBGA79      = BIT(2),  \r
 510 }ODM_Package_TYPE_E;\r
 511 \r
 512 typedef enum tag_ODM_TYPE_GPA_Definition\r
 513 {\r
 514     TYPE_GPA0 = 0,        \r
 515     TYPE_GPA1 = BIT(1)|BIT(0)\r
 516 }ODM_TYPE_GPA_E;\r
 517 \r
 518 typedef enum tag_ODM_TYPE_APA_Definition\r
 519 {\r
 520     TYPE_APA0 = 0,        \r
 521     TYPE_APA1 = BIT(1)|BIT(0)\r
 522 }ODM_TYPE_APA_E;\r
 523 \r
 524 typedef enum tag_ODM_TYPE_GLNA_Definition\r
 525 {\r
 526     TYPE_GLNA0 = 0,       \r
 527     TYPE_GLNA1 = BIT(2)|BIT(0),\r
 528     TYPE_GLNA2 = BIT(3)|BIT(1),\r
 529     TYPE_GLNA3 = BIT(3)|BIT(2)|BIT(1)|BIT(0)\r
 530 }ODM_TYPE_GLNA_E;\r
 531 \r
 532 typedef enum tag_ODM_TYPE_ALNA_Definition\r
 533 {\r
 534     TYPE_ALNA0 = 0,       \r
 535     TYPE_ALNA1 = BIT(2)|BIT(0),\r
 536     TYPE_ALNA2 = BIT(3)|BIT(1),\r
 537     TYPE_ALNA3 = BIT(3)|BIT(2)|BIT(1)|BIT(0)\r
 538 }ODM_TYPE_ALNA_E;\r
 539 \r
 540 \r
 541 typedef enum _ODM_RF_RADIO_PATH {\r
 542     ODM_RF_PATH_A = 0,   //Radio Path A\r
 543     ODM_RF_PATH_B = 1,   //Radio Path B\r
 544     ODM_RF_PATH_C = 2,   //Radio Path C\r
 545     ODM_RF_PATH_D = 3,   //Radio Path D\r
 546     ODM_RF_PATH_AB,\r
 547     ODM_RF_PATH_AC,\r
 548     ODM_RF_PATH_AD,\r
 549     ODM_RF_PATH_BC,\r
 550     ODM_RF_PATH_BD,\r
 551     ODM_RF_PATH_CD,\r
 552     ODM_RF_PATH_ABC,\r
 553     ODM_RF_PATH_ACD,\r
 554     ODM_RF_PATH_BCD,\r
 555     ODM_RF_PATH_ABCD,\r
 556   //  ODM_RF_PATH_MAX,    //Max RF number 90 support\r
 557 } ODM_RF_RADIO_PATH_E, *PODM_RF_RADIO_PATH_E;\r
 558 \r
 559 \r
 560 \r
 561 \r
 562 \r
 563 \r
 564 #endif\r