drivers/net/wireless/rockchip_wlan/rtl8723bu/hal/rtl8723b/rtl8723b_mp.c

   1 /******************************************************************************\r
   2  *\r
   3  * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.\r
   4  *\r
   5  * This program is free software; you can redistribute it and/or modify it\r
   6  * under the terms of version 2 of the GNU General Public License as\r
   7  * published by the Free Software Foundation.\r
   8  *\r
   9  * This program is distributed in the hope that it will be useful, but WITHOUT\r
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\r
  11  * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\r
  12  * more details.\r
  13  *\r
  14  * You should have received a copy of the GNU General Public License along with\r
  15  * this program; if not, write to the Free Software Foundation, Inc.,\r
  16  * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA\r
  17  *\r
  18  *\r
  19  ******************************************************************************/\r
  20 #define _RTL8723B_MP_C_\r
  21 #ifdef CONFIG_MP_INCLUDED\r
  22 \r
  23 #include <rtl8723b_hal.h>\r
  24 \r
  25 \r
  26 /*-----------------------------------------------------------------------------\r
  27  * Function:    mpt_SwitchRfSetting\r
  28  *\r
  29  * Overview:    Change RF Setting when we siwthc channel/rate/BW for MP.\r
  30  *\r
  31  * Input:               IN      PADAPTER                                pAdapter\r
  32  *\r
  33  * Output:              NONE\r
  34  *\r
  35  * Return:              NONE\r
  36  *\r
  37  * Revised History:\r
  38  * When                 Who     Remark\r
  39  * 01/08/2009   MHC     Suggestion from SD3 Willis for 92S series.\r
  40  * 01/09/2009   MHC     Add CCK modification for 40MHZ. Suggestion from SD3.\r
  41  *\r
  42  *---------------------------------------------------------------------------*/\r
  43  static void phy_SwitchRfSetting(PADAPTER        pAdapter,u8 channel )\r
  44 {\r
  45 /*\r
  46         HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);\r
  47     u32                                 u4RF_IPA[3], u4RF_TXBIAS, u4RF_SYN_G2;\r
  48 \r
  49         //default value\r
  50         {\r
  51                 u4RF_IPA[0] = 0x4F424;                  //CCK\r
  52                 u4RF_IPA[1] = 0xCF424;                  //OFDM\r
  53                 u4RF_IPA[2] = 0x8F424;                  //MCS\r
  54                 u4RF_TXBIAS = 0xC0356;\r
  55                 u4RF_SYN_G2 = 0x4F200;\r
  56         }\r
  57 \r
  58         switch(channel)\r
  59         {\r
  60                 case 1:\r
  61                         u4RF_IPA[0] = 0x4F40C;\r
  62                         u4RF_IPA[1] = 0xCF466;\r
  63                         u4RF_TXBIAS = 0xC0350;\r
  64                         break;\r
  65 \r
  66                 case 2:\r
  67                         u4RF_IPA[0] =  0x4F407;\r
  68                         u4RF_TXBIAS =  0xC0350;\r
  69                         break;\r
  70 \r
  71                 case 3:\r
  72                         u4RF_IPA[0] =  0x4F407;\r
  73                         u4RF_IPA[2] =  0x8F466;\r
  74                         u4RF_TXBIAS =  0xC0350;\r
  75                         break;\r
  76 \r
  77                 case 5:\r
  78                 case 8:\r
  79                         u4RF_SYN_G2 =  0x0F400;\r
  80                         break;\r
  81 \r
  82                 case 6:\r
  83                 case 13:\r
  84                         u4RF_IPA[0] =  0x4F40C;\r
  85                         break;\r
  86 \r
  87                 case 7:\r
  88                         u4RF_IPA[0] =  0x4F40C;\r
  89                         u4RF_SYN_G2 =  0x0F400;\r
  90                         break;\r
  91 \r
  92                 case 9:\r
  93                         u4RF_IPA[2] =  0x8F454;\r
  94                         u4RF_SYN_G2 =  0x0F400;\r
  95                         break;\r
  96 \r
  97                 case 11:\r
  98                         u4RF_IPA[0] =  0x4F40C;\r
  99                         u4RF_IPA[1] =  0xCF454;\r
 100                         u4RF_SYN_G2 =  0x0F400;\r
 101                         break;\r
 102 \r
 103                 default:\r
 104                         u4RF_IPA[0] =  0x4F424;\r
 105                         u4RF_IPA[1] =  0x8F424;\r
 106                         u4RF_IPA[2] =  0xCF424;\r
 107                         u4RF_TXBIAS =  0xC0356;\r
 108                         u4RF_SYN_G2 =  0x4F200;\r
 109                         break;\r
 110         }\r
 111 \r
 112         PHY_SetRFReg(pAdapter, RF_PATH_A, RF_IPA, bRFRegOffsetMask, u4RF_IPA[0]);\r
 113         PHY_SetRFReg(pAdapter, RF_PATH_A, RF_IPA, bRFRegOffsetMask, u4RF_IPA[1]);\r
 114         PHY_SetRFReg(pAdapter, RF_PATH_A, RF_IPA, bRFRegOffsetMask, u4RF_IPA[2]);\r
 115         PHY_SetRFReg(pAdapter, RF_PATH_A, RF_TXBIAS, bRFRegOffsetMask, u4RF_TXBIAS);\r
 116         PHY_SetRFReg(pAdapter, RF_PATH_A, RF_SYN_G2, bRFRegOffsetMask, u4RF_SYN_G2);\r
 117 */\r
 118 }\r
 119 \r
 120 void Hal_mpt_SwitchRfSetting(PADAPTER pAdapter)\r
 121 {\r
 122         HAL_DATA_TYPE           *pHalData = GET_HAL_DATA(pAdapter);\r
 123         PMPT_CONTEXT            pMptCtx = &(pAdapter->mppriv.MptCtx);\r
 124         u8                              ChannelToSw = pMptCtx->MptChannelToSw;\r
 125 \r
 126         phy_SwitchRfSetting(pAdapter, ChannelToSw);\r
 127 }\r
 128 \r
 129 s32 Hal_SetPowerTracking(PADAPTER padapter, u8 enable)\r
 130 {\r
 131         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(padapter);\r
 132         PDM_ODM_T               pDM_Odm = &(pHalData->odmpriv);\r
 133 \r
 134 \r
 135         if (!netif_running(padapter->pnetdev)) {\r
 136                 RT_TRACE(_module_mp_, _drv_warning_, ("SetPowerTracking! Fail: interface not opened!\n"));\r
 137                 return _FAIL;\r
 138         }\r
 139 \r
 140         if (check_fwstate(&padapter->mlmepriv, WIFI_MP_STATE) == _FALSE) {\r
 141                 RT_TRACE(_module_mp_, _drv_warning_, ("SetPowerTracking! Fail: not in MP mode!\n"));\r
 142                 return _FAIL;\r
 143         }\r
 144         if (enable) \r
 145                 pDM_Odm->RFCalibrateInfo.TxPowerTrackControl = _TRUE;   \r
 146         else\r
 147                 pDM_Odm->RFCalibrateInfo.TxPowerTrackControl= _FALSE;\r
 148 \r
 149         return _SUCCESS;\r
 150 }\r
 151 \r
 152 void Hal_GetPowerTracking(PADAPTER padapter, u8 *enable)\r
 153 {\r
 154         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(padapter);\r
 155         PDM_ODM_T               pDM_Odm = &(pHalData->odmpriv);\r
 156 \r
 157 \r
 158         *enable = pDM_Odm->RFCalibrateInfo.TxPowerTrackControl;\r
 159 }\r
 160 \r
 161 \r
 162 static void Hal_disable_dm(PADAPTER padapter)\r
 163 {\r
 164         u8 v8;\r
 165         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(padapter);\r
 166         PDM_ODM_T               pDM_Odm = &(pHalData->odmpriv);\r
 167 \r
 168         //3 1. disable firmware dynamic mechanism\r
 169         // disable Power Training, Rate Adaptive\r
 170         v8 = rtw_read8(padapter, REG_BCN_CTRL);\r
 171         v8 &= ~EN_BCN_FUNCTION;\r
 172         rtw_write8(padapter, REG_BCN_CTRL, v8);\r
 173 \r
 174         //3 2. disable driver dynamic mechanism\r
 175         Switch_DM_Func(padapter, DYNAMIC_FUNC_DISABLE, _FALSE);\r
 176 \r
 177         // enable APK, LCK and IQK but disable power tracking\r
 178         pDM_Odm->RFCalibrateInfo.TxPowerTrackControl = _FALSE;\r
 179         Switch_DM_Func(padapter, ODM_RF_CALIBRATION , _TRUE);\r
 180 }\r
 181 \r
 182 void Hal_MPT_CCKTxPowerAdjust(PADAPTER Adapter, BOOLEAN bInCH14)\r
 183 {\r
 184         u32             TempVal = 0, TempVal2 = 0, TempVal3 = 0;\r
 185         u32             CurrCCKSwingVal = 0, CCKSwingIndex = 12;\r
 186         u8              i;\r
 187         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(Adapter);\r
 188 \r
 189 \r
 190         // get current cck swing value and check 0xa22 & 0xa23 later to match the table.\r
 191         CurrCCKSwingVal = read_bbreg(Adapter, rCCK0_TxFilter1, bMaskHWord);\r
 192 \r
 193         if (!bInCH14)\r
 194         {\r
 195                 // Readback the current bb cck swing value and compare with the table to\r
 196                 // get the current swing index\r
 197                 for (i = 0; i < CCK_TABLE_SIZE; i++)\r
 198                 {\r
 199                         if (((CurrCCKSwingVal&0xff) == (u32)CCKSwingTable_Ch1_Ch13[i][0]) &&\r
 200                                 (((CurrCCKSwingVal&0xff00)>>8) == (u32)CCKSwingTable_Ch1_Ch13[i][1]))\r
 201                         {\r
 202                                 CCKSwingIndex = i;\r
 203 //                              RT_TRACE(COMP_INIT, DBG_LOUD,("Ch1~13, Current reg0x%x = 0x%lx, CCKSwingIndex=0x%x\n",\r
 204 //                                      (rCCK0_TxFilter1+2), CurrCCKSwingVal, CCKSwingIndex));\r
 205                                 break;\r
 206                         }\r
 207                 }\r
 208 \r
 209                 //Write 0xa22 0xa23\r
 210                 TempVal = CCKSwingTable_Ch1_Ch13[CCKSwingIndex][0] +\r
 211                                 (CCKSwingTable_Ch1_Ch13[CCKSwingIndex][1]<<8) ;\r
 212 \r
 213 \r
 214                 //Write 0xa24 ~ 0xa27\r
 215                 TempVal2 = 0;\r
 216                 TempVal2 = CCKSwingTable_Ch1_Ch13[CCKSwingIndex][2] +\r
 217                                 (CCKSwingTable_Ch1_Ch13[CCKSwingIndex][3]<<8) +\r
 218                                 (CCKSwingTable_Ch1_Ch13[CCKSwingIndex][4]<<16 )+\r
 219                                 (CCKSwingTable_Ch1_Ch13[CCKSwingIndex][5]<<24);\r
 220 \r
 221                 //Write 0xa28  0xa29\r
 222                 TempVal3 = 0;\r
 223                 TempVal3 = CCKSwingTable_Ch1_Ch13[CCKSwingIndex][6] +\r
 224                                 (CCKSwingTable_Ch1_Ch13[CCKSwingIndex][7]<<8) ;\r
 225         }\r
 226         else\r
 227         {\r
 228                 for (i = 0; i < CCK_TABLE_SIZE; i++)\r
 229                 {\r
 230                         if (((CurrCCKSwingVal&0xff) == (u32)CCKSwingTable_Ch14[i][0]) &&\r
 231                                 (((CurrCCKSwingVal&0xff00)>>8) == (u32)CCKSwingTable_Ch14[i][1]))\r
 232                         {\r
 233                                 CCKSwingIndex = i;\r
 234 //                              RT_TRACE(COMP_INIT, DBG_LOUD,("Ch14, Current reg0x%x = 0x%lx, CCKSwingIndex=0x%x\n",\r
 235 //                                      (rCCK0_TxFilter1+2), CurrCCKSwingVal, CCKSwingIndex));\r
 236                                 break;\r
 237                         }\r
 238                 }\r
 239 \r
 240                 //Write 0xa22 0xa23\r
 241                 TempVal = CCKSwingTable_Ch14[CCKSwingIndex][0] +\r
 242                                 (CCKSwingTable_Ch14[CCKSwingIndex][1]<<8) ;\r
 243 \r
 244                 //Write 0xa24 ~ 0xa27\r
 245                 TempVal2 = 0;\r
 246                 TempVal2 = CCKSwingTable_Ch14[CCKSwingIndex][2] +\r
 247                                 (CCKSwingTable_Ch14[CCKSwingIndex][3]<<8) +\r
 248                                 (CCKSwingTable_Ch14[CCKSwingIndex][4]<<16 )+\r
 249                                 (CCKSwingTable_Ch14[CCKSwingIndex][5]<<24);\r
 250 \r
 251                 //Write 0xa28  0xa29\r
 252                 TempVal3 = 0;\r
 253                 TempVal3 = CCKSwingTable_Ch14[CCKSwingIndex][6] +\r
 254                                 (CCKSwingTable_Ch14[CCKSwingIndex][7]<<8) ;\r
 255         }\r
 256 \r
 257         write_bbreg(Adapter, rCCK0_TxFilter1, bMaskHWord, TempVal);\r
 258         write_bbreg(Adapter, rCCK0_TxFilter2, bMaskDWord, TempVal2);\r
 259         write_bbreg(Adapter, rCCK0_DebugPort, bMaskLWord, TempVal3);\r
 260 }\r
 261 \r
 262 void Hal_MPT_CCKTxPowerAdjustbyIndex(PADAPTER pAdapter, BOOLEAN beven)\r
 263 {\r
 264         s32             TempCCk;\r
 265         u8              CCK_index, CCK_index_old=0;\r
 266         u8              Action = 0;     //0: no action, 1: even->odd, 2:odd->even\r
 267         u8              TimeOut = 100;\r
 268         s32             i = 0;\r
 269         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(pAdapter);\r
 270         PMPT_CONTEXT    pMptCtx = &pAdapter->mppriv.MptCtx;\r
 271 \r
 272 #if 1\r
 273         return;\r
 274 #else\r
 275         if (!IS_92C_SERIAL(pHalData->VersionID))\r
 276                 return;\r
 277 #if 0\r
 278         while(PlatformAtomicExchange(&Adapter->IntrCCKRefCount, TRUE) == TRUE)\r
 279         {\r
 280                 PlatformSleepUs(100);\r
 281                 TimeOut--;\r
 282                 if(TimeOut <= 0)\r
 283                 {\r
 284                         RTPRINT(FINIT, INIT_TxPower,\r
 285                          ("!!!MPT_CCKTxPowerAdjustbyIndex Wait for check CCK gain index too long!!!\n" ));\r
 286                         break;\r
 287                 }\r
 288         }\r
 289 #endif\r
 290         if (beven && !pMptCtx->bMptIndexEven)   //odd->even\r
 291         {\r
 292                 Action = 2;\r
 293                 pMptCtx->bMptIndexEven = _TRUE;\r
 294         }\r
 295         else if (!beven && pMptCtx->bMptIndexEven)      //even->odd\r
 296         {\r
 297                 Action = 1;\r
 298                 pMptCtx->bMptIndexEven = _FALSE;\r
 299         }\r
 300 \r
 301         if (Action != 0)\r
 302         {\r
 303                 //Query CCK default setting From 0xa24\r
 304                 TempCCk = read_bbreg(pAdapter, rCCK0_TxFilter2, bMaskDWord) & bMaskCCK;\r
 305                 for (i = 0; i < CCK_TABLE_SIZE; i++)\r
 306                 {\r
 307                         if (pHalData->dmpriv.bCCKinCH14)\r
 308                         {\r
 309                                 if (_rtw_memcmp((void*)&TempCCk, (void*)&CCKSwingTable_Ch14[i][2], 4) == _TRUE)\r
 310                                 {\r
 311                                         CCK_index_old = (u8) i;\r
 312 //                                      RTPRINT(FINIT, INIT_TxPower,("MPT_CCKTxPowerAdjustbyIndex: Initial reg0x%x = 0x%lx, CCK_index=0x%x, ch 14 %d\n",\r
 313 //                                              rCCK0_TxFilter2, TempCCk, CCK_index_old, pHalData->bCCKinCH14));\r
 314                                         break;\r
 315                                 }\r
 316                         }\r
 317                         else\r
 318                         {\r
 319                                 if (_rtw_memcmp((void*)&TempCCk, (void*)&CCKSwingTable_Ch1_Ch13[i][2], 4) == _TRUE)\r
 320                                 {\r
 321                                         CCK_index_old = (u8) i;\r
 322 //                                      RTPRINT(FINIT, INIT_TxPower,("MPT_CCKTxPowerAdjustbyIndex: Initial reg0x%x = 0x%lx, CCK_index=0x%x, ch14 %d\n",\r
 323 //                                              rCCK0_TxFilter2, TempCCk, CCK_index_old, pHalData->bCCKinCH14));\r
 324                                         break;\r
 325                                 }\r
 326                         }\r
 327                 }\r
 328 \r
 329                 if (Action == 1) {\r
 330                         if (CCK_index_old == 0)\r
 331                                 CCK_index_old = 1;\r
 332                         CCK_index = CCK_index_old - 1;\r
 333                 } else {\r
 334                         CCK_index = CCK_index_old + 1;\r
 335                 }\r
 336 \r
 337                 if (CCK_index == CCK_TABLE_SIZE) {\r
 338                         CCK_index = CCK_TABLE_SIZE -1;\r
 339                         RT_TRACE(_module_mp_, _drv_info_, ("CCK_index == CCK_TABLE_SIZE\n"));\r
 340                 }\r
 341 \r
 342 //              RTPRINT(FINIT, INIT_TxPower,("MPT_CCKTxPowerAdjustbyIndex: new CCK_index=0x%x\n",\r
 343 //                       CCK_index));\r
 344 \r
 345                 //Adjust CCK according to gain index\r
 346                 if (!pHalData->dmpriv.bCCKinCH14) {\r
 347                         rtw_write8(pAdapter, 0xa22, CCKSwingTable_Ch1_Ch13[CCK_index][0]);\r
 348                         rtw_write8(pAdapter, 0xa23, CCKSwingTable_Ch1_Ch13[CCK_index][1]);\r
 349                         rtw_write8(pAdapter, 0xa24, CCKSwingTable_Ch1_Ch13[CCK_index][2]);\r
 350                         rtw_write8(pAdapter, 0xa25, CCKSwingTable_Ch1_Ch13[CCK_index][3]);\r
 351                         rtw_write8(pAdapter, 0xa26, CCKSwingTable_Ch1_Ch13[CCK_index][4]);\r
 352                         rtw_write8(pAdapter, 0xa27, CCKSwingTable_Ch1_Ch13[CCK_index][5]);\r
 353                         rtw_write8(pAdapter, 0xa28, CCKSwingTable_Ch1_Ch13[CCK_index][6]);\r
 354                         rtw_write8(pAdapter, 0xa29, CCKSwingTable_Ch1_Ch13[CCK_index][7]);\r
 355                 } else {\r
 356                         rtw_write8(pAdapter, 0xa22, CCKSwingTable_Ch14[CCK_index][0]);\r
 357                         rtw_write8(pAdapter, 0xa23, CCKSwingTable_Ch14[CCK_index][1]);\r
 358                         rtw_write8(pAdapter, 0xa24, CCKSwingTable_Ch14[CCK_index][2]);\r
 359                         rtw_write8(pAdapter, 0xa25, CCKSwingTable_Ch14[CCK_index][3]);\r
 360                         rtw_write8(pAdapter, 0xa26, CCKSwingTable_Ch14[CCK_index][4]);\r
 361                         rtw_write8(pAdapter, 0xa27, CCKSwingTable_Ch14[CCK_index][5]);\r
 362                         rtw_write8(pAdapter, 0xa28, CCKSwingTable_Ch14[CCK_index][6]);\r
 363                         rtw_write8(pAdapter, 0xa29, CCKSwingTable_Ch14[CCK_index][7]);\r
 364                 }\r
 365         }\r
 366 #if 0\r
 367         RTPRINT(FINIT, INIT_TxPower,\r
 368         ("MPT_CCKTxPowerAdjustbyIndex 0xa20=%x\n", PlatformEFIORead4Byte(Adapter, 0xa20)));\r
 369 \r
 370         PlatformAtomicExchange(&Adapter->IntrCCKRefCount, FALSE);\r
 371 #endif\r
 372 #endif\r
 373 }\r
 374 /*---------------------------hal\rtl8192c\MPT_HelperFunc.c---------------------------*/\r
 375 \r
 376 /*\r
 377  * SetChannel\r
 378  * Description\r
 379  *      Use H2C command to change channel,\r
 380  *      not only modify rf register, but also other setting need to be done.\r
 381  */\r
 382 void Hal_SetChannel(PADAPTER pAdapter)\r
 383 {\r
 384 #if 0\r
 385         struct mp_priv *pmp = &pAdapter->mppriv;\r
 386 \r
 387 //      SelectChannel(pAdapter, pmp->channel);\r
 388         set_channel_bwmode(pAdapter, pmp->channel, pmp->channel_offset, pmp->bandwidth);\r
 389 #else\r
 390         u8              eRFPath;\r
 391 \r
 392         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(pAdapter);\r
 393         PDM_ODM_T               pDM_Odm = &(pHalData->odmpriv);\r
 394         struct mp_priv  *pmp = &pAdapter->mppriv;\r
 395         u8              channel = pmp->channel;\r
 396         u8              bandwidth = pmp->bandwidth;\r
 397         u8              rate = pmp->rateidx;\r
 398 \r
 399 \r
 400         // set RF channel register\r
 401         for (eRFPath = 0; eRFPath < pHalData->NumTotalRFPath; eRFPath++)\r
 402         {\r
 403                 _write_rfreg(pAdapter, eRFPath, rRfChannel, 0x3FF, channel);\r
 404         }\r
 405         Hal_mpt_SwitchRfSetting(pAdapter);\r
 406 \r
 407         SelectChannel(pAdapter, channel);\r
 408 \r
 409         if (pHalData->CurrentChannel == 14 && !pDM_Odm->RFCalibrateInfo.bCCKinCH14) {\r
 410                 pDM_Odm->RFCalibrateInfo.bCCKinCH14 = _TRUE;\r
 411                 Hal_MPT_CCKTxPowerAdjust(pAdapter, pDM_Odm->RFCalibrateInfo.bCCKinCH14);\r
 412         }\r
 413         else if (pHalData->CurrentChannel != 14 && pDM_Odm->RFCalibrateInfo.bCCKinCH14) {\r
 414                 pDM_Odm->RFCalibrateInfo.bCCKinCH14 = _FALSE;\r
 415                 Hal_MPT_CCKTxPowerAdjust(pAdapter, pDM_Odm->RFCalibrateInfo.bCCKinCH14);\r
 416         }\r
 417 \r
 418 #endif\r
 419 }\r
 420 \r
 421 /*\r
 422  * Notice\r
 423  *      Switch bandwitdth may change center frequency(channel)\r
 424  */\r
 425 void Hal_SetBandwidth(PADAPTER pAdapter)\r
 426 {\r
 427         struct mp_priv *pmp = &pAdapter->mppriv;\r
 428 \r
 429 \r
 430         SetBWMode(pAdapter, pmp->bandwidth, pmp->prime_channel_offset);\r
 431         Hal_mpt_SwitchRfSetting(pAdapter);\r
 432 }\r
 433 \r
 434 void Hal_SetCCKTxPower(PADAPTER pAdapter, u8 *TxPower)\r
 435 {\r
 436         u32 tmpval = 0;\r
 437 \r
 438 \r
 439         // rf-A cck tx power\r
 440         write_bbreg(pAdapter, rTxAGC_A_CCK1_Mcs32, bMaskByte1, TxPower[RF_PATH_A]);\r
 441         tmpval = (TxPower[RF_PATH_A]<<16) | (TxPower[RF_PATH_A]<<8) | TxPower[RF_PATH_A];\r
 442         write_bbreg(pAdapter, rTxAGC_B_CCK11_A_CCK2_11, bMaskH3Bytes, tmpval);\r
 443 \r
 444         // rf-B cck tx power\r
 445         write_bbreg(pAdapter, rTxAGC_B_CCK11_A_CCK2_11, bMaskByte0, TxPower[RF_PATH_B]);\r
 446         tmpval = (TxPower[RF_PATH_B]<<16) | (TxPower[RF_PATH_B]<<8) | TxPower[RF_PATH_B];\r
 447         write_bbreg(pAdapter, rTxAGC_B_CCK1_55_Mcs32, bMaskH3Bytes, tmpval);\r
 448 \r
 449         RT_TRACE(_module_mp_, _drv_notice_,\r
 450                  ("-SetCCKTxPower: A[0x%02x] B[0x%02x]\n",\r
 451                   TxPower[RF_PATH_A], TxPower[RF_PATH_B]));\r
 452 }\r
 453 \r
 454 void Hal_SetOFDMTxPower(PADAPTER pAdapter, u8 *TxPower)\r
 455 {\r
 456         u32 TxAGC = 0;\r
 457         u8 tmpval = 0;\r
 458         PMPT_CONTEXT    pMptCtx = &pAdapter->mppriv.MptCtx;\r
 459         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(pAdapter);\r
 460 \r
 461 \r
 462         // HT Tx-rf(A)\r
 463         tmpval = TxPower[RF_PATH_A];\r
 464         TxAGC = (tmpval<<24) | (tmpval<<16) | (tmpval<<8) | tmpval;\r
 465 \r
 466         write_bbreg(pAdapter, rTxAGC_A_Rate18_06, bMaskDWord, TxAGC);\r
 467         write_bbreg(pAdapter, rTxAGC_A_Rate54_24, bMaskDWord, TxAGC);\r
 468         write_bbreg(pAdapter, rTxAGC_A_Mcs03_Mcs00, bMaskDWord, TxAGC);\r
 469         write_bbreg(pAdapter, rTxAGC_A_Mcs07_Mcs04, bMaskDWord, TxAGC);\r
 470         write_bbreg(pAdapter, rTxAGC_A_Mcs11_Mcs08, bMaskDWord, TxAGC);\r
 471         write_bbreg(pAdapter, rTxAGC_A_Mcs15_Mcs12, bMaskDWord, TxAGC);\r
 472 \r
 473         // HT Tx-rf(B)\r
 474         tmpval = TxPower[RF_PATH_B];\r
 475         TxAGC = (tmpval<<24) | (tmpval<<16) | (tmpval<<8) | tmpval;\r
 476 \r
 477         write_bbreg(pAdapter, rTxAGC_B_Rate18_06, bMaskDWord, TxAGC);\r
 478         write_bbreg(pAdapter, rTxAGC_B_Rate54_24, bMaskDWord, TxAGC);\r
 479         write_bbreg(pAdapter, rTxAGC_B_Mcs03_Mcs00, bMaskDWord, TxAGC);\r
 480         write_bbreg(pAdapter, rTxAGC_B_Mcs07_Mcs04, bMaskDWord, TxAGC);\r
 481         write_bbreg(pAdapter, rTxAGC_B_Mcs11_Mcs08, bMaskDWord, TxAGC);\r
 482         write_bbreg(pAdapter, rTxAGC_B_Mcs15_Mcs12, bMaskDWord, TxAGC);\r
 483 \r
 484         RT_TRACE(_module_mp_, _drv_notice_,\r
 485                  ("-SetOFDMTxPower: A[0x%02x] B[0x%02x]\n",\r
 486                   TxPower[RF_PATH_A], TxPower[RF_PATH_B]));\r
 487 }\r
 488 \r
 489 void Hal_SetAntennaPathPower(PADAPTER pAdapter)\r
 490 {\r
 491         HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);\r
 492         u8 TxPowerLevel[MAX_RF_PATH_NUMS];\r
 493         u8 rfPath;\r
 494 \r
 495         TxPowerLevel[RF_PATH_A] = pAdapter->mppriv.txpoweridx;\r
 496         TxPowerLevel[RF_PATH_B] = pAdapter->mppriv.txpoweridx_b;\r
 497 \r
 498         switch (pAdapter->mppriv.antenna_tx)\r
 499         {\r
 500                 case ANTENNA_A:\r
 501                 default:\r
 502                         rfPath = RF_PATH_A;\r
 503                         break;\r
 504                 case ANTENNA_B:\r
 505                         rfPath = RF_PATH_B;\r
 506                         break;\r
 507                 case ANTENNA_C:\r
 508                         rfPath = RF_PATH_C;\r
 509                         break;\r
 510         }\r
 511 \r
 512         switch (pHalData->rf_chip)\r
 513         {\r
 514                 case RF_8225:\r
 515                 case RF_8256:\r
 516                 case RF_6052:\r
 517                         Hal_SetCCKTxPower(pAdapter, TxPowerLevel);\r
 518                         if (pAdapter->mppriv.rateidx < MPT_RATE_6M)     // CCK rate\r
 519                                 Hal_MPT_CCKTxPowerAdjustbyIndex(pAdapter, TxPowerLevel[rfPath]%2 == 0);\r
 520                         Hal_SetOFDMTxPower(pAdapter, TxPowerLevel);\r
 521                         break;\r
 522 \r
 523                 default:\r
 524                         break;\r
 525         }\r
 526 }\r
 527 \r
 528 \r
 529 \r
 530 void \r
 531 mpt_SetTxPower(\r
 532         IN      PADAPTER                pAdapter,\r
 533         IN      MPT_TXPWR_DEF   Rate,\r
 534         IN      pu1Byte                 pTxPower\r
 535         )\r
 536 {\r
 537         if (IS_HARDWARE_TYPE_JAGUAR(pAdapter))\r
 538         {\r
 539                 //mpt_SetTxPower_8812(pAdapter, Rate, pTxPower);\r
 540                 return;\r
 541         }\r
 542         \r
 543         \r
 544         switch (Rate)\r
 545         {\r
 546                 case MPT_CCK:\r
 547                 {\r
 548                         u4Byte  TxAGC = 0, pwr=0;\r
 549                         u1Byte  rf;\r
 550 \r
 551                         pwr = pTxPower[ODM_RF_PATH_A];\r
 552                         TxAGC = (pwr<<16)|(pwr<<8)|(pwr);\r
 553                         PHY_SetBBReg(pAdapter, rTxAGC_A_CCK1_Mcs32, bMaskByte1, pTxPower[ODM_RF_PATH_A]);\r
 554                         PHY_SetBBReg(pAdapter, rTxAGC_B_CCK11_A_CCK2_11, bMaskH3Bytes, TxAGC);\r
 555 \r
 556                         pwr = pTxPower[ODM_RF_PATH_B];\r
 557                         TxAGC = (pwr<<16)|(pwr<<8)|(pwr);\r
 558                         PHY_SetBBReg(pAdapter, rTxAGC_B_CCK11_A_CCK2_11, bMaskByte0, pTxPower[ODM_RF_PATH_B]);\r
 559                         PHY_SetBBReg(pAdapter, rTxAGC_B_CCK1_55_Mcs32, bMaskH3Bytes, TxAGC);\r
 560                         \r
 561                 } break;\r
 562                 \r
 563                 case MPT_OFDM:\r
 564 {\r
 565                         u4Byte  TxAGC=0;\r
 566                         u1Byte  pwr=0, rf;\r
 567                         PMPT_CONTEXT    pMptCtx = &(pAdapter->mppriv.MptCtx);           \r
 568         HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);\r
 569 \r
 570                         pwr = pTxPower[0];\r
 571                         TxAGC |= ((pwr<<24)|(pwr<<16)|(pwr<<8)|pwr);\r
 572                         DBG_8192C("HT Tx-rf(A) Power = 0x%x\n", TxAGC);\r
 573                         \r
 574                         PHY_SetBBReg(pAdapter, rTxAGC_A_Rate18_06, bMaskDWord, TxAGC);\r
 575                         PHY_SetBBReg(pAdapter, rTxAGC_A_Rate54_24, bMaskDWord, TxAGC);\r
 576                         PHY_SetBBReg(pAdapter, rTxAGC_A_Mcs03_Mcs00, bMaskDWord, TxAGC);\r
 577                         PHY_SetBBReg(pAdapter, rTxAGC_A_Mcs07_Mcs04, bMaskDWord, TxAGC);\r
 578                         PHY_SetBBReg(pAdapter, rTxAGC_A_Mcs11_Mcs08, bMaskDWord, TxAGC);\r
 579                         PHY_SetBBReg(pAdapter, rTxAGC_A_Mcs15_Mcs12, bMaskDWord, TxAGC);\r
 580                         \r
 581                         TxAGC=0;\r
 582                         pwr = pTxPower[1];\r
 583                         TxAGC |= ((pwr<<24)|(pwr<<16)|(pwr<<8)|pwr);\r
 584                         DBG_8192C("HT Tx-rf(B) Power = 0x%x\n", TxAGC);\r
 585                         \r
 586                         PHY_SetBBReg(pAdapter, rTxAGC_B_Rate18_06, bMaskDWord, TxAGC);\r
 587                         PHY_SetBBReg(pAdapter, rTxAGC_B_Rate54_24, bMaskDWord, TxAGC);\r
 588                         PHY_SetBBReg(pAdapter, rTxAGC_B_Mcs03_Mcs00, bMaskDWord, TxAGC);\r
 589                         PHY_SetBBReg(pAdapter, rTxAGC_B_Mcs07_Mcs04, bMaskDWord, TxAGC);\r
 590                         PHY_SetBBReg(pAdapter, rTxAGC_B_Mcs11_Mcs08, bMaskDWord, TxAGC);\r
 591                         PHY_SetBBReg(pAdapter, rTxAGC_B_Mcs15_Mcs12, bMaskDWord, TxAGC);\r
 592                         \r
 593                 } break;\r
 594 \r
 595                 default:\r
 596                         break;\r
 597                         \r
 598         }\r
 599         \r
 600         }\r
 601 \r
 602 void Hal_SetTxPower(PADAPTER pAdapter)\r
 603 {\r
 604         HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);\r
 605         PMPT_CONTEXT            pMptCtx = &(pAdapter->mppriv.MptCtx);\r
 606         PDM_ODM_T               pDM_Odm = &pHalData->odmpriv;\r
 607         u8 TxPowerLevel[MAX_RF_PATH];\r
 608         u1Byte                          path;\r
 609         \r
 610         //#if DEV_BUS_TYPE == RT_USB_INTERFACE || DEV_BUS_TYPE == RT_SDIO_INTERFACE\r
 611                 //RT_ASSERT((KeGetCurrentIrql() == PASSIVE_LEVEL), ("MPT_ProSetTxPower(): not in PASSIVE_LEVEL!\n"));\r
 612         //#endif\r
 613         \r
 614         path = (pHalData->AntennaTxPath == ANTENNA_A) ? (ODM_RF_PATH_A) : (ODM_RF_PATH_B);\r
 615                 \r
 616                 if (pHalData->rf_chip < RF_TYPE_MAX)\r
 617                 {\r
 618                         if (IS_HARDWARE_TYPE_JAGUAR(pAdapter))\r
 619         {\r
 620 \r
 621                                 DBG_8192C("===> MPT_ProSetTxPower: Jaguar\n");\r
 622                                 /*\r
 623                                         mpt_SetTxPower_8812(pAdapter, MPT_CCK, pMptCtx->TxPwrLevel);\r
 624                                         mpt_SetTxPower_8812(pAdapter, MPT_OFDM, pMptCtx->TxPwrLevel);\r
 625                                         mpt_SetTxPower_8812(pAdapter, MPT_VHT_OFDM, pMptCtx->TxPwrLevel);\r
 626                                         */\r
 627                         }\r
 628                         else \r
 629                         {\r
 630                                 DBG_8192C("===> MPT_ProSetTxPower: Others\n");\r
 631                                 mpt_SetTxPower(pAdapter, MPT_CCK, pMptCtx->TxPwrLevel);\r
 632                                 Hal_MPT_CCKTxPowerAdjustbyIndex(pAdapter, pMptCtx->TxPwrLevel[path]%2 == 0);            \r
 633                                 mpt_SetTxPower(pAdapter, MPT_OFDM, pMptCtx->TxPwrLevel);\r
 634                         }\r
 635                 }\r
 636                 else\r
 637                 {\r
 638                    DBG_8192C("RFChipID < RF_TYPE_MAX, the RF chip is not supported - %d\n", pHalData->rf_chip);\r
 639         }\r
 640 \r
 641                 ODM_ClearTxPowerTrackingState(pDM_Odm);\r
 642 \r
 643 }\r
 644 \r
 645 void Hal_SetTxAGCOffset(PADAPTER pAdapter, u32 ulTxAGCOffset)\r
 646 {\r
 647 #if 0\r
 648         u32 TxAGCOffset_B, TxAGCOffset_C, TxAGCOffset_D,tmpAGC;\r
 649 \r
 650 \r
 651         TxAGCOffset_B = (ulTxAGCOffset&0x000000ff);\r
 652         TxAGCOffset_C = ((ulTxAGCOffset&0x0000ff00)>>8);\r
 653         TxAGCOffset_D = ((ulTxAGCOffset&0x00ff0000)>>16);\r
 654 \r
 655         tmpAGC = (TxAGCOffset_D<<8 | TxAGCOffset_C<<4 | TxAGCOffset_B);\r
 656         write_bbreg(pAdapter, rFPGA0_TxGainStage,\r
 657                         (bXBTxAGC|bXCTxAGC|bXDTxAGC), tmpAGC);\r
 658 #endif\r
 659 }\r
 660 \r
 661 void Hal_SetDataRate(PADAPTER pAdapter)\r
 662 {\r
 663         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(pAdapter);\r
 664         PMPT_CONTEXT            pMptCtx = &(pAdapter->mppriv.MptCtx);\r
 665         u32 DataRate;\r
 666         \r
 667         DataRate=MptToMgntRate(pAdapter->mppriv.rateidx);\r
 668         \r
 669                 Hal_mpt_SwitchRfSetting(pAdapter);\r
 670                 if (IS_CCK_RATE(DataRate))\r
 671                 {\r
 672                         if (pMptCtx->MptRfPath == ODM_RF_PATH_A) // S1\r
 673                                 PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, 0x51, 0xF, 0x6);  \r
 674                         else // S0\r
 675                                 PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, 0x71, 0xF, 0x6);\r
 676                 }\r
 677                 else\r
 678                 {\r
 679                         if (pMptCtx->MptRfPath == ODM_RF_PATH_A) // S1\r
 680                                 PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, 0x51, 0xF, 0xE);  \r
 681                         else // S0\r
 682                                 PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, 0x71, 0xF, 0xE);          \r
 683                 }\r
 684 \r
 685         // <20130913, Kordan> 8723BS TFBGA uses the default setting.\r
 686         if ((IS_HARDWARE_TYPE_8723BS(pAdapter) && \r
 687                   ((pHalData->PackageType == PACKAGE_TFBGA79) || (pHalData->PackageType == PACKAGE_TFBGA90))))\r
 688         {\r
 689                 if (pMptCtx->MptRfPath == ODM_RF_PATH_A) // S1\r
 690                         PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, 0x51, 0xF, 0xE);  \r
 691                 else // S0\r
 692                         PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, 0x71, 0xF, 0xE);                  \r
 693         }\r
 694 }\r
 695 \r
 696 #define RF_PATH_AB      22\r
 697 \r
 698 void Hal_SetAntenna(PADAPTER pAdapter)\r
 699 {\r
 700         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(pAdapter);\r
 701         u4Byte                                  ulAntennaTx, ulAntennaRx;\r
 702         PMPT_CONTEXT            pMptCtx = &(pAdapter->mppriv.MptCtx);\r
 703         PDM_ODM_T               pDM_Odm = &pHalData->odmpriv;\r
 704         PODM_RF_CAL_T                   pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo);\r
 705 \r
 706         ulAntennaTx = pHalData->AntennaTxPath;\r
 707         ulAntennaRx = pHalData->AntennaRxPath;\r
 708 \r
 709         if (pHalData->rf_chip>= RF_TYPE_MAX)\r
 710         {\r
 711                 DBG_8192C("This RF chip ID is not supported\n");\r
 712                 return ;\r
 713         }\r
 714 \r
 715         switch (pAdapter->mppriv.antenna_tx)\r
 716         {\r
 717                 u1Byte p = 0, i = 0;\r
 718 \r
 719             case ANTENNA_A: // Actually path S1  (Wi-Fi)\r
 720                         {\r
 721                                 pMptCtx->MptRfPath = ODM_RF_PATH_A;                     \r
 722                                 PHY_SetBBReg(pAdapter, rS0S1_PathSwitch, BIT9|BIT8|BIT7, 0x0);\r
 723                                 PHY_SetBBReg(pAdapter, 0xB2C, BIT31, 0x0); // AGC Table Sel\r
 724 \r
 725                                 //<20130522, Kordan> 0x51 and 0x71 should be set immediately after path switched, or they might be overwritten.\r
 726                                 if ((pHalData->PackageType == PACKAGE_TFBGA79) || (pHalData->PackageType == PACKAGE_TFBGA90))\r
 727                                         PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, 0x51, bRFRegOffsetMask, 0x6B10E);\r
 728                                 else\r
 729                                         PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, 0x51, bRFRegOffsetMask, 0x6B04E);\r
 730 \r
 731 \r
 732                                 for (i = 0; i < 3; ++i)\r
 733                                 {\r
 734                                         u4Byte offset = pRFCalibrateInfo->TxIQC_8723B[ODM_RF_PATH_A][i][0];\r
 735                                          u4Byte data = pRFCalibrateInfo->TxIQC_8723B[ODM_RF_PATH_A][i][1];\r
 736                                         if (offset != 0) {\r
 737                                                 PHY_SetBBReg(pAdapter, offset, bMaskDWord, data);\r
 738                                                 DBG_8192C("Switch to S1 TxIQC(offset, data) = (0x%X, 0x%X)\n", offset, data);\r
 739                                         }\r
 740 \r
 741                                 }\r
 742                                  for (i = 0; i < 2; ++i)\r
 743                                 {\r
 744                                         u4Byte offset = pRFCalibrateInfo->RxIQC_8723B[ODM_RF_PATH_A][i][0];\r
 745                                         u4Byte data = pRFCalibrateInfo->RxIQC_8723B[ODM_RF_PATH_A][i][1];\r
 746                                         if (offset != 0) {\r
 747                                                 PHY_SetBBReg(pAdapter, offset, bMaskDWord, data);                                       \r
 748                                                 DBG_8192C("Switch to S1 RxIQC (offset, data) = (0x%X, 0x%X)\n", offset, data);\r
 749                                         }\r
 750                                 }\r
 751                         }\r
 752                 break;\r
 753                 case ANTENNA_B: // Actually path S0 (BT)\r
 754                         {\r
 755                                 pMptCtx->MptRfPath = ODM_RF_PATH_B;\r
 756                                 PHY_SetBBReg(pAdapter, rS0S1_PathSwitch, BIT9|BIT8|BIT7, 0x5);\r
 757                                 PHY_SetBBReg(pAdapter, 0xB2C, BIT31, 0x1); // AGC Table Sel\r
 758                                 \r
 759                                 //<20130522, Kordan> 0x51 and 0x71 should be set immediately after path switched, or they might be overwritten.\r
 760                                 if ((pHalData->PackageType == PACKAGE_TFBGA79) || (pHalData->PackageType == PACKAGE_TFBGA90))\r
 761                                                 PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, 0x51, bRFRegOffsetMask, 0x6B10E);\r
 762                                 else\r
 763                                                 PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, 0x51, bRFRegOffsetMask, 0x6B04E);\r
 764 \r
 765 \r
 766                                 for (i = 0; i < 3; ++i)\r
 767                                 {\r
 768                                          // <20130603, Kordan> Because BB suppors only 1T1R, we restore IQC  to S1 instead of S0.\r
 769                                          u4Byte offset = pRFCalibrateInfo->TxIQC_8723B[ODM_RF_PATH_A][i][0];\r
 770                                          u4Byte data = pRFCalibrateInfo->TxIQC_8723B[ODM_RF_PATH_B][i][1];\r
 771                                         if (pRFCalibrateInfo->TxIQC_8723B[ODM_RF_PATH_B][i][0] != 0) {\r
 772                                          PHY_SetBBReg(pAdapter, offset, bMaskDWord, data);\r
 773                                          DBG_8192C("Switch to S0 TxIQC (offset, data) = (0x%X, 0x%X)\n", offset, data);\r
 774                                         }\r
 775                                 }\r
 776                                 for (i = 0; i < 2; ++i)\r
 777                                 {\r
 778                                          // <20130603, Kordan> Because BB suppors only 1T1R, we restore IQC to S1 instead of S0.\r
 779                                          u4Byte offset = pRFCalibrateInfo->RxIQC_8723B[ODM_RF_PATH_A][i][0];\r
 780                                          u4Byte data = pRFCalibrateInfo->RxIQC_8723B[ODM_RF_PATH_B][i][1];\r
 781                                         if (pRFCalibrateInfo->RxIQC_8723B[ODM_RF_PATH_B][i][0] != 0) {\r
 782                                                 PHY_SetBBReg(pAdapter, offset, bMaskDWord, data);\r
 783                                                 DBG_8192C("Switch to S0 RxIQC (offset, data) = (0x%X, 0x%X)\n", offset, data);\r
 784                                         }\r
 785                                 }\r
 786 \r
 787                         }\r
 788                         break;\r
 789                 default:\r
 790                         pMptCtx->MptRfPath = RF_PATH_AB; \r
 791            RT_TRACE(_module_mp_, _drv_notice_, ("Unknown Tx antenna.\n"));\r
 792                         break;\r
 793         }\r
 794 \r
 795         RT_TRACE(_module_mp_, _drv_notice_, ("-SwitchAntenna: finished\n"));\r
 796 }\r
 797 \r
 798 s32 Hal_SetThermalMeter(PADAPTER pAdapter, u8 target_ther)\r
 799 {\r
 800         HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);\r
 801 \r
 802 \r
 803         if (!netif_running(pAdapter->pnetdev)) {\r
 804                 RT_TRACE(_module_mp_, _drv_warning_, ("SetThermalMeter! Fail: interface not opened!\n"));\r
 805                 return _FAIL;\r
 806         }\r
 807 \r
 808         if (check_fwstate(&pAdapter->mlmepriv, WIFI_MP_STATE) == _FALSE) {\r
 809                 RT_TRACE(_module_mp_, _drv_warning_, ("SetThermalMeter: Fail! not in MP mode!\n"));\r
 810                 return _FAIL;\r
 811         }\r
 812 \r
 813         target_ther &= 0xff;\r
 814         if (target_ther < 0x07)\r
 815                 target_ther = 0x07;\r
 816         else if (target_ther > 0x1d)\r
 817                 target_ther = 0x1d;\r
 818 \r
 819         pHalData->EEPROMThermalMeter = target_ther;\r
 820 \r
 821         return _SUCCESS;\r
 822 }\r
 823 \r
 824 void Hal_TriggerRFThermalMeter(PADAPTER pAdapter)\r
 825 {\r
 826         PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, RF_T_METER_8723B, BIT17 | BIT16, 0x03);\r
 827 //      RT_TRACE(_module_mp_,_drv_alert_, ("TriggerRFThermalMeter() finished.\n" ));\r
 828 }\r
 829 \r
 830 u8 Hal_ReadRFThermalMeter(PADAPTER pAdapter)\r
 831 {\r
 832         u32 ThermalValue = 0;\r
 833 \r
 834         ThermalValue = (u1Byte)PHY_QueryRFReg(pAdapter, ODM_RF_PATH_A, RF_T_METER_8723B, 0xfc00);       // 0x42: RF Reg[15:10]                                  \r
 835 \r
 836         return (u8)ThermalValue;\r
 837 }\r
 838 \r
 839 void Hal_GetThermalMeter(PADAPTER pAdapter, u8 *value)\r
 840 {\r
 841 #if 0\r
 842         fw_cmd(pAdapter, IOCMD_GET_THERMAL_METER);\r
 843         rtw_msleep_os(1000);\r
 844         fw_cmd_data(pAdapter, value, 1);\r
 845         *value &= 0xFF;\r
 846 #else\r
 847 \r
 848         Hal_TriggerRFThermalMeter(pAdapter);\r
 849         rtw_msleep_os(1000);\r
 850         *value = Hal_ReadRFThermalMeter(pAdapter);\r
 851 #endif\r
 852 }\r
 853 \r
 854 void Hal_SetSingleCarrierTx(PADAPTER pAdapter, u8 bStart)\r
 855 {\r
 856     HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);\r
 857         pAdapter->mppriv.MptCtx.bSingleCarrier = bStart;\r
 858         if (bStart)// Start Single Carrier.\r
 859         {\r
 860                 RT_TRACE(_module_mp_,_drv_alert_, ("SetSingleCarrierTx: test start\n"));\r
 861                 // Start Single Carrier.\r
 862                 // 1. if OFDM block on?\r
 863                 if(!PHY_QueryBBReg(pAdapter, rFPGA0_RFMOD, bOFDMEn))\r
 864                         PHY_SetBBReg(pAdapter, rFPGA0_RFMOD, bOFDMEn, 1);//set OFDM block on\r
 865 \r
 866                 // 2. set CCK test mode off, set to CCK normal mode\r
 867                 PHY_SetBBReg(pAdapter, rCCK0_System, bCCKBBMode, 0);\r
 868 \r
 869                 // 3. turn on scramble setting\r
 870                 PHY_SetBBReg(pAdapter, rCCK0_System, bCCKScramble, 1);\r
 871 \r
 872                 // 4. Turn On Continue Tx and turn off the other test modes.\r
 873                 //if (IS_HARDWARE_TYPE_JAGUAR(pAdapter))\r
 874                         //PHY_SetBBReg(pAdapter, rSingleTone_ContTx_Jaguar, BIT18|BIT17|BIT16, OFDM_SingleCarrier);\r
 875                 //else\r
 876                 PHY_SetBBReg(pAdapter, rOFDM1_LSTF, BIT30|BIT29|BIT28, OFDM_SingleCarrier);\r
 877         }\r
 878         else// Stop Single Carrier.\r
 879         {\r
 880                 // Stop Single Carrier.\r
 881                 // Turn off all test modes.\r
 882                 //if (IS_HARDWARE_TYPE_JAGUAR(pAdapter))\r
 883                 //      PHY_SetBBReg(pAdapter, rSingleTone_ContTx_Jaguar, BIT18|BIT17|BIT16, OFDM_ALL_OFF);\r
 884                 //else\r
 885                 PHY_SetBBReg(pAdapter, rOFDM1_LSTF, BIT30|BIT29|BIT28, OFDM_ALL_OFF);\r
 886             //Delay 10 ms\r
 887                 rtw_msleep_os(10);\r
 888                 //BB Reset\r
 889             PHY_SetBBReg(pAdapter, rPMAC_Reset, bBBResetB, 0x0);\r
 890             PHY_SetBBReg(pAdapter, rPMAC_Reset, bBBResetB, 0x1);\r
 891         }\r
 892 }\r
 893 \r
 894 \r
 895 void Hal_SetSingleToneTx(PADAPTER pAdapter, u8 bStart)\r
 896 {\r
 897         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(pAdapter);\r
 898         PMPT_CONTEXT            pMptCtx = &(pAdapter->mppriv.MptCtx);\r
 899         static u4Byte       reg58 = 0x0;\r
 900         static u4Byte       regRF0x0 = 0x0;\r
 901     static u4Byte       reg0xCB0 = 0x0;\r
 902     static u4Byte       reg0xEB0 = 0x0;\r
 903     static u4Byte       reg0xCB4 = 0x0;\r
 904     static u4Byte       reg0xEB4 = 0x0;\r
 905         u8 rfPath;\r
 906 \r
 907         switch (pAdapter->mppriv.antenna_tx)\r
 908         {\r
 909                 case ANTENNA_A:\r
 910                 default:\r
 911                         pMptCtx->MptRfPath = rfPath = RF_PATH_A;\r
 912                         break;\r
 913                 case ANTENNA_B:\r
 914                         pMptCtx->MptRfPath = rfPath = RF_PATH_B;\r
 915                         break;\r
 916                 case ANTENNA_C:\r
 917                         pMptCtx->MptRfPath = rfPath = RF_PATH_C;\r
 918                         break;\r
 919         }\r
 920 \r
 921         pAdapter->mppriv.MptCtx.bSingleTone = bStart;\r
 922         if (bStart)// Start Single Tone.\r
 923         {\r
 924 \r
 925                 // <20120326, Kordan> To amplify the power of tone for Xtal calibration. (asked by Edlu)\r
 926                 if (IS_HARDWARE_TYPE_8188E(pAdapter))\r
 927                  {\r
 928                         reg58 = PHY_QueryRFReg(pAdapter, rfPath, LNA_Low_Gain_3, bRFRegOffsetMask);\r
 929                         if (rfPath == ODM_RF_PATH_A) \r
 930                                 pMptCtx->backup0x58_RF_A = reg58; \r
 931                         else\r
 932                                 pMptCtx->backup0x58_RF_B = reg58;\r
 933                         \r
 934                         PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, LNA_Low_Gain_3, BIT1, 0x1); // RF LO enabled              \r
 935                         PHY_SetBBReg(pAdapter, rFPGA0_RFMOD, bCCKEn, 0x0);\r
 936                         PHY_SetBBReg(pAdapter, rFPGA0_RFMOD, bOFDMEn, 0x0);\r
 937                 \r
 938                 \r
 939                 }\r
 940                 else if (IS_HARDWARE_TYPE_8192E(pAdapter))\r
 941                 { // USB need to do RF LO disable first, PCIE isn't required to follow this order.\r
 942                         PHY_SetRFReg(pAdapter, pMptCtx->MptRfPath, LNA_Low_Gain_3, BIT1, 0x1); // RF LO disabled\r
 943                         PHY_SetRFReg(pAdapter, pMptCtx->MptRfPath, RF_AC, 0xF0000, 0x2); // Tx mode\r
 944                 }                       \r
 945                 else if (IS_HARDWARE_TYPE_8723B(pAdapter))\r
 946                 {\r
 947                         if (pMptCtx->MptRfPath == ODM_RF_PATH_A) {\r
 948                                 PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, RF_AC, 0xF0000, 0x2); // Tx mode\r
 949                                 PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, 0x56, 0xF, 0x1); // RF LO enabled\r
 950                         } else { \r
 951                                 // S0/S1 both use PATH A to configure\r
 952                                 PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, RF_AC, 0xF0000, 0x2); // Tx mode\r
 953                                 PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, 0x76, 0xF, 0x1); // RF LO enabled\r
 954                         }\r
 955                 }\r
 956                 else if (IS_HARDWARE_TYPE_JAGUAR(pAdapter)) \r
 957                 {\r
 958                         /*\r
 959                         u1Byte p = ODM_RF_PATH_A;\r
 960                 \r
 961                         regRF0x0 = PHY_QueryRFReg(pAdapter, ODM_RF_PATH_A, RF_AC_Jaguar, bRFRegOffsetMask);\r
 962                         reg0xCB0 = PHY_QueryBBReg(pAdapter, rA_RFE_Pinmux_Jaguar, bMaskDWord);\r
 963                         reg0xEB0 = PHY_QueryBBReg(pAdapter, rB_RFE_Pinmux_Jaguar, bMaskDWord);\r
 964                         reg0xCB4 = PHY_QueryBBReg(pAdapter, rA_RFE_Pinmux_Jaguar+4, bMaskDWord);\r
 965                         reg0xEB4 = PHY_QueryBBReg(pAdapter, rB_RFE_Pinmux_Jaguar+4, bMaskDWord);\r
 966                         \r
 967                         PHY_SetBBReg(pAdapter, rOFDMCCKEN_Jaguar, BIT29|BIT28, 0x0); // Disable CCK and OFDM\r
 968                 \r
 969                         if (pMptCtx->MptRfPath == RF_PATH_AB) {\r
 970                                 for (p = ODM_RF_PATH_A; p <= ODM_RF_PATH_B; ++p) {                                      \r
 971                                         PHY_SetRFReg(pAdapter, p, RF_AC_Jaguar, 0xF0000, 0x2); // Tx mode: RF0x00[19:16]=4'b0010 \r
 972                                         PHY_SetRFReg(pAdapter, p, RF_AC_Jaguar, 0x1F, 0x0); // Lowest RF gain index: RF_0x0[4:0] = 0\r
 973                                         PHY_SetRFReg(pAdapter, p, LNA_Low_Gain_3, BIT1, 0x1); // RF LO enabled\r
 974                                 }\r
 975                         } else {\r
 976                                 PHY_SetRFReg(pAdapter, pMptCtx->MptRfPath, RF_AC_Jaguar, 0xF0000, 0x2); // Tx mode: RF0x00[19:16]=4'b0010 \r
 977                                 PHY_SetRFReg(pAdapter, pMptCtx->MptRfPath, RF_AC_Jaguar, 0x1F, 0x0); // Lowest RF gain index: RF_0x0[4:0] = 0\r
 978                                 PHY_SetRFReg(pAdapter, pMptCtx->MptRfPath, LNA_Low_Gain_3, BIT1, 0x1); // RF LO enabled\r
 979                         }\r
 980                         \r
 981                 \r
 982                         PHY_SetBBReg(pAdapter, rA_RFE_Pinmux_Jaguar, 0xFF00F0, 0x77007);  // 0xCB0[[23:16, 7:4] = 0x77007\r
 983                         PHY_SetBBReg(pAdapter, rB_RFE_Pinmux_Jaguar, 0xFF00F0, 0x77007);  // 0xCB0[[23:16, 7:4] = 0x77007\r
 984                 \r
 985                         if (pHalData->ExternalPA_5G) {\r
 986                 \r
 987                                 PHY_SetBBReg(pAdapter, rA_RFE_Pinmux_Jaguar+4, 0xFF00000, 0x12); // 0xCB4[23:16] = 0x12\r
 988                                 PHY_SetBBReg(pAdapter, rB_RFE_Pinmux_Jaguar+4, 0xFF00000, 0x12); // 0xEB4[23:16] = 0x12\r
 989                         } else if (pHalData->ExternalPA_2G) {\r
 990                                 PHY_SetBBReg(pAdapter, rA_RFE_Pinmux_Jaguar+4, 0xFF00000, 0x11); // 0xCB4[23:16] = 0x11\r
 991                                 PHY_SetBBReg(pAdapter, rB_RFE_Pinmux_Jaguar+4, 0xFF00000, 0x11); // 0xEB4[23:16] = 0x11\r
 992                         }\r
 993                         */\r
 994                 }\r
 995                 else\r
 996                 {\r
 997                         // Turn On SingleTone and turn off the other test modes.\r
 998                         PHY_SetBBReg(pAdapter, rOFDM1_LSTF, BIT30|BIT29|BIT28, OFDM_SingleTone);                        \r
 999                 }\r
1000 \r
1001 \r
1002                 write_bbreg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000500);\r
1003                 write_bbreg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000500);\r
1004 \r
1005         }\r
1006         else// Stop Single Tone.\r
1007         {\r
1008         // Stop Single Tone.\r
1009                 if (IS_HARDWARE_TYPE_8188E(pAdapter))\r
1010                 {\r
1011             PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, LNA_Low_Gain_3, bRFRegOffsetMask, pMptCtx->backup0x58_RF_A);\r
1012                         \r
1013                 PHY_SetBBReg(pAdapter, rFPGA0_RFMOD, bCCKEn, 0x1);\r
1014                 PHY_SetBBReg(pAdapter, rFPGA0_RFMOD, bOFDMEn, 0x1);\r
1015                 }               \r
1016                 else if (IS_HARDWARE_TYPE_8192E(pAdapter))\r
1017                 {\r
1018                         PHY_SetRFReg(pAdapter, pMptCtx->MptRfPath, RF_AC, 0xF0000, 0x3); // Tx mode\r
1019                         PHY_SetRFReg(pAdapter, pMptCtx->MptRfPath, LNA_Low_Gain_3, BIT1, 0x0); // RF LO disabled        \r
1020                 }                                               \r
1021                 else if (IS_HARDWARE_TYPE_8723B(pAdapter))\r
1022                 {\r
1023                         if (pMptCtx->MptRfPath == ODM_RF_PATH_A) {\r
1024                                 PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, RF_AC, 0xF0000, 0x3); // Rx mode\r
1025                                 PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, 0x56, 0xF, 0x0); // RF LO disabled\r
1026                         } else {\r
1027                                 // S0/S1 both use PATH A to configure\r
1028                                 PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, RF_AC, 0xF0000, 0x3); // Rx mode\r
1029                                 PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, 0x76, 0xF, 0x0); // RF LO disabled\r
1030                         }       \r
1031                 }               \r
1032         else if (IS_HARDWARE_TYPE_JAGUAR(pAdapter)) \r
1033                 {\r
1034                         /*\r
1035                         u1Byte p = ODM_RF_PATH_A;\r
1036 \r
1037                         PHY_SetBBReg(pAdapter, rOFDMCCKEN_Jaguar, BIT29|BIT28, 0x3); // Disable CCK and OFDM\r
1038 \r
1039                         if (pMptCtx->MptRfPath == RF_PATH_AB) {\r
1040                                 for (p = ODM_RF_PATH_A; p <= ODM_RF_PATH_B; ++p) {                                      \r
1041                                         PHY_SetRFReg(pAdapter, p, RF_AC_Jaguar, bRFRegOffsetMask, regRF0x0);\r
1042                                         PHY_SetRFReg(pAdapter, p, LNA_Low_Gain_3, BIT1, 0x0); // RF LO disabled\r
1043                                 }\r
1044                 } else {\r
1045                                 PHY_SetRFReg(pAdapter, p, RF_AC_Jaguar, bRFRegOffsetMask, regRF0x0);\r
1046                                 PHY_SetRFReg(pAdapter, p, LNA_Low_Gain_3, BIT1, 0x0); // RF LO disabled\r
1047                         }\r
1048                         PHY_SetBBReg(pAdapter, rA_RFE_Pinmux_Jaguar, bMaskDWord, reg0xCB0); \r
1049                         PHY_SetBBReg(pAdapter, rB_RFE_Pinmux_Jaguar, bMaskDWord, reg0xEB0); \r
1050                         PHY_SetBBReg(pAdapter, rA_RFE_Pinmux_Jaguar+4, bMaskDWord, reg0xCB4);\r
1051                         PHY_SetBBReg(pAdapter, rB_RFE_Pinmux_Jaguar+4, bMaskDWord, reg0xEB4); \r
1052                         */\r
1053             }   \r
1054                 else\r
1055                 {\r
1056                         // Turn off all test modes.     \r
1057                         /*\r
1058                         PHY_SetBBReg(pAdapter, rSingleTone_ContTx_Jaguar, BIT18|BIT17|BIT16, OFDM_ALL_OFF);\r
1059                         */\r
1060                 }\r
1061 \r
1062                 write_bbreg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000100);\r
1063                 write_bbreg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000100);\r
1064 \r
1065         }\r
1066 \r
1067 }\r
1068 \r
1069 \r
1070 void Hal_SetCarrierSuppressionTx(PADAPTER pAdapter, u8 bStart)\r
1071 {\r
1072         pAdapter->mppriv.MptCtx.bCarrierSuppression = bStart;\r
1073         if (bStart) // Start Carrier Suppression.\r
1074         {\r
1075                 RT_TRACE(_module_mp_,_drv_alert_, ("SetCarrierSuppressionTx: test start\n"));\r
1076                 //if(pMgntInfo->dot11CurrentWirelessMode == WIRELESS_MODE_B)\r
1077                 if (pAdapter->mppriv.rateidx <= MPT_RATE_11M)\r
1078                   {\r
1079                         // 1. if CCK block on?\r
1080                         if(!read_bbreg(pAdapter, rFPGA0_RFMOD, bCCKEn))\r
1081                                 write_bbreg(pAdapter, rFPGA0_RFMOD, bCCKEn, bEnable);//set CCK block on\r
1082 \r
1083                         //Turn Off All Test Mode\r
1084                         write_bbreg(pAdapter, rOFDM1_LSTF, bOFDMContinueTx, bDisable);\r
1085                         write_bbreg(pAdapter, rOFDM1_LSTF, bOFDMSingleCarrier, bDisable);\r
1086                         write_bbreg(pAdapter, rOFDM1_LSTF, bOFDMSingleTone, bDisable);\r
1087 \r
1088                         write_bbreg(pAdapter, rCCK0_System, bCCKBBMode, 0x2);    //transmit mode\r
1089                         write_bbreg(pAdapter, rCCK0_System, bCCKScramble, 0x0);  //turn off scramble setting\r
1090 \r
1091                         //Set CCK Tx Test Rate\r
1092                         //PHY_SetBBReg(pAdapter, rCCK0_System, bCCKTxRate, pMgntInfo->ForcedDataRate);\r
1093                         write_bbreg(pAdapter, rCCK0_System, bCCKTxRate, 0x0);    //Set FTxRate to 1Mbps\r
1094                 }\r
1095 \r
1096                  //Set for dynamic set Power index\r
1097                  write_bbreg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000500);\r
1098                  write_bbreg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000500);\r
1099 \r
1100         }\r
1101         else// Stop Carrier Suppression.\r
1102         {\r
1103                 RT_TRACE(_module_mp_,_drv_alert_, ("SetCarrierSuppressionTx: test stop\n"));\r
1104                 //if(pMgntInfo->dot11CurrentWirelessMode == WIRELESS_MODE_B)\r
1105                 if (pAdapter->mppriv.rateidx <= MPT_RATE_11M ) {\r
1106                         write_bbreg(pAdapter, rCCK0_System, bCCKBBMode, 0x0);    //normal mode\r
1107                         write_bbreg(pAdapter, rCCK0_System, bCCKScramble, 0x1);  //turn on scramble setting\r
1108 \r
1109                         //BB Reset\r
1110                         write_bbreg(pAdapter, rPMAC_Reset, bBBResetB, 0x0);\r
1111                         write_bbreg(pAdapter, rPMAC_Reset, bBBResetB, 0x1);\r
1112                 }\r
1113                 //Stop for dynamic set Power index\r
1114                 write_bbreg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000100);\r
1115                 write_bbreg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000100);\r
1116         }\r
1117         //DbgPrint("\n MPT_ProSetCarrierSupp() is finished. \n");\r
1118 }\r
1119 \r
1120 void Hal_SetCCKContinuousTx(PADAPTER pAdapter, u8 bStart)\r
1121 {\r
1122         u32 cckrate;\r
1123 \r
1124         if (bStart)\r
1125         {\r
1126                 RT_TRACE(_module_mp_, _drv_alert_,\r
1127                          ("SetCCKContinuousTx: test start\n"));\r
1128 \r
1129                 // 1. if CCK block on?\r
1130                 if(!read_bbreg(pAdapter, rFPGA0_RFMOD, bCCKEn))\r
1131                         write_bbreg(pAdapter, rFPGA0_RFMOD, bCCKEn, bEnable);//set CCK block on\r
1132 \r
1133                 //Turn Off All Test Mode\r
1134                 //if (IS_HARDWARE_TYPE_JAGUAR(pAdapter))\r
1135                         //PHY_SetBBReg(pAdapter, rSingleTone_ContTx_Jaguar, BIT18|BIT17|BIT16, OFDM_ALL_OFF);\r
1136                 //else\r
1137                         PHY_SetBBReg(pAdapter, rOFDM1_LSTF, BIT30|BIT29|BIT28, OFDM_ALL_OFF);\r
1138                 //Set CCK Tx Test Rate\r
1139                 #if 0\r
1140                 switch(pAdapter->mppriv.rateidx)\r
1141                 {\r
1142                         case 2:\r
1143                                 cckrate = 0;\r
1144                                 break;\r
1145                         case 4:\r
1146                                 cckrate = 1;\r
1147                                 break;\r
1148                         case 11:\r
1149                                 cckrate = 2;\r
1150                                 break;\r
1151                         case 22:\r
1152                                 cckrate = 3;\r
1153                                 break;\r
1154                         default:\r
1155                                 cckrate = 0;\r
1156                                 break;\r
1157                 }\r
1158                 #else\r
1159                 cckrate  = pAdapter->mppriv.rateidx;\r
1160                 #endif\r
1161                 write_bbreg(pAdapter, rCCK0_System, bCCKTxRate, cckrate);\r
1162                 write_bbreg(pAdapter, rCCK0_System, bCCKBBMode, 0x2);   //transmit mode\r
1163                 write_bbreg(pAdapter, rCCK0_System, bCCKScramble, bEnable);     //turn on scramble setting\r
1164 \r
1165                 write_bbreg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000500);\r
1166                 write_bbreg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000500);\r
1167 \r
1168         }\r
1169         else {\r
1170                 RT_TRACE(_module_mp_, _drv_info_,\r
1171                          ("SetCCKContinuousTx: test stop\n"));\r
1172 \r
1173                 write_bbreg(pAdapter, rCCK0_System, bCCKBBMode, 0x0);   //normal mode\r
1174                 write_bbreg(pAdapter, rCCK0_System, bCCKScramble, bEnable);     //turn on scramble setting\r
1175 \r
1176                 //BB Reset\r
1177                 write_bbreg(pAdapter, rPMAC_Reset, bBBResetB, 0x0);\r
1178                 write_bbreg(pAdapter, rPMAC_Reset, bBBResetB, 0x1);\r
1179 \r
1180                 write_bbreg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000100);\r
1181                 write_bbreg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000100);\r
1182         }\r
1183 \r
1184         pAdapter->mppriv.MptCtx.bCckContTx = bStart;\r
1185         pAdapter->mppriv.MptCtx.bOfdmContTx = _FALSE;\r
1186 }/* mpt_StartCckContTx */\r
1187 \r
1188 void Hal_SetOFDMContinuousTx(PADAPTER pAdapter, u8 bStart)\r
1189 {\r
1190     HAL_DATA_TYPE       *pHalData = GET_HAL_DATA(pAdapter);\r
1191 \r
1192         if (bStart) {\r
1193                 RT_TRACE(_module_mp_, _drv_info_, ("SetOFDMContinuousTx: test start\n"));\r
1194                 // 1. if OFDM block on?\r
1195                 if(!read_bbreg(pAdapter, rFPGA0_RFMOD, bOFDMEn))\r
1196                         write_bbreg(pAdapter, rFPGA0_RFMOD, bOFDMEn, bEnable);//set OFDM block on\r
1197         {\r
1198 \r
1199                 // 2. set CCK test mode off, set to CCK normal mode\r
1200                 write_bbreg(pAdapter, rCCK0_System, bCCKBBMode, bDisable);\r
1201 \r
1202                 // 3. turn on scramble setting\r
1203                 write_bbreg(pAdapter, rCCK0_System, bCCKScramble, bEnable);\r
1204         }\r
1205                 // 4. Turn On Continue Tx and turn off the other test modes.\r
1206                 write_bbreg(pAdapter, rOFDM1_LSTF, bOFDMContinueTx, bEnable);\r
1207                 write_bbreg(pAdapter, rOFDM1_LSTF, bOFDMSingleCarrier, bDisable);\r
1208                 write_bbreg(pAdapter, rOFDM1_LSTF, bOFDMSingleTone, bDisable);\r
1209 \r
1210                 write_bbreg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000500);\r
1211                 write_bbreg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000500);\r
1212 \r
1213         } else {\r
1214                 RT_TRACE(_module_mp_,_drv_info_, ("SetOFDMContinuousTx: test stop\n"));\r
1215                 write_bbreg(pAdapter, rOFDM1_LSTF, bOFDMContinueTx, bDisable);\r
1216                 write_bbreg(pAdapter, rOFDM1_LSTF, bOFDMSingleCarrier, bDisable);\r
1217                 write_bbreg(pAdapter, rOFDM1_LSTF, bOFDMSingleTone, bDisable);\r
1218                 //Delay 10 ms\r
1219                 rtw_msleep_os(10);\r
1220                 //BB Reset\r
1221                 write_bbreg(pAdapter, rPMAC_Reset, bBBResetB, 0x0);\r
1222                 write_bbreg(pAdapter, rPMAC_Reset, bBBResetB, 0x1);\r
1223 \r
1224                 write_bbreg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000100);\r
1225                 write_bbreg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000100);\r
1226         }\r
1227 \r
1228         pAdapter->mppriv.MptCtx.bCckContTx = _FALSE;\r
1229         pAdapter->mppriv.MptCtx.bOfdmContTx = bStart;\r
1230 }/* mpt_StartOfdmContTx */\r
1231 \r
1232 void Hal_SetContinuousTx(PADAPTER pAdapter, u8 bStart)\r
1233 {\r
1234 #if 0\r
1235         // ADC turn off [bit24-21] adc port0 ~ port1\r
1236         if (bStart) {\r
1237                 write_bbreg(pAdapter, rRx_Wait_CCCA, read_bbreg(pAdapter, rRx_Wait_CCCA) & 0xFE1FFFFF);\r
1238                 rtw_usleep_os(100);\r
1239         }\r
1240 #endif\r
1241         RT_TRACE(_module_mp_, _drv_info_,\r
1242                  ("SetContinuousTx: rate:%d\n", pAdapter->mppriv.rateidx));\r
1243 \r
1244         pAdapter->mppriv.MptCtx.bStartContTx = bStart;\r
1245 \r
1246         //write_bbreg(pAdapter, rFixContTxRate, bFixContTxRate, bStart);\r
1247 \r
1248         if (pAdapter->mppriv.rateidx <= MPT_RATE_11M)\r
1249         {\r
1250                 Hal_SetCCKContinuousTx(pAdapter, bStart);\r
1251         }\r
1252         else if ((pAdapter->mppriv.rateidx >= MPT_RATE_6M) &&\r
1253                  (pAdapter->mppriv.rateidx <= MPT_RATE_MCS15))\r
1254         {\r
1255                 Hal_SetOFDMContinuousTx(pAdapter, bStart);\r
1256         }\r
1257 #if 0\r
1258         // ADC turn on [bit24-21] adc port0 ~ port1\r
1259         if (!bStart) {\r
1260                 write_bbreg(pAdapter, rRx_Wait_CCCA, read_bbreg(pAdapter, rRx_Wait_CCCA) | 0x01E00000);\r
1261         }\r
1262 #endif\r
1263 }\r
1264 \r
1265 \r
1266 \r
1267 u8 MRateToHwRate8723B( u8 rate)\r
1268 {\r
1269         u8      ret = DESC8723B_RATE1M;\r
1270                 \r
1271         switch(rate)\r
1272         {\r
1273                 // CCK and OFDM non-HT rates\r
1274         case MPT_RATE_1M:               ret = DESC8723B_RATE1M; break;\r
1275         case MPT_RATE_2M:               ret = DESC8723B_RATE2M; break;\r
1276         case MPT_RATE_55M:              ret = DESC8723B_RATE5_5M;       break;\r
1277         case MPT_RATE_11M:              ret = DESC8723B_RATE11M;        break;\r
1278         case MPT_RATE_6M:               ret = DESC8723B_RATE6M; break;\r
1279         case MPT_RATE_9M:               ret = DESC8723B_RATE9M; break;\r
1280         case MPT_RATE_12M:              ret = DESC8723B_RATE12M;        break;\r
1281         case MPT_RATE_18M:              ret = DESC8723B_RATE18M;        break;\r
1282         case MPT_RATE_24M:              ret = DESC8723B_RATE24M;        break;\r
1283         case MPT_RATE_36M:              ret = DESC8723B_RATE36M;        break;\r
1284         case MPT_RATE_48M:              ret = DESC8723B_RATE48M;        break;\r
1285         case MPT_RATE_54M:              ret = DESC8723B_RATE54M;        break;\r
1286 \r
1287                 // HT rates since here\r
1288         case MPT_RATE_MCS0:             ret = DESC8723B_RATEMCS0;       break;\r
1289         case MPT_RATE_MCS1:             ret = DESC8723B_RATEMCS1;       break;\r
1290         case MPT_RATE_MCS2:             ret = DESC8723B_RATEMCS2;       break;\r
1291         case MPT_RATE_MCS3:             ret = DESC8723B_RATEMCS3;       break;\r
1292         case MPT_RATE_MCS4:             ret = DESC8723B_RATEMCS4;       break;\r
1293         case MPT_RATE_MCS5:             ret = DESC8723B_RATEMCS5;       break;\r
1294         case MPT_RATE_MCS6:             ret = DESC8723B_RATEMCS6;       break;\r
1295         case MPT_RATE_MCS7:             ret = DESC8723B_RATEMCS7;       break;\r
1296         case MPT_RATE_MCS8:             ret = DESC8723B_RATEMCS8;       break;\r
1297         case MPT_RATE_MCS9:             ret = DESC8723B_RATEMCS9;       break;\r
1298         case MPT_RATE_MCS10: ret = DESC8723B_RATEMCS10; break;\r
1299         case MPT_RATE_MCS11: ret = DESC8723B_RATEMCS11; break;\r
1300         case MPT_RATE_MCS12: ret = DESC8723B_RATEMCS12; break;\r
1301         case MPT_RATE_MCS13: ret = DESC8723B_RATEMCS13; break;\r
1302         case MPT_RATE_MCS14: ret = DESC8723B_RATEMCS14; break;\r
1303         case MPT_RATE_MCS15: ret = DESC8723B_RATEMCS15; break;\r
1304         case MPT_RATE_VHT1SS_MCS0:              ret = DESC8723B_RATEVHTSS1MCS0; break;\r
1305         case MPT_RATE_VHT1SS_MCS1:              ret = DESC8723B_RATEVHTSS1MCS1; break;\r
1306         case MPT_RATE_VHT1SS_MCS2:              ret = DESC8723B_RATEVHTSS1MCS2; break;\r
1307         case MPT_RATE_VHT1SS_MCS3:              ret = DESC8723B_RATEVHTSS1MCS3; break;\r
1308         case MPT_RATE_VHT1SS_MCS4:              ret = DESC8723B_RATEVHTSS1MCS4; break;\r
1309         case MPT_RATE_VHT1SS_MCS5:              ret = DESC8723B_RATEVHTSS1MCS5; break;\r
1310         case MPT_RATE_VHT1SS_MCS6:              ret = DESC8723B_RATEVHTSS1MCS6; break;\r
1311         case MPT_RATE_VHT1SS_MCS7:              ret = DESC8723B_RATEVHTSS1MCS7; break;\r
1312         case MPT_RATE_VHT1SS_MCS8:              ret = DESC8723B_RATEVHTSS1MCS8; break;\r
1313         case MPT_RATE_VHT1SS_MCS9:              ret = DESC8723B_RATEVHTSS1MCS9; break;  \r
1314         case MPT_RATE_VHT2SS_MCS0:              ret = DESC8723B_RATEVHTSS2MCS0; break;\r
1315         case MPT_RATE_VHT2SS_MCS1:              ret = DESC8723B_RATEVHTSS2MCS1; break;\r
1316         case MPT_RATE_VHT2SS_MCS2:              ret = DESC8723B_RATEVHTSS2MCS2; break;\r
1317         case MPT_RATE_VHT2SS_MCS3:              ret = DESC8723B_RATEVHTSS2MCS3; break;\r
1318         case MPT_RATE_VHT2SS_MCS4:              ret = DESC8723B_RATEVHTSS2MCS4; break;\r
1319         case MPT_RATE_VHT2SS_MCS5:              ret = DESC8723B_RATEVHTSS2MCS5; break;\r
1320         case MPT_RATE_VHT2SS_MCS6:              ret = DESC8723B_RATEVHTSS2MCS6; break;\r
1321         case MPT_RATE_VHT2SS_MCS7:              ret = DESC8723B_RATEVHTSS2MCS7; break;\r
1322         case MPT_RATE_VHT2SS_MCS8:              ret = DESC8723B_RATEVHTSS2MCS8; break;\r
1323         case MPT_RATE_VHT2SS_MCS9:              ret = DESC8723B_RATEVHTSS2MCS9; break;  \r
1324         default:                break;\r
1325         }\r
1326 \r
1327         return ret;\r
1328 }\r
1329 \r
1330 \r
1331 u8 HwRateToMRate8723B(u8         rate)\r
1332 {\r
1333 \r
1334         u8      ret_rate = MGN_1M;\r
1335 \r
1336 \r
1337         switch(rate)\r
1338         {\r
1339         \r
1340                 case DESC8723B_RATE1M:          ret_rate = MGN_1M;              break;\r
1341                 case DESC8723B_RATE2M:          ret_rate = MGN_2M;              break;\r
1342                 case DESC8723B_RATE5_5M:                ret_rate = MGN_5_5M;            break;\r
1343                 case DESC8723B_RATE11M:         ret_rate = MGN_11M;     break;\r
1344                 case DESC8723B_RATE6M:          ret_rate = MGN_6M;              break;\r
1345                 case DESC8723B_RATE9M:          ret_rate = MGN_9M;              break;\r
1346                 case DESC8723B_RATE12M:         ret_rate = MGN_12M;     break;\r
1347                 case DESC8723B_RATE18M:         ret_rate = MGN_18M;     break;\r
1348                 case DESC8723B_RATE24M:         ret_rate = MGN_24M;     break;\r
1349                 case DESC8723B_RATE36M:         ret_rate = MGN_36M;     break;\r
1350                 case DESC8723B_RATE48M:         ret_rate = MGN_48M;     break;\r
1351                 case DESC8723B_RATE54M:         ret_rate = MGN_54M;     break;                  \r
1352                 case DESC8723B_RATEMCS0:        ret_rate = MGN_MCS0;            break;\r
1353                 case DESC8723B_RATEMCS1:        ret_rate = MGN_MCS1;            break;\r
1354                 case DESC8723B_RATEMCS2:        ret_rate = MGN_MCS2;            break;\r
1355                 case DESC8723B_RATEMCS3:        ret_rate = MGN_MCS3;            break;\r
1356                 case DESC8723B_RATEMCS4:        ret_rate = MGN_MCS4;            break;\r
1357                 case DESC8723B_RATEMCS5:        ret_rate = MGN_MCS5;            break;\r
1358                 case DESC8723B_RATEMCS6:        ret_rate = MGN_MCS6;            break;\r
1359                 case DESC8723B_RATEMCS7:        ret_rate = MGN_MCS7;            break;\r
1360                 case DESC8723B_RATEMCS8:        ret_rate = MGN_MCS8;            break;\r
1361                 case DESC8723B_RATEMCS9:        ret_rate = MGN_MCS9;            break;\r
1362                 case DESC8723B_RATEMCS10:       ret_rate = MGN_MCS10;   break;\r
1363                 case DESC8723B_RATEMCS11:       ret_rate = MGN_MCS11;   break;\r
1364                 case DESC8723B_RATEMCS12:       ret_rate = MGN_MCS12;   break;\r
1365                 case DESC8723B_RATEMCS13:       ret_rate = MGN_MCS13;   break;\r
1366                 case DESC8723B_RATEMCS14:       ret_rate = MGN_MCS14;   break;\r
1367                 case DESC8723B_RATEMCS15:       ret_rate = MGN_MCS15;   break;\r
1368                 case DESC8723B_RATEVHTSS1MCS0:  ret_rate = MGN_VHT1SS_MCS0;     break;\r
1369                 case DESC8723B_RATEVHTSS1MCS1:  ret_rate = MGN_VHT1SS_MCS1;     break;\r
1370                 case DESC8723B_RATEVHTSS1MCS2:  ret_rate = MGN_VHT1SS_MCS2;     break;\r
1371                 case DESC8723B_RATEVHTSS1MCS3:  ret_rate = MGN_VHT1SS_MCS3;     break;\r
1372                 case DESC8723B_RATEVHTSS1MCS4:  ret_rate = MGN_VHT1SS_MCS4;     break;\r
1373                 case DESC8723B_RATEVHTSS1MCS5:  ret_rate = MGN_VHT1SS_MCS5;     break;\r
1374                 case DESC8723B_RATEVHTSS1MCS6:  ret_rate = MGN_VHT1SS_MCS6;     break;\r
1375                 case DESC8723B_RATEVHTSS1MCS7:  ret_rate = MGN_VHT1SS_MCS7;     break;\r
1376                 case DESC8723B_RATEVHTSS1MCS8:  ret_rate = MGN_VHT1SS_MCS8;     break;\r
1377                 case DESC8723B_RATEVHTSS1MCS9:  ret_rate = MGN_VHT1SS_MCS9;     break;\r
1378                 case DESC8723B_RATEVHTSS2MCS0:  ret_rate = MGN_VHT2SS_MCS0;     break;\r
1379                 case DESC8723B_RATEVHTSS2MCS1:  ret_rate = MGN_VHT2SS_MCS1;     break;\r
1380                 case DESC8723B_RATEVHTSS2MCS2:  ret_rate = MGN_VHT2SS_MCS2;     break;\r
1381                 case DESC8723B_RATEVHTSS2MCS3:  ret_rate = MGN_VHT2SS_MCS3;     break;\r
1382                 case DESC8723B_RATEVHTSS2MCS4:  ret_rate = MGN_VHT2SS_MCS4;     break;\r
1383                 case DESC8723B_RATEVHTSS2MCS5:  ret_rate = MGN_VHT2SS_MCS5;     break;\r
1384                 case DESC8723B_RATEVHTSS2MCS6:  ret_rate = MGN_VHT2SS_MCS6;     break;\r
1385                 case DESC8723B_RATEVHTSS2MCS7:  ret_rate = MGN_VHT2SS_MCS7;     break;\r
1386                 case DESC8723B_RATEVHTSS2MCS8:  ret_rate = MGN_VHT2SS_MCS8;     break;\r
1387                 case DESC8723B_RATEVHTSS2MCS9:  ret_rate = MGN_VHT2SS_MCS9;     break;                          \r
1388                 \r
1389                 default:                                                        \r
1390                         DBG_8192C("HwRateToMRate8723B(): Non supported Rate [%x]!!!\n",rate );\r
1391                         break;\r
1392         }       \r
1393         return ret_rate;\r
1394 }\r
1395 \r
1396 #endif // CONFIG_MP_INCLUDE\r
1397 \r