drivers/net/wireless/rockchip_wlan/rtl8723bu/hal/rtl8723b/rtl8723b_mp.c

   1 /******************************************************************************\r
   2  *\r
   3  * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.\r
   4  *\r
   5  * This program is free software; you can redistribute it and/or modify it\r
   6  * under the terms of version 2 of the GNU General Public License as\r
   7  * published by the Free Software Foundation.\r
   8  *\r
   9  * This program is distributed in the hope that it will be useful, but WITHOUT\r
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\r
  11  * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\r
  12  * more details.\r
  13  *\r
  14  * You should have received a copy of the GNU General Public License along with\r
  15  * this program; if not, write to the Free Software Foundation, Inc.,\r
  16  * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA\r
  17  *\r
  18  *\r
  19  ******************************************************************************/\r
  20 #define _RTL8723B_MP_C_\r
  21 #ifdef CONFIG_MP_INCLUDED\r
  22 \r
  23 #include <rtl8723b_hal.h>\r
  24 \r
  25 \r
  26 /*-----------------------------------------------------------------------------\r
  27  * Function:    mpt_SwitchRfSetting\r
  28  *\r
  29  * Overview:    Change RF Setting when we siwthc channel/rate/BW for MP.\r
  30  *\r
  31  * Input:               IN      PADAPTER                                pAdapter\r
  32  *\r
  33  * Output:              NONE\r
  34  *\r
  35  * Return:              NONE\r
  36  *\r
  37  * Revised History:\r
  38  * When                 Who     Remark\r
  39  * 01/08/2009   MHC     Suggestion from SD3 Willis for 92S series.\r
  40  * 01/09/2009   MHC     Add CCK modification for 40MHZ. Suggestion from SD3.\r
  41  *\r
  42  *---------------------------------------------------------------------------*/\r
  43  static void phy_SwitchRfSetting(PADAPTER        pAdapter,u8 channel )\r
  44 {\r
  45 /*\r
  46         HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);\r
  47     u32                                 u4RF_IPA[3], u4RF_TXBIAS, u4RF_SYN_G2;\r
  48 \r
  49         //default value\r
  50         {\r
  51                 u4RF_IPA[0] = 0x4F424;                  //CCK\r
  52                 u4RF_IPA[1] = 0xCF424;                  //OFDM\r
  53                 u4RF_IPA[2] = 0x8F424;                  //MCS\r
  54                 u4RF_TXBIAS = 0xC0356;\r
  55                 u4RF_SYN_G2 = 0x4F200;\r
  56         }\r
  57 \r
  58         switch(channel)\r
  59         {\r
  60                 case 1:\r
  61                         u4RF_IPA[0] = 0x4F40C;\r
  62                         u4RF_IPA[1] = 0xCF466;\r
  63                         u4RF_TXBIAS = 0xC0350;\r
  64                         break;\r
  65 \r
  66                 case 2:\r
  67                         u4RF_IPA[0] =  0x4F407;\r
  68                         u4RF_TXBIAS =  0xC0350;\r
  69                         break;\r
  70 \r
  71                 case 3:\r
  72                         u4RF_IPA[0] =  0x4F407;\r
  73                         u4RF_IPA[2] =  0x8F466;\r
  74                         u4RF_TXBIAS =  0xC0350;\r
  75                         break;\r
  76 \r
  77                 case 5:\r
  78                 case 8:\r
  79                         u4RF_SYN_G2 =  0x0F400;\r
  80                         break;\r
  81 \r
  82                 case 6:\r
  83                 case 13:\r
  84                         u4RF_IPA[0] =  0x4F40C;\r
  85                         break;\r
  86 \r
  87                 case 7:\r
  88                         u4RF_IPA[0] =  0x4F40C;\r
  89                         u4RF_SYN_G2 =  0x0F400;\r
  90                         break;\r
  91 \r
  92                 case 9:\r
  93                         u4RF_IPA[2] =  0x8F454;\r
  94                         u4RF_SYN_G2 =  0x0F400;\r
  95                         break;\r
  96 \r
  97                 case 11:\r
  98                         u4RF_IPA[0] =  0x4F40C;\r
  99                         u4RF_IPA[1] =  0xCF454;\r
 100                         u4RF_SYN_G2 =  0x0F400;\r
 101                         break;\r
 102 \r
 103                 default:\r
 104                         u4RF_IPA[0] =  0x4F424;\r
 105                         u4RF_IPA[1] =  0x8F424;\r
 106                         u4RF_IPA[2] =  0xCF424;\r
 107                         u4RF_TXBIAS =  0xC0356;\r
 108                         u4RF_SYN_G2 =  0x4F200;\r
 109                         break;\r
 110         }\r
 111 \r
 112         PHY_SetRFReg(pAdapter, RF_PATH_A, RF_IPA, bRFRegOffsetMask, u4RF_IPA[0]);\r
 113         PHY_SetRFReg(pAdapter, RF_PATH_A, RF_IPA, bRFRegOffsetMask, u4RF_IPA[1]);\r
 114         PHY_SetRFReg(pAdapter, RF_PATH_A, RF_IPA, bRFRegOffsetMask, u4RF_IPA[2]);\r
 115         PHY_SetRFReg(pAdapter, RF_PATH_A, RF_TXBIAS, bRFRegOffsetMask, u4RF_TXBIAS);\r
 116         PHY_SetRFReg(pAdapter, RF_PATH_A, RF_SYN_G2, bRFRegOffsetMask, u4RF_SYN_G2);\r
 117 */\r
 118 }\r
 119 \r
 120 void Hal_mpt_SwitchRfSetting(PADAPTER pAdapter)\r
 121 {\r
 122         HAL_DATA_TYPE           *pHalData = GET_HAL_DATA(pAdapter);\r
 123         PMPT_CONTEXT            pMptCtx = &(pAdapter->mppriv.MptCtx);\r
 124         u8                              ChannelToSw = pMptCtx->MptChannelToSw;\r
 125 \r
 126         phy_SwitchRfSetting(pAdapter, ChannelToSw);\r
 127 }\r
 128 \r
 129 s32 Hal_SetPowerTracking(PADAPTER padapter, u8 enable)\r
 130 {\r
 131         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(padapter);\r
 132         struct dm_priv  *pdmpriv = &pHalData->dmpriv;\r
 133 \r
 134 \r
 135         if (!netif_running(padapter->pnetdev)) {\r
 136                 RT_TRACE(_module_mp_, _drv_warning_, ("SetPowerTracking! Fail: interface not opened!\n"));\r
 137                 return _FAIL;\r
 138         }\r
 139 \r
 140         if (check_fwstate(&padapter->mlmepriv, WIFI_MP_STATE) == _FALSE) {\r
 141                 RT_TRACE(_module_mp_, _drv_warning_, ("SetPowerTracking! Fail: not in MP mode!\n"));\r
 142                 return _FAIL;\r
 143         }\r
 144 \r
 145         if (enable)\r
 146                 pdmpriv->TxPowerTrackControl = _TRUE;\r
 147         else\r
 148                 pdmpriv->TxPowerTrackControl = _FALSE;\r
 149 \r
 150         return _SUCCESS;\r
 151 }\r
 152 \r
 153 void Hal_GetPowerTracking(PADAPTER padapter, u8 *enable)\r
 154 {\r
 155         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(padapter);\r
 156         struct dm_priv  *pdmpriv = &pHalData->dmpriv;\r
 157 \r
 158 \r
 159         *enable = pdmpriv->TxPowerTrackControl;\r
 160 }\r
 161 \r
 162 static void Hal_disable_dm(PADAPTER padapter)\r
 163 {\r
 164         u8 v8;\r
 165         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(padapter);\r
 166         struct dm_priv  *pdmpriv = &pHalData->dmpriv;\r
 167 \r
 168 \r
 169         //3 1. disable firmware dynamic mechanism\r
 170         // disable Power Training, Rate Adaptive\r
 171         v8 = rtw_read8(padapter, REG_BCN_CTRL);\r
 172         v8 &= ~EN_BCN_FUNCTION;\r
 173         rtw_write8(padapter, REG_BCN_CTRL, v8);\r
 174 \r
 175         //3 2. disable driver dynamic mechanism\r
 176         // disable Dynamic Initial Gain\r
 177         // disable High Power\r
 178         // disable Power Tracking\r
 179         Switch_DM_Func(padapter, DYNAMIC_FUNC_DISABLE, _FALSE);\r
 180 \r
 181         // enable APK, LCK and IQK but disable power tracking\r
 182         pdmpriv->TxPowerTrackControl = _FALSE;\r
 183         Switch_DM_Func(padapter, DYNAMIC_RF_TX_PWR_TRACK , _TRUE);\r
 184 }\r
 185 \r
 186 void Hal_MPT_CCKTxPowerAdjust(PADAPTER Adapter, BOOLEAN bInCH14)\r
 187 {\r
 188         u32             TempVal = 0, TempVal2 = 0, TempVal3 = 0;\r
 189         u32             CurrCCKSwingVal = 0, CCKSwingIndex = 12;\r
 190         u8              i;\r
 191         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(Adapter);\r
 192 \r
 193 \r
 194         // get current cck swing value and check 0xa22 & 0xa23 later to match the table.\r
 195         CurrCCKSwingVal = read_bbreg(Adapter, rCCK0_TxFilter1, bMaskHWord);\r
 196 \r
 197         if (!bInCH14)\r
 198         {\r
 199                 // Readback the current bb cck swing value and compare with the table to\r
 200                 // get the current swing index\r
 201                 for (i = 0; i < CCK_TABLE_SIZE; i++)\r
 202                 {\r
 203                         if (((CurrCCKSwingVal&0xff) == (u32)CCKSwingTable_Ch1_Ch13[i][0]) &&\r
 204                                 (((CurrCCKSwingVal&0xff00)>>8) == (u32)CCKSwingTable_Ch1_Ch13[i][1]))\r
 205                         {\r
 206                                 CCKSwingIndex = i;\r
 207 //                              RT_TRACE(COMP_INIT, DBG_LOUD,("Ch1~13, Current reg0x%x = 0x%lx, CCKSwingIndex=0x%x\n",\r
 208 //                                      (rCCK0_TxFilter1+2), CurrCCKSwingVal, CCKSwingIndex));\r
 209                                 break;\r
 210                         }\r
 211                 }\r
 212 \r
 213                 //Write 0xa22 0xa23\r
 214                 TempVal = CCKSwingTable_Ch1_Ch13[CCKSwingIndex][0] +\r
 215                                 (CCKSwingTable_Ch1_Ch13[CCKSwingIndex][1]<<8) ;\r
 216 \r
 217 \r
 218                 //Write 0xa24 ~ 0xa27\r
 219                 TempVal2 = 0;\r
 220                 TempVal2 = CCKSwingTable_Ch1_Ch13[CCKSwingIndex][2] +\r
 221                                 (CCKSwingTable_Ch1_Ch13[CCKSwingIndex][3]<<8) +\r
 222                                 (CCKSwingTable_Ch1_Ch13[CCKSwingIndex][4]<<16 )+\r
 223                                 (CCKSwingTable_Ch1_Ch13[CCKSwingIndex][5]<<24);\r
 224 \r
 225                 //Write 0xa28  0xa29\r
 226                 TempVal3 = 0;\r
 227                 TempVal3 = CCKSwingTable_Ch1_Ch13[CCKSwingIndex][6] +\r
 228                                 (CCKSwingTable_Ch1_Ch13[CCKSwingIndex][7]<<8) ;\r
 229         }\r
 230         else\r
 231         {\r
 232                 for (i = 0; i < CCK_TABLE_SIZE; i++)\r
 233                 {\r
 234                         if (((CurrCCKSwingVal&0xff) == (u32)CCKSwingTable_Ch14[i][0]) &&\r
 235                                 (((CurrCCKSwingVal&0xff00)>>8) == (u32)CCKSwingTable_Ch14[i][1]))\r
 236                         {\r
 237                                 CCKSwingIndex = i;\r
 238 //                              RT_TRACE(COMP_INIT, DBG_LOUD,("Ch14, Current reg0x%x = 0x%lx, CCKSwingIndex=0x%x\n",\r
 239 //                                      (rCCK0_TxFilter1+2), CurrCCKSwingVal, CCKSwingIndex));\r
 240                                 break;\r
 241                         }\r
 242                 }\r
 243 \r
 244                 //Write 0xa22 0xa23\r
 245                 TempVal = CCKSwingTable_Ch14[CCKSwingIndex][0] +\r
 246                                 (CCKSwingTable_Ch14[CCKSwingIndex][1]<<8) ;\r
 247 \r
 248                 //Write 0xa24 ~ 0xa27\r
 249                 TempVal2 = 0;\r
 250                 TempVal2 = CCKSwingTable_Ch14[CCKSwingIndex][2] +\r
 251                                 (CCKSwingTable_Ch14[CCKSwingIndex][3]<<8) +\r
 252                                 (CCKSwingTable_Ch14[CCKSwingIndex][4]<<16 )+\r
 253                                 (CCKSwingTable_Ch14[CCKSwingIndex][5]<<24);\r
 254 \r
 255                 //Write 0xa28  0xa29\r
 256                 TempVal3 = 0;\r
 257                 TempVal3 = CCKSwingTable_Ch14[CCKSwingIndex][6] +\r
 258                                 (CCKSwingTable_Ch14[CCKSwingIndex][7]<<8) ;\r
 259         }\r
 260 \r
 261         write_bbreg(Adapter, rCCK0_TxFilter1, bMaskHWord, TempVal);\r
 262         write_bbreg(Adapter, rCCK0_TxFilter2, bMaskDWord, TempVal2);\r
 263         write_bbreg(Adapter, rCCK0_DebugPort, bMaskLWord, TempVal3);\r
 264 }\r
 265 \r
 266 void Hal_MPT_CCKTxPowerAdjustbyIndex(PADAPTER pAdapter, BOOLEAN beven)\r
 267 {\r
 268         s32             TempCCk;\r
 269         u8              CCK_index, CCK_index_old=0;\r
 270         u8              Action = 0;     //0: no action, 1: even->odd, 2:odd->even\r
 271         u8              TimeOut = 100;\r
 272         s32             i = 0;\r
 273         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(pAdapter);\r
 274         PMPT_CONTEXT    pMptCtx = &pAdapter->mppriv.MptCtx;\r
 275 \r
 276 \r
 277         if (!IS_92C_SERIAL(pHalData->VersionID))\r
 278                 return;\r
 279 #if 0\r
 280         while(PlatformAtomicExchange(&Adapter->IntrCCKRefCount, TRUE) == TRUE)\r
 281         {\r
 282                 PlatformSleepUs(100);\r
 283                 TimeOut--;\r
 284                 if(TimeOut <= 0)\r
 285                 {\r
 286                         RTPRINT(FINIT, INIT_TxPower,\r
 287                          ("!!!MPT_CCKTxPowerAdjustbyIndex Wait for check CCK gain index too long!!!\n" ));\r
 288                         break;\r
 289                 }\r
 290         }\r
 291 #endif\r
 292         if (beven && !pMptCtx->bMptIndexEven)   //odd->even\r
 293         {\r
 294                 Action = 2;\r
 295                 pMptCtx->bMptIndexEven = _TRUE;\r
 296         }\r
 297         else if (!beven && pMptCtx->bMptIndexEven)      //even->odd\r
 298         {\r
 299                 Action = 1;\r
 300                 pMptCtx->bMptIndexEven = _FALSE;\r
 301         }\r
 302 \r
 303         if (Action != 0)\r
 304         {\r
 305                 //Query CCK default setting From 0xa24\r
 306                 TempCCk = read_bbreg(pAdapter, rCCK0_TxFilter2, bMaskDWord) & bMaskCCK;\r
 307                 for (i = 0; i < CCK_TABLE_SIZE; i++)\r
 308                 {\r
 309                         if (pHalData->dmpriv.bCCKinCH14)\r
 310                         {\r
 311                                 if (_rtw_memcmp((void*)&TempCCk, (void*)&CCKSwingTable_Ch14[i][2], 4) == _TRUE)\r
 312                                 {\r
 313                                         CCK_index_old = (u8) i;\r
 314 //                                      RTPRINT(FINIT, INIT_TxPower,("MPT_CCKTxPowerAdjustbyIndex: Initial reg0x%x = 0x%lx, CCK_index=0x%x, ch 14 %d\n",\r
 315 //                                              rCCK0_TxFilter2, TempCCk, CCK_index_old, pHalData->bCCKinCH14));\r
 316                                         break;\r
 317                                 }\r
 318                         }\r
 319                         else\r
 320                         {\r
 321                                 if (_rtw_memcmp((void*)&TempCCk, (void*)&CCKSwingTable_Ch1_Ch13[i][2], 4) == _TRUE)\r
 322                                 {\r
 323                                         CCK_index_old = (u8) i;\r
 324 //                                      RTPRINT(FINIT, INIT_TxPower,("MPT_CCKTxPowerAdjustbyIndex: Initial reg0x%x = 0x%lx, CCK_index=0x%x, ch14 %d\n",\r
 325 //                                              rCCK0_TxFilter2, TempCCk, CCK_index_old, pHalData->bCCKinCH14));\r
 326                                         break;\r
 327                                 }\r
 328                         }\r
 329                 }\r
 330 \r
 331                 if (Action == 1) {\r
 332                         if (CCK_index_old == 0)\r
 333                                 CCK_index_old = 1;\r
 334                         CCK_index = CCK_index_old - 1;\r
 335                 } else {\r
 336                         CCK_index = CCK_index_old + 1;\r
 337                 }\r
 338 \r
 339                 if (CCK_index == CCK_TABLE_SIZE) {\r
 340                         CCK_index = CCK_TABLE_SIZE -1;\r
 341                         RT_TRACE(_module_mp_, _drv_info_, ("CCK_index == CCK_TABLE_SIZE\n"));\r
 342                 }\r
 343 \r
 344 //              RTPRINT(FINIT, INIT_TxPower,("MPT_CCKTxPowerAdjustbyIndex: new CCK_index=0x%x\n",\r
 345 //                       CCK_index));\r
 346 \r
 347                 //Adjust CCK according to gain index\r
 348                 if (!pHalData->dmpriv.bCCKinCH14) {\r
 349                         rtw_write8(pAdapter, 0xa22, CCKSwingTable_Ch1_Ch13[CCK_index][0]);\r
 350                         rtw_write8(pAdapter, 0xa23, CCKSwingTable_Ch1_Ch13[CCK_index][1]);\r
 351                         rtw_write8(pAdapter, 0xa24, CCKSwingTable_Ch1_Ch13[CCK_index][2]);\r
 352                         rtw_write8(pAdapter, 0xa25, CCKSwingTable_Ch1_Ch13[CCK_index][3]);\r
 353                         rtw_write8(pAdapter, 0xa26, CCKSwingTable_Ch1_Ch13[CCK_index][4]);\r
 354                         rtw_write8(pAdapter, 0xa27, CCKSwingTable_Ch1_Ch13[CCK_index][5]);\r
 355                         rtw_write8(pAdapter, 0xa28, CCKSwingTable_Ch1_Ch13[CCK_index][6]);\r
 356                         rtw_write8(pAdapter, 0xa29, CCKSwingTable_Ch1_Ch13[CCK_index][7]);\r
 357                 } else {\r
 358                         rtw_write8(pAdapter, 0xa22, CCKSwingTable_Ch14[CCK_index][0]);\r
 359                         rtw_write8(pAdapter, 0xa23, CCKSwingTable_Ch14[CCK_index][1]);\r
 360                         rtw_write8(pAdapter, 0xa24, CCKSwingTable_Ch14[CCK_index][2]);\r
 361                         rtw_write8(pAdapter, 0xa25, CCKSwingTable_Ch14[CCK_index][3]);\r
 362                         rtw_write8(pAdapter, 0xa26, CCKSwingTable_Ch14[CCK_index][4]);\r
 363                         rtw_write8(pAdapter, 0xa27, CCKSwingTable_Ch14[CCK_index][5]);\r
 364                         rtw_write8(pAdapter, 0xa28, CCKSwingTable_Ch14[CCK_index][6]);\r
 365                         rtw_write8(pAdapter, 0xa29, CCKSwingTable_Ch14[CCK_index][7]);\r
 366                 }\r
 367         }\r
 368 #if 0\r
 369         RTPRINT(FINIT, INIT_TxPower,\r
 370         ("MPT_CCKTxPowerAdjustbyIndex 0xa20=%x\n", PlatformEFIORead4Byte(Adapter, 0xa20)));\r
 371 \r
 372         PlatformAtomicExchange(&Adapter->IntrCCKRefCount, FALSE);\r
 373 #endif\r
 374 }\r
 375 /*---------------------------hal\rtl8192c\MPT_HelperFunc.c---------------------------*/\r
 376 \r
 377 /*\r
 378  * SetChannel\r
 379  * Description\r
 380  *      Use H2C command to change channel,\r
 381  *      not only modify rf register, but also other setting need to be done.\r
 382  */\r
 383 void Hal_SetChannel(PADAPTER pAdapter)\r
 384 {\r
 385 #if 0\r
 386         struct mp_priv *pmp = &pAdapter->mppriv;\r
 387 \r
 388 //      SelectChannel(pAdapter, pmp->channel);\r
 389         set_channel_bwmode(pAdapter, pmp->channel, pmp->channel_offset, pmp->bandwidth);\r
 390 #else\r
 391         u8              eRFPath;\r
 392 \r
 393         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(pAdapter);\r
 394         struct mp_priv  *pmp = &pAdapter->mppriv;\r
 395         u8              channel = pmp->channel;\r
 396         u8              bandwidth = pmp->bandwidth;\r
 397         u8              rate = pmp->rateidx;\r
 398 \r
 399 \r
 400         // set RF channel register\r
 401         for (eRFPath = 0; eRFPath < pHalData->NumTotalRFPath; eRFPath++)\r
 402         {\r
 403       if(IS_HARDWARE_TYPE_8192D(pAdapter))\r
 404                         _write_rfreg(pAdapter, (RF_PATH)eRFPath, rRfChannel, 0xFF, channel);\r
 405                 else\r
 406                 _write_rfreg(pAdapter, eRFPath, rRfChannel, 0x3FF, channel);\r
 407         }\r
 408         Hal_mpt_SwitchRfSetting(pAdapter);\r
 409 \r
 410         SelectChannel(pAdapter, channel);\r
 411 \r
 412         if (pHalData->CurrentChannel == 14 && !pHalData->dmpriv.bCCKinCH14) {\r
 413                 pHalData->dmpriv.bCCKinCH14 = _TRUE;\r
 414                 Hal_MPT_CCKTxPowerAdjust(pAdapter, pHalData->dmpriv.bCCKinCH14);\r
 415         }\r
 416         else if (pHalData->CurrentChannel != 14 && pHalData->dmpriv.bCCKinCH14) {\r
 417                 pHalData->dmpriv.bCCKinCH14 = _FALSE;\r
 418                 Hal_MPT_CCKTxPowerAdjust(pAdapter, pHalData->dmpriv.bCCKinCH14);\r
 419         }\r
 420 \r
 421 #endif\r
 422 }\r
 423 \r
 424 /*\r
 425  * Notice\r
 426  *      Switch bandwitdth may change center frequency(channel)\r
 427  */\r
 428 void Hal_SetBandwidth(PADAPTER pAdapter)\r
 429 {\r
 430         struct mp_priv *pmp = &pAdapter->mppriv;\r
 431 \r
 432 \r
 433         SetBWMode(pAdapter, pmp->bandwidth, pmp->prime_channel_offset);\r
 434         Hal_mpt_SwitchRfSetting(pAdapter);\r
 435 }\r
 436 \r
 437 void Hal_SetCCKTxPower(PADAPTER pAdapter, u8 *TxPower)\r
 438 {\r
 439         u32 tmpval = 0;\r
 440 \r
 441 \r
 442         // rf-A cck tx power\r
 443         write_bbreg(pAdapter, rTxAGC_A_CCK1_Mcs32, bMaskByte1, TxPower[RF_PATH_A]);\r
 444         tmpval = (TxPower[RF_PATH_A]<<16) | (TxPower[RF_PATH_A]<<8) | TxPower[RF_PATH_A];\r
 445         write_bbreg(pAdapter, rTxAGC_B_CCK11_A_CCK2_11, bMaskH3Bytes, tmpval);\r
 446 \r
 447         // rf-B cck tx power\r
 448         write_bbreg(pAdapter, rTxAGC_B_CCK11_A_CCK2_11, bMaskByte0, TxPower[RF_PATH_B]);\r
 449         tmpval = (TxPower[RF_PATH_B]<<16) | (TxPower[RF_PATH_B]<<8) | TxPower[RF_PATH_B];\r
 450         write_bbreg(pAdapter, rTxAGC_B_CCK1_55_Mcs32, bMaskH3Bytes, tmpval);\r
 451 \r
 452         RT_TRACE(_module_mp_, _drv_notice_,\r
 453                  ("-SetCCKTxPower: A[0x%02x] B[0x%02x]\n",\r
 454                   TxPower[RF_PATH_A], TxPower[RF_PATH_B]));\r
 455 }\r
 456 \r
 457 void Hal_SetOFDMTxPower(PADAPTER pAdapter, u8 *TxPower)\r
 458 {\r
 459         u32 TxAGC = 0;\r
 460         u8 tmpval = 0;\r
 461         PMPT_CONTEXT    pMptCtx = &pAdapter->mppriv.MptCtx;\r
 462         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(pAdapter);\r
 463 \r
 464 \r
 465         // HT Tx-rf(A)\r
 466         tmpval = TxPower[RF_PATH_A];\r
 467         TxAGC = (tmpval<<24) | (tmpval<<16) | (tmpval<<8) | tmpval;\r
 468 \r
 469         write_bbreg(pAdapter, rTxAGC_A_Rate18_06, bMaskDWord, TxAGC);\r
 470         write_bbreg(pAdapter, rTxAGC_A_Rate54_24, bMaskDWord, TxAGC);\r
 471         write_bbreg(pAdapter, rTxAGC_A_Mcs03_Mcs00, bMaskDWord, TxAGC);\r
 472         write_bbreg(pAdapter, rTxAGC_A_Mcs07_Mcs04, bMaskDWord, TxAGC);\r
 473         write_bbreg(pAdapter, rTxAGC_A_Mcs11_Mcs08, bMaskDWord, TxAGC);\r
 474         write_bbreg(pAdapter, rTxAGC_A_Mcs15_Mcs12, bMaskDWord, TxAGC);\r
 475 \r
 476         // HT Tx-rf(B)\r
 477         tmpval = TxPower[RF_PATH_B];\r
 478         TxAGC = (tmpval<<24) | (tmpval<<16) | (tmpval<<8) | tmpval;\r
 479 \r
 480         write_bbreg(pAdapter, rTxAGC_B_Rate18_06, bMaskDWord, TxAGC);\r
 481         write_bbreg(pAdapter, rTxAGC_B_Rate54_24, bMaskDWord, TxAGC);\r
 482         write_bbreg(pAdapter, rTxAGC_B_Mcs03_Mcs00, bMaskDWord, TxAGC);\r
 483         write_bbreg(pAdapter, rTxAGC_B_Mcs07_Mcs04, bMaskDWord, TxAGC);\r
 484         write_bbreg(pAdapter, rTxAGC_B_Mcs11_Mcs08, bMaskDWord, TxAGC);\r
 485         write_bbreg(pAdapter, rTxAGC_B_Mcs15_Mcs12, bMaskDWord, TxAGC);\r
 486 \r
 487         RT_TRACE(_module_mp_, _drv_notice_,\r
 488                  ("-SetOFDMTxPower: A[0x%02x] B[0x%02x]\n",\r
 489                   TxPower[RF_PATH_A], TxPower[RF_PATH_B]));\r
 490 }\r
 491 \r
 492 void Hal_SetAntennaPathPower(PADAPTER pAdapter)\r
 493 {\r
 494         HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);\r
 495         u8 TxPowerLevel[MAX_RF_PATH_NUMS];\r
 496         u8 rfPath;\r
 497 \r
 498         TxPowerLevel[RF_PATH_A] = pAdapter->mppriv.txpoweridx;\r
 499         TxPowerLevel[RF_PATH_B] = pAdapter->mppriv.txpoweridx_b;\r
 500 \r
 501         switch (pAdapter->mppriv.antenna_tx)\r
 502         {\r
 503                 case ANTENNA_A:\r
 504                 default:\r
 505                         rfPath = RF_PATH_A;\r
 506                         break;\r
 507                 case ANTENNA_B:\r
 508                         rfPath = RF_PATH_B;\r
 509                         break;\r
 510                 case ANTENNA_C:\r
 511                         rfPath = RF_PATH_C;\r
 512                         break;\r
 513         }\r
 514 \r
 515         switch (pHalData->rf_chip)\r
 516         {\r
 517                 case RF_8225:\r
 518                 case RF_8256:\r
 519                 case RF_6052:\r
 520                         Hal_SetCCKTxPower(pAdapter, TxPowerLevel);\r
 521                         if (pAdapter->mppriv.rateidx < MPT_RATE_6M)     // CCK rate\r
 522                                 Hal_MPT_CCKTxPowerAdjustbyIndex(pAdapter, TxPowerLevel[rfPath]%2 == 0);\r
 523                         Hal_SetOFDMTxPower(pAdapter, TxPowerLevel);\r
 524                         break;\r
 525 \r
 526                 default:\r
 527                         break;\r
 528         }\r
 529 }\r
 530 \r
 531 \r
 532 \r
 533 void \r
 534 mpt_SetTxPower(\r
 535         IN      PADAPTER                pAdapter,\r
 536         IN      MPT_TXPWR_DEF   Rate,\r
 537         IN      pu1Byte                 pTxPower\r
 538         )\r
 539 {\r
 540         if (IS_HARDWARE_TYPE_JAGUAR(pAdapter))\r
 541         {\r
 542                 //mpt_SetTxPower_8812(pAdapter, Rate, pTxPower);\r
 543                 return;\r
 544         }\r
 545         \r
 546         \r
 547         switch (Rate)\r
 548         {\r
 549                 case MPT_CCK:\r
 550                 {\r
 551                         u4Byte  TxAGC = 0, pwr=0;\r
 552                         u1Byte  rf;\r
 553 \r
 554                         pwr = pTxPower[ODM_RF_PATH_A];\r
 555                         TxAGC = (pwr<<16)|(pwr<<8)|(pwr);\r
 556                         PHY_SetBBReg(pAdapter, rTxAGC_A_CCK1_Mcs32, bMaskByte1, pTxPower[ODM_RF_PATH_A]);\r
 557                         PHY_SetBBReg(pAdapter, rTxAGC_B_CCK11_A_CCK2_11, bMaskH3Bytes, TxAGC);\r
 558 \r
 559                         pwr = pTxPower[ODM_RF_PATH_B];\r
 560                         TxAGC = (pwr<<16)|(pwr<<8)|(pwr);\r
 561                         PHY_SetBBReg(pAdapter, rTxAGC_B_CCK11_A_CCK2_11, bMaskByte0, pTxPower[ODM_RF_PATH_B]);\r
 562                         PHY_SetBBReg(pAdapter, rTxAGC_B_CCK1_55_Mcs32, bMaskH3Bytes, TxAGC);\r
 563                         \r
 564                 } break;\r
 565                 \r
 566                 case MPT_OFDM:\r
 567 {\r
 568                         u4Byte  TxAGC=0;\r
 569                         u1Byte  pwr=0, rf;\r
 570                         PMPT_CONTEXT    pMptCtx = &(pAdapter->mppriv.MptCtx);           \r
 571         HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);\r
 572 \r
 573                         pwr = pTxPower[0];\r
 574                         TxAGC |= ((pwr<<24)|(pwr<<16)|(pwr<<8)|pwr);\r
 575                         DBG_8192C("HT Tx-rf(A) Power = 0x%x\n", TxAGC);\r
 576                         \r
 577                         PHY_SetBBReg(pAdapter, rTxAGC_A_Rate18_06, bMaskDWord, TxAGC);\r
 578                         PHY_SetBBReg(pAdapter, rTxAGC_A_Rate54_24, bMaskDWord, TxAGC);\r
 579                         PHY_SetBBReg(pAdapter, rTxAGC_A_Mcs03_Mcs00, bMaskDWord, TxAGC);\r
 580                         PHY_SetBBReg(pAdapter, rTxAGC_A_Mcs07_Mcs04, bMaskDWord, TxAGC);\r
 581                         PHY_SetBBReg(pAdapter, rTxAGC_A_Mcs11_Mcs08, bMaskDWord, TxAGC);\r
 582                         PHY_SetBBReg(pAdapter, rTxAGC_A_Mcs15_Mcs12, bMaskDWord, TxAGC);\r
 583                         \r
 584                         TxAGC=0;\r
 585                         pwr = pTxPower[1];\r
 586                         TxAGC |= ((pwr<<24)|(pwr<<16)|(pwr<<8)|pwr);\r
 587                         DBG_8192C("HT Tx-rf(B) Power = 0x%x\n", TxAGC);\r
 588                         \r
 589                         PHY_SetBBReg(pAdapter, rTxAGC_B_Rate18_06, bMaskDWord, TxAGC);\r
 590                         PHY_SetBBReg(pAdapter, rTxAGC_B_Rate54_24, bMaskDWord, TxAGC);\r
 591                         PHY_SetBBReg(pAdapter, rTxAGC_B_Mcs03_Mcs00, bMaskDWord, TxAGC);\r
 592                         PHY_SetBBReg(pAdapter, rTxAGC_B_Mcs07_Mcs04, bMaskDWord, TxAGC);\r
 593                         PHY_SetBBReg(pAdapter, rTxAGC_B_Mcs11_Mcs08, bMaskDWord, TxAGC);\r
 594                         PHY_SetBBReg(pAdapter, rTxAGC_B_Mcs15_Mcs12, bMaskDWord, TxAGC);\r
 595                         \r
 596                 } break;\r
 597 \r
 598                 default:\r
 599                         break;\r
 600                         \r
 601         }\r
 602         \r
 603         }\r
 604 \r
 605 void Hal_SetTxPower(PADAPTER pAdapter)\r
 606 {\r
 607         HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);\r
 608         PMPT_CONTEXT            pMptCtx = &(pAdapter->mppriv.MptCtx);\r
 609         PDM_ODM_T               pDM_Odm = &pHalData->odmpriv;\r
 610         u8 TxPowerLevel[MAX_RF_PATH];\r
 611         u1Byte                          path;\r
 612         \r
 613         //#if DEV_BUS_TYPE == RT_USB_INTERFACE || DEV_BUS_TYPE == RT_SDIO_INTERFACE\r
 614                 //RT_ASSERT((KeGetCurrentIrql() == PASSIVE_LEVEL), ("MPT_ProSetTxPower(): not in PASSIVE_LEVEL!\n"));\r
 615         //#endif\r
 616         \r
 617         path = (pHalData->AntennaTxPath == ANTENNA_A) ? (ODM_RF_PATH_A) : (ODM_RF_PATH_B);\r
 618                 \r
 619                 if (pHalData->rf_chip < RF_TYPE_MAX)\r
 620                 {\r
 621                         if (IS_HARDWARE_TYPE_JAGUAR(pAdapter))\r
 622         {\r
 623 \r
 624                                 DBG_8192C("===> MPT_ProSetTxPower: Jaguar\n");\r
 625                                 /*\r
 626                                         mpt_SetTxPower_8812(pAdapter, MPT_CCK, pMptCtx->TxPwrLevel);\r
 627                                         mpt_SetTxPower_8812(pAdapter, MPT_OFDM, pMptCtx->TxPwrLevel);\r
 628                                         mpt_SetTxPower_8812(pAdapter, MPT_VHT_OFDM, pMptCtx->TxPwrLevel);\r
 629                                         */\r
 630                         }\r
 631                         else \r
 632                         {\r
 633                                 DBG_8192C("===> MPT_ProSetTxPower: Others\n");\r
 634                                 mpt_SetTxPower(pAdapter, MPT_CCK, pMptCtx->TxPwrLevel);\r
 635                                 Hal_MPT_CCKTxPowerAdjustbyIndex(pAdapter, pMptCtx->TxPwrLevel[path]%2 == 0);            \r
 636                                 mpt_SetTxPower(pAdapter, MPT_OFDM, pMptCtx->TxPwrLevel);\r
 637                         }\r
 638                 }\r
 639                 else\r
 640                 {\r
 641                    DBG_8192C("RFChipID < RF_TYPE_MAX, the RF chip is not supported - %d\n", pHalData->rf_chip);\r
 642         }\r
 643 \r
 644                 ODM_ClearTxPowerTrackingState(pDM_Odm);\r
 645 \r
 646 }\r
 647 \r
 648 void Hal_SetTxAGCOffset(PADAPTER pAdapter, u32 ulTxAGCOffset)\r
 649 {\r
 650 #if 0\r
 651         u32 TxAGCOffset_B, TxAGCOffset_C, TxAGCOffset_D,tmpAGC;\r
 652 \r
 653 \r
 654         TxAGCOffset_B = (ulTxAGCOffset&0x000000ff);\r
 655         TxAGCOffset_C = ((ulTxAGCOffset&0x0000ff00)>>8);\r
 656         TxAGCOffset_D = ((ulTxAGCOffset&0x00ff0000)>>16);\r
 657 \r
 658         tmpAGC = (TxAGCOffset_D<<8 | TxAGCOffset_C<<4 | TxAGCOffset_B);\r
 659         write_bbreg(pAdapter, rFPGA0_TxGainStage,\r
 660                         (bXBTxAGC|bXCTxAGC|bXDTxAGC), tmpAGC);\r
 661 #endif\r
 662 }\r
 663 \r
 664 void Hal_SetDataRate(PADAPTER pAdapter)\r
 665 {\r
 666         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(pAdapter);\r
 667         PMPT_CONTEXT            pMptCtx = &(pAdapter->mppriv.MptCtx);\r
 668         u32 DataRate;\r
 669         \r
 670         DataRate=MptToMgntRate(pAdapter->mppriv.rateidx);\r
 671         \r
 672                 if(!IS_HARDWARE_TYPE_8723A(pAdapter))\r
 673                 Hal_mpt_SwitchRfSetting(pAdapter);\r
 674                 if (IS_CCK_RATE(DataRate))\r
 675                 {\r
 676                         if (pMptCtx->MptRfPath == ODM_RF_PATH_A) // S1\r
 677                                 PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, 0x51, 0xF, 0x6);  \r
 678                         else // S0\r
 679                                 PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, 0x71, 0xF, 0x6);\r
 680                 }\r
 681                 else\r
 682                 {\r
 683                         if (pMptCtx->MptRfPath == ODM_RF_PATH_A) // S1\r
 684                                 PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, 0x51, 0xF, 0xE);  \r
 685                         else // S0\r
 686                                 PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, 0x71, 0xF, 0xE);          \r
 687                 }\r
 688 \r
 689         // <20130913, Kordan> 8723BS TFBGA uses the default setting.\r
 690         if ((IS_HARDWARE_TYPE_8723BS(pAdapter) && \r
 691                   ((pHalData->PackageType == PACKAGE_TFBGA79) || (pHalData->PackageType == PACKAGE_TFBGA90))))\r
 692         {\r
 693                 if (pMptCtx->MptRfPath == ODM_RF_PATH_A) // S1\r
 694                         PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, 0x51, 0xF, 0xE);  \r
 695                 else // S0\r
 696                         PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, 0x71, 0xF, 0xE);                  \r
 697         }\r
 698 }\r
 699 \r
 700 #define RF_PATH_AB      22\r
 701 \r
 702 void Hal_SetAntenna(PADAPTER pAdapter)\r
 703 {\r
 704         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(pAdapter);\r
 705         u4Byte                                  ulAntennaTx, ulAntennaRx;\r
 706         PMPT_CONTEXT            pMptCtx = &(pAdapter->mppriv.MptCtx);\r
 707         PDM_ODM_T               pDM_Odm = &pHalData->odmpriv;\r
 708         PODM_RF_CAL_T                   pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo);\r
 709 \r
 710         ulAntennaTx = pHalData->AntennaTxPath;\r
 711         ulAntennaRx = pHalData->AntennaRxPath;\r
 712 \r
 713         if (pHalData->rf_chip>= RF_TYPE_MAX)\r
 714         {\r
 715                 DBG_8192C("This RF chip ID is not supported\n");\r
 716                 return ;\r
 717         }\r
 718 \r
 719         switch (pAdapter->mppriv.antenna_tx)\r
 720         {\r
 721                 u1Byte p = 0, i = 0;\r
 722 \r
 723             case ANTENNA_A: // Actually path S1  (Wi-Fi)\r
 724                         {\r
 725                                 pMptCtx->MptRfPath = ODM_RF_PATH_A;                     \r
 726                                 PHY_SetBBReg(pAdapter, rS0S1_PathSwitch, BIT9|BIT8|BIT7, 0x0);\r
 727                                 PHY_SetBBReg(pAdapter, 0xB2C, BIT31, 0x0); // AGC Table Sel\r
 728 \r
 729                                 //<20130522, Kordan> 0x51 and 0x71 should be set immediately after path switched, or they might be overwritten.\r
 730                                 if ((pHalData->PackageType == PACKAGE_TFBGA79) || (pHalData->PackageType == PACKAGE_TFBGA90))\r
 731                                         PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, 0x51, bRFRegOffsetMask, 0x6B10E);\r
 732                                 else\r
 733                                         PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, 0x51, bRFRegOffsetMask, 0x6B04E);\r
 734 \r
 735 \r
 736                                 for (i = 0; i < 3; ++i)\r
 737                                 {\r
 738                                         u4Byte offset = pRFCalibrateInfo->TxIQC_8723B[ODM_RF_PATH_A][i][0];\r
 739                                          u4Byte data = pRFCalibrateInfo->TxIQC_8723B[ODM_RF_PATH_A][i][1];\r
 740                                         if (offset != 0) {\r
 741                                                 PHY_SetBBReg(pAdapter, offset, bMaskDWord, data);\r
 742                                                 DBG_8192C("Switch to S1 TxIQC(offset, data) = (0x%X, 0x%X)\n", offset, data);\r
 743                                         }\r
 744 \r
 745                                 }\r
 746                                  for (i = 0; i < 2; ++i)\r
 747                                 {\r
 748                                         u4Byte offset = pRFCalibrateInfo->RxIQC_8723B[ODM_RF_PATH_A][i][0];\r
 749                                         u4Byte data = pRFCalibrateInfo->RxIQC_8723B[ODM_RF_PATH_A][i][1];\r
 750                                         if (offset != 0) {\r
 751                                                 PHY_SetBBReg(pAdapter, offset, bMaskDWord, data);                                       \r
 752                                                 DBG_8192C("Switch to S1 RxIQC (offset, data) = (0x%X, 0x%X)\n", offset, data);\r
 753                                         }\r
 754                                 }\r
 755                         }\r
 756                 break;\r
 757                 case ANTENNA_B: // Actually path S0 (BT)\r
 758                         {\r
 759                                 pMptCtx->MptRfPath = ODM_RF_PATH_B;\r
 760                                 PHY_SetBBReg(pAdapter, rS0S1_PathSwitch, BIT9|BIT8|BIT7, 0x5);\r
 761                                 PHY_SetBBReg(pAdapter, 0xB2C, BIT31, 0x1); // AGC Table Sel\r
 762                                 \r
 763                                 //<20130522, Kordan> 0x51 and 0x71 should be set immediately after path switched, or they might be overwritten.\r
 764                                 if ((pHalData->PackageType == PACKAGE_TFBGA79) || (pHalData->PackageType == PACKAGE_TFBGA90))\r
 765                                                 PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, 0x51, bRFRegOffsetMask, 0x6B10E);\r
 766                                 else\r
 767                                                 PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, 0x51, bRFRegOffsetMask, 0x6B04E);\r
 768 \r
 769 \r
 770                                 for (i = 0; i < 3; ++i)\r
 771                                 {\r
 772                                          // <20130603, Kordan> Because BB suppors only 1T1R, we restore IQC  to S1 instead of S0.\r
 773                                          u4Byte offset = pRFCalibrateInfo->TxIQC_8723B[ODM_RF_PATH_A][i][0];\r
 774                                          u4Byte data = pRFCalibrateInfo->TxIQC_8723B[ODM_RF_PATH_B][i][1];\r
 775                                         if (pRFCalibrateInfo->TxIQC_8723B[ODM_RF_PATH_B][i][0] != 0) {\r
 776                                          PHY_SetBBReg(pAdapter, offset, bMaskDWord, data);\r
 777                                          DBG_8192C("Switch to S0 TxIQC (offset, data) = (0x%X, 0x%X)\n", offset, data);\r
 778                                         }\r
 779                                 }\r
 780                                 for (i = 0; i < 2; ++i)\r
 781                                 {\r
 782                                          // <20130603, Kordan> Because BB suppors only 1T1R, we restore IQC to S1 instead of S0.\r
 783                                          u4Byte offset = pRFCalibrateInfo->RxIQC_8723B[ODM_RF_PATH_A][i][0];\r
 784                                          u4Byte data = pRFCalibrateInfo->RxIQC_8723B[ODM_RF_PATH_B][i][1];\r
 785                                         if (pRFCalibrateInfo->RxIQC_8723B[ODM_RF_PATH_B][i][0] != 0) {\r
 786                                                 PHY_SetBBReg(pAdapter, offset, bMaskDWord, data);\r
 787                                                 DBG_8192C("Switch to S0 RxIQC (offset, data) = (0x%X, 0x%X)\n", offset, data);\r
 788                                         }\r
 789                                 }\r
 790 \r
 791                         }\r
 792                         break;\r
 793                 default:\r
 794                         pMptCtx->MptRfPath = RF_PATH_AB; \r
 795            RT_TRACE(_module_mp_, _drv_notice_, ("Unknown Tx antenna.\n"));\r
 796                         break;\r
 797         }\r
 798 \r
 799         RT_TRACE(_module_mp_, _drv_notice_, ("-SwitchAntenna: finished\n"));\r
 800 }\r
 801 \r
 802 s32 Hal_SetThermalMeter(PADAPTER pAdapter, u8 target_ther)\r
 803 {\r
 804         HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);\r
 805 \r
 806 \r
 807         if (!netif_running(pAdapter->pnetdev)) {\r
 808                 RT_TRACE(_module_mp_, _drv_warning_, ("SetThermalMeter! Fail: interface not opened!\n"));\r
 809                 return _FAIL;\r
 810         }\r
 811 \r
 812         if (check_fwstate(&pAdapter->mlmepriv, WIFI_MP_STATE) == _FALSE) {\r
 813                 RT_TRACE(_module_mp_, _drv_warning_, ("SetThermalMeter: Fail! not in MP mode!\n"));\r
 814                 return _FAIL;\r
 815         }\r
 816 \r
 817         target_ther &= 0xff;\r
 818         if (target_ther < 0x07)\r
 819                 target_ther = 0x07;\r
 820         else if (target_ther > 0x1d)\r
 821                 target_ther = 0x1d;\r
 822 \r
 823         pHalData->EEPROMThermalMeter = target_ther;\r
 824 \r
 825         return _SUCCESS;\r
 826 }\r
 827 \r
 828 void Hal_TriggerRFThermalMeter(PADAPTER pAdapter)\r
 829 {\r
 830         PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, RF_T_METER_8723B, BIT17 | BIT16, 0x03);\r
 831 //      RT_TRACE(_module_mp_,_drv_alert_, ("TriggerRFThermalMeter() finished.\n" ));\r
 832 }\r
 833 \r
 834 u8 Hal_ReadRFThermalMeter(PADAPTER pAdapter)\r
 835 {\r
 836         u32 ThermalValue = 0;\r
 837 \r
 838         ThermalValue = (u1Byte)PHY_QueryRFReg(pAdapter, ODM_RF_PATH_A, RF_T_METER_8723B, 0xfc00);       // 0x42: RF Reg[15:10]                                  \r
 839 \r
 840         return (u8)ThermalValue;\r
 841 }\r
 842 \r
 843 void Hal_GetThermalMeter(PADAPTER pAdapter, u8 *value)\r
 844 {\r
 845 #if 0\r
 846         fw_cmd(pAdapter, IOCMD_GET_THERMAL_METER);\r
 847         rtw_msleep_os(1000);\r
 848         fw_cmd_data(pAdapter, value, 1);\r
 849         *value &= 0xFF;\r
 850 #else\r
 851 \r
 852         Hal_TriggerRFThermalMeter(pAdapter);\r
 853         rtw_msleep_os(1000);\r
 854         *value = Hal_ReadRFThermalMeter(pAdapter);\r
 855 #endif\r
 856 }\r
 857 \r
 858 void Hal_SetSingleCarrierTx(PADAPTER pAdapter, u8 bStart)\r
 859 {\r
 860     HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);\r
 861         pAdapter->mppriv.MptCtx.bSingleCarrier = bStart;\r
 862         if (bStart)// Start Single Carrier.\r
 863         {\r
 864                 RT_TRACE(_module_mp_,_drv_alert_, ("SetSingleCarrierTx: test start\n"));\r
 865                 // Start Single Carrier.\r
 866                 // 1. if OFDM block on?\r
 867                 if(!PHY_QueryBBReg(pAdapter, rFPGA0_RFMOD, bOFDMEn))\r
 868                         PHY_SetBBReg(pAdapter, rFPGA0_RFMOD, bOFDMEn, 1);//set OFDM block on\r
 869 \r
 870                 // 2. set CCK test mode off, set to CCK normal mode\r
 871                 PHY_SetBBReg(pAdapter, rCCK0_System, bCCKBBMode, 0);\r
 872 \r
 873                 // 3. turn on scramble setting\r
 874                 PHY_SetBBReg(pAdapter, rCCK0_System, bCCKScramble, 1);\r
 875 \r
 876                 // 4. Turn On Continue Tx and turn off the other test modes.\r
 877                 //if (IS_HARDWARE_TYPE_JAGUAR(pAdapter))\r
 878                         //PHY_SetBBReg(pAdapter, rSingleTone_ContTx_Jaguar, BIT18|BIT17|BIT16, OFDM_SingleCarrier);\r
 879                 //else\r
 880                 PHY_SetBBReg(pAdapter, rOFDM1_LSTF, BIT30|BIT29|BIT28, OFDM_SingleCarrier);\r
 881         }\r
 882         else// Stop Single Carrier.\r
 883         {\r
 884                 // Stop Single Carrier.\r
 885                 // Turn off all test modes.\r
 886                 //if (IS_HARDWARE_TYPE_JAGUAR(pAdapter))\r
 887                 //      PHY_SetBBReg(pAdapter, rSingleTone_ContTx_Jaguar, BIT18|BIT17|BIT16, OFDM_ALL_OFF);\r
 888                 //else\r
 889                 PHY_SetBBReg(pAdapter, rOFDM1_LSTF, BIT30|BIT29|BIT28, OFDM_ALL_OFF);\r
 890             //Delay 10 ms\r
 891                 rtw_msleep_os(10);\r
 892                 //BB Reset\r
 893             PHY_SetBBReg(pAdapter, rPMAC_Reset, bBBResetB, 0x0);\r
 894             PHY_SetBBReg(pAdapter, rPMAC_Reset, bBBResetB, 0x1);\r
 895         }\r
 896 }\r
 897 \r
 898 \r
 899 void Hal_SetSingleToneTx(PADAPTER pAdapter, u8 bStart)\r
 900 {\r
 901         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(pAdapter);\r
 902         PMPT_CONTEXT            pMptCtx = &(pAdapter->mppriv.MptCtx);\r
 903         BOOLEAN         is92C = IS_92C_SERIAL(pHalData->VersionID);\r
 904         static u4Byte       reg58 = 0x0;\r
 905         static u4Byte       regRF0x0 = 0x0;\r
 906     static u4Byte       reg0xCB0 = 0x0;\r
 907     static u4Byte       reg0xEB0 = 0x0;\r
 908     static u4Byte       reg0xCB4 = 0x0;\r
 909     static u4Byte       reg0xEB4 = 0x0;\r
 910         u8 rfPath;\r
 911 \r
 912         switch (pAdapter->mppriv.antenna_tx)\r
 913         {\r
 914                 case ANTENNA_A:\r
 915                 default:\r
 916                         pMptCtx->MptRfPath = rfPath = RF_PATH_A;\r
 917                         break;\r
 918                 case ANTENNA_B:\r
 919                         pMptCtx->MptRfPath = rfPath = RF_PATH_B;\r
 920                         break;\r
 921                 case ANTENNA_C:\r
 922                         pMptCtx->MptRfPath = rfPath = RF_PATH_C;\r
 923                         break;\r
 924         }\r
 925 \r
 926         pAdapter->mppriv.MptCtx.bSingleTone = bStart;\r
 927         if (bStart)// Start Single Tone.\r
 928         {\r
 929 \r
 930                 // <20120326, Kordan> To amplify the power of tone for Xtal calibration. (asked by Edlu)\r
 931                 if (IS_HARDWARE_TYPE_8188E(pAdapter))\r
 932                  {\r
 933                         reg58 = PHY_QueryRFReg(pAdapter, rfPath, LNA_Low_Gain_3, bRFRegOffsetMask);\r
 934                         if (rfPath == ODM_RF_PATH_A) \r
 935                                 pMptCtx->backup0x58_RF_A = reg58; \r
 936                         else\r
 937                                 pMptCtx->backup0x58_RF_B = reg58;\r
 938                         \r
 939                         PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, LNA_Low_Gain_3, BIT1, 0x1); // RF LO enabled              \r
 940                         PHY_SetBBReg(pAdapter, rFPGA0_RFMOD, bCCKEn, 0x0);\r
 941                         PHY_SetBBReg(pAdapter, rFPGA0_RFMOD, bOFDMEn, 0x0);\r
 942                 \r
 943                 \r
 944                 }\r
 945                 else if (IS_HARDWARE_TYPE_8192E(pAdapter))\r
 946                 { // USB need to do RF LO disable first, PCIE isn't required to follow this order.\r
 947                         PHY_SetRFReg(pAdapter, pMptCtx->MptRfPath, LNA_Low_Gain_3, BIT1, 0x1); // RF LO disabled\r
 948                         PHY_SetRFReg(pAdapter, pMptCtx->MptRfPath, RF_AC, 0xF0000, 0x2); // Tx mode\r
 949                 }                       \r
 950                 else if (IS_HARDWARE_TYPE_8723B(pAdapter))\r
 951                 {\r
 952                         if (pMptCtx->MptRfPath == ODM_RF_PATH_A) {\r
 953                                 PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, RF_AC, 0xF0000, 0x2); // Tx mode\r
 954                                 PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, 0x56, 0xF, 0x1); // RF LO enabled\r
 955                         } else { \r
 956                                 // S0/S1 both use PATH A to configure\r
 957                                 PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, RF_AC, 0xF0000, 0x2); // Tx mode\r
 958                                 PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, 0x76, 0xF, 0x1); // RF LO enabled\r
 959                         }\r
 960                 }\r
 961                 else if (IS_HARDWARE_TYPE_JAGUAR(pAdapter)) \r
 962                 {\r
 963                         /*\r
 964                         u1Byte p = ODM_RF_PATH_A;\r
 965                 \r
 966                         regRF0x0 = PHY_QueryRFReg(pAdapter, ODM_RF_PATH_A, RF_AC_Jaguar, bRFRegOffsetMask);\r
 967                         reg0xCB0 = PHY_QueryBBReg(pAdapter, rA_RFE_Pinmux_Jaguar, bMaskDWord);\r
 968                         reg0xEB0 = PHY_QueryBBReg(pAdapter, rB_RFE_Pinmux_Jaguar, bMaskDWord);\r
 969                         reg0xCB4 = PHY_QueryBBReg(pAdapter, rA_RFE_Pinmux_Jaguar+4, bMaskDWord);\r
 970                         reg0xEB4 = PHY_QueryBBReg(pAdapter, rB_RFE_Pinmux_Jaguar+4, bMaskDWord);\r
 971                         \r
 972                         PHY_SetBBReg(pAdapter, rOFDMCCKEN_Jaguar, BIT29|BIT28, 0x0); // Disable CCK and OFDM\r
 973                 \r
 974                         if (pMptCtx->MptRfPath == RF_PATH_AB) {\r
 975                                 for (p = ODM_RF_PATH_A; p <= ODM_RF_PATH_B; ++p) {                                      \r
 976                                         PHY_SetRFReg(pAdapter, p, RF_AC_Jaguar, 0xF0000, 0x2); // Tx mode: RF0x00[19:16]=4'b0010 \r
 977                                         PHY_SetRFReg(pAdapter, p, RF_AC_Jaguar, 0x1F, 0x0); // Lowest RF gain index: RF_0x0[4:0] = 0\r
 978                                         PHY_SetRFReg(pAdapter, p, LNA_Low_Gain_3, BIT1, 0x1); // RF LO enabled\r
 979                                 }\r
 980                         } else {\r
 981                                 PHY_SetRFReg(pAdapter, pMptCtx->MptRfPath, RF_AC_Jaguar, 0xF0000, 0x2); // Tx mode: RF0x00[19:16]=4'b0010 \r
 982                                 PHY_SetRFReg(pAdapter, pMptCtx->MptRfPath, RF_AC_Jaguar, 0x1F, 0x0); // Lowest RF gain index: RF_0x0[4:0] = 0\r
 983                                 PHY_SetRFReg(pAdapter, pMptCtx->MptRfPath, LNA_Low_Gain_3, BIT1, 0x1); // RF LO enabled\r
 984                         }\r
 985                         \r
 986                 \r
 987                         PHY_SetBBReg(pAdapter, rA_RFE_Pinmux_Jaguar, 0xFF00F0, 0x77007);  // 0xCB0[[23:16, 7:4] = 0x77007\r
 988                         PHY_SetBBReg(pAdapter, rB_RFE_Pinmux_Jaguar, 0xFF00F0, 0x77007);  // 0xCB0[[23:16, 7:4] = 0x77007\r
 989                 \r
 990                         if (pHalData->ExternalPA_5G) {\r
 991                 \r
 992                                 PHY_SetBBReg(pAdapter, rA_RFE_Pinmux_Jaguar+4, 0xFF00000, 0x12); // 0xCB4[23:16] = 0x12\r
 993                                 PHY_SetBBReg(pAdapter, rB_RFE_Pinmux_Jaguar+4, 0xFF00000, 0x12); // 0xEB4[23:16] = 0x12\r
 994                         } else if (pHalData->ExternalPA_2G) {\r
 995                                 PHY_SetBBReg(pAdapter, rA_RFE_Pinmux_Jaguar+4, 0xFF00000, 0x11); // 0xCB4[23:16] = 0x11\r
 996                                 PHY_SetBBReg(pAdapter, rB_RFE_Pinmux_Jaguar+4, 0xFF00000, 0x11); // 0xEB4[23:16] = 0x11\r
 997                         }\r
 998                         */\r
 999                 }\r
1000                 else\r
1001                 {\r
1002                         // Turn On SingleTone and turn off the other test modes.\r
1003                         PHY_SetBBReg(pAdapter, rOFDM1_LSTF, BIT30|BIT29|BIT28, OFDM_SingleTone);                        \r
1004                 }\r
1005 \r
1006 \r
1007                 write_bbreg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000500);\r
1008                 write_bbreg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000500);\r
1009 \r
1010         }\r
1011         else// Stop Single Tone.\r
1012         {\r
1013         // Stop Single Tone.\r
1014                 if (IS_HARDWARE_TYPE_8188E(pAdapter))\r
1015                 {\r
1016             PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, LNA_Low_Gain_3, bRFRegOffsetMask, pMptCtx->backup0x58_RF_A);\r
1017                         \r
1018                 PHY_SetBBReg(pAdapter, rFPGA0_RFMOD, bCCKEn, 0x1);\r
1019                 PHY_SetBBReg(pAdapter, rFPGA0_RFMOD, bOFDMEn, 0x1);\r
1020                 }               \r
1021                 else if (IS_HARDWARE_TYPE_8192E(pAdapter))\r
1022                 {\r
1023                         PHY_SetRFReg(pAdapter, pMptCtx->MptRfPath, RF_AC, 0xF0000, 0x3); // Tx mode\r
1024                         PHY_SetRFReg(pAdapter, pMptCtx->MptRfPath, LNA_Low_Gain_3, BIT1, 0x0); // RF LO disabled        \r
1025                 }                                               \r
1026                 else if (IS_HARDWARE_TYPE_8723B(pAdapter))\r
1027                 {\r
1028                         if (pMptCtx->MptRfPath == ODM_RF_PATH_A) {\r
1029                                 PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, RF_AC, 0xF0000, 0x3); // Rx mode\r
1030                                 PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, 0x56, 0xF, 0x0); // RF LO disabled\r
1031                         } else {\r
1032                                 // S0/S1 both use PATH A to configure\r
1033                                 PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, RF_AC, 0xF0000, 0x3); // Rx mode\r
1034                                 PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, 0x76, 0xF, 0x0); // RF LO disabled\r
1035                         }       \r
1036                 }               \r
1037         else if (IS_HARDWARE_TYPE_JAGUAR(pAdapter)) \r
1038                 {\r
1039                         /*\r
1040                         u1Byte p = ODM_RF_PATH_A;\r
1041 \r
1042                         PHY_SetBBReg(pAdapter, rOFDMCCKEN_Jaguar, BIT29|BIT28, 0x3); // Disable CCK and OFDM\r
1043 \r
1044                         if (pMptCtx->MptRfPath == RF_PATH_AB) {\r
1045                                 for (p = ODM_RF_PATH_A; p <= ODM_RF_PATH_B; ++p) {                                      \r
1046                                         PHY_SetRFReg(pAdapter, p, RF_AC_Jaguar, bRFRegOffsetMask, regRF0x0);\r
1047                                         PHY_SetRFReg(pAdapter, p, LNA_Low_Gain_3, BIT1, 0x0); // RF LO disabled\r
1048                                 }\r
1049                 } else {\r
1050                                 PHY_SetRFReg(pAdapter, p, RF_AC_Jaguar, bRFRegOffsetMask, regRF0x0);\r
1051                                 PHY_SetRFReg(pAdapter, p, LNA_Low_Gain_3, BIT1, 0x0); // RF LO disabled\r
1052                         }\r
1053                         PHY_SetBBReg(pAdapter, rA_RFE_Pinmux_Jaguar, bMaskDWord, reg0xCB0); \r
1054                         PHY_SetBBReg(pAdapter, rB_RFE_Pinmux_Jaguar, bMaskDWord, reg0xEB0); \r
1055                         PHY_SetBBReg(pAdapter, rA_RFE_Pinmux_Jaguar+4, bMaskDWord, reg0xCB4);\r
1056                         PHY_SetBBReg(pAdapter, rB_RFE_Pinmux_Jaguar+4, bMaskDWord, reg0xEB4); \r
1057                         */\r
1058             }   \r
1059                 else\r
1060                 {\r
1061                         // Turn off all test modes.     \r
1062                         /*\r
1063                         PHY_SetBBReg(pAdapter, rSingleTone_ContTx_Jaguar, BIT18|BIT17|BIT16, OFDM_ALL_OFF);\r
1064                         */\r
1065                 }\r
1066 \r
1067                 write_bbreg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000100);\r
1068                 write_bbreg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000100);\r
1069 \r
1070         }\r
1071 \r
1072 }\r
1073 \r
1074 \r
1075 void Hal_SetCarrierSuppressionTx(PADAPTER pAdapter, u8 bStart)\r
1076 {\r
1077         pAdapter->mppriv.MptCtx.bCarrierSuppression = bStart;\r
1078         if (bStart) // Start Carrier Suppression.\r
1079         {\r
1080                 RT_TRACE(_module_mp_,_drv_alert_, ("SetCarrierSuppressionTx: test start\n"));\r
1081                 //if(pMgntInfo->dot11CurrentWirelessMode == WIRELESS_MODE_B)\r
1082                 if (pAdapter->mppriv.rateidx <= MPT_RATE_11M)\r
1083                   {\r
1084                         // 1. if CCK block on?\r
1085                         if(!read_bbreg(pAdapter, rFPGA0_RFMOD, bCCKEn))\r
1086                                 write_bbreg(pAdapter, rFPGA0_RFMOD, bCCKEn, bEnable);//set CCK block on\r
1087 \r
1088                         //Turn Off All Test Mode\r
1089                         write_bbreg(pAdapter, rOFDM1_LSTF, bOFDMContinueTx, bDisable);\r
1090                         write_bbreg(pAdapter, rOFDM1_LSTF, bOFDMSingleCarrier, bDisable);\r
1091                         write_bbreg(pAdapter, rOFDM1_LSTF, bOFDMSingleTone, bDisable);\r
1092 \r
1093                         write_bbreg(pAdapter, rCCK0_System, bCCKBBMode, 0x2);    //transmit mode\r
1094                         write_bbreg(pAdapter, rCCK0_System, bCCKScramble, 0x0);  //turn off scramble setting\r
1095 \r
1096                         //Set CCK Tx Test Rate\r
1097                         //PHY_SetBBReg(pAdapter, rCCK0_System, bCCKTxRate, pMgntInfo->ForcedDataRate);\r
1098                         write_bbreg(pAdapter, rCCK0_System, bCCKTxRate, 0x0);    //Set FTxRate to 1Mbps\r
1099                 }\r
1100 \r
1101                  //Set for dynamic set Power index\r
1102                  write_bbreg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000500);\r
1103                  write_bbreg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000500);\r
1104 \r
1105         }\r
1106         else// Stop Carrier Suppression.\r
1107         {\r
1108                 RT_TRACE(_module_mp_,_drv_alert_, ("SetCarrierSuppressionTx: test stop\n"));\r
1109                 //if(pMgntInfo->dot11CurrentWirelessMode == WIRELESS_MODE_B)\r
1110                 if (pAdapter->mppriv.rateidx <= MPT_RATE_11M ) {\r
1111                         write_bbreg(pAdapter, rCCK0_System, bCCKBBMode, 0x0);    //normal mode\r
1112                         write_bbreg(pAdapter, rCCK0_System, bCCKScramble, 0x1);  //turn on scramble setting\r
1113 \r
1114                         //BB Reset\r
1115                         write_bbreg(pAdapter, rPMAC_Reset, bBBResetB, 0x0);\r
1116                         write_bbreg(pAdapter, rPMAC_Reset, bBBResetB, 0x1);\r
1117                 }\r
1118                 //Stop for dynamic set Power index\r
1119                 write_bbreg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000100);\r
1120                 write_bbreg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000100);\r
1121         }\r
1122         //DbgPrint("\n MPT_ProSetCarrierSupp() is finished. \n");\r
1123 }\r
1124 \r
1125 void Hal_SetCCKContinuousTx(PADAPTER pAdapter, u8 bStart)\r
1126 {\r
1127         u32 cckrate;\r
1128 \r
1129         if (bStart)\r
1130         {\r
1131                 RT_TRACE(_module_mp_, _drv_alert_,\r
1132                          ("SetCCKContinuousTx: test start\n"));\r
1133 \r
1134                 // 1. if CCK block on?\r
1135                 if(!read_bbreg(pAdapter, rFPGA0_RFMOD, bCCKEn))\r
1136                         write_bbreg(pAdapter, rFPGA0_RFMOD, bCCKEn, bEnable);//set CCK block on\r
1137 \r
1138                 //Turn Off All Test Mode\r
1139                 //if (IS_HARDWARE_TYPE_JAGUAR(pAdapter))\r
1140                         //PHY_SetBBReg(pAdapter, rSingleTone_ContTx_Jaguar, BIT18|BIT17|BIT16, OFDM_ALL_OFF);\r
1141                 //else\r
1142                         PHY_SetBBReg(pAdapter, rOFDM1_LSTF, BIT30|BIT29|BIT28, OFDM_ALL_OFF);\r
1143                 //Set CCK Tx Test Rate\r
1144                 #if 0\r
1145                 switch(pAdapter->mppriv.rateidx)\r
1146                 {\r
1147                         case 2:\r
1148                                 cckrate = 0;\r
1149                                 break;\r
1150                         case 4:\r
1151                                 cckrate = 1;\r
1152                                 break;\r
1153                         case 11:\r
1154                                 cckrate = 2;\r
1155                                 break;\r
1156                         case 22:\r
1157                                 cckrate = 3;\r
1158                                 break;\r
1159                         default:\r
1160                                 cckrate = 0;\r
1161                                 break;\r
1162                 }\r
1163                 #else\r
1164                 cckrate  = pAdapter->mppriv.rateidx;\r
1165                 #endif\r
1166                 write_bbreg(pAdapter, rCCK0_System, bCCKTxRate, cckrate);\r
1167                 write_bbreg(pAdapter, rCCK0_System, bCCKBBMode, 0x2);   //transmit mode\r
1168                 write_bbreg(pAdapter, rCCK0_System, bCCKScramble, bEnable);     //turn on scramble setting\r
1169 \r
1170                 write_bbreg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000500);\r
1171                 write_bbreg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000500);\r
1172 #ifdef CONFIG_RTL8192C\r
1173                 // Patch for CCK 11M waveform\r
1174                 if (cckrate == MPT_RATE_1M)\r
1175                         write_bbreg(pAdapter, 0xA71, BIT(6), bDisable);\r
1176                 else\r
1177                         write_bbreg(pAdapter, 0xA71, BIT(6), bEnable);\r
1178 #endif\r
1179 \r
1180         }\r
1181         else {\r
1182                 RT_TRACE(_module_mp_, _drv_info_,\r
1183                          ("SetCCKContinuousTx: test stop\n"));\r
1184 \r
1185                 write_bbreg(pAdapter, rCCK0_System, bCCKBBMode, 0x0);   //normal mode\r
1186                 write_bbreg(pAdapter, rCCK0_System, bCCKScramble, bEnable);     //turn on scramble setting\r
1187 \r
1188                 //BB Reset\r
1189                 write_bbreg(pAdapter, rPMAC_Reset, bBBResetB, 0x0);\r
1190                 write_bbreg(pAdapter, rPMAC_Reset, bBBResetB, 0x1);\r
1191 \r
1192                 write_bbreg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000100);\r
1193                 write_bbreg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000100);\r
1194         }\r
1195 \r
1196         pAdapter->mppriv.MptCtx.bCckContTx = bStart;\r
1197         pAdapter->mppriv.MptCtx.bOfdmContTx = _FALSE;\r
1198 }/* mpt_StartCckContTx */\r
1199 \r
1200 void Hal_SetOFDMContinuousTx(PADAPTER pAdapter, u8 bStart)\r
1201 {\r
1202     HAL_DATA_TYPE       *pHalData = GET_HAL_DATA(pAdapter);\r
1203 \r
1204         if (bStart) {\r
1205                 RT_TRACE(_module_mp_, _drv_info_, ("SetOFDMContinuousTx: test start\n"));\r
1206                 // 1. if OFDM block on?\r
1207                 if(!read_bbreg(pAdapter, rFPGA0_RFMOD, bOFDMEn))\r
1208                         write_bbreg(pAdapter, rFPGA0_RFMOD, bOFDMEn, bEnable);//set OFDM block on\r
1209         {\r
1210 \r
1211                 // 2. set CCK test mode off, set to CCK normal mode\r
1212                 write_bbreg(pAdapter, rCCK0_System, bCCKBBMode, bDisable);\r
1213 \r
1214                 // 3. turn on scramble setting\r
1215                 write_bbreg(pAdapter, rCCK0_System, bCCKScramble, bEnable);\r
1216         }\r
1217                 // 4. Turn On Continue Tx and turn off the other test modes.\r
1218                 write_bbreg(pAdapter, rOFDM1_LSTF, bOFDMContinueTx, bEnable);\r
1219                 write_bbreg(pAdapter, rOFDM1_LSTF, bOFDMSingleCarrier, bDisable);\r
1220                 write_bbreg(pAdapter, rOFDM1_LSTF, bOFDMSingleTone, bDisable);\r
1221 \r
1222                 write_bbreg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000500);\r
1223                 write_bbreg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000500);\r
1224 \r
1225         } else {\r
1226                 RT_TRACE(_module_mp_,_drv_info_, ("SetOFDMContinuousTx: test stop\n"));\r
1227                 write_bbreg(pAdapter, rOFDM1_LSTF, bOFDMContinueTx, bDisable);\r
1228                 write_bbreg(pAdapter, rOFDM1_LSTF, bOFDMSingleCarrier, bDisable);\r
1229                 write_bbreg(pAdapter, rOFDM1_LSTF, bOFDMSingleTone, bDisable);\r
1230                 //Delay 10 ms\r
1231                 rtw_msleep_os(10);\r
1232                 //BB Reset\r
1233                 write_bbreg(pAdapter, rPMAC_Reset, bBBResetB, 0x0);\r
1234                 write_bbreg(pAdapter, rPMAC_Reset, bBBResetB, 0x1);\r
1235 \r
1236                 write_bbreg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000100);\r
1237                 write_bbreg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000100);\r
1238         }\r
1239 \r
1240         pAdapter->mppriv.MptCtx.bCckContTx = _FALSE;\r
1241         pAdapter->mppriv.MptCtx.bOfdmContTx = bStart;\r
1242 }/* mpt_StartOfdmContTx */\r
1243 \r
1244 void Hal_SetContinuousTx(PADAPTER pAdapter, u8 bStart)\r
1245 {\r
1246 #if 0\r
1247         // ADC turn off [bit24-21] adc port0 ~ port1\r
1248         if (bStart) {\r
1249                 write_bbreg(pAdapter, rRx_Wait_CCCA, read_bbreg(pAdapter, rRx_Wait_CCCA) & 0xFE1FFFFF);\r
1250                 rtw_usleep_os(100);\r
1251         }\r
1252 #endif\r
1253         RT_TRACE(_module_mp_, _drv_info_,\r
1254                  ("SetContinuousTx: rate:%d\n", pAdapter->mppriv.rateidx));\r
1255 \r
1256         pAdapter->mppriv.MptCtx.bStartContTx = bStart;\r
1257 \r
1258         //write_bbreg(pAdapter, rFixContTxRate, bFixContTxRate, bStart);\r
1259 \r
1260         if (pAdapter->mppriv.rateidx <= MPT_RATE_11M)\r
1261         {\r
1262                 Hal_SetCCKContinuousTx(pAdapter, bStart);\r
1263         }\r
1264         else if ((pAdapter->mppriv.rateidx >= MPT_RATE_6M) &&\r
1265                  (pAdapter->mppriv.rateidx <= MPT_RATE_MCS15))\r
1266         {\r
1267                 Hal_SetOFDMContinuousTx(pAdapter, bStart);\r
1268         }\r
1269 #if 0\r
1270         // ADC turn on [bit24-21] adc port0 ~ port1\r
1271         if (!bStart) {\r
1272                 write_bbreg(pAdapter, rRx_Wait_CCCA, read_bbreg(pAdapter, rRx_Wait_CCCA) | 0x01E00000);\r
1273         }\r
1274 #endif\r
1275 }\r
1276 \r
1277 \r
1278 \r
1279 u8 MRateToHwRate8723B( u8 rate)\r
1280 {\r
1281         u8      ret = DESC8723B_RATE1M;\r
1282                 \r
1283         switch(rate)\r
1284         {\r
1285                 // CCK and OFDM non-HT rates\r
1286         case MPT_RATE_1M:               ret = DESC8723B_RATE1M; break;\r
1287         case MPT_RATE_2M:               ret = DESC8723B_RATE2M; break;\r
1288         case MPT_RATE_55M:              ret = DESC8723B_RATE5_5M;       break;\r
1289         case MPT_RATE_11M:              ret = DESC8723B_RATE11M;        break;\r
1290         case MPT_RATE_6M:               ret = DESC8723B_RATE6M; break;\r
1291         case MPT_RATE_9M:               ret = DESC8723B_RATE9M; break;\r
1292         case MPT_RATE_12M:              ret = DESC8723B_RATE12M;        break;\r
1293         case MPT_RATE_18M:              ret = DESC8723B_RATE18M;        break;\r
1294         case MPT_RATE_24M:              ret = DESC8723B_RATE24M;        break;\r
1295         case MPT_RATE_36M:              ret = DESC8723B_RATE36M;        break;\r
1296         case MPT_RATE_48M:              ret = DESC8723B_RATE48M;        break;\r
1297         case MPT_RATE_54M:              ret = DESC8723B_RATE54M;        break;\r
1298 \r
1299                 // HT rates since here\r
1300         case MPT_RATE_MCS0:             ret = DESC8723B_RATEMCS0;       break;\r
1301         case MPT_RATE_MCS1:             ret = DESC8723B_RATEMCS1;       break;\r
1302         case MPT_RATE_MCS2:             ret = DESC8723B_RATEMCS2;       break;\r
1303         case MPT_RATE_MCS3:             ret = DESC8723B_RATEMCS3;       break;\r
1304         case MPT_RATE_MCS4:             ret = DESC8723B_RATEMCS4;       break;\r
1305         case MPT_RATE_MCS5:             ret = DESC8723B_RATEMCS5;       break;\r
1306         case MPT_RATE_MCS6:             ret = DESC8723B_RATEMCS6;       break;\r
1307         case MPT_RATE_MCS7:             ret = DESC8723B_RATEMCS7;       break;\r
1308         case MPT_RATE_MCS8:             ret = DESC8723B_RATEMCS8;       break;\r
1309         case MPT_RATE_MCS9:             ret = DESC8723B_RATEMCS9;       break;\r
1310         case MPT_RATE_MCS10: ret = DESC8723B_RATEMCS10; break;\r
1311         case MPT_RATE_MCS11: ret = DESC8723B_RATEMCS11; break;\r
1312         case MPT_RATE_MCS12: ret = DESC8723B_RATEMCS12; break;\r
1313         case MPT_RATE_MCS13: ret = DESC8723B_RATEMCS13; break;\r
1314         case MPT_RATE_MCS14: ret = DESC8723B_RATEMCS14; break;\r
1315         case MPT_RATE_MCS15: ret = DESC8723B_RATEMCS15; break;\r
1316         case MPT_RATE_VHT1SS_MCS0:              ret = DESC8723B_RATEVHTSS1MCS0; break;\r
1317         case MPT_RATE_VHT1SS_MCS1:              ret = DESC8723B_RATEVHTSS1MCS1; break;\r
1318         case MPT_RATE_VHT1SS_MCS2:              ret = DESC8723B_RATEVHTSS1MCS2; break;\r
1319         case MPT_RATE_VHT1SS_MCS3:              ret = DESC8723B_RATEVHTSS1MCS3; break;\r
1320         case MPT_RATE_VHT1SS_MCS4:              ret = DESC8723B_RATEVHTSS1MCS4; break;\r
1321         case MPT_RATE_VHT1SS_MCS5:              ret = DESC8723B_RATEVHTSS1MCS5; break;\r
1322         case MPT_RATE_VHT1SS_MCS6:              ret = DESC8723B_RATEVHTSS1MCS6; break;\r
1323         case MPT_RATE_VHT1SS_MCS7:              ret = DESC8723B_RATEVHTSS1MCS7; break;\r
1324         case MPT_RATE_VHT1SS_MCS8:              ret = DESC8723B_RATEVHTSS1MCS8; break;\r
1325         case MPT_RATE_VHT1SS_MCS9:              ret = DESC8723B_RATEVHTSS1MCS9; break;  \r
1326         case MPT_RATE_VHT2SS_MCS0:              ret = DESC8723B_RATEVHTSS2MCS0; break;\r
1327         case MPT_RATE_VHT2SS_MCS1:              ret = DESC8723B_RATEVHTSS2MCS1; break;\r
1328         case MPT_RATE_VHT2SS_MCS2:              ret = DESC8723B_RATEVHTSS2MCS2; break;\r
1329         case MPT_RATE_VHT2SS_MCS3:              ret = DESC8723B_RATEVHTSS2MCS3; break;\r
1330         case MPT_RATE_VHT2SS_MCS4:              ret = DESC8723B_RATEVHTSS2MCS4; break;\r
1331         case MPT_RATE_VHT2SS_MCS5:              ret = DESC8723B_RATEVHTSS2MCS5; break;\r
1332         case MPT_RATE_VHT2SS_MCS6:              ret = DESC8723B_RATEVHTSS2MCS6; break;\r
1333         case MPT_RATE_VHT2SS_MCS7:              ret = DESC8723B_RATEVHTSS2MCS7; break;\r
1334         case MPT_RATE_VHT2SS_MCS8:              ret = DESC8723B_RATEVHTSS2MCS8; break;\r
1335         case MPT_RATE_VHT2SS_MCS9:              ret = DESC8723B_RATEVHTSS2MCS9; break;  \r
1336         default:                break;\r
1337         }\r
1338 \r
1339         return ret;\r
1340 }\r
1341 \r
1342 \r
1343 u8 HwRateToMRate8723B(u8         rate)\r
1344 {\r
1345 \r
1346         u8      ret_rate = MGN_1M;\r
1347 \r
1348 \r
1349         switch(rate)\r
1350         {\r
1351         \r
1352                 case DESC8723B_RATE1M:          ret_rate = MGN_1M;              break;\r
1353                 case DESC8723B_RATE2M:          ret_rate = MGN_2M;              break;\r
1354                 case DESC8723B_RATE5_5M:                ret_rate = MGN_5_5M;            break;\r
1355                 case DESC8723B_RATE11M:         ret_rate = MGN_11M;     break;\r
1356                 case DESC8723B_RATE6M:          ret_rate = MGN_6M;              break;\r
1357                 case DESC8723B_RATE9M:          ret_rate = MGN_9M;              break;\r
1358                 case DESC8723B_RATE12M:         ret_rate = MGN_12M;     break;\r
1359                 case DESC8723B_RATE18M:         ret_rate = MGN_18M;     break;\r
1360                 case DESC8723B_RATE24M:         ret_rate = MGN_24M;     break;\r
1361                 case DESC8723B_RATE36M:         ret_rate = MGN_36M;     break;\r
1362                 case DESC8723B_RATE48M:         ret_rate = MGN_48M;     break;\r
1363                 case DESC8723B_RATE54M:         ret_rate = MGN_54M;     break;                  \r
1364                 case DESC8723B_RATEMCS0:        ret_rate = MGN_MCS0;            break;\r
1365                 case DESC8723B_RATEMCS1:        ret_rate = MGN_MCS1;            break;\r
1366                 case DESC8723B_RATEMCS2:        ret_rate = MGN_MCS2;            break;\r
1367                 case DESC8723B_RATEMCS3:        ret_rate = MGN_MCS3;            break;\r
1368                 case DESC8723B_RATEMCS4:        ret_rate = MGN_MCS4;            break;\r
1369                 case DESC8723B_RATEMCS5:        ret_rate = MGN_MCS5;            break;\r
1370                 case DESC8723B_RATEMCS6:        ret_rate = MGN_MCS6;            break;\r
1371                 case DESC8723B_RATEMCS7:        ret_rate = MGN_MCS7;            break;\r
1372                 case DESC8723B_RATEMCS8:        ret_rate = MGN_MCS8;            break;\r
1373                 case DESC8723B_RATEMCS9:        ret_rate = MGN_MCS9;            break;\r
1374                 case DESC8723B_RATEMCS10:       ret_rate = MGN_MCS10;   break;\r
1375                 case DESC8723B_RATEMCS11:       ret_rate = MGN_MCS11;   break;\r
1376                 case DESC8723B_RATEMCS12:       ret_rate = MGN_MCS12;   break;\r
1377                 case DESC8723B_RATEMCS13:       ret_rate = MGN_MCS13;   break;\r
1378                 case DESC8723B_RATEMCS14:       ret_rate = MGN_MCS14;   break;\r
1379                 case DESC8723B_RATEMCS15:       ret_rate = MGN_MCS15;   break;\r
1380                 case DESC8723B_RATEVHTSS1MCS0:  ret_rate = MGN_VHT1SS_MCS0;     break;\r
1381                 case DESC8723B_RATEVHTSS1MCS1:  ret_rate = MGN_VHT1SS_MCS1;     break;\r
1382                 case DESC8723B_RATEVHTSS1MCS2:  ret_rate = MGN_VHT1SS_MCS2;     break;\r
1383                 case DESC8723B_RATEVHTSS1MCS3:  ret_rate = MGN_VHT1SS_MCS3;     break;\r
1384                 case DESC8723B_RATEVHTSS1MCS4:  ret_rate = MGN_VHT1SS_MCS4;     break;\r
1385                 case DESC8723B_RATEVHTSS1MCS5:  ret_rate = MGN_VHT1SS_MCS5;     break;\r
1386                 case DESC8723B_RATEVHTSS1MCS6:  ret_rate = MGN_VHT1SS_MCS6;     break;\r
1387                 case DESC8723B_RATEVHTSS1MCS7:  ret_rate = MGN_VHT1SS_MCS7;     break;\r
1388                 case DESC8723B_RATEVHTSS1MCS8:  ret_rate = MGN_VHT1SS_MCS8;     break;\r
1389                 case DESC8723B_RATEVHTSS1MCS9:  ret_rate = MGN_VHT1SS_MCS9;     break;\r
1390                 case DESC8723B_RATEVHTSS2MCS0:  ret_rate = MGN_VHT2SS_MCS0;     break;\r
1391                 case DESC8723B_RATEVHTSS2MCS1:  ret_rate = MGN_VHT2SS_MCS1;     break;\r
1392                 case DESC8723B_RATEVHTSS2MCS2:  ret_rate = MGN_VHT2SS_MCS2;     break;\r
1393                 case DESC8723B_RATEVHTSS2MCS3:  ret_rate = MGN_VHT2SS_MCS3;     break;\r
1394                 case DESC8723B_RATEVHTSS2MCS4:  ret_rate = MGN_VHT2SS_MCS4;     break;\r
1395                 case DESC8723B_RATEVHTSS2MCS5:  ret_rate = MGN_VHT2SS_MCS5;     break;\r
1396                 case DESC8723B_RATEVHTSS2MCS6:  ret_rate = MGN_VHT2SS_MCS6;     break;\r
1397                 case DESC8723B_RATEVHTSS2MCS7:  ret_rate = MGN_VHT2SS_MCS7;     break;\r
1398                 case DESC8723B_RATEVHTSS2MCS8:  ret_rate = MGN_VHT2SS_MCS8;     break;\r
1399                 case DESC8723B_RATEVHTSS2MCS9:  ret_rate = MGN_VHT2SS_MCS9;     break;                          \r
1400                 \r
1401                 default:                                                        \r
1402                         DBG_8192C("HwRateToMRate8723B(): Non supported Rate [%x]!!!\n",rate );\r
1403                         break;\r
1404         }       \r
1405         return ret_rate;\r
1406 }\r
1407 \r
1408 #endif // CONFIG_MP_INCLUDE\r
1409 \r