drivers/net/wireless/rockchip_wlan/rtl8723bu/hal/rtl8723b/usb/usb_halinit.c

   1 /******************************************************************************
   2  *
   3  * Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of version 2 of the GNU General Public License as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program; if not, write to the Free Software Foundation, Inc.,
  16  * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  17  *
  18  *
  19  ******************************************************************************/
  20
  21  #define _USB_HALINIT_C_
  22
  23 #include <rtl8723b_hal.h>
  24 #ifdef CONFIG_WOWLAN
  25 #include "hal_com_h2c.h"
  26 #endif
  27
  28
  29
  30 static void _dbg_dump_macreg(_adapter *padapter)
  31 {
  32         u32 offset = 0;
  33         u32 val32 = 0;
  34         u32 index =0 ;
  35         for(index=0;index<64;index++)
  36         {
  37                 offset = index*4;
  38                 val32 = rtw_read32(padapter,offset);
  39                 DBG_8192C("offset : 0x%02x ,val:0x%08x\n",offset,val32);
  40         }
  41 }
  42
  43 static VOID
  44 _ConfigChipOutEP_8723(
  45         IN      PADAPTER        pAdapter,
  46         IN      u8              NumOutPipe
  47         )
  48 {
  49         HAL_DATA_TYPE   *pHalData       = GET_HAL_DATA(pAdapter);
  50
  51
  52         pHalData->OutEpQueueSel = 0;
  53         pHalData->OutEpNumber   = 0;
  54
  55         switch(NumOutPipe){
  56                 case    4:
  57                                 pHalData->OutEpQueueSel=TX_SELE_HQ| TX_SELE_LQ|TX_SELE_NQ;
  58                                 pHalData->OutEpNumber=4;
  59                                 break;
  60                 case    3:
  61                                 pHalData->OutEpQueueSel=TX_SELE_HQ| TX_SELE_LQ|TX_SELE_NQ;
  62                                 pHalData->OutEpNumber=3;
  63                                 break;
  64                 case    2:
  65                                 pHalData->OutEpQueueSel=TX_SELE_HQ| TX_SELE_NQ;
  66                                 pHalData->OutEpNumber=2;
  67                                 break;
  68                 case    1:
  69                                 pHalData->OutEpQueueSel=TX_SELE_HQ;
  70                                 pHalData->OutEpNumber=1;
  71                                 break;
  72                 default:
  73                                 break;
  74
  75         }
  76         DBG_871X("%s OutEpQueueSel(0x%02x), OutEpNumber(%d) \n",__FUNCTION__,pHalData->OutEpQueueSel,pHalData->OutEpNumber );
  77
  78         }
  79
  80 static BOOLEAN HalUsbSetQueuePipeMapping8723BUsb(
  81         IN      PADAPTER        pAdapter,
  82         IN      u8              NumInPipe,
  83         IN      u8              NumOutPipe
  84         )
  85 {
  86         HAL_DATA_TYPE   *pHalData       = GET_HAL_DATA(pAdapter);
  87         BOOLEAN                 result          = _FALSE;
  88
  89         _ConfigChipOutEP_8723(pAdapter, NumOutPipe);
  90
  91         // Normal chip with one IN and one OUT doesn't have interrupt IN EP.
  92         if(1 == pHalData->OutEpNumber){
  93                 if(1 != NumInPipe){
  94                         return result;
  95                 }
  96         }
  97
  98         // All config other than above support one Bulk IN and one Interrupt IN.
  99         //if(2 != NumInPipe){
 100         //      return result;
 101         //}
 102
 103         result = Hal_MappingOutPipe(pAdapter, NumOutPipe);
 104
 105         return result;
 106
 107 }
 108
 109 void rtl8723bu_interface_configure(_adapter *padapter)
 110 {
 111         HAL_DATA_TYPE   *pHalData       = GET_HAL_DATA(padapter);
 112         struct dvobj_priv       *pdvobjpriv = adapter_to_dvobj(padapter);
 113
 114         if (IS_HIGH_SPEED_USB(padapter))
 115         {
 116                 pHalData->UsbBulkOutSize = USB_HIGH_SPEED_BULK_SIZE;//512 bytes
 117         }
 118         else
 119         {
 120                 pHalData->UsbBulkOutSize = USB_FULL_SPEED_BULK_SIZE;//64 bytes
 121         }
 122
 123         pHalData->interfaceIndex = pdvobjpriv->InterfaceNumber;
 124
 125 #ifdef CONFIG_USB_TX_AGGREGATION
 126         pHalData->UsbTxAggMode          = 1;
 127         pHalData->UsbTxAggDescNum       = 0x6;  // only 4 bits
 128 #endif
 129
 130 #ifdef CONFIG_USB_RX_AGGREGATION
 131         pHalData->UsbRxAggMode          = USB_RX_AGG_USB;
 132         pHalData->UsbRxAggBlockCount    = 0x5; /* unit: 4KB, for USB mode */
 133         pHalData->UsbRxAggBlockTimeout  = 0x20; /* unit: 32us, for USB mode */
 134         pHalData->UsbRxAggPageCount     = 0xF; /* uint: 1KB, for DMA mode */
 135         pHalData->UsbRxAggPageTimeout   = 0x20; /* unit: 32us, for DMA mode */
 136 #endif
 137
 138         HalUsbSetQueuePipeMapping8723BUsb(padapter,
 139                                 pdvobjpriv->RtNumInPipes, pdvobjpriv->RtNumOutPipes);
 140
 141 }
 142
 143 #ifdef CONFIG_GPIO_WAKEUP
 144 //we set it high under init and fw will
 145 //give us Low Pulse when host wake up
 146 void HostWakeUpGpioClear(PADAPTER Adapter)
 147 {
 148         u32     value32;
 149
 150         value32 = rtw_read32(Adapter, REG_GPIO_PIN_CTRL_2);
 151
 152         //set GPIO 12 1
 153         value32 |= BIT(12);//4+8
 154         //GPIO 12 out put
 155         value32 |= BIT(20);//4+16
 156
 157         rtw_write32(Adapter, REG_GPIO_PIN_CTRL_2, value32);
 158 } //HostWakeUpGpioClear
 159
 160 void HalSetOutPutGPIO(PADAPTER padapter, u8 index, u8 OutPutValue)
 161 {
 162         if ( index <= 7 ) {
 163                 /* config GPIO mode */
 164                 rtw_write8(padapter, REG_GPIO_PIN_CTRL + 3, rtw_read8(padapter, REG_GPIO_PIN_CTRL + 3) & ~BIT(index) );
 165
 166                 /* config GPIO Sel */
 167                 /* 0: input */
 168                 /* 1: output */
 169                 rtw_write8(padapter, REG_GPIO_PIN_CTRL + 2, rtw_read8(padapter, REG_GPIO_PIN_CTRL + 2) | BIT(index));
 170
 171                 /* set output value */
 172                 if ( OutPutValue ) {
 173                         rtw_write8(padapter, REG_GPIO_PIN_CTRL + 1, rtw_read8(padapter, REG_GPIO_PIN_CTRL + 1) | BIT(index));
 174                 } else {
 175                         rtw_write8(padapter, REG_GPIO_PIN_CTRL + 1, rtw_read8(padapter, REG_GPIO_PIN_CTRL + 1) & ~BIT(index));
 176                 }
 177         } else {
 178                 /* 88C Series: */
 179                 /* index: 11~8 transform to 3~0 */
 180                 /* 8723 Series: */
 181                 /* index: 12~8 transform to 4~0 */
 182                 index -= 8;
 183
 184                 /* config GPIO mode */
 185                 rtw_write8(padapter, REG_GPIO_PIN_CTRL_2 + 3, rtw_read8(padapter, REG_GPIO_PIN_CTRL_2 + 3) & ~BIT(index) );
 186
 187                 /* config GPIO Sel */
 188                 /* 0: input */
 189                 /* 1: output */
 190                 rtw_write8(padapter, REG_GPIO_PIN_CTRL_2 + 2, rtw_read8(padapter, REG_GPIO_PIN_CTRL_2 + 2) | BIT(index));
 191
 192                 /* set output value */
 193                 if ( OutPutValue ) {
 194                         rtw_write8(padapter, REG_GPIO_PIN_CTRL_2 + 1, rtw_read8(padapter, REG_GPIO_PIN_CTRL_2 + 1) | BIT(index));
 195                 } else {
 196                         rtw_write8(padapter, REG_GPIO_PIN_CTRL_2 + 1, rtw_read8(padapter, REG_GPIO_PIN_CTRL_2 + 1) & ~BIT(index));
 197                 }
 198         }
 199 }
 200 #endif
 201
 202 static u32 _InitPowerOn_8723BU(PADAPTER padapter)
 203 {
 204         u8              status = _SUCCESS;
 205         u16                     value16=0;
 206         u8                      value8 = 0;
 207         u32 value32;
 208
 209         rtw_hal_get_hwreg(padapter, HW_VAR_APFM_ON_MAC, &value8);
 210         if (value8 == _TRUE)
 211                 return _SUCCESS;
 212
 213         // HW Power on sequence
 214         if(!HalPwrSeqCmdParsing(padapter, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, rtl8723B_card_enable_flow ))
 215                 return _FAIL;
 216
 217         // Enable MAC DMA/WMAC/SCHEDULE/SEC block
 218         // Set CR bit10 to enable 32k calibration. Suggested by SD1 Gimmy. Added by tynli. 2011.08.31.
 219         rtw_write8(padapter, REG_CR_8723B, 0x00);  //suggseted by zhouzhou, by page, 20111230
 220         value16 = rtw_read16(padapter, REG_CR_8723B);
 221         value16 |= (HCI_TXDMA_EN | HCI_RXDMA_EN | TXDMA_EN | RXDMA_EN
 222                                 | PROTOCOL_EN | SCHEDULE_EN | ENSEC | CALTMR_EN);
 223         rtw_write16(padapter, REG_CR_8723B, value16);
 224
 225         value8 = _TRUE;
 226         rtw_hal_set_hwreg(padapter, HW_VAR_APFM_ON_MAC, &value8);
 227
 228 #ifdef CONFIG_BT_COEXIST
 229         rtw_btcoex_PowerOnSetting(padapter);
 230
 231         // external switch to S1
 232         // 0x38[11] = 0x1
 233         // 0x4c[23] = 0x1
 234         // 0x64[0] = 0
 235         value16 = rtw_read16(padapter, REG_PWR_DATA);
 236         // Switch the control of EESK, EECS to RFC for DPDT or Antenna switch
 237         value16 |= BIT(11); // BIT_EEPRPAD_RFE_CTRL_EN
 238         rtw_write16(padapter, REG_PWR_DATA, value16);
 239         //DBG_8192C("%s: REG_PWR_DATA(0x%x)=0x%04X\n", __FUNCTION__, REG_PWR_DATA, rtw_read16(padapter, REG_PWR_DATA));
 240
 241         value32 = rtw_read32(padapter, REG_LEDCFG0);
 242         value32 |= BIT(23); // DPDT_SEL_EN, 1 for SW control
 243         rtw_write32(padapter, REG_LEDCFG0, value32);
 244         //DBG_8192C("%s: REG_LEDCFG0(0x%x)=0x%08X\n", __FUNCTION__, REG_LEDCFG0, rtw_read32(padapter, REG_LEDCFG0));
 245
 246         value8 = rtw_read8(padapter, REG_PAD_CTRL1_8723B);
 247         value8 &= ~BIT(0); // BIT_SW_DPDT_SEL_DATA, DPDT_SEL default configuration
 248         rtw_write8(padapter, REG_PAD_CTRL1_8723B, value8);
 249         //DBG_8192C("%s: REG_PAD_CTRL1(0x%x)=0x%02X\n", __FUNCTION__, REG_PAD_CTRL1_8723B, rtw_read8(padapter, REG_PAD_CTRL1_8723B));
 250 #endif // CONFIG_BT_COEXIST
 251
 252         return status;
 253 }
 254
 255
 256
 257 //-------------------------------------------------------------------------
 258 //
 259 // LLT R/W/Init function
 260 //
 261 //-------------------------------------------------------------------------
 262 static u8 _LLTWrite(
 263         IN  PADAPTER    Adapter,
 264         IN      u32             address,
 265         IN      u32             data
 266         )
 267 {
 268         u8      status = _SUCCESS;
 269         s8      count = POLLING_LLT_THRESHOLD;
 270         u32     value = _LLT_INIT_ADDR(address) | _LLT_INIT_DATA(data) | _LLT_OP(_LLT_WRITE_ACCESS);
 271
 272         rtw_write32(Adapter, REG_LLT_INIT, value);
 273
 274         //polling
 275         do{
 276                 value = rtw_read32(Adapter, REG_LLT_INIT);
 277                 if(_LLT_NO_ACTIVE == _LLT_OP_VALUE(value)){
 278                         break;
 279                 }
 280         }while(--count);
 281
 282         if(count <= 0){
 283                 DBG_871X("Failed to polling write LLT done at address %d!\n", address);
 284                 status = _FAIL;
 285         }
 286         return status;
 287
 288 }
 289
 290
 291 static u8 _LLTRead(
 292         IN  PADAPTER    Adapter,
 293         IN      u32             address
 294         )
 295 {
 296         int             count = 0;
 297         u32             value = _LLT_INIT_ADDR(address) | _LLT_OP(_LLT_READ_ACCESS);
 298
 299         rtw_write32(Adapter, REG_LLT_INIT, value);
 300
 301         //polling and get value
 302         do{
 303
 304                 value = rtw_read32(Adapter, REG_LLT_INIT);
 305                 if(_LLT_NO_ACTIVE == _LLT_OP_VALUE(value)){
 306                         return (u8)value;
 307                 }
 308
 309                 if(count > POLLING_LLT_THRESHOLD){
 310                         //RT_TRACE(COMP_INIT,DBG_SERIOUS,("Failed to polling read LLT done at address %d!\n", address));
 311                         break;
 312                 }
 313         }while(count++);
 314
 315         return 0xFF;
 316
 317 }
 318
 319
 320 //---------------------------------------------------------------
 321 //
 322 //      MAC init functions
 323 //
 324 //---------------------------------------------------------------
 325
 326 // Shall USB interface init this?
 327 static VOID
 328 _InitInterrupt(
 329         IN  PADAPTER Adapter
 330         )
 331 {
 332         u32     value32;
 333
 334         // HISR - turn all on
 335         value32 = 0xFFFFFFFF;
 336         rtw_write32(Adapter, REG_HISR, value32);
 337
 338         // HIMR - turn all on
 339         rtw_write32(Adapter, REG_HIMR, value32);
 340 }
 341
 342 static void _InitQueueReservedPage(PADAPTER padapter)
 343 {
 344         HAL_DATA_TYPE           *pHalData = GET_HAL_DATA(padapter);
 345         struct registry_priv    *pregistrypriv = &padapter->registrypriv;
 346         u32                     outEPNum        = (u32)pHalData->OutEpNumber;
 347         u32                     numHQ           = 0;
 348         u32                     numLQ           = 0;
 349         u32                     numNQ           = 0;
 350         u32                     numPubQ;
 351         u32                     value32;
 352         u8                      value8;
 353         BOOLEAN         bWiFiConfig     = pregistrypriv->wifi_spec;
 354
 355         if (pHalData->OutEpQueueSel & TX_SELE_HQ)
 356         {
 357                 numHQ = bWiFiConfig ? WMM_NORMAL_PAGE_NUM_HPQ_8723B : NORMAL_PAGE_NUM_HPQ_8723B;
 358         }
 359
 360         if (pHalData->OutEpQueueSel & TX_SELE_LQ)
 361         {
 362                 numLQ = bWiFiConfig ? WMM_NORMAL_PAGE_NUM_LPQ_8723B : NORMAL_PAGE_NUM_LPQ_8723B;
 363         }
 364
 365         // NOTE: This step shall be proceed before writting REG_RQPN.
 366         if (pHalData->OutEpQueueSel & TX_SELE_NQ) {
 367                         numNQ = bWiFiConfig ? WMM_NORMAL_PAGE_NUM_NPQ_8723B : NORMAL_PAGE_NUM_NPQ_8723B;
 368         }
 369         value8 = (u8)_NPQ(numNQ);
 370         rtw_write8(padapter, REG_RQPN_NPQ, value8);
 371
 372         numPubQ = TX_TOTAL_PAGE_NUMBER_8723B - numHQ - numLQ - numNQ;
 373
 374         // TX DMA
 375         value32 = _HPQ(numHQ) | _LPQ(numLQ) | _PUBQ(numPubQ) | LD_RQPN;
 376         rtw_write32(padapter, REG_RQPN, value32);
 377
 378 }
 379
 380 static void _InitTxBufferBoundary(PADAPTER padapter)
 381 {
 382         struct registry_priv *pregistrypriv = &padapter->registrypriv;
 383 #ifdef CONFIG_CONCURRENT_MODE
 384         u8 val8;
 385 #endif // CONFIG_CONCURRENT_MODE
 386
 387         //u16   txdmactrl;
 388         u8      txpktbuf_bndy;
 389
 390         if(!pregistrypriv->wifi_spec){
 391                 txpktbuf_bndy = TX_PAGE_BOUNDARY_8723B;
 392         } else {
 393                 //for WMM
 394                 txpktbuf_bndy = WMM_NORMAL_TX_PAGE_BOUNDARY_8723B;
 395         }
 396
 397         rtw_write8(padapter, REG_TXPKTBUF_BCNQ_BDNY_8723B, txpktbuf_bndy);
 398         rtw_write8(padapter, REG_TXPKTBUF_MGQ_BDNY_8723B, txpktbuf_bndy);
 399         rtw_write8(padapter, REG_TXPKTBUF_WMAC_LBK_BF_HD_8723B, txpktbuf_bndy);
 400         rtw_write8(padapter, REG_TRXFF_BNDY, txpktbuf_bndy);
 401         rtw_write8(padapter, REG_TDECTRL+1, txpktbuf_bndy);
 402
 403 #ifdef CONFIG_CONCURRENT_MODE
 404         val8 = txpktbuf_bndy + 8;
 405         rtw_write8(padapter, REG_BCNQ1_BDNY, val8);
 406         rtw_write8(padapter, REG_DWBCN1_CTRL_8723B+1, val8); // BCN1_HEAD
 407
 408         val8 = rtw_read8(padapter, REG_DWBCN1_CTRL_8723B+2);
 409         val8 |= BIT(1); // BIT1- BIT_SW_BCN_SEL_EN
 410         rtw_write8(padapter, REG_DWBCN1_CTRL_8723B+2, val8);
 411 #endif // CONFIG_CONCURRENT_MODE
 412 }
 413
 414
 415 VOID
 416 _InitTransferPageSize_8723bu(
 417           PADAPTER Adapter
 418         )
 419 {
 420
 421         u1Byte  value8;
 422         value8 = _PSRX(PBP_256) | _PSTX(PBP_256);
 423
 424         rtw_write8(Adapter, REG_PBP_8723B, value8);
 425 }
 426
 427
 428 static VOID
 429 _InitNormalChipRegPriority(
 430         IN      PADAPTER        Adapter,
 431         IN      u16             beQ,
 432         IN      u16             bkQ,
 433         IN      u16             viQ,
 434         IN      u16             voQ,
 435         IN      u16             mgtQ,
 436         IN      u16             hiQ
 437         )
 438 {
 439         u16 value16             = (rtw_read16(Adapter, REG_TRXDMA_CTRL_8723B) & 0x7);
 440
 441         value16 |=      _TXDMA_BEQ_MAP(beQ)     | _TXDMA_BKQ_MAP(bkQ) |
 442                                 _TXDMA_VIQ_MAP(viQ)     | _TXDMA_VOQ_MAP(voQ) |
 443                                 _TXDMA_MGQ_MAP(mgtQ)| _TXDMA_HIQ_MAP(hiQ);
 444
 445         rtw_write16(Adapter, REG_TRXDMA_CTRL_8723B, value16);
 446 }
 447
 448
 449 static VOID
 450 _InitNormalChipTwoOutEpPriority(
 451         IN      PADAPTER Adapter
 452         )
 453 {
 454         HAL_DATA_TYPE   *pHalData       = GET_HAL_DATA(Adapter);
 455         struct registry_priv *pregistrypriv = &Adapter->registrypriv;
 456         u16                     beQ,bkQ,viQ,voQ,mgtQ,hiQ;
 457
 458
 459         u16     valueHi = 0;
 460         u16     valueLow = 0;
 461
 462         switch(pHalData->OutEpQueueSel)
 463         {
 464                 case (TX_SELE_HQ | TX_SELE_LQ):
 465                         valueHi = QUEUE_HIGH;
 466                         valueLow = QUEUE_LOW;
 467                         break;
 468                 case (TX_SELE_NQ | TX_SELE_LQ):
 469                         valueHi = QUEUE_NORMAL;
 470                         valueLow = QUEUE_LOW;
 471                         break;
 472                 case (TX_SELE_HQ | TX_SELE_NQ):
 473                         valueHi = QUEUE_HIGH;
 474                         valueLow = QUEUE_NORMAL;
 475                         break;
 476                 default:
 477                         //RT_ASSERT(FALSE,("Shall not reach here!\n"));
 478                         break;
 479         }
 480
 481         if(!pregistrypriv->wifi_spec ){
 482                 beQ             = valueLow;
 483                 bkQ             = valueLow;
 484                 viQ             = valueHi;
 485                 voQ             = valueHi;
 486                 mgtQ    = valueHi;
 487                 hiQ             = valueHi;
 488         }
 489         else{//for WMM ,CONFIG_OUT_EP_WIFI_MODE
 490                 beQ             = valueLow;
 491                 bkQ             = valueHi;
 492                 viQ             = valueHi;
 493                 voQ             = valueLow;
 494                 mgtQ    = valueHi;
 495                 hiQ             = valueHi;
 496         }
 497
 498         _InitNormalChipRegPriority(Adapter,beQ,bkQ,viQ,voQ,mgtQ,hiQ);
 499
 500 }
 501
 502 static VOID
 503 _InitNormalChipThreeOutEpPriority(
 504         IN      PADAPTER padapter
 505         )
 506 {
 507         struct registry_priv *pregistrypriv = &padapter->registrypriv;
 508         u16                     beQ,bkQ,viQ,voQ,mgtQ,hiQ;
 509
 510         if(!pregistrypriv->wifi_spec ){// typical setting
 511                 beQ             = QUEUE_LOW;
 512                 bkQ             = QUEUE_LOW;
 513                 viQ             = QUEUE_NORMAL;
 514                 voQ             = QUEUE_HIGH;
 515                 mgtQ    = QUEUE_HIGH;
 516                 hiQ             = QUEUE_HIGH;
 517         }
 518         else{// for WMM
 519                 beQ             = QUEUE_LOW;
 520                 bkQ             = QUEUE_NORMAL;
 521                 viQ             = QUEUE_NORMAL;
 522                 voQ             = QUEUE_HIGH;
 523                 mgtQ    = QUEUE_HIGH;
 524                 hiQ             = QUEUE_HIGH;
 525         }
 526         _InitNormalChipRegPriority(padapter,beQ,bkQ,viQ,voQ,mgtQ,hiQ);
 527 }
 528
 529 static void _InitQueuePriority(PADAPTER padapter)
 530 {
 531         HAL_DATA_TYPE   *pHalData       = GET_HAL_DATA(padapter);
 532         switch(pHalData->OutEpNumber)
 533         {
 534                 case 2:
 535                         _InitNormalChipTwoOutEpPriority(padapter);
 536                         break;
 537                 case 3:
 538                 case 4:
 539                         _InitNormalChipThreeOutEpPriority(padapter);
 540                         break;
 541                 default:
 542                         //RT_ASSERT(FALSE,("Shall not reach here!\n"));
 543                         break;
 544         }
 545
 546 }
 547
 548
 549 static void _InitPageBoundary(PADAPTER padapter)
 550 {
 551         /* RX FIFO(RXFF0) Boundary, unit is byte */
 552         rtw_write16(padapter, REG_TRXFF_BNDY+2, RX_DMA_BOUNDARY_8723B);
 553 }
 554
 555 static VOID
 556 _InitHardwareDropIncorrectBulkOut(
 557         IN  PADAPTER Adapter
 558         )
 559 {
 560         u32     value32 = rtw_read32(Adapter, REG_TXDMA_OFFSET_CHK);
 561         value32 |= DROP_DATA_EN;
 562         rtw_write32(Adapter, REG_TXDMA_OFFSET_CHK, value32);
 563 }
 564
 565 static VOID
 566 _InitNetworkType(
 567         IN  PADAPTER Adapter
 568         )
 569 {
 570         u32     value32;
 571
 572         value32 = rtw_read32(Adapter, REG_CR);
 573
 574         // TODO: use the other function to set network type
 575 #if 0//RTL8191C_FPGA_NETWORKTYPE_ADHOC
 576         value32 = (value32 & ~MASK_NETTYPE) | _NETTYPE(NT_LINK_AD_HOC);
 577 #else
 578         value32 = (value32 & ~MASK_NETTYPE) | _NETTYPE(NT_LINK_AP);
 579 #endif
 580         rtw_write32(Adapter, REG_CR, value32);
 581 //      RASSERT(pIoBase->rtw_read8(REG_CR + 2) == 0x2);
 582 }
 583
 584
 585 static VOID
 586 _InitDriverInfoSize(
 587         IN  PADAPTER    Adapter,
 588         IN      u8              drvInfoSize
 589         )
 590 {
 591         rtw_write8(Adapter,REG_RX_DRVINFO_SZ, drvInfoSize);
 592 }
 593
 594 static VOID
 595 _InitWMACSetting(
 596         IN  PADAPTER Adapter
 597         )
 598 {
 599         //u4Byte                        value32;
 600         u16                     value16;
 601         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(Adapter);
 602
 603 //      pHalData->ReceiveConfig = AAP | APM | AM |AB  |ADD3|APWRMGT| APP_ICV | APP_MIC |APP_FCS|ADF |ACF|AMF|HTC_LOC_CTRL|APP_PHYSTS;
 604         pHalData->ReceiveConfig = AAP | APM | AM |AB  |ADD3|APWRMGT| APP_ICV | APP_MIC |ADF |ACF|AMF|HTC_LOC_CTRL|APP_PHYSTS;
 605
 606         rtw_write32(Adapter, REG_RCR, pHalData->ReceiveConfig);
 607
 608         // Accept all data frames
 609         value16 = 0xFFFF;
 610         rtw_write16(Adapter, REG_RXFLTMAP2_8723B, value16);
 611
 612         // 2010.09.08 hpfan
 613         // Since ADF is removed from RCR, ps-poll will not be indicate to driver,
 614         // RxFilterMap should mask ps-poll to gurantee AP mode can rx ps-poll.
 615
 616         value16 = 0x400;
 617         rtw_write16(Adapter, REG_RXFLTMAP1_8723B, value16);
 618
 619         // Accept all management frames
 620         value16 = 0xFFFF;
 621         rtw_write16(Adapter, REG_RXFLTMAP0_8723B, value16);
 622
 623 }
 624
 625 static VOID
 626 _InitAdaptiveCtrl(
 627         IN  PADAPTER Adapter
 628         )
 629 {
 630         u16     value16;
 631         u32     value32;
 632
 633         // Response Rate Set
 634         value32 = rtw_read32(Adapter, REG_RRSR);
 635         value32 &= ~RATE_BITMAP_ALL;
 636         value32 |= RATE_RRSR_CCK_ONLY_1M;
 637         rtw_write32(Adapter, REG_RRSR, value32);
 638
 639         // CF-END Threshold
 640         //m_spIoBase->rtw_write8(REG_CFEND_TH, 0x1);
 641
 642         // SIFS (used in NAV)
 643         value16 = _SPEC_SIFS_CCK(0x10) | _SPEC_SIFS_OFDM(0x10);
 644         rtw_write16(Adapter, REG_SPEC_SIFS, value16);
 645
 646         // Retry Limit
 647         value16 = _LRL(0x30) | _SRL(0x30);
 648         rtw_write16(Adapter, REG_RL, value16);
 649
 650 }
 651
 652 static VOID
 653 _InitRateFallback(
 654         IN  PADAPTER Adapter
 655         )
 656 {
 657         // Set Data Auto Rate Fallback Retry Count register.
 658         rtw_write32(Adapter, REG_DARFRC, 0x00000000);
 659         rtw_write32(Adapter, REG_DARFRC+4, 0x10080404);
 660         rtw_write32(Adapter, REG_RARFRC, 0x04030201);
 661         rtw_write32(Adapter, REG_RARFRC+4, 0x08070605);
 662
 663 }
 664
 665
 666 static VOID
 667 _InitEDCA(
 668         IN  PADAPTER Adapter
 669         )
 670 {
 671         // Set Spec SIFS (used in NAV)
 672         rtw_write16(Adapter,REG_SPEC_SIFS, 0x100a);
 673         rtw_write16(Adapter,REG_MAC_SPEC_SIFS, 0x100a);
 674
 675         // Set SIFS for CCK
 676         rtw_write16(Adapter,REG_SIFS_CTX, 0x100a);
 677
 678         // Set SIFS for OFDM
 679         rtw_write16(Adapter,REG_SIFS_TRX, 0x100a);
 680
 681         // TXOP
 682         rtw_write32(Adapter, REG_EDCA_BE_PARAM, 0x005EA42B);
 683         rtw_write32(Adapter, REG_EDCA_BK_PARAM, 0x0000A44F);
 684         rtw_write32(Adapter, REG_EDCA_VI_PARAM, 0x005EA324);
 685         rtw_write32(Adapter, REG_EDCA_VO_PARAM, 0x002FA226);
 686 }
 687
 688 #ifdef CONFIG_LED
 689 static void _InitHWLed(PADAPTER Adapter)
 690 {
 691         struct led_priv *pledpriv = &(Adapter->ledpriv);
 692
 693         if( pledpriv->LedStrategy != HW_LED)
 694                 return;
 695
 696 // HW led control
 697 // to do ....
 698 //must consider cases of antenna diversity/ commbo card/solo card/mini card
 699
 700 }
 701 #endif //CONFIG_LED
 702
 703 static VOID
 704 _InitRDGSetting_8723bu(
 705         IN      PADAPTER Adapter
 706         )
 707 {
 708         rtw_write8(Adapter,REG_RD_CTRL_8723B,0xFF);
 709         rtw_write16(Adapter, REG_RD_NAV_NXT_8723B, 0x200);
 710         rtw_write8(Adapter,REG_RD_RESP_PKT_TH_8723B,0x05);
 711 }
 712
 713 static VOID
 714 _InitRxSetting_8723bu(
 715         IN      PADAPTER Adapter
 716         )
 717 {
 718         rtw_write32(Adapter, REG_MACID, 0x87654321);
 719         rtw_write32(Adapter, 0x0700, 0x87654321);
 720 }
 721
 722 static VOID
 723 _InitRetryFunction(
 724         IN  PADAPTER Adapter
 725         )
 726 {
 727         u8      value8;
 728
 729         value8 = rtw_read8(Adapter, REG_FWHW_TXQ_CTRL);
 730         value8 |= EN_AMPDU_RTY_NEW;
 731         rtw_write8(Adapter, REG_FWHW_TXQ_CTRL, value8);
 732
 733         // Set ACK timeout
 734         rtw_write8(Adapter, REG_ACKTO, 0x40);
 735 }
 736
 737 static void _InitBurstPktLen(PADAPTER padapter)
 738 {
 739         PHAL_DATA_TYPE pHalData = GET_HAL_DATA(padapter);
 740         u8 tmp8;
 741
 742
 743         tmp8 = rtw_read8(padapter, REG_RXDMA_PRO_8723B);
 744         tmp8 &= ~(BIT(4) | BIT(5));
 745         switch (pHalData->UsbBulkOutSize) {
 746         case USB_HIGH_SPEED_BULK_SIZE:
 747                 tmp8 |= BIT(4); // set burst pkt len=512B
 748                 break;
 749         case USB_FULL_SPEED_BULK_SIZE:
 750         default:
 751                 tmp8 |= BIT(5); // set burst pkt len=64B
 752                 break;
 753         }
 754         tmp8 |= BIT(1) | BIT(2) | BIT(3);
 755         rtw_write8(padapter, REG_RXDMA_PRO_8723B, tmp8);
 756
 757         pHalData->bSupportUSB3 = _FALSE;
 758
 759         tmp8 = rtw_read8(padapter, REG_HT_SINGLE_AMPDU_8723B);
 760         tmp8 |= BIT(7); // enable single pkt ampdu
 761         rtw_write8(padapter, REG_HT_SINGLE_AMPDU_8723B, tmp8);
 762         rtw_write16(padapter, REG_MAX_AGGR_NUM, 0x0C14);
 763         rtw_write8(padapter, REG_AMPDU_MAX_TIME_8723B, 0x5E);
 764         rtw_write32(padapter, REG_AMPDU_MAX_LENGTH_8723B, 0xffffffff);
 765         if (pHalData->AMPDUBurstMode)
 766                 rtw_write8(padapter, REG_AMPDU_BURST_MODE_8723B, 0x5F);
 767
 768         // for VHT packet length 11K
 769         rtw_write8(padapter, REG_RX_PKT_LIMIT, 0x18);
 770
 771         rtw_write8(padapter, REG_PIFS, 0x00);
 772         rtw_write8(padapter, REG_FWHW_TXQ_CTRL, 0x80);
 773         rtw_write32(padapter, REG_FAST_EDCA_CTRL, 0x03086666);
 774         rtw_write8(padapter, REG_USTIME_TSF_8723B, 0x50);
 775         rtw_write8(padapter, REG_USTIME_EDCA_8723B, 0x50);
 776
 777         // to prevent mac is reseted by bus. 20111208, by Page
 778         tmp8 = rtw_read8(padapter, REG_RSV_CTRL);
 779         tmp8 |= BIT(5) | BIT(6);
 780         rtw_write8(padapter, REG_RSV_CTRL, tmp8);
 781 }
 782
 783 /*-----------------------------------------------------------------------------
 784  * Function:    usb_AggSettingTxUpdate()
 785  *
 786  * Overview:    Seperate TX/RX parameters update independent for TP detection and
 787  *                      dynamic TX/RX aggreagtion parameters update.
 788  *
 789  * Input:                       PADAPTER
 790  *
 791  * Output/Return:       NONE
 792  *
 793  * Revised History:
 794  *      When            Who             Remark
 795  *      12/10/2010      MHC             Seperate to smaller function.
 796  *
 797  *---------------------------------------------------------------------------*/
 798 static VOID
 799 usb_AggSettingTxUpdate(
 800         IN      PADAPTER                        Adapter
 801         )
 802 {
 803 #ifdef CONFIG_USB_TX_AGGREGATION
 804         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(Adapter);
 805         //PMGNT_INFO            pMgntInfo = &(Adapter->MgntInfo);
 806         u32                     value32;
 807
 808         if(Adapter->registrypriv.wifi_spec)
 809                 pHalData->UsbTxAggMode = _FALSE;
 810
 811         if(pHalData->UsbTxAggMode){
 812                 value32 = rtw_read32(Adapter, REG_DWBCN0_CTRL_8723B);
 813                 value32 = value32 & ~(BLK_DESC_NUM_MASK << BLK_DESC_NUM_SHIFT);
 814                 value32 |= ((pHalData->UsbTxAggDescNum & BLK_DESC_NUM_MASK) << BLK_DESC_NUM_SHIFT);
 815
 816                 rtw_write32(Adapter, REG_DWBCN0_CTRL_8723B, value32);
 817                 rtw_write8(Adapter, REG_DWBCN1_CTRL_8723B, pHalData->UsbTxAggDescNum<<1);
 818         }
 819
 820 #endif
 821 }       // usb_AggSettingTxUpdate
 822
 823
 824 /*-----------------------------------------------------------------------------
 825  * Function:    usb_AggSettingRxUpdate()
 826  *
 827  * Overview:    Seperate TX/RX parameters update independent for TP detection and
 828  *                      dynamic TX/RX aggreagtion parameters update.
 829  *
 830  * Input:                       PADAPTER
 831  *
 832  * Output/Return:       NONE
 833  *
 834  *---------------------------------------------------------------------------*/
 835 static void usb_AggSettingRxUpdate(PADAPTER padapter)
 836 {
 837         PHAL_DATA_TYPE pHalData;
 838         u8 aggctrl;
 839         u32 aggrx;
 840         u32 agg_size;
 841
 842
 843         pHalData = GET_HAL_DATA(padapter);
 844
 845         aggctrl = rtw_read8(padapter, REG_TRXDMA_CTRL);
 846         aggctrl &= ~RXDMA_AGG_EN;
 847
 848         aggrx = rtw_read32(padapter, REG_RXDMA_AGG_PG_TH);
 849         aggrx &= ~BIT_USB_RXDMA_AGG_EN;
 850         aggrx &= ~0xFF0F; // reset agg size and timeout
 851
 852 #ifdef CONFIG_USB_RX_AGGREGATION
 853         switch(pHalData->UsbRxAggMode) {
 854         case USB_RX_AGG_DMA:
 855                 agg_size = pHalData->UsbRxAggPageCount << 10;
 856                 if (agg_size > RX_DMA_BOUNDARY_8723B)
 857                         agg_size = RX_DMA_BOUNDARY_8723B >> 1;
 858                 if ((agg_size + 2048) > MAX_RECVBUF_SZ)
 859                         agg_size = MAX_RECVBUF_SZ - 2048;
 860                 agg_size >>= 10; /* unit: 1K */
 861                 if (agg_size > 0xF)
 862                         agg_size = 0xF;
 863
 864                 aggctrl |= RXDMA_AGG_EN;
 865                 aggrx |= BIT_USB_RXDMA_AGG_EN;
 866                 aggrx |= agg_size;
 867                 aggrx |= (pHalData->UsbRxAggPageTimeout << 8);
 868                 DBG_8192C("%s: RX Agg-DMA mode, size=%dKB, timeout=%dus\n",
 869                         __func__, agg_size, pHalData->UsbRxAggPageTimeout*32);
 870                 break;
 871
 872         case USB_RX_AGG_USB:
 873         case USB_RX_AGG_MIX:
 874                 agg_size = pHalData->UsbRxAggBlockCount << 12;
 875                 if ((agg_size + 2048) > MAX_RECVBUF_SZ)
 876                         agg_size = MAX_RECVBUF_SZ - 2048;
 877                 agg_size >>= 12; /* unit: 4K */
 878                 if (agg_size > 0xF)
 879                         agg_size = 0xF;
 880
 881                 aggctrl |= RXDMA_AGG_EN;
 882                 aggrx &= ~BIT_USB_RXDMA_AGG_EN;
 883                 aggrx |= agg_size;
 884                 aggrx |= (pHalData->UsbRxAggBlockTimeout << 8);
 885                 DBG_8192C("%s: RX Agg-USB mode, size=%dKB, timeout=%dus\n",
 886                         __func__, agg_size*4, pHalData->UsbRxAggBlockTimeout*32);
 887                 break;
 888
 889         case USB_RX_AGG_DISABLE:
 890         default:
 891                 DBG_8192C("%s: RX Aggregation Disable!\n", __FUNCTION__);
 892                 break;
 893         }
 894 #endif // CONFIG_USB_RX_AGGREGATION
 895
 896         rtw_write8(padapter, REG_TRXDMA_CTRL, aggctrl);
 897         rtw_write32(padapter, REG_RXDMA_AGG_PG_TH, aggrx);
 898 }
 899
 900 static VOID
 901 _initUsbAggregationSetting(
 902         IN  PADAPTER Adapter
 903         )
 904 {
 905         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(Adapter);
 906
 907         // Tx aggregation setting
 908         usb_AggSettingTxUpdate(Adapter);
 909
 910         // Rx aggregation setting
 911         usb_AggSettingRxUpdate(Adapter);
 912
 913         // 201/12/10 MH Add for USB agg mode dynamic switch.
 914         pHalData->UsbRxHighSpeedMode = _FALSE;
 915 }
 916
 917 static VOID
 918 PHY_InitAntennaSelection8723B(
 919         PADAPTER Adapter
 920         )
 921 {
 922         // TODO: <20130114, Kordan> The following setting is only for DPDT and Fixed board type.
 923         // TODO:  A better solution is configure it according EFUSE during the run-time.
 924         PHY_SetMacReg(Adapter, 0x64, BIT20, 0x0);                  //0x66[4]=0
 925         PHY_SetMacReg(Adapter, 0x64, BIT24, 0x0);                  //0x66[8]=0
 926         PHY_SetMacReg(Adapter, 0x40, BIT4, 0x0);                   //0x40[4]=0
 927         PHY_SetMacReg(Adapter, 0x40, BIT3, 0x1);                   //0x40[3]=1
 928         PHY_SetMacReg(Adapter, 0x4C, BIT24, 0x1);          //0x4C[24:23]=10
 929         PHY_SetMacReg(Adapter, 0x4C, BIT23, 0x0);          //0x4C[24:23]=10
 930         PHY_SetBBReg(Adapter, 0x944, BIT1|BIT0, 0x3);     //0x944[1:0]=11
 931         PHY_SetBBReg(Adapter, 0x930, bMaskByte0, 0x77);   //0x930[7:0]=77
 932         PHY_SetMacReg(Adapter, 0x38, BIT11, 0x1);              //0x38[11]=1
 933 }
 934
 935 static VOID _InitAdhocWorkaroundParams(IN PADAPTER Adapter)
 936 {
 937 #ifdef CONFIG_ADHOC_WORKAROUND_SETTING
 938         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(Adapter);
 939         pHalData->RegBcnCtrlVal = rtw_read8(Adapter, REG_BCN_CTRL);
 940         pHalData->RegTxPause = rtw_read8(Adapter, REG_TXPAUSE);
 941         pHalData->RegFwHwTxQCtrl = rtw_read8(Adapter, REG_FWHW_TXQ_CTRL+2);
 942         pHalData->RegReg542 = rtw_read8(Adapter, REG_TBTT_PROHIBIT+2);
 943 #endif
 944 }
 945
 946 // Set CCK and OFDM Block "ON"
 947 static VOID _BBTurnOnBlock(
 948         IN      PADAPTER                Adapter
 949         )
 950 {
 951 #if (DISABLE_BB_RF)
 952         return;
 953 #endif
 954
 955         PHY_SetBBReg(Adapter, rFPGA0_RFMOD, bCCKEn, 0x1);
 956         PHY_SetBBReg(Adapter, rFPGA0_RFMOD, bOFDMEn, 0x1);
 957 }
 958
 959 #define MgntActSet_RF_State(...)
 960
 961 enum {
 962         Antenna_Lfet = 1,
 963         Antenna_Right = 2,
 964 };
 965
 966 //
 967 // 2010/08/09 MH Add for power down check.
 968 //
 969 static BOOLEAN
 970 HalDetectPwrDownMode(
 971         IN PADAPTER                             Adapter
 972         )
 973 {
 974         u8      tmpvalue;
 975         HAL_DATA_TYPE           *pHalData       = GET_HAL_DATA(Adapter);
 976         struct pwrctrl_priv             *pwrctrlpriv = adapter_to_pwrctl(Adapter);
 977
 978         EFUSE_ShadowRead(Adapter, 1, EEPROM_FEATURE_OPTION_8723B, (u32 *)&tmpvalue);
 979
 980         // 2010/08/25 MH INF priority > PDN Efuse value.
 981         if(tmpvalue & BIT4 && pwrctrlpriv->reg_pdnmode)
 982         {
 983                 pHalData->pwrdown = _TRUE;
 984         }
 985         else
 986         {
 987                 pHalData->pwrdown = _FALSE;
 988         }
 989
 990         DBG_8192C("HalDetectPwrDownMode(): PDN=%d\n", pHalData->pwrdown);
 991         return pHalData->pwrdown;
 992
 993 }       // HalDetectPwrDownMode
 994
 995
 996 //
 997 // 2010/08/26 MH Add for selective suspend mode check.
 998 // If Efuse 0x0e bit1 is not enabled, we can not support selective suspend for Minicard and
 999 // slim card.
1000 //
1001 static VOID
1002 HalDetectSelectiveSuspendMode(
1003         IN PADAPTER                             Adapter
1004         )
1005 {
1006 #if 0   //amyma
1007         u8      tmpvalue;
1008         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(Adapter);
1009         struct dvobj_priv       *pdvobjpriv = adapter_to_dvobj(Adapter);
1010
1011         // If support HW radio detect, we need to enable WOL ability, otherwise, we
1012         // can not use FW to notify host the power state switch.
1013
1014         EFUSE_ShadowRead(Adapter, 1, EEPROM_USB_OPTIONAL1, (u32 *)&tmpvalue);
1015
1016         DBG_8192C("HalDetectSelectiveSuspendMode(): SS ");
1017         if(tmpvalue & BIT1)
1018         {
1019                 DBG_8192C("Enable\n");
1020         }
1021         else
1022         {
1023                 DBG_8192C("Disable\n");
1024                 pdvobjpriv->RegUsbSS = _FALSE;
1025         }
1026
1027         // 2010/09/01 MH According to Dongle Selective Suspend INF. We can switch SS mode.
1028         if (pdvobjpriv->RegUsbSS && !SUPPORT_HW_RADIO_DETECT(pHalData))
1029         {
1030                 //PMGNT_INFO                            pMgntInfo = &(Adapter->MgntInfo);
1031
1032                 //if (!pMgntInfo->bRegDongleSS)
1033                 //{
1034                 //      RT_TRACE(COMP_INIT, DBG_LOUD, ("Dongle disable SS\n"));
1035                         pdvobjpriv->RegUsbSS = _FALSE;
1036                 //}
1037         }
1038 #endif
1039 }       // HalDetectSelectiveSuspendMode
1040 /*-----------------------------------------------------------------------------
1041  * Function:    HwSuspendModeEnable92Cu()
1042  *
1043  * Overview:    HW suspend mode switch.
1044  *
1045  * Input:               NONE
1046  *
1047  * Output:      NONE
1048  *
1049  * Return:      NONE
1050  *
1051  * Revised History:
1052  *      When            Who             Remark
1053  *      08/23/2010      MHC             HW suspend mode switch test..
1054  *---------------------------------------------------------------------------*/
1055 static VOID
1056 HwSuspendModeEnable92Cu(
1057         IN      PADAPTER        pAdapter,
1058         IN      u8                      Type
1059         )
1060 {
1061         //PRT_USB_DEVICE                pDevice = GET_RT_USB_DEVICE(pAdapter);
1062         u16     reg = rtw_read16(pAdapter, REG_GPIO_MUXCFG);
1063
1064         //if (!pDevice->RegUsbSS)
1065         {
1066                 return;
1067         }
1068
1069         //
1070         // 2010/08/23 MH According to Alfred's suggestion, we need to to prevent HW
1071         // to enter suspend mode automatically. Otherwise, it will shut down major power
1072         // domain and 8051 will stop. When we try to enter selective suspend mode, we
1073         // need to prevent HW to enter D2 mode aumotmatically. Another way, Host will
1074         // issue a S10 signal to power domain. Then it will cleat SIC setting(from Yngli).
1075         // We need to enable HW suspend mode when enter S3/S4 or disable. We need
1076         // to disable HW suspend mode for IPS/radio_off.
1077         //
1078         //RT_TRACE(COMP_RF, DBG_LOUD, ("HwSuspendModeEnable92Cu = %d\n", Type));
1079         if (Type == _FALSE)
1080         {
1081                 reg |= BIT14;
1082                 //RT_TRACE(COMP_RF, DBG_LOUD, ("REG_GPIO_MUXCFG = %x\n", reg));
1083                 rtw_write16(pAdapter, REG_GPIO_MUXCFG, reg);
1084                 reg |= BIT12;
1085                 //RT_TRACE(COMP_RF, DBG_LOUD, ("REG_GPIO_MUXCFG = %x\n", reg));
1086                 rtw_write16(pAdapter, REG_GPIO_MUXCFG, reg);
1087         }
1088         else
1089         {
1090                 reg &= (~BIT12);
1091                 rtw_write16(pAdapter, REG_GPIO_MUXCFG, reg);
1092                 reg &= (~BIT14);
1093                 rtw_write16(pAdapter, REG_GPIO_MUXCFG, reg);
1094         }
1095
1096 }       // HwSuspendModeEnable92Cu
1097 rt_rf_power_state RfOnOffDetect(IN      PADAPTER pAdapter )
1098 {
1099         //HAL_DATA_TYPE         *pHalData = GET_HAL_DATA(pAdapter);
1100         u8      val8;
1101         rt_rf_power_state rfpowerstate = rf_off;
1102
1103         if(adapter_to_pwrctl(pAdapter)->bHWPowerdown)
1104         {
1105                 val8 = rtw_read8(pAdapter, REG_HSISR);
1106                 DBG_8192C("pwrdown, 0x5c(BIT7)=%02x\n", val8);
1107                 rfpowerstate = (val8 & BIT7) ? rf_off: rf_on;
1108         }
1109         else // rf on/off
1110         {
1111                 rtw_write8(     pAdapter, REG_MAC_PINMUX_CFG,rtw_read8(pAdapter, REG_MAC_PINMUX_CFG)&~(BIT3));
1112                 val8 = rtw_read8(pAdapter, REG_GPIO_IO_SEL);
1113                 DBG_8192C("GPIO_IN=%02x\n", val8);
1114                 rfpowerstate = (val8 & BIT3) ? rf_on : rf_off;
1115         }
1116         return rfpowerstate;
1117 }       // HalDetectPwrDownMode
1118
1119 void _ps_open_RF(_adapter *padapter);
1120
1121 u32 rtl8723bu_hal_init(PADAPTER padapter)
1122 {
1123         u8      value8 = 0, u1bRegCR;
1124         u32     boundary, status = _SUCCESS;
1125         HAL_DATA_TYPE           *pHalData = GET_HAL_DATA(padapter);
1126         struct pwrctrl_priv             *pwrctrlpriv = adapter_to_pwrctl(padapter);
1127         struct registry_priv    *pregistrypriv = &padapter->registrypriv;
1128         rt_rf_power_state               eRfPowerStateToSet;
1129         u32 NavUpper = WiFiNavUpperUs;
1130         u32 value32;
1131         u32 init_start_time = rtw_get_current_time();
1132
1133
1134 #ifdef DBG_HAL_INIT_PROFILING
1135
1136         enum HAL_INIT_STAGES {
1137                 HAL_INIT_STAGES_BEGIN = 0,
1138                 HAL_INIT_STAGES_INIT_PW_ON,
1139                 HAL_INIT_STAGES_INIT_LLTT,
1140                 HAL_INIT_STAGES_MISC01,
1141                 HAL_INIT_STAGES_DOWNLOAD_FW,
1142                 HAL_INIT_STAGES_MAC,
1143                 HAL_INIT_STAGES_BB,
1144                 HAL_INIT_STAGES_RF,
1145                 HAL_INIT_STAGES_MISC02,
1146                 HAL_INIT_STAGES_TURN_ON_BLOCK,
1147                 HAL_INIT_STAGES_INIT_SECURITY,
1148                 HAL_INIT_STAGES_MISC11,
1149                 //HAL_INIT_STAGES_RF_PS,
1150                 HAL_INIT_STAGES_INIT_HAL_DM,
1151 //              HAL_INIT_STAGES_IQK,
1152 //              HAL_INIT_STAGES_PW_TRACK,
1153 //              HAL_INIT_STAGES_LCK,
1154                 HAL_INIT_STAGES_MISC21,
1155                 //HAL_INIT_STAGES_INIT_PABIAS,
1156                 HAL_INIT_STAGES_BT_COEXIST,
1157                 //HAL_INIT_STAGES_ANTENNA_SEL,
1158                 HAL_INIT_STAGES_MISC31,
1159                 HAL_INIT_STAGES_END,
1160                 HAL_INIT_STAGES_NUM
1161         };
1162
1163         char * hal_init_stages_str[] = {
1164                 "HAL_INIT_STAGES_BEGIN",
1165                 "HAL_INIT_STAGES_INIT_PW_ON",
1166                 "HAL_INIT_STAGES_INIT_LLTT",
1167                 "HAL_INIT_STAGES_MISC01",
1168                 "HAL_INIT_STAGES_DOWNLOAD_FW",
1169                 "HAL_INIT_STAGES_MAC",
1170                 "HAL_INIT_STAGES_BB",
1171                 "HAL_INIT_STAGES_RF",
1172                 "HAL_INIT_STAGES_MISC02",
1173                 "HAL_INIT_STAGES_TURN_ON_BLOCK",
1174                 "HAL_INIT_STAGES_INIT_SECURITY",
1175                 "HAL_INIT_STAGES_MISC11",
1176                 //"HAL_INIT_STAGES_RF_PS",
1177                 "HAL_INIT_STAGES_INIT_HAL_DM",
1178 //              "HAL_INIT_STAGES_IQK",
1179 //              "HAL_INIT_STAGES_PW_TRACK",
1180 //              "HAL_INIT_STAGES_LCK",
1181                 "HAL_INIT_STAGES_MISC21",
1182                 //"HAL_INIT_STAGES_INIT_PABIAS",
1183                 "HAL_INIT_STAGES_BT_COEXIST",
1184                 //"HAL_INIT_STAGES_ANTENNA_SEL",
1185                 "HAL_INIT_STAGES_MISC31",
1186                 "HAL_INIT_STAGES_END",
1187         };
1188
1189         int hal_init_profiling_i;
1190         u32 hal_init_stages_timestamp[HAL_INIT_STAGES_NUM]; //used to record the time of each stage's starting point
1191
1192         for(hal_init_profiling_i=0;hal_init_profiling_i<HAL_INIT_STAGES_NUM;hal_init_profiling_i++)
1193                 hal_init_stages_timestamp[hal_init_profiling_i]=0;
1194
1195         #define HAL_INIT_PROFILE_TAG(stage) hal_init_stages_timestamp[(stage)]=rtw_get_current_time();
1196 #else
1197         #define HAL_INIT_PROFILE_TAG(stage) do {} while(0)
1198 #endif //DBG_HAL_INIT_PROFILING
1199
1200
1201
1202 _func_enter_;
1203
1204 HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_BEGIN);
1205
1206 //      if(Adapter->bSurpriseRemoved)
1207 //              return _FAIL;
1208
1209         // Check if MAC has already power on.
1210         value8 = rtw_read8(padapter, REG_SYS_CLKR_8723B+1);
1211         u1bRegCR = rtw_read8(padapter, REG_CR_8723B);
1212         DBG_871X(" power-on :REG_SYS_CLKR 0x09=0x%02x. REG_CR 0x100=0x%02x.\n", value8, u1bRegCR);
1213         if((value8&BIT3) && (u1bRegCR != 0 && u1bRegCR != 0xEA))
1214         {
1215                 DBG_871X(" MAC has already power on.\n");
1216         }
1217         else
1218         {
1219                 // Set FwPSState to ALL_ON mode to prevent from the I/O be return because of 32k
1220                 // state which is set before sleep under wowlan mode. 2012.01.04. by tynli.
1221                 //pHalData->FwPSState = FW_PS_STATE_ALL_ON_88E;
1222                 DBG_871X(" MAC has not been powered on yet.\n");
1223         }
1224
1225 #ifdef CONFIG_WOWLAN
1226         if(rtw_read8(padapter, REG_MCUFWDL)&BIT7 &&
1227                 (pwrctrlpriv->wowlan_wake_reason & FWDecisionDisconnect)) {
1228                 u8 reg_val=0;
1229                 DBG_871X("+Reset Entry+\n");
1230                 rtw_write8(padapter, REG_MCUFWDL, 0x00);
1231                 _8051Reset8723(padapter);
1232                 //reset BB
1233                 reg_val = rtw_read8(padapter, REG_SYS_FUNC_EN);
1234                 reg_val &= ~(BIT(0) | BIT(1));
1235                 rtw_write8(padapter, REG_SYS_FUNC_EN, reg_val);
1236                 //reset RF
1237                 rtw_write8(padapter, REG_RF_CTRL, 0);
1238                 //reset TRX path
1239                 rtw_write16(padapter, REG_CR, 0);
1240                 //reset MAC, Digital Core
1241                 reg_val = rtw_read8(padapter, REG_SYS_FUNC_EN+1);
1242                 reg_val &= ~(BIT(4) | BIT(7));
1243                 rtw_write8(padapter, REG_SYS_FUNC_EN+1, reg_val);
1244                 reg_val = rtw_read8(padapter, REG_SYS_FUNC_EN+1);
1245                 reg_val |= BIT(4) | BIT(7);
1246                 rtw_write8(padapter, REG_SYS_FUNC_EN+1, reg_val);
1247                 DBG_871X("-Reset Entry-\n");
1248         }
1249 #endif //CONFIG_WOWLAN
1250
1251 HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_INIT_PW_ON);
1252         status = _InitPowerOn_8723BU(padapter);
1253         if(status == _FAIL){
1254                 RT_TRACE(_module_hci_hal_init_c_, _drv_err_, ("Failed to init power on!\n"));
1255                 goto exit;
1256         }
1257
1258
1259 HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_INIT_LLTT);
1260         if (!pregistrypriv->wifi_spec) {
1261                 boundary = TX_PAGE_BOUNDARY_8723B;
1262         } else {
1263                 // for WMM
1264                 boundary = WMM_NORMAL_TX_PAGE_BOUNDARY_8723B;
1265         }
1266         status =  rtl8723b_InitLLTTable(padapter);
1267         if(status == _FAIL){
1268                 RT_TRACE(_module_hci_hal_init_c_, _drv_err_, ("Failed to init LLT table\n"));
1269                 goto exit;
1270         }
1271
1272 HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_MISC01);
1273         if(pHalData->bRDGEnable){
1274                 _InitRDGSetting_8723bu(padapter);
1275         }
1276
1277
1278         //Enable TX Report
1279         //Enable Tx Report Timer
1280         value8 = rtw_read8(padapter, REG_TX_RPT_CTRL);
1281         rtw_write8(padapter, REG_TX_RPT_CTRL, value8|BIT1);
1282         //Set MAX RPT MACID
1283         rtw_write8(padapter, REG_TX_RPT_CTRL+1, 2);
1284         //Tx RPT Timer. Unit: 32us
1285         rtw_write16(padapter, REG_TX_RPT_TIME, 0xCdf0);
1286
1287 #ifdef CONFIG_TX_EARLY_MODE
1288         if(pHalData->AMPDUBurstMode)
1289         {
1290                 RT_TRACE(_module_hci_hal_init_c_, _drv_err_, ("EarlyMode Enabled!!!\n"));
1291
1292                 value8 = rtw_read8(padapter, REG_EARLY_MODE_CONTROL_8723B);
1293 #if RTL8723B_EARLY_MODE_PKT_NUM_10 == 1
1294                 value8 = value8|0x1f;
1295 #else
1296                 value8 = value8|0xf;
1297 #endif
1298                 rtw_write8(padapter, REG_EARLY_MODE_CONTROL_8723B, value8);
1299
1300                 rtw_write8(padapter, REG_EARLY_MODE_CONTROL_8723B+3, 0x80);
1301
1302                 value8 = rtw_read8(padapter, REG_TCR_8723B+1);
1303                 value8 = value8|0x40;
1304                 rtw_write8(padapter,REG_TCR_8723B+1, value8);
1305         }
1306         else
1307                 rtw_write8(padapter,REG_EARLY_MODE_CONTROL_8723B, 0);
1308 #endif
1309
1310         // <Kordan> InitHalDm should be put ahead of FirmwareDownload. (HWConfig flow: FW->MAC->-BB->RF)
1311         //InitHalDm(Adapter);
1312
1313 HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_DOWNLOAD_FW);
1314 #if (1 == MP_DRIVER)
1315         if (padapter->registrypriv.mp_mode == 1)
1316         {
1317                 _InitRxSetting_8723bu(padapter);
1318         }
1319 //      else
1320 #endif
1321         {
1322                 status = rtl8723b_FirmwareDownload(padapter,_FALSE);
1323                 if(status != _SUCCESS)
1324                 {
1325                         padapter->bFWReady = _FALSE;
1326                         pHalData->fw_ractrl = _FALSE;
1327                         DBG_871X("fw download fail!\n");
1328                         goto exit;
1329                 }
1330                 else
1331                 {
1332                         padapter->bFWReady = _TRUE;
1333                         pHalData->fw_ractrl = _TRUE;
1334                         DBG_871X("fw download ok!\n");
1335                 }
1336         }
1337
1338         rtl8723b_InitializeFirmwareVars(padapter);
1339
1340         if(pwrctrlpriv->reg_rfoff == _TRUE){
1341                 pwrctrlpriv->rf_pwrstate = rf_off;
1342         }
1343
1344         // Set RF type for BB/RF configuration
1345         //_InitRFType(Adapter);
1346
1347         // We should call the function before MAC/BB configuration.
1348         PHY_InitAntennaSelection8723B(padapter);
1349
1350
1351
1352 HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_MAC);
1353 #if (HAL_MAC_ENABLE == 1)
1354         status = PHY_MACConfig8723B(padapter);
1355         if(status == _FAIL)
1356         {
1357                 DBG_871X("PHY_MACConfig8723B fault !!\n");
1358                 goto exit;
1359         }
1360 #endif
1361
1362
1363 HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_BB);
1364         //
1365         //d. Initialize BB related configurations.
1366         //
1367 #if (HAL_BB_ENABLE == 1)
1368         status = PHY_BBConfig8723B(padapter);
1369         if(status == _FAIL)
1370         {
1371                 DBG_871X("PHY_BBConfig8723B fault !!\n");
1372                 goto exit;
1373         }
1374 #endif
1375
1376
1377
1378
1379 HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_RF);
1380 #if (HAL_RF_ENABLE == 1)
1381         status = PHY_RFConfig8723B(padapter);
1382
1383         if(status == _FAIL)
1384         {
1385                 DBG_871X("PHY_RFConfig8723B fault !!\n");
1386                 goto exit;
1387         }
1388
1389
1390
1391 #endif
1392
1393
1394
1395 HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_MISC02);
1396         _InitQueueReservedPage(padapter);
1397         _InitTxBufferBoundary(padapter);
1398         _InitQueuePriority(padapter);
1399         _InitPageBoundary(padapter);
1400         _InitTransferPageSize_8723bu(padapter);
1401
1402
1403         // Get Rx PHY status in order to report RSSI and others.
1404         _InitDriverInfoSize(padapter, DRVINFO_SZ);
1405
1406         _InitInterrupt(padapter);
1407         hal_init_macaddr(padapter);//set mac_address
1408         _InitNetworkType(padapter);//set msr
1409         _InitWMACSetting(padapter);
1410         _InitAdaptiveCtrl(padapter);
1411         _InitEDCA(padapter);
1412         _InitRateFallback(padapter);
1413         _InitRetryFunction(padapter);
1414 //      _InitOperationMode(Adapter);//todo
1415         rtl8723b_InitBeaconParameters(padapter);
1416         rtl8723b_InitBeaconMaxError(padapter, _TRUE);
1417
1418         _InitBurstPktLen(padapter);
1419         _initUsbAggregationSetting(padapter);
1420
1421 #ifdef ENABLE_USB_DROP_INCORRECT_OUT
1422         _InitHardwareDropIncorrectBulkOut(padapter);
1423 #endif
1424
1425 #if defined(CONFIG_CONCURRENT_MODE) || defined(CONFIG_TX_MCAST2UNI)
1426
1427 #ifdef CONFIG_CHECK_AC_LIFETIME
1428         // Enable lifetime check for the four ACs
1429         rtw_write8(padapter, REG_LIFETIME_CTRL, 0x0F);
1430 #endif  // CONFIG_CHECK_AC_LIFETIME
1431
1432 #ifdef CONFIG_TX_MCAST2UNI
1433         rtw_write16(padapter, REG_PKT_VO_VI_LIFE_TIME, 0x0400); // unit: 256us. 256ms
1434         rtw_write16(padapter, REG_PKT_BE_BK_LIFE_TIME, 0x0400); // unit: 256us. 256ms
1435 #else   // CONFIG_TX_MCAST2UNI
1436         rtw_write16(padapter, REG_PKT_VO_VI_LIFE_TIME, 0x3000); // unit: 256us. 3s
1437         rtw_write16(padapter, REG_PKT_BE_BK_LIFE_TIME, 0x3000); // unit: 256us. 3s
1438 #endif  // CONFIG_TX_MCAST2UNI
1439 #endif  // CONFIG_CONCURRENT_MODE || CONFIG_TX_MCAST2UNI
1440
1441
1442 #ifdef CONFIG_LED
1443         _InitHWLed(padapter);
1444 #endif //CONFIG_LED
1445
1446 HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_TURN_ON_BLOCK);
1447         _BBTurnOnBlock(padapter);
1448         //NicIFSetMacAddress(padapter, padapter->PermanentAddress);
1449
1450
1451         rtw_hal_set_chnl_bw(padapter, padapter->registrypriv.channel,
1452                 CHANNEL_WIDTH_20, HAL_PRIME_CHNL_OFFSET_DONT_CARE, HAL_PRIME_CHNL_OFFSET_DONT_CARE);
1453
1454 HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_INIT_SECURITY);
1455         invalidate_cam_all(padapter);
1456
1457 HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_MISC11);
1458         // 2010/12/17 MH We need to set TX power according to EFUSE content at first.
1459         //PHY_SetTxPowerLevel8723B(padapter, pHalData->CurrentChannel);
1460         rtl8723b_InitAntenna_Selection(padapter);
1461
1462         // HW SEQ CTRL
1463         //set 0x0 to 0xFF by tynli. Default enable HW SEQ NUM.
1464         rtw_write8(padapter,REG_HWSEQ_CTRL, 0xFF);
1465
1466         //
1467         // Disable BAR, suggested by Scott
1468         // 2010.04.09 add by hpfan
1469         //
1470         rtw_write32(padapter, REG_BAR_MODE_CTRL, 0x0201ffff);
1471
1472         if(pregistrypriv->wifi_spec)
1473                 rtw_write16(padapter,REG_FAST_EDCA_CTRL ,0);
1474
1475         // Move by Neo for USB SS from above setp
1476
1477 //      _RfPowerSave(Adapter);
1478
1479 HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_INIT_HAL_DM);
1480         rtl8723b_InitHalDm(padapter);
1481
1482 #if (MP_DRIVER == 1)
1483         if (padapter->registrypriv.mp_mode == 1)
1484         {
1485         padapter->mppriv.channel = pHalData->CurrentChannel;
1486         MPT_InitializeAdapter(padapter, padapter->mppriv.channel);
1487         }
1488         else
1489 #endif
1490         {
1491                 pwrctrlpriv->rf_pwrstate = rf_on;
1492
1493                 if (pwrctrlpriv->rf_pwrstate == rf_on)
1494                 {
1495                         struct pwrctrl_priv *pwrpriv;
1496                         u32 start_time;
1497                         u8 restore_iqk_rst;
1498                         u8 b2Ant;
1499                         u8 h2cCmdBuf;
1500
1501                         pwrpriv = adapter_to_pwrctl(padapter);
1502
1503                         PHY_LCCalibrate_8723B(&pHalData->odmpriv);
1504
1505                         /* Inform WiFi FW that it is the beginning of IQK */
1506                         h2cCmdBuf = 1;
1507                         FillH2CCmd8723B(padapter, H2C_8723B_BT_WLAN_CALIBRATION, 1, &h2cCmdBuf);
1508
1509                         start_time = rtw_get_current_time();
1510                         do {
1511                                 if (rtw_read8(padapter, 0x1e7) & 0x01)
1512                                         break;
1513
1514                                 rtw_msleep_os(50);
1515                         } while (rtw_get_passing_time_ms(start_time) <= 400);
1516
1517 #ifdef CONFIG_BT_COEXIST
1518                         rtw_btcoex_IQKNotify(padapter, _TRUE);
1519 #endif
1520                         restore_iqk_rst = (pwrpriv->bips_processing==_TRUE)?_TRUE:_FALSE;
1521                         b2Ant = pHalData->EEPROMBluetoothAntNum==Ant_x2?_TRUE:_FALSE;
1522                         PHY_IQCalibrate_8723B(padapter, _FALSE, restore_iqk_rst, b2Ant, pHalData->ant_path);
1523                         pHalData->bIQKInitialized = _TRUE;
1524 #ifdef CONFIG_BT_COEXIST
1525                         rtw_btcoex_IQKNotify(padapter, _FALSE);
1526 #endif
1527
1528                         /* Inform WiFi FW that it is the finish of IQK */
1529                         h2cCmdBuf = 0;
1530                         FillH2CCmd8723B(padapter, H2C_8723B_BT_WLAN_CALIBRATION, 1, &h2cCmdBuf);
1531
1532                         ODM_TXPowerTrackingCheck(&pHalData->odmpriv);
1533                 }
1534         }
1535
1536
1537 HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_MISC21);
1538
1539 //HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_INIT_PABIAS);
1540 //      _InitPABias(Adapter);
1541
1542 HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_BT_COEXIST);
1543 #ifdef CONFIG_BT_COEXIST
1544         // Init BT hw config.
1545         rtw_btcoex_HAL_Initialize(padapter, _FALSE);
1546 #else
1547         rtw_btcoex_HAL_Initialize(padapter, _TRUE);
1548 #endif
1549
1550 #if 0
1551         // 2010/05/20 MH We need to init timer after update setting. Otherwise, we can not get correct inf setting.
1552         // 2010/05/18 MH For SE series only now. Init GPIO detect time
1553         if(pDevice->RegUsbSS)
1554         {
1555                 RT_TRACE(COMP_INIT, DBG_LOUD, (" call GpioDetectTimerStart8192CU\n"));
1556                 GpioDetectTimerStart8192CU(Adapter);    // Disable temporarily
1557         }
1558
1559         // 2010/08/23 MH According to Alfred's suggestion, we need to to prevent HW enter
1560         // suspend mode automatically.
1561         HwSuspendModeEnable92Cu(Adapter, _FALSE);
1562 #endif
1563
1564 HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_MISC31);
1565         rtw_hal_set_hwreg(padapter, HW_VAR_NAV_UPPER, (u8*)&NavUpper);
1566
1567 #ifdef CONFIG_XMIT_ACK
1568         //ack for xmit mgmt frames.
1569         rtw_write32(padapter, REG_FWHW_TXQ_CTRL, rtw_read32(padapter, REG_FWHW_TXQ_CTRL)|BIT(12));
1570 #endif //CONFIG_XMIT_ACK
1571
1572         // Enable MACTXEN/MACRXEN block
1573         u1bRegCR = rtw_read8(padapter, REG_CR);
1574         u1bRegCR |= (MACTXEN | MACRXEN);
1575         rtw_write8(padapter, REG_CR, u1bRegCR);
1576
1577         //_dbg_dump_macreg(Adapter);
1578
1579 exit:
1580 HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_END);
1581
1582         DBG_871X("%s in %dms\n", __FUNCTION__, rtw_get_passing_time_ms(init_start_time));
1583
1584         #ifdef DBG_HAL_INIT_PROFILING
1585         hal_init_stages_timestamp[HAL_INIT_STAGES_END]=rtw_get_current_time();
1586
1587         for(hal_init_profiling_i=0;hal_init_profiling_i<HAL_INIT_STAGES_NUM-1;hal_init_profiling_i++) {
1588                 DBG_871X("DBG_HAL_INIT_PROFILING: %35s, %u, %5u, %5u\n"
1589                         , hal_init_stages_str[hal_init_profiling_i]
1590                         , hal_init_stages_timestamp[hal_init_profiling_i]
1591                         , (hal_init_stages_timestamp[hal_init_profiling_i+1]-hal_init_stages_timestamp[hal_init_profiling_i])
1592                         , rtw_get_time_interval_ms(hal_init_stages_timestamp[hal_init_profiling_i], hal_init_stages_timestamp[hal_init_profiling_i+1])
1593                 );
1594         }
1595         #endif
1596
1597 _func_exit_;
1598
1599         return status;
1600 }
1601
1602
1603 static VOID
1604 _DisableGPIO(
1605         IN      PADAPTER        Adapter
1606         )
1607 {
1608 /***************************************
1609 j. GPIO_PIN_CTRL 0x44[31:0]=0x000               //
1610 k. Value = GPIO_PIN_CTRL[7:0]
1611 l.  GPIO_PIN_CTRL 0x44[31:0] = 0x00FF0000 | (value <<8); //write external PIN level
1612 m. GPIO_MUXCFG 0x42 [15:0] = 0x0780
1613 n. LEDCFG 0x4C[15:0] = 0x8080
1614 ***************************************/
1615         u8      value8;
1616         u16     value16;
1617         u32     value32;
1618
1619         //1. Disable GPIO[7:0]
1620         rtw_write16(Adapter, REG_GPIO_PIN_CTRL+2, 0x0000);
1621         value32 = rtw_read32(Adapter, REG_GPIO_PIN_CTRL) & 0xFFFF00FF;
1622         value8 = (u8) (value32&0x000000FF);
1623         value32 |= ((value8<<8) | 0x00FF0000);
1624         rtw_write32(Adapter, REG_GPIO_PIN_CTRL, value32);
1625
1626         //2. Disable GPIO[10:8]
1627         rtw_write8(Adapter, REG_GPIO_MUXCFG+3, 0x00);
1628             value16 = rtw_read16(Adapter, REG_GPIO_MUXCFG+2) & 0xFF0F;
1629         value8 = (u8) (value16&0x000F);
1630         value16 |= ((value8<<4) | 0x0780);
1631         rtw_write16(Adapter, REG_GPIO_MUXCFG+2, value16);
1632
1633         //3. Disable LED0 & 1
1634         rtw_write16(Adapter, REG_LEDCFG0, 0x8080);
1635
1636         //RT_TRACE(COMP_INIT, DBG_LOUD, ("======> Disable GPIO and LED.\n"));
1637
1638 } //end of _DisableGPIO()
1639
1640 static VOID
1641 _ResetFWDownloadRegister(
1642         IN PADAPTER                     Adapter
1643         )
1644 {
1645         u32     value32;
1646
1647         value32 = rtw_read32(Adapter, REG_MCUFWDL);
1648         value32 &= ~(MCUFWDL_EN | MCUFWDL_RDY);
1649         rtw_write32(Adapter, REG_MCUFWDL, value32);
1650         //RT_TRACE(COMP_INIT, DBG_LOUD, ("Reset FW download register.\n"));
1651 }
1652
1653 static VOID
1654 _ResetBB(
1655         IN PADAPTER                     Adapter
1656         )
1657 {
1658         u16     value16;
1659
1660         //reset BB
1661         value16 = rtw_read16(Adapter, REG_SYS_FUNC_EN);
1662         value16 &= ~(FEN_BBRSTB | FEN_BB_GLB_RSTn);
1663         rtw_write16(Adapter, REG_SYS_FUNC_EN, value16);
1664         //RT_TRACE(COMP_INIT, DBG_LOUD, ("Reset BB.\n"));
1665 }
1666
1667 static VOID
1668 _ResetMCU(
1669         IN PADAPTER                     Adapter
1670         )
1671 {
1672         u16     value16;
1673
1674         // reset MCU
1675         value16 = rtw_read16(Adapter, REG_SYS_FUNC_EN);
1676         value16 &= ~FEN_CPUEN;
1677         rtw_write16(Adapter, REG_SYS_FUNC_EN, value16);
1678         //RT_TRACE(COMP_INIT, DBG_LOUD, ("Reset MCU.\n"));
1679 }
1680
1681 static VOID
1682 _DisableMAC_AFE_PLL(
1683         IN PADAPTER                     Adapter
1684         )
1685 {
1686         u32     value32;
1687
1688         //disable MAC/ AFE PLL
1689         value32 = rtw_read32(Adapter, REG_APS_FSMCO);
1690         value32 |= APDM_MAC;
1691         rtw_write32(Adapter, REG_APS_FSMCO, value32);
1692
1693         value32 |= APFM_OFF;
1694         rtw_write32(Adapter, REG_APS_FSMCO, value32);
1695         //RT_TRACE(COMP_INIT, DBG_LOUD, ("Disable MAC, AFE PLL.\n"));
1696 }
1697
1698 static VOID
1699 _AutoPowerDownToHostOff(
1700         IN      PADAPTER                Adapter
1701         )
1702 {
1703         u32                     value32;
1704         rtw_write8(Adapter, REG_SPS0_CTRL, 0x22);
1705
1706         value32 = rtw_read32(Adapter, REG_APS_FSMCO);
1707
1708         value32 |= APDM_HOST;//card disable
1709         rtw_write32(Adapter, REG_APS_FSMCO, value32);
1710         //RT_TRACE(COMP_INIT, DBG_LOUD, ("Auto Power Down to Host-off state.\n"));
1711
1712         // set USB suspend
1713         value32 = rtw_read32(Adapter, REG_APS_FSMCO);
1714         value32 &= ~AFSM_PCIE;
1715         rtw_write32(Adapter, REG_APS_FSMCO, value32);
1716
1717 }
1718
1719 static VOID
1720 _SetUsbSuspend(
1721         IN PADAPTER                     Adapter
1722         )
1723 {
1724         u32                     value32;
1725
1726         value32 = rtw_read32(Adapter, REG_APS_FSMCO);
1727
1728         // set USB suspend
1729         value32 |= AFSM_HSUS;
1730         rtw_write32(Adapter, REG_APS_FSMCO, value32);
1731
1732         //RT_ASSERT(0 == (rtw_read32(Adapter, REG_APS_FSMCO) & BIT(12)),(""));
1733         //RT_TRACE(COMP_INIT, DBG_LOUD, ("Set USB suspend.\n"));
1734
1735 }
1736
1737 static VOID
1738 _DisableRFAFEAndResetBB(
1739         IN PADAPTER                     Adapter
1740         )
1741 {
1742 /**************************************
1743 a.      TXPAUSE 0x522[7:0] = 0xFF             //Pause MAC TX queue
1744 b.      RF path 0 offset 0x00 = 0x00            // disable RF
1745 c.      APSD_CTRL 0x600[7:0] = 0x40
1746 d.      SYS_FUNC_EN 0x02[7:0] = 0x16            //reset BB state machine
1747 e.      SYS_FUNC_EN 0x02[7:0] = 0x14            //reset BB state machine
1748 ***************************************/
1749         u8 eRFPath = 0,value8 = 0;
1750         rtw_write8(Adapter, REG_TXPAUSE, 0xFF);
1751         PHY_SetRFReg(Adapter, eRFPath, 0x0, bMaskByte0, 0x0);
1752
1753         value8 |= APSDOFF;
1754         rtw_write8(Adapter, REG_APSD_CTRL, value8);//0x40
1755
1756         value8 = 0 ;
1757         value8 |=( FEN_USBD | FEN_USBA | FEN_BB_GLB_RSTn);
1758         rtw_write8(Adapter, REG_SYS_FUNC_EN,value8 );//0x16
1759
1760         value8 &=( ~FEN_BB_GLB_RSTn );
1761         rtw_write8(Adapter, REG_SYS_FUNC_EN, value8); //0x14
1762
1763         //RT_TRACE(COMP_INIT, DBG_LOUD, ("======> RF off and reset BB.\n"));
1764 }
1765
1766 static VOID
1767 _ResetDigitalProcedure1(
1768         IN      PADAPTER                        Adapter,
1769         IN      BOOLEAN                         bWithoutHWSM
1770         )
1771 {
1772
1773         HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
1774
1775         if(pHalData->FirmwareVersion <=  0x20){
1776                 #if 0
1777                 /*****************************
1778                 f.      SYS_FUNC_EN 0x03[7:0]=0x54              // reset MAC register, DCORE
1779                 g.      MCUFWDL 0x80[7:0]=0                             // reset MCU ready status
1780                 ******************************/
1781                 u4Byte  value32 = 0;
1782                 PlatformIOWrite1Byte(Adapter, REG_SYS_FUNC_EN+1, 0x54);
1783                 PlatformIOWrite1Byte(Adapter, REG_MCUFWDL, 0);
1784                 #else
1785                 /*****************************
1786                 f.      MCUFWDL 0x80[7:0]=0                             // reset MCU ready status
1787                 g.      SYS_FUNC_EN 0x02[10]= 0                 // reset MCU register, (8051 reset)
1788                 h.      SYS_FUNC_EN 0x02[15-12]= 5              // reset MAC register, DCORE
1789                 i.     SYS_FUNC_EN 0x02[10]= 1                  // enable MCU register, (8051 enable)
1790                 ******************************/
1791                         u16 valu16 = 0;
1792                         rtw_write8(Adapter, REG_MCUFWDL, 0);
1793
1794                         valu16 = rtw_read16(Adapter, REG_SYS_FUNC_EN);
1795                         rtw_write16(Adapter, REG_SYS_FUNC_EN, (valu16 & (~FEN_CPUEN)));//reset MCU ,8051
1796
1797                         valu16 = rtw_read16(Adapter, REG_SYS_FUNC_EN)&0x0FFF;
1798                         rtw_write16(Adapter, REG_SYS_FUNC_EN, (valu16 |(FEN_HWPDN|FEN_ELDR)));//reset MAC
1799
1800                         #ifdef DBG_SHOW_MCUFWDL_BEFORE_51_ENABLE
1801                         {
1802                                 u8 val;
1803                                 if( (val=rtw_read8(Adapter, REG_MCUFWDL)))
1804                                         DBG_871X("DBG_SHOW_MCUFWDL_BEFORE_51_ENABLE %s:%d REG_MCUFWDL:0x%02x\n", __FUNCTION__, __LINE__, val);
1805                         }
1806                         #endif
1807
1808
1809                         valu16 = rtw_read16(Adapter, REG_SYS_FUNC_EN);
1810                         rtw_write16(Adapter, REG_SYS_FUNC_EN, (valu16 | FEN_CPUEN));//enable MCU ,8051
1811
1812
1813                 #endif
1814         }
1815         else{
1816                 u8 retry_cnts = 0;
1817
1818                 if(rtw_read8(Adapter, REG_MCUFWDL) & BIT1)
1819                 { //IF fw in RAM code, do reset
1820
1821                         rtw_write8(Adapter, REG_MCUFWDL, 0);
1822                         if(Adapter->bFWReady){
1823                                 // 2010/08/25 MH Accordign to RD alfred's suggestion, we need to disable other
1824                                 // HRCV INT to influence 8051 reset.
1825                                 rtw_write8(Adapter, REG_FWIMR, 0x20);
1826
1827                                 rtw_write8(Adapter, REG_HMETFR+3, 0x20);//8051 reset by self
1828
1829                                 while( (retry_cnts++ <100) && (FEN_CPUEN &rtw_read16(Adapter, REG_SYS_FUNC_EN)))
1830                                 {
1831                                         rtw_udelay_os(50);//PlatformStallExecution(50);//us
1832                                 }
1833
1834                                 if(retry_cnts >= 100){
1835                                         DBG_8192C("%s #####=> 8051 reset failed!.........................\n", __FUNCTION__);
1836                                         // if 8051 reset fail we trigger GPIO 0 for LA
1837                                         //PlatformEFIOWrite4Byte(       Adapter,
1838                                         //                                              REG_GPIO_PIN_CTRL,
1839                                         //                                              0x00010100);
1840                                         // 2010/08/31 MH According to Filen's info, if 8051 reset fail, reset MAC directly.
1841                                         rtw_write8(Adapter, REG_SYS_FUNC_EN+1, 0x50);   //Reset MAC and Enable 8051
1842                                         rtw_mdelay_os(10);
1843                                 }
1844                                 else {
1845                                         //DBG_871X("%s =====> 8051 reset success (%d) .\n", __FUNCTION__, retry_cnts);
1846                                 }
1847                         }
1848                         else {
1849                                 DBG_871X("%s =====> 8051 in RAM but !Adapter->bFWReady\n", __FUNCTION__);
1850                         }
1851                 }
1852                 else{
1853                         //DBG_871X("%s =====> 8051 in ROM.\n", __FUNCTION__);
1854                 }
1855
1856                 #ifdef DBG_SHOW_MCUFWDL_BEFORE_51_ENABLE
1857                 {
1858                         u8 val;
1859                         if( (val=rtw_read8(Adapter, REG_MCUFWDL)))
1860                                 DBG_871X("DBG_SHOW_MCUFWDL_BEFORE_51_ENABLE %s:%d REG_MCUFWDL:0x%02x\n", __FUNCTION__, __LINE__, val);
1861                 }
1862                 #endif
1863
1864                 rtw_write8(Adapter, REG_SYS_FUNC_EN+1, 0x54);   //Reset MAC and Enable 8051
1865         }
1866
1867         // Clear rpwm value for initial toggle bit trigger.
1868         rtw_write8(Adapter, REG_USB_HRPWM, 0x00);
1869
1870         if(bWithoutHWSM){
1871         /*****************************
1872                 Without HW auto state machine
1873         g.      SYS_CLKR 0x08[15:0] = 0x30A3                    //disable MAC clock
1874         h.      AFE_PLL_CTRL 0x28[7:0] = 0x80                   //disable AFE PLL
1875         i.      AFE_XTAL_CTRL 0x24[15:0] = 0x880F               //gated AFE DIG_CLOCK
1876         j.      SYS_ISO_CTRL 0x00[7:0] = 0xF9                   // isolated digital to PON
1877         ******************************/
1878                 //rtw_write16(Adapter, REG_SYS_CLKR, 0x30A3);
1879                 rtw_write16(Adapter, REG_SYS_CLKR, 0x70A3);//modify to 0x70A3 by Scott.
1880                 rtw_write8(Adapter, REG_AFE_PLL_CTRL, 0x80);
1881                 rtw_write16(Adapter, REG_AFE_XTAL_CTRL, 0x880F);
1882                 rtw_write8(Adapter, REG_SYS_ISO_CTRL, 0xF9);
1883         }
1884         else
1885         {
1886                 // Disable all RF/BB power
1887                 rtw_write8(Adapter, REG_RF_CTRL, 0x00);
1888         }
1889         //RT_TRACE(COMP_INIT, DBG_LOUD, ("======> Reset Digital.\n"));
1890
1891 }
1892
1893 static VOID
1894 _ResetDigitalProcedure2(
1895         IN      PADAPTER                        Adapter
1896 )
1897 {
1898 /*****************************
1899 k.      SYS_FUNC_EN 0x03[7:0] = 0x44                    // disable ELDR runction
1900 l.      SYS_CLKR 0x08[15:0] = 0x3083                    // disable ELDR clock
1901 m.      SYS_ISO_CTRL 0x01[7:0] = 0x83                   // isolated ELDR to PON
1902 ******************************/
1903         //rtw_write8(Adapter, REG_SYS_FUNC_EN+1, 0x44);//marked by Scott.
1904         //rtw_write16(Adapter, REG_SYS_CLKR, 0x3083);
1905         //rtw_write8(Adapter, REG_SYS_ISO_CTRL+1, 0x83);
1906
1907         rtw_write16(Adapter, REG_SYS_CLKR, 0x70a3); //modify to 0x70a3 by Scott.
1908         rtw_write8(Adapter, REG_SYS_ISO_CTRL+1, 0x82); //modify to 0x82 by Scott.
1909 }
1910
1911 static VOID
1912 _DisableAnalog(
1913         IN PADAPTER                     Adapter,
1914         IN BOOLEAN                      bWithoutHWSM
1915         )
1916 {
1917         u16 value16 = 0;
1918         u8 value8=0;
1919         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(Adapter);
1920
1921         if(bWithoutHWSM){
1922         /*****************************
1923         n.      LDOA15_CTRL 0x20[7:0] = 0x04            // disable A15 power
1924         o.      LDOV12D_CTRL 0x21[7:0] = 0x54           // disable digital core power
1925         r.      When driver call disable, the ASIC will turn off remaining clock automatically
1926         ******************************/
1927
1928                 rtw_write8(Adapter, REG_LDOA15_CTRL, 0x04);
1929                 //PlatformIOWrite1Byte(Adapter, REG_LDOV12D_CTRL, 0x54);
1930
1931                 value8 = rtw_read8(Adapter, REG_LDOV12D_CTRL);
1932                 value8 &= (~LDV12_EN);
1933                 rtw_write8(Adapter, REG_LDOV12D_CTRL, value8);
1934                 //RT_TRACE(COMP_INIT, DBG_LOUD, (" REG_LDOV12D_CTRL Reg0x21:0x%02x.\n",value8));
1935         }
1936
1937 /*****************************
1938 h.      SPS0_CTRL 0x11[7:0] = 0x23                      //enter PFM mode
1939 i.      APS_FSMCO 0x04[15:0] = 0x4802           // set USB suspend
1940 ******************************/
1941
1942
1943         value8 = 0x23;
1944
1945         rtw_write8(Adapter, REG_SPS0_CTRL, value8);
1946
1947
1948         if(bWithoutHWSM)
1949         {
1950                 //value16 |= (APDM_HOST | /*AFSM_HSUS |*/PFM_ALDN);
1951                 // 2010/08/31 According to Filen description, we need to use HW to shut down 8051 automatically.
1952                 // Becasue suspend operatione need the asistance of 8051 to wait for 3ms.
1953                 value16 |= (APDM_HOST | AFSM_HSUS |PFM_ALDN);
1954         }
1955         else
1956         {
1957                 value16 |= (APDM_HOST | AFSM_HSUS |PFM_ALDN);
1958         }
1959
1960         rtw_write16(Adapter, REG_APS_FSMCO,value16 );//0x4802
1961
1962         rtw_write8(Adapter, REG_RSV_CTRL, 0x0e);
1963
1964  #if 0
1965         //tynli_test for suspend mode.
1966         if(!bWithoutHWSM){
1967                 rtw_write8(Adapter, 0xfe10, 0x19);
1968         }
1969 #endif
1970
1971         //RT_TRACE(COMP_INIT, DBG_LOUD, ("======> Disable Analog Reg0x04:0x%04x.\n",value16));
1972 }
1973
1974 static void rtl8723bu_hw_power_down(_adapter *padapter)
1975 {
1976         u8      u1bTmp;
1977
1978         DBG_8192C("PowerDownRTL8723U\n");
1979
1980
1981         // 1. Run Card Disable Flow
1982         // Done before this function call.
1983
1984         // 2. 0x04[16] = 0                      // reset WLON
1985         u1bTmp = rtw_read8(padapter, REG_APS_FSMCO+2);
1986         rtw_write8(padapter, REG_APS_FSMCO+2, (u1bTmp&(~BIT0)));
1987
1988         // 3. 0x04[12:11] = 2b'11 // enable suspend
1989         // Done before this function call.
1990
1991         // 4. 0x04[15] = 1                      // enable PDN
1992         u1bTmp = rtw_read8(padapter, REG_APS_FSMCO+1);
1993         rtw_write8(padapter, REG_APS_FSMCO+1, (u1bTmp|BIT7));
1994 }
1995
1996 //
1997 // Description: RTL8723e card disable power sequence v003 which suggested by Scott.
1998 // First created by tynli. 2011.01.28.
1999 //
2000 VOID
2001 CardDisableRTL8723U(
2002         PADAPTER                        Adapter
2003 )
2004 {
2005         u8              u1bTmp;
2006
2007         rtw_hal_get_hwreg(Adapter, HW_VAR_APFM_ON_MAC, &u1bTmp);
2008         DBG_8192C(FUNC_ADPT_FMT ": bMacPwrCtrlOn=%d\n", FUNC_ADPT_ARG(Adapter), u1bTmp);
2009         if (u1bTmp == _FALSE)
2010                 return;
2011         u1bTmp = _FALSE;
2012         rtw_hal_set_hwreg(Adapter, HW_VAR_APFM_ON_MAC, &u1bTmp);
2013
2014         //Stop Tx Report Timer. 0x4EC[Bit1]=b'0
2015         u1bTmp = rtw_read8(Adapter, REG_TX_RPT_CTRL);
2016         rtw_write8(Adapter, REG_TX_RPT_CTRL, u1bTmp&(~BIT1));
2017
2018         // stop rx
2019         rtw_write8(Adapter, REG_CR_8723B, 0x0);
2020
2021         // 1. Run LPS WL RFOFF flow
2022         HalPwrSeqCmdParsing(Adapter, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, rtl8723B_enter_lps_flow);
2023
2024         if((rtw_read8(Adapter, REG_MCUFWDL_8723B)&BIT7) &&
2025                 Adapter->bFWReady) //8051 RAM code
2026         {
2027                 rtl8723b_FirmwareSelfReset(Adapter);
2028         }
2029
2030         // Reset MCU. Suggested by Filen. 2011.01.26. by tynli.
2031         u1bTmp = rtw_read8(Adapter, REG_SYS_FUNC_EN_8723B+1);
2032         rtw_write8(Adapter, REG_SYS_FUNC_EN_8723B+1, (u1bTmp&(~BIT2)));
2033
2034         // MCUFWDL 0x80[1:0]=0                          // reset MCU ready status
2035         rtw_write8(Adapter, REG_MCUFWDL_8723B, 0x00);
2036
2037         // Card disable power action flow
2038         HalPwrSeqCmdParsing(Adapter, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, rtl8723B_card_disable_flow);
2039
2040 }
2041
2042
2043 u32 rtl8723bu_hal_deinit(PADAPTER padapter)
2044 {
2045         PHAL_DATA_TYPE  pHalData = GET_HAL_DATA(padapter);
2046
2047
2048         DBG_8192C("==> %s\n", __FUNCTION__);
2049
2050
2051         // 2011/02/18 To Fix RU LNA  power leakage problem. We need to execute below below in
2052         // Adapter init and halt sequence. Accordingto EEchou's opinion, we can enable the ability for all
2053         // IC. Accord to johnny's opinion, only RU need the support.
2054         CardDisableRTL8723U(padapter);
2055
2056         return _SUCCESS;
2057 }
2058
2059
2060 unsigned int rtl8723bu_inirp_init(PADAPTER Adapter)
2061 {
2062         u8 i;
2063         struct recv_buf *precvbuf;
2064         uint    status;
2065         struct dvobj_priv *pdev= adapter_to_dvobj(Adapter);
2066         struct intf_hdl * pintfhdl=&Adapter->iopriv.intf;
2067         struct recv_priv *precvpriv = &(Adapter->recvpriv);
2068         u32 (*_read_port)(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *pmem);
2069 #ifdef CONFIG_USB_INTERRUPT_IN_PIPE
2070         u32 (*_read_interrupt)(struct intf_hdl *pintfhdl, u32 addr);
2071         HAL_DATA_TYPE   *pHalData=GET_HAL_DATA(Adapter);
2072 #endif //CONFIG_USB_INTERRUPT_IN_PIPE
2073
2074 _func_enter_;
2075
2076         _read_port = pintfhdl->io_ops._read_port;
2077
2078         status = _SUCCESS;
2079
2080         RT_TRACE(_module_hci_hal_init_c_,_drv_info_,("===> usb_inirp_init \n"));
2081
2082         precvpriv->ff_hwaddr = RECV_BULK_IN_ADDR;
2083
2084         //issue Rx irp to receive data
2085         precvbuf = (struct recv_buf *)precvpriv->precv_buf;
2086         for(i=0; i<NR_RECVBUFF; i++)
2087         {
2088                 if(_read_port(pintfhdl, precvpriv->ff_hwaddr, 0, (unsigned char *)precvbuf) == _FALSE )
2089                 {
2090                         RT_TRACE(_module_hci_hal_init_c_,_drv_err_,("usb_rx_init: usb_read_port error \n"));
2091                         status = _FAIL;
2092                         goto exit;
2093                 }
2094
2095                 precvbuf++;
2096                 precvpriv->free_recv_buf_queue_cnt--;
2097         }
2098
2099 #ifdef CONFIG_USB_INTERRUPT_IN_PIPE
2100         _read_interrupt = pintfhdl->io_ops._read_interrupt;
2101         if(_read_interrupt(pintfhdl, RECV_INT_IN_ADDR) == _FALSE )
2102         {
2103                 RT_TRACE(_module_hci_hal_init_c_,_drv_err_,("usb_rx_init: usb_read_interrupt error \n"));
2104                 status = _FAIL;
2105         }
2106         pHalData->IntrMask[0]=rtw_read32(Adapter, REG_USB_HIMR);
2107         MSG_8192C("pHalData->IntrMask = 0x%04x\n", pHalData->IntrMask[0]);
2108         pHalData->IntrMask[0]|=UHIMR_C2HCMD|UHIMR_CPWM;
2109         rtw_write32(Adapter, REG_USB_HIMR,pHalData->IntrMask[0]);
2110 #endif //CONFIG_USB_INTERRUPT_IN_PIPE
2111
2112 exit:
2113
2114         RT_TRACE(_module_hci_hal_init_c_,_drv_info_,("<=== usb_inirp_init \n"));
2115
2116 _func_exit_;
2117
2118         return status;
2119
2120 }
2121
2122 unsigned int rtl8723bu_inirp_deinit(PADAPTER Adapter)
2123 {
2124 #ifdef CONFIG_USB_INTERRUPT_IN_PIPE
2125         u32 (*_read_interrupt)(struct intf_hdl *pintfhdl, u32 addr);
2126         HAL_DATA_TYPE   *pHalData=GET_HAL_DATA(Adapter);
2127 #endif //CONFIG_USB_INTERRUPT_IN_PIPE
2128         RT_TRACE(_module_hci_hal_init_c_,_drv_info_,("\n ===> usb_rx_deinit \n"));
2129
2130         rtw_read_port_cancel(Adapter);
2131 #ifdef CONFIG_USB_INTERRUPT_IN_PIPE
2132         pHalData->IntrMask[0]=rtw_read32(Adapter, REG_USB_HIMR);
2133         MSG_8192C("%s pHalData->IntrMask = 0x%04x\n",__FUNCTION__, pHalData->IntrMask[0]);
2134         pHalData->IntrMask[0]=0x0;
2135         rtw_write32(Adapter, REG_USB_HIMR,pHalData->IntrMask[0]);
2136         RT_TRACE(_module_hci_hal_init_c_,_drv_info_,("\n <=== usb_rx_deinit \n"));
2137 #endif //CONFIG_USB_INTERRUPT_IN_PIPE
2138         return _SUCCESS;
2139 }
2140
2141
2142 static u32
2143 _GetChannelGroup(
2144         IN      u32     channel
2145         )
2146 {
2147         //RT_ASSERT((channel < 14), ("Channel %d no is supported!\n"));
2148
2149         if(channel < 3){        // Channel 1~3
2150                 return 0;
2151         }
2152         else if(channel < 9){ // Channel 4~9
2153                 return 1;
2154         }
2155
2156         return 2;                               // Channel 10~14
2157 }
2158
2159
2160 //-------------------------------------------------------------------
2161 //
2162 //      EEPROM/EFUSE Content Parsing
2163 //
2164 //-------------------------------------------------------------------
2165 static VOID
2166 _ReadMACAddress(
2167         IN      PADAPTER        Adapter,
2168         IN      u8*             PROMContent,
2169         IN      BOOLEAN         AutoloadFail
2170         )
2171 {
2172         PHAL_DATA_TYPE pHalData = GET_HAL_DATA(Adapter);
2173
2174         if(_FALSE == AutoloadFail){
2175                 //Read Permanent MAC address and set value to hardware
2176                 _rtw_memcpy(pHalData->EEPROMMACAddr, &PROMContent[EEPROM_MAC_ADDR_8723BU], ETH_ALEN);
2177         }
2178         else{
2179                 //Random assigh MAC address
2180                 u8 sMacAddr[MAC_ADDR_LEN] = {0x00, 0xE0, 0x4C, 0x81, 0x92, 0x00};
2181                 //sMacAddr[5] = (u8)GetRandomNumber(1, 254);
2182                 _rtw_memcpy(pHalData->EEPROMMACAddr, sMacAddr, ETH_ALEN);
2183         }
2184         DBG_8192C("%s MAC Address from EFUSE = "MAC_FMT"\n",__FUNCTION__, MAC_ARG(pHalData->EEPROMMACAddr));
2185         //NicIFSetMacAddress(Adapter, Adapter->PermanentAddress);
2186         //RT_PRINT_ADDR(COMP_INIT|COMP_EFUSE, DBG_LOUD, "MAC Addr: %s", Adapter->PermanentAddress);
2187
2188 }
2189
2190 static VOID
2191 _ReadLEDSetting(
2192         IN      PADAPTER        Adapter,
2193         IN      u8*             PROMContent,
2194         IN      BOOLEAN         AutoloadFail
2195         )
2196 {
2197         struct led_priv *pledpriv = &(Adapter->ledpriv);
2198         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(Adapter);
2199
2200 #ifdef CONFIG_SW_LED
2201         pledpriv->bRegUseLed = _TRUE;
2202
2203         //
2204         // Led mode
2205         //
2206         switch(pHalData->CustomerID)
2207         {
2208                 case RT_CID_DEFAULT:
2209                         pledpriv->LedStrategy = SW_LED_MODE1;
2210                         pledpriv->bRegUseLed = _TRUE;
2211                         break;
2212
2213                 case RT_CID_819x_HP:
2214                         pledpriv->LedStrategy = SW_LED_MODE6;
2215                         break;
2216
2217                 default:
2218                         pledpriv->LedStrategy = SW_LED_MODE1;
2219                         break;
2220         }
2221
2222         pHalData->bLedOpenDrain = _TRUE;// Support Open-drain arrangement for controlling the LED. Added by Roger, 2009.10.16.
2223 #else // HW LED
2224         pledpriv->LedStrategy = HW_LED;
2225 #endif //CONFIG_SW_LED
2226 }
2227
2228 static VOID
2229 _ReadRFSetting(
2230         IN      PADAPTER        Adapter,
2231         IN      u8*     PROMContent,
2232         IN      BOOLEAN         AutoloadFail
2233         )
2234 {
2235 }
2236
2237 // Read HW power down mode selection
2238 static void _ReadPSSetting(IN PADAPTER Adapter,IN u8*PROMContent,IN u8  AutoloadFail)
2239 {
2240         struct pwrctrl_priv *pwrctl = adapter_to_pwrctl(Adapter);
2241
2242         if(AutoloadFail){
2243                 pwrctl->bHWPowerdown = _FALSE;
2244                 pwrctl->bSupportRemoteWakeup = _FALSE;
2245         }
2246         else    {
2247                 //if(SUPPORT_HW_RADIO_DETECT(Adapter))
2248                         pwrctl->bHWPwrPindetect = Adapter->registrypriv.hwpwrp_detect;
2249                 //else
2250                         //pwrctl->bHWPwrPindetect = _FALSE;//dongle not support new
2251
2252
2253                 //hw power down mode selection , 0:rf-off / 1:power down
2254
2255                 if(Adapter->registrypriv.hwpdn_mode==2)
2256                         pwrctl->bHWPowerdown = (PROMContent[EEPROM_FEATURE_OPTION_8723B] & BIT4);
2257                 else
2258                         pwrctl->bHWPowerdown = Adapter->registrypriv.hwpdn_mode;
2259
2260                 // decide hw if support remote wakeup function
2261                 // if hw supported, 8051 (SIE) will generate WeakUP signal( D+/D- toggle) when autoresume
2262                 pwrctl->bSupportRemoteWakeup = (PROMContent[EEPROM_USB_OPTIONAL_FUNCTION0] & BIT1)?_TRUE :_FALSE;
2263
2264                 //if(SUPPORT_HW_RADIO_DETECT(Adapter))
2265                         //Adapter->registrypriv.usbss_enable = pwrctl->bSupportRemoteWakeup ;
2266
2267                 DBG_8192C("%s...bHWPwrPindetect(%x)-bHWPowerdown(%x) ,bSupportRemoteWakeup(%x)\n",__FUNCTION__,
2268                         pwrctl->bHWPwrPindetect, pwrctl->bHWPowerdown, pwrctl->bSupportRemoteWakeup);
2269
2270                 DBG_8192C("### PS params=>  power_mgnt(%x),usbss_enable(%x) ###\n",Adapter->registrypriv.power_mgnt,Adapter->registrypriv.usbss_enable);
2271
2272         }
2273
2274 }
2275
2276
2277
2278
2279
2280
2281 VOID
2282 Hal_EfuseParsePIDVID_8723BU(
2283         IN      PADAPTER                pAdapter,
2284         IN      u8*                     hwinfo,
2285         IN      BOOLEAN                 AutoLoadFail
2286         )
2287 {
2288         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(pAdapter);
2289
2290         if(AutoLoadFail)
2291         {
2292                 pHalData->EEPROMVID = 0;
2293                 pHalData->EEPROMPID = 0;
2294         }
2295         else
2296         {
2297                         // VID, PID
2298                 pHalData->EEPROMVID = le16_to_cpu(*(u16*)&hwinfo[EEPROM_VID_8723BU]);
2299                 pHalData->EEPROMPID = le16_to_cpu(*(u16*)&hwinfo[EEPROM_PID_8723BU]);
2300
2301         }
2302
2303         MSG_8192C("EEPROM VID = 0x%4x\n", pHalData->EEPROMVID);
2304         MSG_8192C("EEPROM PID = 0x%4x\n", pHalData->EEPROMPID);
2305 }
2306
2307
2308 static void
2309 Hal_EfuseParseMACAddr_8723BU(
2310         IN      PADAPTER                padapter,
2311         IN      u8*                     hwinfo,
2312         IN      BOOLEAN                 AutoLoadFail
2313         )
2314 {
2315         u16                     i, usValue;
2316         u8                      sMacAddr[6] = {0x00, 0xE0, 0x4C, 0x87, 0x23, 0x00};
2317         PHAL_DATA_TYPE pHalData = GET_HAL_DATA(padapter);
2318         if (AutoLoadFail)
2319         {
2320 //              sMacAddr[5] = (u1Byte)GetRandomNumber(1, 254);
2321                 for (i=0; i<6; i++)
2322                         pHalData->EEPROMMACAddr[i] = sMacAddr[i];
2323         }
2324         else
2325         {
2326                 //Read Permanent MAC address
2327 #if 1
2328                 _rtw_memcpy(pHalData->EEPROMMACAddr, &hwinfo[EEPROM_MAC_ADDR_8723BU], ETH_ALEN);
2329 #else
2330                 for(i=0; i<6; i+=2)
2331                 {
2332                         usValue = *(u16*)&hwinfo[EEPROM_MAC_ADDR_8723S+i];
2333                         *((u16*)(&pHalData->EEPROMMACAddr[i])) = usValue;
2334                 }
2335 #endif
2336         }
2337 //      NicIFSetMacAddress(pAdapter, pAdapter->PermanentAddress);
2338
2339         RT_TRACE(_module_hci_hal_init_c_, _drv_notice_,
2340                  ("Hal_EfuseParseMACAddr_8723BU: Permanent Address=%02x:%02x:%02x:%02x:%02x:%02x\n",
2341                   pHalData->EEPROMMACAddr[0], pHalData->EEPROMMACAddr[1],
2342                   pHalData->EEPROMMACAddr[2], pHalData->EEPROMMACAddr[3],
2343                   pHalData->EEPROMMACAddr[4], pHalData->EEPROMMACAddr[5]));
2344 }
2345
2346
2347 #ifdef CONFIG_EFUSE_CONFIG_FILE
2348 static u32 Hal_readPGDataFromConfigFile(
2349         PADAPTER        padapter)
2350 {
2351         u32 i;
2352         struct file *fp;
2353         mm_segment_t fs;
2354         u8 temp[3];
2355         loff_t pos = 0;
2356         PHAL_DATA_TYPE pHalData = GET_HAL_DATA(padapter);
2357         u8      *PROMContent = pHalData->efuse_eeprom_data;
2358
2359
2360         temp[2] = 0; // add end of string '\0'
2361
2362         fp = filp_open("/system/etc/wifi/wifi_efuse.map", O_RDWR,  0644);
2363         if (IS_ERR(fp)) {
2364                 pHalData->bloadfile_fail_flag= _TRUE;
2365                 DBG_871X("Error, Efuse configure file doesn't exist.\n");
2366                 return _FAIL;
2367         }
2368
2369         fs = get_fs();
2370         set_fs(KERNEL_DS);
2371
2372         DBG_871X("Efuse configure file:\n");
2373         for (i=0; i<HWSET_MAX_SIZE_88E; i++) {
2374                 vfs_read(fp, temp, 2, &pos);
2375                 PROMContent[i] = simple_strtoul(temp, NULL, 16 );
2376                 pos += 1; // Filter the space character
2377                 DBG_871X("%02X \n", PROMContent[i]);
2378         }
2379         DBG_871X("\n");
2380         set_fs(fs);
2381
2382         filp_close(fp, NULL);
2383
2384         pHalData->bloadfile_fail_flag= _FALSE;
2385         return _SUCCESS;
2386 }
2387
2388
2389 static void
2390 Hal_ReadMACAddrFromFile_8723AU(
2391         PADAPTER                padapter
2392         )
2393 {
2394         u32 i;
2395         struct file *fp;
2396         mm_segment_t fs;
2397         u8 source_addr[18];
2398         loff_t pos = 0;
2399         u32 curtime = rtw_get_current_time();
2400         PHAL_DATA_TYPE pHalData = GET_HAL_DATA(padapter);
2401         u8 *head, *end;
2402
2403         u8 null_mac_addr[ETH_ALEN] = {0, 0, 0,0, 0, 0};
2404         u8 multi_mac_addr[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
2405
2406         _rtw_memset(source_addr, 0, 18);
2407         _rtw_memset(pHalData->EEPROMMACAddr, 0, ETH_ALEN);
2408
2409         fp = filp_open("/data/wifimac.txt", O_RDWR,  0644);
2410         if (IS_ERR(fp)) {
2411                 pHalData->bloadmac_fail_flag = _TRUE;
2412                 DBG_871X("Error, wifi mac address file doesn't exist.\n");
2413         } else {
2414                 fs = get_fs();
2415                 set_fs(KERNEL_DS);
2416
2417                 DBG_871X("wifi mac address:\n");
2418                 vfs_read(fp, source_addr, 18, &pos);
2419                 source_addr[17] = ':';
2420
2421                 head = end = source_addr;
2422                 for (i=0; i<ETH_ALEN; i++) {
2423                         while (end && (*end != ':') )
2424                                 end++;
2425
2426                         if (end && (*end == ':') )
2427                                 *end = '\0';
2428
2429                         pHalData->EEPROMMACAddr[i] = simple_strtoul(head, NULL, 16 );
2430
2431                         if (end) {
2432                                 end++;
2433                                 head = end;
2434                         }
2435                         DBG_871X("%02x \n", pHalData->EEPROMMACAddr[i]);
2436                 }
2437                 DBG_871X("\n");
2438                 set_fs(fs);
2439
2440                 filp_close(fp, NULL);
2441         }
2442
2443         if ( (_rtw_memcmp(pHalData->EEPROMMACAddr, null_mac_addr, ETH_ALEN)) ||
2444                 (_rtw_memcmp(pHalData->EEPROMMACAddr, multi_mac_addr, ETH_ALEN)) ) {
2445                 pHalData->EEPROMMACAddr[0] = 0x00;
2446                 pHalData->EEPROMMACAddr[1] = 0xe0;
2447                 pHalData->EEPROMMACAddr[2] = 0x4c;
2448                 pHalData->EEPROMMACAddr[3] = (u8)(curtime & 0xff) ;
2449                 pHalData->EEPROMMACAddr[4] = (u8)((curtime>>8) & 0xff) ;
2450                 pHalData->EEPROMMACAddr[5] = (u8)((curtime>>16) & 0xff) ;
2451         }
2452
2453         pHalData->bloadmac_fail_flag = _FALSE;
2454
2455          DBG_871X("Hal_ReadMACAddrFromFile_8188ES: Permanent Address = %02x-%02x-%02x-%02x-%02x-%02x\n",
2456                   pHalData->EEPROMMACAddr[0], pHalData->EEPROMMACAddr[1],
2457                   pHalData->EEPROMMACAddr[2], pHalData->EEPROMMACAddr[3],
2458                   pHalData->EEPROMMACAddr[4], pHalData->EEPROMMACAddr[5]);
2459 }
2460 #endif //CONFIG_EFUSE_CONFIG_FILE
2461
2462
2463 static VOID
2464 InitAdapterVariablesByPROM_8723BU(
2465         IN      PADAPTER        padapter
2466         )
2467 {
2468
2469         PHAL_DATA_TYPE pHalData = GET_HAL_DATA(padapter);
2470         u8*                     hwinfo = NULL;
2471
2472         if (sizeof(pHalData->efuse_eeprom_data) < HWSET_MAX_SIZE_8723B)
2473                 DBG_871X("[WARNING] size of efuse_eeprom_data is less than HWSET_MAX_SIZE_8723B!\n");
2474
2475         hwinfo = pHalData->efuse_eeprom_data;
2476
2477 #ifdef CONFIG_EFUSE_CONFIG_FILE
2478         Hal_readPGDataFromConfigFile(padapter);
2479 #else //CONFIG_EFUSE_CONFIG_FILE
2480         Hal_InitPGData(padapter, hwinfo);
2481 #endif  //CONFIG_EFUSE_CONFIG_FILE
2482         Hal_EfuseParseIDCode(padapter, hwinfo);
2483         Hal_EfuseParsePIDVID_8723BU(padapter, hwinfo, pHalData->bautoload_fail_flag);
2484         Hal_EfuseParseEEPROMVer_8723B(padapter, hwinfo, pHalData->bautoload_fail_flag);
2485 #ifdef CONFIG_EFUSE_CONFIG_FILE
2486         Hal_ReadMACAddrFromFile_8723BU(padapter);
2487 #else //CONFIG_EFUSE_CONFIG_FILE
2488         Hal_EfuseParseMACAddr_8723BU(padapter, hwinfo, pHalData->bautoload_fail_flag);
2489 #endif
2490         Hal_EfuseParseTxPowerInfo_8723B(padapter, hwinfo, pHalData->bautoload_fail_flag);
2491         Hal_EfuseParseBoardType_8723B(padapter, hwinfo, pHalData->bautoload_fail_flag);
2492
2493         Hal_EfuseParseBTCoexistInfo_8723B(padapter, hwinfo, pHalData->bautoload_fail_flag);
2494
2495         Hal_EfuseParseChnlPlan_8723B(padapter, hwinfo, pHalData->bautoload_fail_flag);
2496         Hal_EfuseParseThermalMeter_8723B(padapter, hwinfo, pHalData->bautoload_fail_flag);
2497 //      _ReadLEDSetting(Adapter, PROMContent, pHalData->bautoload_fail_flag);
2498 //      _ReadRFSetting(Adapter, PROMContent, pHalData->bautoload_fail_flag);
2499 //      _ReadPSSetting(Adapter, PROMContent, pHalData->bautoload_fail_flag);
2500         Hal_EfuseParseAntennaDiversity_8723B(padapter, hwinfo, pHalData->bautoload_fail_flag);
2501
2502         Hal_EfuseParseEEPROMVer_8723B(padapter, hwinfo, pHalData->bautoload_fail_flag);
2503         Hal_EfuseParseCustomerID_8723B(padapter, hwinfo, pHalData->bautoload_fail_flag);
2504 //      Hal_EfuseParseRateIndicationOption(padapter, hwinfo, pHalData->bautoload_fail_flag);
2505         Hal_EfuseParseXtal_8723B(padapter, hwinfo, pHalData->bautoload_fail_flag);
2506         //
2507         // The following part initialize some vars by PG info.
2508         //
2509
2510
2511
2512         //hal_CustomizedBehavior_8723U(Adapter);
2513
2514 //      Adapter->bDongle = (PROMContent[EEPROM_EASY_REPLACEMENT] == 1)? 0: 1;
2515         DBG_8192C("%s(): REPLACEMENT = %x\n",__FUNCTION__,padapter->bDongle);
2516 }
2517
2518 static void _ReadPROMContent(
2519         IN PADAPTER             Adapter
2520         )
2521 {
2522         PHAL_DATA_TYPE pHalData = GET_HAL_DATA(Adapter);
2523
2524         u8                      eeValue;
2525         u32                     i;
2526         u16                     value16;
2527
2528         eeValue = rtw_read8(Adapter, REG_9346CR);
2529         // To check system boot selection.
2530         pHalData->EepromOrEfuse         = (eeValue & BOOT_FROM_EEPROM) ? _TRUE : _FALSE;
2531         pHalData->bautoload_fail_flag   = (eeValue & EEPROM_EN) ? _FALSE : _TRUE;
2532
2533
2534         DBG_8192C("Boot from %s, Autoload %s !\n", (pHalData->EepromOrEfuse ? "EEPROM" : "EFUSE"),
2535                                 (pHalData->bautoload_fail_flag ? "Fail" : "OK") );
2536
2537
2538         InitAdapterVariablesByPROM_8723BU(Adapter);
2539 }
2540
2541
2542 static VOID
2543 _InitOtherVariable(
2544         IN PADAPTER             Adapter
2545         )
2546 {
2547         //HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
2548
2549
2550         //if(Adapter->bInHctTest){
2551         //      pMgntInfo->PowerSaveControl.bInactivePs = FALSE;
2552         //      pMgntInfo->PowerSaveControl.bIPSModeBackup = FALSE;
2553         //      pMgntInfo->PowerSaveControl.bLeisurePs = FALSE;
2554         //      pMgntInfo->keepAliveLevel = 0;
2555         //}
2556
2557
2558 }
2559
2560 static VOID
2561 _ReadRFType(
2562         IN      PADAPTER        Adapter
2563         )
2564 {
2565         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(Adapter);
2566
2567 #if DISABLE_BB_RF
2568         pHalData->rf_chip = RF_PSEUDO_11N;
2569 #else
2570         pHalData->rf_chip = RF_6052;
2571 #endif
2572 }
2573
2574
2575
2576 //
2577 //      Description:
2578 //              We should set Efuse cell selection to WiFi cell in default.
2579 //
2580 //      Assumption:
2581 //              PASSIVE_LEVEL
2582 //
2583 //      Added by Roger, 2010.11.23.
2584 //
2585 void
2586 hal_EfuseCellSel(
2587         IN      PADAPTER        Adapter
2588         )
2589 {
2590         u32                     value32;
2591
2592         value32 = rtw_read32(Adapter, EFUSE_TEST);
2593         value32 = (value32 & ~EFUSE_SEL_MASK) | EFUSE_SEL(EFUSE_WIFI_SEL_0);
2594         rtw_write32(Adapter, EFUSE_TEST, value32);
2595 }
2596
2597 static int _ReadAdapterInfo8723BU(PADAPTER      Adapter)
2598 {
2599         //HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
2600         u32 start=rtw_get_current_time();
2601
2602         MSG_8192C("====> _ReadAdapterInfo8723BU\n");
2603
2604         //Efuse_InitSomeVar(Adapter);
2605
2606         hal_EfuseCellSel(Adapter);
2607
2608         _ReadRFType(Adapter);//rf_chip -> _InitRFType()
2609         _ReadPROMContent(Adapter);
2610
2611         // 2010/10/25 MH THe function must be called after borad_type & IC-Version recognize.
2612 //      _ReadSilmComboMode(Adapter);
2613
2614         _InitOtherVariable(Adapter);
2615
2616         //MSG_8192C("%s()(done), rf_chip=0x%x, rf_type=0x%x\n",  __FUNCTION__, pHalData->rf_chip, pHalData->rf_type);
2617
2618         MSG_8192C("<==== _ReadAdapterInfo8723BU in %d ms\n", rtw_get_passing_time_ms(start));
2619
2620         return _SUCCESS;
2621 }
2622
2623
2624 static void ReadAdapterInfo8723BU(PADAPTER Adapter)
2625 {
2626         // Read EEPROM size before call any EEPROM function
2627         Adapter->EepromAddressSize = GetEEPROMSize8723B(Adapter);
2628
2629         _ReadAdapterInfo8723BU(Adapter);
2630 }
2631
2632
2633 #define GPIO_DEBUG_PORT_NUM 0
2634 static void rtl8723bu_trigger_gpio_0(_adapter *padapter)
2635 {
2636
2637         u32 gpioctrl;
2638         DBG_871X("==> trigger_gpio_0...\n");
2639         rtw_write16_async(padapter,REG_GPIO_PIN_CTRL,0);
2640         rtw_write8_async(padapter,REG_GPIO_PIN_CTRL+2,0xFF);
2641         gpioctrl = (BIT(GPIO_DEBUG_PORT_NUM)<<24 )|(BIT(GPIO_DEBUG_PORT_NUM)<<16);
2642         rtw_write32_async(padapter,REG_GPIO_PIN_CTRL,gpioctrl);
2643         gpioctrl |= (BIT(GPIO_DEBUG_PORT_NUM)<<8);
2644         rtw_write32_async(padapter,REG_GPIO_PIN_CTRL,gpioctrl);
2645         DBG_871X("<=== trigger_gpio_0...\n");
2646
2647 }
2648
2649 /*
2650  * If variable not handled here,
2651  * some variables will be processed in SetHwReg8723A()
2652  */
2653 void SetHwReg8723BU(PADAPTER Adapter, u8 variable, u8* val)
2654 {
2655         PHAL_DATA_TYPE  pHalData = GET_HAL_DATA(Adapter);
2656
2657 _func_enter_;
2658
2659         switch(variable)
2660         {
2661                 case HW_VAR_RXDMA_AGG_PG_TH:
2662 #ifdef CONFIG_USB_RX_AGGREGATION
2663                         {
2664                                 u8 threshold = *val;
2665                                 if (threshold == 0)
2666                                         threshold = pHalData->UsbRxAggPageCount;
2667                                 SetHwReg8723B(Adapter, HW_VAR_RXDMA_AGG_PG_TH, &threshold);
2668                         }
2669 #endif
2670                         break;
2671
2672                 case HW_VAR_SET_RPWM:
2673                         rtw_write8(Adapter, REG_USB_HRPWM, *val);
2674                         break;
2675
2676                 case HW_VAR_TRIGGER_GPIO_0:
2677                         rtl8723bu_trigger_gpio_0(Adapter);
2678                         break;
2679
2680                 default:
2681                         SetHwReg8723B(Adapter, variable, val);
2682                         break;
2683         }
2684
2685 _func_exit_;
2686 }
2687
2688 /*
2689  * If variable not handled here,
2690  * some variables will be processed in GetHwReg8723A()
2691  */
2692 void GetHwReg8723BU(PADAPTER Adapter, u8 variable, u8* val)
2693 {
2694         PHAL_DATA_TYPE  pHalData = GET_HAL_DATA(Adapter);
2695
2696 _func_enter_;
2697
2698         switch (variable)
2699         {
2700                 default:
2701                         GetHwReg8723B(Adapter, variable, val);
2702                         break;
2703         }
2704
2705 _func_exit_;
2706 }
2707
2708 //
2709 //      Description:
2710 //              Query setting of specified variable.
2711 //
2712 u8
2713 GetHalDefVar8723BUsb(
2714         IN      PADAPTER                                Adapter,
2715         IN      HAL_DEF_VARIABLE                eVariable,
2716         IN      PVOID                                   pValue
2717         )
2718 {
2719         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(Adapter);
2720         u8                      bResult = _SUCCESS;
2721
2722         switch(eVariable)
2723         {
2724                 case HAL_DEF_IS_SUPPORT_ANT_DIV:
2725                         #ifdef CONFIG_ANTENNA_DIVERSITY
2726                         *((u8 *)pValue) =_FALSE;
2727                         #endif
2728                         break;
2729                 case HAL_DEF_CURRENT_ANTENNA:
2730                         #ifdef CONFIG_ANTENNA_DIVERSITY
2731                         *(( u8*)pValue) = pHalData->CurAntenna;
2732                         #endif
2733                         break;
2734                 case HAL_DEF_DRVINFO_SZ:
2735                         *(( u32*)pValue) = DRVINFO_SZ;
2736                         break;
2737                 case HAL_DEF_MAX_RECVBUF_SZ:
2738                         *(( u32*)pValue) = MAX_RECVBUF_SZ;
2739                         break;
2740                 case HAL_DEF_RX_PACKET_OFFSET:
2741                         *(( u32*)pValue) = RXDESC_SIZE + DRVINFO_SZ;
2742                         break;
2743                 case HW_VAR_MAX_RX_AMPDU_FACTOR:
2744                         *((HT_CAP_AMPDU_FACTOR*)pValue) = MAX_AMPDU_FACTOR_64K;
2745                         break;
2746                 default:
2747                         bResult = GetHalDefVar8723B(Adapter, eVariable, pValue);
2748                         break;
2749         }
2750
2751         return bResult;
2752 }
2753
2754
2755
2756
2757 //
2758 //      Description:
2759 //              Change default setting of specified variable.
2760 //
2761 u8
2762 SetHalDefVar8723BUsb(
2763         IN      PADAPTER                                Adapter,
2764         IN      HAL_DEF_VARIABLE                eVariable,
2765         IN      PVOID                                   pValue
2766         )
2767 {
2768         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(Adapter);
2769         u8                      bResult = _SUCCESS;
2770
2771         switch(eVariable)
2772         {
2773                 default:
2774                         bResult = SetHalDefVar8723B(Adapter, eVariable, pValue);
2775                         break;
2776         }
2777
2778         return bResult;
2779 }
2780
2781 void _update_response_rate(_adapter *padapter,unsigned int mask)
2782 {
2783         u8      RateIndex = 0;
2784         // Set RRSR rate table.
2785         rtw_write8(padapter, REG_RRSR, mask&0xff);
2786         rtw_write8(padapter,REG_RRSR+1, (mask>>8)&0xff);
2787
2788         // Set RTS initial rate
2789         while(mask > 0x1)
2790         {
2791                 mask = (mask>> 1);
2792                 RateIndex++;
2793         }
2794         rtw_write8(padapter, REG_INIRTS_RATE_SEL, RateIndex);
2795 }
2796
2797 static void rtl8723bu_init_default_value(PADAPTER padapter)
2798 {
2799         rtl8723b_init_default_value(padapter);
2800 }
2801
2802 static u8 rtl8723bu_ps_func(PADAPTER Adapter,HAL_INTF_PS_FUNC efunc_id, u8 *val)
2803 {
2804         u8 bResult = _TRUE;
2805         switch(efunc_id){
2806
2807                 #if defined(CONFIG_AUTOSUSPEND) && defined(SUPPORT_HW_RFOFF_DETECTED)
2808                 case HAL_USB_SELECT_SUSPEND:
2809                         {
2810                                 u8 bfwpoll = *(( u8*)val);
2811                                 rtl8723b_set_FwSelectSuspend_cmd(Adapter,bfwpoll ,500);//note fw to support hw power down ping detect
2812                         }
2813                         break;
2814                 #endif //CONFIG_AUTOSUSPEND && SUPPORT_HW_RFOFF_DETECTED
2815
2816                 default:
2817                         break;
2818         }
2819         return bResult;
2820 }
2821
2822 void rtl8723bu_set_hal_ops(_adapter * padapter)
2823 {
2824         struct hal_ops  *pHalFunc = &padapter->HalFunc;
2825
2826 _func_enter_;
2827
2828         rtl8723b_set_hal_ops(pHalFunc);
2829
2830         pHalFunc->hal_power_on = &_InitPowerOn_8723BU;
2831         pHalFunc->hal_power_off = &CardDisableRTL8723U;
2832
2833         pHalFunc->hal_init = &rtl8723bu_hal_init;
2834         pHalFunc->hal_deinit = &rtl8723bu_hal_deinit;
2835
2836         pHalFunc->inirp_init = &rtl8723bu_inirp_init;
2837         pHalFunc->inirp_deinit = &rtl8723bu_inirp_deinit;
2838
2839         pHalFunc->init_xmit_priv = &rtl8723bu_init_xmit_priv;
2840         pHalFunc->free_xmit_priv = &rtl8723bu_free_xmit_priv;
2841
2842         pHalFunc->init_recv_priv = &rtl8723bu_init_recv_priv;
2843         pHalFunc->free_recv_priv = &rtl8723bu_free_recv_priv;
2844 #ifdef CONFIG_SW_LED
2845         pHalFunc->InitSwLeds = &rtl8723bu_InitSwLeds;
2846         pHalFunc->DeInitSwLeds = &rtl8723bu_DeInitSwLeds;
2847 #else //case of hw led or no led
2848         pHalFunc->InitSwLeds = NULL;
2849         pHalFunc->DeInitSwLeds = NULL;
2850 #endif//CONFIG_SW_LED
2851
2852         pHalFunc->init_default_value = &rtl8723b_init_default_value;
2853         pHalFunc->intf_chip_configure = &rtl8723bu_interface_configure;
2854         pHalFunc->read_adapter_info = &ReadAdapterInfo8723BU;
2855
2856         pHalFunc->SetHwRegHandler = &SetHwReg8723BU;
2857         pHalFunc->GetHwRegHandler = &GetHwReg8723BU;
2858         pHalFunc->GetHalDefVarHandler = &GetHalDefVar8723BUsb;
2859         pHalFunc->SetHalDefVarHandler = &SetHalDefVar8723BUsb;
2860
2861         pHalFunc->hal_xmit = &rtl8723bu_hal_xmit;
2862         pHalFunc->mgnt_xmit = &rtl8723bu_mgnt_xmit;
2863         pHalFunc->hal_xmitframe_enqueue = &rtl8723bu_hal_xmitframe_enqueue;
2864
2865 #ifdef CONFIG_HOSTAPD_MLME
2866         pHalFunc->hostap_mgnt_xmit_entry = &rtl8723bu_hostap_mgnt_xmit_entry;
2867 #endif
2868         pHalFunc->interface_ps_func = &rtl8723bu_ps_func;
2869
2870 #ifdef CONFIG_XMIT_THREAD_MODE
2871         pHalFunc->xmit_thread_handler = &rtl8723bu_xmit_buf_handler;
2872 #endif
2873
2874 _func_exit_;
2875 }
2876