1 /******************************************************************************
3 * Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
19 ******************************************************************************/
20 #ifndef __RTW_PWRCTRL_H_
21 #define __RTW_PWRCTRL_H_
39 #define XMIT_ALIVE BIT(0)
40 #define RECV_ALIVE BIT(1)
41 #define CMD_ALIVE BIT(2)
42 #define EVT_ALIVE BIT(3)
43 #ifdef CONFIG_BT_COEXIST
44 #define BTCOEX_ALIVE BIT(4)
45 #endif // CONFIG_BT_COEXIST
53 PS_MODE_DTIM , //PS_MODE_SELF_DEFINED
64 #ifdef CONFIG_PNO_SUPPORT
65 #define MAX_PNO_LIST_COUNT 16
66 #define MAX_SCAN_LIST_COUNT 14 //2.4G only
71 BIT[3] = Protocol PS state, 0: register active state , 1: register sleep state
76 #define PS_LCLK (PS_DPS)
77 #define PS_RF_OFF BIT(1)
78 #define PS_ALL_ON BIT(2)
79 #define PS_ST_ACTIVE BIT(3)
81 #define PS_ISR_ENABLE BIT(4)
82 #define PS_IMR_ENABLE BIT(5)
84 #define PS_TOGGLE BIT(7)
86 #define PS_STATE_MASK (0x0F)
87 #define PS_STATE_HW_MASK (0x07)
88 #define PS_SEQ_MASK (0xc0)
90 #define PS_STATE(x) (PS_STATE_MASK & (x))
91 #define PS_STATE_HW(x) (PS_STATE_HW_MASK & (x))
92 #define PS_SEQ(x) (PS_SEQ_MASK & (x))
94 #define PS_STATE_S0 (PS_DPS)
95 #define PS_STATE_S1 (PS_LCLK)
96 #define PS_STATE_S2 (PS_RF_OFF)
97 #define PS_STATE_S3 (PS_ALL_ON)
98 #define PS_STATE_S4 ((PS_ST_ACTIVE) | (PS_ALL_ON))
101 #define PS_IS_RF_ON(x) ((x) & (PS_ALL_ON))
102 #define PS_IS_ACTIVE(x) ((x) & (PS_ST_ACTIVE))
103 #define CLR_PS_STATE(x) ((x) = ((x) & (0xF0)))
106 struct reportpwrstate_parm {
108 unsigned char state; //the CPWM value
113 typedef _sema _pwrlock;
116 __inline static void _init_pwrlock(_pwrlock *plock)
118 _rtw_init_sema(plock, 1);
121 __inline static void _free_pwrlock(_pwrlock *plock)
123 _rtw_free_sema(plock);
127 __inline static void _enter_pwrlock(_pwrlock *plock)
129 _rtw_down_sema(plock);
133 __inline static void _exit_pwrlock(_pwrlock *plock)
138 #define LPS_DELAY_TIME 1*HZ // 1 sec
140 #define EXE_PWR_NONE 0x01
141 #define EXE_PWR_IPS 0x02
142 #define EXE_PWR_LPS 0x04
145 typedef enum _rt_rf_power_state
147 rf_on, // RF is on after RFSleep or RFOff
148 rf_sleep, // 802.11 Power Save mode
149 rf_off, // HW/SW Radio OFF or Inactive Power Save
150 //=====Add the new RF state above this line=====//
154 // RF Off Level for IPS or HW/SW radio off
155 #define RT_RF_OFF_LEVL_ASPM BIT(0) // PCI ASPM
156 #define RT_RF_OFF_LEVL_CLK_REQ BIT(1) // PCI clock request
157 #define RT_RF_OFF_LEVL_PCI_D3 BIT(2) // PCI D3 mode
158 #define RT_RF_OFF_LEVL_HALT_NIC BIT(3) // NIC halt, re-initialize hw parameters
159 #define RT_RF_OFF_LEVL_FREE_FW BIT(4) // FW free, re-download the FW
160 #define RT_RF_OFF_LEVL_FW_32K BIT(5) // FW in 32k
161 #define RT_RF_PS_LEVEL_ALWAYS_ASPM BIT(6) // Always enable ASPM and Clock Req in initialization.
162 #define RT_RF_LPS_DISALBE_2R BIT(30) // When LPS is on, disable 2R if no packet is received or transmittd.
163 #define RT_RF_LPS_LEVEL_ASPM BIT(31) // LPS with ASPM
165 #define RT_IN_PS_LEVEL(ppsc, _PS_FLAG) ((ppsc->cur_ps_level & _PS_FLAG) ? _TRUE : _FALSE)
166 #define RT_CLEAR_PS_LEVEL(ppsc, _PS_FLAG) (ppsc->cur_ps_level &= (~(_PS_FLAG)))
167 #define RT_SET_PS_LEVEL(ppsc, _PS_FLAG) (ppsc->cur_ps_level |= _PS_FLAG)
169 // ASPM OSC Control bit, added by Roger, 2013.03.29.
170 #define RT_PCI_ASPM_OSC_IGNORE 0 // PCI ASPM ignore OSC control in default
171 #define RT_PCI_ASPM_OSC_ENABLE BIT0 // PCI ASPM controlled by OS according to ACPI Spec 5.0
172 #define RT_PCI_ASPM_OSC_DISABLE BIT1 // PCI ASPM controlled by driver or BIOS, i.e., force enable ASPM
175 enum _PS_BBRegBackup_ {
183 enum { // for ips_mode
190 // Design for pwrctrl_priv.ips_deny, 32 bits for 32 reasons at most
191 typedef enum _PS_DENY_REASON
193 PS_DENY_DRV_INITIAL = 0,
200 PS_DENY_DRV_REMOVE = 30,
204 #ifdef CONFIG_PNO_SUPPORT
205 typedef struct pno_nlo_info
207 u32 fast_scan_period; //Fast scan period
208 u32 ssid_num; //number of entry
209 u32 slow_scan_period; //slow scan period
210 u32 fast_scan_iterations; //Fast scan iterations
211 u8 ssid_length[MAX_PNO_LIST_COUNT]; //SSID Length Array
212 u8 ssid_cipher_info[MAX_PNO_LIST_COUNT]; //Cipher information for security
213 u8 ssid_channel_info[MAX_PNO_LIST_COUNT]; //channel information
216 typedef struct pno_ssid {
221 typedef struct pno_ssid_list {
222 pno_ssid_t node[MAX_PNO_LIST_COUNT];
225 typedef struct pno_scan_channel_info
230 u8 active; //set 1 means active scan, or pasivite scan.
231 }pno_scan_channel_info_t;
233 typedef struct pno_scan_info
235 u8 enableRFE; //Enable RFE
236 u8 period_scan_time; //exclusive with fast_scan_period and slow_scan_period
237 u8 periodScan; //exclusive with fast_scan_period and slow_scan_period
238 u8 orig_80_offset; //original channel 80 offset
239 u8 orig_40_offset; //original channel 40 offset
240 u8 orig_bw; //original bandwidth
241 u8 orig_ch; //original channel
242 u8 channel_num; //number of channel
243 u64 rfe_type; //rfe_type && 0x00000000000000ff
244 pno_scan_channel_info_t ssid_channel_info[MAX_SCAN_LIST_COUNT];
246 #endif //CONFIG_PNO_SUPPORT
251 _pwrlock check_32k_lock;
252 volatile u8 rpwm; // requested power state for fw
253 volatile u8 cpwm; // fw current power state. updated when 1. read from HCPWM 2. driver lowers power level
254 volatile u8 tog; // toggling
255 volatile u8 cpwm_tog; // toggling
263 _workitem cpwm_event;
264 #ifdef CONFIG_LPS_RPWM_TIMER
266 _workitem rpwmtimeoutwi;
267 _timer pwr_rpwm_timer;
268 #endif // CONFIG_LPS_RPWM_TIMER
269 u8 bpower_saving; //for LPS/IPS
273 u8 reg_pdnmode; //powerdown mode
285 u8 ips_mode_req; // used to accept the mode setting request, will update to ipsmode later
286 uint bips_processing;
287 u32 ips_deny_time; /* will deny IPS when system time is smaller than this */
288 u8 pre_ips_type;// 0: default flow, 1: carddisbale flow
290 // ps_deny: if 0, power save is free to go; otherwise deny all kinds of power save.
291 // Use PS_DENY_REASON to decide reason.
292 // Don't access this variable directly without control function,
293 // and this variable should be protected by lock.
296 u8 ps_processing; /* temporarily used to mark whether in rtw_ps_processor */
298 u8 fw_psmode_iface_id;
303 u8 bFwCurrentInPSMode;
304 u32 DelayLPSLastTimeStamp;
305 s32 pnp_current_pwr_state;
309 u8 bInternalAutoSuspend;
311 #ifdef CONFIG_BT_COEXIST
315 u8 bSupportRemoteWakeup;
316 u8 wowlan_wake_reason;
323 u8 wowlan_pattern_idx;
324 u8 wowlan_pno_enable;
325 #ifdef CONFIG_PNO_SUPPORT
327 pno_nlo_info_t *pnlo_info;
328 pno_scan_info_t *pscan_info;
329 pno_ssid_list_t *pno_ssid_list;
331 u32 wowlan_pattern_context[8][5];
333 #endif // CONFIG_WOWLAN
334 _timer pwr_state_check_timer;
335 int pwr_state_check_interval;
336 u8 pwr_state_check_cnts;
338 int ps_flag; /* used by autosuspend */
340 rt_rf_power_state rf_pwrstate;//cur power state, only for IPS
341 //rt_rf_power_state current_rfpwrstate;
342 rt_rf_power_state change_rfpwrstate;
344 u8 bHWPowerdown; /* power down mode selection. 0:radio off, 1:power down */
345 u8 bHWPwrPindetect; /* come from registrypriv.hwpwrp_detect. enable power down function. 0:disable, 1:enable */
348 unsigned long PS_BBRegBackup[PSBBREG_TOTALCNT];
350 #ifdef CONFIG_RESUME_IN_WORKQUEUE
351 struct workqueue_struct *rtw_workqueue;
352 _workitem resume_work;
355 #ifdef CONFIG_HAS_EARLYSUSPEND
356 struct early_suspend early_suspend;
358 #endif //CONFIG_HAS_EARLYSUSPEND
360 #ifdef CONFIG_ANDROID_POWER
361 android_early_suspend_t early_suspend;
365 #ifdef CONFIG_INTEL_PROXIM
366 u8 stored_power_mgnt;
370 #define rtw_get_ips_mode_req(pwrctl) \
371 (pwrctl)->ips_mode_req
373 #define rtw_ips_mode_req(pwrctl, ips_mode) \
374 (pwrctl)->ips_mode_req = (ips_mode)
376 #define RTW_PWR_STATE_CHK_INTERVAL 2000
378 #define _rtw_set_pwr_state_check_timer(pwrctl, ms) \
380 /*DBG_871X("%s _rtw_set_pwr_state_check_timer(%p, %d)\n", __FUNCTION__, (pwrctl), (ms));*/ \
381 _set_timer(&(pwrctl)->pwr_state_check_timer, (ms)); \
384 #define rtw_set_pwr_state_check_timer(pwrctl) \
385 _rtw_set_pwr_state_check_timer((pwrctl), (pwrctl)->pwr_state_check_interval)
387 extern void rtw_init_pwrctrl_priv(_adapter *adapter);
388 extern void rtw_free_pwrctrl_priv(_adapter * adapter);
390 #ifdef CONFIG_LPS_LCLK
391 s32 rtw_register_task_alive(PADAPTER, u32 task);
392 void rtw_unregister_task_alive(PADAPTER, u32 task);
393 extern s32 rtw_register_tx_alive(PADAPTER padapter);
394 extern void rtw_unregister_tx_alive(PADAPTER padapter);
395 extern s32 rtw_register_rx_alive(PADAPTER padapter);
396 extern void rtw_unregister_rx_alive(PADAPTER padapter);
397 extern s32 rtw_register_cmd_alive(PADAPTER padapter);
398 extern void rtw_unregister_cmd_alive(PADAPTER padapter);
399 extern s32 rtw_register_evt_alive(PADAPTER padapter);
400 extern void rtw_unregister_evt_alive(PADAPTER padapter);
401 extern void cpwm_int_hdl(PADAPTER padapter, struct reportpwrstate_parm *preportpwrstate);
402 extern void LPS_Leave_check(PADAPTER padapter);
405 extern void rtw_set_ps_mode(PADAPTER padapter, u8 ps_mode, u8 smart_ps, u8 bcn_ant_mode, const char *msg);
406 extern void rtw_set_rpwm(_adapter * padapter, u8 val8);
407 extern void LeaveAllPowerSaveMode(PADAPTER Adapter);
408 extern void LeaveAllPowerSaveModeDirect(PADAPTER Adapter);
410 void _ips_enter(_adapter * padapter);
411 void ips_enter(_adapter * padapter);
412 int _ips_leave(_adapter * padapter);
413 int ips_leave(_adapter * padapter);
416 void rtw_ps_processor(_adapter*padapter);
418 #ifdef CONFIG_AUTOSUSPEND
419 int autoresume_enter(_adapter* padapter);
421 #ifdef SUPPORT_HW_RFOFF_DETECTED
422 rt_rf_power_state RfOnOffDetect(IN PADAPTER pAdapter );
426 int rtw_fw_ps_state(PADAPTER padapter);
429 s32 LPS_RF_ON_check(PADAPTER padapter, u32 delay_ms);
430 void LPS_Enter(PADAPTER padapter, const char *msg);
431 void LPS_Leave(PADAPTER padapter, const char *msg);
432 void traffic_check_for_leave_lps(PADAPTER padapter, u8 tx, u32 tx_packets);
435 #ifdef CONFIG_RESUME_IN_WORKQUEUE
436 void rtw_resume_in_workqueue(struct pwrctrl_priv *pwrpriv);
437 #endif //CONFIG_RESUME_IN_WORKQUEUE
439 #if defined(CONFIG_HAS_EARLYSUSPEND ) || defined(CONFIG_ANDROID_POWER)
440 bool rtw_is_earlysuspend_registered(struct pwrctrl_priv *pwrpriv);
441 bool rtw_is_do_late_resume(struct pwrctrl_priv *pwrpriv);
442 void rtw_set_do_late_resume(struct pwrctrl_priv *pwrpriv, bool enable);
443 void rtw_register_early_suspend(struct pwrctrl_priv *pwrpriv);
444 void rtw_unregister_early_suspend(struct pwrctrl_priv *pwrpriv);
446 #define rtw_is_earlysuspend_registered(pwrpriv) _FALSE
447 #define rtw_is_do_late_resume(pwrpriv) _FALSE
448 #define rtw_set_do_late_resume(pwrpriv, enable) do {} while (0)
449 #define rtw_register_early_suspend(pwrpriv) do {} while (0)
450 #define rtw_unregister_early_suspend(pwrpriv) do {} while (0)
451 #endif /* CONFIG_HAS_EARLYSUSPEND || CONFIG_ANDROID_POWER */
453 u8 rtw_interface_ps_func(_adapter *padapter,HAL_INTF_PS_FUNC efunc_id,u8* val);
454 void rtw_set_ips_deny(_adapter *padapter, u32 ms);
455 int _rtw_pwr_wakeup(_adapter *padapter, u32 ips_deffer_ms, const char *caller);
456 #define rtw_pwr_wakeup(adapter) _rtw_pwr_wakeup(adapter, RTW_PWR_STATE_CHK_INTERVAL, __FUNCTION__)
457 #define rtw_pwr_wakeup_ex(adapter, ips_deffer_ms) _rtw_pwr_wakeup(adapter, ips_deffer_ms, __FUNCTION__)
458 int rtw_pm_set_ips(_adapter *padapter, u8 mode);
459 int rtw_pm_set_lps(_adapter *padapter, u8 mode);
461 void rtw_ps_deny(PADAPTER padapter, PS_DENY_REASON reason);
462 void rtw_ps_deny_cancel(PADAPTER padapter, PS_DENY_REASON reason);
463 u32 rtw_ps_deny_get(PADAPTER padapter);
465 #endif //__RTL871X_PWRCTRL_H_