drivers/net/wireless/rockchip_wlan/rtl8723cs/hal/hal_mp.c

   1 /******************************************************************************
   2  *
   3  * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of version 2 of the GNU General Public License as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program; if not, write to the Free Software Foundation, Inc.,
  16  * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  17  *
  18  *
  19  ******************************************************************************/
  20 #define _HAL_MP_C_
  21
  22 #include <drv_types.h>
  23
  24 #ifdef CONFIG_MP_INCLUDED
  25
  26 #ifdef RTW_HALMAC
  27         #include <hal_data.h>           /* struct HAL_DATA_TYPE, RF register definition and etc. */
  28 #else /* !RTW_HALMAC */
  29         #ifdef CONFIG_RTL8188E
  30                 #include <rtl8188e_hal.h>
  31         #endif
  32         #ifdef CONFIG_RTL8723B
  33                 #include <rtl8723b_hal.h>
  34         #endif
  35         #ifdef CONFIG_RTL8192E
  36                 #include <rtl8192e_hal.h>
  37         #endif
  38         #ifdef CONFIG_RTL8814A
  39                 #include <rtl8814a_hal.h>
  40         #endif
  41         #if defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A)
  42                 #include <rtl8812a_hal.h>
  43         #endif
  44         #ifdef CONFIG_RTL8703B
  45                 #include <rtl8703b_hal.h>
  46         #endif
  47         #ifdef CONFIG_RTL8723D
  48                 #include <rtl8723d_hal.h>
  49         #endif
  50         #ifdef CONFIG_RTL8188F
  51                 #include <rtl8188f_hal.h>
  52         #endif
  53 #endif /* !RTW_HALMAC */
  54
  55
  56 u8 MgntQuery_NssTxRate(u16 Rate)
  57 {
  58         u8      NssNum = RF_TX_NUM_NONIMPLEMENT;
  59
  60         if ((Rate >= MGN_MCS8 && Rate <= MGN_MCS15) ||
  61             (Rate >= MGN_VHT2SS_MCS0 && Rate <= MGN_VHT2SS_MCS9))
  62                 NssNum = RF_2TX;
  63         else if ((Rate >= MGN_MCS16 && Rate <= MGN_MCS23) ||
  64                  (Rate >= MGN_VHT3SS_MCS0 && Rate <= MGN_VHT3SS_MCS9))
  65                 NssNum = RF_3TX;
  66         else if ((Rate >= MGN_MCS24 && Rate <= MGN_MCS31) ||
  67                  (Rate >= MGN_VHT4SS_MCS0 && Rate <= MGN_VHT4SS_MCS9))
  68                 NssNum = RF_4TX;
  69         else
  70                 NssNum = RF_1TX;
  71
  72         return NssNum;
  73 }
  74
  75 void hal_mpt_SwitchRfSetting(PADAPTER   pAdapter)
  76 {
  77         HAL_DATA_TYPE           *pHalData = GET_HAL_DATA(pAdapter);
  78         PMPT_CONTEXT            pMptCtx = &(pAdapter->mppriv.mpt_ctx);
  79         u8                              ChannelToSw = pMptCtx->MptChannelToSw;
  80         ULONG                           ulRateIdx = pMptCtx->mpt_rate_index;
  81         ULONG                           ulbandwidth = pMptCtx->MptBandWidth;
  82
  83         /* <20120525, Kordan> Dynamic mechanism for APK, asked by Dennis.*/
  84         if (IS_HARDWARE_TYPE_8188ES(pAdapter) && (1 <= ChannelToSw && ChannelToSw <= 11) &&
  85             (ulRateIdx == MPT_RATE_MCS0 || ulRateIdx == MPT_RATE_1M || ulRateIdx == MPT_RATE_6M)) {
  86                 pMptCtx->backup0x52_RF_A = (u1Byte)phy_query_rf_reg(pAdapter, ODM_RF_PATH_A, RF_0x52, 0x000F0);
  87                 pMptCtx->backup0x52_RF_B = (u1Byte)phy_query_rf_reg(pAdapter, ODM_RF_PATH_B, RF_0x52, 0x000F0);
  88
  89                 if ((PlatformEFIORead4Byte(pAdapter, 0xF4) & BIT29) == BIT29) {
  90                         phy_set_rf_reg(pAdapter, ODM_RF_PATH_A, RF_0x52, 0x000F0, 0xB);
  91                         phy_set_rf_reg(pAdapter, ODM_RF_PATH_B, RF_0x52, 0x000F0, 0xB);
  92                 } else {
  93                         phy_set_rf_reg(pAdapter, ODM_RF_PATH_A, RF_0x52, 0x000F0, 0xD);
  94                         phy_set_rf_reg(pAdapter, ODM_RF_PATH_B, RF_0x52, 0x000F0, 0xD);
  95                 }
  96         } else if (IS_HARDWARE_TYPE_8188EE(pAdapter)) { /* <20140903, VincentL> Asked by RF Eason and Edlu*/
  97                 if (ChannelToSw == 3 && ulbandwidth == MPT_BW_40MHZ) {
  98                         phy_set_rf_reg(pAdapter, ODM_RF_PATH_A, RF_0x52, 0x000F0, 0xB); /*RF 0x52 = 0x0007E4BD*/
  99                         phy_set_rf_reg(pAdapter, ODM_RF_PATH_B, RF_0x52, 0x000F0, 0xB); /*RF 0x52 = 0x0007E4BD*/
 100                 } else {
 101                         phy_set_rf_reg(pAdapter, ODM_RF_PATH_A, RF_0x52, 0x000F0, 0x9); /*RF 0x52 = 0x0007E49D*/
 102                         phy_set_rf_reg(pAdapter, ODM_RF_PATH_B, RF_0x52, 0x000F0, 0x9); /*RF 0x52 = 0x0007E49D*/
 103                 }
 104         } else if (IS_HARDWARE_TYPE_8188E(pAdapter)) {
 105                 phy_set_rf_reg(pAdapter, ODM_RF_PATH_A, RF_0x52, 0x000F0, pMptCtx->backup0x52_RF_A);
 106                 phy_set_rf_reg(pAdapter, ODM_RF_PATH_B, RF_0x52, 0x000F0, pMptCtx->backup0x52_RF_B);
 107         }
 108 }
 109
 110 s32 hal_mpt_SetPowerTracking(PADAPTER padapter, u8 enable)
 111 {
 112         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(padapter);
 113         struct PHY_DM_STRUCT            *pDM_Odm = &(pHalData->odmpriv);
 114
 115
 116         if (!netif_running(padapter->pnetdev)) {
 117                 return _FAIL;
 118         }
 119
 120         if (check_fwstate(&padapter->mlmepriv, WIFI_MP_STATE) == _FALSE) {
 121                 return _FAIL;
 122         }
 123         if (enable)
 124                 pDM_Odm->rf_calibrate_info.txpowertrack_control = _TRUE;
 125         else
 126                 pDM_Odm->rf_calibrate_info.txpowertrack_control = _FALSE;
 127
 128         return _SUCCESS;
 129 }
 130
 131 void hal_mpt_GetPowerTracking(PADAPTER padapter, u8 *enable)
 132 {
 133         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(padapter);
 134         struct PHY_DM_STRUCT            *pDM_Odm = &(pHalData->odmpriv);
 135
 136
 137         *enable = pDM_Odm->rf_calibrate_info.txpowertrack_control;
 138 }
 139
 140
 141 void hal_mpt_CCKTxPowerAdjust(PADAPTER Adapter, BOOLEAN bInCH14)
 142 {
 143         u32             TempVal = 0, TempVal2 = 0, TempVal3 = 0;
 144         u32             CurrCCKSwingVal = 0, CCKSwingIndex = 12;
 145         u8              i;
 146         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(Adapter);
 147         PMPT_CONTEXT            pMptCtx = &(Adapter->mppriv.mpt_ctx);
 148         u1Byte                          u1Channel = pHalData->current_channel;
 149         ULONG                           ulRateIdx = pMptCtx->mpt_rate_index;
 150         u1Byte                          DataRate = 0xFF;
 151
 152         /* Do not modify CCK TX filter parameters for 8822B*/
 153         if(IS_HARDWARE_TYPE_8822B(Adapter) || IS_HARDWARE_TYPE_8821C(Adapter) || IS_HARDWARE_TYPE_8723D(Adapter))
 154                 return;
 155
 156         DataRate = mpt_to_mgnt_rate(ulRateIdx);
 157
 158         if (u1Channel == 14 && IS_CCK_RATE(DataRate))
 159                 pHalData->bCCKinCH14 = TRUE;
 160         else
 161                 pHalData->bCCKinCH14 = FALSE;
 162
 163         if (IS_HARDWARE_TYPE_8703B(Adapter)) {
 164                 if ((u1Channel == 14) && IS_CCK_RATE(DataRate)) {
 165                         /* Channel 14 in CCK, need to set 0xA26~0xA29 to 0 for 8703B */
 166                         phy_set_bb_reg(Adapter, rCCK0_TxFilter2, bMaskHWord, 0);
 167                         phy_set_bb_reg(Adapter, rCCK0_DebugPort, bMaskLWord, 0);
 168
 169                 } else {
 170                         /* Normal setting for 8703B, just recover to the default setting. */
 171                         /* This hardcore values reference from the parameter which BB team gave. */
 172                         for (i = 0 ; i < 2 ; ++i)
 173                                 phy_set_bb_reg(Adapter, pHalData->RegForRecover[i].offset, bMaskDWord, pHalData->RegForRecover[i].value);
 174
 175                 }
 176         } else if (IS_HARDWARE_TYPE_8723D(Adapter)) {
 177                 /* 2.4G CCK TX DFIR */
 178                 /* 2016.01.20 Suggest from RS BB mingzhi*/
 179                 if ((u1Channel == 14)) {
 180                         phy_set_bb_reg(Adapter, rCCK0_TxFilter2, bMaskDWord, 0x0000B81C);
 181                         phy_set_bb_reg(Adapter, rCCK0_DebugPort, bMaskDWord, 0x00000000);
 182                         phy_set_bb_reg(Adapter, 0xAAC, bMaskDWord, 0x00003667);
 183                 } else {
 184                         for (i = 0 ; i < 3 ; ++i) {
 185                                 phy_set_bb_reg(Adapter,
 186                                              pHalData->RegForRecover[i].offset,
 187                                              bMaskDWord,
 188                                              pHalData->RegForRecover[i].value);
 189                         }
 190                 }
 191         } else if (IS_HARDWARE_TYPE_8188F(Adapter)) {
 192                 /* get current cck swing value and check 0xa22 & 0xa23 later to match the table.*/
 193                 CurrCCKSwingVal = read_bbreg(Adapter, rCCK0_TxFilter1, bMaskHWord);
 194                 CCKSwingIndex = 20; /* default index */
 195
 196                 if (!pHalData->bCCKinCH14) {
 197                         /* Readback the current bb cck swing value and compare with the table to */
 198                         /* get the current swing index */
 199                         for (i = 0; i < CCK_TABLE_SIZE_88F; i++) {
 200                                 if (((CurrCCKSwingVal & 0xff) == (u32)cck_swing_table_ch1_ch13_88f[i][0]) &&
 201                                     (((CurrCCKSwingVal & 0xff00) >> 8) == (u32)cck_swing_table_ch1_ch13_88f[i][1])) {
 202                                         CCKSwingIndex = i;
 203                                         break;
 204                                 }
 205                         }
 206                         write_bbreg(Adapter, 0xa22, bMaskByte0, cck_swing_table_ch1_ch13_88f[CCKSwingIndex][0]);
 207                         write_bbreg(Adapter, 0xa23, bMaskByte0, cck_swing_table_ch1_ch13_88f[CCKSwingIndex][1]);
 208                         write_bbreg(Adapter, 0xa24, bMaskByte0, cck_swing_table_ch1_ch13_88f[CCKSwingIndex][2]);
 209                         write_bbreg(Adapter, 0xa25, bMaskByte0, cck_swing_table_ch1_ch13_88f[CCKSwingIndex][3]);
 210                         write_bbreg(Adapter, 0xa26, bMaskByte0, cck_swing_table_ch1_ch13_88f[CCKSwingIndex][4]);
 211                         write_bbreg(Adapter, 0xa27, bMaskByte0, cck_swing_table_ch1_ch13_88f[CCKSwingIndex][5]);
 212                         write_bbreg(Adapter, 0xa28, bMaskByte0, cck_swing_table_ch1_ch13_88f[CCKSwingIndex][6]);
 213                         write_bbreg(Adapter, 0xa29, bMaskByte0, cck_swing_table_ch1_ch13_88f[CCKSwingIndex][7]);
 214                         write_bbreg(Adapter, 0xa9a, bMaskByte0, cck_swing_table_ch1_ch13_88f[CCKSwingIndex][8]);
 215                         write_bbreg(Adapter, 0xa9b, bMaskByte0, cck_swing_table_ch1_ch13_88f[CCKSwingIndex][9]);
 216                         write_bbreg(Adapter, 0xa9c, bMaskByte0, cck_swing_table_ch1_ch13_88f[CCKSwingIndex][10]);
 217                         write_bbreg(Adapter, 0xa9d, bMaskByte0, cck_swing_table_ch1_ch13_88f[CCKSwingIndex][11]);
 218                         write_bbreg(Adapter, 0xaa0, bMaskByte0, cck_swing_table_ch1_ch13_88f[CCKSwingIndex][12]);
 219                         write_bbreg(Adapter, 0xaa1, bMaskByte0, cck_swing_table_ch1_ch13_88f[CCKSwingIndex][13]);
 220                         write_bbreg(Adapter, 0xaa2, bMaskByte0, cck_swing_table_ch1_ch13_88f[CCKSwingIndex][14]);
 221                         write_bbreg(Adapter, 0xaa3, bMaskByte0, cck_swing_table_ch1_ch13_88f[CCKSwingIndex][15]);
 222                         RTW_INFO("%s , cck_swing_table_ch1_ch13_88f[%d]\n", __func__, CCKSwingIndex);
 223                 }  else {
 224                         for (i = 0; i < CCK_TABLE_SIZE_88F; i++) {
 225                                 if (((CurrCCKSwingVal & 0xff) == (u32)cck_swing_table_ch14_88f[i][0]) &&
 226                                     (((CurrCCKSwingVal & 0xff00) >> 8) == (u32)cck_swing_table_ch14_88f[i][1])) {
 227                                         CCKSwingIndex = i;
 228                                         break;
 229                                 }
 230                         }
 231                         write_bbreg(Adapter, 0xa22, bMaskByte0, cck_swing_table_ch14_88f[CCKSwingIndex][0]);
 232                         write_bbreg(Adapter, 0xa23, bMaskByte0, cck_swing_table_ch14_88f[CCKSwingIndex][1]);
 233                         write_bbreg(Adapter, 0xa24, bMaskByte0, cck_swing_table_ch14_88f[CCKSwingIndex][2]);
 234                         write_bbreg(Adapter, 0xa25, bMaskByte0, cck_swing_table_ch14_88f[CCKSwingIndex][3]);
 235                         write_bbreg(Adapter, 0xa26, bMaskByte0, cck_swing_table_ch14_88f[CCKSwingIndex][4]);
 236                         write_bbreg(Adapter, 0xa27, bMaskByte0, cck_swing_table_ch14_88f[CCKSwingIndex][5]);
 237                         write_bbreg(Adapter, 0xa28, bMaskByte0, cck_swing_table_ch14_88f[CCKSwingIndex][6]);
 238                         write_bbreg(Adapter, 0xa29, bMaskByte0, cck_swing_table_ch14_88f[CCKSwingIndex][7]);
 239                         write_bbreg(Adapter, 0xa9a, bMaskByte0, cck_swing_table_ch14_88f[CCKSwingIndex][8]);
 240                         write_bbreg(Adapter, 0xa9b, bMaskByte0, cck_swing_table_ch14_88f[CCKSwingIndex][9]);
 241                         write_bbreg(Adapter, 0xa9c, bMaskByte0, cck_swing_table_ch14_88f[CCKSwingIndex][10]);
 242                         write_bbreg(Adapter, 0xa9d, bMaskByte0, cck_swing_table_ch14_88f[CCKSwingIndex][11]);
 243                         write_bbreg(Adapter, 0xaa0, bMaskByte0, cck_swing_table_ch14_88f[CCKSwingIndex][12]);
 244                         write_bbreg(Adapter, 0xaa1, bMaskByte0, cck_swing_table_ch14_88f[CCKSwingIndex][13]);
 245                         write_bbreg(Adapter, 0xaa2, bMaskByte0, cck_swing_table_ch14_88f[CCKSwingIndex][14]);
 246                         write_bbreg(Adapter, 0xaa3, bMaskByte0, cck_swing_table_ch14_88f[CCKSwingIndex][15]);
 247                         RTW_INFO("%s , cck_swing_table_ch14_88f[%d]\n", __func__, CCKSwingIndex);
 248                 }
 249         } else {
 250
 251                 /* get current cck swing value and check 0xa22 & 0xa23 later to match the table.*/
 252                 CurrCCKSwingVal = read_bbreg(Adapter, rCCK0_TxFilter1, bMaskHWord);
 253
 254                 if (!pHalData->bCCKinCH14) {
 255                         /* Readback the current bb cck swing value and compare with the table to */
 256                         /* get the current swing index */
 257                         for (i = 0; i < CCK_TABLE_SIZE; i++) {
 258                                 if (((CurrCCKSwingVal & 0xff) == (u32)cck_swing_table_ch1_ch13[i][0]) &&
 259                                     (((CurrCCKSwingVal & 0xff00) >> 8) == (u32)cck_swing_table_ch1_ch13[i][1])) {
 260                                         CCKSwingIndex = i;
 261                                         break;
 262                                 }
 263                         }
 264
 265                         /*Write 0xa22 0xa23*/
 266                         TempVal = cck_swing_table_ch1_ch13[CCKSwingIndex][0] +
 267                                 (cck_swing_table_ch1_ch13[CCKSwingIndex][1] << 8);
 268
 269
 270                         /*Write 0xa24 ~ 0xa27*/
 271                         TempVal2 = 0;
 272                         TempVal2 = cck_swing_table_ch1_ch13[CCKSwingIndex][2] +
 273                                 (cck_swing_table_ch1_ch13[CCKSwingIndex][3] << 8) +
 274                                 (cck_swing_table_ch1_ch13[CCKSwingIndex][4] << 16) +
 275                                 (cck_swing_table_ch1_ch13[CCKSwingIndex][5] << 24);
 276
 277                         /*Write 0xa28  0xa29*/
 278                         TempVal3 = 0;
 279                         TempVal3 = cck_swing_table_ch1_ch13[CCKSwingIndex][6] +
 280                                 (cck_swing_table_ch1_ch13[CCKSwingIndex][7] << 8);
 281                 }  else {
 282                         for (i = 0; i < CCK_TABLE_SIZE; i++) {
 283                                 if (((CurrCCKSwingVal & 0xff) == (u32)cck_swing_table_ch14[i][0]) &&
 284                                     (((CurrCCKSwingVal & 0xff00) >> 8) == (u32)cck_swing_table_ch14[i][1])) {
 285                                         CCKSwingIndex = i;
 286                                         break;
 287                                 }
 288                         }
 289
 290                         /*Write 0xa22 0xa23*/
 291                         TempVal = cck_swing_table_ch14[CCKSwingIndex][0] +
 292                                   (cck_swing_table_ch14[CCKSwingIndex][1] << 8);
 293
 294                         /*Write 0xa24 ~ 0xa27*/
 295                         TempVal2 = 0;
 296                         TempVal2 = cck_swing_table_ch14[CCKSwingIndex][2] +
 297                                    (cck_swing_table_ch14[CCKSwingIndex][3] << 8) +
 298                                 (cck_swing_table_ch14[CCKSwingIndex][4] << 16) +
 299                                    (cck_swing_table_ch14[CCKSwingIndex][5] << 24);
 300
 301                         /*Write 0xa28  0xa29*/
 302                         TempVal3 = 0;
 303                         TempVal3 = cck_swing_table_ch14[CCKSwingIndex][6] +
 304                                    (cck_swing_table_ch14[CCKSwingIndex][7] << 8);
 305                 }
 306
 307                 write_bbreg(Adapter, rCCK0_TxFilter1, bMaskHWord, TempVal);
 308                 write_bbreg(Adapter, rCCK0_TxFilter2, bMaskDWord, TempVal2);
 309                 write_bbreg(Adapter, rCCK0_DebugPort, bMaskLWord, TempVal3);
 310         }
 311
 312 }
 313
 314 void hal_mpt_SetChannel(PADAPTER pAdapter)
 315 {
 316         u8 eRFPath;
 317         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(pAdapter);
 318         struct PHY_DM_STRUCT            *pDM_Odm = &(pHalData->odmpriv);
 319         struct mp_priv  *pmp = &pAdapter->mppriv;
 320         u8              channel = pmp->channel;
 321         u8              bandwidth = pmp->bandwidth;
 322
 323         hal_mpt_SwitchRfSetting(pAdapter);
 324
 325         pHalData->bSwChnl = _TRUE;
 326         pHalData->bSetChnlBW = _TRUE;
 327         rtw_hal_set_chnl_bw(pAdapter, channel, bandwidth, 0, 0);
 328
 329         hal_mpt_CCKTxPowerAdjust(pAdapter, pHalData->bCCKinCH14);
 330
 331 }
 332
 333 /*
 334  * Notice
 335  *      Switch bandwitdth may change center frequency(channel)
 336  */
 337 void hal_mpt_SetBandwidth(PADAPTER pAdapter)
 338 {
 339         struct mp_priv *pmp = &pAdapter->mppriv;
 340         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(pAdapter);
 341
 342         u8              channel = pmp->channel;
 343         u8              bandwidth = pmp->bandwidth;
 344
 345         pHalData->bSwChnl = _TRUE;
 346         pHalData->bSetChnlBW = _TRUE;
 347         rtw_hal_set_chnl_bw(pAdapter, channel, bandwidth, 0, 0);
 348
 349         hal_mpt_SwitchRfSetting(pAdapter);
 350 }
 351
 352 void mpt_SetTxPower_Old(PADAPTER pAdapter, MPT_TXPWR_DEF Rate, u8 *pTxPower)
 353 {
 354         switch (Rate) {
 355         case MPT_CCK: {
 356                 u4Byte  TxAGC = 0, pwr = 0;
 357                 u1Byte  rf;
 358
 359                 pwr = pTxPower[ODM_RF_PATH_A];
 360                 if (pwr < 0x3f) {
 361                         TxAGC = (pwr << 16) | (pwr << 8) | (pwr);
 362                         phy_set_bb_reg(pAdapter, rTxAGC_A_CCK1_Mcs32, bMaskByte1, pTxPower[ODM_RF_PATH_A]);
 363                         phy_set_bb_reg(pAdapter, rTxAGC_B_CCK11_A_CCK2_11, 0xffffff00, TxAGC);
 364                 }
 365                 pwr = pTxPower[ODM_RF_PATH_B];
 366                 if (pwr < 0x3f) {
 367                         TxAGC = (pwr << 16) | (pwr << 8) | (pwr);
 368                         phy_set_bb_reg(pAdapter, rTxAGC_B_CCK11_A_CCK2_11, bMaskByte0, pTxPower[ODM_RF_PATH_B]);
 369                         phy_set_bb_reg(pAdapter, rTxAGC_B_CCK1_55_Mcs32, 0xffffff00, TxAGC);
 370                 }
 371         }
 372         break;
 373
 374         case MPT_OFDM_AND_HT: {
 375                 u4Byte  TxAGC = 0;
 376                 u1Byte  pwr = 0, rf;
 377
 378                 pwr = pTxPower[0];
 379                 if (pwr < 0x3f) {
 380                         TxAGC |= ((pwr << 24) | (pwr << 16) | (pwr << 8) | pwr);
 381                         RTW_INFO("HT Tx-rf(A) Power = 0x%x\n", TxAGC);
 382                         phy_set_bb_reg(pAdapter, rTxAGC_A_Rate18_06, bMaskDWord, TxAGC);
 383                         phy_set_bb_reg(pAdapter, rTxAGC_A_Rate54_24, bMaskDWord, TxAGC);
 384                         phy_set_bb_reg(pAdapter, rTxAGC_A_Mcs03_Mcs00, bMaskDWord, TxAGC);
 385                         phy_set_bb_reg(pAdapter, rTxAGC_A_Mcs07_Mcs04, bMaskDWord, TxAGC);
 386                         phy_set_bb_reg(pAdapter, rTxAGC_A_Mcs11_Mcs08, bMaskDWord, TxAGC);
 387                         phy_set_bb_reg(pAdapter, rTxAGC_A_Mcs15_Mcs12, bMaskDWord, TxAGC);
 388                 }
 389                 TxAGC = 0;
 390                 pwr = pTxPower[1];
 391                 if (pwr < 0x3f) {
 392                         TxAGC |= ((pwr << 24) | (pwr << 16) | (pwr << 8) | pwr);
 393                         RTW_INFO("HT Tx-rf(B) Power = 0x%x\n", TxAGC);
 394                         phy_set_bb_reg(pAdapter, rTxAGC_B_Rate18_06, bMaskDWord, TxAGC);
 395                         phy_set_bb_reg(pAdapter, rTxAGC_B_Rate54_24, bMaskDWord, TxAGC);
 396                         phy_set_bb_reg(pAdapter, rTxAGC_B_Mcs03_Mcs00, bMaskDWord, TxAGC);
 397                         phy_set_bb_reg(pAdapter, rTxAGC_B_Mcs07_Mcs04, bMaskDWord, TxAGC);
 398                         phy_set_bb_reg(pAdapter, rTxAGC_B_Mcs11_Mcs08, bMaskDWord, TxAGC);
 399                         phy_set_bb_reg(pAdapter, rTxAGC_B_Mcs15_Mcs12, bMaskDWord, TxAGC);
 400                 }
 401         }
 402         break;
 403
 404         default:
 405                 break;
 406         }
 407         RTW_INFO("<===mpt_SetTxPower_Old()\n");
 408 }
 409
 410 void
 411 mpt_SetTxPower(
 412         PADAPTER                pAdapter,
 413         MPT_TXPWR_DEF   Rate,
 414         pu1Byte pTxPower
 415 )
 416 {
 417         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(pAdapter);
 418
 419         u1Byte path = 0 , i = 0, MaxRate = MGN_6M;
 420         u1Byte StartPath = ODM_RF_PATH_A, EndPath = ODM_RF_PATH_B;
 421
 422         if (IS_HARDWARE_TYPE_8814A(pAdapter))
 423                 EndPath = ODM_RF_PATH_D;
 424         else if (IS_HARDWARE_TYPE_8188F(pAdapter) || IS_HARDWARE_TYPE_8723D(pAdapter) || IS_HARDWARE_TYPE_8821C(pAdapter))
 425                 EndPath = ODM_RF_PATH_A;
 426
 427         switch (Rate) {
 428         case MPT_CCK: {
 429                 u1Byte rate[] = {MGN_1M, MGN_2M, MGN_5_5M, MGN_11M};
 430
 431                 for (path = StartPath; path <= EndPath; path++)
 432                         for (i = 0; i < sizeof(rate); ++i)
 433                                 PHY_SetTxPowerIndex(pAdapter, pTxPower[path], path, rate[i]);
 434         }
 435         break;
 436         case MPT_OFDM: {
 437                 u1Byte rate[] = {
 438                         MGN_6M, MGN_9M, MGN_12M, MGN_18M,
 439                         MGN_24M, MGN_36M, MGN_48M, MGN_54M,
 440                 };
 441
 442                 for (path = StartPath; path <= EndPath; path++)
 443                         for (i = 0; i < sizeof(rate); ++i)
 444                                 PHY_SetTxPowerIndex(pAdapter, pTxPower[path], path, rate[i]);
 445         }
 446         break;
 447         case MPT_HT: {
 448                 u1Byte rate[] = {
 449                         MGN_MCS0, MGN_MCS1, MGN_MCS2, MGN_MCS3, MGN_MCS4,
 450                         MGN_MCS5, MGN_MCS6, MGN_MCS7, MGN_MCS8, MGN_MCS9,
 451                         MGN_MCS10, MGN_MCS11, MGN_MCS12, MGN_MCS13, MGN_MCS14,
 452                         MGN_MCS15, MGN_MCS16, MGN_MCS17, MGN_MCS18, MGN_MCS19,
 453                         MGN_MCS20, MGN_MCS21, MGN_MCS22, MGN_MCS23, MGN_MCS24,
 454                         MGN_MCS25, MGN_MCS26, MGN_MCS27, MGN_MCS28, MGN_MCS29,
 455                         MGN_MCS30, MGN_MCS31,
 456                 };
 457                 if (pHalData->rf_type == RF_3T3R)
 458                         MaxRate = MGN_MCS23;
 459                 else if (pHalData->rf_type == RF_2T2R)
 460                         MaxRate = MGN_MCS15;
 461                 else
 462                         MaxRate = MGN_MCS7;
 463                 for (path = StartPath; path <= EndPath; path++) {
 464                         for (i = 0; i < sizeof(rate); ++i) {
 465                                 if (rate[i] > MaxRate)
 466                                         break;
 467                                 PHY_SetTxPowerIndex(pAdapter, pTxPower[path], path, rate[i]);
 468                         }
 469                 }
 470         }
 471         break;
 472         case MPT_VHT: {
 473                 u1Byte rate[] = {
 474                         MGN_VHT1SS_MCS0, MGN_VHT1SS_MCS1, MGN_VHT1SS_MCS2, MGN_VHT1SS_MCS3, MGN_VHT1SS_MCS4,
 475                         MGN_VHT1SS_MCS5, MGN_VHT1SS_MCS6, MGN_VHT1SS_MCS7, MGN_VHT1SS_MCS8, MGN_VHT1SS_MCS9,
 476                         MGN_VHT2SS_MCS0, MGN_VHT2SS_MCS1, MGN_VHT2SS_MCS2, MGN_VHT2SS_MCS3, MGN_VHT2SS_MCS4,
 477                         MGN_VHT2SS_MCS5, MGN_VHT2SS_MCS6, MGN_VHT2SS_MCS7, MGN_VHT2SS_MCS8, MGN_VHT2SS_MCS9,
 478                         MGN_VHT3SS_MCS0, MGN_VHT3SS_MCS1, MGN_VHT3SS_MCS2, MGN_VHT3SS_MCS3, MGN_VHT3SS_MCS4,
 479                         MGN_VHT3SS_MCS5, MGN_VHT3SS_MCS6, MGN_VHT3SS_MCS7, MGN_VHT3SS_MCS8, MGN_VHT3SS_MCS9,
 480                         MGN_VHT4SS_MCS0, MGN_VHT4SS_MCS1, MGN_VHT4SS_MCS2, MGN_VHT4SS_MCS3, MGN_VHT4SS_MCS4,
 481                         MGN_VHT4SS_MCS5, MGN_VHT4SS_MCS6, MGN_VHT4SS_MCS7, MGN_VHT4SS_MCS8, MGN_VHT4SS_MCS9,
 482                 };
 483                 if (pHalData->rf_type == RF_3T3R)
 484                         MaxRate = MGN_VHT3SS_MCS9;
 485                 else if (pHalData->rf_type == RF_2T2R || pHalData->rf_type == RF_2T4R)
 486                         MaxRate = MGN_VHT2SS_MCS9;
 487                 else
 488                         MaxRate = MGN_VHT1SS_MCS9;
 489
 490                 for (path = StartPath; path <= EndPath; path++) {
 491                         for (i = 0; i < sizeof(rate); ++i) {
 492                                 if (rate[i] > MaxRate)
 493                                         break;
 494                                 PHY_SetTxPowerIndex(pAdapter, pTxPower[path], path, rate[i]);
 495                         }
 496                 }
 497         }
 498         break;
 499         default:
 500                 RTW_INFO("<===mpt_SetTxPower: Illegal channel!!\n");
 501                 break;
 502         }
 503 }
 504
 505 void hal_mpt_SetTxPower(PADAPTER pAdapter)
 506 {
 507         HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
 508         PMPT_CONTEXT            pMptCtx = &(pAdapter->mppriv.mpt_ctx);
 509         struct PHY_DM_STRUCT            *pDM_Odm = &pHalData->odmpriv;
 510
 511         if (pHalData->rf_chip < RF_TYPE_MAX) {
 512                 if (IS_HARDWARE_TYPE_8188E(pAdapter) ||
 513                     IS_HARDWARE_TYPE_8723B(pAdapter) ||
 514                     IS_HARDWARE_TYPE_8192E(pAdapter) ||
 515                     IS_HARDWARE_TYPE_8703B(pAdapter) ||
 516                     IS_HARDWARE_TYPE_8188F(pAdapter)) {
 517                         u8 path = (pHalData->antenna_tx_path == ANTENNA_A) ? (ODM_RF_PATH_A) : (ODM_RF_PATH_B);
 518
 519                         RTW_INFO("===> MPT_ProSetTxPower: Old\n");
 520
 521                         mpt_SetTxPower_Old(pAdapter, MPT_CCK, pMptCtx->TxPwrLevel);
 522                         mpt_SetTxPower_Old(pAdapter, MPT_OFDM_AND_HT, pMptCtx->TxPwrLevel);
 523
 524                 } else {
 525                         RTW_INFO("===> MPT_ProSetTxPower: Jaguar/Jaguar2\n");
 526                         mpt_SetTxPower(pAdapter, MPT_CCK, pMptCtx->TxPwrLevel);
 527                         mpt_SetTxPower(pAdapter, MPT_OFDM, pMptCtx->TxPwrLevel);
 528                         mpt_SetTxPower(pAdapter, MPT_HT, pMptCtx->TxPwrLevel);
 529                         mpt_SetTxPower(pAdapter, MPT_VHT, pMptCtx->TxPwrLevel);
 530
 531                 }
 532         } else
 533                 RTW_INFO("RFChipID < RF_TYPE_MAX, the RF chip is not supported - %d\n", pHalData->rf_chip);
 534
 535         odm_clear_txpowertracking_state(pDM_Odm);
 536 }
 537
 538 void hal_mpt_SetDataRate(PADAPTER pAdapter)
 539 {
 540         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(pAdapter);
 541         PMPT_CONTEXT            pMptCtx = &(pAdapter->mppriv.mpt_ctx);
 542         u32 DataRate;
 543
 544         DataRate = mpt_to_mgnt_rate(pMptCtx->mpt_rate_index);
 545
 546         hal_mpt_SwitchRfSetting(pAdapter);
 547
 548         hal_mpt_CCKTxPowerAdjust(pAdapter, pHalData->bCCKinCH14);
 549 #ifdef CONFIG_RTL8723B
 550         if (IS_HARDWARE_TYPE_8723B(pAdapter) || IS_HARDWARE_TYPE_8188F(pAdapter)) {
 551                 if (IS_CCK_RATE(DataRate)) {
 552                         if (pMptCtx->mpt_rf_path == ODM_RF_PATH_A)
 553                                 phy_set_rf_reg(pAdapter, ODM_RF_PATH_A, 0x51, 0xF, 0x6);
 554                         else
 555                                 phy_set_rf_reg(pAdapter, ODM_RF_PATH_A, 0x71, 0xF, 0x6);
 556                 } else {
 557                         if (pMptCtx->mpt_rf_path == ODM_RF_PATH_A)
 558                                 phy_set_rf_reg(pAdapter, ODM_RF_PATH_A, 0x51, 0xF, 0xE);
 559                         else
 560                                 phy_set_rf_reg(pAdapter, ODM_RF_PATH_A, 0x71, 0xF, 0xE);
 561                 }
 562         }
 563
 564         if ((IS_HARDWARE_TYPE_8723BS(pAdapter) &&
 565              ((pHalData->PackageType == PACKAGE_TFBGA79) || (pHalData->PackageType == PACKAGE_TFBGA90)))) {
 566                 if (pMptCtx->mpt_rf_path == ODM_RF_PATH_A)
 567                         phy_set_rf_reg(pAdapter, ODM_RF_PATH_A, 0x51, 0xF, 0xE);
 568                 else
 569                         phy_set_rf_reg(pAdapter, ODM_RF_PATH_A, 0x71, 0xF, 0xE);
 570         }
 571 #endif
 572 }
 573
 574 #define RF_PATH_AB      22
 575
 576 #ifdef CONFIG_RTL8814A
 577 VOID mpt_ToggleIG_8814A(PADAPTER        pAdapter)
 578 {
 579         u1Byte Path = 0;
 580         u4Byte IGReg = rA_IGI_Jaguar, IGvalue = 0;
 581
 582         for (Path; Path <= ODM_RF_PATH_D; Path++) {
 583                 switch (Path) {
 584                 case ODM_RF_PATH_B:
 585                         IGReg = rB_IGI_Jaguar;
 586                         break;
 587                 case ODM_RF_PATH_C:
 588                         IGReg = rC_IGI_Jaguar2;
 589                         break;
 590                 case ODM_RF_PATH_D:
 591                         IGReg = rD_IGI_Jaguar2;
 592                         break;
 593                 default:
 594                         IGReg = rA_IGI_Jaguar;
 595                         break;
 596                 }
 597
 598                 IGvalue = phy_query_bb_reg(pAdapter, IGReg, bMaskByte0);
 599                 phy_set_bb_reg(pAdapter, IGReg, bMaskByte0, IGvalue + 2);
 600                 phy_set_bb_reg(pAdapter, IGReg, bMaskByte0, IGvalue);
 601         }
 602 }
 603
 604 VOID mpt_SetRFPath_8814A(PADAPTER       pAdapter)
 605 {
 606
 607         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(pAdapter);
 608         PMPT_CONTEXT    pMptCtx = &pAdapter->mppriv.mpt_ctx;
 609         R_ANTENNA_SELECT_OFDM   *p_ofdm_tx;     /* OFDM Tx register */
 610         R_ANTENNA_SELECT_CCK    *p_cck_txrx;
 611         u8      ForcedDataRate = mpt_to_mgnt_rate(pMptCtx->mpt_rate_index);
 612         u8      HtStbcCap = pAdapter->registrypriv.stbc_cap;
 613         /*/PRT_HIGH_THROUGHPUT          pHTInfo = GET_HT_INFO(pMgntInfo);*/
 614         /*/PRT_VERY_HIGH_THROUGHPUT     pVHTInfo = GET_VHT_INFO(pMgntInfo);*/
 615
 616         u32     ulAntennaTx = pHalData->antenna_tx_path;
 617         u32     ulAntennaRx = pHalData->AntennaRxPath;
 618         u8      NssforRate = MgntQuery_NssTxRate(ForcedDataRate);
 619
 620         if ((NssforRate == RF_2TX) || ((NssforRate == RF_1TX) && IS_HT_RATE(ForcedDataRate)) || ((NssforRate == RF_1TX) && IS_VHT_RATE(ForcedDataRate))) {
 621                 RTW_INFO("===> SetAntenna 2T ForcedDataRate %d NssforRate %d AntennaTx %d\n", ForcedDataRate, NssforRate, ulAntennaTx);
 622
 623                 switch (ulAntennaTx) {
 624                 case ANTENNA_BC:
 625                         pMptCtx->mpt_rf_path = ODM_RF_PATH_BC;
 626                         /*pHalData->ValidTxPath = 0x06; linux no use */
 627                         phy_set_bb_reg(pAdapter, rTxAnt_23Nsts_Jaguar2, 0x0000fff0, 0x106);     /*/ 0x940[15:4]=12'b0000_0100_0011*/
 628                         break;
 629
 630                 case ANTENNA_CD:
 631                         pMptCtx->mpt_rf_path = ODM_RF_PATH_CD;
 632                         /*pHalData->ValidTxPath = 0x0C;*/
 633                         phy_set_bb_reg(pAdapter, rTxAnt_23Nsts_Jaguar2, 0x0000fff0, 0x40c);     /*/ 0x940[15:4]=12'b0000_0100_0011*/
 634                         break;
 635                 case ANTENNA_AB:
 636                 default:
 637                         pMptCtx->mpt_rf_path = ODM_RF_PATH_AB;
 638                         /*pHalData->ValidTxPath = 0x03;*/
 639                         phy_set_bb_reg(pAdapter, rTxAnt_23Nsts_Jaguar2, 0x0000fff0, 0x043);     /*/ 0x940[15:4]=12'b0000_0100_0011*/
 640                         break;
 641                 }
 642
 643         } else if (NssforRate == RF_3TX) {
 644                 RTW_INFO("===> SetAntenna 3T ForcedDataRate %d NssforRate %d AntennaTx %d\n", ForcedDataRate, NssforRate, ulAntennaTx);
 645
 646                 switch (ulAntennaTx) {
 647                 case ANTENNA_BCD:
 648                         pMptCtx->mpt_rf_path = ODM_RF_PATH_BCD;
 649                         /*pHalData->ValidTxPath = 0x0e;*/
 650                         phy_set_bb_reg(pAdapter, rTxAnt_23Nsts_Jaguar2, 0x0fff0000, 0x90e);     /*/ 0x940[27:16]=12'b0010_0100_0111*/
 651                         break;
 652
 653                 case ANTENNA_ABC:
 654                 default:
 655                         pMptCtx->mpt_rf_path = ODM_RF_PATH_ABC;
 656                         /*pHalData->ValidTxPath = 0x0d;*/
 657                         phy_set_bb_reg(pAdapter, rTxAnt_23Nsts_Jaguar2, 0x0fff0000, 0x247);     /*/ 0x940[27:16]=12'b0010_0100_0111*/
 658                         break;
 659                 }
 660
 661         } else { /*/if(NssforRate == RF_1TX)*/
 662                 RTW_INFO("===> SetAntenna 1T ForcedDataRate %d NssforRate %d AntennaTx %d\n", ForcedDataRate, NssforRate, ulAntennaTx);
 663                 switch (ulAntennaTx) {
 664                 case ANTENNA_BCD:
 665                         pMptCtx->mpt_rf_path = ODM_RF_PATH_BCD;
 666                         /*pHalData->ValidTxPath = 0x0e;*/
 667                         phy_set_bb_reg(pAdapter, rCCK_RX_Jaguar, 0xf0000000, 0x7);
 668                         phy_set_bb_reg(pAdapter, rTxAnt_1Nsts_Jaguar2, 0x000f00000, 0xe);
 669                         phy_set_bb_reg(pAdapter, rTxPath_Jaguar, 0xf0, 0xe);
 670                         break;
 671
 672                 case ANTENNA_BC:
 673                         pMptCtx->mpt_rf_path = ODM_RF_PATH_BC;
 674                         /*pHalData->ValidTxPath = 0x06;*/
 675                         phy_set_bb_reg(pAdapter, rCCK_RX_Jaguar, 0xf0000000, 0x6);
 676                         phy_set_bb_reg(pAdapter, rTxAnt_1Nsts_Jaguar2, 0x000f00000, 0x6);
 677                         phy_set_bb_reg(pAdapter, rTxPath_Jaguar, 0xf0, 0x6);
 678                         break;
 679                 case ANTENNA_B:
 680                         pMptCtx->mpt_rf_path = ODM_RF_PATH_B;
 681                         /*pHalData->ValidTxPath = 0x02;*/
 682                         phy_set_bb_reg(pAdapter, rCCK_RX_Jaguar, 0xf0000000, 0x4);                      /*/ 0xa07[7:4] = 4'b0100*/
 683                         phy_set_bb_reg(pAdapter, rTxAnt_1Nsts_Jaguar2, 0xfff00000, 0x002);      /*/ 0x93C[31:20]=12'b0000_0000_0010*/
 684                         phy_set_bb_reg(pAdapter, rTxPath_Jaguar, 0xf0, 0x2);                                    /* 0x80C[7:4] = 4'b0010*/
 685                         break;
 686
 687                 case ANTENNA_C:
 688                         pMptCtx->mpt_rf_path = ODM_RF_PATH_C;
 689                         /*pHalData->ValidTxPath = 0x04;*/
 690                         phy_set_bb_reg(pAdapter, rCCK_RX_Jaguar, 0xf0000000, 0x2);                      /*/ 0xa07[7:4] = 4'b0010*/
 691                         phy_set_bb_reg(pAdapter, rTxAnt_1Nsts_Jaguar2, 0xfff00000, 0x004);      /*/ 0x93C[31:20]=12'b0000_0000_0100*/
 692                         phy_set_bb_reg(pAdapter, rTxPath_Jaguar, 0xf0, 0x4);                                    /*/ 0x80C[7:4] = 4'b0100*/
 693                         break;
 694
 695                 case ANTENNA_D:
 696                         pMptCtx->mpt_rf_path = ODM_RF_PATH_D;
 697                         /*pHalData->ValidTxPath = 0x08;*/
 698                         phy_set_bb_reg(pAdapter, rCCK_RX_Jaguar, 0xf0000000, 0x1);                      /*/ 0xa07[7:4] = 4'b0001*/
 699                         phy_set_bb_reg(pAdapter, rTxAnt_1Nsts_Jaguar2, 0xfff00000, 0x008);      /*/ 0x93C[31:20]=12'b0000_0000_1000*/
 700                         phy_set_bb_reg(pAdapter, rTxPath_Jaguar, 0xf0, 0x8);                                    /*/ 0x80C[7:4] = 4'b1000*/
 701                         break;
 702
 703                 case ANTENNA_A:
 704                 default:
 705                         pMptCtx->mpt_rf_path = ODM_RF_PATH_A;
 706                         /*pHalData->ValidTxPath = 0x01;*/
 707                         phy_set_bb_reg(pAdapter, rCCK_RX_Jaguar, 0xf0000000, 0x8);                      /*/ 0xa07[7:4] = 4'b1000*/
 708                         phy_set_bb_reg(pAdapter, rTxAnt_1Nsts_Jaguar2, 0xfff00000, 0x001);      /*/ 0x93C[31:20]=12'b0000_0000_0001*/
 709                         phy_set_bb_reg(pAdapter, rTxPath_Jaguar, 0xf0, 0x1);                                    /*/ 0x80C[7:4] = 4'b0001*/
 710                         break;
 711                 }
 712         }
 713
 714         switch (ulAntennaRx) {
 715         case ANTENNA_A:
 716                 /*pHalData->ValidRxPath = 0x01;*/
 717                 phy_set_bb_reg(pAdapter, 0x1000, bMaskByte2, 0x2);
 718                 phy_set_bb_reg(pAdapter, rRxPath_Jaguar, bMaskByte0, 0x11);
 719                 phy_set_bb_reg(pAdapter, 0x1000, bMaskByte2, 0x3);
 720                 phy_set_bb_reg(pAdapter, rCCK_RX_Jaguar, 0x0C000000, 0x0);
 721                 phy_set_rf_reg(pAdapter, ODM_RF_PATH_A, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_A_0x0[19:16] = 3, RX mode*/
 722                 phy_set_rf_reg(pAdapter, ODM_RF_PATH_B, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_B_0x0[19:16] = 1, Standby mode*/
 723                 phy_set_rf_reg(pAdapter, ODM_RF_PATH_C, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_C_0x0[19:16] = 1, Standby mode*/
 724                 phy_set_rf_reg(pAdapter, ODM_RF_PATH_D, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_D_0x0[19:16] = 1, Standby mode*/
 725                 /*/ CCA related PD_delay_th*/
 726                 phy_set_bb_reg(pAdapter, rAGC_table_Jaguar, 0x0F000000, 0x5);
 727                 phy_set_bb_reg(pAdapter, rPwed_TH_Jaguar, 0x0000000F, 0xA);
 728                 break;
 729
 730         case ANTENNA_B:
 731                 /*pHalData->ValidRxPath = 0x02;*/
 732                 phy_set_bb_reg(pAdapter, 0x1000, bMaskByte2, 0x2);
 733                 phy_set_bb_reg(pAdapter, rRxPath_Jaguar, bMaskByte0, 0x22);
 734                 phy_set_bb_reg(pAdapter, 0x1000, bMaskByte2, 0x3);
 735                 phy_set_bb_reg(pAdapter, rCCK_RX_Jaguar, 0x0C000000, 0x1);
 736                 phy_set_rf_reg(pAdapter, ODM_RF_PATH_A, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_A_0x0[19:16] = 1, Standby mode*/
 737                 phy_set_rf_reg(pAdapter, ODM_RF_PATH_B, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_B_0x0[19:16] = 3, RX mode*/
 738                 phy_set_rf_reg(pAdapter, ODM_RF_PATH_C, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_C_0x0[19:16] = 1, Standby mode*/
 739                 phy_set_rf_reg(pAdapter, ODM_RF_PATH_D, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_D_0x0[19:16] = 1, Standby mode*/
 740                 /*/ CCA related PD_delay_th*/
 741                 phy_set_bb_reg(pAdapter, rAGC_table_Jaguar, 0x0F000000, 0x5);
 742                 phy_set_bb_reg(pAdapter, rPwed_TH_Jaguar, 0x0000000F, 0xA);
 743                 break;
 744
 745         case ANTENNA_C:
 746                 /*pHalData->ValidRxPath = 0x04;*/
 747                 phy_set_bb_reg(pAdapter, 0x1000, bMaskByte2, 0x2);
 748                 phy_set_bb_reg(pAdapter, rRxPath_Jaguar, bMaskByte0, 0x44);
 749                 phy_set_bb_reg(pAdapter, 0x1000, bMaskByte2, 0x3);
 750                 phy_set_bb_reg(pAdapter, rCCK_RX_Jaguar, 0x0C000000, 0x2);
 751                 phy_set_rf_reg(pAdapter, ODM_RF_PATH_A, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_A_0x0[19:16] = 1, Standby mode*/
 752                 phy_set_rf_reg(pAdapter, ODM_RF_PATH_B, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_B_0x0[19:16] = 1, Standby mode*/
 753                 phy_set_rf_reg(pAdapter, ODM_RF_PATH_C, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_C_0x0[19:16] = 3, RX mode*/
 754                 phy_set_rf_reg(pAdapter, ODM_RF_PATH_D, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_D_0x0[19:16] = 1, Standby mode*/
 755                 /*/ CCA related PD_delay_th*/
 756                 phy_set_bb_reg(pAdapter, rAGC_table_Jaguar, 0x0F000000, 0x5);
 757                 phy_set_bb_reg(pAdapter, rPwed_TH_Jaguar, 0x0000000F, 0xA);
 758                 break;
 759
 760         case ANTENNA_D:
 761                 /*pHalData->ValidRxPath = 0x08;*/
 762                 phy_set_bb_reg(pAdapter, 0x1000, bMaskByte2, 0x2);
 763                 phy_set_bb_reg(pAdapter, rRxPath_Jaguar, bMaskByte0, 0x88);
 764                 phy_set_bb_reg(pAdapter, 0x1000, bMaskByte2, 0x3);
 765                 phy_set_bb_reg(pAdapter, rCCK_RX_Jaguar, 0x0C000000, 0x3);
 766                 phy_set_rf_reg(pAdapter, ODM_RF_PATH_A, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_A_0x0[19:16] = 1, Standby mode*/
 767                 phy_set_rf_reg(pAdapter, ODM_RF_PATH_B, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_B_0x0[19:16] = 1, Standby mode*/
 768                 phy_set_rf_reg(pAdapter, ODM_RF_PATH_C, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_C_0x0[19:16] = 1, Standby mode*/
 769                 phy_set_rf_reg(pAdapter, ODM_RF_PATH_D, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_D_0x0[19:16] = 3, RX mode*/
 770                 /*/ CCA related PD_delay_th*/
 771                 phy_set_bb_reg(pAdapter, rAGC_table_Jaguar, 0x0F000000, 0x5);
 772                 phy_set_bb_reg(pAdapter, rPwed_TH_Jaguar, 0x0000000F, 0xA);
 773                 break;
 774
 775         case ANTENNA_BC:
 776                 /*pHalData->ValidRxPath = 0x06;*/
 777                 phy_set_bb_reg(pAdapter, 0x1000, bMaskByte2, 0x2);
 778                 phy_set_bb_reg(pAdapter, rRxPath_Jaguar, bMaskByte0, 0x66);
 779                 phy_set_bb_reg(pAdapter, 0x1000, bMaskByte2, 0x3);
 780                 phy_set_bb_reg(pAdapter, rCCK_RX_Jaguar, 0x0f000000, 0x6);
 781                 phy_set_rf_reg(pAdapter, ODM_RF_PATH_A, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_A_0x0[19:16] = 1, Standby mode*/
 782                 phy_set_rf_reg(pAdapter, ODM_RF_PATH_B, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_B_0x0[19:16] = 3, RX mode*/
 783                 phy_set_rf_reg(pAdapter, ODM_RF_PATH_C, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_C_0x0[19:16] = 3, Rx mode*/
 784                 phy_set_rf_reg(pAdapter, ODM_RF_PATH_D, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_D_0x0[19:16] = 1, Standby mode*/
 785                 /*/ CCA related PD_delay_th*/
 786                 phy_set_bb_reg(pAdapter, rAGC_table_Jaguar, 0x0F000000, 0x5);
 787                 phy_set_bb_reg(pAdapter, rPwed_TH_Jaguar, 0x0000000F, 0xA);
 788                 break;
 789
 790         case ANTENNA_CD:
 791                 /*pHalData->ValidRxPath = 0x0C;*/
 792                 phy_set_bb_reg(pAdapter, 0x1000, bMaskByte2, 0x2);
 793                 phy_set_bb_reg(pAdapter, rRxPath_Jaguar, bMaskByte0, 0xcc);
 794                 phy_set_bb_reg(pAdapter, 0x1000, bMaskByte2, 0x3);
 795                 phy_set_bb_reg(pAdapter, rCCK_RX_Jaguar, 0x0f000000, 0xB);
 796                 phy_set_rf_reg(pAdapter, ODM_RF_PATH_A, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_A_0x0[19:16] = 1, Standby mode*/
 797                 phy_set_rf_reg(pAdapter, ODM_RF_PATH_B, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_B_0x0[19:16] = 1, Standby mode*/
 798                 phy_set_rf_reg(pAdapter, ODM_RF_PATH_C, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_C_0x0[19:16] = 3, Rx mode*/
 799                 phy_set_rf_reg(pAdapter, ODM_RF_PATH_D, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_D_0x0[19:16] = 3, RX mode*/
 800                 /*/ CCA related PD_delay_th*/
 801                 phy_set_bb_reg(pAdapter, rAGC_table_Jaguar, 0x0F000000, 0x5);
 802                 phy_set_bb_reg(pAdapter, rPwed_TH_Jaguar, 0x0000000F, 0xA);
 803                 break;
 804
 805         case ANTENNA_BCD:
 806                 /*pHalData->ValidRxPath = 0x0e;*/
 807                 phy_set_bb_reg(pAdapter, 0x1000, bMaskByte2, 0x2);
 808                 phy_set_bb_reg(pAdapter, rRxPath_Jaguar, bMaskByte0, 0xee);
 809                 phy_set_bb_reg(pAdapter, 0x1000, bMaskByte2, 0x3);
 810                 phy_set_bb_reg(pAdapter, rCCK_RX_Jaguar, 0x0f000000, 0x6);
 811                 phy_set_rf_reg(pAdapter, ODM_RF_PATH_A, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_A_0x0[19:16] = 1, Standby mode*/
 812                 phy_set_rf_reg(pAdapter, ODM_RF_PATH_B, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_B_0x0[19:16] = 3, RX mode*/
 813                 phy_set_rf_reg(pAdapter, ODM_RF_PATH_C, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_C_0x0[19:16] = 3, RX mode*/
 814                 phy_set_rf_reg(pAdapter, ODM_RF_PATH_D, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_D_0x0[19:16] = 3, Rx mode*/
 815                 /*/ CCA related PD_delay_th*/
 816                 phy_set_bb_reg(pAdapter, rAGC_table_Jaguar, 0x0F000000, 0x3);
 817                 phy_set_bb_reg(pAdapter, rPwed_TH_Jaguar, 0x0000000F, 0x8);
 818                 break;
 819
 820         case ANTENNA_ABCD:
 821                 /*pHalData->ValidRxPath = 0x0f;*/
 822                 phy_set_bb_reg(pAdapter, 0x1000, bMaskByte2, 0x2);
 823                 phy_set_bb_reg(pAdapter, rRxPath_Jaguar, bMaskByte0, 0xff);
 824                 phy_set_bb_reg(pAdapter, 0x1000, bMaskByte2, 0x3);
 825                 phy_set_bb_reg(pAdapter, rCCK_RX_Jaguar, 0x0f000000, 0x1);
 826                 phy_set_rf_reg(pAdapter, ODM_RF_PATH_A, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_A_0x0[19:16] = 3, RX mode*/
 827                 phy_set_rf_reg(pAdapter, ODM_RF_PATH_B, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_B_0x0[19:16] = 3, RX mode*/
 828                 phy_set_rf_reg(pAdapter, ODM_RF_PATH_C, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_C_0x0[19:16] = 3, RX mode*/
 829                 phy_set_rf_reg(pAdapter, ODM_RF_PATH_D, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_D_0x0[19:16] = 3, RX mode*/
 830                 /*/ CCA related PD_delay_th*/
 831                 phy_set_bb_reg(pAdapter, rAGC_table_Jaguar, 0x0F000000, 0x3);
 832                 phy_set_bb_reg(pAdapter, rPwed_TH_Jaguar, 0x0000000F, 0x8);
 833                 break;
 834
 835         default:
 836                 break;
 837         }
 838
 839         PHY_Set_SecCCATH_by_RXANT_8814A(pAdapter, ulAntennaRx);
 840
 841         mpt_ToggleIG_8814A(pAdapter);
 842 }
 843 #endif /* CONFIG_RTL8814A */
 844 #if defined(CONFIG_RTL8814A) || defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8821C)
 845 VOID
 846 mpt_SetSingleTone_8814A(
 847         IN      PADAPTER        pAdapter,
 848         IN      BOOLEAN bSingleTone,
 849         IN      BOOLEAN bEnPMacTx)
 850 {
 851
 852         PMPT_CONTEXT    pMptCtx = &(pAdapter->mppriv.mpt_ctx);
 853         u1Byte StartPath = ODM_RF_PATH_A,  EndPath = ODM_RF_PATH_A;
 854         static u4Byte           regIG0 = 0, regIG1 = 0, regIG2 = 0, regIG3 = 0;
 855
 856         if (bSingleTone) {
 857                 regIG0 = phy_query_bb_reg(pAdapter, rA_TxScale_Jaguar, bMaskDWord);             /*/ 0xC1C[31:21]*/
 858                 regIG1 = phy_query_bb_reg(pAdapter, rB_TxScale_Jaguar, bMaskDWord);             /*/ 0xE1C[31:21]*/
 859                 regIG2 = phy_query_bb_reg(pAdapter, rC_TxScale_Jaguar2, bMaskDWord);    /*/ 0x181C[31:21]*/
 860                 regIG3 = phy_query_bb_reg(pAdapter, rD_TxScale_Jaguar2, bMaskDWord);    /*/ 0x1A1C[31:21]*/
 861
 862                 switch (pMptCtx->mpt_rf_path) {
 863                 case ODM_RF_PATH_A:
 864                 case ODM_RF_PATH_B:
 865                 case ODM_RF_PATH_C:
 866                 case ODM_RF_PATH_D:
 867                         StartPath = pMptCtx->mpt_rf_path;
 868                         EndPath = pMptCtx->mpt_rf_path;
 869                         break;
 870                 case ODM_RF_PATH_AB:
 871                         EndPath = ODM_RF_PATH_B;
 872                         break;
 873                 case ODM_RF_PATH_BC:
 874                         StartPath = ODM_RF_PATH_B;
 875                         EndPath = ODM_RF_PATH_C;
 876                         break;
 877                 case ODM_RF_PATH_ABC:
 878                         EndPath = ODM_RF_PATH_C;
 879                         break;
 880                 case ODM_RF_PATH_BCD:
 881                         StartPath = ODM_RF_PATH_B;
 882                         EndPath = ODM_RF_PATH_D;
 883                         break;
 884                 case ODM_RF_PATH_ABCD:
 885                         EndPath = ODM_RF_PATH_D;
 886                         break;
 887                 }
 888
 889                 if (bEnPMacTx == FALSE) {
 890                         hal_mpt_SetContinuousTx(pAdapter, _TRUE);
 891                         issue_nulldata(pAdapter, NULL, 1, 3, 500);
 892                 }
 893
 894                 phy_set_bb_reg(pAdapter, rCCAonSec_Jaguar, BIT1, 0x1); /*/ Disable CCA*/
 895
 896                 for (StartPath; StartPath <= EndPath; StartPath++) {
 897                         phy_set_rf_reg(pAdapter, StartPath, RF_AC_Jaguar, 0xF0000, 0x2); /*/ Tx mode: RF0x00[19:16]=4'b0010 */
 898                         phy_set_rf_reg(pAdapter, StartPath, RF_AC_Jaguar, 0x1F, 0x0); /*/ Lowest RF gain index: RF_0x0[4:0] = 0*/
 899
 900                         phy_set_rf_reg(pAdapter, StartPath, lna_low_gain_3, BIT1, 0x1); /*/ RF LO enabled*/
 901                 }
 902
 903                 phy_set_bb_reg(pAdapter, rA_TxScale_Jaguar, 0xFFE00000, 0); /*/ 0xC1C[31:21]*/
 904                 phy_set_bb_reg(pAdapter, rB_TxScale_Jaguar, 0xFFE00000, 0); /*/ 0xE1C[31:21]*/
 905                 phy_set_bb_reg(pAdapter, rC_TxScale_Jaguar2, 0xFFE00000, 0); /*/ 0x181C[31:21]*/
 906                 phy_set_bb_reg(pAdapter, rD_TxScale_Jaguar2, 0xFFE00000, 0); /*/ 0x1A1C[31:21]*/
 907         } else {
 908                 switch (pMptCtx->mpt_rf_path) {
 909                 case ODM_RF_PATH_A:
 910                 case ODM_RF_PATH_B:
 911                 case ODM_RF_PATH_C:
 912                 case ODM_RF_PATH_D:
 913                         StartPath = pMptCtx->mpt_rf_path;
 914                         EndPath = pMptCtx->mpt_rf_path;
 915                         break;
 916                 case ODM_RF_PATH_AB:
 917                         EndPath = ODM_RF_PATH_B;
 918                         break;
 919                 case ODM_RF_PATH_BC:
 920                         StartPath = ODM_RF_PATH_B;
 921                         EndPath = ODM_RF_PATH_C;
 922                         break;
 923                 case ODM_RF_PATH_ABC:
 924                         EndPath = ODM_RF_PATH_C;
 925                         break;
 926                 case ODM_RF_PATH_BCD:
 927                         StartPath = ODM_RF_PATH_B;
 928                         EndPath = ODM_RF_PATH_D;
 929                         break;
 930                 case ODM_RF_PATH_ABCD:
 931                         EndPath = ODM_RF_PATH_D;
 932                         break;
 933                 }
 934                 for (StartPath; StartPath <= EndPath; StartPath++)
 935                         phy_set_rf_reg(pAdapter, StartPath, lna_low_gain_3, BIT1, 0x0); /* RF LO disabled */
 936
 937                 phy_set_bb_reg(pAdapter, rCCAonSec_Jaguar, BIT1, 0x0); /* Enable CCA*/
 938
 939                 if (bEnPMacTx == FALSE)
 940                         hal_mpt_SetContinuousTx(pAdapter, _FALSE);
 941
 942                 phy_set_bb_reg(pAdapter, rA_TxScale_Jaguar, bMaskDWord, regIG0); /* 0xC1C[31:21]*/
 943                 phy_set_bb_reg(pAdapter, rB_TxScale_Jaguar, bMaskDWord, regIG1); /* 0xE1C[31:21]*/
 944                 phy_set_bb_reg(pAdapter, rC_TxScale_Jaguar2, bMaskDWord, regIG2); /* 0x181C[31:21]*/
 945                 phy_set_bb_reg(pAdapter, rD_TxScale_Jaguar2, bMaskDWord, regIG3); /* 0x1A1C[31:21]*/
 946         }
 947 }
 948
 949 #endif
 950
 951 #if     defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A)
 952 void mpt_SetRFPath_8812A(PADAPTER pAdapter)
 953 {
 954         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(pAdapter);
 955         PMPT_CONTEXT    pMptCtx = &pAdapter->mppriv.mpt_ctx;
 956         struct mp_priv *pmp = &pAdapter->mppriv;
 957         u8              channel = pmp->channel;
 958         u8              bandwidth = pmp->bandwidth;
 959         u8              eLNA_2g = pHalData->ExternalLNA_2G;
 960         u32             ulAntennaTx, ulAntennaRx;
 961
 962         ulAntennaTx = pHalData->antenna_tx_path;
 963         ulAntennaRx = pHalData->AntennaRxPath;
 964
 965         switch (ulAntennaTx) {
 966         case ANTENNA_A:
 967                 pMptCtx->mpt_rf_path = ODM_RF_PATH_A;
 968                 phy_set_bb_reg(pAdapter, rTxPath_Jaguar, bMaskLWord, 0x1111);
 969                 if (pHalData->rfe_type == 3 && IS_HARDWARE_TYPE_8812(pAdapter))
 970                         phy_set_bb_reg(pAdapter, r_ANTSEL_SW_Jaguar, bMask_AntselPathFollow_Jaguar, 0x0);
 971                 break;
 972         case ANTENNA_B:
 973                 pMptCtx->mpt_rf_path = ODM_RF_PATH_B;
 974                 phy_set_bb_reg(pAdapter, rTxPath_Jaguar, bMaskLWord, 0x2222);
 975                 if (pHalData->rfe_type == 3 && IS_HARDWARE_TYPE_8812(pAdapter))
 976                         phy_set_bb_reg(pAdapter,        r_ANTSEL_SW_Jaguar, bMask_AntselPathFollow_Jaguar, 0x1);
 977                 break;
 978         case ANTENNA_AB:
 979                 pMptCtx->mpt_rf_path = ODM_RF_PATH_AB;
 980                 phy_set_bb_reg(pAdapter, rTxPath_Jaguar, bMaskLWord, 0x3333);
 981                 if (pHalData->rfe_type == 3 && IS_HARDWARE_TYPE_8812(pAdapter))
 982                         phy_set_bb_reg(pAdapter, r_ANTSEL_SW_Jaguar, bMask_AntselPathFollow_Jaguar, 0x0);
 983                 break;
 984         default:
 985                 pMptCtx->mpt_rf_path = ODM_RF_PATH_AB;
 986                 RTW_INFO("Unknown Tx antenna.\n");
 987                 break;
 988         }
 989
 990         switch (ulAntennaRx) {
 991                 u32 reg0xC50 = 0;
 992         case ANTENNA_A:
 993                 phy_set_bb_reg(pAdapter, rRxPath_Jaguar, bMaskByte0, 0x11);
 994                 phy_set_rf_reg(pAdapter, ODM_RF_PATH_B, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_B_0x0[19:16] = 1, Standby mode*/
 995                 phy_set_bb_reg(pAdapter, rCCK_RX_Jaguar, bCCK_RX_Jaguar, 0x0);
 996                 phy_set_rf_reg(pAdapter, ODM_RF_PATH_A, RF_AC_Jaguar, BIT19 | BIT18 | BIT17 | BIT16, 0x3);
 997
 998                 /*/ <20121101, Kordan> To prevent gain table from not switched, asked by Ynlin.*/
 999                 reg0xC50 = phy_query_bb_reg(pAdapter, rA_IGI_Jaguar, bMaskByte0);
1000                 phy_set_bb_reg(pAdapter, rA_IGI_Jaguar, bMaskByte0, reg0xC50 + 2);
1001                 phy_set_bb_reg(pAdapter, rA_IGI_Jaguar, bMaskByte0, reg0xC50);
1002
1003                 /* set PWED_TH for BB Yn user guide R29 */
1004                 if (IS_HARDWARE_TYPE_8812(pAdapter)) {
1005                         if (channel <= 14) { /* 2.4G */
1006                                 if (bandwidth == CHANNEL_WIDTH_20
1007                                     && eLNA_2g == 0) {
1008                                         /* 0x830[3:1]=3'b010 */
1009                                         phy_set_bb_reg(pAdapter, rPwed_TH_Jaguar, BIT1 | BIT2 | BIT3, 0x02);
1010                                 } else
1011                                         /* 0x830[3:1]=3'b100 */
1012                                         phy_set_bb_reg(pAdapter, rPwed_TH_Jaguar, BIT1 | BIT2 | BIT3, 0x04);
1013                         } else
1014                                 /* 0x830[3:1]=3'b100 for 5G */
1015                                 phy_set_bb_reg(pAdapter, rPwed_TH_Jaguar, BIT1 | BIT2 | BIT3, 0x04);
1016                 }
1017                 break;
1018         case ANTENNA_B:
1019                 phy_set_bb_reg(pAdapter, rRxPath_Jaguar, bMaskByte0, 0x22);
1020                 phy_set_rf_reg(pAdapter, ODM_RF_PATH_A, RF_AC_Jaguar, 0xF0000, 0x1);/*/ RF_A_0x0[19:16] = 1, Standby mode */
1021                 phy_set_bb_reg(pAdapter, rCCK_RX_Jaguar, bCCK_RX_Jaguar, 0x1);
1022                 phy_set_rf_reg(pAdapter, ODM_RF_PATH_B, RF_AC_Jaguar, BIT19 | BIT18 | BIT17 | BIT16, 0x3);
1023
1024                 /*/ <20121101, Kordan> To prevent gain table from not switched, asked by Ynlin.*/
1025                 reg0xC50 = phy_query_bb_reg(pAdapter, rB_IGI_Jaguar, bMaskByte0);
1026                 phy_set_bb_reg(pAdapter, rB_IGI_Jaguar, bMaskByte0, reg0xC50 + 2);
1027                 phy_set_bb_reg(pAdapter, rB_IGI_Jaguar, bMaskByte0, reg0xC50);
1028
1029                 /* set PWED_TH for BB Yn user guide R29 */
1030                 if (IS_HARDWARE_TYPE_8812(pAdapter)) {
1031                         if (channel <= 14) {
1032                                 if (bandwidth == CHANNEL_WIDTH_20
1033                                     && eLNA_2g == 0) {
1034                                         /* 0x830[3:1]=3'b010 */
1035                                         phy_set_bb_reg(pAdapter, rPwed_TH_Jaguar, BIT1 | BIT2 | BIT3, 0x02);
1036                                 } else
1037                                         /* 0x830[3:1]=3'b100 */
1038                                         phy_set_bb_reg(pAdapter, rPwed_TH_Jaguar, BIT1 | BIT2 | BIT3, 0x04);
1039                         } else
1040                                 /* 0x830[3:1]=3'b100 for 5G */
1041                                 phy_set_bb_reg(pAdapter, rPwed_TH_Jaguar, BIT1 | BIT2 | BIT3, 0x04);
1042                 }
1043                 break;
1044         case ANTENNA_AB:
1045                 phy_set_bb_reg(pAdapter, rRxPath_Jaguar, bMaskByte0, 0x33);
1046                 phy_set_rf_reg(pAdapter, ODM_RF_PATH_B, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_B_0x0[19:16] = 3, Rx mode*/
1047                 phy_set_bb_reg(pAdapter, rCCK_RX_Jaguar, bCCK_RX_Jaguar, 0x0);
1048                 /* set PWED_TH for BB Yn user guide R29 */
1049                 phy_set_bb_reg(pAdapter, rPwed_TH_Jaguar, BIT1 | BIT2 | BIT3, 0x04);
1050                 break;
1051         default:
1052                 RTW_INFO("Unknown Rx antenna.\n");
1053                 break;
1054         }
1055 }
1056 #endif
1057
1058 #ifdef CONFIG_RTL8723B
1059 void mpt_SetRFPath_8723B(PADAPTER pAdapter)
1060 {
1061         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(pAdapter);
1062         u32             ulAntennaTx, ulAntennaRx;
1063         PMPT_CONTEXT    pMptCtx = &(pAdapter->mppriv.mpt_ctx);
1064         struct PHY_DM_STRUCT    *pDM_Odm = &pHalData->odmpriv;
1065         struct odm_rf_calibration_structure     *pRFCalibrateInfo = &(pDM_Odm->rf_calibrate_info);
1066
1067         ulAntennaTx = pHalData->antenna_tx_path;
1068         ulAntennaRx = pHalData->AntennaRxPath;
1069
1070         if (pHalData->rf_chip >= RF_TYPE_MAX) {
1071                 RTW_INFO("This RF chip ID is not supported\n");
1072                 return;
1073         }
1074
1075         switch (pAdapter->mppriv.antenna_tx) {
1076                 u8 p = 0, i = 0;
1077         case ANTENNA_A: { /*/ Actually path S1  (Wi-Fi)*/
1078                 pMptCtx->mpt_rf_path = ODM_RF_PATH_A;
1079                 phy_set_bb_reg(pAdapter, rS0S1_PathSwitch, BIT9 | BIT8 | BIT7, 0x0);
1080                 phy_set_bb_reg(pAdapter, 0xB2C, BIT31, 0x0); /* AGC Table Sel*/
1081
1082                 /*/<20130522, Kordan> 0x51 and 0x71 should be set immediately after path switched, or they might be overwritten.*/
1083                 if ((pHalData->PackageType == PACKAGE_TFBGA79) || (pHalData->PackageType == PACKAGE_TFBGA90))
1084                         phy_set_rf_reg(pAdapter, ODM_RF_PATH_A, 0x51, bRFRegOffsetMask, 0x6B10E);
1085                 else
1086                         phy_set_rf_reg(pAdapter, ODM_RF_PATH_A, 0x51, bRFRegOffsetMask, 0x6B04E);
1087
1088                 for (i = 0; i < 3; ++i) {
1089                         u4Byte offset = pRFCalibrateInfo->tx_iqc_8723b[ODM_RF_PATH_A][i][0];
1090                         u4Byte data = pRFCalibrateInfo->tx_iqc_8723b[ODM_RF_PATH_A][i][1];
1091
1092                         if (offset != 0) {
1093                                 phy_set_bb_reg(pAdapter, offset, bMaskDWord, data);
1094                                 RTW_INFO("Switch to S1 TxIQC(offset, data) = (0x%X, 0x%X)\n", offset, data);
1095                         }
1096                 }
1097                 for (i = 0; i < 2; ++i) {
1098                         u4Byte offset = pRFCalibrateInfo->rx_iqc_8723b[ODM_RF_PATH_A][i][0];
1099                         u4Byte data = pRFCalibrateInfo->rx_iqc_8723b[ODM_RF_PATH_A][i][1];
1100
1101                         if (offset != 0) {
1102                                 phy_set_bb_reg(pAdapter, offset, bMaskDWord, data);
1103                                 RTW_INFO("Switch to S1 RxIQC (offset, data) = (0x%X, 0x%X)\n", offset, data);
1104                         }
1105                 }
1106         }
1107         break;
1108         case ANTENNA_B: { /*/ Actually path S0 (BT)*/
1109                 u4Byte offset;
1110                 u4Byte data;
1111
1112                 pMptCtx->mpt_rf_path = ODM_RF_PATH_B;
1113                 phy_set_bb_reg(pAdapter, rS0S1_PathSwitch, BIT9 | BIT8 | BIT7, 0x5);
1114                 phy_set_bb_reg(pAdapter, 0xB2C, BIT31, 0x1); /*/ AGC Table Sel.*/
1115                 /* <20130522, Kordan> 0x51 and 0x71 should be set immediately after path switched, or they might be overwritten.*/
1116                 if ((pHalData->PackageType == PACKAGE_TFBGA79) || (pHalData->PackageType == PACKAGE_TFBGA90))
1117                         phy_set_rf_reg(pAdapter, ODM_RF_PATH_A, 0x51, bRFRegOffsetMask, 0x6B10E);
1118                 else
1119                         phy_set_rf_reg(pAdapter, ODM_RF_PATH_A, 0x51, bRFRegOffsetMask, 0x6B04E);
1120
1121                 for (i = 0; i < 3; ++i) {
1122                         /*/ <20130603, Kordan> Because BB suppors only 1T1R, we restore IQC  to S1 instead of S0.*/
1123                         offset = pRFCalibrateInfo->tx_iqc_8723b[ODM_RF_PATH_A][i][0];
1124                         data = pRFCalibrateInfo->tx_iqc_8723b[ODM_RF_PATH_B][i][1];
1125                         if (pRFCalibrateInfo->tx_iqc_8723b[ODM_RF_PATH_B][i][0] != 0) {
1126                                 phy_set_bb_reg(pAdapter, offset, bMaskDWord, data);
1127                                 RTW_INFO("Switch to S0 TxIQC (offset, data) = (0x%X, 0x%X)\n", offset, data);
1128                         }
1129                 }
1130                 /*/ <20130603, Kordan> Because BB suppors only 1T1R, we restore IQC to S1 instead of S0.*/
1131                 for (i = 0; i < 2; ++i) {
1132                         offset = pRFCalibrateInfo->rx_iqc_8723b[ODM_RF_PATH_A][i][0];
1133                         data = pRFCalibrateInfo->rx_iqc_8723b[ODM_RF_PATH_B][i][1];
1134                         if (pRFCalibrateInfo->rx_iqc_8723b[ODM_RF_PATH_B][i][0] != 0) {
1135                                 phy_set_bb_reg(pAdapter, offset, bMaskDWord, data);
1136                                 RTW_INFO("Switch to S0 RxIQC (offset, data) = (0x%X, 0x%X)\n", offset, data);
1137                         }
1138                 }
1139         }
1140         break;
1141         default:
1142                 pMptCtx->mpt_rf_path = RF_PATH_AB;
1143                 break;
1144         }
1145 }
1146 #endif
1147
1148 #ifdef CONFIG_RTL8703B
1149 void mpt_SetRFPath_8703B(PADAPTER pAdapter)
1150 {
1151         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(pAdapter);
1152         u4Byte                                  ulAntennaTx, ulAntennaRx;
1153         PMPT_CONTEXT            pMptCtx = &(pAdapter->mppriv.mpt_ctx);
1154         struct PHY_DM_STRUCT            *pDM_Odm = &pHalData->odmpriv;
1155         struct odm_rf_calibration_structure                     *pRFCalibrateInfo = &(pDM_Odm->rf_calibrate_info);
1156
1157         ulAntennaTx = pHalData->antenna_tx_path;
1158         ulAntennaRx = pHalData->AntennaRxPath;
1159
1160         if (pHalData->rf_chip >= RF_TYPE_MAX) {
1161                 RTW_INFO("This RF chip ID is not supported\n");
1162                 return;
1163         }
1164
1165         switch (pAdapter->mppriv.antenna_tx) {
1166                 u1Byte p = 0, i = 0;
1167
1168         case ANTENNA_A: { /* Actually path S1  (Wi-Fi) */
1169                 pMptCtx->mpt_rf_path = ODM_RF_PATH_A;
1170                 phy_set_bb_reg(pAdapter, rS0S1_PathSwitch, BIT9 | BIT8 | BIT7, 0x0);
1171                 phy_set_bb_reg(pAdapter, 0xB2C, BIT31, 0x0); /* AGC Table Sel*/
1172
1173                 for (i = 0; i < 3; ++i) {
1174                         u4Byte offset = pRFCalibrateInfo->tx_iqc_8703b[i][0];
1175                         u4Byte data = pRFCalibrateInfo->tx_iqc_8703b[i][1];
1176
1177                         if (offset != 0) {
1178                                 phy_set_bb_reg(pAdapter, offset, bMaskDWord, data);
1179                                 RTW_INFO("Switch to S1 TxIQC(offset, data) = (0x%X, 0x%X)\n", offset, data);
1180                         }
1181
1182                 }
1183                 for (i = 0; i < 2; ++i) {
1184                         u4Byte offset = pRFCalibrateInfo->rx_iqc_8703b[i][0];
1185                         u4Byte data = pRFCalibrateInfo->rx_iqc_8703b[i][1];
1186
1187                         if (offset != 0) {
1188                                 phy_set_bb_reg(pAdapter, offset, bMaskDWord, data);
1189                                 RTW_INFO("Switch to S1 RxIQC (offset, data) = (0x%X, 0x%X)\n", offset, data);
1190                         }
1191                 }
1192         }
1193         break;
1194         case ANTENNA_B: { /* Actually path S0 (BT)*/
1195                 pMptCtx->mpt_rf_path = ODM_RF_PATH_B;
1196                 phy_set_bb_reg(pAdapter, rS0S1_PathSwitch, BIT9 | BIT8 | BIT7, 0x5);
1197                 phy_set_bb_reg(pAdapter, 0xB2C, BIT31, 0x1); /* AGC Table Sel */
1198
1199                 for (i = 0; i < 3; ++i) {
1200                         u4Byte offset = pRFCalibrateInfo->tx_iqc_8703b[i][0];
1201                         u4Byte data = pRFCalibrateInfo->tx_iqc_8703b[i][1];
1202
1203                         if (pRFCalibrateInfo->tx_iqc_8703b[i][0] != 0) {
1204                                 phy_set_bb_reg(pAdapter, offset, bMaskDWord, data);
1205                                 RTW_INFO("Switch to S0 TxIQC (offset, data) = (0x%X, 0x%X)\n", offset, data);
1206                         }
1207                 }
1208                 for (i = 0; i < 2; ++i) {
1209                         u4Byte offset = pRFCalibrateInfo->rx_iqc_8703b[i][0];
1210                         u4Byte data = pRFCalibrateInfo->rx_iqc_8703b[i][1];
1211
1212                         if (pRFCalibrateInfo->rx_iqc_8703b[i][0] != 0) {
1213                                 phy_set_bb_reg(pAdapter, offset, bMaskDWord, data);
1214                                 RTW_INFO("Switch to S0 RxIQC (offset, data) = (0x%X, 0x%X)\n", offset, data);
1215                         }
1216                 }
1217         }
1218         break;
1219         default:
1220                 pMptCtx->mpt_rf_path = RF_PATH_AB;
1221                 break;
1222         }
1223
1224 }
1225 #endif
1226
1227 #ifdef CONFIG_RTL8723D
1228 void mpt_SetRFPath_8723D(PADAPTER pAdapter)
1229 {
1230         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(pAdapter);
1231         u1Byte  p = 0, i = 0;
1232         u4Byte  ulAntennaTx, ulAntennaRx, offset = 0, data = 0, val32 = 0;
1233         PMPT_CONTEXT    pMptCtx = &(pAdapter->mppriv.mpt_ctx);
1234         struct PHY_DM_STRUCT    *pDM_Odm = &pHalData->odmpriv;
1235         struct odm_rf_calibration_structure     *pRFCalibrateInfo = &(pDM_Odm->rf_calibrate_info);
1236
1237         ulAntennaTx = pHalData->antenna_tx_path;
1238         ulAntennaRx = pHalData->AntennaRxPath;
1239
1240         if (pHalData->rf_chip >= RF_TYPE_MAX) {
1241                 RTW_INFO("This RF chip ID is not supported\n");
1242                 return;
1243         }
1244
1245         switch (pAdapter->mppriv.antenna_tx) {
1246         /* Actually path S1  (Wi-Fi) */
1247         case ANTENNA_A: {
1248                 pMptCtx->mpt_rf_path = ODM_RF_PATH_A;
1249                 phy_set_bb_reg(pAdapter, rS0S1_PathSwitch, BIT9|BIT8|BIT7|BIT6, 0);
1250         }
1251         break;
1252         /* Actually path S0 (BT) */
1253         case ANTENNA_B: {
1254                 pMptCtx->mpt_rf_path = ODM_RF_PATH_B;
1255                 phy_set_bb_reg(pAdapter, rS0S1_PathSwitch, BIT9|BIT8|BIT7|BIT6, 0xA);
1256
1257         }
1258         break;
1259         default:
1260                 pMptCtx->mpt_rf_path = RF_PATH_AB;
1261                 break;
1262         }
1263 }
1264 #endif
1265
1266 VOID mpt_SetRFPath_819X(PADAPTER        pAdapter)
1267 {
1268         HAL_DATA_TYPE                   *pHalData       = GET_HAL_DATA(pAdapter);
1269         PMPT_CONTEXT            pMptCtx = &(pAdapter->mppriv.mpt_ctx);
1270         u4Byte                  ulAntennaTx, ulAntennaRx;
1271         R_ANTENNA_SELECT_OFDM   *p_ofdm_tx;     /* OFDM Tx register */
1272         R_ANTENNA_SELECT_CCK    *p_cck_txrx;
1273         u1Byte          r_rx_antenna_ofdm = 0, r_ant_select_cck_val = 0;
1274         u1Byte          chgTx = 0, chgRx = 0;
1275         u4Byte          r_ant_sel_cck_val = 0, r_ant_select_ofdm_val = 0, r_ofdm_tx_en_val = 0;
1276
1277         ulAntennaTx = pHalData->antenna_tx_path;
1278         ulAntennaRx = pHalData->AntennaRxPath;
1279
1280         p_ofdm_tx = (R_ANTENNA_SELECT_OFDM *)&r_ant_select_ofdm_val;
1281         p_cck_txrx = (R_ANTENNA_SELECT_CCK *)&r_ant_select_cck_val;
1282
1283         p_ofdm_tx->r_ant_ht1                    = 0x1;
1284         p_ofdm_tx->r_ant_ht2                    = 0x2;/*Second TX RF path is A*/
1285         p_ofdm_tx->r_ant_non_ht                 = 0x3;/*/ 0x1+0x2=0x3 */
1286
1287         switch (ulAntennaTx) {
1288         case ANTENNA_A:
1289                 p_ofdm_tx->r_tx_antenna         = 0x1;
1290                 r_ofdm_tx_en_val                = 0x1;
1291                 p_ofdm_tx->r_ant_l              = 0x1;
1292                 p_ofdm_tx->r_ant_ht_s1          = 0x1;
1293                 p_ofdm_tx->r_ant_non_ht_s1      = 0x1;
1294                 p_cck_txrx->r_ccktx_enable      = 0x8;
1295                 chgTx = 1;
1296                 /*/ From SD3 Willis suggestion !!! Set RF A=TX and B as standby*/
1297                 /*/if (IS_HARDWARE_TYPE_8192S(pAdapter))*/
1298                 {
1299                         phy_set_bb_reg(pAdapter, rFPGA0_XA_HSSIParameter2, 0xe, 2);
1300                         phy_set_bb_reg(pAdapter, rFPGA0_XB_HSSIParameter2, 0xe, 1);
1301                         r_ofdm_tx_en_val                        = 0x3;
1302                         /*/ Power save*/
1303                         /*/cosa r_ant_select_ofdm_val = 0x11111111;*/
1304                         /*/ We need to close RFB by SW control*/
1305                         if (pHalData->rf_type == RF_2T2R) {
1306                                 phy_set_bb_reg(pAdapter, rFPGA0_XAB_RFInterfaceSW, BIT10, 0);
1307                                 phy_set_bb_reg(pAdapter, rFPGA0_XAB_RFInterfaceSW, BIT26, 1);
1308                                 phy_set_bb_reg(pAdapter, rFPGA0_XB_RFInterfaceOE, BIT10, 0);
1309                                 phy_set_bb_reg(pAdapter, rFPGA0_XAB_RFParameter, BIT1, 1);
1310                                 phy_set_bb_reg(pAdapter, rFPGA0_XAB_RFParameter, BIT17, 0);
1311                         }
1312                 }
1313                 pMptCtx->mpt_rf_path = ODM_RF_PATH_A;
1314                 break;
1315         case ANTENNA_B:
1316                 p_ofdm_tx->r_tx_antenna         = 0x2;
1317                 r_ofdm_tx_en_val                = 0x2;
1318                 p_ofdm_tx->r_ant_l              = 0x2;
1319                 p_ofdm_tx->r_ant_ht_s1          = 0x2;
1320                 p_ofdm_tx->r_ant_non_ht_s1      = 0x2;
1321                 p_cck_txrx->r_ccktx_enable      = 0x4;
1322                 chgTx = 1;
1323                 /*/ From SD3 Willis suggestion !!! Set RF A as standby*/
1324                 /*/if (IS_HARDWARE_TYPE_8192S(pAdapter))*/
1325                 {
1326                         phy_set_bb_reg(pAdapter, rFPGA0_XA_HSSIParameter2, 0xe, 1);
1327                         phy_set_bb_reg(pAdapter, rFPGA0_XB_HSSIParameter2, 0xe, 2);
1328
1329                         /*/ 2008/10/31 MH From SD3 Willi's suggestion. We must read RF 1T table.*/
1330                         /*/ 2009/01/08 MH From Sd3 Willis. We need to close RFA by SW control*/
1331                         if (pHalData->rf_type == RF_2T2R || pHalData->rf_type == RF_1T2R) {
1332                                 phy_set_bb_reg(pAdapter, rFPGA0_XAB_RFInterfaceSW, BIT10, 1);
1333                                 phy_set_bb_reg(pAdapter, rFPGA0_XA_RFInterfaceOE, BIT10, 0);
1334                                 phy_set_bb_reg(pAdapter, rFPGA0_XAB_RFInterfaceSW, BIT26, 0);
1335                                 /*/phy_set_bb_reg(pAdapter, rFPGA0_XB_RFInterfaceOE, BIT10, 0);*/
1336                                 phy_set_bb_reg(pAdapter, rFPGA0_XAB_RFParameter, BIT1, 0);
1337                                 phy_set_bb_reg(pAdapter, rFPGA0_XAB_RFParameter, BIT17, 1);
1338                         }
1339                 }
1340                 pMptCtx->mpt_rf_path = ODM_RF_PATH_B;
1341                 break;
1342         case ANTENNA_AB:/*/ For 8192S*/
1343                 p_ofdm_tx->r_tx_antenna         = 0x3;
1344                 r_ofdm_tx_en_val                = 0x3;
1345                 p_ofdm_tx->r_ant_l              = 0x3;
1346                 p_ofdm_tx->r_ant_ht_s1          = 0x3;
1347                 p_ofdm_tx->r_ant_non_ht_s1      = 0x3;
1348                 p_cck_txrx->r_ccktx_enable      = 0xC;
1349                 chgTx = 1;
1350                 /*/ From SD3Willis suggestion !!! Set RF B as standby*/
1351                 /*/if (IS_HARDWARE_TYPE_8192S(pAdapter))*/
1352                 {
1353                         phy_set_bb_reg(pAdapter, rFPGA0_XA_HSSIParameter2, 0xe, 2);
1354                         phy_set_bb_reg(pAdapter, rFPGA0_XB_HSSIParameter2, 0xe, 2);
1355                         /* Disable Power save*/
1356                         /*cosa r_ant_select_ofdm_val = 0x3321333;*/
1357                         /* 2009/01/08 MH From Sd3 Willis. We need to enable RFA/B by SW control*/
1358                         if (pHalData->rf_type == RF_2T2R) {
1359                                 phy_set_bb_reg(pAdapter, rFPGA0_XAB_RFInterfaceSW, BIT10, 0);
1360
1361                                 phy_set_bb_reg(pAdapter, rFPGA0_XAB_RFInterfaceSW, BIT26, 0);
1362                                 /*/phy_set_bb_reg(pAdapter, rFPGA0_XB_RFInterfaceOE, BIT10, 0);*/
1363                                 phy_set_bb_reg(pAdapter, rFPGA0_XAB_RFParameter, BIT1, 1);
1364                                 phy_set_bb_reg(pAdapter, rFPGA0_XAB_RFParameter, BIT17, 1);
1365                         }
1366                 }
1367                 pMptCtx->mpt_rf_path = ODM_RF_PATH_AB;
1368                 break;
1369         default:
1370                 break;
1371         }
1372 #if 0
1373         /*  r_rx_antenna_ofdm, bit0=A, bit1=B, bit2=C, bit3=D */
1374         /*  r_cckrx_enable : CCK default, 0=A, 1=B, 2=C, 3=D */
1375         /* r_cckrx_enable_2 : CCK option, 0=A, 1=B, 2=C, 3=D     */
1376 #endif
1377         switch (ulAntennaRx) {
1378         case ANTENNA_A:
1379                 r_rx_antenna_ofdm               = 0x1;  /* A*/
1380                 p_cck_txrx->r_cckrx_enable      = 0x0;  /* default: A*/
1381                 p_cck_txrx->r_cckrx_enable_2    = 0x0;  /* option: A*/
1382                 chgRx = 1;
1383                 break;
1384         case ANTENNA_B:
1385                 r_rx_antenna_ofdm                       = 0x2;  /*/ B*/
1386                 p_cck_txrx->r_cckrx_enable      = 0x1;  /*/ default: B*/
1387                 p_cck_txrx->r_cckrx_enable_2    = 0x1;  /*/ option: B*/
1388                 chgRx = 1;
1389                 break;
1390         case ANTENNA_AB:/*/ For 8192S and 8192E/U...*/
1391                 r_rx_antenna_ofdm               = 0x3;/*/ AB*/
1392                 p_cck_txrx->r_cckrx_enable      = 0x0;/*/ default:A*/
1393                 p_cck_txrx->r_cckrx_enable_2    = 0x1;/*/ option:B*/
1394                 chgRx = 1;
1395                 break;
1396         default:
1397                 break;
1398         }
1399
1400
1401         if (chgTx && chgRx) {
1402                 switch (pHalData->rf_chip) {
1403                 case RF_8225:
1404                 case RF_8256:
1405                 case RF_6052:
1406                         /*/r_ant_sel_cck_val = r_ant_select_cck_val;*/
1407                         phy_set_bb_reg(pAdapter, rFPGA1_TxInfo, 0x7fffffff, r_ant_select_ofdm_val);             /*/OFDM Tx*/
1408                         phy_set_bb_reg(pAdapter, rFPGA0_TxInfo, 0x0000000f, r_ofdm_tx_en_val);          /*/OFDM Tx*/
1409                         phy_set_bb_reg(pAdapter, rOFDM0_TRxPathEnable, 0x0000000f, r_rx_antenna_ofdm);  /*/OFDM Rx*/
1410                         phy_set_bb_reg(pAdapter, rOFDM1_TRxPathEnable, 0x0000000f, r_rx_antenna_ofdm);  /*/OFDM Rx*/
1411                         if (IS_HARDWARE_TYPE_8192E(pAdapter)) {
1412                                 phy_set_bb_reg(pAdapter, rOFDM0_TRxPathEnable, 0x000000F0, r_rx_antenna_ofdm);  /*/OFDM Rx*/
1413                                 phy_set_bb_reg(pAdapter, rOFDM1_TRxPathEnable, 0x000000F0, r_rx_antenna_ofdm);  /*/OFDM Rx*/
1414                         }
1415                         phy_set_bb_reg(pAdapter, rCCK0_AFESetting, bMaskByte3, r_ant_select_cck_val);/*/r_ant_sel_cck_val); /CCK TxRx*/
1416                         break;
1417
1418                 default:
1419                         RTW_INFO("Unsupported RFChipID for switching antenna.\n");
1420                         break;
1421                 }
1422         }
1423 }       /* MPT_ProSetRFPath */
1424
1425
1426 void hal_mpt_SetAntenna(PADAPTER        pAdapter)
1427
1428 {
1429         RTW_INFO("Do %s\n", __func__);
1430 #ifdef CONFIG_RTL8814A
1431         if (IS_HARDWARE_TYPE_8814A(pAdapter)) {
1432                 mpt_SetRFPath_8814A(pAdapter);
1433                 return;
1434         }
1435 #endif
1436 #ifdef CONFIG_RTL8822B
1437         if (IS_HARDWARE_TYPE_8822B(pAdapter)) {
1438                 rtl8822b_mp_config_rfpath(pAdapter);
1439                 return;
1440         }
1441 #endif
1442 #ifdef CONFIG_RTL8821C
1443         if (IS_HARDWARE_TYPE_8821C(pAdapter)) {
1444                 rtl8821c_mp_config_rfpath(pAdapter);
1445                 return;
1446         }
1447 #endif
1448 #if     defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A)
1449         if (IS_HARDWARE_TYPE_JAGUAR(pAdapter)) {
1450                 mpt_SetRFPath_8812A(pAdapter);
1451                 return;
1452         }
1453 #endif
1454 #ifdef CONFIG_RTL8723B
1455         if (IS_HARDWARE_TYPE_8723B(pAdapter)) {
1456                 mpt_SetRFPath_8723B(pAdapter);
1457                 return;
1458         }
1459 #endif
1460
1461 #ifdef CONFIG_RTL8703B
1462         if (IS_HARDWARE_TYPE_8703B(pAdapter)) {
1463                 mpt_SetRFPath_8703B(pAdapter);
1464                 return;
1465         }
1466 #endif
1467
1468 #ifdef CONFIG_RTL8723D
1469         if (IS_HARDWARE_TYPE_8723D(pAdapter)) {
1470                 mpt_SetRFPath_8723D(pAdapter);
1471                 return;
1472         }
1473 #endif
1474         /*      else if (IS_HARDWARE_TYPE_8821B(pAdapter))
1475                         mpt_SetRFPath_8821B(pAdapter);
1476                 Prepare for 8822B
1477                 else if (IS_HARDWARE_TYPE_8822B(Context))
1478                         mpt_SetRFPath_8822B(Context);
1479         */
1480         mpt_SetRFPath_819X(pAdapter);
1481         RTW_INFO("mpt_SetRFPath_819X Do %s\n", __func__);
1482 }
1483
1484 s32 hal_mpt_SetThermalMeter(PADAPTER pAdapter, u8 target_ther)
1485 {
1486         HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
1487
1488         if (!netif_running(pAdapter->pnetdev)) {
1489                 return _FAIL;
1490         }
1491
1492
1493         if (check_fwstate(&pAdapter->mlmepriv, WIFI_MP_STATE) == _FALSE) {
1494                 return _FAIL;
1495         }
1496
1497
1498         target_ther &= 0xff;
1499         if (target_ther < 0x07)
1500                 target_ther = 0x07;
1501         else if (target_ther > 0x1d)
1502                 target_ther = 0x1d;
1503
1504         pHalData->eeprom_thermal_meter = target_ther;
1505
1506         return _SUCCESS;
1507 }
1508
1509
1510 void hal_mpt_TriggerRFThermalMeter(PADAPTER pAdapter)
1511 {
1512         phy_set_rf_reg(pAdapter, ODM_RF_PATH_A, 0x42, BIT17 | BIT16, 0x03);
1513
1514 }
1515
1516
1517 u8 hal_mpt_ReadRFThermalMeter(PADAPTER pAdapter)
1518
1519 {
1520         u32 ThermalValue = 0;
1521
1522         ThermalValue = (u1Byte)phy_query_rf_reg(pAdapter, ODM_RF_PATH_A, 0x42, 0xfc00); /*0x42: RF Reg[15:10]*/
1523         return (u8)ThermalValue;
1524
1525 }
1526
1527
1528 void hal_mpt_GetThermalMeter(PADAPTER pAdapter, u8 *value)
1529 {
1530 #if 0
1531         fw_cmd(pAdapter, IOCMD_GET_THERMAL_METER);
1532         rtw_msleep_os(1000);
1533         fw_cmd_data(pAdapter, value, 1);
1534         *value &= 0xFF;
1535 #else
1536         hal_mpt_TriggerRFThermalMeter(pAdapter);
1537         rtw_msleep_os(1000);
1538         *value = hal_mpt_ReadRFThermalMeter(pAdapter);
1539 #endif
1540
1541 }
1542
1543
1544 void hal_mpt_SetSingleCarrierTx(PADAPTER pAdapter, u8 bStart)
1545 {
1546         HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
1547
1548         pAdapter->mppriv.mpt_ctx.bSingleCarrier = bStart;
1549
1550         if (bStart) {/*/ Start Single Carrier.*/
1551                 /*/ Start Single Carrier.*/
1552                 /*/ 1. if OFDM block on?*/
1553                 if (!phy_query_bb_reg(pAdapter, rFPGA0_RFMOD, bOFDMEn))
1554                         phy_set_bb_reg(pAdapter, rFPGA0_RFMOD, bOFDMEn, 1); /*set OFDM block on*/
1555
1556                 /*/ 2. set CCK test mode off, set to CCK normal mode*/
1557                 phy_set_bb_reg(pAdapter, rCCK0_System, bCCKBBMode, 0);
1558
1559                 /*/ 3. turn on scramble setting*/
1560                 phy_set_bb_reg(pAdapter, rCCK0_System, bCCKScramble, 1);
1561
1562                 /*/ 4. Turn On Continue Tx and turn off the other test modes.*/
1563 #if defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A) || defined(CONFIG_RTL8814A) || defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8821C)
1564                 if (IS_HARDWARE_TYPE_JAGUAR_AND_JAGUAR2(pAdapter))
1565                         phy_set_bb_reg(pAdapter, rSingleTone_ContTx_Jaguar, BIT18 | BIT17 | BIT16, OFDM_SingleCarrier);
1566                 else
1567 #endif /* CONFIG_RTL8812A || CONFIG_RTL8821A || CONFIG_RTL8814A || CONFIG_RTL8822B || CONFIG_RTL8821C */
1568                         phy_set_bb_reg(pAdapter, rOFDM1_LSTF, BIT30 | BIT29 | BIT28, OFDM_SingleCarrier);
1569
1570         } else {
1571                 /*/ Stop Single Carrier.*/
1572                 /*/ Stop Single Carrier.*/
1573                 /*/ Turn off all test modes.*/
1574 #if defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A) || defined(CONFIG_RTL8814A) || defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8821C)
1575                 if (IS_HARDWARE_TYPE_JAGUAR_AND_JAGUAR2(pAdapter))
1576                         phy_set_bb_reg(pAdapter, rSingleTone_ContTx_Jaguar, BIT18 | BIT17 | BIT16, OFDM_ALL_OFF);
1577                 else
1578 #endif /* CONFIG_RTL8812A || CONFIG_RTL8821A || CONFIG_RTL8814A || CONFIG_RTL8822B || CONFIG_RTL8821C */
1579                         phy_set_bb_reg(pAdapter, rOFDM1_LSTF, BIT30 | BIT29 | BIT28, OFDM_ALL_OFF);
1580
1581                 rtw_msleep_os(10);
1582                 /*/BB Reset*/
1583                 phy_set_bb_reg(pAdapter, rPMAC_Reset, bBBResetB, 0x0);
1584                 phy_set_bb_reg(pAdapter, rPMAC_Reset, bBBResetB, 0x1);
1585         }
1586 }
1587
1588
1589 void hal_mpt_SetSingleToneTx(PADAPTER pAdapter, u8 bStart)
1590 {
1591         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(pAdapter);
1592         PMPT_CONTEXT            pMptCtx = &(pAdapter->mppriv.mpt_ctx);
1593         u4Byte                  ulAntennaTx = pHalData->antenna_tx_path;
1594         static u4Byte           regRF = 0, regBB0 = 0, regBB1 = 0, regBB2 = 0, regBB3 = 0;
1595         u8 rfPath;
1596
1597         switch (ulAntennaTx) {
1598         case ANTENNA_B:
1599                 rfPath = ODM_RF_PATH_B;
1600                 break;
1601         case ANTENNA_C:
1602                 rfPath = ODM_RF_PATH_C;
1603                 break;
1604         case ANTENNA_D:
1605                 rfPath = ODM_RF_PATH_D;
1606                 break;
1607         case ANTENNA_A:
1608         default:
1609                 rfPath = ODM_RF_PATH_A;
1610                 break;
1611         }
1612
1613         pAdapter->mppriv.mpt_ctx.is_single_tone = bStart;
1614         if (bStart) {
1615                 /*/ Start Single Tone.*/
1616                 /*/ <20120326, Kordan> To amplify the power of tone for Xtal calibration. (asked by Edlu)*/
1617                 if (IS_HARDWARE_TYPE_8188E(pAdapter)) {
1618                         regRF = phy_query_rf_reg(pAdapter, rfPath, lna_low_gain_3, bRFRegOffsetMask);
1619                         phy_set_rf_reg(pAdapter, ODM_RF_PATH_A, lna_low_gain_3, BIT1, 0x1); /*/ RF LO enabled*/
1620                         phy_set_bb_reg(pAdapter, rFPGA0_RFMOD, bCCKEn, 0x0);
1621                         phy_set_bb_reg(pAdapter, rFPGA0_RFMOD, bOFDMEn, 0x0);
1622                 } else if (IS_HARDWARE_TYPE_8192E(pAdapter)) { /*/ USB need to do RF LO disable first, PCIE isn't required to follow this order.*/
1623                         /*/Set MAC REG 88C: Prevent SingleTone Fail*/
1624                         phy_set_mac_reg(pAdapter, 0x88C, 0xF00000, 0xF);
1625                         phy_set_rf_reg(pAdapter, pMptCtx->mpt_rf_path, lna_low_gain_3, BIT1, 0x1); /*/ RF LO disabled*/
1626                         phy_set_rf_reg(pAdapter, pMptCtx->mpt_rf_path, RF_AC, 0xF0000, 0x2); /*/ Tx mode*/
1627                 } else if (IS_HARDWARE_TYPE_8723B(pAdapter)) {
1628                         if (pMptCtx->mpt_rf_path == ODM_RF_PATH_A) {
1629                                 phy_set_rf_reg(pAdapter, ODM_RF_PATH_A, RF_AC, 0xF0000, 0x2); /*/ Tx mode*/
1630                                 phy_set_rf_reg(pAdapter, ODM_RF_PATH_A, 0x56, 0xF, 0x1); /*/ RF LO enabled*/
1631                         } else {
1632                                 /*/ S0/S1 both use PATH A to configure*/
1633                                 phy_set_rf_reg(pAdapter, ODM_RF_PATH_A, RF_AC, 0xF0000, 0x2); /*/ Tx mode*/
1634                                 phy_set_rf_reg(pAdapter, ODM_RF_PATH_A, 0x76, 0xF, 0x1); /*/ RF LO enabled*/
1635                         }
1636                 } else if (IS_HARDWARE_TYPE_8703B(pAdapter)) {
1637                         if (pMptCtx->mpt_rf_path == ODM_RF_PATH_A) {
1638                                 phy_set_rf_reg(pAdapter, ODM_RF_PATH_A, RF_AC, 0xF0000, 0x2); /* Tx mode */
1639                                 phy_set_rf_reg(pAdapter, ODM_RF_PATH_A, 0x53, 0xF000, 0x1); /* RF LO enabled */
1640                         }
1641                 } else if (IS_HARDWARE_TYPE_8188F(pAdapter)) {
1642                         /*Set BB REG 88C: Prevent SingleTone Fail*/
1643                         phy_set_bb_reg(pAdapter, rFPGA0_AnalogParameter4, 0xF00000, 0xF);
1644                         phy_set_rf_reg(pAdapter, pMptCtx->mpt_rf_path, lna_low_gain_3, BIT1, 0x1);
1645                         phy_set_rf_reg(pAdapter, pMptCtx->mpt_rf_path, RF_AC, 0xF0000, 0x2);
1646
1647                 } else if (IS_HARDWARE_TYPE_8723D(pAdapter)) {
1648                         if (pMptCtx->mpt_rf_path == ODM_RF_PATH_A) {
1649                                 phy_set_bb_reg(pAdapter, rFPGA0_RFMOD, bCCKEn|bOFDMEn, 0);
1650                                 phy_set_rf_reg(pAdapter, ODM_RF_PATH_A, RF_AC, BIT16, 0x0);
1651                                 phy_set_rf_reg(pAdapter, ODM_RF_PATH_A, 0x53, BIT0, 0x1);
1652                         } else {/* S0/S1 both use PATH A to configure */
1653                                 phy_set_bb_reg(pAdapter, rFPGA0_RFMOD, bCCKEn|bOFDMEn, 0);
1654                                 phy_set_rf_reg(pAdapter, ODM_RF_PATH_A, RF_AC, BIT16, 0x0);
1655                                 phy_set_rf_reg(pAdapter, ODM_RF_PATH_A, 0x63, BIT0, 0x1);
1656                         }
1657                 } else if (IS_HARDWARE_TYPE_JAGUAR(pAdapter) || IS_HARDWARE_TYPE_8822B(pAdapter)) {
1658 #if defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A) || defined(CONFIG_RTL8822B)
1659                         u1Byte p = ODM_RF_PATH_A;
1660
1661                         regRF = phy_query_rf_reg(pAdapter, ODM_RF_PATH_A, RF_AC_Jaguar, bRFRegOffsetMask);
1662                         regBB0 = phy_query_bb_reg(pAdapter, rA_RFE_Pinmux_Jaguar, bMaskDWord);
1663                         regBB1 = phy_query_bb_reg(pAdapter, rB_RFE_Pinmux_Jaguar, bMaskDWord);
1664                         regBB2 = phy_query_bb_reg(pAdapter, rA_RFE_Pinmux_Jaguar + 4, bMaskDWord);
1665                         regBB3 = phy_query_bb_reg(pAdapter, rB_RFE_Pinmux_Jaguar + 4, bMaskDWord);
1666
1667                         phy_set_bb_reg(pAdapter, rOFDMCCKEN_Jaguar, BIT29 | BIT28, 0x0); /*/ Disable CCK and OFDM*/
1668
1669                         if (pMptCtx->mpt_rf_path == ODM_RF_PATH_AB) {
1670                                 for (p = ODM_RF_PATH_A; p <= ODM_RF_PATH_B; ++p) {
1671                                         phy_set_rf_reg(pAdapter, p, RF_AC_Jaguar, 0xF0000, 0x2); /*/ Tx mode: RF0x00[19:16]=4'b0010 */
1672                                         phy_set_rf_reg(pAdapter, p, RF_AC_Jaguar, 0x1F, 0x0); /*/ Lowest RF gain index: RF_0x0[4:0] = 0*/
1673                                         phy_set_rf_reg(pAdapter, p, lna_low_gain_3, BIT1, 0x1); /*/ RF LO enabled*/
1674                                 }
1675                         } else {
1676                                 phy_set_rf_reg(pAdapter, pMptCtx->mpt_rf_path, RF_AC_Jaguar, 0xF0000, 0x2); /*/ Tx mode: RF0x00[19:16]=4'b0010 */
1677                                 phy_set_rf_reg(pAdapter, pMptCtx->mpt_rf_path, RF_AC_Jaguar, 0x1F, 0x0); /*/ Lowest RF gain index: RF_0x0[4:0] = 0*/
1678                                 phy_set_rf_reg(pAdapter, pMptCtx->mpt_rf_path, lna_low_gain_3, BIT1, 0x1); /*/ RF LO enabled*/
1679                         }
1680
1681                         phy_set_bb_reg(pAdapter, rA_RFE_Pinmux_Jaguar, 0xFF00F0, 0x77007);  /*/ 0xCB0[[23:16, 7:4] = 0x77007*/
1682                         phy_set_bb_reg(pAdapter, rB_RFE_Pinmux_Jaguar, 0xFF00F0, 0x77007);  /*/ 0xCB0[[23:16, 7:4] = 0x77007*/
1683
1684                         if (pHalData->external_pa_5g) {
1685                                 phy_set_bb_reg(pAdapter, rA_RFE_Pinmux_Jaguar + 4, 0xFF00000, 0x12); /*/ 0xCB4[23:16] = 0x12*/
1686                                 phy_set_bb_reg(pAdapter, rB_RFE_Pinmux_Jaguar + 4, 0xFF00000, 0x12); /*/ 0xEB4[23:16] = 0x12*/
1687                         } else if (pHalData->ExternalPA_2G) {
1688                                 phy_set_bb_reg(pAdapter, rA_RFE_Pinmux_Jaguar + 4, 0xFF00000, 0x11); /*/ 0xCB4[23:16] = 0x11*/
1689                                 phy_set_bb_reg(pAdapter, rB_RFE_Pinmux_Jaguar + 4, 0xFF00000, 0x11); /*/ 0xEB4[23:16] = 0x11*/
1690                         }
1691 #endif
1692                 }
1693 #if defined(CONFIG_RTL8814A) || defined(CONFIG_RTL8821C)
1694                                 else if (IS_HARDWARE_TYPE_8814A(pAdapter) || IS_HARDWARE_TYPE_8821C(pAdapter))
1695                                                 mpt_SetSingleTone_8814A(pAdapter, TRUE, FALSE);
1696 #endif
1697
1698                 else    /*/ Turn On SingleTone and turn off the other test modes.*/
1699                         phy_set_bb_reg(pAdapter, rOFDM1_LSTF, BIT30 | BIT29 | BIT28, OFDM_SingleTone);
1700
1701                 write_bbreg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000500);
1702                 write_bbreg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000500);
1703
1704         } else {/*/ Stop Single Ton e.*/
1705
1706                 if (IS_HARDWARE_TYPE_8188E(pAdapter)) {
1707                         phy_set_rf_reg(pAdapter, ODM_RF_PATH_A, lna_low_gain_3, bRFRegOffsetMask, regRF);
1708                         phy_set_bb_reg(pAdapter, rFPGA0_RFMOD, bCCKEn, 0x1);
1709                         phy_set_bb_reg(pAdapter, rFPGA0_RFMOD, bOFDMEn, 0x1);
1710                 } else if (IS_HARDWARE_TYPE_8192E(pAdapter)) {
1711                         phy_set_rf_reg(pAdapter, pMptCtx->mpt_rf_path, RF_AC, 0xF0000, 0x3);/*/ Tx mode*/
1712                         phy_set_rf_reg(pAdapter, pMptCtx->mpt_rf_path, lna_low_gain_3, BIT1, 0x0);/*/ RF LO disabled */
1713                         /*/ RESTORE MAC REG 88C: Enable RF Functions*/
1714                         phy_set_mac_reg(pAdapter, 0x88C, 0xF00000, 0x0);
1715                 } else if (IS_HARDWARE_TYPE_8723B(pAdapter)) {
1716                         if (pMptCtx->mpt_rf_path == ODM_RF_PATH_A) {
1717                                 phy_set_rf_reg(pAdapter, ODM_RF_PATH_A, RF_AC, 0xF0000, 0x3); /*/ Rx mode*/
1718                                 phy_set_rf_reg(pAdapter, ODM_RF_PATH_A, 0x56, 0xF, 0x0); /*/ RF LO disabled*/
1719                         } else {
1720                                 /*/ S0/S1 both use PATH A to configure*/
1721                                 phy_set_rf_reg(pAdapter, ODM_RF_PATH_A, RF_AC, 0xF0000, 0x3); /*/ Rx mode*/
1722                                 phy_set_rf_reg(pAdapter, ODM_RF_PATH_A, 0x76, 0xF, 0x0); /*/ RF LO disabled*/
1723                         }
1724                 } else if (IS_HARDWARE_TYPE_8703B(pAdapter)) {
1725                         if (pMptCtx->mpt_rf_path == ODM_RF_PATH_A) {
1726                                 phy_set_rf_reg(pAdapter, ODM_RF_PATH_A, RF_AC, 0xF0000, 0x3); /* Rx mode */
1727                                 phy_set_rf_reg(pAdapter, ODM_RF_PATH_A, 0x53, 0xF000, 0x0); /* RF LO disabled */
1728                         }
1729                 } else if (IS_HARDWARE_TYPE_8188F(pAdapter)) {
1730                         phy_set_rf_reg(pAdapter, pMptCtx->mpt_rf_path, RF_AC, 0xF0000, 0x3); /*Tx mode*/
1731                         phy_set_rf_reg(pAdapter, pMptCtx->mpt_rf_path, lna_low_gain_3, BIT1, 0x0); /*RF LO disabled*/
1732                         /*Set BB REG 88C: Prevent SingleTone Fail*/
1733                         phy_set_bb_reg(pAdapter, rFPGA0_AnalogParameter4, 0xF00000, 0xc);
1734                 } else if (IS_HARDWARE_TYPE_8723D(pAdapter)) {
1735                         if (pMptCtx->mpt_rf_path == ODM_RF_PATH_A) {
1736                                 phy_set_bb_reg(pAdapter, rFPGA0_RFMOD, bCCKEn|bOFDMEn, 0x3);
1737                                 phy_set_rf_reg(pAdapter, ODM_RF_PATH_A, RF_AC, BIT16, 0x1);
1738                                 phy_set_rf_reg(pAdapter, ODM_RF_PATH_A, 0x53, BIT0, 0x0);
1739                         } else {        /* S0/S1 both use PATH A to configure */
1740                                 phy_set_bb_reg(pAdapter, rFPGA0_RFMOD, bCCKEn|bOFDMEn, 0x3);
1741                                 phy_set_rf_reg(pAdapter, ODM_RF_PATH_A, RF_AC, BIT16, 0x1);
1742                                 phy_set_rf_reg(pAdapter, ODM_RF_PATH_A, 0x63, BIT0, 0x0);
1743                         }
1744                 } else if (IS_HARDWARE_TYPE_JAGUAR(pAdapter) || IS_HARDWARE_TYPE_8822B(pAdapter)) {
1745 #if defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A) || defined(CONFIG_RTL8822B)
1746                         u1Byte p = ODM_RF_PATH_A;
1747
1748                         phy_set_bb_reg(pAdapter, rOFDMCCKEN_Jaguar, BIT29 | BIT28, 0x3); /*/ Disable CCK and OFDM*/
1749
1750                         if (pMptCtx->mpt_rf_path == ODM_RF_PATH_AB) {
1751                                 for (p = ODM_RF_PATH_A; p <= ODM_RF_PATH_B; ++p) {
1752                                         phy_set_rf_reg(pAdapter, p, RF_AC_Jaguar, bRFRegOffsetMask, regRF);
1753                                         phy_set_rf_reg(pAdapter, p, lna_low_gain_3, BIT1, 0x0); /*/ RF LO disabled*/
1754                                 }
1755                         } else {
1756                                 phy_set_rf_reg(pAdapter, p, RF_AC_Jaguar, bRFRegOffsetMask, regRF);
1757                                 phy_set_rf_reg(pAdapter, p, lna_low_gain_3, BIT1, 0x0); /*/ RF LO disabled*/
1758                         }
1759
1760                         phy_set_bb_reg(pAdapter, rA_RFE_Pinmux_Jaguar, bMaskDWord, regBB0);
1761                         phy_set_bb_reg(pAdapter, rB_RFE_Pinmux_Jaguar, bMaskDWord, regBB1);
1762                         phy_set_bb_reg(pAdapter, rA_RFE_Pinmux_Jaguar + 4, bMaskDWord, regBB2);
1763                         phy_set_bb_reg(pAdapter, rB_RFE_Pinmux_Jaguar + 4, bMaskDWord, regBB3);
1764 #endif
1765                 }
1766 #if defined(CONFIG_RTL8814A) || defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8821C)
1767                 else if (IS_HARDWARE_TYPE_8814A(pAdapter) || IS_HARDWARE_TYPE_8821C(pAdapter))
1768                         mpt_SetSingleTone_8814A(pAdapter, FALSE, FALSE);
1769
1770                 else/*/ Turn off all test modes.*/
1771                         phy_set_bb_reg(pAdapter, rSingleTone_ContTx_Jaguar, BIT18 | BIT17 | BIT16, OFDM_ALL_OFF);
1772 #endif
1773                 write_bbreg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000100);
1774                 write_bbreg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000100);
1775
1776         }
1777 }
1778
1779 void hal_mpt_SetCarrierSuppressionTx(PADAPTER pAdapter, u8 bStart)
1780 {
1781         u8 Rate;
1782
1783         pAdapter->mppriv.mpt_ctx.is_carrier_suppression = bStart;
1784
1785         Rate = HwRateToMPTRate(pAdapter->mppriv.rateidx);
1786         if (bStart) {/* Start Carrier Suppression.*/
1787                 if (Rate <= MPT_RATE_11M) {
1788                         /*/ 1. if CCK block on?*/
1789                         if (!read_bbreg(pAdapter, rFPGA0_RFMOD, bCCKEn))
1790                                 write_bbreg(pAdapter, rFPGA0_RFMOD, bCCKEn, bEnable);/*set CCK block on*/
1791
1792                         /*/Turn Off All Test Mode*/
1793                         if (IS_HARDWARE_TYPE_JAGUAR(pAdapter) || IS_HARDWARE_TYPE_8814A(pAdapter) /*|| IS_HARDWARE_TYPE_8822B(pAdapter)*/)
1794                                 phy_set_bb_reg(pAdapter, 0x914, BIT18 | BIT17 | BIT16, OFDM_ALL_OFF); /* rSingleTone_ContTx_Jaguar*/
1795                         else
1796                                 phy_set_bb_reg(pAdapter, rOFDM1_LSTF, BIT30 | BIT29 | BIT28, OFDM_ALL_OFF);
1797
1798                         write_bbreg(pAdapter, rCCK0_System, bCCKBBMode, 0x2);    /*/transmit mode*/
1799                         write_bbreg(pAdapter, rCCK0_System, bCCKScramble, 0x0);  /*/turn off scramble setting*/
1800
1801                         /*/Set CCK Tx Test Rate*/
1802                         write_bbreg(pAdapter, rCCK0_System, bCCKTxRate, 0x0);    /*/Set FTxRate to 1Mbps*/
1803                 }
1804
1805                 /*Set for dynamic set Power index*/
1806                 write_bbreg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000500);
1807                 write_bbreg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000500);
1808
1809         } else {/* Stop Carrier Suppression.*/
1810
1811                 if (Rate <= MPT_RATE_11M) {
1812                         write_bbreg(pAdapter, rCCK0_System, bCCKBBMode, 0x0);    /*normal mode*/
1813                         write_bbreg(pAdapter, rCCK0_System, bCCKScramble, 0x1);  /*turn on scramble setting*/
1814
1815                         /*BB Reset*/
1816                         write_bbreg(pAdapter, rPMAC_Reset, bBBResetB, 0x0);
1817                         write_bbreg(pAdapter, rPMAC_Reset, bBBResetB, 0x1);
1818                 }
1819                 /*Stop for dynamic set Power index*/
1820                 write_bbreg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000100);
1821                 write_bbreg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000100);
1822         }
1823         RTW_INFO("\n MPT_ProSetCarrierSupp() is finished.\n");
1824 }
1825
1826 u32 hal_mpt_query_phytxok(PADAPTER      pAdapter)
1827 {
1828         PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.mpt_ctx);
1829         RT_PMAC_TX_INFO PMacTxInfo = pMptCtx->PMacTxInfo;
1830         u16 count = 0;
1831
1832         if (IS_MPT_CCK_RATE(PMacTxInfo.TX_RATE))
1833                 count = phy_query_bb_reg(pAdapter, 0xF50, bMaskLWord); /* [15:0]*/
1834         else
1835                 count = phy_query_bb_reg(pAdapter, 0xF50, bMaskHWord); /* [31:16]*/
1836
1837         if (count > 50000) {
1838                 rtw_reset_phy_trx_ok_counters(pAdapter);
1839                 pAdapter->mppriv.tx.sended += count;
1840                 count = 0;
1841         }
1842
1843         return pAdapter->mppriv.tx.sended + count;
1844
1845 }
1846
1847 static  VOID mpt_StopCckContTx(
1848         PADAPTER        pAdapter
1849 )
1850 {
1851         HAL_DATA_TYPE   *pHalData       = GET_HAL_DATA(pAdapter);
1852         PMPT_CONTEXT    pMptCtx = &(pAdapter->mppriv.mpt_ctx);
1853         u1Byte                  u1bReg;
1854
1855         pMptCtx->bCckContTx = FALSE;
1856         pMptCtx->bOfdmContTx = FALSE;
1857
1858         phy_set_bb_reg(pAdapter, rCCK0_System, bCCKBBMode, 0x0);        /*normal mode*/
1859         phy_set_bb_reg(pAdapter, rCCK0_System, bCCKScramble, 0x1);      /*turn on scramble setting*/
1860
1861         if (!IS_HARDWARE_TYPE_JAGUAR2(pAdapter)) {
1862                 phy_set_bb_reg(pAdapter, 0xa14, 0x300, 0x0);                    /* 0xa15[1:0] = 2b00*/
1863                 phy_set_bb_reg(pAdapter, rOFDM0_TRMuxPar, 0x10000, 0x0);                /* 0xc08[16] = 0*/
1864
1865                 phy_set_bb_reg(pAdapter, rFPGA0_XA_HSSIParameter2, BIT14, 0);
1866                 phy_set_bb_reg(pAdapter, rFPGA0_XB_HSSIParameter2, BIT14, 0);
1867                 phy_set_bb_reg(pAdapter, 0x0B34, BIT14, 0);
1868         }
1869
1870         /*BB Reset*/
1871         phy_set_bb_reg(pAdapter, rPMAC_Reset, bBBResetB, 0x0);
1872         phy_set_bb_reg(pAdapter, rPMAC_Reset, bBBResetB, 0x1);
1873
1874         phy_set_bb_reg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000100);
1875         phy_set_bb_reg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000100);
1876
1877 }       /* mpt_StopCckContTx */
1878
1879
1880 static  VOID mpt_StopOfdmContTx(
1881         PADAPTER        pAdapter
1882 )
1883 {
1884         HAL_DATA_TYPE   *pHalData       = GET_HAL_DATA(pAdapter);
1885         PMPT_CONTEXT    pMptCtx = &(pAdapter->mppriv.mpt_ctx);
1886         u1Byte                  u1bReg;
1887         u4Byte                  data;
1888
1889         pMptCtx->bCckContTx = FALSE;
1890         pMptCtx->bOfdmContTx = FALSE;
1891
1892         if (IS_HARDWARE_TYPE_JAGUAR(pAdapter) || IS_HARDWARE_TYPE_JAGUAR2(pAdapter))
1893                 phy_set_bb_reg(pAdapter, 0x914, BIT18 | BIT17 | BIT16, OFDM_ALL_OFF);
1894         else
1895                 phy_set_bb_reg(pAdapter, rOFDM1_LSTF, BIT30 | BIT29 | BIT28, OFDM_ALL_OFF);
1896
1897         rtw_mdelay_os(10);
1898
1899         if (!IS_HARDWARE_TYPE_JAGUAR(pAdapter) && !IS_HARDWARE_TYPE_JAGUAR2(pAdapter)) {
1900                 phy_set_bb_reg(pAdapter, 0xa14, 0x300, 0x0);                    /* 0xa15[1:0] = 0*/
1901                 phy_set_bb_reg(pAdapter, rOFDM0_TRMuxPar, 0x10000, 0x0);                /* 0xc08[16] = 0*/
1902         }
1903
1904         /*BB Reset*/
1905         phy_set_bb_reg(pAdapter, rPMAC_Reset, bBBResetB, 0x0);
1906         phy_set_bb_reg(pAdapter, rPMAC_Reset, bBBResetB, 0x1);
1907
1908         phy_set_bb_reg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000100);
1909         phy_set_bb_reg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000100);
1910 }       /* mpt_StopOfdmContTx */
1911
1912
1913 static  VOID mpt_StartCckContTx(
1914         PADAPTER                pAdapter
1915 )
1916 {
1917         HAL_DATA_TYPE   *pHalData       = GET_HAL_DATA(pAdapter);
1918         PMPT_CONTEXT    pMptCtx = &(pAdapter->mppriv.mpt_ctx);
1919         u4Byte                  cckrate;
1920
1921         /* 1. if CCK block on */
1922         if (!phy_query_bb_reg(pAdapter, rFPGA0_RFMOD, bCCKEn))
1923                 phy_set_bb_reg(pAdapter, rFPGA0_RFMOD, bCCKEn, 1);/*set CCK block on*/
1924
1925         /*Turn Off All Test Mode*/
1926         if (IS_HARDWARE_TYPE_JAGUAR_AND_JAGUAR2(pAdapter))
1927                 phy_set_bb_reg(pAdapter, 0x914, BIT18 | BIT17 | BIT16, OFDM_ALL_OFF);
1928         else
1929                 phy_set_bb_reg(pAdapter, rOFDM1_LSTF, BIT30 | BIT29 | BIT28, OFDM_ALL_OFF);
1930
1931         cckrate  = pAdapter->mppriv.rateidx;
1932
1933         phy_set_bb_reg(pAdapter, rCCK0_System, bCCKTxRate, cckrate);
1934
1935         phy_set_bb_reg(pAdapter, rCCK0_System, bCCKBBMode, 0x2);        /*transmit mode*/
1936         phy_set_bb_reg(pAdapter, rCCK0_System, bCCKScramble, 0x1);      /*turn on scramble setting*/
1937
1938         if (!IS_HARDWARE_TYPE_JAGUAR_AND_JAGUAR2(pAdapter)) {
1939                 phy_set_bb_reg(pAdapter, 0xa14, 0x300, 0x3);                    /* 0xa15[1:0] = 11 force cck rxiq = 0*/
1940                 phy_set_bb_reg(pAdapter, rOFDM0_TRMuxPar, 0x10000, 0x1);                /* 0xc08[16] = 1 force ofdm rxiq = ofdm txiq*/
1941                 phy_set_bb_reg(pAdapter, rFPGA0_XA_HSSIParameter2, BIT14, 1);
1942                 phy_set_bb_reg(pAdapter, rFPGA0_XB_HSSIParameter2, BIT14, 1);
1943                 phy_set_bb_reg(pAdapter, 0x0B34, BIT14, 1);
1944         }
1945
1946         phy_set_bb_reg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000500);
1947         phy_set_bb_reg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000500);
1948
1949         pMptCtx->bCckContTx = TRUE;
1950         pMptCtx->bOfdmContTx = FALSE;
1951
1952 }       /* mpt_StartCckContTx */
1953
1954
1955 static  VOID mpt_StartOfdmContTx(
1956         PADAPTER                pAdapter
1957 )
1958 {
1959         HAL_DATA_TYPE   *pHalData       = GET_HAL_DATA(pAdapter);
1960         PMPT_CONTEXT    pMptCtx = &(pAdapter->mppriv.mpt_ctx);
1961
1962         /* 1. if OFDM block on?*/
1963         if (!phy_query_bb_reg(pAdapter, rFPGA0_RFMOD, bOFDMEn))
1964                 phy_set_bb_reg(pAdapter, rFPGA0_RFMOD, bOFDMEn, 1);/*set OFDM block on*/
1965
1966         /* 2. set CCK test mode off, set to CCK normal mode*/
1967         phy_set_bb_reg(pAdapter, rCCK0_System, bCCKBBMode, 0);
1968
1969         /* 3. turn on scramble setting*/
1970         phy_set_bb_reg(pAdapter, rCCK0_System, bCCKScramble, 1);
1971
1972         if (!IS_HARDWARE_TYPE_JAGUAR(pAdapter) && !IS_HARDWARE_TYPE_JAGUAR2(pAdapter)) {
1973                 phy_set_bb_reg(pAdapter, 0xa14, 0x300, 0x3);                    /* 0xa15[1:0] = 2b'11*/
1974                 phy_set_bb_reg(pAdapter, rOFDM0_TRMuxPar, 0x10000, 0x1);                /* 0xc08[16] = 1*/
1975         }
1976
1977         /* 4. Turn On Continue Tx and turn off the other test modes.*/
1978         if (IS_HARDWARE_TYPE_JAGUAR(pAdapter) || IS_HARDWARE_TYPE_JAGUAR2(pAdapter))
1979                 phy_set_bb_reg(pAdapter, 0x914, BIT18 | BIT17 | BIT16, OFDM_ContinuousTx);
1980         else
1981                 phy_set_bb_reg(pAdapter, rOFDM1_LSTF, BIT30 | BIT29 | BIT28, OFDM_ContinuousTx);
1982
1983         phy_set_bb_reg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000500);
1984         phy_set_bb_reg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000500);
1985
1986         pMptCtx->bCckContTx = FALSE;
1987         pMptCtx->bOfdmContTx = TRUE;
1988 }       /* mpt_StartOfdmContTx */
1989
1990
1991 #if defined(CONFIG_RTL8814A) || defined(CONFIG_RTL8821B) || defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8821C)
1992 /* for HW TX mode */
1993 void mpt_ProSetPMacTx(PADAPTER  Adapter)
1994 {
1995         PMPT_CONTEXT    pMptCtx         =       &(Adapter->mppriv.mpt_ctx);
1996         RT_PMAC_TX_INFO PMacTxInfo      =       pMptCtx->PMacTxInfo;
1997         u32                     u4bTmp;
1998
1999         dbg_print("SGI %d bSPreamble %d bSTBC %d bLDPC %d NDP_sound %d\n", PMacTxInfo.bSGI, PMacTxInfo.bSPreamble, PMacTxInfo.bSTBC, PMacTxInfo.bLDPC, PMacTxInfo.NDP_sound);
2000         dbg_print("TXSC %d BandWidth %d PacketPeriod %d PacketCount %d PacketLength %d PacketPattern %d\n", PMacTxInfo.TX_SC, PMacTxInfo.BandWidth, PMacTxInfo.PacketPeriod, PMacTxInfo.PacketCount,
2001                  PMacTxInfo.PacketLength, PMacTxInfo.PacketPattern);
2002 #if 0
2003         PRINT_DATA("LSIG ", PMacTxInfo.LSIG, 3);
2004         PRINT_DATA("HT_SIG", PMacTxInfo.HT_SIG, 6);
2005         PRINT_DATA("VHT_SIG_A", PMacTxInfo.VHT_SIG_A, 6);
2006         PRINT_DATA("VHT_SIG_B", PMacTxInfo.VHT_SIG_B, 4);
2007         dbg_print("VHT_SIG_B_CRC %x\n", PMacTxInfo.VHT_SIG_B_CRC);
2008         PRINT_DATA("VHT_Delimiter", PMacTxInfo.VHT_Delimiter, 4);
2009
2010         PRINT_DATA("Src Address", Adapter->mac_addr, 6);
2011         PRINT_DATA("Dest Address", PMacTxInfo.MacAddress, 6);
2012 #endif
2013
2014         if (PMacTxInfo.bEnPMacTx == FALSE) {
2015                 if (PMacTxInfo.Mode == CONTINUOUS_TX) {
2016                         phy_set_bb_reg(Adapter, 0xb04, 0xf, 2);                 /*      TX Stop*/
2017                         if (IS_MPT_CCK_RATE(PMacTxInfo.TX_RATE))
2018                                 mpt_StopCckContTx(Adapter);
2019                         else
2020                                 mpt_StopOfdmContTx(Adapter);
2021                 } else if (IS_MPT_CCK_RATE(PMacTxInfo.TX_RATE)) {
2022                         u4bTmp = phy_query_bb_reg(Adapter, 0xf50, bMaskLWord);
2023                         phy_set_bb_reg(Adapter, 0xb1c, bMaskLWord, u4bTmp + 50);
2024                         phy_set_bb_reg(Adapter, 0xb04, 0xf, 2);         /*TX Stop*/
2025                 } else
2026                         phy_set_bb_reg(Adapter, 0xb04, 0xf, 2);         /*      TX Stop*/
2027
2028                 if (PMacTxInfo.Mode == OFDM_Single_Tone_TX) {
2029                         /* Stop HW TX -> Stop Continuous TX -> Stop RF Setting*/
2030                         if (IS_MPT_CCK_RATE(PMacTxInfo.TX_RATE))
2031                                 mpt_StopCckContTx(Adapter);
2032                         else
2033                                 mpt_StopOfdmContTx(Adapter);
2034
2035                         mpt_SetSingleTone_8814A(Adapter, FALSE, TRUE);
2036                 }
2037
2038                 return;
2039         }
2040
2041         if (PMacTxInfo.Mode == CONTINUOUS_TX) {
2042                 PMacTxInfo.PacketCount = 1;
2043
2044                 if (IS_MPT_CCK_RATE(PMacTxInfo.TX_RATE))
2045                         mpt_StartCckContTx(Adapter);
2046                 else
2047                         mpt_StartOfdmContTx(Adapter);
2048         } else if (PMacTxInfo.Mode == OFDM_Single_Tone_TX) {
2049                 /* Continuous TX -> HW TX -> RF Setting */
2050                 PMacTxInfo.PacketCount = 1;
2051
2052                 if (IS_MPT_CCK_RATE(PMacTxInfo.TX_RATE))
2053                         mpt_StartCckContTx(Adapter);
2054                 else
2055                         mpt_StartOfdmContTx(Adapter);
2056         } else if (PMacTxInfo.Mode == PACKETS_TX) {
2057                 if (IS_MPT_CCK_RATE(PMacTxInfo.TX_RATE) && PMacTxInfo.PacketCount == 0)
2058                         PMacTxInfo.PacketCount = 0xffff;
2059         }
2060
2061         if (IS_MPT_CCK_RATE(PMacTxInfo.TX_RATE)) {
2062                 /* 0xb1c[0:15] TX packet count 0xb1C[31:16]     SFD*/
2063                 u4bTmp = PMacTxInfo.PacketCount | (PMacTxInfo.SFD << 16);
2064                 phy_set_bb_reg(Adapter, 0xb1c, bMaskDWord, u4bTmp);
2065                 /* 0xb40 7:0 SIGNAL     15:8 SERVICE    31:16 LENGTH*/
2066                 u4bTmp = PMacTxInfo.SignalField | (PMacTxInfo.ServiceField << 8) | (PMacTxInfo.LENGTH << 16);
2067                 phy_set_bb_reg(Adapter, 0xb40, bMaskDWord, u4bTmp);
2068                 u4bTmp = PMacTxInfo.CRC16[0] | (PMacTxInfo.CRC16[1] << 8);
2069                 phy_set_bb_reg(Adapter, 0xb44, bMaskLWord, u4bTmp);
2070
2071                 if (PMacTxInfo.bSPreamble)
2072                         phy_set_bb_reg(Adapter, 0xb0c, BIT27, 0);
2073                 else
2074                         phy_set_bb_reg(Adapter, 0xb0c, BIT27, 1);
2075         } else {
2076                 phy_set_bb_reg(Adapter, 0xb18, 0xfffff, PMacTxInfo.PacketCount);
2077
2078                 u4bTmp = PMacTxInfo.LSIG[0] | ((PMacTxInfo.LSIG[1]) << 8) | ((PMacTxInfo.LSIG[2]) << 16) | ((PMacTxInfo.PacketPattern) << 24);
2079                 phy_set_bb_reg(Adapter, 0xb08, bMaskDWord, u4bTmp);     /*      Set 0xb08[23:0] = LSIG, 0xb08[31:24] =  Data init octet*/
2080
2081                 if (PMacTxInfo.PacketPattern == 0x12)
2082                         u4bTmp = 0x3000000;
2083                 else
2084                         u4bTmp = 0;
2085         }
2086
2087         if (IS_MPT_HT_RATE(PMacTxInfo.TX_RATE)) {
2088                 u4bTmp |= PMacTxInfo.HT_SIG[0] | ((PMacTxInfo.HT_SIG[1]) << 8) | ((PMacTxInfo.HT_SIG[2]) << 16);
2089                 phy_set_bb_reg(Adapter, 0xb0c, bMaskDWord, u4bTmp);
2090                 u4bTmp = PMacTxInfo.HT_SIG[3] | ((PMacTxInfo.HT_SIG[4]) << 8) | ((PMacTxInfo.HT_SIG[5]) << 16);
2091                 phy_set_bb_reg(Adapter, 0xb10, 0xffffff, u4bTmp);
2092         } else if (IS_MPT_VHT_RATE(PMacTxInfo.TX_RATE)) {
2093                 u4bTmp |= PMacTxInfo.VHT_SIG_A[0] | ((PMacTxInfo.VHT_SIG_A[1]) << 8) | ((PMacTxInfo.VHT_SIG_A[2]) << 16);
2094                 phy_set_bb_reg(Adapter, 0xb0c, bMaskDWord, u4bTmp);
2095                 u4bTmp = PMacTxInfo.VHT_SIG_A[3] | ((PMacTxInfo.VHT_SIG_A[4]) << 8) | ((PMacTxInfo.VHT_SIG_A[5]) << 16);
2096                 phy_set_bb_reg(Adapter, 0xb10, 0xffffff, u4bTmp);
2097
2098                 _rtw_memcpy(&u4bTmp, PMacTxInfo.VHT_SIG_B, 4);
2099                 phy_set_bb_reg(Adapter, 0xb14, bMaskDWord, u4bTmp);
2100         }
2101
2102         if (IS_MPT_VHT_RATE(PMacTxInfo.TX_RATE)) {
2103                 u4bTmp = (PMacTxInfo.VHT_SIG_B_CRC << 24) | PMacTxInfo.PacketPeriod;    /* for TX interval */
2104                 phy_set_bb_reg(Adapter, 0xb20, bMaskDWord, u4bTmp);
2105
2106                 _rtw_memcpy(&u4bTmp, PMacTxInfo.VHT_Delimiter, 4);
2107                 phy_set_bb_reg(Adapter, 0xb24, bMaskDWord, u4bTmp);
2108
2109                 /* 0xb28 - 0xb34 24 byte Probe Request MAC Header*/
2110                 /*& Duration & Frame control*/
2111                 phy_set_bb_reg(Adapter, 0xb28, bMaskDWord, 0x00000040);
2112
2113                 /* Address1 [0:3]*/
2114                 u4bTmp = PMacTxInfo.MacAddress[0] | (PMacTxInfo.MacAddress[1] << 8) | (PMacTxInfo.MacAddress[2] << 16) | (PMacTxInfo.MacAddress[3] << 24);
2115                 phy_set_bb_reg(Adapter, 0xb2C, bMaskDWord, u4bTmp);
2116
2117                 /* Address3 [3:0]*/
2118                 phy_set_bb_reg(Adapter, 0xb38, bMaskDWord, u4bTmp);
2119
2120                 /* Address2[0:1] & Address1 [5:4]*/
2121                 u4bTmp = PMacTxInfo.MacAddress[4] | (PMacTxInfo.MacAddress[5] << 8) | (Adapter->mac_addr[0] << 16) | (Adapter->mac_addr[1] << 24);
2122                 phy_set_bb_reg(Adapter, 0xb30, bMaskDWord, u4bTmp);
2123
2124                 /* Address2 [5:2]*/
2125                 u4bTmp = Adapter->mac_addr[2] | (Adapter->mac_addr[3] << 8) | (Adapter->mac_addr[4] << 16) | (Adapter->mac_addr[5] << 24);
2126                 phy_set_bb_reg(Adapter, 0xb34, bMaskDWord, u4bTmp);
2127
2128                 /* Sequence Control & Address3 [5:4]*/
2129                 /*u4bTmp = PMacTxInfo.MacAddress[4]|(PMacTxInfo.MacAddress[5] << 8) ;*/
2130                 /*phy_set_bb_reg(Adapter, 0xb38, bMaskDWord, u4bTmp);*/
2131         } else {
2132                 phy_set_bb_reg(Adapter, 0xb20, bMaskDWord, PMacTxInfo.PacketPeriod);    /* for TX interval*/
2133                 /* & Duration & Frame control */
2134                 phy_set_bb_reg(Adapter, 0xb24, bMaskDWord, 0x00000040);
2135
2136                 /* 0xb24 - 0xb38 24 byte Probe Request MAC Header*/
2137                 /* Address1 [0:3]*/
2138                 u4bTmp = PMacTxInfo.MacAddress[0] | (PMacTxInfo.MacAddress[1] << 8) | (PMacTxInfo.MacAddress[2] << 16) | (PMacTxInfo.MacAddress[3] << 24);
2139                 phy_set_bb_reg(Adapter, 0xb28, bMaskDWord, u4bTmp);
2140
2141                 /* Address3 [3:0]*/
2142                 phy_set_bb_reg(Adapter, 0xb34, bMaskDWord, u4bTmp);
2143
2144                 /* Address2[0:1] & Address1 [5:4]*/
2145                 u4bTmp = PMacTxInfo.MacAddress[4] | (PMacTxInfo.MacAddress[5] << 8) | (Adapter->mac_addr[0] << 16) | (Adapter->mac_addr[1] << 24);
2146                 phy_set_bb_reg(Adapter, 0xb2c, bMaskDWord, u4bTmp);
2147
2148                 /* Address2 [5:2] */
2149                 u4bTmp = Adapter->mac_addr[2] | (Adapter->mac_addr[3] << 8) | (Adapter->mac_addr[4] << 16) | (Adapter->mac_addr[5] << 24);
2150                 phy_set_bb_reg(Adapter, 0xb30, bMaskDWord, u4bTmp);
2151
2152                 /* Sequence Control & Address3 [5:4]*/
2153                 u4bTmp = PMacTxInfo.MacAddress[4] | (PMacTxInfo.MacAddress[5] << 8);
2154                 phy_set_bb_reg(Adapter, 0xb38, bMaskDWord, u4bTmp);
2155         }
2156
2157         phy_set_bb_reg(Adapter, 0xb48, bMaskByte3, PMacTxInfo.TX_RATE_HEX);
2158
2159         /* 0xb4c 3:0 TXSC       5:4     BW      7:6 m_STBC      8 NDP_Sound*/
2160         u4bTmp = (PMacTxInfo.TX_SC) | ((PMacTxInfo.BandWidth) << 4) | ((PMacTxInfo.m_STBC - 1) << 6) | ((PMacTxInfo.NDP_sound) << 8);
2161         phy_set_bb_reg(Adapter, 0xb4c, 0x1ff, u4bTmp);
2162
2163         if (IS_HARDWARE_TYPE_8814A(Adapter) || IS_HARDWARE_TYPE_8822B(Adapter)) {
2164                 u4Byte offset = 0xb44;
2165
2166                 if (IS_MPT_OFDM_RATE(PMacTxInfo.TX_RATE))
2167                         phy_set_bb_reg(Adapter, offset, 0xc0000000, 0);
2168                 else if (IS_MPT_HT_RATE(PMacTxInfo.TX_RATE))
2169                         phy_set_bb_reg(Adapter, offset, 0xc0000000, 1);
2170                 else if (IS_MPT_VHT_RATE(PMacTxInfo.TX_RATE))
2171                         phy_set_bb_reg(Adapter, offset, 0xc0000000, 2);
2172         }
2173
2174         phy_set_bb_reg(Adapter, 0xb00, BIT8, 1);                /*      Turn on PMAC*/
2175         /* phy_set_bb_reg(Adapter, 0xb04, 0xf, 2);                               */ /* TX Stop */
2176         if (IS_MPT_CCK_RATE(PMacTxInfo.TX_RATE)) {
2177                 phy_set_bb_reg(Adapter, 0xb04, 0xf, 8);         /*TX CCK ON*/
2178                 phy_set_bb_reg(Adapter, 0xA84, BIT31, 0);
2179         } else
2180                 phy_set_bb_reg(Adapter, 0xb04, 0xf, 4);         /*      TX Ofdm ON      */
2181
2182         if (PMacTxInfo.Mode == OFDM_Single_Tone_TX)
2183                 mpt_SetSingleTone_8814A(Adapter, TRUE, TRUE);
2184
2185 }
2186
2187 #endif
2188
2189 void hal_mpt_SetContinuousTx(PADAPTER pAdapter, u8 bStart)
2190 {
2191         u8 Rate;
2192
2193         RT_TRACE(_module_mp_, _drv_info_,
2194                  ("SetContinuousTx: rate:%d\n", pAdapter->mppriv.rateidx));
2195         Rate = HwRateToMPTRate(pAdapter->mppriv.rateidx);
2196         pAdapter->mppriv.mpt_ctx.is_start_cont_tx = bStart;
2197
2198         if (Rate <= MPT_RATE_11M) {
2199                 if (bStart)
2200                         mpt_StartCckContTx(pAdapter);
2201                 else
2202                         mpt_StopCckContTx(pAdapter);
2203
2204         } else if (Rate >= MPT_RATE_6M) {
2205                 if (bStart)
2206                         mpt_StartOfdmContTx(pAdapter);
2207                 else
2208                         mpt_StopOfdmContTx(pAdapter);
2209         }
2210 }
2211
2212 #endif /* CONFIG_MP_INCLUDE*/