1 /******************************************************************************
3 * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
19 ******************************************************************************/
22 #ifndef __HALDMOUTSRC_H__
23 #define __HALDMOUTSRC_H__
25 /*============================================================*/
27 /*============================================================*/
28 #include "phydm_pre_define.h"
29 #include "phydm_dig.h"
30 #if PHYDM_SUPPORT_EDCA
31 #include "phydm_edcaturbocheck.h"
33 #include "phydm_pathdiv.h"
34 #include "phydm_antdiv.h"
35 #include "phydm_antdect.h"
36 #include "phydm_dynamicbbpowersaving.h"
37 #include "phydm_rainfo.h"
38 #include "phydm_dynamictxpower.h"
39 #include "phydm_cfotracking.h"
40 #include "phydm_acs.h"
41 #include "phydm_adaptivity.h"
42 #include "phydm_iqk.h"
43 #include "phydm_dfs.h"
44 #include "phydm_ccx.h"
45 #include "txbf/phydm_hal_txbf_api.h"
47 #include "phydm_adc_sampling.h"
48 #include "phydm_dynamic_rx_path.h"
49 #include "phydm_psd.h"
52 #if (DM_ODM_SUPPORT_TYPE & (ODM_CE | ODM_WIN))
53 #include "phydm_beamforming.h"
56 #if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
57 #include "halphyrf_ap.h"
60 #if (DM_ODM_SUPPORT_TYPE & (ODM_CE))
61 #include "phydm_noisemonitor.h"
62 #include "halphyrf_ce.h"
65 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN))
66 #include "halphyrf_win.h"
67 #include "phydm_noisemonitor.h"
70 /*============================================================*/
72 /*============================================================*/
74 /* Traffic load decision */
75 #define TRAFFIC_ULTRA_LOW 1
78 #define TRAFFIC_HIGH 4
82 /*NBI API------------------------------------*/
86 #define NBI_TABLE_SIZE_128 27
87 #define NBI_TABLE_SIZE_256 59
89 #define NUM_START_CH_80M 7
90 #define NUM_START_CH_40M 14
92 #define CH_OFFSET_40M 2
93 #define CH_OFFSET_80M 6
95 /*CSI MASK API------------------------------------*/
96 #define CSI_MASK_ENABLE 1
97 #define CSI_MASK_DISABLE 2
99 /*------------------------------------------------*/
101 #define FFT_128_TYPE 1
102 #define FFT_256_TYPE 2
104 #define SET_SUCCESS 1
106 #define SET_NO_NEED 3
108 #define FREQ_POSITIVE 1
109 #define FREQ_NEGATIVE 2
112 #if (DM_ODM_SUPPORT_TYPE == ODM_AP)
113 #define PHYDM_WATCH_DOG_PERIOD 1
115 #define PHYDM_WATCH_DOG_PERIOD 2
118 /*============================================================*/
119 /*structure and define*/
120 /*============================================================*/
122 /*2011/09/20 MH Add for AP/ADSLpseudo DM structuer requirement.*/
123 /*We need to remove to other position???*/
125 #if (DM_ODM_SUPPORT_TYPE & (ODM_CE | ODM_WIN))
126 struct rtl8192cd_priv {
133 #if (DM_ODM_SUPPORT_TYPE & ODM_AP)
136 #ifdef AP_BUILD_WORKAROUND
137 HAL_DATA_TYPE *temp2;
138 struct rtl8192cd_priv *priv;
143 #if (DM_ODM_SUPPORT_TYPE == ODM_AP)
151 struct _dynamic_primary_cca {
162 #if (DM_ODM_SUPPORT_TYPE & ODM_AP)
163 #ifdef ADSL_AP_BUILD_WORKAROUND
164 #define MAX_TOLERANCE 5
165 #define IQK_DELAY_TIME 1 /*ms*/
167 #endif /*#if(DM_ODM_SUPPORT_TYPE & (ODM_AP))*/
169 #define dm_type_by_fw 0
170 #define dm_type_by_driver 1
172 /*Declare for common info*/
174 #define IQK_THRESHOLD 8
175 #define DPK_THRESHOLD 4
178 #if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
179 __PACK struct _odm_phy_status_info_ {
181 u8 signal_quality; /* in 0-100 index. */
182 u8 rx_mimo_signal_strength[4]; /* in 0~100 index */
183 s8 rx_mimo_signal_quality[4]; /* EVM */
184 s8 rx_snr[4]; /* per-path's SNR */
185 #if (ODM_PHY_STATUS_NEW_TYPE_SUPPORT == 1)
186 u8 rx_count:2; /* RX path counter---*/
188 u8 rxsc:4; /* sub-channel---*/
192 #if (ODM_PHY_STATUS_NEW_TYPE_SUPPORT == 1)
193 u8 channel; /* channel number---*/
194 boolean is_mu_packet; /* is MU packet or not---*/
195 boolean is_beamformed; /* BF packet---*/
199 struct _odm_phy_status_info_append_ {
206 struct _odm_phy_status_info_ {
208 /* Be care, if you want to add any element please insert between */
209 /* rx_pwdb_all & signal_strength. */
211 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN))
212 u32 rx_pwdb_all; /*in new Phy-status IC, represent the max PWDB among all path*/
216 u8 signal_quality; /* in 0-100 index. */
217 s8 rx_mimo_signal_quality[4]; /* per-path's EVM translate to 0~100% */
218 u8 rx_mimo_evm_dbm[4]; /* per-path's original EVM (dbm) */
219 u8 rx_mimo_signal_strength[4]; /* in 0~100 index */
220 s16 cfo_short[4]; /* per-path's cfo_short */
221 s16 cfo_tail[4]; /* per-path's cfo_tail */
222 s8 rx_power; /* in dBm Translate from PWdB */
223 s8 recv_signal_power; /* Real power in dBm for this packet, no beautification and aggregation. Keep this raw info to be used for the other procedures. */
224 u8 bt_rx_rssi_percentage;
225 u8 signal_strength; /* in 0-100 index. */
226 s8 rx_pwr[4]; /* per-path's pwdb */
227 s8 rx_snr[4]; /* per-path's SNR */
228 /* s8 BB_Backup[13]; backup reg. */
229 #if (ODM_PHY_STATUS_NEW_TYPE_SUPPORT == 1)
230 u8 rx_count:2; /* RX path counter---*/
232 u8 rxsc:4; /* sub-channel---*/
236 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
237 u8 bt_coex_pwr_adjust;
239 #if (ODM_PHY_STATUS_NEW_TYPE_SUPPORT == 1)
240 u8 channel; /* channel number---*/
241 boolean is_mu_packet; /* is MU packet or not---*/
242 boolean is_beamformed; /* BF packet---*/
247 struct _odm_per_pkt_info_ {
250 boolean is_packet_match_bssid;
251 boolean is_packet_to_self;
252 boolean is_packet_beacon;
258 struct _odm_phy_dbg_info_ {
259 /*ODM Write,debug info*/
261 u32 num_qry_phy_status;
262 u32 num_qry_phy_status_cck;
263 u32 num_qry_phy_status_ofdm;
264 #if (ODM_PHY_STATUS_NEW_TYPE_SUPPORT == 1)
267 u32 num_qry_mu_vht_pkt[40];
268 u32 num_qry_vht_pkt[40];
274 u8 num_qry_beacon_pkt;
281 /*2011/20/20 MH For MP driver RT_WLAN_STA = struct sta_info*/
282 /*Please declare below ODM relative info in your STA info structure.*/
285 struct _ODM_STA_INFO {
287 boolean is_used; /*record the sta status link or not?*/
288 u8 iot_peer; /*Enum value. HT_IOT_PEER_E*/
302 /*-----------HOOK BEFORE REG INIT-----------*/
303 ODM_CMNINFO_PLATFORM = 0,
305 ODM_CMNINFO_INTERFACE,
306 ODM_CMNINFO_MP_TEST_CHIP,
311 ODM_CMNINFO_RFE_TYPE,
313 ODM_CMNINFO_BOARD_TYPE,
314 ODM_CMNINFO_PACKAGE_TYPE,
316 ODM_CMNINFO_5G_EXT_LNA,
318 ODM_CMNINFO_5G_EXT_PA,
323 ODM_CMNINFO_EXT_TRSW,
324 ODM_CMNINFO_EXT_LNA_GAIN,
325 ODM_CMNINFO_PATCH_ID,
326 ODM_CMNINFO_BINHCT_TEST,
327 ODM_CMNINFO_BWIFI_TEST,
328 ODM_CMNINFO_SMART_CONCURRENT,
329 ODM_CMNINFO_CONFIG_BB_RF,
330 ODM_CMNINFO_DOMAIN_CODE_2G,
331 ODM_CMNINFO_DOMAIN_CODE_5G,
332 ODM_CMNINFO_IQKFWOFFLOAD,
333 ODM_CMNINFO_IQKPAOFF,
334 ODM_CMNINFO_HUBUSBMODE,
335 ODM_CMNINFO_FWDWRSVDPAGEINPROGRESS,
338 ODM_CMNINFO_SOUNDING_SEQ,
339 ODM_CMNINFO_REGRFKFREEENABLE,
340 ODM_CMNINFO_RFKFREEENABLE,
341 ODM_CMNINFO_NORMAL_RX_PATH_CHANGE,
342 ODM_CMNINFO_EFUSE0X3D8,
343 ODM_CMNINFO_EFUSE0X3D7,
344 /*-----------HOOK BEFORE REG INIT-----------*/
348 /*--------- POINTER REFERENCE-----------*/
349 ODM_CMNINFO_MAC_PHY_MODE,
354 ODM_CMNINFO_SEC_CHNL_OFFSET,
355 ODM_CMNINFO_SEC_MODE,
358 ODM_CMNINFO_FORCED_RATE,
360 ODM_CMNINFO_ADAPTIVITY,
361 ODM_CMNINFO_DMSP_GET_VALUE,
362 ODM_CMNINFO_BUDDY_ADAPTOR,
363 ODM_CMNINFO_DMSP_IS_MASTER,
365 ODM_CMNINFO_POWER_SAVING,
366 ODM_CMNINFO_ONE_PATH_CCA,
367 ODM_CMNINFO_DRV_STOP,
370 ODM_CMNINFO_ANT_TEST,
371 ODM_CMNINFO_NET_CLOSED,
372 ODM_CMNINFO_FORCED_IGI_LB,
373 ODM_CMNINFO_P2P_LINK,
374 ODM_CMNINFO_FCS_MODE,
375 ODM_CMNINFO_IS1ANTENNA,
376 ODM_CMNINFO_RFDEFAULTPATH,
377 ODM_CMNINFO_DFS_MASTER_ENABLE,
378 ODM_CMNINFO_FORCE_TX_ANT_BY_TXDESC,
379 ODM_CMNINFO_SET_S0S1_DEFAULT_ANTENNA,
380 /*--------- POINTER REFERENCE-----------*/
382 /*------------CALL BY VALUE-------------*/
383 ODM_CMNINFO_WIFI_DIRECT,
384 ODM_CMNINFO_WIFI_DISPLAY,
385 ODM_CMNINFO_LINK_IN_PROGRESS,
387 ODM_CMNINFO_CMW500LINK,
389 ODM_CMNINFO_STATION_STATE,
390 ODM_CMNINFO_RSSI_MIN,
391 ODM_CMNINFO_DBG_COMP,
392 ODM_CMNINFO_DBG_LEVEL,
393 ODM_CMNINFO_RA_THRESHOLD_HIGH,
394 ODM_CMNINFO_RA_THRESHOLD_LOW,
395 ODM_CMNINFO_RF_ANTENNA_TYPE,
396 ODM_CMNINFO_WITH_EXT_ANTENNA_SWITCH,
397 ODM_CMNINFO_BE_FIX_TX_ANT,
398 ODM_CMNINFO_BT_ENABLED,
399 ODM_CMNINFO_BT_HS_CONNECT_PROCESS,
400 ODM_CMNINFO_BT_HS_RSSI,
401 ODM_CMNINFO_BT_OPERATION,
402 ODM_CMNINFO_BT_LIMITED_DIG,
405 ODM_CMNINFO_BT_DISABLE_EDCA,
406 #if (DM_ODM_SUPPORT_TYPE & ODM_AP) /*for repeater mode add by YuChen 2014.06.23*/
407 #ifdef UNIVERSAL_REPEATER
408 ODM_CMNINFO_VXD_LINK,
411 ODM_CMNINFO_AP_TOTAL_NUM,
412 ODM_CMNINFO_POWER_TRAINING,
413 ODM_CMNINFO_DFS_REGION_DOMAIN,
414 /*------------CALL BY VALUE-------------*/
416 /*Dynamic ptr array hook itms.*/
417 ODM_CMNINFO_STA_STATUS,
423 enum phydm_info_query_e {
430 PHYDM_INFO_CRC32_OK_VHT,
431 PHYDM_INFO_CRC32_OK_HT,
432 PHYDM_INFO_CRC32_OK_LEGACY,
433 PHYDM_INFO_CRC32_OK_CCK,
434 PHYDM_INFO_CRC32_ERROR_VHT,
435 PHYDM_INFO_CRC32_ERROR_HT,
436 PHYDM_INFO_CRC32_ERROR_LEGACY,
437 PHYDM_INFO_CRC32_ERROR_CCK,
438 PHYDM_INFO_EDCCA_FLAG,
439 PHYDM_INFO_OFDM_ENABLE,
440 PHYDM_INFO_CCK_ENABLE,
441 PHYDM_INFO_DBG_PORT_0
452 /*2011/10/20 MH Define ODM support ability. ODM_CMNINFO_ABILITY*/
455 /*BB ODM section BIT 0-19*/
457 ODM_BB_RA_MASK = BIT(1),
458 ODM_BB_DYNAMIC_TXPWR = BIT(2),
459 ODM_BB_FA_CNT = BIT(3),
460 ODM_BB_RSSI_MONITOR = BIT(4),
461 ODM_BB_CCK_PD = BIT(5),
462 ODM_BB_ANT_DIV = BIT(6),
463 ODM_BB_PWR_TRAIN = BIT(8),
464 ODM_BB_RATE_ADAPTIVE = BIT(9),
465 ODM_BB_PATH_DIV = BIT(10),
466 ODM_BB_ADAPTIVITY = BIT(13),
467 ODM_BB_CFO_TRACKING = BIT(14),
468 ODM_BB_NHM_CNT = BIT(15),
469 ODM_BB_PRIMARY_CCA = BIT(16),
470 ODM_BB_TXBF = BIT(17),
471 ODM_BB_DYNAMIC_ARFR = BIT(18),
473 ODM_MAC_EDCA_TURBO = BIT(20),
474 ODM_BB_DYNAMIC_RX_PATH = BIT(21),
476 /*RF ODM section BIT 24-31*/
477 ODM_RF_TX_PWR_TRACK = BIT(24),
478 ODM_RF_RX_GAIN_TRACK = BIT(25),
479 ODM_RF_CALIBRATION = BIT(26),
484 /*ODM_CMNINFO_ONE_PATH_CCA*/
485 enum odm_cca_path_e {
491 enum cca_pathdiv_en_e {
492 CCA_PATHDIV_DISABLE = 0,
493 CCA_PATHDIV_ENABLE = 1,
498 enum phy_reg_pg_type {
499 PHY_REG_PG_RELATIVE_VALUE = 0,
500 PHY_REG_PG_EXACT_VALUE = 1
503 /*2011/09/22 MH Copy from SD4 defined structure. We use to support PHY DM integration.*/
505 #if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
506 #if (RT_PLATFORM != PLATFORM_LINUX)
511 #else/*for AP,ADSL,CE Team*/
515 /*Add for different team use temporarily*/
516 struct _ADAPTER *adapter; /*For CE/NIC team*/
517 struct rtl8192cd_priv *priv; /*For AP/ADSL team*/
518 /*WHen you use adapter or priv pointer, you must make sure the pointer is ready.*/
521 #if (DM_ODM_SUPPORT_TYPE & (ODM_CE | ODM_WIN))
522 struct rtl8192cd_priv fake_priv;
524 #if (DM_ODM_SUPPORT_TYPE & ODM_AP)
525 /* ADSL_AP_BUILD_WORKAROUND */
526 struct _ADAPTER fake_adapter;
529 enum phy_reg_pg_type phy_reg_pg_value_type;
530 u8 phy_reg_pg_version;
532 u32 debug_components;
533 u32 fw_debug_components;
536 u32 num_qry_phy_status_all; /*CCK + OFDM*/
537 u32 last_num_qry_phy_status_all;
539 boolean MPDIG_2G; /*off MPDIG*/
541 boolean is_init_hw_info_by_rfe;
543 /*------ ODM HANDLE, DRIVER NEEDS NOT TO HOOK------*/
544 boolean is_cck_high_power;
545 u8 rf_path_rx_enable;
547 /*------ ODM HANDLE, DRIVER NEEDS NOT TO HOOK------*/
550 /* 1 COMMON INFORMATION */
553 /*-----------HOOK BEFORE REG INIT-----------*/
554 /*ODM Platform info AP/ADSL/CE/MP = 1/2/3/4*/
556 /* ODM Platform info WIN/AP/CE = 1/2/3 */
558 /*ODM Support Ability DIG/RATR/TX_PWR_TRACK/ ¡K¡K = 1/2/3/¡K*/
560 /*ODM PCIE/USB/SDIO = 1/2/3*/
561 u8 support_interface;
562 /*ODM composite or independent. Bit oriented/ 92C+92D+ .... or any other type = 1/2/3/...*/
564 /*cut version TestChip/A-cut/B-cut... = 0/1/2/3/...*/
566 /*Fab version TSMC/UMC = 0/1*/
568 /*RF type 4T4R/3T3R/2T2R/1T2R/1T1R/...*/
571 /*Board type Normal/HighPower/MiniCard/SLIM/Combo/... = 0/1/2/3/4/...*/
572 /*Enable Function DPK OFF/ON = 0/1*/
580 /*with external LNA NO/Yes = 0/1*/
582 u8 ext_lna_5g; /*5G*/
583 /*with external PA NO/Yes = 0/1*/
586 /*with Efuse number*/
589 /*with external TRSW NO/Yes = 0/1*/
591 u8 ext_lna_gain; /*2G*/
592 u8 patch_id; /*Customer ID*/
593 boolean is_in_hct_test;
596 boolean is_dual_mac_smart_concurrent;
597 u32 bk_support_ability;
599 u8 with_extenal_ant_switch;
601 u8 odm_regulation_2_4g;
602 u8 odm_regulation_5g;
606 u32 phydm_sys_up_time;
608 /*-----------HOOK BEFORE REG INIT-----------*/
612 /*--------- POINTER REFERENCE-----------*/
615 boolean BOOLEAN_temp;
616 struct _ADAPTER *PADAPTER_temp;
618 /*MAC PHY mode SMSP/DMSP/DMDP = 0/1/2*/
620 /*TX Unicast byte count*/
621 u64 *p_num_tx_bytes_unicast;
622 /*RX Unicast byte count*/
623 u64 *p_num_rx_bytes_unicast;
624 /*Wireless mode B/G/A/N = BIT0/BIT1/BIT2/BIT3*/
626 /*Frequence band 2.4G/5G = 0/1*/
628 /*Secondary channel offset don't_care/below/above = 0/1/2*/
630 /*security mode Open/WEP/AES/TKIP = 0/1/2/3*/
632 /*BW info 20M/40M/80M = 0/1/2*/
634 /*Central channel location Ch1/Ch2/....*/
635 u8 *p_channel; /*central channel number*/
637 /*Common info for 92D DMSP*/
639 boolean *p_is_get_value_from_other_mac;
640 struct _ADAPTER **p_buddy_adapter;
641 boolean *p_is_master_of_dmsp; /* MAC0: master, MAC1: slave */
642 /*Common info for status*/
643 boolean *p_is_scan_in_process;
644 boolean *p_is_power_saving;
645 /*CCA path 2-path/path-A/path-B = 0/1/2; using enum odm_cca_path_e.*/
648 boolean *p_is_net_closed;
649 u8 *pu1_forced_igi_lb;
650 boolean *p_is_fcs_mode_enable;
651 /*--------- For 8723B IQK-----------*/
652 boolean *p_is_1_antenna;
653 u8 *p_rf_default_path;
656 /*--------- POINTER REFERENCE-----------*/
657 u16 *p_forced_data_rate;
659 u8 *p_enable_adaptivity;
661 boolean *p_is_fw_dw_rsvd_page_in_progress;
662 u32 *p_current_tx_tp;
663 u32 *p_current_rx_tp;
665 /*------------CALL BY VALUE-------------*/
666 boolean is_link_in_process;
667 boolean is_wifi_direct;
668 boolean is_wifi_display;
670 boolean bLinkedcmw500;
671 boolean is_in_lps_pg;
673 #if (DM_ODM_SUPPORT_TYPE & ODM_AP) /*for repeater mode add by YuChen 2014.06.23*/
674 #ifdef UNIVERSAL_REPEATER
679 u8 interface_index; /*Add for 92D dual MAC: 0--Mac0 1--Mac1*/
681 boolean is_one_entry_only;
684 u8 pre_number_linked_client;
685 u8 number_linked_client;
686 u8 pre_number_active_client;
687 u8 number_active_client;
688 /*Common info for BTDM*/
689 boolean is_bt_enabled; /*BT is enabled*/
690 boolean is_bt_connect_process; /*BT HS is under connection progress.*/
691 u8 bt_hs_rssi; /*BT HS mode wifi rssi value.*/
692 boolean is_bt_hs_operation; /*BT HS mode is under progress*/
693 u8 bt_hs_dig_val; /*use BT rssi to decide the DIG value*/
694 boolean is_bt_disable_edca_turbo; /*Under some condition, don't enable the EDCA Turbo*/
695 boolean is_bt_busy; /*BT is busy.*/
696 boolean is_bt_limited_dig; /*BT is busy.*/
697 boolean is_disable_phy_api;
698 /*------------CALL BY VALUE-------------*/
715 boolean is_noisy_state;
719 u32 txagc_offset_value_a;
720 boolean is_txagc_offset_positive_a;
721 u32 txagc_offset_value_b;
722 boolean is_txagc_offset_positive_b;
730 u32 bb_swing_offset_a;
731 boolean is_bb_swing_offset_positive_a;
732 u32 bb_swing_offset_b;
733 boolean is_bb_swing_offset_positive_b;
743 u8 evm_antdiv_period;
749 boolean h2c_rarpt_connect;
750 boolean cck_agc_report_type;
757 /*8821C Antenna BTG/WLG/WLA Select*/
758 u8 current_rf_set_8821c;
759 u8 default_rf_set_8821c;
764 s8 th_edcca_hl_diff_default;
768 s8 th_edcca_hl_diff_mode2;
769 boolean carrier_sense_enable;
770 u8 adaptivity_igi_upper;
771 boolean adaptivity_flag;
773 boolean adaptivity_enable;
775 boolean edcca_enable;
777 struct _ADAPTIVITY_STATISTICS adaptivity;
785 u8 fw_debug_trace[60];
787 boolean fw_buff_is_enpty;
790 /*for noise detection*/
791 boolean noisy_decision; /*b_noisy*/
793 u32 noisy_decision_smooth;
794 boolean is_disable_dym_ecs;
796 #if (DM_ODM_SUPPORT_TYPE & (ODM_CE | ODM_WIN))
797 struct _ODM_NOISE_MONITOR_ noise_level;
801 /*2012/01/12 MH For MP, we need to reduce one array pointer for default port.??*/
802 struct sta_info *p_odm_sta_info[ODM_ASSOCIATE_ENTRY_NUM];
803 u16 platform2phydm_macid_table[ODM_ASSOCIATE_ENTRY_NUM];
804 /* platform_macid_table[platform_macid] = phydm_macid */
805 #if (ODM_PHY_STATUS_NEW_TYPE_SUPPORT == 1)
806 s32 accumulate_pwdb[ODM_ASSOCIATE_ENTRY_NUM];
809 #if (RATE_ADAPTIVE_SUPPORT == 1)
810 u16 currmin_rpt_time;
811 struct _odm_ra_info_ ra_info[ODM_ASSOCIATE_ENTRY_NUM];
812 /*Use mac_id as array index. STA mac_id=0, VWiFi Client mac_id={1, ODM_ASSOCIATE_ENTRY_NUM-1} //YJ,add,120119*/
815 /*2012/02/14 MH Add to share 88E ra with other SW team.*/
816 /*We need to colelct all support abilit to a proper area.*/
818 boolean ra_support88e;
820 struct _odm_phy_dbg_info_ phy_dbg_info;
823 #if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY))
824 #if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
825 struct _BF_DIV_COEX_ dm_bdc_table;
828 #if (defined(CONFIG_HL_SMART_ANTENNA_TYPE1)) || (defined(CONFIG_HL_SMART_ANTENNA_TYPE2))
829 struct _SMART_ANTENNA_TRAINNING_ dm_sat_table;
833 struct _FAST_ANTENNA_TRAINNING_ dm_fat_table;
834 struct _dynamic_initial_gain_threshold_ dm_dig_table;
835 #if (defined(CONFIG_BB_POWER_SAVING))
836 struct _dynamic_power_saving dm_ps_table;
838 struct _dynamic_primary_cca dm_pri_cca;
839 struct _rate_adaptive_table_ dm_ra_table;
840 struct _FALSE_ALARM_STATISTICS false_alm_cnt;
841 struct _FALSE_ALARM_STATISTICS flase_alm_cnt_buddy_adapter;
842 struct _sw_antenna_switch_ dm_swat_table;
843 struct _CFO_TRACKING_ dm_cfo_track;
845 struct _CCX_INFO dm_ccx_info;
846 #if (CONFIG_PSD_TOOL == 1)
847 struct _PHYDM_PSD_ dm_psd_table;
850 #if (PHYDM_LA_MODE_SUPPORT == 1)
851 struct _RT_ADCSMP adcsmp;
853 #if (CONFIG_DYNAMIC_RX_PATH == 1)
854 struct _DYNAMIC_RX_PATH_ dm_drp_table;
857 #if (RTL8814A_SUPPORT == 1 || RTL8822B_SUPPORT == 1 || RTL8821C_SUPPORT == 1)
858 struct _IQK_INFORMATION IQK_info;
861 #if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
863 struct _path_div_parameter_define_ path_iqk;
865 #if (defined(CONFIG_PATH_DIVERSITY))
866 struct _ODM_PATH_DIVERSITY_ dm_path_div;
869 #if PHYDM_SUPPORT_EDCA
870 struct _EDCA_TURBO_ dm_edca_table;
874 boolean *p_is_driver_stopped;
875 boolean *p_is_driver_is_going_to_pnp_set_power_sleep;
876 boolean *pinit_adpt_in_progress;
879 boolean is_user_assign_level;
880 u8 RSSI_BT; /*come from BT*/
881 boolean is_psd_in_process;
882 boolean is_psd_active;
883 boolean is_dm_initial_gain_enable;
886 struct timer_list mpt_dig_timer;
888 /*for rate adaptive, in fact, 88c/92c fw will handle this*/
891 /* for dynamic SoML control */
892 boolean bsomlenabled;
894 struct _ODM_RATE_ADAPTIVE rate_adaptive;
895 #if (defined(CONFIG_ANT_DETECTION))
896 struct _ANT_DETECTED_INFO ant_detected_info; /* Antenna detected information for RSSI tool*/
898 struct odm_rf_calibration_structure rf_calibrate_info;
903 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
905 u8 force_power_training_state;
906 boolean is_change_state;
911 boolean is_disable_power_training;
912 u8 dynamic_tx_high_power_lvl;
914 u32 tx_agc_ofdm_18_6;
917 /*ODM relative time.*/
918 struct timer_list path_div_switch_timer;
919 /*2011.09.27 add for path Diversity*/
920 struct timer_list cck_path_diversity_timer;
921 struct timer_list fast_ant_training_timer;
922 #ifdef ODM_EVM_ENHANCE_ANTDIV
923 struct timer_list evm_fast_ant_training_timer;
925 struct timer_list sbdcnt_timer;
927 /*ODM relative workitem.*/
928 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
930 RT_WORK_ITEM path_div_switch_workitem;
931 RT_WORK_ITEM cck_path_diversity_workitem;
932 RT_WORK_ITEM fast_ant_training_workitem;
933 RT_WORK_ITEM mpt_dig_workitem;
934 RT_WORK_ITEM ra_rpt_workitem;
935 RT_WORK_ITEM sbdcnt_workitem;
939 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
940 #if (BEAMFORMING_SUPPORT == 1)
941 struct _RT_BEAMFORMING_INFO beamforming_info;
945 #ifdef CONFIG_PHYDM_DFS_MASTER
946 u8 dfs_region_domain;
947 u8 *dfs_master_enabled;
949 /*====== phydm_radar_detect_with_dbg_parm start ======*/
950 u8 radar_detect_dbg_parm_en;
951 u32 radar_detect_reg_918;
952 u32 radar_detect_reg_91c;
953 u32 radar_detect_reg_920;
954 u32 radar_detect_reg_924;
955 /*====== phydm_radar_detect_with_dbg_parm end ======*/
958 #if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
960 #if (RT_PLATFORM != PLATFORM_LINUX)
961 }PHY_DM_STRUCT; /*DM_Dynamic_Mechanism_Structure*/
966 #else /*for AP,ADSL,CE Team*/
971 enum phydm_structure_type {
981 enum odm_rf_content {
982 odm_radioa_txt = 0x1000,
983 odm_radiob_txt = 0x1001,
984 odm_radioc_txt = 0x1002,
985 odm_radiod_txt = 0x1003
988 enum odm_bb_config_type {
991 CONFIG_BB_AGC_TAB_2G,
992 CONFIG_BB_AGC_TAB_5G,
993 CONFIG_BB_PHY_REG_PG,
994 CONFIG_BB_PHY_REG_MP,
995 CONFIG_BB_AGC_TAB_DIFF,
998 enum odm_rf_config_type {
1000 CONFIG_RF_TXPWR_LMT,
1003 enum odm_fw_config_type {
1011 CONFIG_FW_AP_WOWLAN,
1016 #if (DM_ODM_SUPPORT_TYPE != ODM_WIN)
1022 RT_STATUS_INVALID_CONTEXT,
1023 RT_STATUS_INVALID_PARAMETER,
1024 RT_STATUS_NOT_SUPPORT,
1025 RT_STATUS_OS_API_FAILED,
1027 #endif /*end of enum rt_status definition*/
1033 /*===========================================================*/
1034 /*AGC RX High Power mode*/
1035 /*===========================================================*/
1036 #define lna_low_gain_1 0x64
1037 #define lna_low_gain_2 0x5A
1038 #define lna_low_gain_3 0x58
1040 #define FA_RXHP_TH1 5000
1041 #define FA_RXHP_TH2 1500
1042 #define FA_RXHP_TH3 800
1043 #define FA_RXHP_TH4 600
1044 #define FA_RXHP_TH5 500
1058 /*check Sta pointer valid or not*/
1060 #if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
1061 #define IS_STA_VALID(p_sta) (p_sta && p_sta->expire_to)
1062 #elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)
1063 #define IS_STA_VALID(p_sta) (p_sta && p_sta->bUsed)
1065 #define IS_STA_VALID(p_sta) (p_sta)
1068 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_AP))
1071 odm_check_power_status(
1072 struct _ADAPTER *adapter
1077 u32 odm_convert_to_db(u32 value);
1079 u32 odm_convert_to_linear(u32 value);
1081 #if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
1083 odm_dm_watchdog_lps(
1084 struct PHY_DM_STRUCT *p_dm_odm
1090 odm_pwdb_conversion(
1097 odm_sign_conversion(
1103 odm_init_mp_driver_status(
1104 struct PHY_DM_STRUCT *p_dm_odm
1108 phydm_txcurrentcalibration(
1109 struct PHY_DM_STRUCT *p_dm_odm
1124 struct PHY_DM_STRUCT *p_dm_odm
1129 struct PHY_DM_STRUCT *p_dm_odm
1133 phydm_support_ability_debug(
1135 u32 *const dm_value,
1142 phydm_config_ofdm_rx_path(
1143 struct PHY_DM_STRUCT *p_dm_odm,
1148 phydm_config_trx_path(
1150 u32 *const dm_value,
1158 struct PHY_DM_STRUCT *p_dm_odm
1163 struct PHY_DM_STRUCT *p_dm_odm
1168 struct PHY_DM_STRUCT *p_dm_odm,
1169 enum odm_cmninfo_e cmn_info,
1175 struct PHY_DM_STRUCT *p_dm_odm,
1176 enum odm_cmninfo_e cmn_info,
1181 odm_cmn_info_ptr_array_hook(
1182 struct PHY_DM_STRUCT *p_dm_odm,
1183 enum odm_cmninfo_e cmn_info,
1189 odm_cmn_info_update(
1190 struct PHY_DM_STRUCT *p_dm_odm,
1196 phydm_cmn_info_query(
1197 struct PHY_DM_STRUCT *p_dm_odm,
1198 enum phydm_info_query_e info_type
1201 #if (DM_ODM_SUPPORT_TYPE == ODM_AP)
1203 odm_init_all_threads(
1204 struct PHY_DM_STRUCT *p_dm_odm
1208 odm_stop_all_threads(
1209 struct PHY_DM_STRUCT *p_dm_odm
1214 odm_init_all_timers(
1215 struct PHY_DM_STRUCT *p_dm_odm
1219 odm_cancel_all_timers(
1220 struct PHY_DM_STRUCT *p_dm_odm
1224 odm_release_all_timers(
1225 struct PHY_DM_STRUCT *p_dm_odm
1229 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
1230 void odm_init_all_work_items(struct PHY_DM_STRUCT *p_dm_odm);
1231 void odm_free_all_work_items(struct PHY_DM_STRUCT *p_dm_odm);
1234 platform_division64(
1239 #define dm_change_dynamic_init_gain_thresh odm_change_dynamic_init_gain_thresh
1241 enum dm_dig_connect_e {
1242 DIG_STA_DISCONNECT = 0,
1243 DIG_STA_CONNECT = 1,
1244 DIG_STA_BEFORE_CONNECT = 2,
1245 DIG_MULTI_STA_DISCONNECT = 3,
1246 DIG_MULTI_STA_CONNECT = 4,
1250 /*2012/01/12 MH Check afapter status. Temp fix BSOD.*/
1252 #define HAL_ADAPTER_STS_CHK(p_dm_odm) do {\
1253 if (p_dm_odm->adapter == NULL) { \
1259 #endif /*#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)*/
1262 odm_asoc_entry_init(
1263 struct PHY_DM_STRUCT *p_dm_odm
1268 phydm_get_structure(
1269 struct PHY_DM_STRUCT *p_dm_odm,
1273 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) || (DM_ODM_SUPPORT_TYPE == ODM_CE)
1274 /*===========================================================*/
1275 /* The following is for compile only*/
1276 /*===========================================================*/
1278 #define IS_HARDWARE_TYPE_8723A(_adapter) false
1279 #define IS_HARDWARE_TYPE_8723AE(_adapter) false
1280 #define IS_HARDWARE_TYPE_8192C(_adapter) false
1281 #define IS_HARDWARE_TYPE_8192D(_adapter) false
1282 #define RF_T_METER_92D 0x42
1285 #define GET_RX_STATUS_DESC_RX_MCS(__prx_status_desc) LE_BITS_TO_1BYTE(__prx_status_desc+12, 0, 6)
1287 #define REG_CONFIG_RAM64X16 0xb2c
1289 #define TARGET_CHNL_NUM_2G_5G 59
1291 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
1292 u8 get_right_chnl_place_for_iqk(u8 chnl);
1295 /* *********************************************************** */
1298 #if (DM_ODM_SUPPORT_TYPE == ODM_CE)
1299 void odm_dtc(struct PHY_DM_STRUCT *p_dm_odm);
1300 #endif /* #if (DM_ODM_SUPPORT_TYPE == ODM_CE) */
1303 void phydm_noisy_detection(struct PHY_DM_STRUCT *p_dm_odm);
1309 phydm_set_ext_switch(
1311 u32 *const dm_value,
1321 u32 *const dm_value,