drivers/net/wireless/rockchip_wlan/rtl8723cs/hal/phydm/phydm_dig.h

   1 /******************************************************************************
   2  *
   3  * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of version 2 of the GNU General Public License as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program; if not, write to the Free Software Foundation, Inc.,
  16  * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  17  *
  18  *
  19  ******************************************************************************/
  20
  21 #ifndef __PHYDMDIG_H__
  22 #define    __PHYDMDIG_H__
  23
  24 #define DIG_VERSION     "1.32"  /* 2016.09.02  YuChen. add CCK PD for 8197F*/
  25 #define DIG_HW          0
  26
  27
  28 /* Pause DIG & CCKPD */
  29 #define         DM_DIG_MAX_PAUSE_TYPE           0x7
  30
  31 enum dig_goupcheck_level {
  32
  33         DIG_GOUPCHECK_LEVEL_0,
  34         DIG_GOUPCHECK_LEVEL_1,
  35         DIG_GOUPCHECK_LEVEL_2
  36
  37 };
  38
  39 struct _dynamic_initial_gain_threshold_ {
  40         boolean         is_stop_dig;            /* for debug */
  41         boolean         is_ignore_dig;
  42         boolean         is_psd_in_progress;
  43
  44         u8              dig_enable_flag;
  45         u8              dig_ext_port_stage;
  46
  47         int             rssi_low_thresh;
  48         int             rssi_high_thresh;
  49
  50         u32             fa_low_thresh;
  51         u32             fa_high_thresh;
  52
  53         u8              cur_sta_connect_state;
  54         u8              pre_sta_connect_state;
  55         u8              cur_multi_sta_connect_state;
  56
  57         u8              pre_ig_value;
  58         u8              cur_ig_value;
  59         u8              backup_ig_value;                /* MP DIG */
  60         u8              bt30_cur_igi;
  61         u8              igi_backup;
  62
  63         s8              backoff_val;
  64         s8              backoff_val_range_max;
  65         s8              backoff_val_range_min;
  66         u8              rx_gain_range_max;
  67         u8              rx_gain_range_min;
  68         u8              rssi_val_min;
  69
  70         u8              pre_cck_cca_thres;
  71         u8              cur_cck_cca_thres;
  72         u8              pre_cck_pd_state;
  73         u8              cur_cck_pd_state;
  74         u8              cck_pd_backup;
  75         u8              pause_cckpd_level;
  76         u8              pause_cckpd_value[DM_DIG_MAX_PAUSE_TYPE + 1];
  77
  78         u8              large_fa_hit;
  79         u8              large_fa_timeout;               /*if (large_fa_hit), monitor "large_fa_timeout" sec, if timeout, large_fa_hit=0*/
  80         u8              forbidden_igi;
  81         u32             recover_cnt;
  82
  83         u8              dig_dynamic_min_0;
  84         u8              dig_dynamic_min_1;
  85         boolean         is_media_connect_0;
  86         boolean         is_media_connect_1;
  87
  88         u32             ant_div_rssi_max;
  89         u32             RSSI_max;
  90
  91         u8              *is_p2p_in_process;
  92
  93         u8              pause_dig_level;
  94         u8              pause_dig_value[DM_DIG_MAX_PAUSE_TYPE + 1];
  95
  96         u32             cck_fa_ma;
  97         enum dig_goupcheck_level                dig_go_up_check_level;
  98         u8              aaa_default;
  99
 100 #if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
 101         boolean                                 is_tp_target;
 102         boolean                                 is_noise_est;
 103         u32                                     tp_train_th_min;
 104         u8                                      igi_offset_a;
 105         u8                                      igi_offset_b;
 106 #endif
 107
 108 #if (RTL8822B_SUPPORT == 1 || RTL8197F_SUPPORT == 1 || RTL8821C_SUPPORT == 1)
 109         u8              rf_gain_idx;
 110         u8              agc_table_idx;
 111         u8              big_jump_lmt[16];
 112         u8              enable_adjust_big_jump:1;
 113         u8              big_jump_step1:3;
 114         u8              big_jump_step2:2;
 115         u8              big_jump_step3:2;
 116 #endif
 117
 118 #if (DIG_HW == 1)
 119         u8              pre_rssi_min;
 120 #endif
 121 };
 122
 123 struct _FALSE_ALARM_STATISTICS {
 124         u32             cnt_parity_fail;
 125         u32             cnt_rate_illegal;
 126         u32             cnt_crc8_fail;
 127         u32             cnt_mcs_fail;
 128         u32             cnt_ofdm_fail;
 129         u32             cnt_ofdm_fail_pre;      /* For RTL8881A */
 130         u32             cnt_cck_fail;
 131         u32             cnt_all;
 132         u32             cnt_all_pre;
 133         u32             cnt_fast_fsync;
 134         u32             cnt_sb_search_fail;
 135         u32             cnt_ofdm_cca;
 136         u32             cnt_cck_cca;
 137         u32             cnt_cca_all;
 138         u32             cnt_bw_usc;     /* Gary */
 139         u32             cnt_bw_lsc;     /* Gary */
 140         u32             cnt_cck_crc32_error;
 141         u32             cnt_cck_crc32_ok;
 142         u32             cnt_ofdm_crc32_error;
 143         u32             cnt_ofdm_crc32_ok;
 144         u32             cnt_ht_crc32_error;
 145         u32             cnt_ht_crc32_ok;
 146         u32             cnt_vht_crc32_error;
 147         u32             cnt_vht_crc32_ok;
 148         u32             cnt_crc32_error_all;
 149         u32             cnt_crc32_ok_all;
 150         boolean         cck_block_enable;
 151         boolean         ofdm_block_enable;
 152         u32             dbg_port0;
 153         boolean         edcca_flag;
 154 };
 155
 156 enum dm_dig_op_e {
 157         DIG_TYPE_THRESH_HIGH    = 0,
 158         DIG_TYPE_THRESH_LOW     = 1,
 159         DIG_TYPE_BACKOFF                = 2,
 160         DIG_TYPE_RX_GAIN_MIN    = 3,
 161         DIG_TYPE_RX_GAIN_MAX    = 4,
 162         DIG_TYPE_ENABLE         = 5,
 163         DIG_TYPE_DISABLE                = 6,
 164         DIG_OP_TYPE_MAX
 165 };
 166
 167 /*
 168 enum dm_cck_pdth_e
 169 {
 170         CCK_PD_STAGE_LowRssi = 0,
 171         CCK_PD_STAGE_HighRssi = 1,
 172         CCK_PD_STAGE_MAX = 3,
 173 };
 174
 175 enum dm_dig_ext_port_alg_e
 176 {
 177         DIG_EXT_PORT_STAGE_0 = 0,
 178         DIG_EXT_PORT_STAGE_1 = 1,
 179         DIG_EXT_PORT_STAGE_2 = 2,
 180         DIG_EXT_PORT_STAGE_3 = 3,
 181         DIG_EXT_PORT_STAGE_MAX = 4,
 182 };
 183
 184 enum dm_dig_connect_e
 185 {
 186         DIG_STA_DISCONNECT = 0,
 187         DIG_STA_CONNECT = 1,
 188         DIG_STA_BEFORE_CONNECT = 2,
 189         dig_multi_sta_disconnect = 3,
 190         dig_multi_sta_connect = 4,
 191         DIG_CONNECT_MAX
 192 };
 193
 194
 195 #define DM_MultiSTA_InitGainChangeNotify(Event) {dm_dig_table.cur_multi_sta_connect_state = Event;}
 196
 197 #define DM_MultiSTA_InitGainChangeNotify_CONNECT(_ADAPTER)      \
 198         DM_MultiSTA_InitGainChangeNotify(dig_multi_sta_connect)
 199
 200 #define DM_MultiSTA_InitGainChangeNotify_DISCONNECT(_ADAPTER)   \
 201         DM_MultiSTA_InitGainChangeNotify(dig_multi_sta_disconnect)
 202 */
 203
 204 enum phydm_pause_type {
 205         PHYDM_PAUSE = BIT(0),
 206         PHYDM_RESUME = BIT(1)
 207 };
 208
 209 enum phydm_pause_level {
 210         /* number of pause level can't exceed DM_DIG_MAX_PAUSE_TYPE */
 211         PHYDM_PAUSE_LEVEL_0 = 0,
 212         PHYDM_PAUSE_LEVEL_1 = 1,
 213         PHYDM_PAUSE_LEVEL_2 = 2,
 214         PHYDM_PAUSE_LEVEL_3 = 3,
 215         PHYDM_PAUSE_LEVEL_4 = 4,
 216         PHYDM_PAUSE_LEVEL_5 = 5,
 217         PHYDM_PAUSE_LEVEL_6 = 6,
 218         PHYDM_PAUSE_LEVEL_7 = DM_DIG_MAX_PAUSE_TYPE             /* maximum level */
 219 };
 220
 221 #define         DM_DIG_THRESH_HIGH                      40
 222 #define         DM_DIG_THRESH_LOW                       35
 223
 224 #define         DM_FALSEALARM_THRESH_LOW        400
 225 #define         DM_FALSEALARM_THRESH_HIGH       1000
 226
 227 #define         DM_DIG_MAX_NIC                          0x3e
 228 #define         DM_DIG_MIN_NIC                          0x20
 229 #define         DM_DIG_MAX_OF_MIN_NIC           0x3e
 230
 231 #if (DIG_HW == 1)
 232 #define         DM_DIG_MAX_AP                                   p_dm_odm->priv->pshare->rf_ft_var.dbg_dig_upper /* 0x3e */
 233 #define         DM_DIG_MIN_AP                                   ((p_dm_odm->support_ic_type & (ODM_RTL8812 | ODM_RTL8822B)) ? 0x1c : 0x20)/* 0x1c */
 234 #else
 235 #define         DM_DIG_MAX_AP                                   0x3e
 236 #define         DM_DIG_MIN_AP                                   0x20
 237 #endif
 238 #define         DM_DIG_MAX_OF_MIN                       0x2A    /* 0x32 */
 239 #define         DM_DIG_MIN_AP_DFS                               0x20
 240
 241 #define         DM_DIG_MAX_NIC_HP                       0x46
 242 #define         DM_DIG_MIN_NIC_HP                               0x2e
 243
 244 #define         DM_DIG_MAX_AP_HP                                0x42
 245 #define         DM_DIG_MIN_AP_HP                                0x30
 246
 247 #if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
 248         #define         DM_DIG_MAX_AP_COVERAGR          0x26
 249 #if (DIG_HW == 1)
 250         #define         DM_DIG_MIN_AP_COVERAGE          ((p_dm_odm->support_ic_type & (ODM_RTL8812 | ODM_RTL8822B)) ? 0x1c : 0x20)
 251 #else
 252         #define         DM_DIG_MIN_AP_COVERAGE          0x1c
 253 #endif
 254         #define         DM_DIG_MAX_OF_MIN_COVERAGE      0x22
 255
 256         #define         dm_dig_tp_target_th0                    500
 257         #define         dm_dig_tp_target_th1                    1000
 258         #define         dm_dig_tp_training_period               10
 259 #endif
 260
 261 /* vivi 92c&92d has different definition, 20110504
 262  * this is for 92c */
 263 #if (DM_ODM_SUPPORT_TYPE & ODM_CE)
 264         #ifdef CONFIG_SPECIAL_SETTING_FOR_FUNAI_TV
 265                 #define         DM_DIG_FA_TH0                           0x80/* 0x20 */
 266         #else
 267                 #define         DM_DIG_FA_TH0                           0x200/* 0x20 */
 268         #endif
 269 #else
 270         #define         DM_DIG_FA_TH0                           0x200/* 0x20 */
 271 #endif
 272
 273 #define         DM_DIG_FA_TH1                                   0x300
 274 #define         DM_DIG_FA_TH2                                   0x400
 275 /* this is for 92d */
 276 #define         DM_DIG_FA_TH0_92D                               0x100
 277 #define         DM_DIG_FA_TH1_92D                               0x400
 278 #define         DM_DIG_FA_TH2_92D                               0x600
 279
 280 #define         DM_DIG_BACKOFF_MAX                      12
 281 #define         DM_DIG_BACKOFF_MIN                      -4
 282 #define         DM_DIG_BACKOFF_DEFAULT          10
 283
 284 #define         DM_DIG_FA_TH0_LPS                               4 /* -> 4 in lps */
 285 #define         DM_DIG_FA_TH1_LPS                               15 /* -> 15 lps */
 286 #define         DM_DIG_FA_TH2_LPS                               30 /* -> 30 lps */
 287 #define         RSSI_OFFSET_DIG                         0x05
 288 #define         LARGE_FA_TIMEOUT                                60
 289
 290
 291 void
 292 odm_change_dynamic_init_gain_thresh(
 293         void                                    *p_dm_void,
 294         u32                                     dm_type,
 295         u32                                     dm_value
 296 );
 297
 298 void
 299 odm_write_dig(
 300         void                                    *p_dm_void,
 301         u8                                      current_igi
 302 );
 303
 304 void
 305 odm_pause_dig(
 306         void                                    *p_dm_void,
 307         enum phydm_pause_type           pause_type,
 308         enum phydm_pause_level          pause_level,
 309         u8                                      igi_value
 310 );
 311
 312 void
 313 odm_dig_init(
 314         void                                    *p_dm_void
 315 );
 316
 317 void
 318 odm_DIG(
 319         void                                    *p_dm_void
 320 );
 321
 322 void
 323 odm_dig_by_rssi_lps(
 324         void                                    *p_dm_void
 325 );
 326
 327 void
 328 odm_false_alarm_counter_statistics(
 329         void                                    *p_dm_void
 330 );
 331
 332 void
 333 odm_pause_cck_packet_detection(
 334         void                                    *p_dm_void,
 335         enum phydm_pause_type           pause_type,
 336         enum phydm_pause_level          pause_level,
 337         u8                                      cck_pd_threshold
 338 );
 339
 340 void
 341 odm_cck_packet_detection_thresh(
 342         void                                    *p_dm_void
 343 );
 344
 345 void
 346 odm_write_cck_cca_thres(
 347         void                                    *p_dm_void,
 348         u8                                      cur_cck_cca_thres
 349 );
 350
 351 boolean
 352 phydm_dig_go_up_check(
 353         void            *p_dm_void
 354 );
 355
 356 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
 357 void
 358 odm_mpt_dig_callback(
 359         struct timer_list                                               *p_timer
 360 );
 361
 362 void
 363 odm_mpt_dig_work_item_callback(
 364         void                    *p_context
 365 );
 366
 367 #endif
 368
 369 #if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
 370 void
 371 odm_mpt_dig_callback(
 372         void                                    *p_dm_void
 373 );
 374 #endif
 375
 376 #if (DM_ODM_SUPPORT_TYPE != ODM_CE)
 377 void
 378 ODM_MPT_DIG(
 379         void                                    *p_dm_void
 380 );
 381 #endif
 382
 383
 384 #endif