drivers/net/wireless/rockchip_wlan/rtl8723cs/hal/phydm/phydm_edcaturbocheck.h

   1 /******************************************************************************
   2  *
   3  * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of version 2 of the GNU General Public License as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program; if not, write to the Free Software Foundation, Inc.,
  16  * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  17  *
  18  *
  19  ******************************************************************************/
  20
  21 #ifndef __PHYDMEDCATURBOCHECK_H__
  22 #define    __PHYDMEDCATURBOCHECK_H__
  23
  24 #if PHYDM_SUPPORT_EDCA
  25 /*#define EDCATURBO_VERSION     "2.1"*/
  26 #define EDCATURBO_VERSION       "2.3"   /*2015.07.29 by YuChen*/
  27
  28 struct _EDCA_TURBO_ {
  29         boolean is_current_turbo_edca;
  30         boolean is_cur_rdl_state;
  31
  32 #if (DM_ODM_SUPPORT_TYPE == ODM_CE)
  33         u32     prv_traffic_idx; /* edca turbo */
  34 #endif
  35
  36 };
  37
  38 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
  39 static u32 edca_setting_UL[HT_IOT_PEER_MAX] =
  40         /* UNKNOWN              REALTEK_90      REALTEK_92SE    BROADCOM                RALINK          ATHEROS         CISCO           MERU        MARVELL     92U_AP          SELF_AP(DownLink/Tx) */
  41 { 0x5e4322,             0xa44f,         0x5e4322,               0x5ea32b,               0x5ea422,       0x5ea322,       0x3ea430,       0x5ea42b, 0x5ea44f,     0x5e4322,       0x5e4322};
  42
  43
  44 static u32 edca_setting_DL[HT_IOT_PEER_MAX] =
  45         /* UNKNOWN              REALTEK_90      REALTEK_92SE    BROADCOM                RALINK          ATHEROS         CISCO           MERU,       MARVELL     92U_AP          SELF_AP(UpLink/Rx) */
  46 { 0xa44f,               0x5ea44f,       0x5e4322,               0x5ea42b,               0xa44f,         0xa630,         0x5ea630,       0x5ea42b, 0xa44f,               0xa42b,         0xa42b};
  47
  48 static u32 edca_setting_dl_g_mode[HT_IOT_PEER_MAX] =
  49         /* UNKNOWN              REALTEK_90      REALTEK_92SE    BROADCOM                RALINK          ATHEROS         CISCO           MERU,       MARVELL     92U_AP          SELF_AP */
  50 { 0x4322,               0xa44f,         0x5e4322,               0xa42b,                 0x5e4322,       0x4322,         0xa42b,         0x5ea42b, 0xa44f,               0x5e4322,       0x5ea42b};
  51
  52 #endif
  53
  54
  55
  56 void
  57 odm_edca_turbo_check(
  58         void            *p_dm_void
  59 );
  60 void
  61 odm_edca_turbo_init(
  62         void            *p_dm_void
  63 );
  64
  65 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
  66 void
  67 odm_edca_turbo_check_mp(
  68         void            *p_dm_void
  69 );
  70
  71 /* check if edca turbo is disabled */
  72 boolean
  73 odm_is_edca_turbo_disable(
  74         void            *p_dm_void
  75 );
  76 /* choose edca paramter for special IOT case */
  77 void
  78 odm_edca_para_sel_by_iot(
  79         void                                    *p_dm_void,
  80         u32             *EDCA_BE_UL,
  81         u32             *EDCA_BE_DL
  82 );
  83 /* check if it is UL or DL */
  84 void
  85 odm_edca_choose_traffic_idx(
  86         void            *p_dm_void,
  87         u64                     cur_tx_bytes,
  88         u64                     cur_rx_bytes,
  89         boolean         is_bias_on_rx,
  90         boolean         *p_is_cur_rdl_state
  91 );
  92
  93 #elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
  94 void
  95 odm_edca_turbo_check_ce(
  96         void            *p_dm_void
  97 );
  98 #endif
  99
 100 #endif /*PHYDM_SUPPORT_EDCA*/
 101
 102 #endif