drivers/net/wireless/rockchip_wlan/rtl8723cs/hal/phydm/phydm_hwconfig.c

   1 /******************************************************************************
   2  *
   3  * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of version 2 of the GNU General Public License as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program; if not, write to the Free Software Foundation, Inc.,
  16  * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  17  *
  18  *
  19  ******************************************************************************/
  20
  21 /* ************************************************************
  22  * include files
  23  * ************************************************************ */
  24
  25 #include "mp_precomp.h"
  26 #include "phydm_precomp.h"
  27
  28 #define READ_AND_CONFIG_MP(ic, txt) (odm_read_and_config_mp_##ic##txt(p_dm_odm))
  29 #define READ_AND_CONFIG_TC(ic, txt) (odm_read_and_config_tc_##ic##txt(p_dm_odm))
  30
  31
  32 #if (PHYDM_TESTCHIP_SUPPORT == 1)
  33 #define READ_AND_CONFIG(ic, txt) do {\
  34                 if (p_dm_odm->is_mp_chip)\
  35                         READ_AND_CONFIG_MP(ic, txt);\
  36                 else\
  37                         READ_AND_CONFIG_TC(ic, txt);\
  38         } while (0)
  39 #else
  40 #define READ_AND_CONFIG     READ_AND_CONFIG_MP
  41 #endif
  42
  43
  44 #define READ_FIRMWARE_MP(ic, txt)               (odm_read_firmware_mp_##ic##txt(p_dm_odm, p_firmware, p_size))
  45 #define READ_FIRMWARE_TC(ic, txt)               (odm_read_firmware_tc_##ic##txt(p_dm_odm, p_firmware, p_size))
  46
  47 #if (PHYDM_TESTCHIP_SUPPORT == 1)
  48 #define READ_FIRMWARE(ic, txt) do {\
  49                 if (p_dm_odm->is_mp_chip)\
  50                         READ_FIRMWARE_MP(ic, txt);\
  51                 else\
  52                         READ_FIRMWARE_TC(ic, txt);\
  53         } while (0)
  54 #else
  55 #define READ_FIRMWARE     READ_FIRMWARE_MP
  56 #endif
  57
  58 #define GET_VERSION_MP(ic, txt)         (odm_get_version_mp_##ic##txt())
  59 #define GET_VERSION_TC(ic, txt)         (odm_get_version_tc_##ic##txt())
  60
  61 #if (PHYDM_TESTCHIP_SUPPORT == 1)
  62         #define GET_VERSION(ic, txt) (p_dm_odm->is_mp_chip ? GET_VERSION_MP(ic, txt) : GET_VERSION_TC(ic, txt))
  63 #else
  64         #define GET_VERSION(ic, txt) GET_VERSION_MP(ic, txt)
  65 #endif
  66
  67 u8
  68 odm_query_rx_pwr_percentage(
  69         s8              ant_power
  70 )
  71 {
  72         if ((ant_power <= -100) || (ant_power >= 20))
  73                 return  0;
  74         else if (ant_power >= 0)
  75                 return  100;
  76         else
  77                 return 100 + ant_power;
  78 }
  79
  80
  81 /*
  82  * 2012/01/12 MH MOve some signal strength smooth method to MP HAL layer.
  83  * IF other SW team do not support the feature, remove this section.??
  84  *   */
  85 s32
  86 odm_signal_scale_mapping_92c_series_patch_rt_cid_819x_lenovo(
  87         struct PHY_DM_STRUCT *p_dm_odm,
  88         s32 curr_sig
  89 )
  90 {
  91         s32 ret_sig = 0;
  92 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
  93         /* if(p_dm_odm->support_interface  == ODM_ITRF_PCIE) */
  94         {
  95                 /* step 1. Scale mapping. */
  96                 /* 20100611 Joseph: Re-tunning RSSI presentation for Lenovo. */
  97                 /* 20100426 Joseph: Modify Signal strength mapping. */
  98                 /* This modification makes the RSSI indication similar to Intel solution. */
  99                 /* 20100414 Joseph: Tunning RSSI for Lenovo according to RTL8191SE. */
 100                 if (curr_sig >= 54 && curr_sig <= 100)
 101                         ret_sig = 100;
 102                 else if (curr_sig >= 42 && curr_sig <= 53)
 103                         ret_sig = 95;
 104                 else if (curr_sig >= 36 && curr_sig <= 41)
 105                         ret_sig = 74 + ((curr_sig - 36) * 20) / 6;
 106                 else if (curr_sig >= 33 && curr_sig <= 35)
 107                         ret_sig = 65 + ((curr_sig - 33) * 8) / 2;
 108                 else if (curr_sig >= 18 && curr_sig <= 32)
 109                         ret_sig = 62 + ((curr_sig - 18) * 2) / 15;
 110                 else if (curr_sig >= 15 && curr_sig <= 17)
 111                         ret_sig = 33 + ((curr_sig - 15) * 28) / 2;
 112                 else if (curr_sig >= 10 && curr_sig <= 14)
 113                         ret_sig = 39;
 114                 else if (curr_sig >= 8 && curr_sig <= 9)
 115                         ret_sig = 33;
 116                 else if (curr_sig <= 8)
 117                         ret_sig = 19;
 118         }
 119 #endif /* ENDIF (DM_ODM_SUPPORT_TYPE == ODM_WIN) */
 120         return ret_sig;
 121 }
 122
 123 s32
 124 odm_signal_scale_mapping_92c_series_patch_rt_cid_819x_netcore(
 125         struct PHY_DM_STRUCT *p_dm_odm,
 126         s32 curr_sig
 127 )
 128 {
 129         s32 ret_sig = 0;
 130 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
 131         /* if(p_dm_odm->support_interface  == ODM_ITRF_USB) */
 132         {
 133                 /* Netcore request this modification because 2009.04.13 SU driver use it. */
 134                 if (curr_sig >= 31 && curr_sig <= 100)
 135                         ret_sig = 100;
 136                 else if (curr_sig >= 21 && curr_sig <= 30)
 137                         ret_sig = 90 + ((curr_sig - 20) / 1);
 138                 else if (curr_sig >= 11 && curr_sig <= 20)
 139                         ret_sig = 80 + ((curr_sig - 10) / 1);
 140                 else if (curr_sig >= 7 && curr_sig <= 10)
 141                         ret_sig = 69 + (curr_sig - 7);
 142                 else if (curr_sig == 6)
 143                         ret_sig = 54;
 144                 else if (curr_sig == 5)
 145                         ret_sig = 45;
 146                 else if (curr_sig == 4)
 147                         ret_sig = 36;
 148                 else if (curr_sig == 3)
 149                         ret_sig = 27;
 150                 else if (curr_sig == 2)
 151                         ret_sig = 18;
 152                 else if (curr_sig == 1)
 153                         ret_sig = 9;
 154                 else
 155                         ret_sig = curr_sig;
 156         }
 157 #endif /* ENDIF (DM_ODM_SUPPORT_TYPE == ODM_WIN) */
 158         return ret_sig;
 159 }
 160
 161
 162 s32
 163 odm_signal_scale_mapping_92c_series(
 164         struct PHY_DM_STRUCT *p_dm_odm,
 165         s32 curr_sig
 166 )
 167 {
 168         s32 ret_sig = 0;
 169 #if (DEV_BUS_TYPE == RT_PCI_INTERFACE)
 170         if (p_dm_odm->support_interface  == ODM_ITRF_PCIE) {
 171                 /* step 1. Scale mapping. */
 172                 if (curr_sig >= 61 && curr_sig <= 100)
 173                         ret_sig = 90 + ((curr_sig - 60) / 4);
 174                 else if (curr_sig >= 41 && curr_sig <= 60)
 175                         ret_sig = 78 + ((curr_sig - 40) / 2);
 176                 else if (curr_sig >= 31 && curr_sig <= 40)
 177                         ret_sig = 66 + (curr_sig - 30);
 178                 else if (curr_sig >= 21 && curr_sig <= 30)
 179                         ret_sig = 54 + (curr_sig - 20);
 180                 else if (curr_sig >= 5 && curr_sig <= 20)
 181                         ret_sig = 42 + (((curr_sig - 5) * 2) / 3);
 182                 else if (curr_sig == 4)
 183                         ret_sig = 36;
 184                 else if (curr_sig == 3)
 185                         ret_sig = 27;
 186                 else if (curr_sig == 2)
 187                         ret_sig = 18;
 188                 else if (curr_sig == 1)
 189                         ret_sig = 9;
 190                 else
 191                         ret_sig = curr_sig;
 192         }
 193 #endif
 194
 195 #if ((DEV_BUS_TYPE == RT_USB_INTERFACE) || (DEV_BUS_TYPE == RT_SDIO_INTERFACE))
 196         if ((p_dm_odm->support_interface  == ODM_ITRF_USB) || (p_dm_odm->support_interface  == ODM_ITRF_SDIO)) {
 197                 if (curr_sig >= 51 && curr_sig <= 100)
 198                         ret_sig = 100;
 199                 else if (curr_sig >= 41 && curr_sig <= 50)
 200                         ret_sig = 80 + ((curr_sig - 40) * 2);
 201                 else if (curr_sig >= 31 && curr_sig <= 40)
 202                         ret_sig = 66 + (curr_sig - 30);
 203                 else if (curr_sig >= 21 && curr_sig <= 30)
 204                         ret_sig = 54 + (curr_sig - 20);
 205                 else if (curr_sig >= 10 && curr_sig <= 20)
 206                         ret_sig = 42 + (((curr_sig - 10) * 2) / 3);
 207                 else if (curr_sig >= 5 && curr_sig <= 9)
 208                         ret_sig = 22 + (((curr_sig - 5) * 3) / 2);
 209                 else if (curr_sig >= 1 && curr_sig <= 4)
 210                         ret_sig = 6 + (((curr_sig - 1) * 3) / 2);
 211                 else
 212                         ret_sig = curr_sig;
 213         }
 214
 215 #endif
 216         return ret_sig;
 217 }
 218 s32
 219 odm_signal_scale_mapping(
 220         struct PHY_DM_STRUCT *p_dm_odm,
 221         s32 curr_sig
 222 )
 223 {
 224 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
 225         if ((p_dm_odm->support_platform == ODM_WIN) &&
 226             (p_dm_odm->support_interface  != ODM_ITRF_PCIE) && /* USB & SDIO */
 227             (p_dm_odm->patch_id == 10)) /* p_mgnt_info->customer_id == RT_CID_819x_Netcore */
 228                 return odm_signal_scale_mapping_92c_series_patch_rt_cid_819x_netcore(p_dm_odm, curr_sig);
 229         else if ((p_dm_odm->support_platform == ODM_WIN) &&
 230                  (p_dm_odm->support_interface  == ODM_ITRF_PCIE) &&
 231                 (p_dm_odm->patch_id == 19)) /* p_mgnt_info->customer_id == RT_CID_819X_LENOVO) */
 232                 return odm_signal_scale_mapping_92c_series_patch_rt_cid_819x_lenovo(p_dm_odm, curr_sig);
 233         else
 234 #endif
 235         {
 236 #ifdef CONFIG_SIGNAL_SCALE_MAPPING
 237                 return odm_signal_scale_mapping_92c_series(p_dm_odm, curr_sig);
 238 #else
 239                 return curr_sig;
 240 #endif
 241         }
 242
 243 }
 244
 245
 246
 247 static u8 odm_sq_process_patch_rt_cid_819x_lenovo(
 248         struct PHY_DM_STRUCT    *p_dm_odm,
 249         u8              is_cck_rate,
 250         u8              PWDB_ALL,
 251         u8              path,
 252         u8              RSSI
 253 )
 254 {
 255         u8      SQ = 0;
 256 #if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
 257
 258         if (is_cck_rate) {
 259
 260                 if (IS_HARDWARE_TYPE_8192E(p_dm_odm->adapter)) {
 261
 262                         /*  */
 263                         /* <Roger_Notes> Expected signal strength and bars indication at Lenovo lab. 2013.04.11 */
 264                         /* 802.11n, 802.11b, 802.11g only at channel 6 */
 265                         /*  */
 266                         /*              Attenuation (dB)        OS Signal Bars  RSSI by Xirrus (dBm) */
 267                         /*                      50                              5                       -49 */
 268                         /*                      55                              5                       -49 */
 269                         /*                      60                              5                       -50 */
 270                         /*                      65                              5                       -51 */
 271                         /*                      70                              5                       -52 */
 272                         /*                      75                              5                       -54 */
 273                         /*                      80                              5                       -55 */
 274                         /*                      85                              4                       -60 */
 275                         /*                      90                              3                       -63 */
 276                         /*                      95                              3                       -65 */
 277                         /*                      100                             2                       -67 */
 278                         /*                      102                             2                       -67 */
 279                         /*                      104                             1                       -70 */
 280                         /*  */
 281
 282                         if (PWDB_ALL >= 50)
 283                                 SQ = 100;
 284                         else if (PWDB_ALL >= 35 && PWDB_ALL < 50)
 285                                 SQ = 80;
 286                         else if (PWDB_ALL >= 31 && PWDB_ALL < 35)
 287                                 SQ = 60;
 288                         else if (PWDB_ALL >= 22 && PWDB_ALL < 31)
 289                                 SQ = 40;
 290                         else if (PWDB_ALL >= 18 && PWDB_ALL < 22)
 291                                 SQ = 20;
 292                         else
 293                                 SQ = 10;
 294                 } else {
 295                         if (PWDB_ALL >= 50)
 296                                 SQ = 100;
 297                         else if (PWDB_ALL >= 35 && PWDB_ALL < 50)
 298                                 SQ = 80;
 299                         else if (PWDB_ALL >= 22 && PWDB_ALL < 35)
 300                                 SQ = 60;
 301                         else if (PWDB_ALL >= 18 && PWDB_ALL < 22)
 302                                 SQ = 40;
 303                         else
 304                                 SQ = 10;
 305                 }
 306
 307         } else {
 308                 /* OFDM rate */
 309
 310                 if (IS_HARDWARE_TYPE_8192E(p_dm_odm->adapter)) {
 311                         if (RSSI >= 45)
 312                                 SQ = 100;
 313                         else if (RSSI >= 22 && RSSI < 45)
 314                                 SQ = 80;
 315                         else if (RSSI >= 18 && RSSI < 22)
 316                                 SQ = 40;
 317                         else
 318                                 SQ = 20;
 319                 } else {
 320                         if (RSSI >= 45)
 321                                 SQ = 100;
 322                         else if (RSSI >= 22 && RSSI < 45)
 323                                 SQ = 80;
 324                         else if (RSSI >= 18 && RSSI < 22)
 325                                 SQ = 40;
 326                         else
 327                                 SQ = 20;
 328                 }
 329         }
 330
 331         RT_TRACE(COMP_DBG, DBG_TRACE, ("is_cck_rate(%#d), PWDB_ALL(%#d), RSSI(%#d), SQ(%#d)\n", is_cck_rate, PWDB_ALL, RSSI, SQ));
 332
 333 #endif
 334         return SQ;
 335 }
 336
 337 static u8 odm_sq_process_patch_rt_cid_819x_acer(
 338         struct PHY_DM_STRUCT    *p_dm_odm,
 339         u8              is_cck_rate,
 340         u8              PWDB_ALL,
 341         u8              path,
 342         u8              RSSI
 343 )
 344 {
 345         u8      SQ = 0;
 346
 347 #if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
 348
 349         if (is_cck_rate) {
 350
 351                 RT_TRACE(COMP_DBG, DBG_WARNING, ("odm_SQ_process_patch_RT_Acer\n"));
 352
 353 #if OS_WIN_FROM_WIN8(OS_VERSION)
 354
 355                 if (PWDB_ALL >= 50)
 356                         SQ = 100;
 357                 else if (PWDB_ALL >= 35 && PWDB_ALL < 50)
 358                         SQ = 80;
 359                 else if (PWDB_ALL >= 30 && PWDB_ALL < 35)
 360                         SQ = 60;
 361                 else if (PWDB_ALL >= 25 && PWDB_ALL < 30)
 362                         SQ = 40;
 363                 else if (PWDB_ALL >= 20 && PWDB_ALL < 25)
 364                         SQ = 20;
 365                 else
 366                         SQ = 10;
 367 #else
 368                 if (PWDB_ALL >= 50)
 369                         SQ = 100;
 370                 else if (PWDB_ALL >= 35 && PWDB_ALL < 50)
 371                         SQ = 80;
 372                 else if (PWDB_ALL >= 30 && PWDB_ALL < 35)
 373                         SQ = 60;
 374                 else if (PWDB_ALL >= 25 && PWDB_ALL < 30)
 375                         SQ = 40;
 376                 else if (PWDB_ALL >= 20 && PWDB_ALL < 25)
 377                         SQ = 20;
 378                 else
 379                         SQ = 10;
 380
 381                 if (PWDB_ALL == 0) /* Abnormal case, do not indicate the value above 20 on Win7 */
 382                         SQ = 20;
 383 #endif
 384
 385
 386
 387         } else {
 388                 /* OFDM rate */
 389
 390                 if (IS_HARDWARE_TYPE_8192E(p_dm_odm->adapter)) {
 391                         if (RSSI >= 45)
 392                                 SQ = 100;
 393                         else if (RSSI >= 22 && RSSI < 45)
 394                                 SQ = 80;
 395                         else if (RSSI >= 18 && RSSI < 22)
 396                                 SQ = 40;
 397                         else
 398                                 SQ = 20;
 399                 } else {
 400                         if (RSSI >= 35)
 401                                 SQ = 100;
 402                         else if (RSSI >= 30 && RSSI < 35)
 403                                 SQ = 80;
 404                         else if (RSSI >= 25 && RSSI < 30)
 405                                 SQ = 40;
 406                         else
 407                                 SQ = 20;
 408                 }
 409         }
 410
 411         RT_TRACE(COMP_DBG, DBG_LOUD, ("is_cck_rate(%#d), PWDB_ALL(%#d), RSSI(%#d), SQ(%#d)\n", is_cck_rate, PWDB_ALL, RSSI, SQ));
 412
 413 #endif
 414         return SQ;
 415 }
 416
 417 static u8
 418 odm_evm_db_to_percentage(
 419         s8 value
 420 )
 421 {
 422         /*  */
 423         /* -33dB~0dB to 0%~99% */
 424         /*  */
 425         s8 ret_val;
 426
 427         ret_val = value;
 428         ret_val /= 2;
 429
 430         /*dbg_print("value=%d\n", value);*/
 431         /*ODM_RT_DISP(FRX, RX_PHY_SQ, ("EVMdbToPercentage92C value=%d / %x\n", ret_val, ret_val));*/
 432 #ifdef ODM_EVM_ENHANCE_ANTDIV
 433         if (ret_val >= 0)
 434                 ret_val = 0;
 435
 436         if (ret_val <= -40)
 437                 ret_val = -40;
 438
 439         ret_val = 0 - ret_val;
 440         ret_val *= 3;
 441 #else
 442         if (ret_val >= 0)
 443                 ret_val = 0;
 444
 445         if (ret_val <= -33)
 446                 ret_val = -33;
 447
 448         ret_val = 0 - ret_val;
 449         ret_val *= 3;
 450
 451         if (ret_val == 99)
 452                 ret_val = 100;
 453 #endif
 454
 455         return (u8)ret_val;
 456 }
 457
 458 static u8
 459 odm_evm_dbm_jaguar_series(
 460         s8 value
 461 )
 462 {
 463         s8 ret_val = value;
 464
 465         /* -33dB~0dB to 33dB ~ 0dB */
 466         if (ret_val == -128)
 467                 ret_val = 127;
 468         else if (ret_val < 0)
 469                 ret_val = 0 - ret_val;
 470
 471         ret_val  = ret_val >> 1;
 472         return (u8)ret_val;
 473 }
 474
 475 static s16
 476 odm_cfo(
 477         s8 value
 478 )
 479 {
 480         s16  ret_val;
 481
 482         if (value < 0) {
 483                 ret_val = 0 - value;
 484                 ret_val = (ret_val << 1) + (ret_val >> 1) ;  /* *2.5~=312.5/2^7 */
 485                 ret_val = ret_val | BIT(12);  /* set bit12 as 1 for negative cfo */
 486         } else {
 487                 ret_val = value;
 488                 ret_val = (ret_val << 1) + (ret_val >> 1) ; /* *2.5~=312.5/2^7 */
 489         }
 490         return ret_val;
 491 }
 492
 493 u8
 494 phydm_rate_to_num_ss(
 495         struct PHY_DM_STRUCT            *p_dm_odm,
 496         u8                      data_rate
 497 )
 498 {
 499         u8      num_ss = 1;
 500
 501         if (data_rate  <= ODM_RATE54M)
 502                 num_ss = 1;
 503         else if (data_rate  <= ODM_RATEMCS31)
 504                 num_ss = ((data_rate  - ODM_RATEMCS0) >> 3) + 1;
 505         else if (data_rate  <= ODM_RATEVHTSS1MCS9)
 506                 num_ss = 1;
 507         else if (data_rate  <= ODM_RATEVHTSS2MCS9)
 508                 num_ss = 2;
 509         else if (data_rate  <= ODM_RATEVHTSS3MCS9)
 510                 num_ss = 3;
 511         else if (data_rate  <= ODM_RATEVHTSS4MCS9)
 512                 num_ss = 4;
 513
 514         return num_ss;
 515 }
 516
 517 #if (ODM_IC_11N_SERIES_SUPPORT == 1)
 518
 519 #if (RTL8703B_SUPPORT == 1)
 520 s8
 521 odm_CCKRSSI_8703B(
 522         u16     LNA_idx,
 523         u8      VGA_idx
 524 )
 525 {
 526         s8      rx_pwr_all = 0x00;
 527
 528         switch (LNA_idx) {
 529         case 0xf:
 530                 rx_pwr_all = -48 - (2 * VGA_idx);
 531                 break;
 532         case 0xb:
 533                 rx_pwr_all = -42 - (2 * VGA_idx); /*TBD*/
 534                 break;
 535         case 0xa:
 536                 rx_pwr_all = -36 - (2 * VGA_idx);
 537                 break;
 538         case 8:
 539                 rx_pwr_all = -32 - (2 * VGA_idx);
 540                 break;
 541         case 7:
 542                 rx_pwr_all = -19 - (2 * VGA_idx);
 543                 break;
 544         case 4:
 545                 rx_pwr_all = -6 - (2 * VGA_idx);
 546                 break;
 547         case 0:
 548                 rx_pwr_all = -2 - (2 * VGA_idx);
 549                 break;
 550         default:
 551                 /*rx_pwr_all = -53+(2*(31-VGA_idx));*/
 552                 /*dbg_print("wrong LNA index\n");*/
 553                 break;
 554
 555         }
 556         return  rx_pwr_all;
 557 }
 558 #endif
 559
 560 #if (RTL8195A_SUPPORT == 1)
 561 s8
 562 odm_CCKRSSI_8195A(
 563         struct PHY_DM_STRUCT    *p_dm_odm,
 564         u16             LNA_idx,
 565         u8              VGA_idx
 566 )
 567 {
 568         s8      rx_pwr_all = 0;
 569         s8      lna_gain = 0;
 570         s8      lna_gain_table_0[8] = {0, -8, -15, -22, -29, -36, -45, -54};
 571         s8      lna_gain_table_1[8] = {0, -8, -15, -22, -29, -36, -45, -54};/*use 8195A to calibrate this table. 2016.06.24, Dino*/
 572
 573         if (p_dm_odm->cck_agc_report_type == 0)
 574                 lna_gain = lna_gain_table_0[LNA_idx];
 575         else
 576                 lna_gain = lna_gain_table_1[LNA_idx];
 577
 578         rx_pwr_all = lna_gain - (2 * VGA_idx);
 579
 580         return  rx_pwr_all;
 581 }
 582 #endif
 583
 584 #if (RTL8192E_SUPPORT == 1)
 585 s8
 586 odm_CCKRSSI_8192E(
 587         struct PHY_DM_STRUCT    *p_dm_odm,
 588         u16             LNA_idx,
 589         u8              VGA_idx
 590 )
 591 {
 592         s8      rx_pwr_all = 0;
 593         s8      lna_gain = 0;
 594         s8      lna_gain_table_0[8] = {15, 9, -10, -21, -23, -27, -43, -44};
 595         s8      lna_gain_table_1[8] = {24, 18, 13, -4, -11, -18, -31, -36};/*use 8192EU to calibrate this table. 2015.12.15, Dino*/
 596
 597         if (p_dm_odm->cck_agc_report_type == 0)
 598                 lna_gain = lna_gain_table_0[LNA_idx];
 599         else
 600                 lna_gain = lna_gain_table_1[LNA_idx];
 601
 602         rx_pwr_all = lna_gain - (2 * VGA_idx);
 603
 604         return  rx_pwr_all;
 605 }
 606 #endif
 607
 608 #if (RTL8188E_SUPPORT == 1)
 609 s8
 610 odm_CCKRSSI_8188E(
 611         struct PHY_DM_STRUCT    *p_dm_odm,
 612         u16             LNA_idx,
 613         u8              VGA_idx
 614 )
 615 {
 616         s8      rx_pwr_all = 0;
 617         s8      lna_gain = 0;
 618         s8      lna_gain_table_0[8] = {17, -1, -13, -29, -32, -35, -38, -41};/*only use lna0/1/2/3/7*/
 619         s8      lna_gain_table_1[8] = {29, 20, 12, 3, -6, -15, -24, -33}; /*only use lna3 /7*/
 620
 621         if (p_dm_odm->cut_version >= ODM_CUT_I) /*SMIC*/
 622                 lna_gain = lna_gain_table_0[LNA_idx];
 623         else     /*TSMC*/
 624                 lna_gain = lna_gain_table_1[LNA_idx];
 625
 626         rx_pwr_all = lna_gain - (2 * VGA_idx);
 627
 628         return  rx_pwr_all;
 629 }
 630 #endif
 631
 632 void
 633 odm_rx_phy_status92c_series_parsing(
 634         struct PHY_DM_STRUCT                                    *p_dm_odm,
 635         struct _odm_phy_status_info_                    *p_phy_info,
 636         u8                                              *p_phy_status,
 637         struct _odm_per_pkt_info_                       *p_pktinfo
 638 )
 639 {
 640         struct _sw_antenna_switch_                              *p_dm_swat_table = &p_dm_odm->dm_swat_table;
 641         u8                              i, max_spatial_stream;
 642         s8                              rx_pwr[4], rx_pwr_all = 0;
 643         u8                              EVM, PWDB_ALL = 0, PWDB_ALL_BT;
 644         u8                              RSSI, total_rssi = 0;
 645         boolean                         is_cck_rate = false;
 646         u8                              rf_rx_num = 0;
 647         u8                              cck_highpwr = 0;
 648         u8                              LNA_idx = 0;
 649         u8                              VGA_idx = 0;
 650         u8                              cck_agc_rpt;
 651         u8                              num_ss;
 652         struct _phy_status_rpt_8192cd *p_phy_sta_rpt = (struct _phy_status_rpt_8192cd *)p_phy_status;
 653
 654         is_cck_rate = (p_pktinfo->data_rate <= ODM_RATE11M) ? true : false;
 655
 656         if (p_pktinfo->is_to_self)
 657                 p_dm_odm->curr_station_id = p_pktinfo->station_id;
 658
 659         p_phy_info->rx_mimo_signal_quality[ODM_RF_PATH_A] = -1;
 660         p_phy_info->rx_mimo_signal_quality[ODM_RF_PATH_B] = -1;
 661
 662
 663         if (is_cck_rate) {
 664                 p_dm_odm->phy_dbg_info.num_qry_phy_status_cck++;
 665                 cck_agc_rpt =  p_phy_sta_rpt->cck_agc_rpt_ofdm_cfosho_a ;
 666
 667                 if (p_dm_odm->support_ic_type & (ODM_RTL8703B)) {
 668
 669 #if (RTL8703B_SUPPORT == 1)
 670                         if (p_dm_odm->cck_agc_report_type == 1) {  /*4 bit LNA*/
 671
 672                                 u8 cck_agc_rpt_b = (p_phy_sta_rpt->cck_rpt_b_ofdm_cfosho_b & BIT(7)) ? 1 : 0;
 673
 674                                 LNA_idx = (cck_agc_rpt_b << 3) | ((cck_agc_rpt & 0xE0) >> 5);
 675                                 VGA_idx = (cck_agc_rpt & 0x1F);
 676
 677                                 rx_pwr_all = odm_CCKRSSI_8703B(LNA_idx, VGA_idx);
 678                         }
 679 #endif
 680                 } else { /*3 bit LNA*/
 681
 682                         LNA_idx = ((cck_agc_rpt & 0xE0) >> 5);
 683                         VGA_idx = (cck_agc_rpt & 0x1F);
 684
 685                         if (p_dm_odm->support_ic_type & (ODM_RTL8188E)) {
 686
 687 #if (RTL8188E_SUPPORT == 1)
 688                                 rx_pwr_all = odm_CCKRSSI_8188E(p_dm_odm, LNA_idx, VGA_idx);
 689                                 /**/
 690 #endif
 691                         }
 692 #if (RTL8192E_SUPPORT == 1)
 693                         else if (p_dm_odm->support_ic_type & (ODM_RTL8192E)) {
 694
 695                                 rx_pwr_all = odm_CCKRSSI_8192E(p_dm_odm, LNA_idx, VGA_idx);
 696                                 /**/
 697                         }
 698 #endif
 699 #if (RTL8723B_SUPPORT == 1)
 700                         else if (p_dm_odm->support_ic_type & (ODM_RTL8723B)) {
 701
 702                                 rx_pwr_all = odm_CCKRSSI_8723B(LNA_idx, VGA_idx);
 703                                 /**/
 704                         }
 705 #endif
 706 #if (RTL8188F_SUPPORT == 1)
 707                         else if (p_dm_odm->support_ic_type & (ODM_RTL8188F)) {
 708
 709                                 rx_pwr_all = odm_CCKRSSI_8188F(LNA_idx, VGA_idx);
 710                                 /**/
 711                         }
 712 #endif
 713 #if (RTL8195A_SUPPORT == 1)
 714                         else if (p_dm_odm->support_ic_type & (ODM_RTL8195A)) {
 715
 716                                 rx_pwr_all = odm_CCKRSSI_8195A(LNA_idx, VGA_idx);
 717                                 /**/
 718                         }
 719 #endif
 720                 }
 721
 722                 ODM_RT_TRACE(p_dm_odm, ODM_COMP_RSSI_MONITOR, ODM_DBG_LOUD, ("ext_lna_gain (( %d )), LNA_idx: (( 0x%x )), VGA_idx: (( 0x%x )), rx_pwr_all: (( %d ))\n",
 723                         p_dm_odm->ext_lna_gain, LNA_idx, VGA_idx, rx_pwr_all));
 724
 725                 if (p_dm_odm->board_type & ODM_BOARD_EXT_LNA)
 726                         rx_pwr_all -= p_dm_odm->ext_lna_gain;
 727
 728                 PWDB_ALL = odm_query_rx_pwr_percentage(rx_pwr_all);
 729
 730                 if (p_pktinfo->is_to_self) {
 731                         p_dm_odm->cck_lna_idx = LNA_idx;
 732                         p_dm_odm->cck_vga_idx = VGA_idx;
 733                 }
 734                 p_phy_info->rx_pwdb_all = PWDB_ALL;
 735
 736 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
 737                 p_phy_info->bt_rx_rssi_percentage = PWDB_ALL;
 738                 p_phy_info->recv_signal_power = rx_pwr_all;
 739 #endif
 740                 /*  */
 741                 /* (3) Get Signal Quality (EVM) */
 742                 /*  */
 743                 /* if(p_pktinfo->is_packet_match_bssid) */
 744                 {
 745                         u8      SQ, SQ_rpt;
 746
 747 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
 748                         if ((p_dm_odm->support_platform == ODM_WIN) &&
 749                             (p_dm_odm->patch_id == RT_CID_819X_LENOVO))
 750                                 SQ = odm_sq_process_patch_rt_cid_819x_lenovo(p_dm_odm, is_cck_rate, PWDB_ALL, 0, 0);
 751                         else if ((p_dm_odm->support_platform == ODM_WIN) &&
 752                                  (p_dm_odm->patch_id == RT_CID_819X_ACER))
 753                                 SQ = odm_sq_process_patch_rt_cid_819x_acer(p_dm_odm, is_cck_rate, PWDB_ALL, 0, 0);
 754                         else
 755 #endif
 756                                 if (p_phy_info->rx_pwdb_all > 40 && !p_dm_odm->is_in_hct_test)
 757                                         SQ = 100;
 758                                 else {
 759                                         SQ_rpt = p_phy_sta_rpt->cck_sig_qual_ofdm_pwdb_all;
 760
 761                                         if (SQ_rpt > 64)
 762                                                 SQ = 0;
 763                                         else if (SQ_rpt < 20)
 764                                                 SQ = 100;
 765                                         else
 766                                                 SQ = ((64 - SQ_rpt) * 100) / 44;
 767
 768                                 }
 769
 770                         /* dbg_print("cck SQ = %d\n", SQ); */
 771                         p_phy_info->signal_quality = SQ;
 772                         p_phy_info->rx_mimo_signal_quality[ODM_RF_PATH_A] = SQ;
 773                         p_phy_info->rx_mimo_signal_quality[ODM_RF_PATH_B] = -1;
 774                 }
 775
 776                 for (i = ODM_RF_PATH_A; i < ODM_RF_PATH_MAX; i++) {
 777                         if (i == 0)
 778                                 p_phy_info->rx_mimo_signal_strength[0] = PWDB_ALL;
 779                         else
 780                                 p_phy_info->rx_mimo_signal_strength[1] = 0;
 781                 }
 782         } else { /* 2 is OFDM rate */
 783                 p_dm_odm->phy_dbg_info.num_qry_phy_status_ofdm++;
 784
 785                 /*  */
 786                 /* (1)Get RSSI for HT rate */
 787                 /*  */
 788
 789                 for (i = ODM_RF_PATH_A; i < ODM_RF_PATH_MAX; i++) {
 790                         /* 2008/01/30 MH we will judge RF RX path now. */
 791                         if (p_dm_odm->rf_path_rx_enable & BIT(i))
 792                                 rf_rx_num++;
 793                         /* else */
 794                         /* continue; */
 795
 796                         rx_pwr[i] = ((p_phy_sta_rpt->path_agc[i].gain & 0x3F) * 2) - 110;
 797
 798                         if (p_pktinfo->is_to_self) {
 799                                 p_dm_odm->ofdm_agc_idx[i] = (p_phy_sta_rpt->path_agc[i].gain & 0x3F);
 800                                 /**/
 801                         }
 802
 803 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
 804                         p_phy_info->rx_pwr[i] = rx_pwr[i];
 805 #endif
 806
 807                         /* Translate DBM to percentage. */
 808                         RSSI = odm_query_rx_pwr_percentage(rx_pwr[i]);
 809                         total_rssi += RSSI;
 810                         /* RT_DISP(FRX, RX_PHY_SS, ("RF-%d RXPWR=%x RSSI=%d\n", i, rx_pwr[i], RSSI)); */
 811
 812                         p_phy_info->rx_mimo_signal_strength[i] = (u8) RSSI;
 813
 814 #if (DM_ODM_SUPPORT_TYPE &  (/*ODM_WIN|*/ODM_CE|ODM_AP))
 815                         /* Get Rx snr value in DB */
 816                         p_phy_info->rx_snr[i] = p_dm_odm->phy_dbg_info.rx_snr_db[i] = (s32)(p_phy_sta_rpt->path_rxsnr[i] / 2);
 817 #endif
 818
 819                         /* Record Signal Strength for next packet */
 820                         /* if(p_pktinfo->is_packet_match_bssid) */
 821                         {
 822 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
 823                                 if ((p_dm_odm->support_platform == ODM_WIN) &&
 824                                     (p_dm_odm->patch_id == RT_CID_819X_LENOVO)) {
 825                                         if (i == ODM_RF_PATH_A)
 826                                                 p_phy_info->signal_quality = odm_sq_process_patch_rt_cid_819x_lenovo(p_dm_odm, is_cck_rate, PWDB_ALL, i, RSSI);
 827
 828                                 } else if ((p_dm_odm->support_platform == ODM_WIN) &&
 829                                         (p_dm_odm->patch_id == RT_CID_819X_ACER))
 830                                         p_phy_info->signal_quality = odm_sq_process_patch_rt_cid_819x_acer(p_dm_odm, is_cck_rate, PWDB_ALL, 0, RSSI);
 831 #endif
 832                         }
 833                 }
 834
 835
 836                 /*  */
 837                 /* (2)PWDB, Average PWDB cacluated by hardware (for rate adaptive) */
 838                 /*  */
 839                 rx_pwr_all = (((p_phy_sta_rpt->cck_sig_qual_ofdm_pwdb_all) >> 1) & 0x7f) - 110;
 840
 841                 PWDB_ALL_BT = PWDB_ALL = odm_query_rx_pwr_percentage(rx_pwr_all);
 842
 843
 844                 p_phy_info->rx_pwdb_all = PWDB_ALL;
 845                 /* ODM_RT_TRACE(p_dm_odm,ODM_COMP_RSSI_MONITOR, ODM_DBG_LOUD, ("ODM OFDM RSSI=%d\n",p_phy_info->rx_pwdb_all)); */
 846 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
 847                 p_phy_info->bt_rx_rssi_percentage = PWDB_ALL_BT;
 848                 p_phy_info->rx_power = rx_pwr_all;
 849                 p_phy_info->recv_signal_power = rx_pwr_all;
 850 #endif
 851
 852                 if ((p_dm_odm->support_platform == ODM_WIN) && (p_dm_odm->patch_id == 19)) {
 853                         /* do nothing */
 854                 } else if ((p_dm_odm->support_platform == ODM_WIN) && (p_dm_odm->patch_id == 25)) {
 855                         /* do nothing */
 856                 } else { /* p_mgnt_info->customer_id != RT_CID_819X_LENOVO */
 857                         /*  */
 858                         /* (3)EVM of HT rate */
 859                         /*  */
 860                         if (p_pktinfo->data_rate >= ODM_RATEMCS8 && p_pktinfo->data_rate <= ODM_RATEMCS15)
 861                                 max_spatial_stream = 2; /* both spatial stream make sense */
 862                         else
 863                                 max_spatial_stream = 1; /* only spatial stream 1 makes sense */
 864
 865                         for (i = 0; i < max_spatial_stream; i++) {
 866                                 /* Do not use shift operation like "rx_evmX >>= 1" because the compilor of free build environment */
 867                                 /* fill most significant bit to "zero" when doing shifting operation which may change a negative */
 868                                 /* value to positive one, then the dbm value (which is supposed to be negative)  is not correct anymore. */
 869                                 EVM = odm_evm_db_to_percentage((p_phy_sta_rpt->stream_rxevm[i]));       /* dbm */
 870
 871                                 /* GET_RX_STATUS_DESC_RX_MCS(p_desc), p_drv_info->rxevm[i], "%", EVM)); */
 872
 873                                 /* if(p_pktinfo->is_packet_match_bssid) */
 874                                 {
 875                                         if (i == ODM_RF_PATH_A) /* Fill value in RFD, Get the first spatial stream only */
 876                                                 p_phy_info->signal_quality = (u8)(EVM & 0xff);
 877                                         p_phy_info->rx_mimo_signal_quality[i] = (u8)(EVM & 0xff);
 878                                 }
 879                         }
 880                 }
 881
 882                 num_ss = phydm_rate_to_num_ss(p_dm_odm, p_pktinfo->data_rate);
 883                 odm_parsing_cfo(p_dm_odm, p_pktinfo, p_phy_sta_rpt->path_cfotail, num_ss);
 884
 885         }
 886 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
 887         /* UI BSS List signal strength(in percentage), make it good looking, from 0~100. */
 888         /* It is assigned to the BSS List in GetValueFromBeaconOrProbeRsp(). */
 889         if (is_cck_rate) {
 890 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
 891                 /* 2012/01/12 MH Use customeris signal strength from HalComRxdDesc.c/ */
 892                 p_phy_info->signal_strength = SignalScaleProc(p_dm_odm->adapter, PWDB_ALL, true, true);
 893 #else
 894                 p_phy_info->signal_strength = (u8)(odm_signal_scale_mapping(p_dm_odm, PWDB_ALL));/*PWDB_ALL;*/
 895 #endif /*#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)*/
 896         } else {
 897                 if (rf_rx_num != 0) {
 898 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
 899                         /* 2012/01/12 MH Use customeris signal strength from HalComRxdDesc.c/ */
 900                         p_phy_info->signal_strength = SignalScaleProc(p_dm_odm->adapter, (total_rssi /= rf_rx_num), true, false);
 901 #else
 902                         p_phy_info->signal_strength = (u8)(odm_signal_scale_mapping(p_dm_odm, total_rssi /= rf_rx_num));
 903 #endif
 904                 }
 905         }
 906 #endif /*#if (DM_ODM_SUPPORT_TYPE &  (ODM_WIN|ODM_CE))*/
 907
 908         /* dbg_print("is_cck_rate = %d, p_phy_info->rx_pwdb_all = %d, p_phy_sta_rpt->cck_agc_rpt_ofdm_cfosho_a = 0x%x\n", */
 909         /* is_cck_rate, p_phy_info->rx_pwdb_all, p_phy_sta_rpt->cck_agc_rpt_ofdm_cfosho_a); */
 910
 911         /* For 92C/92D HW (Hybrid) Antenna Diversity */
 912 #if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY))
 913         /* For 88E HW Antenna Diversity */
 914         p_dm_odm->dm_fat_table.antsel_rx_keep_0 = p_phy_sta_rpt->ant_sel;
 915         p_dm_odm->dm_fat_table.antsel_rx_keep_1 = p_phy_sta_rpt->ant_sel_b;
 916         p_dm_odm->dm_fat_table.antsel_rx_keep_2 = p_phy_sta_rpt->antsel_rx_keep_2;
 917 #endif
 918 }
 919 #endif
 920
 921 #if     ODM_IC_11AC_SERIES_SUPPORT
 922
 923 void
 924 odm_rx_phy_bw_jaguar_series_parsing(
 925         struct _odm_phy_status_info_                    *p_phy_info,
 926         struct _odm_per_pkt_info_                       *p_pktinfo,
 927         struct _phy_status_rpt_8812             *p_phy_sta_rpt
 928 )
 929 {
 930
 931         if (p_pktinfo->data_rate <= ODM_RATE54M) {
 932                 switch (p_phy_sta_rpt->r_RFMOD) {
 933                 case 1:
 934                         if (p_phy_sta_rpt->sub_chnl == 0)
 935                                 p_phy_info->band_width = 1;
 936                         else
 937                                 p_phy_info->band_width = 0;
 938                         break;
 939
 940                 case 2:
 941                         if (p_phy_sta_rpt->sub_chnl == 0)
 942                                 p_phy_info->band_width = 2;
 943                         else if (p_phy_sta_rpt->sub_chnl == 9 || p_phy_sta_rpt->sub_chnl == 10)
 944                                 p_phy_info->band_width = 1;
 945                         else
 946                                 p_phy_info->band_width = 0;
 947                         break;
 948
 949                 default:
 950                 case 0:
 951                         p_phy_info->band_width = 0;
 952                         break;
 953                 }
 954         }
 955
 956 }
 957
 958 void
 959 odm_rx_phy_status_jaguar_series_parsing(
 960         struct PHY_DM_STRUCT                                    *p_dm_odm,
 961         struct _odm_phy_status_info_                    *p_phy_info,
 962         u8                                              *p_phy_status,
 963         struct _odm_per_pkt_info_                       *p_pktinfo
 964 )
 965 {
 966         u8                                      i, max_spatial_stream;
 967         s8                                      rx_pwr[4], rx_pwr_all = 0;
 968         u8                                      EVM, evm_dbm, PWDB_ALL = 0, PWDB_ALL_BT;
 969         u8                                      RSSI, avg_rssi = 0, best_rssi = 0, second_rssi = 0;
 970         u8                                      is_cck_rate = 0;
 971         u8                                      rf_rx_num = 0;
 972         u8                                      cck_highpwr = 0;
 973         u8                                      LNA_idx, VGA_idx;
 974         struct _phy_status_rpt_8812 *p_phy_sta_rpt = (struct _phy_status_rpt_8812 *)p_phy_status;
 975         struct _FAST_ANTENNA_TRAINNING_                                 *p_dm_fat_table = &p_dm_odm->dm_fat_table;
 976         u8                                      num_ss;
 977
 978         odm_rx_phy_bw_jaguar_series_parsing(p_phy_info, p_pktinfo, p_phy_sta_rpt);
 979
 980         if (p_pktinfo->data_rate <= ODM_RATE11M)
 981                 is_cck_rate = true;
 982         else
 983                 is_cck_rate = false;
 984
 985         if (p_pktinfo->is_to_self)
 986                 p_dm_odm->curr_station_id = p_pktinfo->station_id;
 987         else
 988                 p_dm_odm->curr_station_id = 0xff;
 989
 990         p_phy_info->rx_mimo_signal_quality[ODM_RF_PATH_A] = -1;
 991         p_phy_info->rx_mimo_signal_quality[ODM_RF_PATH_B] = -1;
 992         p_phy_info->rx_mimo_signal_quality[ODM_RF_PATH_C] = -1;
 993         p_phy_info->rx_mimo_signal_quality[ODM_RF_PATH_D] = -1;
 994
 995         if (is_cck_rate) {
 996                 u8 cck_agc_rpt;
 997                 p_dm_odm->phy_dbg_info.num_qry_phy_status_cck++;
 998
 999                 /*(1)Hardware does not provide RSSI for CCK*/
1000                 /*(2)PWDB, Average PWDB calculated by hardware (for rate adaptive)*/
1001
1002                 /*if(p_hal_data->e_rf_power_state == e_rf_on)*/
1003                 cck_highpwr = p_dm_odm->is_cck_high_power;
1004                 /*else*/
1005                 /*cck_highpwr = false;*/
1006
1007                 cck_agc_rpt =  p_phy_sta_rpt->cfosho[0] ;
1008                 LNA_idx = ((cck_agc_rpt & 0xE0) >> 5);
1009                 VGA_idx = (cck_agc_rpt & 0x1F);
1010
1011                 if (p_dm_odm->support_ic_type == ODM_RTL8812) {
1012                         switch (LNA_idx) {
1013                         case 7:
1014                                 if (VGA_idx <= 27)
1015                                         rx_pwr_all = -100 + 2 * (27 - VGA_idx); /*VGA_idx = 27~2*/
1016                                 else
1017                                         rx_pwr_all = -100;
1018                                 break;
1019                         case 6:
1020                                 rx_pwr_all = -48 + 2 * (2 - VGA_idx); /*VGA_idx = 2~0*/
1021                                 break;
1022                         case 5:
1023                                 rx_pwr_all = -42 + 2 * (7 - VGA_idx); /*VGA_idx = 7~5*/
1024                                 break;
1025                         case 4:
1026                                 rx_pwr_all = -36 + 2 * (7 - VGA_idx); /*VGA_idx = 7~4*/
1027                                 break;
1028                         case 3:
1029                                 /*rx_pwr_all = -28 + 2*(7-VGA_idx); VGA_idx = 7~0*/
1030                                 rx_pwr_all = -24 + 2 * (7 - VGA_idx); /*VGA_idx = 7~0*/
1031                                 break;
1032                         case 2:
1033                                 if (cck_highpwr)
1034                                         rx_pwr_all = -12 + 2 * (5 - VGA_idx); /*VGA_idx = 5~0*/
1035                                 else
1036                                         rx_pwr_all = -6 + 2 * (5 - VGA_idx);
1037                                 break;
1038                         case 1:
1039                                 rx_pwr_all = 8 - 2 * VGA_idx;
1040                                 break;
1041                         case 0:
1042                                 rx_pwr_all = 14 - 2 * VGA_idx;
1043                                 break;
1044                         default:
1045                                 /*dbg_print("CCK Exception default\n");*/
1046                                 break;
1047                         }
1048                         rx_pwr_all += 6;
1049                         PWDB_ALL = odm_query_rx_pwr_percentage(rx_pwr_all);
1050
1051                         if (cck_highpwr == false) {
1052                                 if (PWDB_ALL >= 80)
1053                                         PWDB_ALL = ((PWDB_ALL - 80) << 1) + ((PWDB_ALL - 80) >> 1) + 80;
1054                                 else if ((PWDB_ALL <= 78) && (PWDB_ALL >= 20))
1055                                         PWDB_ALL += 3;
1056                                 if (PWDB_ALL > 100)
1057                                         PWDB_ALL = 100;
1058                         }
1059                 } else if (p_dm_odm->support_ic_type & (ODM_RTL8821 | ODM_RTL8881A)) {
1060                         s8 pout = -6;
1061
1062                         switch (LNA_idx) {
1063                         case 5:
1064                                 rx_pwr_all = pout - 32 - (2 * VGA_idx);
1065                                 break;
1066                         case 4:
1067                                 rx_pwr_all = pout - 24 - (2 * VGA_idx);
1068                                 break;
1069                         case 2:
1070                                 rx_pwr_all = pout - 11 - (2 * VGA_idx);
1071                                 break;
1072                         case 1:
1073                                 rx_pwr_all = pout + 5 - (2 * VGA_idx);
1074                                 break;
1075                         case 0:
1076                                 rx_pwr_all = pout + 21 - (2 * VGA_idx);
1077                                 break;
1078                         }
1079                         PWDB_ALL = odm_query_rx_pwr_percentage(rx_pwr_all);
1080                 } else if (p_dm_odm->support_ic_type == ODM_RTL8814A || p_dm_odm->support_ic_type == ODM_RTL8822B) {
1081                         s8 pout = -6;
1082
1083                         switch (LNA_idx) {
1084                         /*CCK only use LNA: 2, 3, 5, 7*/
1085                         case 7:
1086                                 rx_pwr_all = pout - 32 - (2 * VGA_idx);
1087                                 break;
1088                         case 5:
1089                                 rx_pwr_all = pout - 22 - (2 * VGA_idx);
1090                                 break;
1091                         case 3:
1092                                 rx_pwr_all = pout - 2 - (2 * VGA_idx);
1093                                 break;
1094                         case 2:
1095                                 rx_pwr_all = pout + 5 - (2 * VGA_idx);
1096                                 break;
1097                         /*case 6:*/
1098                         /*rx_pwr_all = pout -26 - (2*VGA_idx);*/
1099                         /*break;*/
1100                         /*case 4:*/
1101                         /*rx_pwr_all = pout - 8 - (2*VGA_idx);*/
1102                         /*break;*/
1103                         /*case 1:*/
1104                         /*rx_pwr_all = pout + 21 - (2*VGA_idx);*/
1105                         /*break;*/
1106                         /*case 0:*/
1107                         /*rx_pwr_all = pout + 10 - (2*VGA_idx);*/
1108                         /*      break; */
1109                         default:
1110                                 /* dbg_print("CCK Exception default\n"); */
1111                                 break;
1112                         }
1113                         PWDB_ALL = odm_query_rx_pwr_percentage(rx_pwr_all);
1114                 }
1115
1116                 p_dm_odm->cck_lna_idx = LNA_idx;
1117                 p_dm_odm->cck_vga_idx = VGA_idx;
1118                 p_phy_info->rx_pwdb_all = PWDB_ALL;
1119                 /* if(p_pktinfo->station_id == 0) */
1120                 /* { */
1121                 /*      dbg_print("CCK: LNA_idx = %d, VGA_idx = %d, p_phy_info->rx_pwdb_all = %d\n", */
1122                 /*              LNA_idx, VGA_idx, p_phy_info->rx_pwdb_all); */
1123                 /* } */
1124 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
1125                 p_phy_info->bt_rx_rssi_percentage = PWDB_ALL;
1126                 p_phy_info->recv_signal_power = rx_pwr_all;
1127 #endif
1128                 /*(3) Get Signal Quality (EVM)*/
1129                 /*if (p_pktinfo->is_packet_match_bssid)*/
1130                 {
1131                         u8      SQ, SQ_rpt;
1132
1133                         if ((p_dm_odm->support_platform == ODM_WIN) &&
1134                             (p_dm_odm->patch_id == RT_CID_819X_LENOVO))
1135                                 SQ = odm_sq_process_patch_rt_cid_819x_lenovo(p_dm_odm, is_cck_rate, PWDB_ALL, 0, 0);
1136                         else if (p_phy_info->rx_pwdb_all > 40 && !p_dm_odm->is_in_hct_test)
1137                                 SQ = 100;
1138                         else {
1139                                 SQ_rpt = p_phy_sta_rpt->pwdb_all;
1140
1141                                 if (SQ_rpt > 64)
1142                                         SQ = 0;
1143                                 else if (SQ_rpt < 20)
1144                                         SQ = 100;
1145                                 else
1146                                         SQ = ((64 - SQ_rpt) * 100) / 44;
1147                         }
1148
1149                         /* dbg_print("cck SQ = %d\n", SQ); */
1150                         p_phy_info->signal_quality = SQ;
1151                         p_phy_info->rx_mimo_signal_quality[ODM_RF_PATH_A] = SQ;
1152                 }
1153
1154                 for (i = ODM_RF_PATH_A; i < ODM_RF_PATH_MAX_JAGUAR; i++) {
1155                         if (i == 0)
1156                                 p_phy_info->rx_mimo_signal_strength[0] = PWDB_ALL;
1157                         else
1158                                 p_phy_info->rx_mimo_signal_strength[i] = 0;
1159                 }
1160         } else {
1161                 /*is OFDM rate*/
1162                 p_dm_fat_table->hw_antsw_occur = p_phy_sta_rpt->hw_antsw_occur;
1163
1164                 p_dm_odm->phy_dbg_info.num_qry_phy_status_ofdm++;
1165
1166                 /*(1)Get RSSI for OFDM rate*/
1167
1168                 for (i = ODM_RF_PATH_A; i < ODM_RF_PATH_MAX_JAGUAR; i++) {
1169                         /*2008/01/30 MH we will judge RF RX path now.*/
1170                         /* dbg_print("p_dm_odm->rf_path_rx_enable = %x\n", p_dm_odm->rf_path_rx_enable); */
1171                         if (p_dm_odm->rf_path_rx_enable & BIT(i))
1172                                 rf_rx_num++;
1173                         /* else */
1174                         /* continue; */
1175                         /*2012.05.25 LukeLee: Testchip AGC report is wrong, it should be restored back to old formula in MP chip*/
1176                         /* if((p_dm_odm->support_ic_type & (ODM_RTL8812|ODM_RTL8821)) && (!p_dm_odm->is_mp_chip)) */
1177                         if (i < ODM_RF_PATH_C)
1178                                 rx_pwr[i] = (p_phy_sta_rpt->gain_trsw[i] & 0x7F) - 110;
1179                         else
1180                                 rx_pwr[i] = (p_phy_sta_rpt->gain_trsw_cd[i - 2] & 0x7F) - 110;
1181                         /* else */
1182                         /*rx_pwr[i] = ((p_phy_sta_rpt->gain_trsw[i]& 0x3F)*2) - 110;  OLD FORMULA*/
1183
1184 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
1185                         p_phy_info->rx_pwr[i] = rx_pwr[i];
1186 #endif
1187
1188                         /* Translate DBM to percentage. */
1189                         RSSI = odm_query_rx_pwr_percentage(rx_pwr[i]);
1190
1191                         /*total_rssi += RSSI;*/
1192                         /*Get the best two RSSI*/
1193                         if (RSSI > best_rssi && RSSI > second_rssi) {
1194                                 second_rssi = best_rssi;
1195                                 best_rssi = RSSI;
1196                         } else if (RSSI > second_rssi && RSSI <= best_rssi)
1197                                 second_rssi = RSSI;
1198
1199                         /*RT_DISP(FRX, RX_PHY_SS, ("RF-%d RXPWR=%x RSSI=%d\n", i, rx_pwr[i], RSSI));*/
1200
1201                         p_phy_info->rx_mimo_signal_strength[i] = (u8) RSSI;
1202
1203
1204                         /*Get Rx snr value in DB*/
1205                         if (i < ODM_RF_PATH_C)
1206                                 p_phy_info->rx_snr[i] = p_dm_odm->phy_dbg_info.rx_snr_db[i] = p_phy_sta_rpt->rxsnr[i] / 2;
1207                         else if (p_dm_odm->support_ic_type & (ODM_RTL8814A | ODM_RTL8822B))
1208                                 p_phy_info->rx_snr[i] = p_dm_odm->phy_dbg_info.rx_snr_db[i] = p_phy_sta_rpt->csi_current[i - 2] / 2;
1209
1210 #if (DM_ODM_SUPPORT_TYPE != ODM_AP)
1211                         /*(2) CFO_short  & CFO_tail*/
1212                         if (i < ODM_RF_PATH_C) {
1213                                 p_phy_info->cfo_short[i] = odm_cfo((p_phy_sta_rpt->cfosho[i]));
1214                                 p_phy_info->cfo_tail[i] = odm_cfo((p_phy_sta_rpt->cfotail[i]));
1215                         }
1216 #endif
1217                         /* Record Signal Strength for next packet */
1218                         if (p_pktinfo->is_packet_match_bssid) {
1219 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
1220                                 if ((p_dm_odm->support_platform == ODM_WIN) &&
1221                                     (p_dm_odm->patch_id == RT_CID_819X_LENOVO)) {
1222                                         if (i == ODM_RF_PATH_A)
1223                                                 p_phy_info->signal_quality = odm_sq_process_patch_rt_cid_819x_lenovo(p_dm_odm, is_cck_rate, PWDB_ALL, i, RSSI);
1224
1225                                 }
1226 #endif
1227                         }
1228                 }
1229
1230                 /*(3)PWDB, Average PWDB calculated by hardware (for rate adaptive)*/
1231
1232                 /*2012.05.25 LukeLee: Testchip AGC report is wrong, it should be restored back to old formula in MP chip*/
1233                 if ((p_dm_odm->support_ic_type & (ODM_RTL8812 | ODM_RTL8821 | ODM_RTL8881A)) && (!p_dm_odm->is_mp_chip))
1234                         rx_pwr_all = (p_phy_sta_rpt->pwdb_all & 0x7f) - 110;
1235                 else
1236                         rx_pwr_all = (((p_phy_sta_rpt->pwdb_all) >> 1) & 0x7f) - 110;    /*OLD FORMULA*/
1237
1238                 PWDB_ALL_BT = PWDB_ALL = odm_query_rx_pwr_percentage(rx_pwr_all);
1239
1240                 p_phy_info->rx_pwdb_all = PWDB_ALL;
1241                 /*ODM_RT_TRACE(p_dm_odm,ODM_COMP_RSSI_MONITOR, ODM_DBG_LOUD, ("ODM OFDM RSSI=%d\n",p_phy_info->rx_pwdb_all));*/
1242 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
1243                 p_phy_info->bt_rx_rssi_percentage = PWDB_ALL_BT;
1244                 p_phy_info->rx_power = rx_pwr_all;
1245                 p_phy_info->recv_signal_power = rx_pwr_all;
1246 #endif
1247
1248                 if ((p_dm_odm->support_platform == ODM_WIN) && (p_dm_odm->patch_id == 19)) {
1249                         /*do nothing*/
1250                 } else {
1251                         /*p_mgnt_info->customer_id != RT_CID_819X_LENOVO*/
1252
1253                         /*(4)EVM of OFDM rate*/
1254
1255                         if ((p_pktinfo->data_rate >= ODM_RATEMCS8) &&
1256                             (p_pktinfo->data_rate <= ODM_RATEMCS15))
1257                                 max_spatial_stream = 2;
1258                         else if ((p_pktinfo->data_rate >= ODM_RATEVHTSS2MCS0) &&
1259                                  (p_pktinfo->data_rate <= ODM_RATEVHTSS2MCS9))
1260                                 max_spatial_stream = 2;
1261                         else if ((p_pktinfo->data_rate >= ODM_RATEMCS16) &&
1262                                  (p_pktinfo->data_rate <= ODM_RATEMCS23))
1263                                 max_spatial_stream = 3;
1264                         else if ((p_pktinfo->data_rate >= ODM_RATEVHTSS3MCS0) &&
1265                                  (p_pktinfo->data_rate <= ODM_RATEVHTSS3MCS9))
1266                                 max_spatial_stream = 3;
1267                         else
1268                                 max_spatial_stream = 1;
1269
1270                         /*if (p_pktinfo->is_packet_match_bssid) */
1271                         {
1272                                 /*dbg_print("p_pktinfo->data_rate = %d\n", p_pktinfo->data_rate);*/
1273
1274                                 for (i = 0; i < max_spatial_stream; i++) {
1275                                         /*Do not use shift operation like "rx_evmX >>= 1" because the compilor of free build environment*/
1276                                         /*fill most significant bit to "zero" when doing shifting operation which may change a negative*/
1277                                         /*value to positive one, then the dbm value (which is supposed to be negative)  is not correct anymore.*/
1278
1279                                         if (p_pktinfo->data_rate >= ODM_RATE6M && p_pktinfo->data_rate <= ODM_RATE54M) {
1280                                                 if (i == ODM_RF_PATH_A) {
1281                                                         EVM = odm_evm_db_to_percentage((p_phy_sta_rpt->sigevm));        /*dbm*/
1282                                                         EVM += 20;
1283                                                         if (EVM > 100)
1284                                                                 EVM = 100;
1285                                                 }
1286                                         } else {
1287                                                 if (i < ODM_RF_PATH_C) {
1288                                                         if (p_phy_sta_rpt->rxevm[i] == -128)
1289                                                                 p_phy_sta_rpt->rxevm[i] = -25;
1290                                                         EVM = odm_evm_db_to_percentage((p_phy_sta_rpt->rxevm[i]));      /*dbm*/
1291                                                 } else {
1292                                                         if (p_phy_sta_rpt->rxevm_cd[i - 2] == -128)
1293                                                                 p_phy_sta_rpt->rxevm_cd[i - 2] = -25;
1294                                                         EVM = odm_evm_db_to_percentage((p_phy_sta_rpt->rxevm_cd[i - 2]));       /*dbm*/
1295                                                 }
1296                                         }
1297
1298                                         if (i < ODM_RF_PATH_C)
1299                                                 evm_dbm = odm_evm_dbm_jaguar_series(p_phy_sta_rpt->rxevm[i]);
1300                                         else
1301                                                 evm_dbm = odm_evm_dbm_jaguar_series(p_phy_sta_rpt->rxevm_cd[i - 2]);
1302                                         /*RT_DISP(FRX, RX_PHY_SQ, ("RXRATE=%x RXEVM=%x EVM=%s%d\n",*/
1303                                         /*p_pktinfo->data_rate, p_phy_sta_rpt->rxevm[i], "%", EVM));*/
1304
1305                                         {
1306                                                 if (i == ODM_RF_PATH_A) {
1307                                                         /*Fill value in RFD, Get the first spatial stream only*/
1308                                                         p_phy_info->signal_quality = EVM;
1309                                                 }
1310                                                 p_phy_info->rx_mimo_signal_quality[i] = EVM;
1311 #if (DM_ODM_SUPPORT_TYPE != ODM_AP)
1312                                                 p_phy_info->rx_mimo_evm_dbm[i] = evm_dbm;
1313 #endif
1314                                         }
1315                                 }
1316                         }
1317                 }
1318
1319                 num_ss = phydm_rate_to_num_ss(p_dm_odm, p_pktinfo->data_rate);
1320                 odm_parsing_cfo(p_dm_odm, p_pktinfo, p_phy_sta_rpt->cfotail, num_ss);
1321
1322         }
1323         /* dbg_print("is_cck_rate= %d, p_phy_info->signal_strength=%d % PWDB_AL=%d rf_rx_num=%d\n", is_cck_rate, p_phy_info->signal_strength, PWDB_ALL, rf_rx_num); */
1324
1325 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
1326         /*UI BSS List signal strength(in percentage), make it good looking, from 0~100.*/
1327         /*It is assigned to the BSS List in GetValueFromBeaconOrProbeRsp().*/
1328         if (is_cck_rate) {
1329 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
1330                 /*2012/01/12 MH Use customeris signal strength from HalComRxdDesc.c/*/
1331                 p_phy_info->signal_strength = SignalScaleProc(p_dm_odm->adapter, PWDB_ALL, false, true);
1332 #else
1333                 p_phy_info->signal_strength = (u8)(odm_signal_scale_mapping(p_dm_odm, PWDB_ALL));/*PWDB_ALL;*/
1334 #endif
1335         } else {
1336                 if (rf_rx_num != 0) {
1337                         /* 2015/01 Sean, use the best two RSSI only, suggested by Ynlin and ChenYu.*/
1338                         if (rf_rx_num == 1)
1339                                 avg_rssi = best_rssi;
1340                         else
1341                                 avg_rssi = (best_rssi + second_rssi) / 2;
1342 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
1343                         /* 2012/01/12 MH Use customeris signal strength from HalComRxdDesc.c/*/
1344                         p_phy_info->signal_strength = SignalScaleProc(p_dm_odm->adapter, avg_rssi, false, false);
1345 #else
1346                         p_phy_info->signal_strength = (u8)(odm_signal_scale_mapping(p_dm_odm, avg_rssi));
1347 #endif
1348                 }
1349         }
1350 #endif
1351         p_dm_odm->rx_pwdb_ave = p_dm_odm->rx_pwdb_ave + p_phy_info->rx_pwdb_all;
1352
1353         p_dm_odm->dm_fat_table.antsel_rx_keep_0 = p_phy_sta_rpt->antidx_anta;
1354         p_dm_odm->dm_fat_table.antsel_rx_keep_1 = p_phy_sta_rpt->antidx_antb;
1355         p_dm_odm->dm_fat_table.antsel_rx_keep_2 = p_phy_sta_rpt->antidx_antc;
1356         p_dm_odm->dm_fat_table.antsel_rx_keep_3 = p_phy_sta_rpt->antidx_antd;
1357         /*ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("StaID[%d]:  antidx_anta = ((%d)), MatchBSSID =  ((%d))\n", p_pktinfo->station_id, p_phy_sta_rpt->antidx_anta, p_pktinfo->is_packet_match_bssid));*/
1358
1359
1360         /*              dbg_print("p_phy_sta_rpt->antidx_anta = %d, p_phy_sta_rpt->antidx_antb = %d\n",*/
1361         /*                      p_phy_sta_rpt->antidx_anta, p_phy_sta_rpt->antidx_antb);*/
1362         /*              dbg_print("----------------------------\n");*/
1363         /*              dbg_print("p_pktinfo->station_id=%d, p_pktinfo->data_rate=0x%x\n",p_pktinfo->station_id, p_pktinfo->data_rate);*/
1364         /*              dbg_print("p_phy_sta_rpt->r_RFMOD = %d\n", p_phy_sta_rpt->r_RFMOD);*/
1365         /*              dbg_print("p_phy_sta_rpt->gain_trsw[0]=0x%x, p_phy_sta_rpt->gain_trsw[1]=0x%x\n",*/
1366         /*                              p_phy_sta_rpt->gain_trsw[0],p_phy_sta_rpt->gain_trsw[1]);*/
1367         /*              dbg_print("p_phy_sta_rpt->gain_trsw[2]=0x%x, p_phy_sta_rpt->gain_trsw[3]=0x%x\n",*/
1368         /*                              p_phy_sta_rpt->gain_trsw_cd[0],p_phy_sta_rpt->gain_trsw_cd[1]);*/
1369         /*              dbg_print("p_phy_sta_rpt->pwdb_all = 0x%x, p_phy_info->rx_pwdb_all = %d\n", p_phy_sta_rpt->pwdb_all, p_phy_info->rx_pwdb_all);*/
1370         /*              dbg_print("p_phy_sta_rpt->cfotail[i] = 0x%x, p_phy_sta_rpt->CFO_tail[i] = 0x%x\n", p_phy_sta_rpt->cfotail[0], p_phy_sta_rpt->cfotail[1]);*/
1371         /*              dbg_print("p_phy_sta_rpt->rxevm[0] = %d, p_phy_sta_rpt->rxevm[1] = %d\n", p_phy_sta_rpt->rxevm[0], p_phy_sta_rpt->rxevm[1]);*/
1372         /*              dbg_print("p_phy_sta_rpt->rxevm[2] = %d, p_phy_sta_rpt->rxevm[3] = %d\n", p_phy_sta_rpt->rxevm_cd[0], p_phy_sta_rpt->rxevm_cd[1]);*/
1373         /*              dbg_print("p_phy_info->rx_mimo_signal_strength[0]=%d, p_phy_info->rx_mimo_signal_strength[1]=%d, rx_pwdb_all=%d\n",*/
1374         /*                              p_phy_info->rx_mimo_signal_strength[0], p_phy_info->rx_mimo_signal_strength[1], p_phy_info->rx_pwdb_all);*/
1375         /*              dbg_print("p_phy_info->rx_mimo_signal_strength[2]=%d, p_phy_info->rx_mimo_signal_strength[3]=%d\n",*/
1376         /*                              p_phy_info->rx_mimo_signal_strength[2], p_phy_info->rx_mimo_signal_strength[3]);*/
1377         /*              dbg_print("ppPhyInfo->rx_mimo_signal_quality[0]=%d, p_phy_info->rx_mimo_signal_quality[1]=%d\n",*/
1378         /*                              p_phy_info->rx_mimo_signal_quality[0], p_phy_info->rx_mimo_signal_quality[1]);*/
1379         /*              dbg_print("ppPhyInfo->rx_mimo_signal_quality[2]=%d, p_phy_info->rx_mimo_signal_quality[3]=%d\n",*/
1380         /*                              p_phy_info->rx_mimo_signal_quality[2], p_phy_info->rx_mimo_signal_quality[3]);*/
1381
1382 }
1383
1384 #endif
1385
1386 void
1387 phydm_reset_rssi_for_dm(
1388         struct PHY_DM_STRUCT    *p_dm_odm,
1389         u8              station_id
1390 )
1391 {
1392         struct sta_info                 *p_entry;
1393 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN))
1394         struct _ADAPTER         *adapter = p_dm_odm->adapter;
1395         HAL_DATA_TYPE   *p_hal_data = GET_HAL_DATA(adapter);
1396 #endif
1397
1398         p_entry = p_dm_odm->p_odm_sta_info[station_id];
1399
1400         if (!IS_STA_VALID(p_entry)) {
1401                 /**/
1402                 return;
1403         }
1404         ODM_RT_TRACE(p_dm_odm, ODM_COMP_RSSI_MONITOR, ODM_DBG_LOUD, ("Reset RSSI for macid = (( %d ))\n", station_id));
1405
1406
1407         p_entry->rssi_stat.undecorated_smoothed_cck = -1;
1408         p_entry->rssi_stat.undecorated_smoothed_ofdm = -1;
1409         p_entry->rssi_stat.undecorated_smoothed_pwdb = -1;
1410         p_entry->rssi_stat.ofdm_pkt = 0;
1411         p_entry->rssi_stat.cck_pkt = 0;
1412         p_entry->rssi_stat.cck_sum_power = 0;
1413         p_entry->rssi_stat.is_send_rssi = RA_RSSI_STATE_INIT;
1414         p_entry->rssi_stat.packet_map = 0;
1415         p_entry->rssi_stat.valid_bit = 0;
1416
1417         /*in WIN Driver: sta_ID==0->p_entry==NULL -> default port HAL_Data*/
1418 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN))
1419         p_entry->bUsed = 0;
1420         if (station_id == 0) {
1421
1422                 p_hal_data->UndecoratedSmoothedPWDB = -1;
1423                 /**/
1424         }
1425 #endif
1426
1427 }
1428
1429 void
1430 odm_init_rssi_for_dm(
1431         struct PHY_DM_STRUCT    *p_dm_odm
1432 )
1433 {
1434
1435 }
1436
1437 void
1438 odm_process_rssi_for_dm(
1439         struct PHY_DM_STRUCT                                    *p_dm_odm,
1440         struct _odm_phy_status_info_                    *p_phy_info,
1441         struct _odm_per_pkt_info_                       *p_pktinfo
1442 )
1443 {
1444
1445         s32                     undecorated_smoothed_pwdb, undecorated_smoothed_cck, undecorated_smoothed_ofdm, rssi_ave, cck_pkt;
1446         u8                      i, is_cck_rate = 0;
1447         u8                      RSSI_max, RSSI_min;
1448         u32                     weighting = 0;
1449         u8                      send_rssi_2_fw = 0;
1450         struct sta_info                 *p_entry;
1451 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN))
1452         struct _FAST_ANTENNA_TRAINNING_                 *p_dm_fat_table = &p_dm_odm->dm_fat_table;
1453         struct _ADAPTER         *adapter = p_dm_odm->adapter;
1454         HAL_DATA_TYPE   *p_hal_data = GET_HAL_DATA(adapter);
1455 #endif
1456
1457         if (p_pktinfo->station_id >= ODM_ASSOCIATE_ENTRY_NUM)
1458                 return;
1459
1460 #ifdef CONFIG_S0S1_SW_ANTENNA_DIVERSITY
1461         odm_s0s1_sw_ant_div_by_ctrl_frame_process_rssi(p_dm_odm, p_phy_info, p_pktinfo);
1462 #endif
1463
1464         /*  */
1465         /* 2012/05/30 MH/Luke.Lee Add some description */
1466         /* In windows driver: AP/IBSS mode STA */
1467         /*  */
1468         /* if (p_dm_odm->support_platform == ODM_WIN) */
1469         /* { */
1470         /*      p_entry = p_dm_odm->p_odm_sta_info[p_dm_odm->pAidMap[p_pktinfo->station_id-1]]; */
1471         /* } */
1472         /* else */
1473         p_entry = p_dm_odm->p_odm_sta_info[p_pktinfo->station_id];
1474
1475         if (!IS_STA_VALID(p_entry)) {
1476                 return;
1477                 /**/
1478         }
1479
1480 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN))
1481         if ((p_dm_odm->support_ability & ODM_BB_ANT_DIV) &&
1482             (p_dm_fat_table->enable_ctrl_frame_antdiv)
1483            ) {
1484                 if (p_pktinfo->is_packet_match_bssid)
1485                         p_dm_odm->data_frame_num++;
1486
1487                 if ((p_dm_fat_table->use_ctrl_frame_antdiv)) {
1488                         if (!p_pktinfo->is_to_self)/*data frame + CTRL frame*/
1489                                 return;
1490                 } else {
1491                         if ((!p_pktinfo->is_packet_match_bssid))/*data frame only*/
1492                                 return;
1493                 }
1494         } else
1495 #endif
1496         {
1497                 if ((!p_pktinfo->is_packet_match_bssid))/*data frame only*/
1498                         return;
1499         }
1500
1501         if (p_pktinfo->is_packet_beacon)
1502                 p_dm_odm->phy_dbg_info.num_qry_beacon_pkt++;
1503
1504         is_cck_rate = (p_pktinfo->data_rate <= ODM_RATE11M) ? true : false;
1505         p_dm_odm->rx_rate = p_pktinfo->data_rate;
1506
1507         /* --------------Statistic for antenna/path diversity------------------ */
1508         if (p_dm_odm->support_ability & ODM_BB_ANT_DIV) {
1509 #if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY))
1510                 odm_process_rssi_for_ant_div(p_dm_odm, p_phy_info, p_pktinfo);
1511 #endif
1512         }
1513 #if (defined(CONFIG_PATH_DIVERSITY))
1514         else if (p_dm_odm->support_ability & ODM_BB_PATH_DIV)
1515                 phydm_process_rssi_for_path_div(p_dm_odm, p_phy_info, p_pktinfo);
1516 #endif
1517         /* -----------------Smart Antenna Debug Message------------------ */
1518
1519         undecorated_smoothed_cck =  p_entry->rssi_stat.undecorated_smoothed_cck;
1520         undecorated_smoothed_ofdm = p_entry->rssi_stat.undecorated_smoothed_ofdm;
1521         undecorated_smoothed_pwdb = p_entry->rssi_stat.undecorated_smoothed_pwdb;
1522
1523         if (p_pktinfo->is_packet_to_self || p_pktinfo->is_packet_beacon) {
1524
1525                 if (!is_cck_rate) { /* ofdm rate */
1526 #if (RTL8814A_SUPPORT == 1) || (RTL8822B_SUPPORT == 1)
1527                         if (p_dm_odm->support_ic_type & (ODM_RTL8814A | ODM_RTL8822B)) {
1528                                 u8 RX_count = 0;
1529                                 u32 RSSI_linear = 0;
1530
1531                                 if (p_dm_odm->rx_ant_status & ODM_RF_A) {
1532                                         p_dm_odm->RSSI_A = p_phy_info->rx_mimo_signal_strength[ODM_RF_PATH_A];
1533                                         RX_count++;
1534                                         RSSI_linear += odm_convert_to_linear(p_phy_info->rx_mimo_signal_strength[ODM_RF_PATH_A]);
1535                                 } else
1536                                         p_dm_odm->RSSI_A = 0;
1537
1538                                 if (p_dm_odm->rx_ant_status & ODM_RF_B) {
1539                                         p_dm_odm->RSSI_B = p_phy_info->rx_mimo_signal_strength[ODM_RF_PATH_B];
1540                                         RX_count++;
1541                                         RSSI_linear += odm_convert_to_linear(p_phy_info->rx_mimo_signal_strength[ODM_RF_PATH_B]);
1542                                 } else
1543                                         p_dm_odm->RSSI_B = 0;
1544
1545                                 if (p_dm_odm->rx_ant_status & ODM_RF_C) {
1546                                         p_dm_odm->RSSI_C = p_phy_info->rx_mimo_signal_strength[ODM_RF_PATH_C];
1547                                         RX_count++;
1548                                         RSSI_linear += odm_convert_to_linear(p_phy_info->rx_mimo_signal_strength[ODM_RF_PATH_C]);
1549                                 } else
1550                                         p_dm_odm->RSSI_C = 0;
1551
1552                                 if (p_dm_odm->rx_ant_status & ODM_RF_D) {
1553                                         p_dm_odm->RSSI_D = p_phy_info->rx_mimo_signal_strength[ODM_RF_PATH_D];
1554                                         RX_count++;
1555                                         RSSI_linear += odm_convert_to_linear(p_phy_info->rx_mimo_signal_strength[ODM_RF_PATH_D]);
1556                                 } else
1557                                         p_dm_odm->RSSI_D = 0;
1558
1559                                 /* Calculate average RSSI */
1560                                 switch (RX_count) {
1561                                 case 2:
1562                                         RSSI_linear = (RSSI_linear >> 1);
1563                                         break;
1564                                 case 3:
1565                                         RSSI_linear = ((RSSI_linear) + (RSSI_linear << 1) + (RSSI_linear << 3)) >> 5;   /* RSSI_linear/3 ~ RSSI_linear*11/32 */
1566                                         break;
1567                                 case 4:
1568                                         RSSI_linear = (RSSI_linear >> 2);
1569                                         break;
1570                                 }
1571                                 rssi_ave = odm_convert_to_db(RSSI_linear);
1572                         } else
1573 #endif
1574                         {
1575                                 if (p_phy_info->rx_mimo_signal_strength[ODM_RF_PATH_B] == 0) {
1576                                         rssi_ave = p_phy_info->rx_mimo_signal_strength[ODM_RF_PATH_A];
1577                                         p_dm_odm->RSSI_A = p_phy_info->rx_mimo_signal_strength[ODM_RF_PATH_A];
1578                                         p_dm_odm->RSSI_B = 0;
1579                                 } else {
1580                                         /*dbg_print("p_rfd->status.rx_mimo_signal_strength[0] = %d, p_rfd->status.rx_mimo_signal_strength[1] = %d\n",*/
1581                                         /*p_rfd->status.rx_mimo_signal_strength[0], p_rfd->status.rx_mimo_signal_strength[1]);*/
1582                                         p_dm_odm->RSSI_A =  p_phy_info->rx_mimo_signal_strength[ODM_RF_PATH_A];
1583                                         p_dm_odm->RSSI_B = p_phy_info->rx_mimo_signal_strength[ODM_RF_PATH_B];
1584
1585                                         if (p_phy_info->rx_mimo_signal_strength[ODM_RF_PATH_A] > p_phy_info->rx_mimo_signal_strength[ODM_RF_PATH_B]) {
1586                                                 RSSI_max = p_phy_info->rx_mimo_signal_strength[ODM_RF_PATH_A];
1587                                                 RSSI_min = p_phy_info->rx_mimo_signal_strength[ODM_RF_PATH_B];
1588                                         } else {
1589                                                 RSSI_max = p_phy_info->rx_mimo_signal_strength[ODM_RF_PATH_B];
1590                                                 RSSI_min = p_phy_info->rx_mimo_signal_strength[ODM_RF_PATH_A];
1591                                         }
1592                                         if ((RSSI_max - RSSI_min) < 3)
1593                                                 rssi_ave = RSSI_max;
1594                                         else if ((RSSI_max - RSSI_min) < 6)
1595                                                 rssi_ave = RSSI_max - 1;
1596                                         else if ((RSSI_max - RSSI_min) < 10)
1597                                                 rssi_ave = RSSI_max - 2;
1598                                         else
1599                                                 rssi_ave = RSSI_max - 3;
1600                                 }
1601                         }
1602
1603                         /* 1 Process OFDM RSSI */
1604                         if (undecorated_smoothed_ofdm <= 0) {   /* initialize */
1605                                 undecorated_smoothed_ofdm = p_phy_info->rx_pwdb_all;
1606                                 ODM_RT_TRACE(p_dm_odm, ODM_COMP_RSSI_MONITOR, ODM_DBG_LOUD, ("OFDM_INIT: (( %d ))\n", undecorated_smoothed_ofdm));
1607                         } else {
1608                                 if (p_phy_info->rx_pwdb_all > (u32)undecorated_smoothed_ofdm) {
1609                                         undecorated_smoothed_ofdm =
1610                                                 (((undecorated_smoothed_ofdm)*(RX_SMOOTH_FACTOR - 1)) +
1611                                                 (rssi_ave)) / (RX_SMOOTH_FACTOR);
1612                                         undecorated_smoothed_ofdm = undecorated_smoothed_ofdm + 1;
1613                                         ODM_RT_TRACE(p_dm_odm, ODM_COMP_RSSI_MONITOR, ODM_DBG_LOUD, ("OFDM_1: (( %d ))\n", undecorated_smoothed_ofdm));
1614                                 } else {
1615                                         undecorated_smoothed_ofdm =
1616                                                 (((undecorated_smoothed_ofdm)*(RX_SMOOTH_FACTOR - 1)) +
1617                                                 (rssi_ave)) / (RX_SMOOTH_FACTOR);
1618                                         ODM_RT_TRACE(p_dm_odm, ODM_COMP_RSSI_MONITOR, ODM_DBG_LOUD, ("OFDM_2: (( %d ))\n", undecorated_smoothed_ofdm));
1619                                 }
1620                         }
1621                         if (p_entry->rssi_stat.ofdm_pkt != 64) {
1622                                 i = 63;
1623                                 p_entry->rssi_stat.ofdm_pkt -= (u8)(((p_entry->rssi_stat.packet_map >> i) & BIT(0)) - 1);
1624                         }
1625                         p_entry->rssi_stat.packet_map = (p_entry->rssi_stat.packet_map << 1) | BIT(0);
1626
1627                 } else {
1628                         rssi_ave = p_phy_info->rx_pwdb_all;
1629                         p_dm_odm->RSSI_A = (u8) p_phy_info->rx_pwdb_all;
1630                         p_dm_odm->RSSI_B = 0xFF;
1631                         p_dm_odm->RSSI_C = 0xFF;
1632                         p_dm_odm->RSSI_D = 0xFF;
1633
1634                         if (p_entry->rssi_stat.cck_pkt <= 63)
1635                                 p_entry->rssi_stat.cck_pkt++;
1636
1637                         /* 1 Process CCK RSSI */
1638                         if (undecorated_smoothed_cck <= 0) {    /* initialize */
1639                                 undecorated_smoothed_cck = p_phy_info->rx_pwdb_all;
1640                                 p_entry->rssi_stat.cck_sum_power = (u16)p_phy_info->rx_pwdb_all ; /*reset*/
1641                                 p_entry->rssi_stat.cck_pkt = 1; /*reset*/
1642                                 ODM_RT_TRACE(p_dm_odm, ODM_COMP_RSSI_MONITOR, ODM_DBG_LOUD, ("CCK_INIT: (( %d ))\n", undecorated_smoothed_cck));
1643                         } else if (p_entry->rssi_stat.cck_pkt <= CCK_RSSI_INIT_COUNT) {
1644
1645                                 p_entry->rssi_stat.cck_sum_power = p_entry->rssi_stat.cck_sum_power + (u16)p_phy_info->rx_pwdb_all;
1646                                 undecorated_smoothed_cck = p_entry->rssi_stat.cck_sum_power / p_entry->rssi_stat.cck_pkt;
1647
1648                                 ODM_RT_TRACE(p_dm_odm, ODM_COMP_RSSI_MONITOR, ODM_DBG_LOUD, ("CCK_0: (( %d )), SumPow = (( %d )), cck_pkt = (( %d ))\n",
1649                                         undecorated_smoothed_cck, p_entry->rssi_stat.cck_sum_power, p_entry->rssi_stat.cck_pkt));
1650                         } else {
1651                                 if (p_phy_info->rx_pwdb_all > (u32)undecorated_smoothed_cck) {
1652                                         undecorated_smoothed_cck =
1653                                                 (((undecorated_smoothed_cck)*(RX_SMOOTH_FACTOR - 1)) +
1654                                                 (p_phy_info->rx_pwdb_all)) / (RX_SMOOTH_FACTOR);
1655                                         undecorated_smoothed_cck = undecorated_smoothed_cck + 1;
1656                                         ODM_RT_TRACE(p_dm_odm, ODM_COMP_RSSI_MONITOR, ODM_DBG_LOUD, ("CCK_1: (( %d ))\n", undecorated_smoothed_cck));
1657                                 } else {
1658                                         undecorated_smoothed_cck =
1659                                                 (((undecorated_smoothed_cck)*(RX_SMOOTH_FACTOR - 1)) +
1660                                                 (p_phy_info->rx_pwdb_all)) / (RX_SMOOTH_FACTOR);
1661                                         ODM_RT_TRACE(p_dm_odm, ODM_COMP_RSSI_MONITOR, ODM_DBG_LOUD, ("CCK_2: (( %d ))\n", undecorated_smoothed_cck));
1662                                 }
1663                         }
1664                         i = 63;
1665                         p_entry->rssi_stat.ofdm_pkt -= (u8)((p_entry->rssi_stat.packet_map >> i) & BIT(0));
1666                         p_entry->rssi_stat.packet_map = p_entry->rssi_stat.packet_map << 1;
1667                 }
1668
1669                 /* if(p_entry) */
1670                 {
1671                         /* 2011.07.28 LukeLee: modified to prevent unstable CCK RSSI */
1672                         if (p_entry->rssi_stat.ofdm_pkt == 64) { /* speed up when all packets are OFDM*/
1673                                 undecorated_smoothed_pwdb = undecorated_smoothed_ofdm;
1674                                 ODM_RT_TRACE(p_dm_odm, ODM_COMP_RSSI_MONITOR, ODM_DBG_LOUD, ("PWDB_0[%d] = (( %d ))\n", p_pktinfo->station_id, undecorated_smoothed_cck));
1675                         } else {
1676                                 if (p_entry->rssi_stat.valid_bit < 64)
1677                                         p_entry->rssi_stat.valid_bit++;
1678
1679                                 if (p_entry->rssi_stat.valid_bit == 64) {
1680                                         weighting = ((p_entry->rssi_stat.ofdm_pkt) > 4) ? 64 : (p_entry->rssi_stat.ofdm_pkt << 4);
1681                                         undecorated_smoothed_pwdb = (weighting * undecorated_smoothed_ofdm + (64 - weighting) * undecorated_smoothed_cck) >> 6;
1682                                         ODM_RT_TRACE(p_dm_odm, ODM_COMP_RSSI_MONITOR, ODM_DBG_LOUD, ("PWDB_1[%d] = (( %d )), W = (( %d ))\n", p_pktinfo->station_id, undecorated_smoothed_cck, weighting));
1683                                 } else {
1684                                         if (p_entry->rssi_stat.valid_bit != 0)
1685                                                 undecorated_smoothed_pwdb = (p_entry->rssi_stat.ofdm_pkt * undecorated_smoothed_ofdm + (p_entry->rssi_stat.valid_bit - p_entry->rssi_stat.ofdm_pkt) * undecorated_smoothed_cck) / p_entry->rssi_stat.valid_bit;
1686                                         else
1687                                                 undecorated_smoothed_pwdb = 0;
1688
1689                                         ODM_RT_TRACE(p_dm_odm, ODM_COMP_RSSI_MONITOR, ODM_DBG_LOUD, ("PWDB_2[%d] = (( %d )), ofdm_pkt = (( %d )), Valid_Bit = (( %d ))\n", p_pktinfo->station_id, undecorated_smoothed_cck, p_entry->rssi_stat.ofdm_pkt, p_entry->rssi_stat.valid_bit));
1690                                 }
1691                         }
1692
1693
1694                         if ((p_entry->rssi_stat.ofdm_pkt >= 1 || p_entry->rssi_stat.cck_pkt >= 5) && (p_entry->rssi_stat.is_send_rssi == RA_RSSI_STATE_INIT)) {
1695
1696                                 send_rssi_2_fw = 1;
1697                                 p_entry->rssi_stat.is_send_rssi = RA_RSSI_STATE_SEND;
1698                         }
1699
1700                         p_entry->rssi_stat.undecorated_smoothed_cck = undecorated_smoothed_cck;
1701                         p_entry->rssi_stat.undecorated_smoothed_ofdm = undecorated_smoothed_ofdm;
1702                         p_entry->rssi_stat.undecorated_smoothed_pwdb = undecorated_smoothed_pwdb;
1703
1704
1705
1706                         if (send_rssi_2_fw) { /* Trigger init rate by RSSI */
1707
1708                                 if (p_entry->rssi_stat.ofdm_pkt != 0)
1709                                         p_entry->rssi_stat.undecorated_smoothed_pwdb = undecorated_smoothed_ofdm;
1710
1711                                 ODM_RT_TRACE(p_dm_odm, ODM_COMP_RSSI_MONITOR, ODM_DBG_LOUD, ("[Send to FW] PWDB = (( %d )), ofdm_pkt = (( %d )), cck_pkt = (( %d ))\n",
1712                                         undecorated_smoothed_pwdb, p_entry->rssi_stat.ofdm_pkt, p_entry->rssi_stat.cck_pkt));
1713
1714 #if (DM_ODM_SUPPORT_TYPE == ODM_CE)
1715                                 phydm_ra_rssi_rpt_wk(p_dm_odm);
1716 #endif
1717                         }
1718
1719
1720                         /*in WIN Driver: sta_ID==0->p_entry==NULL -> default port HAL_Data*/
1721 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN))
1722
1723                         if (p_pktinfo->station_id == 0) {
1724                                 /**/
1725                                 p_hal_data->UndecoratedSmoothedPWDB = undecorated_smoothed_pwdb;
1726                         }
1727 #endif
1728
1729                         /* dbg_print("ofdm_pkt=%d, weighting=%d\n", ofdm_pkt, weighting); */
1730                         /* dbg_print("undecorated_smoothed_ofdm=%d, undecorated_smoothed_pwdb=%d, undecorated_smoothed_cck=%d\n", */
1731                         /*      undecorated_smoothed_ofdm, undecorated_smoothed_pwdb, undecorated_smoothed_cck); */
1732
1733                 }
1734
1735         }
1736 }
1737
1738
1739 #if (ODM_IC_11N_SERIES_SUPPORT == 1)
1740 /*
1741  * Endianness before calling this API
1742  *   */
1743 void
1744 odm_phy_status_query_92c_series(
1745         struct PHY_DM_STRUCT                                    *p_dm_odm,
1746         struct _odm_phy_status_info_                            *p_phy_info,
1747         u8                                              *p_phy_status,
1748         struct _odm_per_pkt_info_                       *p_pktinfo
1749 )
1750 {
1751         odm_rx_phy_status92c_series_parsing(p_dm_odm, p_phy_info, p_phy_status, p_pktinfo);
1752         odm_process_rssi_for_dm(p_dm_odm, p_phy_info, p_pktinfo);
1753 }
1754 #endif
1755
1756
1757 /*
1758  * Endianness before calling this API
1759  *   */
1760 #if     ODM_IC_11AC_SERIES_SUPPORT
1761
1762 void
1763 odm_phy_status_query_jaguar_series(
1764         struct PHY_DM_STRUCT                                    *p_dm_odm,
1765         struct _odm_phy_status_info_                    *p_phy_info,
1766         u8                                              *p_phy_status,
1767         struct _odm_per_pkt_info_                       *p_pktinfo
1768 )
1769 {
1770         odm_rx_phy_status_jaguar_series_parsing(p_dm_odm, p_phy_info,   p_phy_status, p_pktinfo);
1771         odm_process_rssi_for_dm(p_dm_odm, p_phy_info, p_pktinfo);
1772
1773 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
1774         /*phydm_sbd_check(p_dm_odm);*/
1775 #endif
1776 }
1777 #endif
1778
1779 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
1780 void
1781 phydm_normal_driver_rx_sniffer(
1782         struct PHY_DM_STRUCT                    *p_dm_odm,
1783         u8                              *p_desc,
1784         PRT_RFD_STATUS          p_rt_rfd_status,
1785         u8                              *p_drv_info,
1786         u8                              phy_status
1787 )
1788 {
1789 #if (defined(CONFIG_PHYDM_RX_SNIFFER_PARSING))
1790         u32             *p_msg;
1791         u16             seq_num;
1792         struct _FAST_ANTENNA_TRAINNING_         *p_dm_fat_table = &p_dm_odm->dm_fat_table;
1793
1794         if (p_rt_rfd_status->packet_report_type != NORMAL_RX)
1795                 return;
1796
1797         if (!p_dm_odm->is_linked) {
1798                 if (p_rt_rfd_status->is_hw_error)
1799                         return;
1800         }
1801
1802         if (!(p_dm_fat_table->fat_state == FAT_TRAINING_STATE))
1803                 return;
1804
1805         if (phy_status == true) {
1806
1807                 if ((p_dm_odm->rx_pkt_type == type_block_ack) || (p_dm_odm->rx_pkt_type == type_rts) || (p_dm_odm->rx_pkt_type == type_cts))
1808                         seq_num = 0;
1809                 else
1810                         seq_num = p_rt_rfd_status->seq_num;
1811
1812                 ODM_RT_TRACE_F(p_dm_odm, ODM_COMP_SNIFFER, ODM_DBG_LOUD, ("%04d , %01s, rate=0x%02x, L=%04d , %s , %s",
1813                                 seq_num,
1814                                 /*p_rt_rfd_status->mac_id,*/
1815                         ((p_rt_rfd_status->is_crc) ? "C" : (p_rt_rfd_status->is_ampdu) ? "A" : "_"),
1816                                 p_rt_rfd_status->data_rate,
1817                                 p_rt_rfd_status->length,
1818                         ((p_rt_rfd_status->band_width == 0) ? "20M" : ((p_rt_rfd_status->band_width == 1) ? "40M" : "80M")),
1819                                 ((p_rt_rfd_status->is_ldpc) ? "LDP" : "BCC")
1820                                                                          ));
1821
1822                 if (p_dm_odm->rx_pkt_type == type_asoc_req) {
1823                         ODM_RT_TRACE_F(p_dm_odm, ODM_COMP_SNIFFER, ODM_DBG_LOUD, (" , [%s]", "AS_REQ"));
1824                         /**/
1825                 } else if (p_dm_odm->rx_pkt_type == type_asoc_rsp) {
1826                         ODM_RT_TRACE_F(p_dm_odm, ODM_COMP_SNIFFER, ODM_DBG_LOUD, (" , [%s]", "AS_RSP"));
1827                         /**/
1828                 } else if (p_dm_odm->rx_pkt_type == type_probe_req) {
1829                         ODM_RT_TRACE_F(p_dm_odm, ODM_COMP_SNIFFER, ODM_DBG_LOUD, (" , [%s]", "PR_REQ"));
1830                         /**/
1831                 } else if (p_dm_odm->rx_pkt_type == type_probe_rsp) {
1832                         ODM_RT_TRACE_F(p_dm_odm, ODM_COMP_SNIFFER, ODM_DBG_LOUD, (" , [%s]", "PR_RSP"));
1833                         /**/
1834                 } else if (p_dm_odm->rx_pkt_type == type_deauth) {
1835                         ODM_RT_TRACE_F(p_dm_odm, ODM_COMP_SNIFFER, ODM_DBG_LOUD, (" , [%s]", "DEAUTH"));
1836                         /**/
1837                 } else if (p_dm_odm->rx_pkt_type == type_beacon) {
1838                         ODM_RT_TRACE_F(p_dm_odm, ODM_COMP_SNIFFER, ODM_DBG_LOUD, (" , [%s]", "BEACON"));
1839                         /**/
1840                 } else if (p_dm_odm->rx_pkt_type == type_block_ack_req) {
1841                         ODM_RT_TRACE_F(p_dm_odm, ODM_COMP_SNIFFER, ODM_DBG_LOUD, (" , [%s]", "BA_REQ"));
1842                         /**/
1843                 } else if (p_dm_odm->rx_pkt_type == type_rts) {
1844                         ODM_RT_TRACE_F(p_dm_odm, ODM_COMP_SNIFFER, ODM_DBG_LOUD, (" , [%s]", "__RTS_"));
1845                         /**/
1846                 } else if (p_dm_odm->rx_pkt_type == type_cts) {
1847                         ODM_RT_TRACE_F(p_dm_odm, ODM_COMP_SNIFFER, ODM_DBG_LOUD, (" , [%s]", "__CTS_"));
1848                         /**/
1849                 } else if (p_dm_odm->rx_pkt_type == type_ack) {
1850                         ODM_RT_TRACE_F(p_dm_odm, ODM_COMP_SNIFFER, ODM_DBG_LOUD, (" , [%s]", "__ACK_"));
1851                         /**/
1852                 } else if (p_dm_odm->rx_pkt_type == type_block_ack) {
1853                         ODM_RT_TRACE_F(p_dm_odm, ODM_COMP_SNIFFER, ODM_DBG_LOUD, (" , [%s]", "__BA__"));
1854                         /**/
1855                 } else if (p_dm_odm->rx_pkt_type == type_data) {
1856                         ODM_RT_TRACE_F(p_dm_odm, ODM_COMP_SNIFFER, ODM_DBG_LOUD, (" , [%s]", "_DATA_"));
1857                         /**/
1858                 } else if (p_dm_odm->rx_pkt_type == type_data_ack) {
1859                         ODM_RT_TRACE_F(p_dm_odm, ODM_COMP_SNIFFER, ODM_DBG_LOUD, (" , [%s]", "Data_Ack"));
1860                         /**/
1861                 } else if (p_dm_odm->rx_pkt_type == type_qos_data) {
1862                         ODM_RT_TRACE_F(p_dm_odm, ODM_COMP_SNIFFER, ODM_DBG_LOUD, (" , [%s]", "QoS_Data"));
1863                         /**/
1864                 } else {
1865                         ODM_RT_TRACE_F(p_dm_odm, ODM_COMP_SNIFFER, ODM_DBG_LOUD, (" , [0x%x]", p_dm_odm->rx_pkt_type));
1866                         /**/
1867                 }
1868
1869                 ODM_RT_TRACE_F(p_dm_odm, ODM_COMP_SNIFFER, ODM_DBG_LOUD, (" , [RSSI=%d,%d,%d,%d ]",
1870                                 p_dm_odm->RSSI_A,
1871                                 p_dm_odm->RSSI_B,
1872                                 p_dm_odm->RSSI_C,
1873                                 p_dm_odm->RSSI_D
1874                                                                          ));
1875
1876                 p_msg = (u32 *)p_drv_info;
1877
1878                 ODM_RT_TRACE_F(p_dm_odm, ODM_COMP_SNIFFER, ODM_DBG_LOUD, (" , P-STS[28:0]=%08x-%08x-%08x-%08x-%08x-%08x-%08x\n",
1879                         p_msg[6], p_msg[5], p_msg[4], p_msg[3], p_msg[2], p_msg[1], p_msg[1]));
1880         } else {
1881
1882                 ODM_RT_TRACE_F(p_dm_odm, ODM_COMP_SNIFFER, ODM_DBG_LOUD, ("%04d , %01s, rate=0x%02x, L=%04d , %s , %s\n",
1883                                 p_rt_rfd_status->seq_num,
1884                                 /*p_rt_rfd_status->mac_id,*/
1885                         ((p_rt_rfd_status->is_crc) ? "C" : (p_rt_rfd_status->is_ampdu) ? "A" : "_"),
1886                                 p_rt_rfd_status->data_rate,
1887                                 p_rt_rfd_status->length,
1888                         ((p_rt_rfd_status->band_width == 0) ? "20M" : ((p_rt_rfd_status->band_width == 1) ? "40M" : "80M")),
1889                                 ((p_rt_rfd_status->is_ldpc) ? "LDP" : "BCC")
1890                                                                          ));
1891         }
1892
1893
1894 #endif
1895 }
1896 #endif
1897
1898 void
1899 odm_phy_status_query(
1900         struct PHY_DM_STRUCT                                    *p_dm_odm,
1901         struct _odm_phy_status_info_                    *p_phy_info,
1902         u8                                              *p_phy_status,
1903         struct _odm_per_pkt_info_                       *p_pktinfo
1904 )
1905 {
1906 #if (ODM_PHY_STATUS_NEW_TYPE_SUPPORT == 1)
1907         if (p_dm_odm->support_ic_type & ODM_IC_PHY_STATUE_NEW_TYPE) {
1908                 phydm_rx_phy_status_new_type(p_dm_odm, p_phy_status, p_pktinfo, p_phy_info);
1909                 return;
1910         }
1911 #endif
1912
1913 #if     ODM_IC_11AC_SERIES_SUPPORT
1914         if (p_dm_odm->support_ic_type & ODM_IC_11AC_SERIES)
1915                 odm_phy_status_query_jaguar_series(p_dm_odm, p_phy_info, p_phy_status, p_pktinfo);
1916 #endif
1917
1918 #if     ODM_IC_11N_SERIES_SUPPORT
1919         if (p_dm_odm->support_ic_type & ODM_IC_11N_SERIES)
1920                 odm_phy_status_query_92c_series(p_dm_odm, p_phy_info, p_phy_status, p_pktinfo);
1921 #endif
1922 }
1923
1924 /* For future use. */
1925 void
1926 odm_mac_status_query(
1927         struct PHY_DM_STRUCT                                    *p_dm_odm,
1928         u8                                              *p_mac_status,
1929         u8                                              mac_id,
1930         boolean                                         is_packet_match_bssid,
1931         boolean                                         is_packet_to_self,
1932         boolean                                         is_packet_beacon
1933 )
1934 {
1935         /* 2011/10/19 Driver team will handle in the future. */
1936
1937 }
1938
1939
1940 /*
1941  * If you want to add a new IC, Please follow below template and generate a new one.
1942  *
1943  *   */
1944
1945 enum hal_status
1946 odm_config_rf_with_header_file(
1947         struct PHY_DM_STRUCT            *p_dm_odm,
1948         enum odm_rf_config_type         config_type,
1949         enum odm_rf_radio_path_e        e_rf_path
1950 )
1951 {
1952 #if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
1953         struct _ADAPTER         *adapter = p_dm_odm->adapter;
1954         PMGNT_INFO              p_mgnt_info = &(adapter->MgntInfo);
1955 #endif
1956
1957         ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD,
1958                 ("===>odm_config_rf_with_header_file (%s)\n", (p_dm_odm->is_mp_chip) ? "MPChip" : "TestChip"));
1959         ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD,
1960                 ("p_dm_odm->support_platform: 0x%X, p_dm_odm->support_interface: 0x%X, p_dm_odm->board_type: 0x%X\n",
1961                 p_dm_odm->support_platform, p_dm_odm->support_interface, p_dm_odm->board_type));
1962
1963         /* 1 AP doesn't use PHYDM power tracking table in these ICs */
1964 #if (DM_ODM_SUPPORT_TYPE != ODM_AP)
1965 #if (RTL8812A_SUPPORT == 1)
1966         if (p_dm_odm->support_ic_type == ODM_RTL8812) {
1967                 if (config_type == CONFIG_RF_RADIO) {
1968                         if (e_rf_path == ODM_RF_PATH_A)
1969                                 READ_AND_CONFIG_MP(8812a, _radioa);
1970                         else if (e_rf_path == ODM_RF_PATH_B)
1971                                 READ_AND_CONFIG_MP(8812a, _radiob);
1972                 } else if (config_type == CONFIG_RF_TXPWR_LMT) {
1973 #if (DM_ODM_SUPPORT_TYPE & ODM_WIN) && (DEV_BUS_TYPE == RT_PCI_INTERFACE)
1974                         HAL_DATA_TYPE   *p_hal_data = GET_HAL_DATA(adapter);
1975                         if ((p_hal_data->EEPROMSVID == 0x17AA && p_hal_data->EEPROMSMID == 0xA811) ||
1976                             (p_hal_data->EEPROMSVID == 0x10EC && p_hal_data->EEPROMSMID == 0xA812) ||
1977                             (p_hal_data->EEPROMSVID == 0x10EC && p_hal_data->EEPROMSMID == 0x8812))
1978                                 READ_AND_CONFIG_MP(8812a, _txpwr_lmt_hm812a03);
1979                         else
1980 #endif
1981                                 READ_AND_CONFIG_MP(8812a, _txpwr_lmt);
1982                 }
1983         }
1984 #endif
1985 #if (RTL8821A_SUPPORT == 1)
1986         if (p_dm_odm->support_ic_type == ODM_RTL8821) {
1987                 if (config_type == CONFIG_RF_RADIO) {
1988                         if (e_rf_path == ODM_RF_PATH_A)
1989                                 READ_AND_CONFIG_MP(8821a, _radioa);
1990                 } else if (config_type == CONFIG_RF_TXPWR_LMT) {
1991                         if (p_dm_odm->support_interface == ODM_ITRF_USB) {
1992                                 if (p_dm_odm->ext_pa_5g || p_dm_odm->ext_lna_5g)
1993                                         READ_AND_CONFIG_MP(8821a, _txpwr_lmt_8811a_u_fem);
1994                                 else
1995                                         READ_AND_CONFIG_MP(8821a, _txpwr_lmt_8811a_u_ipa);
1996                         } else {
1997 #if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
1998                                 if (p_mgnt_info->CustomerID == RT_CID_8821AE_ASUS_MB)
1999                                         READ_AND_CONFIG_MP(8821a, _txpwr_lmt_8821a_sar_8mm);
2000                                 else if (p_mgnt_info->CustomerID == RT_CID_ASUS_NB)
2001                                         READ_AND_CONFIG_MP(8821a, _txpwr_lmt_8821a_sar_5mm);
2002                                 else
2003 #endif
2004                                         READ_AND_CONFIG_MP(8821a, _txpwr_lmt_8821a);
2005                         }
2006                 }
2007                 ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("<===8821_ODM_ConfigRFWithHeaderFile\n"));
2008         }
2009 #endif
2010 #if (RTL8192E_SUPPORT == 1)
2011         if (p_dm_odm->support_ic_type == ODM_RTL8192E) {
2012                 if (config_type == CONFIG_RF_RADIO) {
2013                         if (e_rf_path == ODM_RF_PATH_A)
2014                                 READ_AND_CONFIG_MP(8192e, _radioa);
2015                         else if (e_rf_path == ODM_RF_PATH_B)
2016                                 READ_AND_CONFIG_MP(8192e, _radiob);
2017                 } else if (config_type == CONFIG_RF_TXPWR_LMT) {
2018 #if (DM_ODM_SUPPORT_TYPE & ODM_WIN) && (DEV_BUS_TYPE == RT_PCI_INTERFACE)       /*Refine by Vincent Lan for 5mm SAR pwr limit*/
2019                         HAL_DATA_TYPE   *p_hal_data = GET_HAL_DATA(adapter);
2020
2021                         if ((p_hal_data->EEPROMSVID == 0x11AD && p_hal_data->EEPROMSMID == 0x8192) ||
2022                             (p_hal_data->EEPROMSVID == 0x11AD && p_hal_data->EEPROMSMID == 0x8193))
2023                                 READ_AND_CONFIG_MP(8192e, _txpwr_lmt_8192e_sar_5mm);
2024                         else
2025 #endif
2026                                 READ_AND_CONFIG_MP(8192e, _txpwr_lmt);
2027                 }
2028         }
2029 #endif
2030 #if (RTL8723D_SUPPORT == 1)
2031         if (p_dm_odm->support_ic_type == ODM_RTL8723D) {
2032                 if (config_type == CONFIG_RF_RADIO) {
2033                         if (e_rf_path == ODM_RF_PATH_A)
2034                                 READ_AND_CONFIG_MP(8723d, _radioa);
2035                 } else if (config_type == CONFIG_RF_TXPWR_LMT)
2036                         READ_AND_CONFIG_MP(8723d, _txpwr_lmt);
2037         }
2038 #endif
2039 /* JJ ADD 20161014 */
2040 #if (RTL8710B_SUPPORT == 1)
2041         if (p_dm_odm->support_ic_type == ODM_RTL8710B) {
2042                 if (config_type == CONFIG_RF_RADIO) {
2043                         if (e_rf_path == ODM_RF_PATH_A)
2044                                 READ_AND_CONFIG_MP(8710b, _radioa);
2045                 } else if (config_type == CONFIG_RF_TXPWR_LMT)
2046                         READ_AND_CONFIG_MP(8710b, _txpwr_lmt);
2047         }
2048 #endif
2049
2050 #endif/* (DM_ODM_SUPPORT_TYPE !=  ODM_AP) */
2051
2052         /* 1 All platforms support */
2053 #if (RTL8188E_SUPPORT == 1)
2054         if (p_dm_odm->support_ic_type == ODM_RTL8188E) {
2055                 if (config_type == CONFIG_RF_RADIO) {
2056                         if (e_rf_path == ODM_RF_PATH_A)
2057                                 READ_AND_CONFIG_MP(8188e, _radioa);
2058                 } else if (config_type == CONFIG_RF_TXPWR_LMT)
2059                         READ_AND_CONFIG_MP(8188e, _txpwr_lmt);
2060         }
2061 #endif
2062 #if (RTL8723B_SUPPORT == 1)
2063         if (p_dm_odm->support_ic_type == ODM_RTL8723B) {
2064                 if (config_type == CONFIG_RF_RADIO)
2065                         READ_AND_CONFIG_MP(8723b, _radioa);
2066                 else if (config_type == CONFIG_RF_TXPWR_LMT)
2067                         READ_AND_CONFIG_MP(8723b, _txpwr_lmt);
2068         }
2069 #endif
2070 #if (RTL8814A_SUPPORT == 1)
2071         if (p_dm_odm->support_ic_type == ODM_RTL8814A) {
2072                 if (config_type == CONFIG_RF_RADIO) {
2073                         if (e_rf_path == ODM_RF_PATH_A)
2074                                 READ_AND_CONFIG_MP(8814a, _radioa);
2075                         else if (e_rf_path == ODM_RF_PATH_B)
2076                                 READ_AND_CONFIG_MP(8814a, _radiob);
2077                         else if (e_rf_path == ODM_RF_PATH_C)
2078                                 READ_AND_CONFIG_MP(8814a, _radioc);
2079                         else if (e_rf_path == ODM_RF_PATH_D)
2080                                 READ_AND_CONFIG_MP(8814a, _radiod);
2081                 } else if (config_type == CONFIG_RF_TXPWR_LMT) {
2082                         if (p_dm_odm->rfe_type == 0)
2083                                 READ_AND_CONFIG_MP(8814a,_txpwr_lmt);
2084                         else if (p_dm_odm->rfe_type == 1)
2085                                 READ_AND_CONFIG_MP(8814a,_txpwr_lmt_type1);
2086                         else if (p_dm_odm->rfe_type == 2)
2087                                 READ_AND_CONFIG_MP(8814a,_txpwr_lmt_type2);
2088                         else if (p_dm_odm->rfe_type == 3)
2089                                 READ_AND_CONFIG_MP(8814a,_txpwr_lmt_type3);
2090                         else if (p_dm_odm->rfe_type == 5)
2091                                 READ_AND_CONFIG_MP(8814a,_txpwr_lmt_type5);
2092                         else if (p_dm_odm->rfe_type == 7)
2093                                 READ_AND_CONFIG_MP(8814a,_txpwr_lmt_type7);
2094                         else
2095                                 READ_AND_CONFIG_MP(8814a,_txpwr_lmt);
2096                 }
2097         }
2098 #endif
2099 #if (RTL8703B_SUPPORT == 1)
2100         if (p_dm_odm->support_ic_type == ODM_RTL8703B) {
2101                 if (config_type == CONFIG_RF_RADIO) {
2102                         if (e_rf_path == ODM_RF_PATH_A)
2103                                 READ_AND_CONFIG_MP(8703b, _radioa);
2104                 }
2105         }
2106 #endif
2107 #if (RTL8188F_SUPPORT == 1)
2108         if (p_dm_odm->support_ic_type == ODM_RTL8188F) {
2109                 if (config_type == CONFIG_RF_RADIO) {
2110                         if (e_rf_path == ODM_RF_PATH_A)
2111                                 READ_AND_CONFIG_MP(8188f, _radioa);
2112                 } else if (config_type == CONFIG_RF_TXPWR_LMT)
2113                         READ_AND_CONFIG_MP(8188f, _txpwr_lmt);
2114         }
2115 #endif
2116 #if (RTL8822B_SUPPORT == 1)
2117         if (p_dm_odm->support_ic_type == ODM_RTL8822B) {
2118                 if (config_type == CONFIG_RF_RADIO) {
2119                         if (e_rf_path == ODM_RF_PATH_A)
2120                                 READ_AND_CONFIG_MP(8822b, _radioa);
2121                         else if (e_rf_path == ODM_RF_PATH_B)
2122                                 READ_AND_CONFIG_MP(8822b, _radiob);
2123                 } else if (config_type == CONFIG_RF_TXPWR_LMT) {
2124                         if (p_dm_odm->rfe_type == 5)
2125                                 READ_AND_CONFIG_MP(8822b, _txpwr_lmt_type5);
2126                         else
2127                                 READ_AND_CONFIG_MP(8822b, _txpwr_lmt);
2128                 }
2129         }
2130 #endif
2131
2132 #if (RTL8197F_SUPPORT == 1)
2133         if (p_dm_odm->support_ic_type == ODM_RTL8197F) {
2134                 if (config_type == CONFIG_RF_RADIO) {
2135                         if (e_rf_path == ODM_RF_PATH_A)
2136                                 READ_AND_CONFIG_MP(8197f, _radioa);
2137                         else if (e_rf_path == ODM_RF_PATH_B)
2138                                 READ_AND_CONFIG_MP(8197f, _radiob);
2139                 }
2140         }
2141 #endif
2142
2143 #if (RTL8821C_SUPPORT == 1)
2144         if (p_dm_odm->support_ic_type == ODM_RTL8821C) {
2145                 if (config_type == CONFIG_RF_RADIO) {
2146                         if (e_rf_path == ODM_RF_PATH_A)
2147                                 READ_AND_CONFIG(8821c, _radioa);
2148                 } else if (config_type == CONFIG_RF_TXPWR_LMT)
2149                         READ_AND_CONFIG(8821c, _txpwr_lmt);
2150         }
2151 #endif
2152
2153         return HAL_STATUS_SUCCESS;
2154 }
2155
2156 enum hal_status
2157 odm_config_rf_with_tx_pwr_track_header_file(
2158         struct PHY_DM_STRUCT            *p_dm_odm
2159 )
2160 {
2161         ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD,
2162                 ("===>odm_config_rf_with_tx_pwr_track_header_file (%s)\n", (p_dm_odm->is_mp_chip) ? "MPChip" : "TestChip"));
2163         ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD,
2164                 ("p_dm_odm->support_platform: 0x%X, p_dm_odm->support_interface: 0x%X, p_dm_odm->board_type: 0x%X\n",
2165                 p_dm_odm->support_platform, p_dm_odm->support_interface, p_dm_odm->board_type));
2166
2167
2168         /* 1 AP doesn't use PHYDM power tracking table in these ICs */
2169 #if (DM_ODM_SUPPORT_TYPE != ODM_AP)
2170 #if RTL8821A_SUPPORT
2171         if (p_dm_odm->support_ic_type == ODM_RTL8821) {
2172                 if (p_dm_odm->support_interface == ODM_ITRF_PCIE)
2173                         READ_AND_CONFIG_MP(8821a, _txpowertrack_pcie);
2174                 else if (p_dm_odm->support_interface == ODM_ITRF_USB)
2175                         READ_AND_CONFIG_MP(8821a, _txpowertrack_usb);
2176                 else if (p_dm_odm->support_interface == ODM_ITRF_SDIO)
2177                         READ_AND_CONFIG_MP(8821a, _txpowertrack_sdio);
2178         }
2179 #endif
2180 #if RTL8812A_SUPPORT
2181         if (p_dm_odm->support_ic_type == ODM_RTL8812) {
2182                 if (p_dm_odm->support_interface == ODM_ITRF_PCIE)
2183                         READ_AND_CONFIG_MP(8812a, _txpowertrack_pcie);
2184                 else if (p_dm_odm->support_interface == ODM_ITRF_USB) {
2185                         if (p_dm_odm->rfe_type == 3 && p_dm_odm->is_mp_chip)
2186                                 READ_AND_CONFIG_MP(8812a, _txpowertrack_rfe3);
2187                         else
2188                                 READ_AND_CONFIG_MP(8812a, _txpowertrack_usb);
2189                 }
2190
2191         }
2192 #endif
2193 #if RTL8192E_SUPPORT
2194         if (p_dm_odm->support_ic_type == ODM_RTL8192E) {
2195                 if (p_dm_odm->support_interface == ODM_ITRF_PCIE)
2196                         READ_AND_CONFIG_MP(8192e, _txpowertrack_pcie);
2197                 else if (p_dm_odm->support_interface == ODM_ITRF_USB)
2198                         READ_AND_CONFIG_MP(8192e, _txpowertrack_usb);
2199                 else if (p_dm_odm->support_interface == ODM_ITRF_SDIO)
2200                         READ_AND_CONFIG_MP(8192e, _txpowertrack_sdio);
2201         }
2202 #endif
2203 #if RTL8723D_SUPPORT
2204         if (p_dm_odm->support_ic_type == ODM_RTL8723D) {
2205                 if (p_dm_odm->support_interface == ODM_ITRF_PCIE)
2206                         READ_AND_CONFIG_MP(8723d, _txpowertrack_pcie);
2207                 else if (p_dm_odm->support_interface == ODM_ITRF_USB)
2208                         READ_AND_CONFIG_MP(8723d, _txpowertrack_usb);
2209                 else if (p_dm_odm->support_interface == ODM_ITRF_SDIO)
2210                         READ_AND_CONFIG_MP(8723d, _txpowertrack_sdio);
2211
2212                 READ_AND_CONFIG_MP(8723d, _txxtaltrack);
2213         }
2214 #endif
2215 /* JJ ADD 20161014 */
2216 #if RTL8710B_SUPPORT
2217         if (p_dm_odm->support_ic_type == ODM_RTL8710B) {
2218                 if (p_dm_odm->support_interface == ODM_ITRF_PCIE)
2219                         READ_AND_CONFIG_MP(8710b, _txpowertrack_pcie);
2220                 else if (p_dm_odm->support_interface == ODM_ITRF_USB)
2221                         READ_AND_CONFIG_MP(8710b, _txpowertrack_usb);
2222                 else if (p_dm_odm->support_interface == ODM_ITRF_SDIO)
2223                         READ_AND_CONFIG_MP(8710b, _txpowertrack_sdio);
2224
2225                 READ_AND_CONFIG_MP(8710b, _txxtaltrack);
2226         }
2227 #endif
2228
2229 #if RTL8188E_SUPPORT
2230         if (p_dm_odm->support_ic_type == ODM_RTL8188E) {
2231                 if (odm_get_mac_reg(p_dm_odm, 0xF0, 0xF000) >= 8) {             /*if 0xF0[15:12] >= 8, SMIC*/
2232                         if (p_dm_odm->support_interface == ODM_ITRF_PCIE)
2233                                 READ_AND_CONFIG_MP(8188e, _txpowertrack_pcie_icut);
2234                         else if (p_dm_odm->support_interface == ODM_ITRF_USB)
2235                                 READ_AND_CONFIG_MP(8188e, _txpowertrack_usb_icut);
2236                         else if (p_dm_odm->support_interface == ODM_ITRF_SDIO)
2237                                 READ_AND_CONFIG_MP(8188e, _txpowertrack_sdio_icut);
2238                 } else {        /*else 0xF0[15:12] < 8, TSMC*/
2239                         if (p_dm_odm->support_interface == ODM_ITRF_PCIE)
2240                                 READ_AND_CONFIG_MP(8188e, _txpowertrack_pcie);
2241                         else if (p_dm_odm->support_interface == ODM_ITRF_USB)
2242                                 READ_AND_CONFIG_MP(8188e, _txpowertrack_usb);
2243                         else if (p_dm_odm->support_interface == ODM_ITRF_SDIO)
2244                                 READ_AND_CONFIG_MP(8188e, _txpowertrack_sdio);
2245                 }
2246
2247         }
2248 #endif
2249 #endif/* (DM_ODM_SUPPORT_TYPE !=  ODM_AP) */
2250
2251         /* 1 All platforms support */
2252 #if RTL8723B_SUPPORT
2253         if (p_dm_odm->support_ic_type == ODM_RTL8723B) {
2254                 if (p_dm_odm->support_interface == ODM_ITRF_PCIE)
2255                         READ_AND_CONFIG_MP(8723b, _txpowertrack_pcie);
2256                 else if (p_dm_odm->support_interface == ODM_ITRF_USB)
2257                         READ_AND_CONFIG_MP(8723b, _txpowertrack_usb);
2258                 else if (p_dm_odm->support_interface == ODM_ITRF_SDIO)
2259                         READ_AND_CONFIG_MP(8723b, _txpowertrack_sdio);
2260         }
2261 #endif
2262 #if RTL8814A_SUPPORT
2263         if (p_dm_odm->support_ic_type == ODM_RTL8814A) {
2264                 if (p_dm_odm->rfe_type == 0)
2265                         READ_AND_CONFIG_MP(8814a, _txpowertrack_type0);
2266                 else if (p_dm_odm->rfe_type == 2)
2267                         READ_AND_CONFIG_MP(8814a, _txpowertrack_type2);
2268                 else if (p_dm_odm->rfe_type == 5)
2269                         READ_AND_CONFIG_MP(8814a, _txpowertrack_type5);
2270                 else
2271                         READ_AND_CONFIG_MP(8814a, _txpowertrack);
2272
2273                 READ_AND_CONFIG_MP(8814a, _txpowertssi);
2274         }
2275 #endif
2276 #if RTL8703B_SUPPORT
2277         if (p_dm_odm->support_ic_type == ODM_RTL8703B) {
2278                 if (p_dm_odm->support_interface == ODM_ITRF_USB)
2279                         READ_AND_CONFIG_MP(8703b, _txpowertrack_usb);
2280                 else if (p_dm_odm->support_interface == ODM_ITRF_SDIO)
2281                         READ_AND_CONFIG_MP(8703b, _txpowertrack_sdio);
2282
2283                 READ_AND_CONFIG_MP(8703b, _txxtaltrack);
2284         }
2285 #endif
2286
2287 #if RTL8188F_SUPPORT
2288         if (p_dm_odm->support_ic_type == ODM_RTL8188F) {
2289                 if (p_dm_odm->support_interface == ODM_ITRF_USB)
2290                         READ_AND_CONFIG_MP(8188f, _txpowertrack_usb);
2291                 else if (p_dm_odm->support_interface == ODM_ITRF_SDIO)
2292                         READ_AND_CONFIG_MP(8188f, _txpowertrack_sdio);
2293         }
2294 #endif
2295
2296 #if RTL8822B_SUPPORT
2297         if (p_dm_odm->support_ic_type == ODM_RTL8822B) {
2298                 if (p_dm_odm->rfe_type == 0)
2299                         READ_AND_CONFIG_MP(8822b, _txpowertrack_type0);
2300                 else if (p_dm_odm->rfe_type == 1)
2301                         READ_AND_CONFIG_MP(8822b, _txpowertrack_type1);
2302                 else if (p_dm_odm->rfe_type == 2)
2303                         READ_AND_CONFIG_MP(8822b, _txpowertrack_type2);
2304                 else if ((p_dm_odm->rfe_type == 3) || (p_dm_odm->rfe_type == 5))
2305                         READ_AND_CONFIG_MP(8822b, _txpowertrack_type3_type5);
2306                 else if (p_dm_odm->rfe_type == 4)
2307                         READ_AND_CONFIG_MP(8822b, _txpowertrack_type4);
2308                 else if (p_dm_odm->rfe_type == 6)
2309                         READ_AND_CONFIG_MP(8822b, _txpowertrack_type6);
2310                 else if (p_dm_odm->rfe_type == 7)
2311                         READ_AND_CONFIG_MP(8822b, _txpowertrack_type7);
2312                 else if (p_dm_odm->rfe_type == 8)
2313                         READ_AND_CONFIG_MP(8822b, _txpowertrack_type8);
2314                 else if (p_dm_odm->rfe_type == 9)
2315                         READ_AND_CONFIG_MP(8822b, _txpowertrack_type9);
2316                 else
2317                         READ_AND_CONFIG_MP(8822b, _txpowertrack);
2318         }
2319 #endif
2320
2321 #if RTL8197F_SUPPORT
2322         if (p_dm_odm->support_ic_type == ODM_RTL8197F) {
2323                 if (p_dm_odm->rfe_type == 0)
2324                         READ_AND_CONFIG_MP(8197f, _txpowertrack_type0);
2325                 else if (p_dm_odm->rfe_type == 1)
2326                         READ_AND_CONFIG_MP(8197f, _txpowertrack_type1);
2327                 else
2328                         READ_AND_CONFIG_MP(8197f, _txpowertrack);
2329         }
2330 #endif
2331
2332 #if RTL8821C_SUPPORT
2333         if (p_dm_odm->support_ic_type == ODM_RTL8821C)
2334                 READ_AND_CONFIG(8821c, _txpowertrack);
2335 #endif
2336
2337         return HAL_STATUS_SUCCESS;
2338 }
2339
2340 enum hal_status
2341 odm_config_bb_with_header_file(
2342         struct PHY_DM_STRUCT            *p_dm_odm,
2343         enum odm_bb_config_type         config_type
2344 )
2345 {
2346 #if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
2347         struct _ADAPTER         *adapter = p_dm_odm->adapter;
2348         PMGNT_INFO              p_mgnt_info = &(adapter->MgntInfo);
2349 #endif
2350
2351         /* 1 AP doesn't use PHYDM initialization in these ICs */
2352 #if (DM_ODM_SUPPORT_TYPE != ODM_AP)
2353 #if (RTL8812A_SUPPORT == 1)
2354         if (p_dm_odm->support_ic_type == ODM_RTL8812) {
2355                 if (config_type == CONFIG_BB_PHY_REG)
2356                         READ_AND_CONFIG_MP(8812a, _phy_reg);
2357                 else if (config_type == CONFIG_BB_AGC_TAB)
2358                         READ_AND_CONFIG_MP(8812a, _agc_tab);
2359                 else if (config_type == CONFIG_BB_PHY_REG_PG) {
2360                         if (p_dm_odm->rfe_type == 3 && p_dm_odm->is_mp_chip)
2361                                 READ_AND_CONFIG_MP(8812a, _phy_reg_pg_asus);
2362 #if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
2363                         else if (p_mgnt_info->CustomerID == RT_CID_WNC_NEC && p_dm_odm->is_mp_chip)
2364                                 READ_AND_CONFIG_MP(8812a, _phy_reg_pg_nec);
2365 #if RT_PLATFORM == PLATFORM_MACOSX
2366                         /*{1827}{1024} for BUFFALO power by rate table. Isaiah 2013-11-29*/
2367                         else if (p_mgnt_info->CustomerID == RT_CID_DNI_BUFFALO)
2368                                 READ_AND_CONFIG_MP(8812a, _phy_reg_pg_dni);
2369                         /* TP-Link T4UH, Isaiah 2015-03-16*/
2370                         else if (p_mgnt_info->CustomerID == RT_CID_TPLINK_HPWR) {
2371                                 dbg_print("RT_CID_TPLINK_HPWR:: _PHY_REG_PG_TPLINK\n");
2372                                 READ_AND_CONFIG_MP(8812a, _phy_reg_pg_tplink);
2373                         }
2374 #endif
2375 #endif
2376                         else
2377                                 READ_AND_CONFIG_MP(8812a, _phy_reg_pg);
2378                 } else if (config_type == CONFIG_BB_PHY_REG_MP)
2379                         READ_AND_CONFIG_MP(8812a, _phy_reg_mp);
2380                 else if (config_type == CONFIG_BB_AGC_TAB_DIFF) {
2381                         if ((36 <= *p_dm_odm->p_channel)  && (*p_dm_odm->p_channel  <= 64))
2382                                 AGC_DIFF_CONFIG_MP(8812a, lb);
2383                         else if (100 <= *p_dm_odm->p_channel)
2384                                 AGC_DIFF_CONFIG_MP(8812a, hb);
2385                 }
2386                 ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD, (" ===> phy_ConfigBBWithHeaderFile() phy:Rtl8812AGCTABArray\n"));
2387                 ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD, (" ===> phy_ConfigBBWithHeaderFile() agc:Rtl8812PHY_REGArray\n"));
2388         }
2389 #endif
2390 #if (RTL8821A_SUPPORT == 1)
2391         if (p_dm_odm->support_ic_type == ODM_RTL8821) {
2392                 if (config_type == CONFIG_BB_PHY_REG)
2393                         READ_AND_CONFIG_MP(8821a, _phy_reg);
2394                 else if (config_type == CONFIG_BB_AGC_TAB)
2395                         READ_AND_CONFIG_MP(8821a, _agc_tab);
2396                 else if (config_type == CONFIG_BB_PHY_REG_PG) {
2397 #if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
2398 #if (DEV_BUS_TYPE == RT_PCI_INTERFACE)
2399                         HAL_DATA_TYPE   *p_hal_data = GET_HAL_DATA(adapter);
2400
2401                         if ((p_hal_data->EEPROMSVID == 0x1043 && p_hal_data->EEPROMSMID == 0x207F))
2402                                 READ_AND_CONFIG_MP(8821a, _phy_reg_pg_e202_sa);
2403                         else
2404 #endif
2405 #if (RT_PLATFORM == PLATFORM_MACOSX)
2406                                 /*{1827}{1022} for BUFFALO power by rate table. Isaiah 2013-10-18*/
2407                                 if (p_mgnt_info->CustomerID == RT_CID_DNI_BUFFALO) {
2408                                         /*{1024} for BUFFALO power by rate table. (JP/US)*/
2409                                         if (p_mgnt_info->channel_plan == RT_CHANNEL_DOMAIN_US_2G_CANADA_5G)
2410                                                 READ_AND_CONFIG_MP(8821a, _phy_reg_pg_dni_us);
2411                                         else
2412                                                 READ_AND_CONFIG_MP(8821a, _phy_reg_pg_dni_jp);
2413                                 } else
2414 #endif
2415 #endif
2416                                         READ_AND_CONFIG_MP(8821a, _phy_reg_pg);
2417                 }
2418                 ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD, (" ===> phy_ConfigBBWithHeaderFile() phy:Rtl8821AGCTABArray\n"));
2419                 ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD, (" ===> phy_ConfigBBWithHeaderFile() agc:Rtl8821PHY_REGArray\n"));
2420         }
2421 #endif
2422 #if (RTL8192E_SUPPORT == 1)
2423         if (p_dm_odm->support_ic_type == ODM_RTL8192E) {
2424                 if (config_type == CONFIG_BB_PHY_REG)
2425                         READ_AND_CONFIG_MP(8192e, _phy_reg);
2426                 else if (config_type == CONFIG_BB_AGC_TAB)
2427                         READ_AND_CONFIG_MP(8192e, _agc_tab);
2428                 else if (config_type == CONFIG_BB_PHY_REG_PG)
2429                         READ_AND_CONFIG_MP(8192e, _phy_reg_pg);
2430         }
2431 #endif
2432 #if (RTL8723D_SUPPORT == 1)
2433         if (p_dm_odm->support_ic_type == ODM_RTL8723D) {
2434                 if (config_type == CONFIG_BB_PHY_REG)
2435                         READ_AND_CONFIG_MP(8723d, _phy_reg);
2436                 else if (config_type == CONFIG_BB_AGC_TAB)
2437                         READ_AND_CONFIG_MP(8723d, _agc_tab);
2438                 else if (config_type == CONFIG_BB_PHY_REG_PG)
2439                         READ_AND_CONFIG_MP(8723d, _phy_reg_pg);
2440         }
2441 #endif
2442 /* JJ ADD 20161014 */
2443 #if (RTL8710B_SUPPORT == 1)
2444         if (p_dm_odm->support_ic_type == ODM_RTL8710B) {
2445                 if (config_type == CONFIG_BB_PHY_REG)
2446                         READ_AND_CONFIG_MP(8710b, _phy_reg);
2447                 else if (config_type == CONFIG_BB_AGC_TAB)
2448                         READ_AND_CONFIG_MP(8710b, _agc_tab);
2449                 else if (config_type == CONFIG_BB_PHY_REG_PG)
2450                         READ_AND_CONFIG_MP(8710b, _phy_reg_pg);
2451         }
2452 #endif
2453
2454 #endif/* (DM_ODM_SUPPORT_TYPE !=  ODM_AP) */
2455
2456
2457         /* 1 All platforms support */
2458 #if (RTL8188E_SUPPORT == 1)
2459         if (p_dm_odm->support_ic_type == ODM_RTL8188E) {
2460                 if (config_type == CONFIG_BB_PHY_REG)
2461                         READ_AND_CONFIG_MP(8188e, _phy_reg);
2462                 else if (config_type == CONFIG_BB_AGC_TAB)
2463                         READ_AND_CONFIG_MP(8188e, _agc_tab);
2464                 else if (config_type == CONFIG_BB_PHY_REG_PG)
2465                         READ_AND_CONFIG_MP(8188e, _phy_reg_pg);
2466         }
2467 #endif
2468 #if (RTL8723B_SUPPORT == 1)
2469         if (p_dm_odm->support_ic_type == ODM_RTL8723B) {
2470                 if (config_type == CONFIG_BB_PHY_REG)
2471                         READ_AND_CONFIG_MP(8723b, _phy_reg);
2472                 else if (config_type == CONFIG_BB_AGC_TAB)
2473                         READ_AND_CONFIG_MP(8723b, _agc_tab);
2474                 else if (config_type == CONFIG_BB_PHY_REG_PG)
2475                         READ_AND_CONFIG_MP(8723b, _phy_reg_pg);
2476         }
2477 #endif
2478 #if (RTL8814A_SUPPORT == 1)
2479         if (p_dm_odm->support_ic_type == ODM_RTL8814A) {
2480                 if (config_type == CONFIG_BB_PHY_REG)
2481                         READ_AND_CONFIG_MP(8814a, _phy_reg);
2482                 else if (config_type == CONFIG_BB_AGC_TAB)
2483                         READ_AND_CONFIG_MP(8814a, _agc_tab);
2484                 else if (config_type == CONFIG_BB_PHY_REG_PG) {
2485                         if (p_dm_odm->rfe_type == 0)
2486                                 READ_AND_CONFIG_MP(8814a,_phy_reg_pg);
2487                         else if (p_dm_odm->rfe_type == 2)
2488                                 READ_AND_CONFIG_MP(8814a,_phy_reg_pg_type2);
2489                         else if (p_dm_odm->rfe_type == 3)
2490                                 READ_AND_CONFIG_MP(8814a,_phy_reg_pg_type3);
2491                         else if (p_dm_odm->rfe_type == 4)
2492                                 READ_AND_CONFIG_MP(8814a,_phy_reg_pg_type4);
2493                         else if (p_dm_odm->rfe_type == 5)
2494                                 READ_AND_CONFIG_MP(8814a,_phy_reg_pg_type5);
2495                         else if (p_dm_odm->rfe_type == 7)
2496                                 READ_AND_CONFIG_MP(8814a,_phy_reg_pg_type7);
2497                         else
2498                                 READ_AND_CONFIG_MP(8814a,_phy_reg_pg);
2499                 }
2500                 else if (config_type == CONFIG_BB_PHY_REG_MP)
2501                         READ_AND_CONFIG_MP(8814a, _phy_reg_mp);
2502         }
2503 #endif
2504 #if (RTL8703B_SUPPORT == 1)
2505         if (p_dm_odm->support_ic_type == ODM_RTL8703B) {
2506                 if (config_type == CONFIG_BB_PHY_REG)
2507                         READ_AND_CONFIG_MP(8703b, _phy_reg);
2508                 else if (config_type == CONFIG_BB_AGC_TAB)
2509                         READ_AND_CONFIG_MP(8703b, _agc_tab);
2510                 else if (config_type == CONFIG_BB_PHY_REG_PG)
2511                         READ_AND_CONFIG_MP(8703b, _phy_reg_pg);
2512         }
2513 #endif
2514 #if (RTL8188F_SUPPORT == 1)
2515         if (p_dm_odm->support_ic_type == ODM_RTL8188F) {
2516                 if (config_type == CONFIG_BB_PHY_REG)
2517                         READ_AND_CONFIG_MP(8188f, _phy_reg);
2518                 else if (config_type == CONFIG_BB_AGC_TAB)
2519                         READ_AND_CONFIG_MP(8188f, _agc_tab);
2520                 else if (config_type == CONFIG_BB_PHY_REG_PG)
2521                         READ_AND_CONFIG_MP(8188f, _phy_reg_pg);
2522         }
2523 #endif
2524 #if (RTL8822B_SUPPORT == 1)
2525         if (p_dm_odm->support_ic_type == ODM_RTL8822B) {
2526                 if (config_type == CONFIG_BB_PHY_REG)
2527                         READ_AND_CONFIG_MP(8822b, _phy_reg);
2528                 else if (config_type == CONFIG_BB_AGC_TAB)
2529                         READ_AND_CONFIG_MP(8822b, _agc_tab);
2530                 else if (config_type == CONFIG_BB_PHY_REG_PG)
2531                         READ_AND_CONFIG_MP(8822b, _phy_reg_pg);
2532                 /*else if (config_type == CONFIG_BB_PHY_REG_MP)*/
2533                 /*READ_AND_CONFIG_MP(8822b, _phy_reg_mp);*/
2534         }
2535 #endif
2536
2537 #if (RTL8197F_SUPPORT == 1)
2538         if (p_dm_odm->support_ic_type == ODM_RTL8197F) {
2539                 if (config_type == CONFIG_BB_PHY_REG) {
2540                         READ_AND_CONFIG_MP(8197f, _phy_reg);
2541                         if (p_dm_odm->cut_version == ODM_CUT_A)
2542                                 phydm_phypara_a_cut(p_dm_odm);
2543                 } else if (config_type == CONFIG_BB_AGC_TAB)
2544                         READ_AND_CONFIG_MP(8197f, _agc_tab);
2545                 /*              else if(config_type == CONFIG_BB_PHY_REG_PG)
2546                                         READ_AND_CONFIG_MP(8197f, _phy_reg_pg);
2547                                 else if(config_type == CONFIG_BB_PHY_REG_MP)
2548                                         READ_AND_CONFIG_MP(8197f, _phy_reg_mp); */
2549         }
2550 #endif
2551
2552 #if (RTL8821C_SUPPORT == 1)
2553         if (p_dm_odm->support_ic_type == ODM_RTL8821C) {
2554                 if (config_type == CONFIG_BB_PHY_REG)
2555                         READ_AND_CONFIG(8821c, _phy_reg);
2556                 else if (config_type == CONFIG_BB_AGC_TAB) {
2557                         READ_AND_CONFIG(8821c, _agc_tab);
2558                         /* According to RFEtype, choosing correct AGC table*/
2559                         if (p_dm_odm->default_rf_set_8821c == SWITCH_TO_BTG)
2560                                 AGC_DIFF_CONFIG_MP(8821c, btg);
2561                 } else if (config_type == CONFIG_BB_PHY_REG_PG)
2562                         READ_AND_CONFIG(8821c, _phy_reg_pg);
2563                 else if (config_type == CONFIG_BB_AGC_TAB_DIFF) {
2564                         if (p_dm_odm->current_rf_set_8821c == SWITCH_TO_BTG)
2565                                 AGC_DIFF_CONFIG_MP(8821c, btg);
2566                         else if (p_dm_odm->current_rf_set_8821c == SWITCH_TO_WLG)
2567                                 AGC_DIFF_CONFIG_MP(8821c, wlg);
2568                 }
2569         }
2570 #endif
2571
2572 #if (RTL8195A_SUPPORT == 1)
2573         if (p_dm_odm->support_ic_type == ODM_RTL8195A) {
2574                 if (config_type == CONFIG_BB_PHY_REG)
2575                         READ_AND_CONFIG(8195a, _phy_reg);
2576                 else if (config_type == CONFIG_BB_AGC_TAB)
2577                         READ_AND_CONFIG(8195a, _agc_tab);
2578                 else if (config_type == CONFIG_BB_PHY_REG_PG)
2579                         READ_AND_CONFIG(8195a, _phy_reg_pg);
2580         }
2581 #endif
2582
2583         return HAL_STATUS_SUCCESS;
2584 }
2585
2586 enum hal_status
2587 odm_config_mac_with_header_file(
2588         struct PHY_DM_STRUCT    *p_dm_odm
2589 )
2590 {
2591 #if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
2592         struct _ADAPTER         *adapter = p_dm_odm->adapter;
2593 #endif
2594
2595         ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD,
2596                 ("===>odm_config_mac_with_header_file (%s)\n", (p_dm_odm->is_mp_chip) ? "MPChip" : "TestChip"));
2597         ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD,
2598                 ("p_dm_odm->support_platform: 0x%X, p_dm_odm->support_interface: 0x%X, p_dm_odm->board_type: 0x%X\n",
2599                 p_dm_odm->support_platform, p_dm_odm->support_interface, p_dm_odm->board_type));
2600
2601         /* 1 AP doesn't use PHYDM initialization in these ICs */
2602 #if (DM_ODM_SUPPORT_TYPE != ODM_AP)
2603 #if (RTL8812A_SUPPORT == 1)
2604         if (p_dm_odm->support_ic_type == ODM_RTL8812)
2605                 READ_AND_CONFIG_MP(8812a, _mac_reg);
2606 #endif
2607 #if (RTL8821A_SUPPORT == 1)
2608         if (p_dm_odm->support_ic_type == ODM_RTL8821) {
2609                 READ_AND_CONFIG_MP(8821a, _mac_reg);
2610
2611                 ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("<===8821_ODM_ConfigMACwithHeaderFile\n"));
2612         }
2613 #endif
2614 #if (RTL8192E_SUPPORT == 1)
2615         if (p_dm_odm->support_ic_type == ODM_RTL8192E)
2616                 READ_AND_CONFIG_MP(8192e, _mac_reg);
2617 #endif
2618 #if (RTL8723D_SUPPORT == 1)
2619         if (p_dm_odm->support_ic_type == ODM_RTL8723D)
2620                 READ_AND_CONFIG_MP(8723d, _mac_reg);
2621 #endif
2622 /* JJ ADD 20161014 */
2623 #if (RTL8710B_SUPPORT == 1)
2624         if (p_dm_odm->support_ic_type == ODM_RTL8710B)
2625                 READ_AND_CONFIG_MP(8710b, _mac_reg);
2626 #endif
2627
2628 #endif/* (DM_ODM_SUPPORT_TYPE !=  ODM_AP) */
2629
2630         /* 1 All platforms support */
2631 #if (RTL8188E_SUPPORT == 1)
2632         if (p_dm_odm->support_ic_type == ODM_RTL8188E)
2633                 READ_AND_CONFIG_MP(8188e, _mac_reg);
2634 #endif
2635 #if (RTL8723B_SUPPORT == 1)
2636         if (p_dm_odm->support_ic_type == ODM_RTL8723B)
2637                 READ_AND_CONFIG_MP(8723b, _mac_reg);
2638 #endif
2639 #if (RTL8814A_SUPPORT == 1)
2640         if (p_dm_odm->support_ic_type == ODM_RTL8814A)
2641                 READ_AND_CONFIG_MP(8814a, _mac_reg);
2642 #endif
2643 #if (RTL8703B_SUPPORT == 1)
2644         if (p_dm_odm->support_ic_type == ODM_RTL8703B)
2645                 READ_AND_CONFIG_MP(8703b, _mac_reg);
2646 #endif
2647 #if (RTL8188F_SUPPORT == 1)
2648         if (p_dm_odm->support_ic_type == ODM_RTL8188F)
2649                 READ_AND_CONFIG_MP(8188f, _mac_reg);
2650 #endif
2651 #if (RTL8822B_SUPPORT == 1)
2652         if (p_dm_odm->support_ic_type == ODM_RTL8822B)
2653                 READ_AND_CONFIG_MP(8822b, _mac_reg);
2654 #endif
2655
2656 #if (RTL8197F_SUPPORT == 1)
2657         if (p_dm_odm->support_ic_type == ODM_RTL8197F)
2658                 READ_AND_CONFIG_MP(8197f, _mac_reg);
2659 #endif
2660
2661 #if (RTL8821C_SUPPORT == 1)
2662         if (p_dm_odm->support_ic_type == ODM_RTL8821C)
2663                 READ_AND_CONFIG(8821c, _mac_reg);
2664 #endif
2665
2666 #if (RTL8195A_SUPPORT == 1)
2667         if (p_dm_odm->support_ic_type == ODM_RTL8195A)
2668                 READ_AND_CONFIG_MP(8195a, _mac_reg);
2669 #endif
2670
2671         return HAL_STATUS_SUCCESS;
2672 }
2673
2674 enum hal_status
2675 odm_config_fw_with_header_file(
2676         struct PHY_DM_STRUCT                    *p_dm_odm,
2677         enum odm_fw_config_type config_type,
2678         u8                              *p_firmware,
2679         u32                             *p_size
2680 )
2681 {
2682 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
2683
2684 #if (RTL8188E_SUPPORT == 1)
2685         if (p_dm_odm->support_ic_type == ODM_RTL8188E) {
2686 #ifdef CONFIG_SFW_SUPPORTED
2687                 if (config_type == CONFIG_FW_NIC)
2688                         READ_FIRMWARE_MP(8188e_t, _fw_nic);
2689                 else if (config_type == CONFIG_FW_WOWLAN)
2690                         READ_FIRMWARE_MP(8188e_t, _fw_wowlan);
2691                 else if (config_type == CONFIG_FW_NIC_2)
2692                         READ_FIRMWARE_MP(8188e_s, _fw_nic);
2693                 else if (config_type == CONFIG_FW_WOWLAN_2)
2694                         READ_FIRMWARE_MP(8188e_s, _fw_wowlan);
2695 #ifdef CONFIG_AP_WOWLAN
2696                 if (config_type == CONFIG_FW_AP)
2697                         READ_FIRMWARE_MP(8188e_t, _fw_ap);
2698                 else if (config_type == CONFIG_FW_AP_2)
2699                         READ_FIRMWARE_MP(8188e_s, _fw_ap);
2700 #endif /* CONFIG_AP_WOWLAN */
2701 #else
2702                 if (config_type == CONFIG_FW_NIC)
2703                         READ_FIRMWARE_MP(8188e_t, _fw_nic);
2704                 else if (config_type == CONFIG_FW_WOWLAN)
2705                         READ_FIRMWARE_MP(8188e_t, _fw_wowlan);
2706 #ifdef CONFIG_AP_WOWLAN
2707                 else if (config_type == CONFIG_FW_AP)
2708                         READ_FIRMWARE_MP(8188e_t, _fw_ap);
2709 #endif /* CONFIG_AP_WOWLAN */
2710 #endif
2711         }
2712 #endif
2713 #if (RTL8723B_SUPPORT == 1)
2714         if (p_dm_odm->support_ic_type == ODM_RTL8723B) {
2715                 if (config_type == CONFIG_FW_NIC)
2716                         READ_FIRMWARE_MP(8723b, _fw_nic);
2717                 else if (config_type == CONFIG_FW_WOWLAN)
2718                         READ_FIRMWARE_MP(8723b, _fw_wowlan);
2719 #ifdef CONFIG_AP_WOWLAN
2720                 else if (config_type == config_fw_ap_wowlan)
2721                         READ_FIRMWARE(8723b, _fw_ap);
2722 #endif
2723
2724         }
2725 #endif /* #if (RTL8723B_SUPPORT == 1) */
2726 #if (RTL8812A_SUPPORT == 1)
2727         if (p_dm_odm->support_ic_type == ODM_RTL8812) {
2728                 if (config_type == CONFIG_FW_NIC)
2729                         READ_FIRMWARE_MP(8812a, _fw_nic);
2730                 else if (config_type == CONFIG_FW_WOWLAN)
2731                         READ_FIRMWARE_MP(8812a, _fw_wowlan);
2732                 else if (config_type == CONFIG_FW_BT)
2733                         READ_FIRMWARE_MP(8812a, _fw_nic_bt);
2734 #ifdef CONFIG_AP_WOWLAN
2735                 else if (config_type == config_fw_ap_wowlan)
2736                         READ_FIRMWARE(8812a, _fw_ap);
2737 #endif
2738         }
2739 #endif
2740 #if (RTL8821A_SUPPORT == 1)
2741         if (p_dm_odm->support_ic_type == ODM_RTL8821) {
2742                 if (config_type == CONFIG_FW_NIC)
2743                         READ_FIRMWARE_MP(8821a, _fw_nic);
2744                 else if (config_type == CONFIG_FW_WOWLAN)
2745                         READ_FIRMWARE_MP(8821a, _fw_wowlan);
2746 #ifdef CONFIG_AP_WOWLAN
2747                 else if (config_type == config_fw_ap_wowlan)
2748                         READ_FIRMWARE_MP(8821a, _fw_ap);
2749 #endif /*CONFIG_AP_WOWLAN*/
2750                 else if (config_type == CONFIG_FW_BT)
2751                         READ_FIRMWARE_MP(8821a, _fw_nic_bt);
2752         }
2753 #endif
2754 #if (RTL8192E_SUPPORT == 1)
2755         if (p_dm_odm->support_ic_type == ODM_RTL8192E) {
2756                 if (config_type == CONFIG_FW_NIC)
2757                         READ_FIRMWARE_MP(8192e, _fw_nic);
2758                 else if (config_type == CONFIG_FW_WOWLAN)
2759                         READ_FIRMWARE_MP(8192e, _fw_wowlan);
2760 #ifdef CONFIG_AP_WOWLAN
2761                 else if (config_type == config_fw_ap_wowlan)
2762                         READ_FIRMWARE_MP(8192e, _fw_ap);
2763 #endif
2764         }
2765 #endif
2766 #if (RTL8723D_SUPPORT == 1)
2767         if (p_dm_odm->support_ic_type == ODM_RTL8723D) {
2768                 if (config_type == CONFIG_FW_NIC)
2769                         READ_FIRMWARE_MP(8723d, _fw_nic);
2770                 else if (config_type == CONFIG_FW_WOWLAN) {
2771                         READ_FIRMWARE_MP(8723d, _fw_wowlan);
2772 #ifdef CONFIG_AP_WOWLAN
2773                         else if (config_type == config_fw_ap_wowlan)
2774                                 READ_FIRMWARE_MP(8723d, _fw_ap);
2775 #endif
2776                 }
2777         }
2778 #endif
2779 /* JJ ADD 20161014 */
2780 #if (RTL8710B_SUPPORT == 1)
2781                 if (p_dm_odm->support_ic_type == ODM_RTL8710B) {
2782                         if (config_type == CONFIG_FW_NIC)
2783                                 READ_FIRMWARE_MP(8710b, _fw_nic);
2784                         else if (config_type == CONFIG_FW_WOWLAN) {
2785                                 READ_FIRMWARE_MP(8710b, _fw_wowlan);
2786 #ifdef CONFIG_AP_WOWLAN
2787                                 else if (config_type == config_fw_ap_wowlan)
2788                                         READ_FIRMWARE_MP(8710b, _fw_ap);
2789 #endif
2790                         }
2791                 }
2792 #endif
2793
2794         /*#if (RTL8814A_SUPPORT == 1)
2795                 if (p_dm_odm->support_ic_type == ODM_RTL8814A)
2796                 {
2797                         if (config_type == CONFIG_FW_NIC)
2798                                 READ_FIRMWARE_MP(8814a, _fw_nic);
2799                         else if (config_type == config_fw_wowlan)
2800                                 READ_FIRMWARE_MP(8814a, _fw_wowlan);
2801                         #ifdef CONFIG_AP_WOWLAN
2802                         else if (config_type == config_fw_ap_wowlan)
2803                                 READ_FIRMWARE_MP(8814a, _fw_ap);
2804                         #endif
2805                 }
2806         #endif */
2807
2808 #if (RTL8814A_SUPPORT == 1)
2809         if (p_dm_odm->support_ic_type == ODM_RTL8814A) {
2810                 if (config_type == CONFIG_FW_NIC)
2811                         READ_FIRMWARE_MP(8814a, _fw_nic);
2812 #ifdef CONFIG_AP_WOWLAN
2813                 else if (config_type == config_fw_ap_wowlan)
2814                         READ_FIRMWARE_MP(8814a, _fw_ap);
2815 #endif
2816         }
2817 #endif
2818
2819 #if (RTL8703B_SUPPORT == 1)
2820         if (p_dm_odm->support_ic_type == ODM_RTL8703B) {
2821                 if (config_type == CONFIG_FW_NIC)
2822                         READ_FIRMWARE_MP(8703b, _fw_nic);
2823                 else if (config_type == CONFIG_FW_WOWLAN)
2824                         READ_FIRMWARE_MP(8703b, _fw_wowlan);
2825 #ifdef CONFIG_AP_WOWLAN
2826                 else if (config_type == config_fw_ap_wowlan)
2827                         READ_FIRMWARE(8703b, _fw_ap);
2828 #endif
2829         }
2830 #endif
2831
2832 #if (RTL8188F_SUPPORT == 1)
2833         if (p_dm_odm->support_ic_type == ODM_RTL8188F) {
2834                 if (config_type == CONFIG_FW_NIC)
2835                         READ_FIRMWARE_MP(8188f, _fw_nic);
2836                 else if (config_type == CONFIG_FW_WOWLAN)
2837                         READ_FIRMWARE_MP(8188f, _fw_wowlan);
2838 #ifdef CONFIG_AP_WOWLAN
2839                 else if (config_type == CONFIG_FW_AP)
2840                         READ_FIRMWARE_MP(8188f, _fw_ap);
2841 #endif
2842         }
2843 #endif
2844
2845 #if (RTL8822B_SUPPORT == 1)
2846         if (p_dm_odm->support_ic_type == ODM_RTL8822B) {
2847
2848                 if (config_type == CONFIG_FW_NIC)
2849                         READ_FIRMWARE_MP(8822b, _fw_nic);
2850                 else if (config_type == CONFIG_FW_WOWLAN)
2851                         READ_FIRMWARE_MP(8822b, _fw_wowlan);
2852 #ifdef CONFIG_AP_WOWLAN
2853                 else if (config_type == config_fw_ap_wowlan)
2854                         READ_FIRMWARE(8822b, _fw_ap);
2855 #endif
2856         }
2857 #endif
2858
2859 #if (RTL8197F_SUPPORT == 1)
2860         if (p_dm_odm->support_ic_type == ODM_RTL8197F) {
2861                 if (config_type == CONFIG_FW_NIC)
2862                         READ_FIRMWARE_MP(8197f, _fw_nic);
2863 #ifdef CONFIG_AP_WOWLAN
2864                 else if (config_type == config_fw_ap_wowlan)
2865                         READ_FIRMWARE(8197f, _fw_ap);
2866 #endif
2867         }
2868 #endif
2869
2870 #if ((DM_ODM_SUPPORT_TYPE == ODM_WIN))
2871 #if (RTL8821C_SUPPORT == 1)
2872         if (p_dm_odm->support_ic_type == ODM_RTL8821C) {
2873                 if (config_type == CONFIG_FW_NIC)
2874                         READ_FIRMWARE_MP(8821c, _fw_nic);
2875                 else if (config_type == CONFIG_FW_WOWLAN)
2876                         READ_FIRMWARE_MP(8821c, _fw_wowlan);
2877 #ifdef CONFIG_AP_WOWLAN
2878                 else if (config_type == config_fw_ap_wowlan)
2879                         READ_FIRMWARE_MP(8821c, _fw_ap);
2880 #endif /*CONFIG_AP_WOWLAN*/
2881         }
2882 #endif
2883 #endif
2884
2885 #endif/* (DM_ODM_SUPPORT_TYPE != ODM_AP) */
2886         return HAL_STATUS_SUCCESS;
2887 }
2888
2889 u32
2890 odm_get_hw_img_version(
2891         struct PHY_DM_STRUCT    *p_dm_odm
2892 )
2893 {
2894         u32  version = 0;
2895
2896         /* 1 AP doesn't use PHYDM initialization in these ICs */
2897 #if (DM_ODM_SUPPORT_TYPE != ODM_AP)
2898 #if (RTL8821A_SUPPORT == 1)
2899         if (p_dm_odm->support_ic_type == ODM_RTL8821)
2900                 version = GET_VERSION_MP(8821a, _mac_reg);
2901 #endif
2902 #if (RTL8192E_SUPPORT == 1)
2903         if (p_dm_odm->support_ic_type == ODM_RTL8192E)
2904                 version = GET_VERSION_MP(8192e, _mac_reg);
2905 #endif
2906 #if (RTL8812A_SUPPORT == 1)
2907         if (p_dm_odm->support_ic_type == ODM_RTL8812)
2908                 version = GET_VERSION_MP(8812a, _mac_reg);
2909 #endif
2910 #if (RTL8723D_SUPPORT == 1)
2911         if (p_dm_odm->support_ic_type == ODM_RTL8723D)
2912                 version = GET_VERSION_MP(8723d, _mac_reg);
2913 #endif
2914 /* JJ ADD 20161014 */
2915 #if (RTL8710B_SUPPORT == 1)
2916         if (p_dm_odm->support_ic_type == ODM_RTL8710B)
2917                 version = GET_VERSION_MP(8710b, _mac_reg);
2918 #endif
2919
2920 #endif /* (DM_ODM_SUPPORT_TYPE != ODM_AP) */
2921
2922         /*1 All platforms support*/
2923 #if (RTL8188E_SUPPORT == 1)
2924         if (p_dm_odm->support_ic_type == ODM_RTL8188E)
2925                 version = GET_VERSION_MP(8188e, _mac_reg);
2926 #endif
2927 #if (RTL8723B_SUPPORT == 1)
2928         if (p_dm_odm->support_ic_type == ODM_RTL8723B)
2929                 version = GET_VERSION_MP(8723b, _mac_reg);
2930 #endif
2931 #if (RTL8814A_SUPPORT == 1)
2932         if (p_dm_odm->support_ic_type == ODM_RTL8814A)
2933                 version = GET_VERSION_MP(8814a, _mac_reg);
2934 #endif
2935 #if (RTL8703B_SUPPORT == 1)
2936         if (p_dm_odm->support_ic_type == ODM_RTL8703B)
2937                 version = GET_VERSION_MP(8703b, _mac_reg);
2938 #endif
2939 #if (RTL8188F_SUPPORT == 1)
2940         if (p_dm_odm->support_ic_type == ODM_RTL8188F)
2941                 version = GET_VERSION_MP(8188f, _mac_reg);
2942 #endif
2943 #if (RTL8822B_SUPPORT == 1)
2944         if (p_dm_odm->support_ic_type == ODM_RTL8822B)
2945                 version = GET_VERSION_MP(8822b, _mac_reg);
2946 #endif
2947
2948 #if (RTL8197F_SUPPORT == 1)
2949         if (p_dm_odm->support_ic_type == ODM_RTL8197F)
2950                 version = GET_VERSION_MP(8197f, _mac_reg);
2951 #endif
2952
2953 #if (RTL8821C_SUPPORT == 1)
2954         if (p_dm_odm->support_ic_type == ODM_RTL8821C)
2955                 version = GET_VERSION(8821c, _mac_reg);
2956 #endif
2957
2958         return version;
2959 }
2960
2961 #if (ODM_PHY_STATUS_NEW_TYPE_SUPPORT == 1)
2962 /* For 8822B only!! need to move to FW finally */
2963 /*==============================================*/
2964
2965 boolean
2966 phydm_query_is_mu_api(
2967         struct PHY_DM_STRUCT                                    *p_phydm,
2968         u8                                                      ppdu_idx,
2969         u8                                                      *p_data_rate,
2970         u8                                                      *p_gid
2971 )
2972 {
2973         u8      data_rate = 0, gid = 0;
2974         boolean is_mu = FALSE;
2975
2976         data_rate = p_phydm->phy_dbg_info.num_of_ppdu[ppdu_idx];
2977         gid = p_phydm->phy_dbg_info.gid_num[ppdu_idx];
2978
2979         if (data_rate & BIT(7)) {
2980                 is_mu = TRUE;
2981                 data_rate = data_rate & ~(BIT(7));
2982         } else
2983                 is_mu = FALSE;
2984
2985         *p_data_rate = data_rate;
2986         *p_gid = gid;
2987
2988         return is_mu;
2989
2990 }
2991
2992 VOID
2993 phydm_rx_statistic_cal(
2994         struct PHY_DM_STRUCT                            *p_phydm,
2995         u8                                                                      *p_phy_status,
2996         struct _odm_per_pkt_info_                               *p_pktinfo
2997 )
2998 {
2999         struct _phy_status_rpt_jaguar2_type1    *p_phy_sta_rpt = (struct _phy_status_rpt_jaguar2_type1 *)p_phy_status;
3000         u8                                                                      date_rate = p_pktinfo->data_rate & ~(BIT(7));
3001
3002         if ((p_phy_sta_rpt->gid != 0) && (p_phy_sta_rpt->gid != 63)) {
3003                 if (date_rate >= ODM_RATEVHTSS1MCS0) {
3004                         p_phydm->phy_dbg_info.num_qry_mu_vht_pkt[date_rate - 0x2C]++;
3005                         p_phydm->phy_dbg_info.num_of_ppdu[p_pktinfo->ppdu_cnt] = date_rate | BIT(7);
3006                         p_phydm->phy_dbg_info.gid_num[p_pktinfo->ppdu_cnt] = p_phy_sta_rpt->gid;
3007                 }
3008
3009         } else {
3010                 if (date_rate >= ODM_RATEVHTSS1MCS0) {
3011                         p_phydm->phy_dbg_info.num_qry_vht_pkt[date_rate - 0x2C]++;
3012                         p_phydm->phy_dbg_info.num_of_ppdu[p_pktinfo->ppdu_cnt] = date_rate;
3013                         p_phydm->phy_dbg_info.gid_num[p_pktinfo->ppdu_cnt] = p_phy_sta_rpt->gid;
3014                 }
3015         }
3016
3017 }
3018
3019 void
3020 phydm_reset_phy_info(
3021         struct PHY_DM_STRUCT                                    *p_phydm,
3022         struct _odm_phy_status_info_                    *p_phy_info
3023 )
3024 {
3025         p_phy_info->rx_pwdb_all = 0;
3026         p_phy_info->signal_quality = 0;
3027         p_phy_info->band_width = 0;
3028         p_phy_info->rx_count = 0;
3029         odm_memory_set(p_phydm, p_phy_info->rx_mimo_signal_quality, 0, 4);
3030         odm_memory_set(p_phydm, p_phy_info->rx_mimo_signal_strength, 0, 4);
3031         odm_memory_set(p_phydm, p_phy_info->rx_snr, 0, 4);
3032
3033 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
3034         p_phy_info->rx_power = -110;
3035         p_phy_info->recv_signal_power = -110;
3036         p_phy_info->bt_rx_rssi_percentage = 0;
3037         p_phy_info->signal_strength = 0;
3038         p_phy_info->bt_coex_pwr_adjust = 0;
3039         p_phy_info->channel = 0;
3040         p_phy_info->is_mu_packet = 0;
3041         p_phy_info->is_beamformed = 0;
3042         p_phy_info->rxsc = 0;
3043         odm_memory_set(p_phydm, p_phy_info->rx_pwr, -110, 4);
3044         odm_memory_set(p_phydm, p_phy_info->rx_mimo_evm_dbm, 0, 4);
3045         odm_memory_set(p_phydm, p_phy_info->cfo_short, 0, 8);
3046         odm_memory_set(p_phydm, p_phy_info->cfo_tail, 0, 8);
3047 #endif
3048 }
3049
3050 void
3051 phydm_set_per_path_phy_info(
3052         u8                                                      rx_path,
3053         s8                                                      rx_pwr,
3054         s8                                                      rx_evm,
3055         s8                                                      cfo_tail,
3056         s8                                                      rx_snr,
3057         struct _odm_phy_status_info_                            *p_phy_info
3058 )
3059 {
3060         u8                      evm_dbm = 0;
3061         u8                      evm_percentage = 0;
3062
3063         /* SNR is S(8,1), EVM is S(8,1), CFO is S(8,7) */
3064
3065         if (rx_evm < 0) {
3066                 /* Calculate EVM in dBm */
3067                 evm_dbm = ((u8)(0 - rx_evm) >> 1);
3068
3069                 /* Calculate EVM in percentage */
3070                 if (evm_dbm >= 33)
3071                         evm_percentage = 100;
3072                 else
3073                         evm_percentage = (evm_dbm << 1) + (evm_dbm);
3074         }
3075
3076
3077 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
3078         p_phy_info->rx_pwr[rx_path] = rx_pwr;
3079         p_phy_info->rx_mimo_evm_dbm[rx_path] = evm_dbm;
3080
3081         /* CFO = CFO_tail * 312.5 / 2^7 ~= CFO tail * 39/512 (kHz)*/
3082         p_phy_info->cfo_tail[rx_path] = cfo_tail;
3083         p_phy_info->cfo_tail[rx_path] = ((p_phy_info->cfo_tail[rx_path] << 5) + (p_phy_info->cfo_tail[rx_path] << 2) +
3084                 (p_phy_info->cfo_tail[rx_path] << 1) + (p_phy_info->cfo_tail[rx_path])) >> 9;
3085 #endif
3086
3087         p_phy_info->rx_mimo_signal_strength[rx_path] = odm_query_rx_pwr_percentage(rx_pwr);
3088         p_phy_info->rx_mimo_signal_quality[rx_path] = evm_percentage;
3089         p_phy_info->rx_snr[rx_path] = rx_snr >> 1;
3090
3091 #if 0
3092         /* if (p_pktinfo->is_packet_match_bssid) */
3093         {
3094                 dbg_print("path (%d)--------\n", rx_path);
3095                 dbg_print("rx_pwr = %d, Signal strength = %d\n", p_phy_info->rx_pwr[rx_path], p_phy_info->rx_mimo_signal_strength[rx_path]);
3096                 dbg_print("evm_dbm = %d, Signal quality = %d\n", p_phy_info->rx_mimo_evm_dbm[rx_path], p_phy_info->rx_mimo_signal_quality[rx_path]);
3097                 dbg_print("CFO = %d, SNR = %d\n", p_phy_info->cfo_tail[rx_path], p_phy_info->rx_snr[rx_path]);
3098         }
3099 #endif
3100 }
3101
3102 void
3103 phydm_set_common_phy_info(
3104         s8                                                      rx_power,
3105         u8                                                      channel,
3106         boolean                                                 is_beamformed,
3107         boolean                                                 is_mu_packet,
3108         u8                                                      bandwidth,
3109         u8                                                      signal_quality,
3110         u8                                                      rxsc,
3111         struct _odm_phy_status_info_                            *p_phy_info
3112 )
3113 {
3114 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
3115         p_phy_info->rx_power = rx_power;                                                                                        /* RSSI in dB */
3116         p_phy_info->recv_signal_power = rx_power;                                                                               /* RSSI in dB */
3117         p_phy_info->channel = channel;                                                                                          /* channel number */
3118         p_phy_info->is_beamformed = is_beamformed;                                                                      /* apply BF */
3119         p_phy_info->is_mu_packet = is_mu_packet;                                                                                /* MU packet */
3120         p_phy_info->rxsc = rxsc;
3121 #endif
3122         p_phy_info->rx_pwdb_all = odm_query_rx_pwr_percentage(rx_power);                                /* RSSI in percentage */
3123         p_phy_info->signal_quality = signal_quality;                                                                            /* signal quality */
3124         p_phy_info->band_width = bandwidth;                                                                                     /* bandwidth */
3125
3126 #if 0
3127         /* if (p_pktinfo->is_packet_match_bssid) */
3128         {
3129                 dbg_print("rx_pwdb_all = %d, rx_power = %d, recv_signal_power = %d\n", p_phy_info->rx_pwdb_all, p_phy_info->rx_power, p_phy_info->recv_signal_power);
3130                 dbg_print("signal_quality = %d\n", p_phy_info->signal_quality);
3131                 dbg_print("is_beamformed = %d, is_mu_packet = %d, rx_count = %d\n", p_phy_info->is_beamformed, p_phy_info->is_mu_packet, p_phy_info->rx_count + 1);
3132                 dbg_print("channel = %d, rxsc = %d, band_width = %d\n", channel, rxsc, bandwidth);
3133         }
3134 #endif
3135 }
3136
3137 void
3138 phydm_get_rx_phy_status_type0(
3139         struct PHY_DM_STRUCT                                            *p_dm_odm,
3140         u8                                                      *p_phy_status,
3141         struct _odm_per_pkt_info_                               *p_pktinfo,
3142         struct _odm_phy_status_info_                            *p_phy_info
3143 )
3144 {
3145         /* type 0 is used for cck packet */
3146
3147         struct _phy_status_rpt_jaguar2_type0    *p_phy_sta_rpt = (struct _phy_status_rpt_jaguar2_type0 *)p_phy_status;
3148         u8                                                      i, SQ = 0;
3149         s8                                                      rx_power = p_phy_sta_rpt->pwdb - 110;
3150
3151
3152 #if (RTL8723D_SUPPORT == 1)
3153         if (p_dm_odm->support_ic_type & ODM_RTL8723D)
3154                 rx_power = p_phy_sta_rpt->pwdb - 97;
3155 #endif
3156 /* JJ ADD 20161014 */
3157 #if (RTL8710B_SUPPORT == 1)
3158         if (p_dm_odm->support_ic_type & ODM_RTL8710B)
3159                 rx_power = p_phy_sta_rpt->pwdb - 97;
3160 #endif
3161
3162 #if (RTL8197F_SUPPORT == 1)
3163         if (p_dm_odm->support_ic_type & ODM_RTL8197F)
3164                 rx_power = p_phy_sta_rpt->pwdb - 97;
3165 #endif
3166 #if (RTL8821C_SUPPORT == 1)
3167         if (p_dm_odm->support_ic_type & ODM_RTL8821C) {
3168                 if (p_phy_sta_rpt->pwdb >= -57)
3169                         rx_power = p_phy_sta_rpt->pwdb - 100;
3170                 else
3171                         rx_power = p_phy_sta_rpt->pwdb - 102;
3172         }
3173 #endif
3174         /* Calculate Signal Quality*/
3175         if (p_pktinfo->is_packet_match_bssid) {
3176                 if (p_phy_sta_rpt->signal_quality >= 64)
3177                         SQ = 0;
3178                 else if (p_phy_sta_rpt->signal_quality <= 20)
3179                         SQ = 100;
3180                 else {
3181                         /* mapping to 2~99% */
3182                         SQ = 64 - p_phy_sta_rpt->signal_quality;
3183                         SQ = ((SQ << 3) + SQ) >> 2;
3184                 }
3185         }
3186
3187         /* Modify CCK PWDB if old AGC */
3188         if (p_dm_odm->cck_new_agc == false) {
3189                 u8      lna_idx, vga_idx;
3190
3191 #if (RTL8197F_SUPPORT == 1)
3192                 if (p_dm_odm->support_ic_type & ODM_RTL8197F)
3193                         lna_idx = p_phy_sta_rpt->lna_l;
3194                 else
3195 #endif
3196                         lna_idx = ((p_phy_sta_rpt->lna_h << 3) | p_phy_sta_rpt->lna_l);
3197                 vga_idx = p_phy_sta_rpt->vga;
3198
3199 #if (RTL8723D_SUPPORT == 1)
3200                 if (p_dm_odm->support_ic_type & ODM_RTL8723D)
3201                         rx_power = odm_cckrssi_8723d(lna_idx, vga_idx);
3202 #endif
3203 /* JJ ADD 20161014 */
3204 #if (RTL8710B_SUPPORT == 1)
3205                 if (p_dm_odm->support_ic_type & ODM_RTL8710B)
3206                         rx_power = odm_cckrssi_8710b(lna_idx, vga_idx);
3207 #endif
3208
3209 #if (RTL8822B_SUPPORT == 1)
3210                 /* Need to do !! */
3211                 /*if (p_dm_odm->support_ic_type & ODM_RTL8822B) */
3212                 /*rx_power = odm_CCKRSSI_8822B(LNA_idx, VGA_idx);*/
3213 #endif
3214 #if (RTL8197F_SUPPORT == 1)
3215                 if (p_dm_odm->support_ic_type & ODM_RTL8197F)
3216                         rx_power = odm_cckrssi_8197f(p_dm_odm, lna_idx, vga_idx);
3217 #endif
3218         }
3219
3220         /* Update CCK packet counter */
3221         p_dm_odm->phy_dbg_info.num_qry_phy_status_cck++;
3222
3223         /*CCK no STBC and LDPC*/
3224         p_dm_odm->phy_dbg_info.is_ldpc_pkt = false;
3225         p_dm_odm->phy_dbg_info.is_stbc_pkt = false;
3226
3227         /* Update Common information */
3228         phydm_set_common_phy_info(rx_power, p_phy_sta_rpt->channel, false,
3229                   false, ODM_BW20M, SQ, p_phy_sta_rpt->rxsc, p_phy_info);
3230
3231         /* Update CCK pwdb */
3232         phydm_set_per_path_phy_info(ODM_RF_PATH_A, rx_power, 0, 0, 0, p_phy_info);                                      /* Update per-path information */
3233
3234         p_dm_odm->dm_fat_table.antsel_rx_keep_0 = p_phy_sta_rpt->antidx_a;
3235         p_dm_odm->dm_fat_table.antsel_rx_keep_1 = p_phy_sta_rpt->antidx_b;
3236         p_dm_odm->dm_fat_table.antsel_rx_keep_2 = p_phy_sta_rpt->antidx_c;
3237         p_dm_odm->dm_fat_table.antsel_rx_keep_3 = p_phy_sta_rpt->antidx_d;
3238 #if 0
3239         /* if (p_pktinfo->is_packet_match_bssid) */
3240         {
3241                 dbg_print("pwdb = 0x%x, MP gain index = 0x%x, TRSW = 0x%x\n", p_phy_sta_rpt->pwdb, p_phy_sta_rpt->gain, p_phy_sta_rpt->trsw);
3242                 dbg_print("channel = %d, band = %d, rxsc = %d\n", p_phy_sta_rpt->channel, p_phy_sta_rpt->band, p_phy_sta_rpt->rxsc);
3243                 dbg_print("agc_table = 0x%x, agc_rpt 0x%x, bb_power = 0x%x\n", p_phy_sta_rpt->agc_table, p_phy_sta_rpt->agc_rpt, p_phy_sta_rpt->bb_power);
3244                 dbg_print("length = %d, SQ = %d\n", p_phy_sta_rpt->length, p_phy_sta_rpt->signal_quality);
3245                 dbg_print("antidx a = 0x%x, b = 0x%x, c = 0x%x, d = 0x%x\n", p_phy_sta_rpt->antidx_a, p_phy_sta_rpt->antidx_b, p_phy_sta_rpt->antidx_c, p_phy_sta_rpt->antidx_d);
3246                 dbg_print("rsvd_0 = 0x%x, rsvd_1 = 0x%x, rsvd_2 = 0x%x\n", p_phy_sta_rpt->rsvd_0, p_phy_sta_rpt->rsvd_1, p_phy_sta_rpt->rsvd_2);
3247                 dbg_print("rsvd_3 = 0x%x, rsvd_4 = 0x%x, rsvd_5 = 0x%x\n", p_phy_sta_rpt->rsvd_3, p_phy_sta_rpt->rsvd_4, p_phy_sta_rpt->rsvd_5);
3248                 dbg_print("rsvd_6 = 0x%x, rsvd_7 = 0x%x, rsvd_8 = 0x%x\n", p_phy_sta_rpt->rsvd_6, p_phy_sta_rpt->rsvd_7, p_phy_sta_rpt->rsvd_8);
3249         }
3250 #endif
3251 }
3252
3253 void
3254 phydm_get_rx_phy_status_type1(
3255         struct PHY_DM_STRUCT                                            *p_dm_odm,
3256         u8                                                      *p_phy_status,
3257         struct _odm_per_pkt_info_                               *p_pktinfo,
3258         struct _odm_phy_status_info_                            *p_phy_info
3259 )
3260 {
3261         /* type 1 is used for ofdm packet */
3262
3263         struct _phy_status_rpt_jaguar2_type1    *p_phy_sta_rpt = (struct _phy_status_rpt_jaguar2_type1 *)p_phy_status;
3264         s8                                                      rx_pwr_db = -120;
3265         u8                                                      i, rxsc, bw = ODM_BW20M, rx_count = 0;
3266         boolean                                                 is_mu;
3267         u8                                                      num_ss;
3268
3269         /* Update OFDM packet counter */
3270         p_dm_odm->phy_dbg_info.num_qry_phy_status_ofdm++;
3271
3272         /* Update per-path information */
3273         for (i = ODM_RF_PATH_A; i < ODM_RF_PATH_MAX_JAGUAR; i++) {
3274                 if (p_dm_odm->rx_ant_status & BIT(i)) {
3275                         s8      rx_path_pwr_db;
3276
3277                         /* RX path counter */
3278                         rx_count++;
3279
3280                         /* Update per-path information (RSSI_dB RSSI_percentage EVM SNR CFO SQ) */
3281                         /* EVM report is reported by stream, not path */
3282                         rx_path_pwr_db = p_phy_sta_rpt->pwdb[i] - 110;                                  /* per-path pwdb in dB domain */
3283                         phydm_set_per_path_phy_info(i, rx_path_pwr_db, p_phy_sta_rpt->rxevm[rx_count - 1],
3284                                 p_phy_sta_rpt->cfo_tail[i], p_phy_sta_rpt->rxsnr[i], p_phy_info);
3285
3286                         /* search maximum pwdb */
3287                         if (rx_path_pwr_db > rx_pwr_db)
3288                                 rx_pwr_db = rx_path_pwr_db;
3289                 }
3290         }
3291
3292         /* mapping RX counter from 1~4 to 0~3 */
3293         if (rx_count > 0)
3294                 p_phy_info->rx_count = rx_count - 1;
3295
3296         /* Check if MU packet or not */
3297         if ((p_phy_sta_rpt->gid != 0) && (p_phy_sta_rpt->gid != 63)) {
3298                 is_mu = true;
3299                 p_dm_odm->phy_dbg_info.num_qry_mu_pkt++;
3300         } else
3301                 is_mu = false;
3302
3303         /* count BF packet */
3304         p_dm_odm->phy_dbg_info.num_qry_bf_pkt = p_dm_odm->phy_dbg_info.num_qry_bf_pkt + p_phy_sta_rpt->beamformed;
3305
3306         /*STBC or LDPC pkt*/
3307         p_dm_odm->phy_dbg_info.is_ldpc_pkt = p_phy_sta_rpt->ldpc;
3308         p_dm_odm->phy_dbg_info.is_stbc_pkt = p_phy_sta_rpt->stbc;
3309
3310         /* Check sub-channel */
3311         if ((p_pktinfo->data_rate > ODM_RATE11M) && (p_pktinfo->data_rate < ODM_RATEMCS0))
3312                 rxsc = p_phy_sta_rpt->l_rxsc;
3313         else
3314                 rxsc = p_phy_sta_rpt->ht_rxsc;
3315
3316         /* Check RX bandwidth */
3317         if (p_dm_odm->support_ic_type & ODM_RTL8822B) {
3318                 if ((rxsc >= 1) && (rxsc <= 8))
3319                         bw = ODM_BW20M;
3320                 else if ((rxsc >= 9) && (rxsc <= 12))
3321                         bw = ODM_BW40M;
3322                 else if (rxsc >= 13)
3323                         bw = ODM_BW80M;
3324                 else
3325                         bw = p_phy_sta_rpt->rf_mode;
3326         } else if (p_dm_odm->support_ic_type & (ODM_RTL8197F | ODM_RTL8723D | ODM_RTL8710B)) {/* JJ ADD 20161014 */
3327                 if (p_phy_sta_rpt->rf_mode == 0)
3328                         bw = ODM_BW20M;
3329                 else if ((rxsc == 1) || (rxsc == 2))
3330                         bw = ODM_BW20M;
3331                 else
3332                         bw = ODM_BW40M;
3333         }
3334
3335         /* Update packet information */
3336         phydm_set_common_phy_info(rx_pwr_db, p_phy_sta_rpt->channel, (boolean)p_phy_sta_rpt->beamformed,
3337                 is_mu, bw, odm_evm_db_to_percentage(p_phy_sta_rpt->rxevm[0]), rxsc, p_phy_info);
3338
3339         num_ss = phydm_rate_to_num_ss(p_dm_odm, p_pktinfo->data_rate);
3340
3341         odm_parsing_cfo(p_dm_odm, p_pktinfo, p_phy_sta_rpt->cfo_tail, num_ss);
3342         p_dm_odm->dm_fat_table.antsel_rx_keep_0 = p_phy_sta_rpt->antidx_a;
3343         p_dm_odm->dm_fat_table.antsel_rx_keep_1 = p_phy_sta_rpt->antidx_b;
3344         p_dm_odm->dm_fat_table.antsel_rx_keep_2 = p_phy_sta_rpt->antidx_c;
3345         p_dm_odm->dm_fat_table.antsel_rx_keep_3 = p_phy_sta_rpt->antidx_d;
3346
3347         if (p_pktinfo->is_packet_match_bssid) {
3348                 /*
3349                                 dbg_print("channel = %d, band = %d, l_rxsc = %d, ht_rxsc = %d, rf_mode = %d\n", p_phy_sta_rpt->channel, p_phy_sta_rpt->band, p_phy_sta_rpt->l_rxsc, p_phy_sta_rpt->ht_rxsc, p_phy_sta_rpt->rf_mode);
3350                                 dbg_print("Antidx A = %d, B = %d, C = %d, D = %d\n", p_phy_sta_rpt->antidx_a, p_phy_sta_rpt->antidx_b, p_phy_sta_rpt->antidx_c, p_phy_sta_rpt->antidx_d);
3351                                 dbg_print("pwdb A: 0x%x, B: 0x%x, C: 0x%x, D: 0x%x\n", p_phy_sta_rpt->pwdb[0], p_phy_sta_rpt->pwdb[1], p_phy_sta_rpt->pwdb[2], p_phy_sta_rpt->pwdb[3]);
3352                                 dbg_print("EVM  A: %d, B: %d, C: %d, D: %d\n", p_phy_sta_rpt->rxevm[0], p_phy_sta_rpt->rxevm[1], p_phy_sta_rpt->rxevm[2], p_phy_sta_rpt->rxevm[3]);
3353                                 dbg_print("SNR  A: %d, B: %d, C: %d, D: %d\n", p_phy_sta_rpt->rxsnr[0], p_phy_sta_rpt->rxsnr[1], p_phy_sta_rpt->rxsnr[2], p_phy_sta_rpt->rxsnr[3]);
3354                                 dbg_print("CFO  A: %d, B: %d, C: %d, D: %d\n", p_phy_sta_rpt->cfo_tail[0], p_phy_sta_rpt->cfo_tail[1], p_phy_sta_rpt->cfo_tail[2], p_phy_sta_rpt->cfo_tail[3]);
3355                                 dbg_print("paid = %d, gid = %d, length = %d\n", (p_phy_sta_rpt->paid + (p_phy_sta_rpt->paid_msb<<8)), p_phy_sta_rpt->gid, p_phy_sta_rpt->lsig_length);
3356                                 dbg_print("ldpc: %d, stbc: %d, bf: %d, gnt_bt: %d, antsw: %d\n", p_phy_sta_rpt->ldpc, p_phy_sta_rpt->stbc, p_phy_sta_rpt->beamformed, p_phy_sta_rpt->gnt_bt, p_phy_sta_rpt->hw_antsw_occu);
3357                                 dbg_print("NBI: %d, pos: %d\n", p_phy_sta_rpt->nb_intf_flag, (p_phy_sta_rpt->intf_pos + (p_phy_sta_rpt->intf_pos_msb<<8)));
3358                                 dbg_print("rsvd_0 = %d, rsvd_1 = %d, rsvd_2 = %d, rsvd_3 = %d, rsvd_4 = %d, rsvd_5 = %d\n", p_phy_sta_rpt->rsvd_0, p_phy_sta_rpt->rsvd_1, p_phy_sta_rpt->rsvd_2, p_phy_sta_rpt->rsvd_3, p_phy_sta_rpt->rsvd_4, p_phy_sta_rpt->rsvd_5);
3359                 */
3360                 phydm_rx_statistic_cal(p_dm_odm, p_phy_status, p_pktinfo);
3361         }
3362         /*
3363                 dbg_print("phydm_get_rx_phy_status_type1   p_pktinfo->is_packet_match_bssid = %d\n", p_pktinfo->is_packet_match_bssid);
3364                 dbg_print("p_pktinfo->data_rate = 0x%x\n", p_pktinfo->data_rate);
3365         */
3366 }
3367
3368 void
3369 phydm_get_rx_phy_status_type2(
3370         struct PHY_DM_STRUCT                                            *p_dm_odm,
3371         u8                                                      *p_phy_status,
3372         struct _odm_per_pkt_info_                               *p_pktinfo,
3373         struct _odm_phy_status_info_                            *p_phy_info
3374 )
3375 {
3376         struct _phy_status_rpt_jaguar2_type2    *p_phy_sta_rpt = (struct _phy_status_rpt_jaguar2_type2 *)p_phy_status;
3377         s8                                                      rx_pwr_db = -120;
3378         u8                                                      i, rxsc, bw = ODM_BW20M, rx_count = 0;
3379
3380         /* Update OFDM packet counter */
3381         p_dm_odm->phy_dbg_info.num_qry_phy_status_ofdm++;
3382
3383         /* Update per-path information */
3384         for (i = ODM_RF_PATH_A; i < ODM_RF_PATH_MAX_JAGUAR; i++) {
3385                 if (p_dm_odm->rx_ant_status & BIT(i)) {
3386                         s8      rx_path_pwr_db;
3387
3388                         /* RX path counter */
3389                         rx_count++;
3390
3391                         /* Update per-path information (RSSI_dB RSSI_percentage EVM SNR CFO SQ) */
3392 #if (RTL8197F_SUPPORT == 1)
3393                         if ((p_dm_odm->support_ic_type & ODM_RTL8197F) && (p_phy_sta_rpt->pwdb[i] == 0x7f)) { /*for 97f workaround*/
3394
3395                                 if (i == ODM_RF_PATH_A) {
3396                                         rx_path_pwr_db = (p_phy_sta_rpt->gain_a) << 1;
3397                                         rx_path_pwr_db = rx_path_pwr_db - 110;
3398                                 } else if (i == ODM_RF_PATH_B) {
3399                                         rx_path_pwr_db = (p_phy_sta_rpt->gain_b) << 1;
3400                                         rx_path_pwr_db = rx_path_pwr_db - 110;
3401                                 } else
3402                                         rx_path_pwr_db = 0;
3403                         } else
3404 #endif
3405                                 rx_path_pwr_db = p_phy_sta_rpt->pwdb[i] - 110;                                  /* per-path pwdb in dB domain */
3406
3407                         phydm_set_per_path_phy_info(i, rx_path_pwr_db, 0, 0, 0, p_phy_info);
3408
3409                         /* search maximum pwdb */
3410                         if (rx_path_pwr_db > rx_pwr_db)
3411                                 rx_pwr_db = rx_path_pwr_db;
3412                 }
3413         }
3414
3415         /* mapping RX counter from 1~4 to 0~3 */
3416         if (rx_count > 0)
3417                 p_phy_info->rx_count = rx_count - 1;
3418
3419         /* Check RX sub-channel */
3420         if ((p_pktinfo->data_rate > ODM_RATE11M) && (p_pktinfo->data_rate < ODM_RATEMCS0))
3421                 rxsc = p_phy_sta_rpt->l_rxsc;
3422         else
3423                 rxsc = p_phy_sta_rpt->ht_rxsc;
3424
3425         /*STBC or LDPC pkt*/
3426         p_dm_odm->phy_dbg_info.is_ldpc_pkt = p_phy_sta_rpt->ldpc;
3427         p_dm_odm->phy_dbg_info.is_stbc_pkt = p_phy_sta_rpt->stbc;
3428
3429         /* Check RX bandwidth */
3430         /* the BW information of sc=0 is useless, because there is no information of RF mode*/
3431
3432         if (p_dm_odm->support_ic_type & ODM_RTL8822B) {
3433                 if ((rxsc >= 1) && (rxsc <= 8))
3434                         bw = ODM_BW20M;
3435                 else if ((rxsc >= 9) && (rxsc <= 12))
3436                         bw = ODM_BW40M;
3437                 else if (rxsc >= 13)
3438                         bw = ODM_BW80M;
3439                 else
3440                         bw = ODM_BW20M;
3441         } else if (p_dm_odm->support_ic_type & (ODM_RTL8197F | ODM_RTL8723D | ODM_RTL8710B)) {/* JJ ADD 20161014 */
3442                 if (rxsc == 3)
3443                         bw = ODM_BW40M;
3444                 else if ((rxsc == 1) || (rxsc == 2))
3445                         bw = ODM_BW20M;
3446                 else
3447                         bw = ODM_BW20M;
3448         }
3449
3450         /* Update packet information */
3451         phydm_set_common_phy_info(rx_pwr_db, p_phy_sta_rpt->channel, (boolean)p_phy_sta_rpt->beamformed,
3452                                   false, bw, 0, rxsc, p_phy_info);
3453
3454 #if 0
3455         /* if (p_pktinfo->is_packet_match_bssid) */
3456         {
3457                 dbg_print("channel = %d, band = %d, l_rxsc = %d, ht_rxsc = %d\n", p_phy_sta_rpt->channel, p_phy_sta_rpt->band, p_phy_sta_rpt->l_rxsc, p_phy_sta_rpt->ht_rxsc);
3458                 dbg_print("pwdb A: 0x%x, B: 0x%x, C: 0x%x, D: 0x%x\n", p_phy_sta_rpt->pwdb[0], p_phy_sta_rpt->pwdb[1], p_phy_sta_rpt->pwdb[2], p_phy_sta_rpt->pwdb[3]);
3459                 dbg_print("Agc table A: 0x%x, B: 0x%x, C: 0x%x, D: 0x%x\n", p_phy_sta_rpt->agc_table_a, p_phy_sta_rpt->agc_table_b, p_phy_sta_rpt->agc_table_c, p_phy_sta_rpt->agc_table_d);
3460                 dbg_print("Gain A: 0x%x, B: 0x%x, C: 0x%x, D: 0x%x\n", p_phy_sta_rpt->gain_a, p_phy_sta_rpt->gain_b, p_phy_sta_rpt->gain_c, p_phy_sta_rpt->gain_d);
3461                 dbg_print("TRSW A: 0x%x, B: 0x%x, C: 0x%x, D: 0x%x\n", p_phy_sta_rpt->trsw_a, p_phy_sta_rpt->trsw_b, p_phy_sta_rpt->trsw_c, p_phy_sta_rpt->trsw_d);
3462                 dbg_print("AAGC step A: 0x%x, B: 0x%x, C: 0x%x, D: 0x%x\n", p_phy_sta_rpt->aagc_step_a, p_phy_sta_rpt->aagc_step_b, p_phy_sta_rpt->aagc_step_c, p_phy_sta_rpt->aagc_step_d);
3463                 dbg_print("HT AAGC gain A: 0x%x, B: 0x%x, C: 0x%x, D: 0x%x\n", p_phy_sta_rpt->ht_aagc_gain[0], p_phy_sta_rpt->ht_aagc_gain[1], p_phy_sta_rpt->ht_aagc_gain[2], p_phy_sta_rpt->ht_aagc_gain[3]);
3464                 dbg_print("DAGC gain A: 0x%x, B: 0x%x, C: 0x%x, D: 0x%x\n", p_phy_sta_rpt->dagc_gain[0], p_phy_sta_rpt->dagc_gain[1], p_phy_sta_rpt->dagc_gain[2], p_phy_sta_rpt->dagc_gain[3]);
3465                 dbg_print("ldpc: %d, stbc: %d, bf: %d, gnt_bt: %d, antsw: %d\n", p_phy_sta_rpt->ldpc, p_phy_sta_rpt->stbc, p_phy_sta_rpt->beamformed, p_phy_sta_rpt->gnt_bt, p_phy_sta_rpt->hw_antsw_occu);
3466                 dbg_print("counter: %d, syn_count: %d\n", p_phy_sta_rpt->counter, p_phy_sta_rpt->syn_count);
3467                 dbg_print("cnt_cca2agc_rdy: %d, cnt_pw2cca: %d, shift_l_map\n", p_phy_sta_rpt->cnt_cca2agc_rdy, p_phy_sta_rpt->cnt_pw2cca, p_phy_sta_rpt->shift_l_map);
3468                 dbg_print("rsvd_0 = %d, rsvd_1 = %d, rsvd_2 = %d, rsvd_3 = %d, rsvd_4 = %d, rsvd_5 = %d\n", p_phy_sta_rpt->rsvd_0, p_phy_sta_rpt->rsvd_1, p_phy_sta_rpt->rsvd_2, p_phy_sta_rpt->rsvd_3, p_phy_sta_rpt->rsvd_4);
3469                 dbg_print("rsvd_5 = %d, rsvd_6 = %d, rsvd_6 = %d\n", p_phy_sta_rpt->rsvd_5, p_phy_sta_rpt->rsvd_6, p_phy_sta_rpt->rsvd_7);
3470         }
3471 #endif
3472 }
3473
3474 void
3475 phydm_get_rx_phy_status_type5(
3476         u8                              *p_phy_status
3477 )
3478 {
3479         /*
3480                 dbg_print("DW0: 0x%02x%02x%02x%02x\n", *(p_phy_status + 3), *(p_phy_status + 2), *(p_phy_status + 1), *(p_phy_status + 0));
3481                 dbg_print("DW1: 0x%02x%02x%02x%02x\n", *(p_phy_status + 7), *(p_phy_status + 6), *(p_phy_status + 5), *(p_phy_status + 4));
3482                 dbg_print("DW2: 0x%02x%02x%02x%02x\n", *(p_phy_status + 11), *(p_phy_status + 10), *(p_phy_status + 9), *(p_phy_status + 8));
3483                 dbg_print("DW3: 0x%02x%02x%02x%02x\n", *(p_phy_status + 15), *(p_phy_status + 14), *(p_phy_status + 13), *(p_phy_status + 12));
3484                 dbg_print("DW4: 0x%02x%02x%02x%02x\n", *(p_phy_status + 19), *(p_phy_status + 18), *(p_phy_status + 17), *(p_phy_status + 16));
3485                 dbg_print("DW5: 0x%02x%02x%02x%02x\n", *(p_phy_status + 23), *(p_phy_status + 22), *(p_phy_status + 21), *(p_phy_status + 20));
3486                 dbg_print("DW6: 0x%02x%02x%02x%02x\n", *(p_phy_status + 27), *(p_phy_status + 26), *(p_phy_status + 25), *(p_phy_status + 24));
3487         */
3488 }
3489
3490 void
3491 phydm_process_rssi_for_dm_new_type(
3492         struct PHY_DM_STRUCT                                    *p_dm_odm,
3493         struct _odm_phy_status_info_                    *p_phy_info,
3494         struct _odm_per_pkt_info_                       *p_pktinfo
3495 )
3496 {
3497         s32                             undecorated_smoothed_pwdb, accumulate_pwdb;
3498         u32                             rssi_ave;
3499         u8                              i;
3500         struct sta_info                 *p_entry;
3501         u8                              scaling_factor = 4;
3502
3503         if (p_pktinfo->station_id >= ODM_ASSOCIATE_ENTRY_NUM)
3504                 return;
3505
3506         p_entry = p_dm_odm->p_odm_sta_info[p_pktinfo->station_id];
3507
3508         if (!IS_STA_VALID(p_entry))
3509                 return;
3510
3511         if ((!p_pktinfo->is_packet_match_bssid))/*data frame only*/
3512                 return;
3513
3514         if (p_pktinfo->is_packet_beacon)
3515                 p_dm_odm->phy_dbg_info.num_qry_beacon_pkt++;
3516
3517 #if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY))
3518         if (p_dm_odm->support_ability & ODM_BB_ANT_DIV)
3519                 odm_process_rssi_for_ant_div(p_dm_odm, p_phy_info, p_pktinfo);
3520 #endif
3521
3522 #if (CONFIG_DYNAMIC_RX_PATH == 1)
3523         phydm_process_phy_status_for_dynamic_rx_path(p_dm_odm, p_phy_info, p_pktinfo);
3524         dbg_print("====>\n");
3525 #endif
3526
3527         if (p_pktinfo->is_packet_to_self || p_pktinfo->is_packet_beacon) {
3528                 u32 RSSI_linear = 0;
3529
3530                 p_dm_odm->rx_rate = p_pktinfo->data_rate;
3531                 undecorated_smoothed_pwdb = p_entry->rssi_stat.undecorated_smoothed_pwdb;
3532                 accumulate_pwdb = p_dm_odm->accumulate_pwdb[p_pktinfo->station_id];
3533                 p_dm_odm->RSSI_A = p_phy_info->rx_mimo_signal_strength[ODM_RF_PATH_A];
3534                 p_dm_odm->RSSI_B = p_phy_info->rx_mimo_signal_strength[ODM_RF_PATH_B];
3535                 p_dm_odm->RSSI_C = p_phy_info->rx_mimo_signal_strength[ODM_RF_PATH_C];
3536                 p_dm_odm->RSSI_D = p_phy_info->rx_mimo_signal_strength[ODM_RF_PATH_D];
3537
3538                 for (i = ODM_RF_PATH_A; i < ODM_RF_PATH_MAX_JAGUAR; i++) {
3539                         if (p_phy_info->rx_mimo_signal_strength[i] != 0)
3540                                 RSSI_linear += odm_convert_to_linear(p_phy_info->rx_mimo_signal_strength[i]);
3541                 }
3542
3543                 switch (p_phy_info->rx_count + 1) {
3544                 case 2:
3545                         RSSI_linear = (RSSI_linear >> 1);
3546                         break;
3547                 case 3:
3548                         RSSI_linear = ((RSSI_linear) + (RSSI_linear << 1) + (RSSI_linear << 3)) >> 5;   /* RSSI_linear/3 ~ RSSI_linear*11/32 */
3549                         break;
3550                 case 4:
3551                         RSSI_linear = (RSSI_linear >> 2);
3552                         break;
3553                 }
3554                 rssi_ave = odm_convert_to_db(RSSI_linear);
3555
3556                 if (undecorated_smoothed_pwdb <= 0) {
3557                         accumulate_pwdb = (p_phy_info->rx_pwdb_all << scaling_factor);
3558                         undecorated_smoothed_pwdb = p_phy_info->rx_pwdb_all;
3559                 } else {
3560                         accumulate_pwdb = accumulate_pwdb - (accumulate_pwdb >> scaling_factor) + rssi_ave;
3561                         undecorated_smoothed_pwdb = (accumulate_pwdb + (1 << (scaling_factor - 1))) >> scaling_factor;
3562                 }
3563
3564 #if (DM_ODM_SUPPORT_TYPE == ODM_CE)
3565                 if (p_entry->rssi_stat.undecorated_smoothed_pwdb == -1)
3566                         phydm_ra_rssi_rpt_wk(p_dm_odm);
3567 #endif
3568                 p_entry->rssi_stat.undecorated_smoothed_pwdb = undecorated_smoothed_pwdb;
3569                 p_dm_odm->accumulate_pwdb[p_pktinfo->station_id] = accumulate_pwdb;
3570
3571 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN))
3572                 if (p_pktinfo->station_id == 0) {
3573                         HAL_DATA_TYPE   *p_hal_data = GET_HAL_DATA(p_dm_odm->adapter);
3574
3575                         p_hal_data->UndecoratedSmoothedPWDB = undecorated_smoothed_pwdb;
3576                 }
3577 #endif
3578         }
3579 }
3580
3581 void
3582 phydm_rx_phy_status_new_type(
3583         struct PHY_DM_STRUCT                                    *p_phydm,
3584         u8                                              *p_phy_status,
3585         struct _odm_per_pkt_info_                       *p_pktinfo,
3586         struct _odm_phy_status_info_                    *p_phy_info
3587 )
3588 {
3589         u8              phy_status_type = (*p_phy_status & 0xf);
3590
3591         /*dbg_print("phydm_rx_phy_status_new_type================> (page: %d)\n", phy_status_type);*/
3592
3593         /* Memory reset */
3594         phydm_reset_phy_info(p_phydm, p_phy_info);
3595
3596         /* Phy status parsing */
3597         switch (phy_status_type) {
3598         case 0:
3599         {
3600                 phydm_get_rx_phy_status_type0(p_phydm, p_phy_status, p_pktinfo, p_phy_info);
3601                 break;
3602         }
3603         case 1:
3604         {
3605                 phydm_get_rx_phy_status_type1(p_phydm, p_phy_status, p_pktinfo, p_phy_info);
3606                 break;
3607         }
3608         case 2:
3609         {
3610                 phydm_get_rx_phy_status_type2(p_phydm, p_phy_status, p_pktinfo, p_phy_info);
3611                 break;
3612         }
3613 #if 0
3614         case 5:
3615         {
3616                 phydm_get_rx_phy_status_type5(p_phy_status);
3617                 return;
3618         }
3619 #endif
3620         default:
3621                 return;
3622         }
3623
3624         /* Update signal strength to UI, and p_phy_info->rx_pwdb_all is the maximum RSSI of all path */
3625 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
3626         p_phy_info->signal_strength = SignalScaleProc(p_phydm->adapter, p_phy_info->rx_pwdb_all, false, false);
3627 #elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
3628         p_phy_info->signal_strength = (u8)(odm_signal_scale_mapping(p_phydm, p_phy_info->rx_pwdb_all));
3629 #endif
3630
3631         /* Calculate average RSSI and smoothed RSSI */
3632         phydm_process_rssi_for_dm_new_type(p_phydm, p_phy_info, p_pktinfo);
3633
3634 }
3635 /*==============================================*/
3636 #endif
3637
3638 u32
3639 query_phydm_trx_capability(
3640         struct PHY_DM_STRUCT                                    *p_dm_odm
3641 )
3642 {
3643         u32 value32 = 0xFFFFFFFF;
3644
3645 #if (RTL8821C_SUPPORT == 1)
3646         if (p_dm_odm->support_ic_type == ODM_RTL8821C)
3647                 value32 = query_phydm_trx_capability_8821c(p_dm_odm);
3648 #endif
3649
3650         return value32;
3651 }
3652
3653 u32
3654 query_phydm_stbc_capability(
3655         struct PHY_DM_STRUCT                                    *p_dm_odm
3656 )
3657 {
3658         u32 value32 = 0xFFFFFFFF;
3659
3660 #if (RTL8821C_SUPPORT == 1)
3661         if (p_dm_odm->support_ic_type == ODM_RTL8821C)
3662                 value32 = query_phydm_stbc_capability_8821c(p_dm_odm);
3663 #endif
3664
3665         return value32;
3666 }
3667
3668 u32
3669 query_phydm_ldpc_capability(
3670         struct PHY_DM_STRUCT                                    *p_dm_odm
3671 )
3672 {
3673         u32 value32 = 0xFFFFFFFF;
3674
3675 #if (RTL8821C_SUPPORT == 1)
3676         if (p_dm_odm->support_ic_type == ODM_RTL8821C)
3677                 value32 = query_phydm_ldpc_capability_8821c(p_dm_odm);
3678 #endif
3679
3680         return value32;
3681 }
3682
3683 u32
3684 query_phydm_txbf_parameters(
3685         struct PHY_DM_STRUCT                                    *p_dm_odm
3686 )
3687 {
3688         u32 value32 = 0xFFFFFFFF;
3689
3690 #if (RTL8821C_SUPPORT == 1)
3691         if (p_dm_odm->support_ic_type == ODM_RTL8821C)
3692                 value32 = query_phydm_txbf_parameters_8821c(p_dm_odm);
3693 #endif
3694
3695         return value32;
3696 }
3697
3698 u32
3699 query_phydm_txbf_capability(
3700         struct PHY_DM_STRUCT                                    *p_dm_odm
3701 )
3702 {
3703         u32 value32 = 0xFFFFFFFF;
3704
3705 #if (RTL8821C_SUPPORT == 1)
3706         if (p_dm_odm->support_ic_type == ODM_RTL8821C)
3707                 value32 = query_phydm_txbf_capability_8821c(p_dm_odm);
3708 #endif
3709
3710         return value32;
3711 }