drivers/net/wireless/rockchip_wlan/rtl8723cs/hal/phydm/phydm_rainfo.c

   1 /******************************************************************************
   2  *
   3  * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of version 2 of the GNU General Public License as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program; if not, write to the Free Software Foundation, Inc.,
  16  * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  17  *
  18  *
  19  ******************************************************************************/
  20
  21 /* ************************************************************
  22  * include files
  23  * ************************************************************ */
  24 #include "mp_precomp.h"
  25 #include "phydm_precomp.h"
  26
  27 void
  28 phydm_h2C_debug(
  29         void            *p_dm_void,
  30         u32             *const dm_value,
  31         u32             *_used,
  32         char                    *output,
  33         u32             *_out_len
  34 )
  35 {
  36         struct PHY_DM_STRUCT            *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
  37         u8                      h2c_parameter[H2C_MAX_LENGTH] = {0};
  38         u8                      phydm_h2c_id = (u8)dm_value[0];
  39         u8                      i;
  40         u32                     used = *_used;
  41         u32                     out_len = *_out_len;
  42
  43         PHYDM_SNPRINTF((output + used, out_len - used, "Phydm Send H2C_ID (( 0x%x))\n", phydm_h2c_id));
  44         for (i = 0; i < H2C_MAX_LENGTH; i++) {
  45
  46                 h2c_parameter[i] = (u8)dm_value[i + 1];
  47                 PHYDM_SNPRINTF((output + used, out_len - used, "H2C: Byte[%d] = ((0x%x))\n", i, h2c_parameter[i]));
  48         }
  49
  50         odm_fill_h2c_cmd(p_dm_odm, phydm_h2c_id, H2C_MAX_LENGTH, h2c_parameter);
  51
  52 }
  53
  54 #if (defined(CONFIG_RA_DBG_CMD))
  55 void
  56 odm_ra_para_adjust_send_h2c(
  57         void    *p_dm_void
  58 )
  59 {
  60
  61         struct PHY_DM_STRUCT            *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
  62         struct _rate_adaptive_table_                    *p_ra_table = &p_dm_odm->dm_ra_table;
  63         u8                      h2c_parameter[6] = {0};
  64
  65         h2c_parameter[0] = RA_FIRST_MACID;
  66
  67         if (p_ra_table->ra_para_feedback_req) { /*h2c_parameter[5]=1 ; ask FW for all RA parameters*/
  68                 ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_RA_DBG, ODM_DBG_LOUD, ("[H2C] Ask FW for RA parameter\n"));
  69                 h2c_parameter[5] |= BIT(1); /*ask FW to report RA parameters*/
  70                 h2c_parameter[1] = p_ra_table->para_idx; /*p_ra_table->para_idx;*/
  71                 p_ra_table->ra_para_feedback_req = 0;
  72         } else {
  73                 ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_RA_DBG, ODM_DBG_LOUD, ("[H2C] Send H2C to FW for modifying RA parameter\n"));
  74
  75                 h2c_parameter[1] =  p_ra_table->para_idx;
  76                 h2c_parameter[2] =  p_ra_table->rate_idx;
  77                 /* [8 bit]*/
  78                 if (p_ra_table->para_idx == RADBG_RTY_PENALTY || p_ra_table->para_idx == RADBG_RATE_UP_RTY_RATIO || p_ra_table->para_idx == RADBG_RATE_DOWN_RTY_RATIO) {
  79                         h2c_parameter[3] = p_ra_table->value;
  80                         h2c_parameter[4] = 0;
  81                 }
  82                 /* [16 bit]*/
  83                 else {
  84                         h2c_parameter[3] = (u8)(((p_ra_table->value_16) & 0xf0) >> 4); /*byte1*/
  85                         h2c_parameter[4] = (u8)((p_ra_table->value_16) & 0x0f); /*byte0*/
  86                 }
  87         }
  88         ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_RA_DBG, ODM_DBG_LOUD, (" h2c_parameter[1] = 0x%x\n", h2c_parameter[1]));
  89         ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_RA_DBG, ODM_DBG_LOUD, (" h2c_parameter[2] = 0x%x\n", h2c_parameter[2]));
  90         ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_RA_DBG, ODM_DBG_LOUD, (" h2c_parameter[3] = 0x%x\n", h2c_parameter[3]));
  91         ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_RA_DBG, ODM_DBG_LOUD, (" h2c_parameter[4] = 0x%x\n", h2c_parameter[4]));
  92         ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_RA_DBG, ODM_DBG_LOUD, (" h2c_parameter[5] = 0x%x\n", h2c_parameter[5]));
  93
  94         odm_fill_h2c_cmd(p_dm_odm, ODM_H2C_RA_PARA_ADJUST, 6, h2c_parameter);
  95
  96 }
  97
  98
  99 void
 100 odm_ra_para_adjust(
 101         void            *p_dm_void
 102 )
 103 {
 104         struct PHY_DM_STRUCT            *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
 105         struct _rate_adaptive_table_                    *p_ra_table = &p_dm_odm->dm_ra_table;
 106         u8                      rate_idx = p_ra_table->rate_idx;
 107         u8                      value = p_ra_table->value;
 108         u8                      pre_value = 0xff;
 109
 110         if (p_ra_table->para_idx == RADBG_RTY_PENALTY) {
 111                 pre_value = p_ra_table->RTY_P[rate_idx];
 112                 p_ra_table->RTY_P[rate_idx] = value;
 113                 p_ra_table->RTY_P_modify_note[rate_idx] = 1;
 114         } else if (p_ra_table->para_idx == RADBG_N_HIGH) {
 115
 116         } else if (p_ra_table->para_idx == RADBG_N_LOW) {
 117
 118         } else if (p_ra_table->para_idx == RADBG_RATE_UP_RTY_RATIO) {
 119                 pre_value = p_ra_table->RATE_UP_RTY_RATIO[rate_idx];
 120                 p_ra_table->RATE_UP_RTY_RATIO[rate_idx] = value;
 121                 p_ra_table->RATE_UP_RTY_RATIO_modify_note[rate_idx] = 1;
 122         } else if (p_ra_table->para_idx == RADBG_RATE_DOWN_RTY_RATIO) {
 123                 pre_value = p_ra_table->RATE_DOWN_RTY_RATIO[rate_idx];
 124                 p_ra_table->RATE_DOWN_RTY_RATIO[rate_idx] = value;
 125                 p_ra_table->RATE_DOWN_RTY_RATIO_modify_note[rate_idx] = 1;
 126         }
 127         ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_RA_DBG, ODM_DBG_LOUD, ("Change RA Papa[%d], rate[ %d ],   ((%d))  ->  ((%d))\n", p_ra_table->para_idx, rate_idx, pre_value, value));
 128         odm_ra_para_adjust_send_h2c(p_dm_odm);
 129 }
 130
 131 void
 132 phydm_ra_print_msg(
 133         void            *p_dm_void,
 134         u8              *value,
 135         u8              *value_default,
 136         u8              *modify_note
 137 )
 138 {
 139         struct PHY_DM_STRUCT            *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
 140         struct _rate_adaptive_table_                    *p_ra_table = &p_dm_odm->dm_ra_table;
 141         u32 i;
 142
 143         ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_RA_DBG, ODM_DBG_LOUD, (" |rate index| |Current-value| |Default-value| |Modify?|\n"));
 144         for (i = 0 ; i <= (p_ra_table->rate_length); i++) {
 145 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN))
 146                 ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_RA_DBG, ODM_DBG_LOUD, ("     [ %d ]  %20d  %25d  %20s\n", i, value[i], value_default[i], ((modify_note[i] == 1) ? "V" : " .  ")));
 147 #else
 148                 ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_RA_DBG, ODM_DBG_LOUD, ("     [ %d ]  %10d  %14d  %14s\n", i, value[i], value_default[i], ((modify_note[i] == 1) ? "V" : " .  ")));
 149 #endif
 150         }
 151
 152 }
 153
 154 void
 155 odm_RA_debug(
 156         void            *p_dm_void,
 157         u32             *const dm_value
 158 )
 159 {
 160         struct PHY_DM_STRUCT            *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
 161         struct _rate_adaptive_table_                    *p_ra_table = &p_dm_odm->dm_ra_table;
 162
 163         p_ra_table->is_ra_dbg_init = false;
 164
 165         if (dm_value[0] == 100) { /*1 Print RA Parameters*/
 166                 u8      default_pointer_value;
 167                 u8      *pvalue;
 168                 u8      *pvalue_default;
 169                 u8      *pmodify_note;
 170
 171                 pvalue = pvalue_default = pmodify_note = &default_pointer_value;
 172
 173                 ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_RA_DBG, ODM_DBG_LOUD, ("\n------------------------------------------------------------------------------------\n"));
 174
 175                 if (dm_value[1] == RADBG_RTY_PENALTY) { /* [1]*/
 176                         ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_RA_DBG, ODM_DBG_LOUD, (" [1] RTY_PENALTY\n"));
 177                         pvalue          =       &(p_ra_table->RTY_P[0]);
 178                         pvalue_default  =       &(p_ra_table->RTY_P_default[0]);
 179                         pmodify_note    =       (u8 *)&(p_ra_table->RTY_P_modify_note[0]);
 180                 } else if (dm_value[1] == RADBG_N_HIGH)   /* [2]*/
 181                         ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_RA_DBG, ODM_DBG_LOUD, (" [2] N_HIGH\n"));
 182
 183                 else if (dm_value[1] == RADBG_N_LOW)   /*[3]*/
 184                         ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_RA_DBG, ODM_DBG_LOUD, (" [3] N_LOW\n"));
 185
 186                 else if (dm_value[1] == RADBG_RATE_UP_RTY_RATIO) { /* [8]*/
 187                         ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_RA_DBG, ODM_DBG_LOUD, (" [8] RATE_UP_RTY_RATIO\n"));
 188                         pvalue          =       &(p_ra_table->RATE_UP_RTY_RATIO[0]);
 189                         pvalue_default  =       &(p_ra_table->RATE_UP_RTY_RATIO_default[0]);
 190                         pmodify_note    =       (u8 *)&(p_ra_table->RATE_UP_RTY_RATIO_modify_note[0]);
 191                 } else if (dm_value[1] == RADBG_RATE_DOWN_RTY_RATIO) { /* [9]*/
 192                         ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_RA_DBG, ODM_DBG_LOUD, (" [9] RATE_DOWN_RTY_RATIO\n"));
 193                         pvalue          =       &(p_ra_table->RATE_DOWN_RTY_RATIO[0]);
 194                         pvalue_default  =       &(p_ra_table->RATE_DOWN_RTY_RATIO_default[0]);
 195                         pmodify_note    =       (u8 *)&(p_ra_table->RATE_DOWN_RTY_RATIO_modify_note[0]);
 196                 }
 197
 198                 phydm_ra_print_msg(p_dm_odm, pvalue, pvalue_default, pmodify_note);
 199                 ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_RA_DBG, ODM_DBG_LOUD, ("\n------------------------------------------------------------------------------------\n\n"));
 200
 201         } else if (dm_value[0] == 101) {
 202                 p_ra_table->para_idx = (u8)dm_value[1];
 203
 204                 p_ra_table->ra_para_feedback_req = 1;
 205                 odm_ra_para_adjust_send_h2c(p_dm_odm);
 206         } else {
 207                 p_ra_table->para_idx = (u8)dm_value[0];
 208                 p_ra_table->rate_idx  = (u8)dm_value[1];
 209                 p_ra_table->value = (u8)dm_value[2];
 210
 211                 odm_ra_para_adjust(p_dm_odm);
 212         }
 213 }
 214
 215 void
 216 odm_ra_para_adjust_init(
 217         void            *p_dm_void
 218 )
 219 {
 220         struct PHY_DM_STRUCT            *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
 221         struct _rate_adaptive_table_                    *p_ra_table = &p_dm_odm->dm_ra_table;
 222         u8                      i;
 223         u8                      ra_para_pool_u8[3] = { RADBG_RTY_PENALTY,  RADBG_RATE_UP_RTY_RATIO, RADBG_RATE_DOWN_RTY_RATIO};
 224         u8                      rate_size_ht_1ss = 20, rate_size_ht_2ss = 28, rate_size_ht_3ss = 36;     /*4+8+8+8+8 =36*/
 225         u8                      rate_size_vht_1ss = 10, rate_size_vht_2ss = 20, rate_size_vht_3ss = 30;  /*10 + 10 +10 =30*/
 226 #if 0
 227         /* RTY_PENALTY          =       1,   u8 */
 228         /* N_HIGH                               =       2, */
 229         /* N_LOW                                =       3, */
 230         /* RATE_UP_TABLE                =       4, */
 231         /* RATE_DOWN_TABLE      =       5, */
 232         /* TRYING_NECESSARY     =       6, */
 233         /* DROPING_NECESSARY =  7, */
 234         /* RATE_UP_RTY_RATIO    =       8,  u8 */
 235         /* RATE_DOWN_RTY_RATIO= 9,  u8 */
 236         /* ALL_PARA             =       0xff */
 237
 238 #endif
 239         ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_RA_DBG, ODM_DBG_LOUD, ("odm_ra_para_adjust_init\n"));
 240
 241 /* JJ ADD 20161014 */
 242         if (p_dm_odm->support_ic_type & (ODM_RTL8188F | ODM_RTL8195A | ODM_RTL8703B | ODM_RTL8723B | ODM_RTL8188E | ODM_RTL8723D | ODM_RTL8710B))
 243                 p_ra_table->rate_length = rate_size_ht_1ss;
 244         else if (p_dm_odm->support_ic_type & (ODM_RTL8192E | ODM_RTL8197F))
 245                 p_ra_table->rate_length = rate_size_ht_2ss;
 246         else if (p_dm_odm->support_ic_type & (ODM_RTL8821 | ODM_RTL8881A | ODM_RTL8821C))
 247                 p_ra_table->rate_length = rate_size_ht_1ss + rate_size_vht_1ss;
 248         else if (p_dm_odm->support_ic_type & (ODM_RTL8812 | ODM_RTL8822B))
 249                 p_ra_table->rate_length = rate_size_ht_2ss + rate_size_vht_2ss;
 250         else if (p_dm_odm->support_ic_type == ODM_RTL8814A)
 251                 p_ra_table->rate_length = rate_size_ht_3ss + rate_size_vht_3ss;
 252         else
 253                 p_ra_table->rate_length = rate_size_ht_1ss;
 254
 255         p_ra_table->is_ra_dbg_init = true;
 256         for (i = 0; i < 3; i++) {
 257                 p_ra_table->ra_para_feedback_req = 1;
 258                 p_ra_table->para_idx    =       ra_para_pool_u8[i];
 259                 odm_ra_para_adjust_send_h2c(p_dm_odm);
 260         }
 261 }
 262
 263 #else
 264
 265 void
 266 phydm_RA_debug_PCR(
 267         void            *p_dm_void,
 268         u32             *const dm_value,
 269         u32             *_used,
 270         char                    *output,
 271         u32             *_out_len
 272 )
 273 {
 274         struct PHY_DM_STRUCT            *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
 275         struct _rate_adaptive_table_                    *p_ra_table = &p_dm_odm->dm_ra_table;
 276         u32 used = *_used;
 277         u32 out_len = *_out_len;
 278
 279         if (dm_value[0] == 100) {
 280                 PHYDM_SNPRINTF((output + used, out_len - used, "[Get] PCR RA_threshold_offset = (( %s%d ))\n", ((p_ra_table->RA_threshold_offset == 0) ? " " : ((p_ra_table->RA_offset_direction) ? "+" : "-")), p_ra_table->RA_threshold_offset));
 281                 /**/
 282         } else if (dm_value[0] == 0) {
 283                 p_ra_table->RA_offset_direction = 0;
 284                 p_ra_table->RA_threshold_offset = (u8)dm_value[1];
 285                 PHYDM_SNPRINTF((output + used, out_len - used, "[Set] PCR RA_threshold_offset = (( -%d ))\n", p_ra_table->RA_threshold_offset));
 286         } else if (dm_value[0] == 1) {
 287                 p_ra_table->RA_offset_direction = 1;
 288                 p_ra_table->RA_threshold_offset = (u8)dm_value[1];
 289                 PHYDM_SNPRINTF((output + used, out_len - used, "[Set] PCR RA_threshold_offset = (( +%d ))\n", p_ra_table->RA_threshold_offset));
 290         } else {
 291                 PHYDM_SNPRINTF((output + used, out_len - used, "[Set] Error\n"));
 292                 /**/
 293         }
 294
 295 }
 296
 297 #endif /*#if (defined(CONFIG_RA_DBG_CMD))*/
 298
 299 void
 300 odm_c2h_ra_para_report_handler(
 301         void    *p_dm_void,
 302         u8      *cmd_buf,
 303         u8      cmd_len
 304 )
 305 {
 306         struct PHY_DM_STRUCT            *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
 307         struct _rate_adaptive_table_                    *p_ra_table = &p_dm_odm->dm_ra_table;
 308
 309         u8      para_idx = cmd_buf[0]; /*Retry Penalty, NH, NL*/
 310         u8      rate_type_start = cmd_buf[1];
 311         u8      rate_type_length = cmd_len - 2;
 312         u8      i;
 313
 314
 315         ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_RA_DBG, ODM_DBG_LOUD, ("[ From FW C2H RA Para ]  cmd_buf[0]= (( %d ))\n", cmd_buf[0]));
 316
 317 #if (defined(CONFIG_RA_DBG_CMD))
 318         if (para_idx == RADBG_RTY_PENALTY) {
 319                 ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_RA_DBG, ODM_DBG_LOUD, (" |rate index|   |RTY Penality index|\n"));
 320
 321                 for (i = 0 ; i < (rate_type_length) ; i++) {
 322                         if (p_ra_table->is_ra_dbg_init)
 323                                 p_ra_table->RTY_P_default[rate_type_start + i] = cmd_buf[2 + i];
 324
 325                         p_ra_table->RTY_P[rate_type_start + i] = cmd_buf[2 + i];
 326                         ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_RA_DBG, ODM_DBG_LOUD, ("%8d  %15d\n", (rate_type_start + i), p_ra_table->RTY_P[rate_type_start + i]));
 327                 }
 328
 329         } else  if (para_idx == RADBG_N_HIGH) {
 330                 /**/
 331                 ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_RA_DBG, ODM_DBG_LOUD, (" |rate index|    |N-High|\n"));
 332
 333
 334         } else if (para_idx == RADBG_N_LOW) {
 335                 ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_RA_DBG, ODM_DBG_LOUD, (" |rate index|   |N-Low|\n"));
 336                 /**/
 337         } else if (para_idx == RADBG_RATE_UP_RTY_RATIO) {
 338                 ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_RA_DBG, ODM_DBG_LOUD, (" |rate index|   |rate Up RTY Ratio|\n"));
 339
 340                 for (i = 0; i < (rate_type_length); i++) {
 341                         if (p_ra_table->is_ra_dbg_init)
 342                                 p_ra_table->RATE_UP_RTY_RATIO_default[rate_type_start + i] = cmd_buf[2 + i];
 343
 344                         p_ra_table->RATE_UP_RTY_RATIO[rate_type_start + i] = cmd_buf[2 + i];
 345                         ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_RA_DBG, ODM_DBG_LOUD, ("%8d  %15d\n", (rate_type_start + i), p_ra_table->RATE_UP_RTY_RATIO[rate_type_start + i]));
 346                 }
 347         } else   if (para_idx == RADBG_RATE_DOWN_RTY_RATIO) {
 348                 ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_RA_DBG, ODM_DBG_LOUD, (" |rate index|   |rate Down RTY Ratio|\n"));
 349
 350                 for (i = 0; i < (rate_type_length); i++) {
 351                         if (p_ra_table->is_ra_dbg_init)
 352                                 p_ra_table->RATE_DOWN_RTY_RATIO_default[rate_type_start + i] = cmd_buf[2 + i];
 353
 354                         p_ra_table->RATE_DOWN_RTY_RATIO[rate_type_start + i] = cmd_buf[2 + i];
 355                         ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_RA_DBG, ODM_DBG_LOUD, ("%8d  %15d\n", (rate_type_start + i), p_ra_table->RATE_DOWN_RTY_RATIO[rate_type_start + i]));
 356                 }
 357         } else
 358 #endif
 359                 if (para_idx == RADBG_DEBUG_MONITOR1) {
 360                         ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("-------------------------------\n"));
 361                         if (p_dm_odm->support_ic_type & PHYDM_IC_3081_SERIES) {
 362
 363                                 ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("%5s  %d\n", "RSSI =", cmd_buf[1]));
 364                                 ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("%5s  0x%x\n", "rate =", cmd_buf[2] & 0x7f));
 365                                 ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("%5s  %d\n", "SGI =", (cmd_buf[2] & 0x80) >> 7));
 366                                 ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("%5s  %d\n", "BW =", cmd_buf[3]));
 367                                 ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("%5s  %d\n", "BW_max =", cmd_buf[4]));
 368                                 ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("%5s  0x%x\n", "multi_rate0 =", cmd_buf[5]));
 369                                 ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("%5s  0x%x\n", "multi_rate1 =", cmd_buf[6]));
 370                                 ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("%5s  %d\n", "DISRA =",       cmd_buf[7]));
 371                                 ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("%5s  %d\n", "VHT_EN =", cmd_buf[8]));
 372                                 ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("%5s  %d\n", "SGI_support =", cmd_buf[9]));
 373                                 ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("%5s  %d\n", "try_ness =", cmd_buf[10]));
 374                                 ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("%5s  0x%x\n", "pre_rate =", cmd_buf[11]));
 375                         } else {
 376                                 ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("%5s  %d\n", "RSSI =", cmd_buf[1]));
 377                                 ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("%5s  %x\n", "BW =", cmd_buf[2]));
 378                                 ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("%5s  %d\n", "DISRA =", cmd_buf[3]));
 379                                 ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("%5s  %d\n", "VHT_EN =", cmd_buf[4]));
 380                                 ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("%5s  %d\n", "Hightest rate =", cmd_buf[5]));
 381                                 ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("%5s  0x%x\n", "Lowest rate =", cmd_buf[6]));
 382                                 ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("%5s  0x%x\n", "SGI_support =", cmd_buf[7]));
 383                                 ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("%5s  %d\n", "Rate_ID =",     cmd_buf[8]));;
 384                         }
 385                         ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("-------------------------------\n"));
 386                 } else   if (para_idx == RADBG_DEBUG_MONITOR2) {
 387                         ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("-------------------------------\n"));
 388                         if (p_dm_odm->support_ic_type & PHYDM_IC_3081_SERIES) {
 389                                 ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("%5s  %d\n", "rate_id =", cmd_buf[1]));
 390                                 ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("%5s  0x%x\n", "highest_rate =", cmd_buf[2]));
 391                                 ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("%5s  0x%x\n", "lowest_rate =", cmd_buf[3]));
 392
 393                                 for (i = 4; i <= 11; i++)
 394                                         ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("RAMASK =  0x%x\n", cmd_buf[i]));
 395                         } else {
 396                                 ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("%5s  %x%x  %x%x  %x%x  %x%x\n", "RA Mask:",
 397                                         cmd_buf[8], cmd_buf[7], cmd_buf[6], cmd_buf[5], cmd_buf[4], cmd_buf[3], cmd_buf[2], cmd_buf[1]));
 398                         }
 399                         ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("-------------------------------\n"));
 400                 } else   if (para_idx == RADBG_DEBUG_MONITOR3) {
 401
 402                         for (i = 0; i < (cmd_len - 1); i++)
 403                                 ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("content[%d] = %d\n", i, cmd_buf[1 + i]));
 404                 } else   if (para_idx == RADBG_DEBUG_MONITOR4)
 405                         ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("%5s  {%d.%d}\n", "RA version =", cmd_buf[1], cmd_buf[2]));
 406                 else if (para_idx == RADBG_DEBUG_MONITOR5) {
 407                         ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("%5s  0x%x\n", "Current rate =", cmd_buf[1]));
 408                         ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("%5s  %d\n", "Retry ratio =", cmd_buf[2]));
 409                         ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("%5s  %d\n", "rate down ratio =", cmd_buf[3]));
 410                         ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("%5s  0x%x\n", "highest rate =", cmd_buf[4]));
 411                         ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("%5s  {0x%x 0x%x}\n", "Muti-try =", cmd_buf[5], cmd_buf[6]));
 412                         ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("%5s  0x%x%x%x%x%x\n", "RA mask =", cmd_buf[11], cmd_buf[10], cmd_buf[9], cmd_buf[8], cmd_buf[7]));
 413                 }
 414 }
 415
 416 void
 417 phydm_ra_dynamic_retry_count(
 418         void    *p_dm_void
 419 )
 420 {
 421         struct PHY_DM_STRUCT            *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
 422         struct _rate_adaptive_table_            *p_ra_table = &p_dm_odm->dm_ra_table;
 423         struct sta_info         *p_entry;
 424         u8      i, retry_offset;
 425         u32     ma_rx_tp;
 426
 427         if (!(p_dm_odm->support_ability & ODM_BB_DYNAMIC_ARFR))
 428                 return;
 429
 430         /*ODM_RT_TRACE(p_dm_odm, ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, ("p_dm_odm->pre_b_noisy = %d\n", p_dm_odm->pre_b_noisy ));*/
 431         if (p_dm_odm->pre_b_noisy != p_dm_odm->noisy_decision) {
 432
 433                 if (p_dm_odm->noisy_decision) {
 434                         ODM_RT_TRACE(p_dm_odm, ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, ("->Noisy Env. RA fallback value\n"));
 435                         odm_set_mac_reg(p_dm_odm, 0x430, MASKDWORD, 0x0);
 436                         odm_set_mac_reg(p_dm_odm, 0x434, MASKDWORD, 0x04030201);
 437                 } else {
 438                         ODM_RT_TRACE(p_dm_odm, ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, ("->Clean Env. RA fallback value\n"));
 439                         odm_set_mac_reg(p_dm_odm, 0x430, MASKDWORD, 0x01000000);
 440                         odm_set_mac_reg(p_dm_odm, 0x434, MASKDWORD, 0x06050402);
 441                 }
 442                 p_dm_odm->pre_b_noisy = p_dm_odm->noisy_decision;
 443         }
 444 }
 445
 446 #if (defined(CONFIG_RA_DYNAMIC_RTY_LIMIT))
 447
 448 void
 449 phydm_retry_limit_table_bound(
 450         void    *p_dm_void,
 451         u8      *retry_limit,
 452         u8      offset
 453 )
 454 {
 455         struct PHY_DM_STRUCT            *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
 456         struct _rate_adaptive_table_            *p_ra_table = &p_dm_odm->dm_ra_table;
 457
 458         if (*retry_limit >  offset) {
 459
 460                 *retry_limit -= offset;
 461
 462                 if (*retry_limit < p_ra_table->retrylimit_low)
 463                         *retry_limit = p_ra_table->retrylimit_low;
 464                 else if (*retry_limit > p_ra_table->retrylimit_high)
 465                         *retry_limit = p_ra_table->retrylimit_high;
 466         } else
 467                 *retry_limit = p_ra_table->retrylimit_low;
 468 }
 469
 470 void
 471 phydm_reset_retry_limit_table(
 472         void    *p_dm_void
 473 )
 474 {
 475         struct PHY_DM_STRUCT            *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
 476         struct _rate_adaptive_table_            *p_ra_table = &p_dm_odm->dm_ra_table;
 477         u8                      i;
 478
 479 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) /*support all IC platform*/
 480
 481 #else
 482 #if ((RTL8192E_SUPPORT == 1) || (RTL8723B_SUPPORT == 1) || (RTL8188E_SUPPORT == 1))
 483         u8 per_rate_retrylimit_table_20M[ODM_RATEMCS15 + 1] = {
 484                 1, 1, 2, 4,                                     /*CCK*/
 485                 2, 2, 4, 6, 8, 12, 16, 18,              /*OFDM*/
 486                 2, 4, 6, 8, 12, 18, 20, 22,             /*20M HT-1SS*/
 487                 2, 4, 6, 8, 12, 18, 20, 22              /*20M HT-2SS*/
 488         };
 489         u8 per_rate_retrylimit_table_40M[ODM_RATEMCS15 + 1] = {
 490                 1, 1, 2, 4,                                     /*CCK*/
 491                 2, 2, 4, 6, 8, 12, 16, 18,              /*OFDM*/
 492                 4, 8, 12, 16, 24, 32, 32, 32,           /*40M HT-1SS*/
 493                 4, 8, 12, 16, 24, 32, 32, 32            /*40M HT-2SS*/
 494         };
 495
 496 #elif (RTL8821A_SUPPORT == 1) || (RTL8881A_SUPPORT == 1)
 497
 498 #elif (RTL8812A_SUPPORT == 1)
 499
 500 #elif (RTL8814A_SUPPORT == 1)
 501
 502 #else
 503
 504 #endif
 505 #endif
 506
 507         memcpy(&(p_ra_table->per_rate_retrylimit_20M[0]), &(per_rate_retrylimit_table_20M[0]), ODM_NUM_RATE_IDX);
 508         memcpy(&(p_ra_table->per_rate_retrylimit_40M[0]), &(per_rate_retrylimit_table_40M[0]), ODM_NUM_RATE_IDX);
 509
 510         for (i = 0; i < ODM_NUM_RATE_IDX; i++) {
 511                 phydm_retry_limit_table_bound(p_dm_odm, &(p_ra_table->per_rate_retrylimit_20M[i]), 0);
 512                 phydm_retry_limit_table_bound(p_dm_odm, &(p_ra_table->per_rate_retrylimit_40M[i]), 0);
 513         }
 514 }
 515
 516 void
 517 phydm_ra_dynamic_retry_limit_init(
 518         void    *p_dm_void
 519 )
 520 {
 521         struct PHY_DM_STRUCT            *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
 522         struct _rate_adaptive_table_                    *p_ra_table = &p_dm_odm->dm_ra_table;
 523
 524         p_ra_table->retry_descend_num = RA_RETRY_DESCEND_NUM;
 525         p_ra_table->retrylimit_low = RA_RETRY_LIMIT_LOW;
 526         p_ra_table->retrylimit_high = RA_RETRY_LIMIT_HIGH;
 527
 528         phydm_reset_retry_limit_table(p_dm_odm);
 529
 530 }
 531
 532 #endif
 533
 534 void
 535 phydm_ra_dynamic_retry_limit(
 536         void    *p_dm_void
 537 )
 538 {
 539 #if (defined(CONFIG_RA_DYNAMIC_RTY_LIMIT))
 540         struct PHY_DM_STRUCT            *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
 541         struct _rate_adaptive_table_            *p_ra_table = &p_dm_odm->dm_ra_table;
 542         struct sta_info         *p_entry;
 543         u8      i, retry_offset;
 544         u32     ma_rx_tp;
 545
 546
 547         if (p_dm_odm->pre_number_active_client == p_dm_odm->number_active_client) {
 548
 549                 ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_RA_DBG, ODM_DBG_LOUD, (" pre_number_active_client ==  number_active_client\n"));
 550                 return;
 551
 552         } else {
 553                 if (p_dm_odm->number_active_client == 1) {
 554                         phydm_reset_retry_limit_table(p_dm_odm);
 555                         ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_RA_DBG, ODM_DBG_LOUD, ("one client only->reset to default value\n"));
 556                 } else {
 557
 558                         retry_offset = p_dm_odm->number_active_client * p_ra_table->retry_descend_num;
 559
 560                         for (i = 0; i < ODM_NUM_RATE_IDX; i++) {
 561
 562                                 phydm_retry_limit_table_bound(p_dm_odm, &(p_ra_table->per_rate_retrylimit_20M[i]), retry_offset);
 563                                 phydm_retry_limit_table_bound(p_dm_odm, &(p_ra_table->per_rate_retrylimit_40M[i]), retry_offset);
 564                         }
 565                 }
 566         }
 567 #endif
 568 }
 569
 570 #if (defined(CONFIG_RA_DYNAMIC_RATE_ID))
 571 void
 572 phydm_ra_dynamic_rate_id_on_assoc(
 573         void    *p_dm_void,
 574         u8      wireless_mode,
 575         u8      init_rate_id
 576 )
 577 {
 578         struct PHY_DM_STRUCT    *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
 579
 580         ODM_RT_TRACE(p_dm_odm, ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, ("[ON ASSOC] rf_mode = ((0x%x)), wireless_mode = ((0x%x)), init_rate_id = ((0x%x))\n", p_dm_odm->rf_type, wireless_mode, init_rate_id));
 581
 582         if ((p_dm_odm->rf_type == ODM_2T2R) | (p_dm_odm->rf_type == ODM_2T2R_GREEN) | (p_dm_odm->rf_type == ODM_2T3R) | (p_dm_odm->rf_type == ODM_2T4R)) {
 583
 584                 if ((p_dm_odm->support_ic_type & (ODM_RTL8812 | ODM_RTL8192E)) &&
 585                     (wireless_mode & (ODM_WM_N24G | ODM_WM_N5G))
 586                    ) {
 587                         ODM_RT_TRACE(p_dm_odm, ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, ("[ON ASSOC] set N-2SS ARFR5 table\n"));
 588                         odm_set_mac_reg(p_dm_odm, 0x4a4, MASKDWORD, 0xfc1ffff); /*N-2SS, ARFR5, rate_id = 0xe*/
 589                         odm_set_mac_reg(p_dm_odm, 0x4a8, MASKDWORD, 0x0);               /*N-2SS, ARFR5, rate_id = 0xe*/
 590                 } else if ((p_dm_odm->support_ic_type & (ODM_RTL8812)) &&
 591                         (wireless_mode & (ODM_WM_AC_5G | ODM_WM_AC_24G | ODM_WM_AC_ONLY))
 592                           ) {
 593                         ODM_RT_TRACE(p_dm_odm, ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, ("[ON ASSOC] set AC-2SS ARFR0 table\n"));
 594                         odm_set_mac_reg(p_dm_odm, 0x444, MASKDWORD, 0x0fff);    /*AC-2SS, ARFR0, rate_id = 0x9*/
 595                         odm_set_mac_reg(p_dm_odm, 0x448, MASKDWORD, 0xff01f000);                /*AC-2SS, ARFR0, rate_id = 0x9*/
 596                 }
 597         }
 598
 599 }
 600
 601 void
 602 phydm_ra_dynamic_rate_id_init(
 603         void    *p_dm_void
 604 )
 605 {
 606         struct PHY_DM_STRUCT    *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
 607
 608         if (p_dm_odm->support_ic_type & (ODM_RTL8812 | ODM_RTL8192E)) {
 609
 610                 odm_set_mac_reg(p_dm_odm, 0x4a4, MASKDWORD, 0xfc1ffff); /*N-2SS, ARFR5, rate_id = 0xe*/
 611                 odm_set_mac_reg(p_dm_odm, 0x4a8, MASKDWORD, 0x0);               /*N-2SS, ARFR5, rate_id = 0xe*/
 612
 613                 odm_set_mac_reg(p_dm_odm, 0x444, MASKDWORD, 0x0fff);            /*AC-2SS, ARFR0, rate_id = 0x9*/
 614                 odm_set_mac_reg(p_dm_odm, 0x448, MASKDWORD, 0xff01f000);        /*AC-2SS, ARFR0, rate_id = 0x9*/
 615         }
 616 }
 617
 618 void
 619 phydm_update_rate_id(
 620         void    *p_dm_void,
 621         u8      rate,
 622         u8      platform_macid
 623 )
 624 {
 625         struct PHY_DM_STRUCT    *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
 626         struct _rate_adaptive_table_            *p_ra_table = &p_dm_odm->dm_ra_table;
 627         u8              current_tx_ss;
 628         u8              rate_idx = rate & 0x7f; /*remove bit7 SGI*/
 629         u8              wireless_mode;
 630         u8              phydm_macid;
 631         struct sta_info *p_entry;
 632
 633
 634 #if     0
 635         if (rate_idx >= ODM_RATEVHTSS2MCS0) {
 636                 ODM_RT_TRACE(p_dm_odm, ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, ("rate[%d]: (( VHT2SS-MCS%d ))\n", platform_macid, (rate_idx - ODM_RATEVHTSS2MCS0)));
 637                 /*dummy for SD4 check patch*/
 638         } else if (rate_idx >= ODM_RATEVHTSS1MCS0) {
 639                 ODM_RT_TRACE(p_dm_odm, ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, ("rate[%d]: (( VHT1SS-MCS%d ))\n", platform_macid, (rate_idx - ODM_RATEVHTSS1MCS0)));
 640                 /*dummy for SD4 check patch*/
 641         } else if (rate_idx >= ODM_RATEMCS0) {
 642                 ODM_RT_TRACE(p_dm_odm, ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, ("rate[%d]: (( HT-MCS%d ))\n", platform_macid, (rate_idx - ODM_RATEMCS0)));
 643                 /*dummy for SD4 check patch*/
 644         } else {
 645                 ODM_RT_TRACE(p_dm_odm, ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, ("rate[%d]: (( HT-MCS%d ))\n", platform_macid, rate_idx));
 646                 /*dummy for SD4 check patch*/
 647         }
 648 #endif
 649
 650         phydm_macid = p_dm_odm->platform2phydm_macid_table[platform_macid];
 651         p_entry = p_dm_odm->p_odm_sta_info[phydm_macid];
 652
 653         if (IS_STA_VALID(p_entry)) {
 654                 wireless_mode = p_entry->wireless_mode;
 655
 656                 if ((p_dm_odm->rf_type  == ODM_2T2R) | (p_dm_odm->rf_type  == ODM_2T2R_GREEN) | (p_dm_odm->rf_type  == ODM_2T3R) | (p_dm_odm->rf_type  == ODM_2T4R)) {
 657
 658                         p_entry->ratr_idx = p_entry->ratr_idx_init;
 659                         if (wireless_mode & (ODM_WM_N24G | ODM_WM_N5G)) { /*N mode*/
 660                                 if (rate_idx >= ODM_RATEMCS8 && rate_idx <= ODM_RATEMCS15) { /*2SS mode*/
 661
 662                                         p_entry->ratr_idx = ARFR_5_RATE_ID;
 663                                         ODM_RT_TRACE(p_dm_odm, ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, ("ARFR_5\n"));
 664                                 }
 665                         } else if (wireless_mode & (ODM_WM_AC_5G | ODM_WM_AC_24G | ODM_WM_AC_ONLY)) {/*AC mode*/
 666                                 if (rate_idx >= ODM_RATEVHTSS2MCS0 && rate_idx <= ODM_RATEVHTSS2MCS9) {/*2SS mode*/
 667
 668                                         p_entry->ratr_idx = ARFR_0_RATE_ID;
 669                                         ODM_RT_TRACE(p_dm_odm, ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, ("ARFR_0\n"));
 670                                 }
 671                         }
 672                         ODM_RT_TRACE(p_dm_odm, ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, ("UPdate_RateID[%d]: (( 0x%x ))\n", platform_macid, p_entry->ratr_idx));
 673                 }
 674         }
 675
 676 }
 677 #endif
 678
 679 void
 680 phydm_print_rate(
 681         void    *p_dm_void,
 682         u8      rate,
 683         u32     dbg_component
 684 )
 685 {
 686         struct PHY_DM_STRUCT    *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
 687         u8              legacy_table[12] = {1, 2, 5, 11, 6, 9, 12, 18, 24, 36, 48, 54};
 688         u8              rate_idx = rate & 0x7f; /*remove bit7 SGI*/
 689         u8              vht_en = (rate_idx >= ODM_RATEVHTSS1MCS0) ? 1 : 0;
 690         u8              b_sgi = (rate & 0x80) >> 7;
 691
 692         ODM_RT_TRACE_F(p_dm_odm, dbg_component, ODM_DBG_LOUD, ("( %s%s%s%s%d%s%s)\n",
 693                 ((rate_idx >= ODM_RATEVHTSS1MCS0) && (rate_idx <= ODM_RATEVHTSS1MCS9)) ? "VHT 1ss  " : "",
 694                 ((rate_idx >= ODM_RATEVHTSS2MCS0) && (rate_idx <= ODM_RATEVHTSS2MCS9)) ? "VHT 2ss " : "",
 695                 ((rate_idx >= ODM_RATEVHTSS3MCS0) && (rate_idx <= ODM_RATEVHTSS3MCS9)) ? "VHT 3ss " : "",
 696                         (rate_idx >= ODM_RATEMCS0) ? "MCS " : "",
 697                 (vht_en) ? ((rate_idx - ODM_RATEVHTSS1MCS0) % 10) : ((rate_idx >= ODM_RATEMCS0) ? (rate_idx - ODM_RATEMCS0) : ((rate_idx <= ODM_RATE54M) ? legacy_table[rate_idx] : 0)),
 698                         (b_sgi) ? "-S" : "  ",
 699                         (rate_idx >= ODM_RATEMCS0) ? "" : "M"));
 700 }
 701
 702 void
 703 phydm_c2h_ra_report_handler(
 704         void    *p_dm_void,
 705         u8   *cmd_buf,
 706         u8   cmd_len
 707 )
 708 {
 709         struct PHY_DM_STRUCT    *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
 710         struct _rate_adaptive_table_            *p_ra_table = &p_dm_odm->dm_ra_table;
 711         u8      legacy_table[12] = {1, 2, 5, 11, 6, 9, 12, 18, 24, 36, 48, 54};
 712         u8      macid = cmd_buf[1];
 713         u8      rate = cmd_buf[0];
 714         u8      rate_idx = rate & 0x7f; /*remove bit7 SGI*/
 715         u8      pre_rate = p_ra_table->link_tx_rate[macid];
 716         u8      rate_order;
 717 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
 718         struct _ADAPTER *adapter = p_dm_odm->adapter;
 719
 720         GET_HAL_DATA(adapter)->CurrentRARate = HwRateToMRate(rate_idx);
 721 #endif
 722
 723
 724         if (cmd_len >= 4) {
 725                 if (cmd_buf[3] == 0) {
 726                         ODM_RT_TRACE(p_dm_odm, ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, ("TX Init-rate Update[%d]:", macid));
 727                         /**/
 728                 } else if (cmd_buf[3] == 0xff) {
 729                         ODM_RT_TRACE(p_dm_odm, ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, ("FW Level: Fix rate[%d]:", macid));
 730                         /**/
 731                 } else if (cmd_buf[3] == 1) {
 732                         ODM_RT_TRACE(p_dm_odm, ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, ("Try Success[%d]:", macid));
 733                         /**/
 734                 } else if (cmd_buf[3] == 2) {
 735                         ODM_RT_TRACE(p_dm_odm, ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, ("Try Fail & Try Again[%d]:", macid));
 736                         /**/
 737                 } else if (cmd_buf[3] == 3) {
 738                         ODM_RT_TRACE(p_dm_odm, ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, ("rate Back[%d]:", macid));
 739                         /**/
 740                 } else if (cmd_buf[3] == 4) {
 741                         ODM_RT_TRACE(p_dm_odm, ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, ("start rate by RSSI[%d]:", macid));
 742                         /**/
 743                 } else if (cmd_buf[3] == 5) {
 744                         ODM_RT_TRACE(p_dm_odm, ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, ("Try rate[%d]:", macid));
 745                         /**/
 746                 }
 747         } else {
 748                 ODM_RT_TRACE(p_dm_odm, ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, ("Tx rate Update[%d]:", macid));
 749                 /**/
 750         }
 751
 752         /*phydm_print_rate(p_dm_odm, pre_rate_idx, ODM_COMP_RATE_ADAPTIVE);*/
 753         /*ODM_RT_TRACE(p_dm_odm, ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, (">\n",macid );*/
 754         phydm_print_rate(p_dm_odm, rate, ODM_COMP_RATE_ADAPTIVE);
 755
 756         p_ra_table->link_tx_rate[macid] = rate;
 757
 758         /*trigger power training*/
 759 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
 760
 761         rate_order = phydm_rate_order_compute(p_dm_odm, rate_idx);
 762
 763         if ((p_dm_odm->is_one_entry_only) ||
 764             ((rate_order > p_ra_table->highest_client_tx_order) && (p_ra_table->power_tracking_flag == 1))
 765            ) {
 766                 phydm_update_pwr_track(p_dm_odm, rate_idx);
 767                 p_ra_table->power_tracking_flag = 0;
 768         }
 769
 770 #endif
 771
 772         /*trigger dynamic rate ID*/
 773 #if (defined(CONFIG_RA_DYNAMIC_RATE_ID))
 774         if (p_dm_odm->support_ic_type & (ODM_RTL8812 | ODM_RTL8192E))
 775                 phydm_update_rate_id(p_dm_odm, rate, macid);
 776 #endif
 777
 778 }
 779
 780 void
 781 odm_rssi_monitor_init(
 782         void            *p_dm_void
 783 )
 784 {
 785 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
 786         struct PHY_DM_STRUCT            *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
 787         struct _rate_adaptive_table_            *p_ra_table = &p_dm_odm->dm_ra_table;
 788 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN))
 789         struct _ADAPTER         *adapter = p_dm_odm->adapter;
 790         HAL_DATA_TYPE   *p_hal_data = GET_HAL_DATA(adapter);
 791
 792         p_ra_table->PT_collision_pre = true;    /*used in odm_dynamic_arfb_select(WIN only)*/
 793
 794         p_hal_data->UndecoratedSmoothedPWDB = -1;
 795         p_hal_data->ra_rpt_linked = false;
 796 #endif
 797
 798         p_ra_table->firstconnect = false;
 799
 800
 801 #endif
 802 }
 803
 804 void
 805 odm_ra_post_action_on_assoc(
 806         void    *p_dm_void
 807 )
 808 {
 809         struct PHY_DM_STRUCT    *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
 810         /*
 811                 p_dm_odm->h2c_rarpt_connect = 1;
 812                 odm_rssi_monitor_check(p_dm_odm);
 813                 p_dm_odm->h2c_rarpt_connect = 0;
 814         */
 815 }
 816
 817 void
 818 phydm_init_ra_info(
 819         void            *p_dm_void
 820 )
 821 {
 822         struct PHY_DM_STRUCT            *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
 823
 824 #if (RTL8822B_SUPPORT == 1)
 825         if (p_dm_odm->support_ic_type == ODM_RTL8822B) {
 826                 u32     ret_value;
 827
 828                 ret_value = odm_get_bb_reg(p_dm_odm, 0x4c8, MASKBYTE2);
 829                 odm_set_bb_reg(p_dm_odm, 0x4cc, MASKBYTE3, (ret_value - 1));
 830         }
 831 #endif
 832 }
 833
 834 void
 835 phydm_modify_RA_PCR_threshold(
 836         void            *p_dm_void,
 837         u8              RA_offset_direction,
 838         u8              RA_threshold_offset
 839
 840 )
 841 {
 842         struct PHY_DM_STRUCT            *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
 843         struct _rate_adaptive_table_                    *p_ra_table = &p_dm_odm->dm_ra_table;
 844
 845         p_ra_table->RA_offset_direction = RA_offset_direction;
 846         p_ra_table->RA_threshold_offset = RA_threshold_offset;
 847         ODM_RT_TRACE(p_dm_odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("Set RA_threshold_offset = (( %s%d ))\n", ((RA_threshold_offset == 0) ? " " : ((RA_offset_direction) ? "+" : "-")), RA_threshold_offset));
 848 }
 849
 850 void
 851 odm_rssi_monitor_check_mp(
 852         void    *p_dm_void
 853 )
 854 {
 855 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
 856         struct PHY_DM_STRUCT            *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
 857         struct _rate_adaptive_table_                    *p_ra_table = &p_dm_odm->dm_ra_table;
 858         u8                      h2c_parameter[H2C_0X42_LENGTH] = {0};
 859         u32                     i;
 860         boolean                 is_ext_ra_info = true;
 861         u8                      cmdlen = H2C_0X42_LENGTH;
 862         u8                      tx_bf_en = 0, stbc_en = 0;
 863
 864         struct _ADAPTER         *adapter = p_dm_odm->adapter;
 865         HAL_DATA_TYPE   *p_hal_data = GET_HAL_DATA(adapter);
 866         struct sta_info         *p_entry = NULL;
 867         s32                     tmp_entry_max_pwdb = 0, tmp_entry_min_pwdb = 0xff;
 868         PMGNT_INFO              p_mgnt_info = &adapter->MgntInfo;
 869         PMGNT_INFO              p_default_mgnt_info = &adapter->MgntInfo;
 870         u64                     cur_tx_ok_cnt = 0, cur_rx_ok_cnt = 0;
 871 #if (BEAMFORMING_SUPPORT == 1)
 872 #ifndef BEAMFORMING_VERSION_1
 873         enum beamforming_cap beamform_cap = BEAMFORMING_CAP_NONE;
 874 #endif
 875 #endif
 876         struct _ADAPTER *p_loop_adapter = GetDefaultAdapter(adapter);
 877
 878         if (p_dm_odm->support_ic_type == ODM_RTL8188E) {
 879                 is_ext_ra_info = false;
 880                 cmdlen = 3;
 881         }
 882
 883         while (p_loop_adapter) {
 884
 885                 if (p_loop_adapter != NULL) {
 886                         p_mgnt_info = &p_loop_adapter->MgntInfo;
 887                         cur_tx_ok_cnt = p_loop_adapter->TxStats.NumTxBytesUnicast - p_mgnt_info->lastTxOkCnt;
 888                         cur_rx_ok_cnt = p_loop_adapter->RxStats.NumRxBytesUnicast - p_mgnt_info->lastRxOkCnt;
 889                         p_mgnt_info->lastTxOkCnt = cur_tx_ok_cnt;
 890                         p_mgnt_info->lastRxOkCnt = cur_rx_ok_cnt;
 891                 }
 892
 893                 for (i = 0; i < ASSOCIATE_ENTRY_NUM; i++) {
 894
 895                         if (IsAPModeExist(p_loop_adapter)) {
 896                                 if (GetFirstExtAdapter(p_loop_adapter) != NULL &&
 897                                     GetFirstExtAdapter(p_loop_adapter) == p_loop_adapter)
 898                                 p_entry = AsocEntry_EnumStation(p_loop_adapter, i);
 899                                 else if (GetFirstGOPort(p_loop_adapter) != NULL &&
 900                                          IsFirstGoAdapter(p_loop_adapter))
 901                                 p_entry = AsocEntry_EnumStation(p_loop_adapter, i);
 902                         } else {
 903                                 if (GetDefaultAdapter(p_loop_adapter) == p_loop_adapter)
 904                                         p_entry = AsocEntry_EnumStation(p_loop_adapter, i);
 905                         }
 906
 907                         if (p_entry != NULL) {
 908                                 if (p_entry->bAssociated) {
 909
 910                                         RT_DISP_ADDR(FDM, DM_PWDB, ("p_entry->mac_addr ="), p_entry->MacAddr);
 911                                         RT_DISP(FDM, DM_PWDB, ("p_entry->rssi = 0x%x(%d)\n",
 912                                                 p_entry->rssi_stat.undecorated_smoothed_pwdb, p_entry->rssi_stat.undecorated_smoothed_pwdb));
 913
 914                                         /* 2 BF_en */
 915 #if (BEAMFORMING_SUPPORT == 1)
 916 #ifndef BEAMFORMING_VERSION_1
 917                                         beamform_cap = phydm_beamforming_get_entry_beam_cap_by_mac_id(p_dm_odm, p_entry->AssociatedMacId);
 918                                         if (beamform_cap & (BEAMFORMER_CAP_HT_EXPLICIT | BEAMFORMER_CAP_VHT_SU))
 919                                                 tx_bf_en = 1;
 920 #else
 921                                         if (Beamform_GetSupportBeamformerCap(GetDefaultAdapter(adapter), p_entry))
 922                                                 tx_bf_en = 1;
 923 #endif
 924 #endif
 925                                         /* 2 STBC_en */
 926                                         if ((IS_WIRELESS_MODE_AC(adapter) && TEST_FLAG(p_entry->VHTInfo.STBC, STBC_VHT_ENABLE_TX)) ||
 927                                             TEST_FLAG(p_entry->HTInfo.STBC, STBC_HT_ENABLE_TX))
 928                                                 stbc_en = 1;
 929
 930                                         if (p_entry->rssi_stat.undecorated_smoothed_pwdb < tmp_entry_min_pwdb)
 931                                                 tmp_entry_min_pwdb = p_entry->rssi_stat.undecorated_smoothed_pwdb;
 932                                         if (p_entry->rssi_stat.undecorated_smoothed_pwdb > tmp_entry_max_pwdb)
 933                                                 tmp_entry_max_pwdb = p_entry->rssi_stat.undecorated_smoothed_pwdb;
 934
 935                                         h2c_parameter[4] = (p_ra_table->RA_threshold_offset & 0x7f) | (p_ra_table->RA_offset_direction << 7);
 936                                         ODM_RT_TRACE(p_dm_odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("RA_threshold_offset = (( %s%d ))\n", ((p_ra_table->RA_threshold_offset == 0) ? " " : ((p_ra_table->RA_offset_direction) ? "+" : "-")), p_ra_table->RA_threshold_offset));
 937
 938                                         if (is_ext_ra_info) {
 939                                                 if (cur_rx_ok_cnt > (cur_tx_ok_cnt * 6))
 940                                                         h2c_parameter[3] |= RAINFO_BE_RX_STATE;
 941
 942                                                 if (tx_bf_en)
 943                                                         h2c_parameter[3] |= RAINFO_BF_STATE;
 944                                                 else {
 945                                                         if (stbc_en)
 946                                                                 h2c_parameter[3] |= RAINFO_STBC_STATE;
 947                                                 }
 948
 949                                                 if (p_dm_odm->noisy_decision)
 950                                                         h2c_parameter[3] |= RAINFO_NOISY_STATE;
 951                                                 else
 952                                                         h2c_parameter[3] &= (~RAINFO_NOISY_STATE);
 953 #if 1
 954                                                 if (p_dm_odm->h2c_rarpt_connect) {
 955                                                         h2c_parameter[3] |= RAINFO_INIT_RSSI_RATE_STATE;
 956                                                         ODM_RT_TRACE(p_dm_odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("h2c_rarpt_connect = (( %d ))\n", p_dm_odm->h2c_rarpt_connect));
 957                                                 }
 958 #else
 959
 960                                                 if (p_entry->rssi_stat.ra_rpt_linked == false) {
 961                                                         h2c_parameter[3] |= RAINFO_INIT_RSSI_RATE_STATE;
 962                                                         p_entry->rssi_stat.ra_rpt_linked = true;
 963
 964                                                         ODM_RT_TRACE(p_dm_odm, ODM_COMP_RSSI_MONITOR, ODM_DBG_LOUD, ("RA First Link, RSSI[%d] = ((%d))\n",
 965                                                                 p_entry->associated_mac_id, p_entry->rssi_stat.undecorated_smoothed_pwdb));
 966                                                 }
 967 #endif
 968                                         }
 969
 970                                         h2c_parameter[2] = (u8)(p_entry->rssi_stat.undecorated_smoothed_pwdb & 0xFF);
 971                                         /* h2c_parameter[1] = 0x20;   */ /* fw v12 cmdid 5:use max macid ,for nic ,default macid is 0 ,max macid is 1 */
 972                                         h2c_parameter[0] = (p_entry->AssociatedMacId);
 973
 974                                         odm_fill_h2c_cmd(p_dm_odm, ODM_H2C_RSSI_REPORT, cmdlen, h2c_parameter);
 975                                 }
 976                         } else
 977                                 break;
 978                 }
 979
 980                 p_loop_adapter = GetNextExtAdapter(p_loop_adapter);
 981         }
 982
 983
 984         /*Default port*/
 985         if (tmp_entry_max_pwdb != 0) {  /* If associated entry is found */
 986                 p_hal_data->EntryMaxUndecoratedSmoothedPWDB = tmp_entry_max_pwdb;
 987                 RT_DISP(FDM, DM_PWDB, ("EntryMaxPWDB = 0x%x(%d)\n",     tmp_entry_max_pwdb, tmp_entry_max_pwdb));
 988         } else
 989                 p_hal_data->EntryMaxUndecoratedSmoothedPWDB = 0;
 990
 991         if (tmp_entry_min_pwdb != 0xff) { /* If associated entry is found */
 992                 p_hal_data->EntryMinUndecoratedSmoothedPWDB = tmp_entry_min_pwdb;
 993                 RT_DISP(FDM, DM_PWDB, ("EntryMinPWDB = 0x%x(%d)\n", tmp_entry_min_pwdb, tmp_entry_min_pwdb));
 994
 995         } else
 996                 p_hal_data->EntryMinUndecoratedSmoothedPWDB = 0;
 997
 998         /* Default porti sent RSSI to FW */
 999         if (p_hal_data->bUseRAMask) {
1000                 ODM_RT_TRACE(p_dm_odm, ODM_COMP_RSSI_MONITOR, ODM_DBG_LOUD, ("1 RA First Link, RSSI[%d] = ((%d)) , ra_rpt_linked = ((%d))\n",
1001                         WIN_DEFAULT_PORT_MACID, p_hal_data->UndecoratedSmoothedPWDB, p_hal_data->ra_rpt_linked));
1002                 if (p_hal_data->UndecoratedSmoothedPWDB > 0) {
1003
1004                         PRT_HIGH_THROUGHPUT                     p_ht_info = GET_HT_INFO(p_default_mgnt_info);
1005                         PRT_VERY_HIGH_THROUGHPUT        p_vht_info = GET_VHT_INFO(p_default_mgnt_info);
1006
1007                         /* BF_en*/
1008 #if (BEAMFORMING_SUPPORT == 1)
1009 #ifndef BEAMFORMING_VERSION_1
1010                         beamform_cap = phydm_beamforming_get_entry_beam_cap_by_mac_id(p_dm_odm, p_default_mgnt_info->m_mac_id);
1011
1012                         if (beamform_cap & (BEAMFORMER_CAP_HT_EXPLICIT | BEAMFORMER_CAP_VHT_SU))
1013                                 tx_bf_en = 1;
1014 #else
1015                         if (Beamform_GetSupportBeamformerCap(GetDefaultAdapter(adapter), NULL))
1016                                 tx_bf_en = 1;
1017 #endif
1018 #endif
1019
1020                         /* STBC_en*/
1021                         if ((IS_WIRELESS_MODE_AC(adapter) && TEST_FLAG(p_vht_info->VhtCurStbc, STBC_VHT_ENABLE_TX)) ||
1022                             TEST_FLAG(p_ht_info->HtCurStbc, STBC_HT_ENABLE_TX))
1023                                 stbc_en = 1;
1024
1025                         h2c_parameter[4] = (p_ra_table->RA_threshold_offset & 0x7f) | (p_ra_table->RA_offset_direction << 7);
1026                         ODM_RT_TRACE(p_dm_odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("RA_threshold_offset = (( %s%d ))\n", ((p_ra_table->RA_threshold_offset == 0) ? " " : ((p_ra_table->RA_offset_direction) ? "+" : "-")), p_ra_table->RA_threshold_offset));
1027
1028                         if (is_ext_ra_info) {
1029                                 if (tx_bf_en)
1030                                         h2c_parameter[3] |= RAINFO_BF_STATE;
1031                                 else {
1032                                         if (stbc_en)
1033                                                 h2c_parameter[3] |= RAINFO_STBC_STATE;
1034                                 }
1035
1036 #if 1
1037                                 if (p_dm_odm->h2c_rarpt_connect) {
1038                                         h2c_parameter[3] |= RAINFO_INIT_RSSI_RATE_STATE;
1039                                         ODM_RT_TRACE(p_dm_odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("h2c_rarpt_connect = (( %d ))\n", p_dm_odm->h2c_rarpt_connect));
1040                                 }
1041 #else
1042                                 ODM_RT_TRACE(p_dm_odm, ODM_COMP_RSSI_MONITOR, ODM_DBG_LOUD, ("2 RA First Link, RSSI[%d] = ((%d)) , ra_rpt_linked = ((%d))\n",
1043                                         WIN_DEFAULT_PORT_MACID, p_hal_data->undecorated_smoothed_pwdb, p_hal_data->ra_rpt_linked));
1044
1045                                 if (p_hal_data->ra_rpt_linked == false) {
1046
1047                                         ODM_RT_TRACE(p_dm_odm, ODM_COMP_RSSI_MONITOR, ODM_DBG_LOUD, ("3 RA First Link, RSSI[%d] = ((%d)) , ra_rpt_linked = ((%d))\n",
1048                                                 WIN_DEFAULT_PORT_MACID, p_hal_data->undecorated_smoothed_pwdb, p_hal_data->ra_rpt_linked));
1049
1050                                         h2c_parameter[3] |= RAINFO_INIT_RSSI_RATE_STATE;
1051                                         p_hal_data->ra_rpt_linked = true;
1052
1053
1054                                 }
1055 #endif
1056
1057                                 if (p_dm_odm->noisy_decision == 1) {
1058                                         h2c_parameter[3] |= RAINFO_NOISY_STATE;
1059                                         ODM_RT_TRACE(p_dm_odm, ODM_COMP_NOISY_DETECT, ODM_DBG_LOUD, ("[RSSIMonitorCheckMP] Send H2C to FW\n"));
1060                                 } else
1061                                         h2c_parameter[3] &= (~RAINFO_NOISY_STATE);
1062
1063                                 ODM_RT_TRACE(p_dm_odm, ODM_COMP_NOISY_DETECT, ODM_DBG_LOUD, ("[RSSIMonitorCheckMP] h2c_parameter=%x\n", h2c_parameter[3]));
1064                         }
1065
1066                         h2c_parameter[2] = (u8)(p_hal_data->UndecoratedSmoothedPWDB & 0xFF);
1067                         /*h2c_parameter[1] = 0x20;*/    /* fw v12 cmdid 5:use max macid ,for nic ,default macid is 0 ,max macid is 1*/
1068                         h2c_parameter[0] = WIN_DEFAULT_PORT_MACID;              /* fw v12 cmdid 5:use max macid ,for nic ,default macid is 0 ,max macid is 1*/
1069
1070                         odm_fill_h2c_cmd(p_dm_odm, ODM_H2C_RSSI_REPORT, cmdlen, h2c_parameter);
1071                 }
1072
1073                 /* BT 3.0 HS mode rssi */
1074                 if (p_dm_odm->is_bt_hs_operation) {
1075                         h2c_parameter[2] = p_dm_odm->bt_hs_rssi;
1076                         /* h2c_parameter[1] = 0x0; */
1077                         h2c_parameter[0] = WIN_BT_PORT_MACID;
1078
1079                         odm_fill_h2c_cmd(p_dm_odm, ODM_H2C_RSSI_REPORT, cmdlen, h2c_parameter);
1080                 }
1081         } else
1082                 PlatformEFIOWrite1Byte(adapter, 0x4fe, (u8)p_hal_data->UndecoratedSmoothedPWDB);
1083
1084         if ((p_dm_odm->support_ic_type == ODM_RTL8812) || (p_dm_odm->support_ic_type == ODM_RTL8192E))
1085                 odm_rssi_dump_to_register(p_dm_odm);
1086
1087
1088         {
1089                 struct _ADAPTER *p_loop_adapter = GetDefaultAdapter(adapter);
1090                 boolean         default_pointer_value, *p_is_link_temp = &default_pointer_value;
1091                 s32     global_rssi_min = 0xFF, local_rssi_min;
1092                 boolean         is_link = false;
1093
1094                 while (p_loop_adapter) {
1095                         local_rssi_min = phydm_find_minimum_rssi(p_dm_odm, p_loop_adapter, p_is_link_temp);
1096                         /* dbg_print("p_hal_data->is_linked=%d, local_rssi_min=%d\n", p_hal_data->is_linked, local_rssi_min); */
1097
1098                         if (*p_is_link_temp)
1099                                 is_link = true;
1100
1101                         if ((local_rssi_min < global_rssi_min) && (*p_is_link_temp))
1102                                 global_rssi_min = local_rssi_min;
1103
1104                         p_loop_adapter = GetNextExtAdapter(p_loop_adapter);
1105                 }
1106
1107                 p_hal_data->bLinked = is_link;
1108                 odm_cmn_info_update(&p_hal_data->DM_OutSrc, ODM_CMNINFO_LINK, (u64)is_link);
1109
1110                 if (is_link)
1111                         odm_cmn_info_update(&p_hal_data->DM_OutSrc, ODM_CMNINFO_RSSI_MIN, (u64)global_rssi_min);
1112                 else
1113                         odm_cmn_info_update(&p_hal_data->DM_OutSrc, ODM_CMNINFO_RSSI_MIN, 0);
1114
1115         }
1116
1117 #endif  /*  #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) */
1118 }
1119
1120 #if (DM_ODM_SUPPORT_TYPE == ODM_CE)
1121 /*H2C_RSSI_REPORT*/
1122 s8 phydm_rssi_report(struct PHY_DM_STRUCT *p_dm_odm, u8 mac_id)
1123 {
1124         struct _ADAPTER *adapter = p_dm_odm->adapter;
1125         struct _rate_adaptive_table_                    *p_ra_table = &p_dm_odm->dm_ra_table;
1126         struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(adapter);
1127         HAL_DATA_TYPE *p_hal_data = GET_HAL_DATA(adapter);
1128         u8 h2c_parameter[H2C_0X42_LENGTH] = {0};
1129         u8 UL_DL_STATE = 0, STBC_TX = 0, tx_bf_en = 0;
1130         u8 cmdlen = H2C_0X42_LENGTH, first_connect = _FALSE;
1131         u64     cur_tx_ok_cnt = 0, cur_rx_ok_cnt = 0;
1132         struct sta_info *p_entry = p_dm_odm->p_odm_sta_info[mac_id];
1133
1134         if (!IS_STA_VALID(p_entry))
1135                 return _FAIL;
1136
1137         if (mac_id != p_entry->mac_id) {
1138                 ODM_RT_TRACE(p_dm_odm, ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, ("%s mac_id:%u:%u invalid\n", __func__, mac_id, p_entry->mac_id));
1139                 rtw_warn_on(1);
1140                 return _FAIL;
1141         }
1142
1143         if (IS_MCAST(p_entry->hwaddr))  /*if(psta->mac_id ==1)*/
1144                 return _FAIL;
1145
1146         if (p_dm_odm->is_in_lps_pg)
1147                 return _FAIL;
1148
1149         if (p_entry->rssi_stat.undecorated_smoothed_pwdb == (-1)) {
1150                 ODM_RT_TRACE(p_dm_odm, ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, ("%s mac_id:%u, mac:"MAC_FMT", rssi == -1\n", __func__, p_entry->mac_id, MAC_ARG(p_entry->hwaddr)));
1151                 return _FAIL;
1152         }
1153
1154         cur_tx_ok_cnt = pdvobjpriv->traffic_stat.cur_tx_bytes;
1155         cur_rx_ok_cnt = pdvobjpriv->traffic_stat.cur_rx_bytes;
1156         if (cur_rx_ok_cnt > (cur_tx_ok_cnt * 6))
1157                 UL_DL_STATE = 1;
1158         else
1159                 UL_DL_STATE = 0;
1160
1161 #ifdef CONFIG_BEAMFORMING
1162         {
1163 #if (BEAMFORMING_SUPPORT == 1)
1164                 enum beamforming_cap beamform_cap = phydm_beamforming_get_entry_beam_cap_by_mac_id(p_dm_odm, p_entry->mac_id);
1165 #else/*for drv beamforming*/
1166                 enum beamforming_cap beamform_cap = beamforming_get_entry_beam_cap_by_mac_id(&adapter->mlmepriv, p_entry->mac_id);
1167 #endif
1168
1169                 if (beamform_cap & (BEAMFORMER_CAP_HT_EXPLICIT | BEAMFORMER_CAP_VHT_SU))
1170                         tx_bf_en = 1;
1171                 else
1172                         tx_bf_en = 0;
1173         }
1174 #endif /*#ifdef CONFIG_BEAMFORMING*/
1175
1176         if (tx_bf_en)
1177                 STBC_TX = 0;
1178         else {
1179 #ifdef CONFIG_80211AC_VHT
1180                 if (is_supported_vht(p_entry->wireless_mode))
1181                         STBC_TX = TEST_FLAG(p_entry->vhtpriv.stbc_cap, STBC_VHT_ENABLE_TX);
1182                 else
1183 #endif
1184                         STBC_TX = TEST_FLAG(p_entry->htpriv.stbc_cap, STBC_HT_ENABLE_TX);
1185         }
1186
1187         h2c_parameter[0] = (u8)(p_entry->mac_id & 0xFF);
1188         h2c_parameter[2] = p_entry->rssi_stat.undecorated_smoothed_pwdb & 0x7F;
1189
1190         if (UL_DL_STATE)
1191                 h2c_parameter[3] |= RAINFO_BE_RX_STATE;
1192
1193         if (tx_bf_en)
1194                 h2c_parameter[3] |= RAINFO_BF_STATE;
1195         if (STBC_TX)
1196                 h2c_parameter[3] |= RAINFO_STBC_STATE;
1197         if (p_dm_odm->noisy_decision)
1198                 h2c_parameter[3] |= RAINFO_NOISY_STATE;
1199
1200         if ((p_entry->ra_rpt_linked == _FALSE) && (p_entry->rssi_stat.is_send_rssi == RA_RSSI_STATE_SEND)) {
1201                 h2c_parameter[3] |= RAINFO_INIT_RSSI_RATE_STATE;
1202                 p_entry->ra_rpt_linked = _TRUE;
1203                 p_entry->rssi_stat.is_send_rssi = RA_RSSI_STATE_HOLD;
1204                 first_connect = _TRUE;
1205         }
1206
1207         h2c_parameter[4] = (p_ra_table->RA_threshold_offset & 0x7f) | (p_ra_table->RA_offset_direction << 7);
1208         ODM_RT_TRACE(p_dm_odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("RA_threshold_offset = (( %s%d ))\n", ((p_ra_table->RA_threshold_offset == 0) ? " " : ((p_ra_table->RA_offset_direction) ? "+" : "-")), p_ra_table->RA_threshold_offset));
1209
1210 #if 1
1211         if (first_connect) {
1212                 ODM_RT_TRACE(p_dm_odm, ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, ("%s mac_id:%u, mac:"MAC_FMT", rssi:%d\n", __func__,
1213                         p_entry->mac_id, MAC_ARG(p_entry->hwaddr), p_entry->rssi_stat.undecorated_smoothed_pwdb));
1214
1215                 ODM_RT_TRACE(p_dm_odm, ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, ("%s RAINFO - TP:%s, TxBF:%s, STBC:%s, Noisy:%s, Firstcont:%s\n", __func__,
1216                         (UL_DL_STATE) ? "DL" : "UL", (tx_bf_en) ? "EN" : "DIS", (STBC_TX) ? "EN" : "DIS",
1217                         (p_dm_odm->noisy_decision) ? "True" : "False", (first_connect) ? "True" : "False"));
1218         }
1219 #endif
1220
1221         if (p_hal_data->fw_ractrl == _TRUE) {
1222 #if (RTL8188E_SUPPORT == 1)
1223                 if (p_dm_odm->support_ic_type == ODM_RTL8188E)
1224                         cmdlen = 3;
1225 #endif
1226                 odm_fill_h2c_cmd(p_dm_odm, ODM_H2C_RSSI_REPORT, cmdlen, h2c_parameter);
1227         } else {
1228 #if ((RTL8188E_SUPPORT == 1) && (RATE_ADAPTIVE_SUPPORT == 1))
1229                 if (p_dm_odm->support_ic_type == ODM_RTL8188E)
1230                         odm_ra_set_rssi_8188e(p_dm_odm, (u8)(p_entry->mac_id & 0xFF), p_entry->rssi_stat.undecorated_smoothed_pwdb & 0x7F);
1231 #endif
1232         }
1233         return _SUCCESS;
1234 }
1235
1236 void phydm_ra_rssi_rpt_wk_hdl(void *p_context)
1237 {
1238         struct PHY_DM_STRUCT    *p_dm_odm = (struct PHY_DM_STRUCT *)p_context;
1239         int i;
1240         u8 mac_id = 0xFF;
1241         struct sta_info *p_entry = NULL;
1242
1243         for (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++) {
1244                 p_entry = p_dm_odm->p_odm_sta_info[i];
1245                 if (IS_STA_VALID(p_entry)) {
1246                         if (IS_MCAST(p_entry->hwaddr))  /*if(psta->mac_id ==1)*/
1247                                 continue;
1248                         if (p_entry->ra_rpt_linked == _FALSE) {
1249                                 mac_id = i;
1250                                 break;
1251                         }
1252                 }
1253         }
1254         if (mac_id != 0xFF)
1255                 phydm_rssi_report(p_dm_odm, mac_id);
1256 }
1257 void phydm_ra_rssi_rpt_wk(void *p_context)
1258 {
1259         struct PHY_DM_STRUCT    *p_dm_odm = (struct PHY_DM_STRUCT *)p_context;
1260
1261         rtw_run_in_thread_cmd(p_dm_odm->adapter, phydm_ra_rssi_rpt_wk_hdl, p_dm_odm);
1262 }
1263 #endif
1264
1265 void
1266 odm_rssi_monitor_check_ce(
1267         void            *p_dm_void
1268 )
1269 {
1270 #if (DM_ODM_SUPPORT_TYPE == ODM_CE)
1271         struct PHY_DM_STRUCT            *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
1272         struct _ADAPTER         *adapter = p_dm_odm->adapter;
1273         HAL_DATA_TYPE   *p_hal_data = GET_HAL_DATA(adapter);
1274         struct sta_info           *p_entry;
1275         int     i;
1276         int     tmp_entry_max_pwdb = 0, tmp_entry_min_pwdb = 0xff;
1277         u8      sta_cnt = 0;
1278
1279         if (p_dm_odm->is_linked != _TRUE)
1280                 return;
1281
1282         for (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++) {
1283                 p_entry = p_dm_odm->p_odm_sta_info[i];
1284                 if (IS_STA_VALID(p_entry)) {
1285                         if (IS_MCAST(p_entry->hwaddr))  /*if(psta->mac_id ==1)*/
1286                                 continue;
1287
1288                         if (p_entry->rssi_stat.undecorated_smoothed_pwdb == (-1))
1289                                 continue;
1290
1291                         if (p_entry->rssi_stat.undecorated_smoothed_pwdb < tmp_entry_min_pwdb)
1292                                 tmp_entry_min_pwdb = p_entry->rssi_stat.undecorated_smoothed_pwdb;
1293
1294                         if (p_entry->rssi_stat.undecorated_smoothed_pwdb > tmp_entry_max_pwdb)
1295                                 tmp_entry_max_pwdb = p_entry->rssi_stat.undecorated_smoothed_pwdb;
1296
1297                         if (phydm_rssi_report(p_dm_odm, i))
1298                                 sta_cnt++;
1299                 }
1300         }
1301
1302         if (tmp_entry_max_pwdb != 0)    /* If associated entry is found */
1303                 p_hal_data->entry_max_undecorated_smoothed_pwdb = tmp_entry_max_pwdb;
1304         else
1305                 p_hal_data->entry_max_undecorated_smoothed_pwdb = 0;
1306
1307         if (tmp_entry_min_pwdb != 0xff) /* If associated entry is found */
1308                 p_hal_data->entry_min_undecorated_smoothed_pwdb = tmp_entry_min_pwdb;
1309         else
1310                 p_hal_data->entry_min_undecorated_smoothed_pwdb = 0;
1311
1312         find_minimum_rssi(adapter);/* get pdmpriv->min_undecorated_pwdb_for_dm */
1313
1314         p_dm_odm->rssi_min = p_hal_data->min_undecorated_pwdb_for_dm;
1315         /* odm_cmn_info_update(&p_hal_data->odmpriv,ODM_CMNINFO_RSSI_MIN, pdmpriv->min_undecorated_pwdb_for_dm); */
1316 #endif/* if (DM_ODM_SUPPORT_TYPE == ODM_CE) */
1317 }
1318
1319
1320 void
1321 odm_rssi_monitor_check_ap(
1322         void            *p_dm_void
1323 )
1324 {
1325 #if (DM_ODM_SUPPORT_TYPE == ODM_AP)
1326 #if (RTL8812A_SUPPORT || RTL8881A_SUPPORT || RTL8192E_SUPPORT || RTL8814A_SUPPORT || RTL8197F_SUPPORT)
1327
1328         struct PHY_DM_STRUCT            *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
1329         struct _rate_adaptive_table_                    *p_ra_table = &p_dm_odm->dm_ra_table;
1330         u8                      h2c_parameter[H2C_0X42_LENGTH] = {0};
1331         u32                      i;
1332         boolean                 is_ext_ra_info = true;
1333         u8                      cmdlen = H2C_0X42_LENGTH;
1334         u8                      tx_bf_en = 0, stbc_en = 0;
1335
1336         struct rtl8192cd_priv   *priv           = p_dm_odm->priv;
1337         struct sta_info *pstat;
1338         boolean                 act_bfer = false;
1339
1340 #if (BEAMFORMING_SUPPORT == 1)
1341         u8      idx = 0xff;
1342 #if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY))
1343         struct _BF_DIV_COEX_    *p_dm_bdc_table = &p_dm_odm->dm_bdc_table;
1344         p_dm_bdc_table->num_txbfee_client = 0;
1345         p_dm_bdc_table->num_txbfer_client = 0;
1346 #endif
1347 #endif
1348         if (!p_dm_odm->h2c_rarpt_connect && (priv->up_time % 2))
1349                 return;
1350
1351         if (p_dm_odm->support_ic_type == ODM_RTL8188E) {
1352                 is_ext_ra_info = false;
1353                 cmdlen = 3;
1354         }
1355
1356         for (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++) {
1357                 pstat = p_dm_odm->p_odm_sta_info[i];
1358
1359                 if (IS_STA_VALID(pstat)) {
1360                         if (pstat->sta_in_firmware != 1)
1361                                 continue;
1362
1363                         /* 2 BF_en */
1364 #if (BEAMFORMING_SUPPORT == 1)
1365                         BEAMFORMING_CAP beamform_cap = Beamforming_GetEntryBeamCapByMacId(priv, pstat->aid);
1366                         PRT_BEAMFORMING_ENTRY   p_entry = Beamforming_GetEntryByMacId(priv, pstat->aid, &idx);
1367
1368                         if (beamform_cap & (BEAMFORMER_CAP_HT_EXPLICIT | BEAMFORMER_CAP_VHT_SU))        {
1369
1370                                 if (p_entry->Sounding_En)
1371                                         tx_bf_en = 1;
1372                                 else
1373                                         tx_bf_en = 0;
1374
1375                                 act_bfer = true;
1376                         }
1377
1378 #if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY)) /*BDC*/
1379                         if (act_bfer == true) {
1380                                 p_dm_bdc_table->w_bfee_client[i] = 1; /* AP act as BFer */
1381                                 p_dm_bdc_table->num_txbfee_client++;
1382                         } else {
1383                                 p_dm_bdc_table->w_bfee_client[i] = 0; /* AP act as BFer */
1384                         }
1385
1386                         if ((beamform_cap & BEAMFORMEE_CAP_HT_EXPLICIT) || (beamform_cap & BEAMFORMEE_CAP_VHT_SU)) {
1387                                 p_dm_bdc_table->w_bfer_client[i] = 1; /* AP act as BFee */
1388                                 p_dm_bdc_table->num_txbfer_client++;
1389                         } else {
1390                                 p_dm_bdc_table->w_bfer_client[i] = 0; /* AP act as BFer */
1391                         }
1392 #endif
1393 #endif
1394
1395                         /* 2 STBC_en */
1396                         if ((priv->pmib->dot11nConfigEntry.dot11nSTBC) &&
1397                             ((pstat->ht_cap_buf.ht_cap_info & cpu_to_le16(_HTCAP_RX_STBC_CAP_))
1398 #ifdef RTK_AC_SUPPORT
1399                              || (pstat->vht_cap_buf.vht_cap_info & cpu_to_le32(_VHTCAP_RX_STBC_CAP_))
1400 #endif
1401                             ))
1402                                 stbc_en = 1;
1403
1404                         /* 2 RAINFO */
1405
1406                         h2c_parameter[4] = (p_ra_table->RA_threshold_offset & 0x7f) | (p_ra_table->RA_offset_direction << 7);
1407                         ODM_RT_TRACE(p_dm_odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("RA_threshold_offset = (( %s%d ))\n", ((p_ra_table->RA_threshold_offset == 0) ? " " : ((p_ra_table->RA_offset_direction) ? "+" : "-")), p_ra_table->RA_threshold_offset));
1408
1409                         if (is_ext_ra_info) {
1410                                 if ((pstat->rx_avarage)  > ((pstat->tx_avarage) * 6))
1411                                         h2c_parameter[3] |= RAINFO_BE_RX_STATE;
1412
1413                                 if (tx_bf_en)
1414                                         h2c_parameter[3] |= RAINFO_BF_STATE;
1415                                 else {
1416                                         if (stbc_en)
1417                                                 h2c_parameter[3] |= RAINFO_STBC_STATE;
1418                                 }
1419
1420                                 if (p_dm_odm->noisy_decision)
1421                                         h2c_parameter[3] |= RAINFO_NOISY_STATE;
1422                                 else
1423                                         h2c_parameter[3] &= (~RAINFO_NOISY_STATE);
1424
1425                                 if (pstat->H2C_rssi_rpt) {
1426                                         h2c_parameter[3] |= RAINFO_INIT_RSSI_RATE_STATE;
1427                                         ODM_RT_TRACE(p_dm_odm, ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, ("[RA Init] set Init rate by RSSI, STA %d\n", pstat->aid));
1428                                 }
1429
1430                                 /*ODM_RT_TRACE(p_dm_odm,PHYDM_COMP_RA_DBG, ODM_DBG_LOUD, ("[RAINFO] H2C_Para[3] = %x\n",h2c_parameter[3]));*/
1431                         }
1432
1433                         h2c_parameter[2] = (u8)(pstat->rssi & 0xFF);
1434                         h2c_parameter[0] = REMAP_AID(pstat);
1435
1436                         ODM_RT_TRACE(p_dm_odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("h2c_parameter[3]=%d\n", h2c_parameter[3]));
1437
1438                         /* ODM_RT_TRACE(p_dm_odm,PHYDM_COMP_RA_DBG, ODM_DBG_LOUD, ("[RSSI] H2C_Para[2] = %x,\n",h2c_parameter[2])); */
1439                         /* ODM_RT_TRACE(p_dm_odm,PHYDM_COMP_RA_DBG, ODM_DBG_LOUD, ("[MACID] H2C_Para[0] = %x,\n",h2c_parameter[0])); */
1440
1441                         odm_fill_h2c_cmd(p_dm_odm, ODM_H2C_RSSI_REPORT, cmdlen, h2c_parameter);
1442
1443                 }
1444         }
1445
1446 #endif
1447 #endif
1448
1449 }
1450
1451 void
1452 odm_rssi_monitor_check(
1453         void            *p_dm_void
1454 )
1455 {
1456         struct PHY_DM_STRUCT            *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
1457
1458         if (!(p_dm_odm->support_ability & ODM_BB_RSSI_MONITOR))
1459                 return;
1460
1461         switch  (p_dm_odm->support_platform) {
1462         case    ODM_WIN:
1463                 odm_rssi_monitor_check_mp(p_dm_odm);
1464                 break;
1465
1466         case    ODM_CE:
1467                 odm_rssi_monitor_check_ce(p_dm_odm);
1468                 break;
1469
1470         case    ODM_AP:
1471                 odm_rssi_monitor_check_ap(p_dm_odm);
1472                 break;
1473
1474         default:
1475                 break;
1476         }
1477
1478 }
1479
1480 void
1481 odm_rate_adaptive_mask_init(
1482         void    *p_dm_void
1483 )
1484 {
1485         struct PHY_DM_STRUCT            *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
1486         struct _ODM_RATE_ADAPTIVE       *p_odm_ra = &p_dm_odm->rate_adaptive;
1487
1488 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
1489         PMGNT_INFO              p_mgnt_info = &p_dm_odm->adapter->MgntInfo;
1490         HAL_DATA_TYPE   *p_hal_data = GET_HAL_DATA(p_dm_odm->adapter);
1491
1492         p_mgnt_info->Ratr_State = DM_RATR_STA_INIT;
1493
1494         if (p_mgnt_info->DM_Type == dm_type_by_driver)
1495                 p_hal_data->bUseRAMask = true;
1496         else
1497                 p_hal_data->bUseRAMask = false;
1498
1499 #elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
1500         p_odm_ra->type = dm_type_by_driver;
1501         if (p_odm_ra->type == dm_type_by_driver)
1502                 p_dm_odm->is_use_ra_mask = _TRUE;
1503         else
1504                 p_dm_odm->is_use_ra_mask = _FALSE;
1505 #endif
1506
1507         p_odm_ra->ratr_state = DM_RATR_STA_INIT;
1508
1509 #if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
1510         if (p_dm_odm->support_ic_type == ODM_RTL8812)
1511                 p_odm_ra->ldpc_thres = 50;
1512         else
1513                 p_odm_ra->ldpc_thres = 35;
1514
1515         p_odm_ra->rts_thres = 35;
1516
1517 #elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
1518         p_odm_ra->ldpc_thres = 35;
1519         p_odm_ra->is_use_ldpc = false;
1520
1521 #else
1522         p_odm_ra->ultra_low_rssi_thresh = 9;
1523
1524 #endif
1525
1526         p_odm_ra->high_rssi_thresh = 50;
1527 #if (DM_ODM_SUPPORT_TYPE == ODM_AP) && \
1528         ((DEV_BUS_TYPE == RT_USB_INTERFACE) || (DEV_BUS_TYPE == RT_SDIO_INTERFACE))
1529         p_odm_ra->low_rssi_thresh = 23;
1530 #else
1531         p_odm_ra->low_rssi_thresh = 20;
1532 #endif
1533 }
1534 /*-----------------------------------------------------------------------------
1535  * Function:    odm_refresh_rate_adaptive_mask()
1536  *
1537  * Overview:    Update rate table mask according to rssi
1538  *
1539  * Input:               NONE
1540  *
1541  * Output:              NONE
1542  *
1543  * Return:              NONE
1544  *
1545  * Revised History:
1546  *      When            Who             Remark
1547  *      05/27/2009      hpfan   Create version 0.
1548  *
1549  *---------------------------------------------------------------------------*/
1550 void
1551 odm_refresh_rate_adaptive_mask(
1552         void    *p_dm_void
1553 )
1554 {
1555         struct PHY_DM_STRUCT            *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
1556         struct _rate_adaptive_table_                    *p_ra_table = &p_dm_odm->dm_ra_table;
1557
1558         if (!p_dm_odm->is_linked)
1559                 return;
1560
1561         if (!(p_dm_odm->support_ability & ODM_BB_RA_MASK)) {
1562                 ODM_RT_TRACE(p_dm_odm, ODM_COMP_RA_MASK, ODM_DBG_TRACE, ("odm_refresh_rate_adaptive_mask(): Return cos not supported\n"));
1563                 return;
1564         }
1565
1566         p_ra_table->force_update_ra_mask_count++;
1567         /*  */
1568         /* 2011/09/29 MH In HW integration first stage, we provide 4 different handle to operate */
1569         /* at the same time. In the stage2/3, we need to prive universal interface and merge all */
1570         /* HW dynamic mechanism. */
1571         /*  */
1572         switch  (p_dm_odm->support_platform) {
1573         case    ODM_WIN:
1574                 odm_refresh_rate_adaptive_mask_mp(p_dm_odm);
1575                 break;
1576
1577         case    ODM_CE:
1578                 odm_refresh_rate_adaptive_mask_ce(p_dm_odm);
1579                 break;
1580
1581         case    ODM_AP:
1582                 odm_refresh_rate_adaptive_mask_apadsl(p_dm_odm);
1583                 break;
1584         }
1585
1586 }
1587
1588 u8
1589 phydm_trans_platform_bw(
1590         void            *p_dm_void,
1591         u8              BW
1592 )
1593 {
1594 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
1595         if (BW == CHANNEL_WIDTH_20)
1596                 BW = PHYDM_BW_20;
1597
1598         else if (BW == CHANNEL_WIDTH_40)
1599                 BW = PHYDM_BW_40;
1600
1601         else if (BW == CHANNEL_WIDTH_80)
1602                 BW = PHYDM_BW_80;
1603
1604         else if (BW == CHANNEL_WIDTH_160)
1605                 BW = PHYDM_BW_160;
1606
1607         else if (BW == CHANNEL_WIDTH_80_80)
1608                 BW = PHYDM_BW_80_80;
1609
1610 #elif (DM_ODM_SUPPORT_TYPE == ODM_AP)
1611
1612         if (BW == HT_CHANNEL_WIDTH_20)
1613                 BW = PHYDM_BW_20;
1614
1615         else if (BW == HT_CHANNEL_WIDTH_20_40)
1616                 BW = PHYDM_BW_40;
1617
1618         else if (BW == HT_CHANNEL_WIDTH_80)
1619                 BW = PHYDM_BW_80;
1620
1621         else if (BW == HT_CHANNEL_WIDTH_160)
1622                 BW = PHYDM_BW_160;
1623
1624         else if (BW == HT_CHANNEL_WIDTH_10)
1625                 BW = PHYDM_BW_10;
1626
1627         else if (BW == HT_CHANNEL_WIDTH_5)
1628                 BW = PHYDM_BW_5;
1629
1630 #elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
1631
1632         if (BW == CHANNEL_WIDTH_20)
1633                 BW = PHYDM_BW_20;
1634
1635         else if (BW == CHANNEL_WIDTH_40)
1636                 BW = PHYDM_BW_40;
1637
1638         else if (BW == CHANNEL_WIDTH_80)
1639                 BW = PHYDM_BW_80;
1640
1641         else if (BW == CHANNEL_WIDTH_160)
1642                 BW = PHYDM_BW_160;
1643
1644         else if (BW == CHANNEL_WIDTH_80_80)
1645                 BW = PHYDM_BW_80_80;
1646 #endif
1647
1648         return BW;
1649
1650 }
1651
1652 u8
1653 phydm_trans_platform_rf_type(
1654         void            *p_dm_void,
1655         u8              rf_type
1656 )
1657 {
1658 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
1659         if (rf_type == RF_1T2R)
1660                 rf_type = PHYDM_RF_1T2R;
1661
1662         else if (rf_type == RF_2T4R)
1663                 rf_type = PHYDM_RF_2T4R;
1664
1665         else if (rf_type == RF_2T2R)
1666                 rf_type = PHYDM_RF_2T2R;
1667
1668         else if (rf_type == RF_1T1R)
1669                 rf_type = PHYDM_RF_1T1R;
1670
1671         else if (rf_type == RF_2T2R_GREEN)
1672                 rf_type = PHYDM_RF_2T2R_GREEN;
1673
1674         else if (rf_type == RF_3T3R)
1675                 rf_type = PHYDM_RF_3T3R;
1676
1677         else if (rf_type == RF_4T4R)
1678                 rf_type = PHYDM_RF_4T4R;
1679
1680         else if (rf_type == RF_2T3R)
1681                 rf_type = PHYDM_RF_1T2R;
1682
1683         else if (rf_type == RF_3T4R)
1684                 rf_type = PHYDM_RF_3T4R;
1685
1686 #elif (DM_ODM_SUPPORT_TYPE == ODM_AP)
1687
1688         if (rf_type == MIMO_1T2R)
1689                 rf_type = PHYDM_RF_1T2R;
1690
1691         else if (rf_type == MIMO_2T4R)
1692                 rf_type = PHYDM_RF_2T4R;
1693
1694         else if (rf_type == MIMO_2T2R)
1695                 rf_type = PHYDM_RF_2T2R;
1696
1697         else if (rf_type == MIMO_1T1R)
1698                 rf_type = PHYDM_RF_1T1R;
1699
1700         else if (rf_type == MIMO_3T3R)
1701                 rf_type = PHYDM_RF_3T3R;
1702
1703         else if (rf_type == MIMO_4T4R)
1704                 rf_type = PHYDM_RF_4T4R;
1705
1706         else if (rf_type == MIMO_2T3R)
1707                 rf_type = PHYDM_RF_1T2R;
1708
1709         else if (rf_type == MIMO_3T4R)
1710                 rf_type = PHYDM_RF_3T4R;
1711
1712 #elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
1713
1714         if (rf_type == RF_1T2R)
1715                 rf_type = PHYDM_RF_1T2R;
1716
1717         else if (rf_type == RF_2T4R)
1718                 rf_type = PHYDM_RF_2T4R;
1719
1720         else if (rf_type == RF_2T2R)
1721                 rf_type = PHYDM_RF_2T2R;
1722
1723         else if (rf_type == RF_1T1R)
1724                 rf_type = PHYDM_RF_1T1R;
1725
1726         else if (rf_type == RF_2T2R_GREEN)
1727                 rf_type = PHYDM_RF_2T2R_GREEN;
1728
1729         else if (rf_type == RF_3T3R)
1730                 rf_type = PHYDM_RF_3T3R;
1731
1732         else if (rf_type == RF_4T4R)
1733                 rf_type = PHYDM_RF_4T4R;
1734
1735         else if (rf_type == RF_2T3R)
1736                 rf_type = PHYDM_RF_1T2R;
1737
1738         else if (rf_type == RF_3T4R)
1739                 rf_type = PHYDM_RF_3T4R;
1740
1741 #endif
1742
1743         return rf_type;
1744
1745 }
1746
1747 u32
1748 phydm_trans_platform_wireless_mode(
1749         void            *p_dm_void,
1750         u32             wireless_mode
1751 )
1752 {
1753 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
1754
1755 #elif (DM_ODM_SUPPORT_TYPE == ODM_AP)
1756
1757 #elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
1758
1759         if (wireless_mode == WIRELESS_11A)
1760                 wireless_mode = PHYDM_WIRELESS_MODE_A;
1761
1762         else if (wireless_mode == WIRELESS_11B)
1763                 wireless_mode = PHYDM_WIRELESS_MODE_B;
1764
1765         else if ((wireless_mode == WIRELESS_11G) || (wireless_mode == WIRELESS_11BG))
1766                 wireless_mode = PHYDM_WIRELESS_MODE_G;
1767
1768         else if (wireless_mode == WIRELESS_AUTO)
1769                 wireless_mode = PHYDM_WIRELESS_MODE_AUTO;
1770
1771         else if ((wireless_mode == WIRELESS_11_24N) || (wireless_mode == WIRELESS_11G_24N) || (wireless_mode == WIRELESS_11B_24N) ||
1772                 (wireless_mode == WIRELESS_11BG_24N) || (wireless_mode == WIRELESS_MODE_24G) || (wireless_mode == WIRELESS_11ABGN) || (wireless_mode == WIRELESS_11AGN))
1773                 wireless_mode = PHYDM_WIRELESS_MODE_N_24G;
1774
1775         else if ((wireless_mode == WIRELESS_11_5N) || (wireless_mode == WIRELESS_11A_5N))
1776                 wireless_mode = PHYDM_WIRELESS_MODE_N_5G;
1777
1778         else if ((wireless_mode == WIRELESS_11AC) || (wireless_mode == WIRELESS_11_5AC) || (wireless_mode == WIRELESS_MODE_5G))
1779                 wireless_mode = PHYDM_WIRELESS_MODE_AC_5G;
1780
1781         else if (wireless_mode == WIRELESS_11_24AC)
1782                 wireless_mode = PHYDM_WIRELESS_MODE_AC_24G;
1783
1784         else if (wireless_mode == WIRELESS_11AC)
1785                 wireless_mode = PHYDM_WIRELESS_MODE_AC_ONLY;
1786
1787         else if (wireless_mode == WIRELESS_MODE_MAX)
1788                 wireless_mode = PHYDM_WIRELESS_MODE_MAX;
1789         else
1790                 wireless_mode = PHYDM_WIRELESS_MODE_UNKNOWN;
1791 #endif
1792
1793         return wireless_mode;
1794
1795 }
1796
1797 u8
1798 phydm_vht_en_mapping(
1799         void                    *p_dm_void,
1800         u32                     wireless_mode
1801 )
1802 {
1803         struct PHY_DM_STRUCT            *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
1804         u8                      vht_en_out = 0;
1805
1806         if ((wireless_mode == PHYDM_WIRELESS_MODE_AC_5G) ||
1807             (wireless_mode == PHYDM_WIRELESS_MODE_AC_24G) ||
1808             (wireless_mode == PHYDM_WIRELESS_MODE_AC_ONLY)
1809            ) {
1810                 vht_en_out = 1;
1811                 /**/
1812         }
1813
1814         ODM_RT_TRACE(p_dm_odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("wireless_mode= (( 0x%x )), VHT_EN= (( %d ))\n", wireless_mode, vht_en_out));
1815         return vht_en_out;
1816 }
1817
1818 u8
1819 phydm_rate_id_mapping(
1820         void                    *p_dm_void,
1821         u32                     wireless_mode,
1822         u8                      rf_type,
1823         u8                      bw
1824 )
1825 {
1826         struct PHY_DM_STRUCT            *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
1827         u8                      rate_id_idx = 0;
1828         u8                      phydm_BW;
1829         u8                      phydm_rf_type;
1830
1831         phydm_BW = phydm_trans_platform_bw(p_dm_odm, bw);
1832         phydm_rf_type = phydm_trans_platform_rf_type(p_dm_odm, rf_type);
1833 #if (DM_ODM_SUPPORT_TYPE == ODM_CE)
1834         wireless_mode = phydm_trans_platform_wireless_mode(p_dm_odm, wireless_mode);
1835 #endif
1836
1837         ODM_RT_TRACE(p_dm_odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("wireless_mode= (( 0x%x )), rf_type = (( 0x%x )), BW = (( 0x%x ))\n",
1838                         wireless_mode, phydm_rf_type, phydm_BW));
1839
1840
1841         switch (wireless_mode) {
1842
1843         case PHYDM_WIRELESS_MODE_N_24G:
1844         {
1845
1846                 if (phydm_BW == PHYDM_BW_40) {
1847
1848                         if (phydm_rf_type == PHYDM_RF_1T1R)
1849                                 rate_id_idx = PHYDM_BGN_40M_1SS;
1850                         else if (phydm_rf_type == PHYDM_RF_2T2R)
1851                                 rate_id_idx = PHYDM_BGN_40M_2SS;
1852                         else
1853                                 rate_id_idx = PHYDM_ARFR5_N_3SS;
1854
1855                 } else {
1856
1857                         if (phydm_rf_type == PHYDM_RF_1T1R)
1858                                 rate_id_idx = PHYDM_BGN_20M_1SS;
1859                         else if (phydm_rf_type == PHYDM_RF_2T2R)
1860                                 rate_id_idx = PHYDM_BGN_20M_2SS;
1861                         else
1862                                 rate_id_idx = PHYDM_ARFR5_N_3SS;
1863                 }
1864         }
1865         break;
1866
1867         case PHYDM_WIRELESS_MODE_N_5G:
1868         {
1869                 if (phydm_rf_type == PHYDM_RF_1T1R)
1870                         rate_id_idx = PHYDM_GN_N1SS;
1871                 else if (phydm_rf_type == PHYDM_RF_2T2R)
1872                         rate_id_idx = PHYDM_GN_N2SS;
1873                 else
1874                         rate_id_idx = PHYDM_ARFR5_N_3SS;
1875         }
1876
1877         break;
1878
1879         case PHYDM_WIRELESS_MODE_G:
1880                 rate_id_idx = PHYDM_BG;
1881                 break;
1882
1883         case PHYDM_WIRELESS_MODE_A:
1884                 rate_id_idx = PHYDM_G;
1885                 break;
1886
1887         case PHYDM_WIRELESS_MODE_B:
1888                 rate_id_idx = PHYDM_B_20M;
1889                 break;
1890
1891
1892         case PHYDM_WIRELESS_MODE_AC_5G:
1893         case PHYDM_WIRELESS_MODE_AC_ONLY:
1894         {
1895                 if (phydm_rf_type == PHYDM_RF_1T1R)
1896                         rate_id_idx = PHYDM_ARFR1_AC_1SS;
1897                 else if (phydm_rf_type == PHYDM_RF_2T2R)
1898                         rate_id_idx = PHYDM_ARFR0_AC_2SS;
1899                 else
1900                         rate_id_idx = PHYDM_ARFR4_AC_3SS;
1901         }
1902         break;
1903
1904         case PHYDM_WIRELESS_MODE_AC_24G:
1905         {
1906                 /*Becareful to set "Lowest rate" while using PHYDM_ARFR4_AC_3SS in 2.4G/5G*/
1907                 if (phydm_BW >= PHYDM_BW_80) {
1908                         if (phydm_rf_type == PHYDM_RF_1T1R)
1909                                 rate_id_idx = PHYDM_ARFR1_AC_1SS;
1910                         else if (phydm_rf_type == PHYDM_RF_2T2R)
1911                                 rate_id_idx = PHYDM_ARFR0_AC_2SS;
1912                         else
1913                                 rate_id_idx = PHYDM_ARFR4_AC_3SS;
1914                 } else {
1915
1916                         if (phydm_rf_type == PHYDM_RF_1T1R)
1917                                 rate_id_idx = PHYDM_ARFR2_AC_2G_1SS;
1918                         else if (phydm_rf_type == PHYDM_RF_2T2R)
1919                                 rate_id_idx = PHYDM_ARFR3_AC_2G_2SS;
1920                         else
1921                                 rate_id_idx = PHYDM_ARFR4_AC_3SS;
1922                 }
1923         }
1924         break;
1925
1926         default:
1927                 rate_id_idx = 0;
1928                 break;
1929         }
1930
1931         ODM_RT_TRACE(p_dm_odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("RA rate ID = (( 0x%x ))\n", rate_id_idx));
1932
1933         return rate_id_idx;
1934 }
1935
1936 void
1937 phydm_update_hal_ra_mask(
1938         void                    *p_dm_void,
1939         u32                     wireless_mode,
1940         u8                      rf_type,
1941         u8                      BW,
1942         u8                      mimo_ps_enable,
1943         u8                      disable_cck_rate,
1944         u32                     *ratr_bitmap_msb_in,
1945         u32                     *ratr_bitmap_lsb_in,
1946         u8                      tx_rate_level
1947 )
1948 {
1949         struct PHY_DM_STRUCT            *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
1950         u32                     mask_rate_threshold;
1951         u8                      phydm_rf_type;
1952         u8                      phydm_BW;
1953         u32                     ratr_bitmap = *ratr_bitmap_lsb_in, ratr_bitmap_msb = *ratr_bitmap_msb_in;
1954         /*struct _ODM_RATE_ADAPTIVE*            p_ra = &(p_dm_odm->rate_adaptive);*/
1955
1956 #if (DM_ODM_SUPPORT_TYPE == ODM_CE)
1957         wireless_mode = phydm_trans_platform_wireless_mode(p_dm_odm, wireless_mode);
1958 #endif
1959
1960         phydm_rf_type = phydm_trans_platform_rf_type(p_dm_odm, rf_type);
1961         phydm_BW = phydm_trans_platform_bw(p_dm_odm, BW);
1962
1963         /*ODM_RT_TRACE(p_dm_odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("phydm_rf_type = (( %x )), rf_type = (( %x ))\n", phydm_rf_type, rf_type));*/
1964         ODM_RT_TRACE(p_dm_odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("Platfoem original RA Mask = (( 0x %x | %x ))\n", ratr_bitmap_msb, ratr_bitmap));
1965
1966         switch (wireless_mode) {
1967
1968         case PHYDM_WIRELESS_MODE_B:
1969         {
1970                 ratr_bitmap &= 0x0000000f;
1971         }
1972         break;
1973
1974         case PHYDM_WIRELESS_MODE_G:
1975         {
1976                 ratr_bitmap &= 0x00000ff5;
1977         }
1978         break;
1979
1980         case PHYDM_WIRELESS_MODE_A:
1981         {
1982                 ratr_bitmap &= 0x00000ff0;
1983         }
1984         break;
1985
1986         case PHYDM_WIRELESS_MODE_N_24G:
1987         case PHYDM_WIRELESS_MODE_N_5G:
1988         {
1989                 if (mimo_ps_enable)
1990                         phydm_rf_type = PHYDM_RF_1T1R;
1991
1992                 if (phydm_rf_type == PHYDM_RF_1T1R) {
1993
1994                         if (phydm_BW == PHYDM_BW_40)
1995                                 ratr_bitmap &= 0x000ff015;
1996                         else
1997                                 ratr_bitmap &= 0x000ff005;
1998                 } else if (phydm_rf_type == PHYDM_RF_2T2R || phydm_rf_type == PHYDM_RF_2T4R || phydm_rf_type == PHYDM_RF_2T3R) {
1999
2000                         if (phydm_BW == PHYDM_BW_40)
2001                                 ratr_bitmap &= 0x0ffff015;
2002                         else
2003                                 ratr_bitmap &= 0x0ffff005;
2004                 } else { /*3T*/
2005
2006                         ratr_bitmap &= 0xfffff015;
2007                         ratr_bitmap_msb &= 0xf;
2008                 }
2009         }
2010         break;
2011
2012         case PHYDM_WIRELESS_MODE_AC_24G:
2013         {
2014                 if (phydm_rf_type == PHYDM_RF_1T1R)
2015                         ratr_bitmap &= 0x003ff015;
2016                 else if (phydm_rf_type == PHYDM_RF_2T2R || phydm_rf_type == PHYDM_RF_2T4R || phydm_rf_type == PHYDM_RF_2T3R)
2017                         ratr_bitmap &= 0xfffff015;
2018                 else {/*3T*/
2019
2020                         ratr_bitmap &= 0xfffff010;
2021                         ratr_bitmap_msb &= 0x3ff;
2022                 }
2023
2024                 if (phydm_BW == PHYDM_BW_20) {/* AC 20MHz doesn't support MCS9 */
2025                         ratr_bitmap &= 0x7fdfffff;
2026                         ratr_bitmap_msb &= 0x1ff;
2027                 }
2028         }
2029         break;
2030
2031         case PHYDM_WIRELESS_MODE_AC_5G:
2032         {
2033                 if (phydm_rf_type == PHYDM_RF_1T1R)
2034                         ratr_bitmap &= 0x003ff010;
2035                 else if (phydm_rf_type == PHYDM_RF_2T2R || phydm_rf_type == PHYDM_RF_2T4R || phydm_rf_type == PHYDM_RF_2T3R)
2036                         ratr_bitmap &= 0xfffff010;
2037                 else {/*3T*/
2038
2039                         ratr_bitmap &= 0xfffff010;
2040                         ratr_bitmap_msb &= 0x3ff;
2041                 }
2042
2043                 if (phydm_BW == PHYDM_BW_20) {/* AC 20MHz doesn't support MCS9 */
2044                         ratr_bitmap &= 0x7fdfffff;
2045                         ratr_bitmap_msb &= 0x1ff;
2046                 }
2047         }
2048         break;
2049
2050         default:
2051                 break;
2052         }
2053
2054         if (wireless_mode != PHYDM_WIRELESS_MODE_B) {
2055
2056                 if (tx_rate_level == 0)
2057                         ratr_bitmap &=  0xffffffff;
2058                 else if (tx_rate_level == 1)
2059                         ratr_bitmap &=  0xfffffff0;
2060                 else if (tx_rate_level == 2)
2061                         ratr_bitmap &=  0xffffefe0;
2062                 else if (tx_rate_level == 3)
2063                         ratr_bitmap &=  0xffffcfc0;
2064                 else if (tx_rate_level == 4)
2065                         ratr_bitmap &=  0xffff8f80;
2066                 else if (tx_rate_level >= 5)
2067                         ratr_bitmap &=  0xffff0f00;
2068
2069         }
2070
2071         if (disable_cck_rate)
2072                 ratr_bitmap &= 0xfffffff0;
2073
2074         ODM_RT_TRACE(p_dm_odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("wireless_mode= (( 0x%x )), rf_type = (( 0x%x )), BW = (( 0x%x )), MimoPs_en = (( %d )), tx_rate_level= (( 0x%x ))\n",
2075                 wireless_mode, phydm_rf_type, phydm_BW, mimo_ps_enable, tx_rate_level));
2076
2077         /*ODM_RT_TRACE(p_dm_odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("111 Phydm modified RA Mask = (( 0x %x | %x ))\n", ratr_bitmap_msb, ratr_bitmap));*/
2078
2079         *ratr_bitmap_lsb_in = ratr_bitmap;
2080         *ratr_bitmap_msb_in = ratr_bitmap_msb;
2081         ODM_RT_TRACE(p_dm_odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("Phydm modified RA Mask = (( 0x %x | %x ))\n", *ratr_bitmap_msb_in, *ratr_bitmap_lsb_in));
2082
2083 }
2084
2085 u8
2086 phydm_RA_level_decision(
2087         void                    *p_dm_void,
2088         u32                     rssi,
2089         u8                      ratr_state
2090 )
2091 {
2092         struct PHY_DM_STRUCT    *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
2093         u8      ra_lowest_rate;
2094         u8      ra_rate_floor_table[RA_FLOOR_TABLE_SIZE] = {20, 34, 38, 42, 46, 50, 100}; /*MCS0 ~ MCS4 , VHT1SS MCS0 ~ MCS4 , G 6M~24M*/
2095         u8      new_ratr_state = 0;
2096         u8      i;
2097
2098         ODM_RT_TRACE(p_dm_odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("curr RA level = ((%d)), Rate_floor_table ori [ %d , %d, %d , %d, %d, %d]\n", ratr_state,
2099                 ra_rate_floor_table[0], ra_rate_floor_table[1], ra_rate_floor_table[2], ra_rate_floor_table[3], ra_rate_floor_table[4], ra_rate_floor_table[5]));
2100
2101         for (i = 0; i < RA_FLOOR_TABLE_SIZE; i++) {
2102
2103                 if (i >= (ratr_state))
2104                         ra_rate_floor_table[i] += RA_FLOOR_UP_GAP;
2105         }
2106
2107         ODM_RT_TRACE(p_dm_odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("RSSI = ((%d)), Rate_floor_table_mod [ %d , %d, %d , %d, %d, %d]\n",
2108                 rssi, ra_rate_floor_table[0], ra_rate_floor_table[1], ra_rate_floor_table[2], ra_rate_floor_table[3], ra_rate_floor_table[4], ra_rate_floor_table[5]));
2109
2110         for (i = 0; i < RA_FLOOR_TABLE_SIZE; i++) {
2111
2112                 if (rssi < ra_rate_floor_table[i]) {
2113                         new_ratr_state = i;
2114                         break;
2115                 }
2116         }
2117
2118
2119
2120         return  new_ratr_state;
2121
2122 }
2123
2124 void
2125 odm_refresh_rate_adaptive_mask_mp(
2126         void            *p_dm_void
2127 )
2128 {
2129 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
2130         struct PHY_DM_STRUCT                            *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
2131         struct _rate_adaptive_table_                                    *p_ra_table = &p_dm_odm->dm_ra_table;
2132         struct _ADAPTER                         *p_adapter       =  p_dm_odm->adapter;
2133         struct _ADAPTER                         *p_target_adapter = NULL;
2134         HAL_DATA_TYPE                   *p_hal_data = GET_HAL_DATA(p_adapter);
2135         PMGNT_INFO                              p_mgnt_info = GetDefaultMgntInfo(p_adapter);
2136         u32             i;
2137         struct sta_info *p_entry;
2138         u8              ratr_state_new;
2139
2140         if (p_adapter->bDriverStopped) {
2141                 ODM_RT_TRACE(p_dm_odm, ODM_COMP_RA_MASK, ODM_DBG_TRACE, ("<---- odm_refresh_rate_adaptive_mask(): driver is going to unload\n"));
2142                 return;
2143         }
2144
2145         if (!p_hal_data->bUseRAMask) {
2146                 ODM_RT_TRACE(p_dm_odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("<---- odm_refresh_rate_adaptive_mask(): driver does not control rate adaptive mask\n"));
2147                 return;
2148         }
2149
2150         /* if default port is connected, update RA table for default port (infrastructure mode only) */
2151         if (p_mgnt_info->mAssoc && (!ACTING_AS_AP(p_adapter))) {
2152                 odm_refresh_ldpc_rts_mp(p_adapter, p_dm_odm, p_mgnt_info->mMacId,  p_mgnt_info->IOTPeer, p_hal_data->UndecoratedSmoothedPWDB);
2153                 /*ODM_RT_TRACE(p_dm_odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("Infrasture mode\n"));*/
2154
2155 #if RA_MASK_PHYDMLIZE_WIN
2156                 ratr_state_new = phydm_RA_level_decision(p_dm_odm, p_hal_data->UndecoratedSmoothedPWDB, p_mgnt_info->Ratr_State);
2157
2158                 if ((p_mgnt_info->Ratr_State != ratr_state_new) || (p_ra_table->force_update_ra_mask_count >= FORCED_UPDATE_RAMASK_PERIOD)) {
2159
2160                         p_ra_table->force_update_ra_mask_count = 0;
2161                         ODM_PRINT_ADDR(p_dm_odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("Target AP addr :"), p_mgnt_info->Bssid);
2162                         ODM_RT_TRACE(p_dm_odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("Update RA Level: ((%x)) -> ((%x)),  RSSI = ((%d))\n\n",
2163                                 p_mgnt_info->Ratr_State, ratr_state_new, p_hal_data->UndecoratedSmoothedPWDB));
2164
2165                         p_mgnt_info->Ratr_State = ratr_state_new;
2166                         p_adapter->HalFunc.UpdateHalRAMaskHandler(p_adapter, p_mgnt_info->mMacId, NULL, ratr_state_new);
2167                 } else {
2168                         ODM_RT_TRACE(p_dm_odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("Stay in RA level  = (( %d ))\n\n", ratr_state_new));
2169                         /**/
2170                 }
2171
2172 #else
2173                 if (odm_ra_state_check(p_dm_odm, p_hal_data->UndecoratedSmoothedPWDB, p_mgnt_info->bSetTXPowerTrainingByOid, &p_mgnt_info->Ratr_State)) {
2174                         ODM_PRINT_ADDR(p_dm_odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("Target AP addr : "), p_mgnt_info->Bssid);
2175                         ODM_RT_TRACE(p_dm_odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("RSSI:%d, RSSI_LEVEL:%d\n", p_hal_data->UndecoratedSmoothedPWDB, p_mgnt_info->Ratr_State));
2176                         p_adapter->HalFunc.UpdateHalRAMaskHandler(p_adapter, p_mgnt_info->mMacId, NULL, p_mgnt_info->Ratr_State);
2177                 } else if (p_dm_odm->is_change_state) {
2178                         ODM_PRINT_ADDR(p_dm_odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("Target AP addr : "), p_mgnt_info->Bssid);
2179                         ODM_RT_TRACE(p_dm_odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("Change Power Training state, is_disable_power_training = %d\n", p_dm_odm->is_disable_power_training));
2180                         p_adapter->HalFunc.UpdateHalRAMaskHandler(p_adapter, p_mgnt_info->mMacId, NULL, p_mgnt_info->Ratr_State);
2181                 }
2182 #endif
2183         }
2184
2185         /*  */
2186         /* The following part configure AP/VWifi/IBSS rate adaptive mask. */
2187         /*  */
2188
2189         if (p_mgnt_info->mIbss) /* Target: AP/IBSS peer. */
2190                 p_target_adapter = GetDefaultAdapter(p_adapter);
2191         else
2192                 p_target_adapter = GetFirstAPAdapter(p_adapter);
2193
2194         /* if extension port (softap) is started, updaet RA table for more than one clients associate */
2195         if (p_target_adapter != NULL) {
2196                 for (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++) {
2197
2198                         p_entry = AsocEntry_EnumStation(p_target_adapter, i);
2199
2200                         if (IS_STA_VALID(p_entry)) {
2201
2202                                 odm_refresh_ldpc_rts_mp(p_adapter, p_dm_odm, p_entry->AssociatedMacId, p_entry->IOTPeer, p_entry->rssi_stat.undecorated_smoothed_pwdb);
2203
2204 #if RA_MASK_PHYDMLIZE_WIN
2205                                 ratr_state_new = phydm_RA_level_decision(p_dm_odm, p_entry->rssi_stat.undecorated_smoothed_pwdb, p_entry->Ratr_State);
2206
2207                                 if ((p_entry->Ratr_State != ratr_state_new) || (p_ra_table->force_update_ra_mask_count >= FORCED_UPDATE_RAMASK_PERIOD)) {
2208
2209                                         p_ra_table->force_update_ra_mask_count = 0;
2210                                         ODM_PRINT_ADDR(p_dm_odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("Target AP addr :"), p_entry->MacAddr);
2211                                         ODM_RT_TRACE(p_dm_odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("Update Tx RA Level: ((%x)) -> ((%x)),  RSSI = ((%d))\n",
2212                                                 p_entry->Ratr_State, ratr_state_new,  p_entry->rssi_stat.undecorated_smoothed_pwdb));
2213
2214                                         p_entry->Ratr_State = ratr_state_new;
2215                                         p_adapter->HalFunc.UpdateHalRAMaskHandler(p_adapter, p_entry->AssociatedMacId, NULL, ratr_state_new);
2216                                 } else {
2217                                         ODM_RT_TRACE(p_dm_odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("Stay in RA level  = (( %d ))\n\n", ratr_state_new));
2218                                         /**/
2219                                 }
2220
2221
2222 #else
2223
2224                                 if (odm_ra_state_check(p_dm_odm, p_entry->rssi_stat.undecorated_smoothed_pwdb, p_mgnt_info->bSetTXPowerTrainingByOid, &p_entry->Ratr_State)) {
2225                                         ODM_PRINT_ADDR(p_dm_odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("Target STA addr : "), p_entry->mac_addr);
2226                                         ODM_RT_TRACE(p_dm_odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("RSSI:%d, RSSI_LEVEL:%d\n", p_entry->rssi_stat.undecorated_smoothed_pwdb, p_entry->Ratr_State));
2227                                         p_adapter->hal_func.update_hal_ra_mask_handler(p_target_adapter, p_entry->AssociatedMacId, p_entry, p_entry->Ratr_State);
2228                                 } else if (p_dm_odm->is_change_state) {
2229                                         ODM_RT_TRACE(p_dm_odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("Change Power Training state, is_disable_power_training = %d\n", p_dm_odm->is_disable_power_training));
2230                                         p_adapter->HalFunc.UpdateHalRAMaskHandler(p_adapter, p_mgnt_info->mMacId, NULL, p_mgnt_info->Ratr_State);
2231                                 }
2232 #endif
2233
2234                         }
2235                 }
2236         }
2237
2238 #if RA_MASK_PHYDMLIZE_WIN
2239
2240 #else
2241         if (p_mgnt_info->bSetTXPowerTrainingByOid)
2242                 p_mgnt_info->bSetTXPowerTrainingByOid = false;
2243 #endif
2244 #endif  /*  #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) */
2245 }
2246
2247
2248 void
2249 odm_refresh_rate_adaptive_mask_ce(
2250         void    *p_dm_void
2251 )
2252 {
2253 #if (DM_ODM_SUPPORT_TYPE == ODM_CE)
2254         struct PHY_DM_STRUCT            *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
2255         struct _rate_adaptive_table_                    *p_ra_table = &p_dm_odm->dm_ra_table;
2256         struct _ADAPTER *p_adapter       =  p_dm_odm->adapter;
2257         struct _ODM_RATE_ADAPTIVE               *p_ra = &p_dm_odm->rate_adaptive;
2258         u32             i;
2259         struct sta_info *p_entry;
2260         u8              ratr_state_new;
2261
2262         if (RTW_CANNOT_RUN(p_adapter)) {
2263                 ODM_RT_TRACE(p_dm_odm, ODM_COMP_RA_MASK, ODM_DBG_TRACE, ("<---- odm_refresh_rate_adaptive_mask(): driver is going to unload\n"));
2264                 return;
2265         }
2266
2267         if (!p_dm_odm->is_use_ra_mask) {
2268                 ODM_RT_TRACE(p_dm_odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("<---- odm_refresh_rate_adaptive_mask(): driver does not control rate adaptive mask\n"));
2269                 return;
2270         }
2271
2272         for (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++) {
2273
2274                 p_entry = p_dm_odm->p_odm_sta_info[i];
2275
2276                 if (IS_STA_VALID(p_entry)) {
2277
2278                         if (IS_MCAST(p_entry->hwaddr))
2279                                 continue;
2280
2281 #if ((RTL8812A_SUPPORT == 1) || (RTL8821A_SUPPORT == 1))
2282                         if ((p_dm_odm->support_ic_type == ODM_RTL8812) || (p_dm_odm->support_ic_type == ODM_RTL8821)) {
2283                                 if (p_entry->rssi_stat.undecorated_smoothed_pwdb < p_ra->ldpc_thres) {
2284                                         p_ra->is_use_ldpc = true;
2285                                         p_ra->is_lower_rts_rate = true;
2286                                         if ((p_dm_odm->support_ic_type == ODM_RTL8821) && (p_dm_odm->cut_version == ODM_CUT_A))
2287                                                 set_ra_ldpc_8812(p_entry, true);
2288                                         /* dbg_print("RSSI=%d, is_use_ldpc = true\n", p_hal_data->undecorated_smoothed_pwdb); */
2289                                 } else if (p_entry->rssi_stat.undecorated_smoothed_pwdb > (p_ra->ldpc_thres - 5)) {
2290                                         p_ra->is_use_ldpc = false;
2291                                         p_ra->is_lower_rts_rate = false;
2292                                         if ((p_dm_odm->support_ic_type == ODM_RTL8821) && (p_dm_odm->cut_version == ODM_CUT_A))
2293                                                 set_ra_ldpc_8812(p_entry, false);
2294                                         /* dbg_print("RSSI=%d, is_use_ldpc = false\n", p_hal_data->undecorated_smoothed_pwdb); */
2295                                 }
2296                         }
2297 #endif
2298
2299 #if RA_MASK_PHYDMLIZE_CE
2300                         ratr_state_new = phydm_RA_level_decision(p_dm_odm, p_entry->rssi_stat.undecorated_smoothed_pwdb, p_entry->rssi_level);
2301
2302                         if ((p_entry->rssi_level != ratr_state_new) || (p_ra_table->force_update_ra_mask_count >= FORCED_UPDATE_RAMASK_PERIOD)) {
2303
2304                                 p_ra_table->force_update_ra_mask_count = 0;
2305                                 /*ODM_PRINT_ADDR(p_dm_odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("Target AP addr :"), pstat->hwaddr);*/
2306                                 ODM_RT_TRACE(p_dm_odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("Update Tx RA Level: ((%x)) -> ((%x)),  RSSI = ((%d))\n",
2307                                         p_entry->rssi_level, ratr_state_new, p_entry->rssi_stat.undecorated_smoothed_pwdb));
2308
2309                                 p_entry->rssi_level = ratr_state_new;
2310                                 rtw_hal_update_ra_mask(p_entry, p_entry->rssi_level, _FALSE);
2311                         } else {
2312                                 ODM_RT_TRACE(p_dm_odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("Stay in RA level  = (( %d ))\n\n", ratr_state_new));
2313                                 /**/
2314                         }
2315 #else
2316                         if (true == odm_ra_state_check(p_dm_odm, p_entry->rssi_stat.undecorated_smoothed_pwdb, false, &p_entry->rssi_level)) {
2317                                 ODM_RT_TRACE(p_dm_odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("RSSI:%d, RSSI_LEVEL:%d\n", p_entry->rssi_stat.undecorated_smoothed_pwdb, p_entry->rssi_level));
2318                                 /* printk("RSSI:%d, RSSI_LEVEL:%d\n", pstat->rssi_stat.undecorated_smoothed_pwdb, pstat->rssi_level); */
2319                                 rtw_hal_update_ra_mask(p_entry, p_entry->rssi_level, _FALSE);
2320                         } else if (p_dm_odm->is_change_state) {
2321                                 ODM_RT_TRACE(p_dm_odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("Change Power Training state, is_disable_power_training = %d\n", p_dm_odm->is_disable_power_training));
2322                                 rtw_hal_update_ra_mask(p_entry, p_entry->rssi_level, _FALSE);
2323                         }
2324 #endif
2325
2326                 }
2327         }
2328
2329 #endif
2330 }
2331
2332 #if (DM_ODM_SUPPORT_TYPE & ODM_AP)
2333 void
2334 phydm_gen_ramask_h2c_AP(
2335         void                    *p_dm_void,
2336         struct rtl8192cd_priv *priv,
2337         struct sta_info *p_entry,
2338         u8                      rssi_level
2339 )
2340 {
2341         struct PHY_DM_STRUCT    *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
2342
2343         if (p_dm_odm->support_ic_type == ODM_RTL8812) {
2344
2345 #if (RTL8812A_SUPPORT == 1)
2346                 UpdateHalRAMask8812(priv, p_entry, rssi_level);
2347                 /**/
2348 #endif
2349         } else if (p_dm_odm->support_ic_type == ODM_RTL8188E) {
2350
2351 #if (RTL8188E_SUPPORT == 1)
2352 #ifdef TXREPORT
2353                 add_RATid(priv, p_entry);
2354                 /**/
2355 #endif
2356 #endif
2357         } else {
2358
2359 #ifdef CONFIG_WLAN_HAL
2360                 GET_HAL_INTERFACE(priv)->UpdateHalRAMaskHandler(priv, p_entry, rssi_level);
2361 #endif
2362
2363         }
2364 }
2365
2366 #endif
2367
2368 void
2369 odm_refresh_rate_adaptive_mask_apadsl(
2370         void    *p_dm_void
2371 )
2372 {
2373 #if (DM_ODM_SUPPORT_TYPE & ODM_AP)
2374         struct PHY_DM_STRUCT            *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
2375         struct _rate_adaptive_table_                    *p_ra_table = &p_dm_odm->dm_ra_table;
2376         struct rtl8192cd_priv *priv = p_dm_odm->priv;
2377         struct aid_obj *aidarray;
2378         u32             i;
2379         struct sta_info *p_entry;
2380         u8              ratr_state_new;
2381
2382         if (priv->up_time % 2)
2383                 return;
2384
2385         for (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++) {
2386                 p_entry = p_dm_odm->p_odm_sta_info[i];
2387
2388                 if (IS_STA_VALID(p_entry)) {
2389
2390 #if defined(UNIVERSAL_REPEATER) || defined(MBSSID)
2391                         aidarray = container_of(p_entry, struct aid_obj, station);
2392                         priv = aidarray->priv;
2393 #endif
2394
2395                         if (!priv->pmib->dot11StationConfigEntry.autoRate)
2396                                 continue;
2397
2398 #if RA_MASK_PHYDMLIZE_AP
2399                         ratr_state_new = phydm_RA_level_decision(p_dm_odm, (u32)p_entry->rssi, p_entry->rssi_level);
2400
2401                         if ((p_entry->rssi_level != ratr_state_new) || (p_ra_table->force_update_ra_mask_count >= FORCED_UPDATE_RAMASK_PERIOD)) {
2402
2403                                 p_ra_table->force_update_ra_mask_count = 0;
2404                                 ODM_PRINT_ADDR(p_dm_odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("Target AP addr :"), p_entry->hwaddr);
2405                                 ODM_RT_TRACE(p_dm_odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("Update Tx RA Level: ((%x)) -> ((%x)),  RSSI = ((%d))\n", p_entry->rssi_level, ratr_state_new, p_entry->rssi));
2406
2407                                 p_entry->rssi_level = ratr_state_new;
2408                                 phydm_gen_ramask_h2c_AP(p_dm_odm, priv, p_entry, p_entry->rssi_level);
2409                         } else {
2410                                 ODM_RT_TRACE(p_dm_odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("Stay in RA level  = (( %d ))\n\n", ratr_state_new));
2411                                 /**/
2412                         }
2413
2414 #else
2415                         if (odm_ra_state_check(p_dm_odm, (s32)p_entry->rssi, false, &p_entry->rssi_level)) {
2416                                 ODM_PRINT_ADDR(p_dm_odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("Target STA addr : "), p_entry->hwaddr);
2417                                 ODM_RT_TRACE(p_dm_odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("RSSI:%d, RSSI_LEVEL:%d\n", p_entry->rssi, p_entry->rssi_level));
2418
2419 #ifdef CONFIG_WLAN_HAL
2420                                 if (IS_HAL_CHIP(priv)) {
2421 #ifdef WDS
2422                                         /*if(!(pstat->state & WIFI_WDS))*/      /*if WDS donot setting*/
2423 #endif
2424                                         GET_HAL_INTERFACE(priv)->update_hal_ra_mask_handler(priv, p_entry, p_entry->rssi_level);
2425                                 } else
2426 #endif
2427
2428 #ifdef CONFIG_RTL_8812_SUPPORT
2429                                         if (GET_CHIP_VER(priv) == VERSION_8812E)
2430                                                 update_hal_ra_mask8812(priv, p_entry, 3);
2431                                         else
2432 #endif
2433                                         {
2434 #ifdef CONFIG_RTL_88E_SUPPORT
2435                                                 if (GET_CHIP_VER(priv) == VERSION_8188E) {
2436 #ifdef TXREPORT
2437                                                         add_ra_tid(priv, p_entry);
2438 #endif
2439                                                 }
2440 #endif
2441
2442
2443                                         }
2444                         }
2445 #endif /*#ifdef RA_MASK_PHYDMLIZE*/
2446
2447                 }
2448         }
2449 #endif /*#if (DM_ODM_SUPPORT_TYPE & ODM_AP)*/
2450 }
2451
2452 void
2453 odm_refresh_basic_rate_mask(
2454         void    *p_dm_void
2455 )
2456 {
2457 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
2458         struct PHY_DM_STRUCT            *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
2459         struct _ADAPTER         *adapter         =  p_dm_odm->adapter;
2460         static u8               stage = 0;
2461         u8                      cur_stage = 0;
2462         OCTET_STRING    os_rate_set;
2463         PMGNT_INFO              p_mgnt_info = GetDefaultMgntInfo(adapter);
2464         u8                      rate_set[5] = {MGN_1M, MGN_2M, MGN_5_5M, MGN_11M, MGN_6M};
2465
2466         if (p_dm_odm->support_ic_type != ODM_RTL8812 && p_dm_odm->support_ic_type != ODM_RTL8821)
2467                 return;
2468
2469         if (p_dm_odm->is_linked == false)       /* unlink Default port information */
2470                 cur_stage = 0;
2471         else if (p_dm_odm->rssi_min < 40)       /* link RSSI  < 40% */
2472                 cur_stage = 1;
2473         else if (p_dm_odm->rssi_min > 45)       /* link RSSI > 45% */
2474                 cur_stage = 3;
2475         else
2476                 cur_stage = 2;                                  /* link  25% <= RSSI <= 30% */
2477
2478         if (cur_stage != stage) {
2479                 if (cur_stage == 1) {
2480                         FillOctetString(os_rate_set, rate_set, 5);
2481                         FilterSupportRate(p_mgnt_info->mBrates, &os_rate_set, false);
2482                         phydm_set_hw_reg_handler_interface(p_dm_odm, HW_VAR_BASIC_RATE, (u8 *)&os_rate_set);
2483                 } else if (cur_stage == 3 && (stage == 1 || stage == 2))
2484                         phydm_set_hw_reg_handler_interface(p_dm_odm, HW_VAR_BASIC_RATE, (u8 *)(&p_mgnt_info->mBrates));
2485         }
2486
2487         stage = cur_stage;
2488 #endif
2489 }
2490
2491 u8
2492 phydm_rate_order_compute(
2493         void    *p_dm_void,
2494         u8      rate_idx
2495 )
2496 {
2497         struct PHY_DM_STRUCT    *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
2498         u8              rate_order = 0;
2499
2500         if (rate_idx >= ODM_RATEVHTSS4MCS0) {
2501
2502                 rate_idx -= ODM_RATEVHTSS4MCS0;
2503                 /**/
2504         } else if (rate_idx >= ODM_RATEVHTSS3MCS0) {
2505
2506                 rate_idx -= ODM_RATEVHTSS3MCS0;
2507                 /**/
2508         } else if (rate_idx >= ODM_RATEVHTSS2MCS0) {
2509
2510                 rate_idx -= ODM_RATEVHTSS2MCS0;
2511                 /**/
2512         } else if (rate_idx >= ODM_RATEVHTSS1MCS0) {
2513
2514                 rate_idx -= ODM_RATEVHTSS1MCS0;
2515                 /**/
2516         } else if (rate_idx >= ODM_RATEMCS24) {
2517
2518                 rate_idx -= ODM_RATEMCS24;
2519                 /**/
2520         } else if (rate_idx >= ODM_RATEMCS16) {
2521
2522                 rate_idx -= ODM_RATEMCS16;
2523                 /**/
2524         } else if (rate_idx >= ODM_RATEMCS8) {
2525
2526                 rate_idx -= ODM_RATEMCS8;
2527                 /**/
2528         }
2529         rate_order = rate_idx;
2530
2531         return rate_order;
2532
2533 }
2534
2535 void
2536 phydm_ra_common_info_update(
2537         void    *p_dm_void
2538 )
2539 {
2540         struct PHY_DM_STRUCT    *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
2541         struct _rate_adaptive_table_            *p_ra_table = &p_dm_odm->dm_ra_table;
2542         u16             macid;
2543         u8              rate_order_tmp;
2544         u8              cnt = 0;
2545
2546         p_ra_table->highest_client_tx_order = 0;
2547         p_ra_table->power_tracking_flag = 1;
2548
2549         if (p_dm_odm->number_linked_client != 0) {
2550                 for (macid = 0; macid < ODM_ASSOCIATE_ENTRY_NUM; macid++) {
2551
2552                         rate_order_tmp = phydm_rate_order_compute(p_dm_odm, ((p_ra_table->link_tx_rate[macid]) & 0x7f));
2553
2554                         if (rate_order_tmp >= (p_ra_table->highest_client_tx_order)) {
2555                                 p_ra_table->highest_client_tx_order = rate_order_tmp;
2556                                 p_ra_table->highest_client_tx_rate_order = macid;
2557                         }
2558
2559                         cnt++;
2560
2561                         if (cnt == p_dm_odm->number_linked_client)
2562                                 break;
2563                 }
2564                 ODM_RT_TRACE(p_dm_odm, ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, ("MACID[%d], Highest Tx order Update for power traking: %d\n", (p_ra_table->highest_client_tx_rate_order), (p_ra_table->highest_client_tx_order)));
2565         }
2566 }
2567
2568 void
2569 phydm_ra_info_watchdog(
2570         void    *p_dm_void
2571 )
2572 {
2573         struct PHY_DM_STRUCT    *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
2574
2575         phydm_ra_common_info_update(p_dm_odm);
2576         phydm_ra_dynamic_retry_limit(p_dm_odm);
2577         phydm_ra_dynamic_retry_count(p_dm_odm);
2578         odm_refresh_rate_adaptive_mask(p_dm_odm);
2579         odm_refresh_basic_rate_mask(p_dm_odm);
2580 }
2581
2582 void
2583 phydm_ra_info_init(
2584         void    *p_dm_void
2585 )
2586 {
2587         struct PHY_DM_STRUCT    *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
2588         struct _rate_adaptive_table_            *p_ra_table = &p_dm_odm->dm_ra_table;
2589
2590         p_ra_table->highest_client_tx_rate_order = 0;
2591         p_ra_table->highest_client_tx_order = 0;
2592         p_ra_table->RA_threshold_offset = 0;
2593         p_ra_table->RA_offset_direction = 0;
2594
2595 #if (defined(CONFIG_RA_DYNAMIC_RTY_LIMIT))
2596         phydm_ra_dynamic_retry_limit_init(p_dm_odm);
2597 #endif
2598
2599 #if (defined(CONFIG_RA_DYNAMIC_RATE_ID))
2600         phydm_ra_dynamic_rate_id_init(p_dm_odm);
2601 #endif
2602 #if (defined(CONFIG_RA_DBG_CMD))
2603         odm_ra_para_adjust_init(p_dm_odm);
2604 #endif
2605
2606 }
2607
2608
2609 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
2610 u8
2611 odm_find_rts_rate(
2612         void                    *p_dm_void,
2613         u8                      tx_rate,
2614         boolean                 is_erp_protect
2615 )
2616 {
2617         struct PHY_DM_STRUCT            *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
2618         u8      rts_ini_rate = ODM_RATE6M;
2619
2620         if (is_erp_protect) /* use CCK rate as RTS*/
2621                 rts_ini_rate = ODM_RATE1M;
2622         else {
2623                 switch (tx_rate) {
2624                 case ODM_RATEVHTSS3MCS9:
2625                 case ODM_RATEVHTSS3MCS8:
2626                 case ODM_RATEVHTSS3MCS7:
2627                 case ODM_RATEVHTSS3MCS6:
2628                 case ODM_RATEVHTSS3MCS5:
2629                 case ODM_RATEVHTSS3MCS4:
2630                 case ODM_RATEVHTSS3MCS3:
2631                 case ODM_RATEVHTSS2MCS9:
2632                 case ODM_RATEVHTSS2MCS8:
2633                 case ODM_RATEVHTSS2MCS7:
2634                 case ODM_RATEVHTSS2MCS6:
2635                 case ODM_RATEVHTSS2MCS5:
2636                 case ODM_RATEVHTSS2MCS4:
2637                 case ODM_RATEVHTSS2MCS3:
2638                 case ODM_RATEVHTSS1MCS9:
2639                 case ODM_RATEVHTSS1MCS8:
2640                 case ODM_RATEVHTSS1MCS7:
2641                 case ODM_RATEVHTSS1MCS6:
2642                 case ODM_RATEVHTSS1MCS5:
2643                 case ODM_RATEVHTSS1MCS4:
2644                 case ODM_RATEVHTSS1MCS3:
2645                 case ODM_RATEMCS15:
2646                 case ODM_RATEMCS14:
2647                 case ODM_RATEMCS13:
2648                 case ODM_RATEMCS12:
2649                 case ODM_RATEMCS11:
2650                 case ODM_RATEMCS7:
2651                 case ODM_RATEMCS6:
2652                 case ODM_RATEMCS5:
2653                 case ODM_RATEMCS4:
2654                 case ODM_RATEMCS3:
2655                 case ODM_RATE54M:
2656                 case ODM_RATE48M:
2657                 case ODM_RATE36M:
2658                 case ODM_RATE24M:
2659                         rts_ini_rate = ODM_RATE24M;
2660                         break;
2661                 case ODM_RATEVHTSS3MCS2:
2662                 case ODM_RATEVHTSS3MCS1:
2663                 case ODM_RATEVHTSS2MCS2:
2664                 case ODM_RATEVHTSS2MCS1:
2665                 case ODM_RATEVHTSS1MCS2:
2666                 case ODM_RATEVHTSS1MCS1:
2667                 case ODM_RATEMCS10:
2668                 case ODM_RATEMCS9:
2669                 case ODM_RATEMCS2:
2670                 case ODM_RATEMCS1:
2671                 case ODM_RATE18M:
2672                 case ODM_RATE12M:
2673                         rts_ini_rate = ODM_RATE12M;
2674                         break;
2675                 case ODM_RATEVHTSS3MCS0:
2676                 case ODM_RATEVHTSS2MCS0:
2677                 case ODM_RATEVHTSS1MCS0:
2678                 case ODM_RATEMCS8:
2679                 case ODM_RATEMCS0:
2680                 case ODM_RATE9M:
2681                 case ODM_RATE6M:
2682                         rts_ini_rate = ODM_RATE6M;
2683                         break;
2684                 case ODM_RATE11M:
2685                 case ODM_RATE5_5M:
2686                 case ODM_RATE2M:
2687                 case ODM_RATE1M:
2688                         rts_ini_rate = ODM_RATE1M;
2689                         break;
2690                 default:
2691                         rts_ini_rate = ODM_RATE6M;
2692                         break;
2693                 }
2694         }
2695
2696         if (*p_dm_odm->p_band_type == 1) {
2697                 if (rts_ini_rate < ODM_RATE6M)
2698                         rts_ini_rate = ODM_RATE6M;
2699         }
2700         return rts_ini_rate;
2701
2702 }
2703
2704 void
2705 odm_set_ra_dm_arfb_by_noisy(
2706         struct PHY_DM_STRUCT    *p_dm_odm
2707 )
2708 {
2709 #if 0
2710
2711         /*dbg_print("DM_ARFB ====>\n");*/
2712         if (p_dm_odm->is_noisy_state) {
2713                 odm_write_4byte(p_dm_odm, 0x430, 0x00000000);
2714                 odm_write_4byte(p_dm_odm, 0x434, 0x05040200);
2715                 /*dbg_print("DM_ARFB ====> Noisy state\n");*/
2716         } else {
2717                 odm_write_4byte(p_dm_odm, 0x430, 0x02010000);
2718                 odm_write_4byte(p_dm_odm, 0x434, 0x07050403);
2719                 /*dbg_print("DM_ARFB ====> Clean state\n");*/
2720         }
2721 #endif
2722 }
2723
2724 void
2725 odm_update_noisy_state(
2726         void            *p_dm_void,
2727         boolean         is_noisy_state_from_c2h
2728 )
2729 {
2730         struct PHY_DM_STRUCT            *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
2731
2732 /* JJ ADD 20161014 */
2733         /*dbg_print("Get C2H Command! NoisyState=0x%x\n ", is_noisy_state_from_c2h);*/
2734         if (p_dm_odm->support_ic_type == ODM_RTL8821  || p_dm_odm->support_ic_type == ODM_RTL8812  ||
2735             p_dm_odm->support_ic_type == ODM_RTL8723B || p_dm_odm->support_ic_type == ODM_RTL8192E || p_dm_odm->support_ic_type == ODM_RTL8188E || p_dm_odm->support_ic_type == ODM_RTL8723D || p_dm_odm->support_ic_type == ODM_RTL8710B)
2736                 p_dm_odm->is_noisy_state = is_noisy_state_from_c2h;
2737         odm_set_ra_dm_arfb_by_noisy(p_dm_odm);
2738 };
2739
2740 void
2741 phydm_update_pwr_track(
2742         void            *p_dm_void,
2743         u8              rate
2744 )
2745 {
2746         struct PHY_DM_STRUCT            *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
2747         u8                      path_idx = 0;
2748
2749         ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("Pwr Track Get rate=0x%x\n", rate));
2750
2751         p_dm_odm->tx_rate = rate;
2752
2753 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
2754 #if DEV_BUS_TYPE == RT_PCI_INTERFACE
2755 #if USE_WORKITEM
2756         odm_schedule_work_item(&p_dm_odm->ra_rpt_workitem);
2757 #else
2758         if (p_dm_odm->support_ic_type == ODM_RTL8821) {
2759 #if (RTL8821A_SUPPORT == 1)
2760                 odm_tx_pwr_track_set_pwr8821a(p_dm_odm, MIX_MODE, ODM_RF_PATH_A, 0);
2761 #endif
2762         } else if (p_dm_odm->support_ic_type == ODM_RTL8812) {
2763                 for (path_idx = ODM_RF_PATH_A; path_idx < MAX_PATH_NUM_8812A; path_idx++) {
2764 #if (RTL8812A_SUPPORT == 1)
2765                         odm_tx_pwr_track_set_pwr8812a(p_dm_odm, MIX_MODE, path_idx, 0);
2766 #endif
2767                 }
2768         } else if (p_dm_odm->support_ic_type == ODM_RTL8723B) {
2769 #if (RTL8723B_SUPPORT == 1)
2770                 odm_tx_pwr_track_set_pwr_8723b(p_dm_odm, MIX_MODE, ODM_RF_PATH_A, 0);
2771 #endif
2772         } else if (p_dm_odm->support_ic_type == ODM_RTL8192E) {
2773                 for (path_idx = ODM_RF_PATH_A; path_idx < MAX_PATH_NUM_8192E; path_idx++) {
2774 #if (RTL8192E_SUPPORT == 1)
2775                         odm_tx_pwr_track_set_pwr92_e(p_dm_odm, MIX_MODE, path_idx, 0);
2776 #endif
2777                 }
2778         } else if (p_dm_odm->support_ic_type == ODM_RTL8188E) {
2779 #if (RTL8188E_SUPPORT == 1)
2780                 odm_tx_pwr_track_set_pwr88_e(p_dm_odm, MIX_MODE, ODM_RF_PATH_A, 0);
2781 #endif
2782         }
2783 #endif
2784 #else
2785         odm_schedule_work_item(&p_dm_odm->ra_rpt_workitem);
2786 #endif
2787 #endif
2788
2789 }
2790
2791 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
2792
2793 s32
2794 phydm_find_minimum_rssi(
2795         struct PHY_DM_STRUCT            *p_dm_odm,
2796         struct _ADAPTER         *p_adapter,
2797         OUT     boolean                 *p_is_link_temp
2798
2799 )
2800 {
2801         HAL_DATA_TYPE   *p_hal_data = GET_HAL_DATA(p_adapter);
2802         PMGNT_INFO              p_mgnt_info = &(p_adapter->MgntInfo);
2803         boolean                 act_as_ap = ACTING_AS_AP(p_adapter);
2804
2805         /* 1.Determine the minimum RSSI */
2806         if ((!p_mgnt_info->bMediaConnect) ||
2807             (act_as_ap && (p_hal_data->EntryMinUndecoratedSmoothedPWDB == 0))) {/* We should check AP mode and Entry info.into consideration, revised by Roger, 2013.10.18*/
2808
2809                 p_hal_data->MinUndecoratedPWDBForDM = 0;
2810                 *p_is_link_temp = false;
2811
2812         } else
2813                 *p_is_link_temp = true;
2814
2815
2816         if (p_mgnt_info->bMediaConnect) {       /* Default port*/
2817
2818                 if (act_as_ap || p_mgnt_info->mIbss) {
2819                         p_hal_data->MinUndecoratedPWDBForDM = p_hal_data->EntryMinUndecoratedSmoothedPWDB;
2820                         /**/
2821                 } else {
2822                         p_hal_data->MinUndecoratedPWDBForDM = p_hal_data->UndecoratedSmoothedPWDB;
2823                         /**/
2824                 }
2825         } else { /* associated entry pwdb*/
2826                 p_hal_data->MinUndecoratedPWDBForDM = p_hal_data->EntryMinUndecoratedSmoothedPWDB;
2827                 /**/
2828         }
2829
2830         return p_hal_data->MinUndecoratedPWDBForDM;
2831 }
2832
2833 void
2834 odm_update_init_rate_work_item_callback(
2835         void    *p_context
2836 )
2837 {
2838         struct _ADAPTER *adapter = (struct _ADAPTER *)p_context;
2839         HAL_DATA_TYPE   *p_hal_data = GET_HAL_DATA(adapter);
2840         struct PHY_DM_STRUCT            *p_dm_odm = &p_hal_data->DM_OutSrc;
2841         u8              p = 0;
2842
2843         if (p_dm_odm->support_ic_type == ODM_RTL8821) {
2844                 odm_tx_pwr_track_set_pwr8821a(p_dm_odm, MIX_MODE, ODM_RF_PATH_A, 0);
2845                 /**/
2846         } else if (p_dm_odm->support_ic_type == ODM_RTL8812) {
2847                 for (p = ODM_RF_PATH_A; p < MAX_PATH_NUM_8812A; p++) {    /*DOn't know how to include &c*/
2848
2849                         odm_tx_pwr_track_set_pwr8812a(p_dm_odm, MIX_MODE, p, 0);
2850                         /**/
2851                 }
2852         } else if (p_dm_odm->support_ic_type == ODM_RTL8723B) {
2853                 odm_tx_pwr_track_set_pwr_8723b(p_dm_odm, MIX_MODE, ODM_RF_PATH_A, 0);
2854                 /**/
2855         } else if (p_dm_odm->support_ic_type == ODM_RTL8192E) {
2856                 for (p = ODM_RF_PATH_A; p < MAX_PATH_NUM_8192E; p++) {   /*DOn't know how to include &c*/
2857                         odm_tx_pwr_track_set_pwr92_e(p_dm_odm, MIX_MODE, p, 0);
2858                         /**/
2859                 }
2860         } else if (p_dm_odm->support_ic_type == ODM_RTL8188E) {
2861                 odm_tx_pwr_track_set_pwr88_e(p_dm_odm, MIX_MODE, ODM_RF_PATH_A, 0);
2862                 /**/
2863         }
2864 }
2865
2866 void
2867 odm_rssi_dump_to_register(
2868         void    *p_dm_void
2869 )
2870 {
2871         struct PHY_DM_STRUCT            *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
2872         struct _ADAPTER         *adapter = p_dm_odm->adapter;
2873
2874         if (p_dm_odm->support_ic_type == ODM_RTL8812) {
2875                 PlatformEFIOWrite1Byte(adapter, REG_A_RSSI_DUMP_JAGUAR, adapter->RxStats.RxRSSIPercentage[0]);
2876                 PlatformEFIOWrite1Byte(adapter, REG_B_RSSI_DUMP_JAGUAR, adapter->RxStats.RxRSSIPercentage[1]);
2877
2878                 /* Rx EVM*/
2879                 PlatformEFIOWrite1Byte(adapter, REG_S1_RXEVM_DUMP_JAGUAR, adapter->RxStats.RxEVMdbm[0]);
2880                 PlatformEFIOWrite1Byte(adapter, REG_S2_RXEVM_DUMP_JAGUAR, adapter->RxStats.RxEVMdbm[1]);
2881
2882                 /* Rx SNR*/
2883                 PlatformEFIOWrite1Byte(adapter, REG_A_RX_SNR_DUMP_JAGUAR, (u8)(adapter->RxStats.RxSNRdB[0]));
2884                 PlatformEFIOWrite1Byte(adapter, REG_B_RX_SNR_DUMP_JAGUAR, (u8)(adapter->RxStats.RxSNRdB[1]));
2885
2886                 /* Rx Cfo_Short*/
2887                 PlatformEFIOWrite2Byte(adapter, REG_A_CFO_SHORT_DUMP_JAGUAR, adapter->RxStats.RxCfoShort[0]);
2888                 PlatformEFIOWrite2Byte(adapter, REG_B_CFO_SHORT_DUMP_JAGUAR, adapter->RxStats.RxCfoShort[1]);
2889
2890                 /* Rx Cfo_Tail*/
2891                 PlatformEFIOWrite2Byte(adapter, REG_A_CFO_LONG_DUMP_JAGUAR, adapter->RxStats.RxCfoTail[0]);
2892                 PlatformEFIOWrite2Byte(adapter, REG_B_CFO_LONG_DUMP_JAGUAR, adapter->RxStats.RxCfoTail[1]);
2893         } else if (p_dm_odm->support_ic_type == ODM_RTL8192E) {
2894                 PlatformEFIOWrite1Byte(adapter, REG_A_RSSI_DUMP_92E, adapter->RxStats.RxRSSIPercentage[0]);
2895                 PlatformEFIOWrite1Byte(adapter, REG_B_RSSI_DUMP_92E, adapter->RxStats.RxRSSIPercentage[1]);
2896                 /* Rx EVM*/
2897                 PlatformEFIOWrite1Byte(adapter, REG_S1_RXEVM_DUMP_92E, adapter->RxStats.RxEVMdbm[0]);
2898                 PlatformEFIOWrite1Byte(adapter, REG_S2_RXEVM_DUMP_92E, adapter->RxStats.RxEVMdbm[1]);
2899                 /* Rx SNR*/
2900                 PlatformEFIOWrite1Byte(adapter, REG_A_RX_SNR_DUMP_92E, (u8)(adapter->RxStats.RxSNRdB[0]));
2901                 PlatformEFIOWrite1Byte(adapter, REG_B_RX_SNR_DUMP_92E, (u8)(adapter->RxStats.RxSNRdB[1]));
2902                 /* Rx Cfo_Short*/
2903                 PlatformEFIOWrite2Byte(adapter, REG_A_CFO_SHORT_DUMP_92E, adapter->RxStats.RxCfoShort[0]);
2904                 PlatformEFIOWrite2Byte(adapter, REG_B_CFO_SHORT_DUMP_92E, adapter->RxStats.RxCfoShort[1]);
2905                 /* Rx Cfo_Tail*/
2906                 PlatformEFIOWrite2Byte(adapter, REG_A_CFO_LONG_DUMP_92E, adapter->RxStats.RxCfoTail[0]);
2907                 PlatformEFIOWrite2Byte(adapter, REG_B_CFO_LONG_DUMP_92E, adapter->RxStats.RxCfoTail[1]);
2908         }
2909 }
2910
2911 void
2912 odm_refresh_ldpc_rts_mp(
2913         struct _ADAPTER                 *p_adapter,
2914         struct PHY_DM_STRUCT                    *p_dm_odm,
2915         u8                              m_mac_id,
2916         u8                              iot_peer,
2917         s32                             undecorated_smoothed_pwdb
2918 )
2919 {
2920         boolean                                 is_ctl_ldpc = false;
2921         struct _ODM_RATE_ADAPTIVE               *p_ra = &p_dm_odm->rate_adaptive;
2922
2923         if (p_dm_odm->support_ic_type != ODM_RTL8821 && p_dm_odm->support_ic_type != ODM_RTL8812)
2924                 return;
2925
2926         if ((p_dm_odm->support_ic_type == ODM_RTL8821) && (p_dm_odm->cut_version == ODM_CUT_A))
2927                 is_ctl_ldpc = true;
2928         else if (p_dm_odm->support_ic_type == ODM_RTL8812 &&
2929                  iot_peer == HT_IOT_PEER_REALTEK_JAGUAR_CCUTAP)
2930                 is_ctl_ldpc = true;
2931
2932         if (is_ctl_ldpc) {
2933                 if (undecorated_smoothed_pwdb < (p_ra->ldpc_thres - 5))
2934                         MgntSet_TX_LDPC(p_adapter, m_mac_id, true);
2935                 else if (undecorated_smoothed_pwdb > p_ra->ldpc_thres)
2936                         MgntSet_TX_LDPC(p_adapter, m_mac_id, false);
2937         }
2938
2939         if (undecorated_smoothed_pwdb < (p_ra->rts_thres - 5))
2940                 p_ra->is_lower_rts_rate = true;
2941         else if (undecorated_smoothed_pwdb > p_ra->rts_thres)
2942                 p_ra->is_lower_rts_rate = false;
2943 }
2944
2945 #if 0
2946 void
2947 odm_dynamic_arfb_select(
2948         void            *p_dm_void,
2949         u8                      rate,
2950         boolean                 collision_state
2951 )
2952 {
2953         struct PHY_DM_STRUCT            *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
2954         struct _rate_adaptive_table_                    *p_ra_table = &p_dm_odm->dm_ra_table;
2955
2956         if (p_dm_odm->support_ic_type != ODM_RTL8192E)
2957                 return;
2958
2959         if (collision_state == p_ra_table->PT_collision_pre)
2960                 return;
2961
2962         if (rate >= DESC_RATEMCS8  && rate <= DESC_RATEMCS12) {
2963                 if (collision_state == 1) {
2964                         if (rate == DESC_RATEMCS12) {
2965
2966                                 odm_write_4byte(p_dm_odm, REG_DARFRC_8192E, 0x0);
2967                                 odm_write_4byte(p_dm_odm, REG_DARFRC_8192E+4, 0x07060501);
2968                         } else if (rate == DESC_RATEMCS11) {
2969
2970                                 odm_write_4byte(p_dm_odm, REG_DARFRC_8192E, 0x0);
2971                                 odm_write_4byte(p_dm_odm, REG_DARFRC_8192E+4, 0x07070605);
2972                         } else if (rate == DESC_RATEMCS10) {
2973
2974                                 odm_write_4byte(p_dm_odm, REG_DARFRC_8192E, 0x0);
2975                                 odm_write_4byte(p_dm_odm, REG_DARFRC_8192E+4, 0x08080706);
2976                         } else if (rate == DESC_RATEMCS9) {
2977
2978                                 odm_write_4byte(p_dm_odm, REG_DARFRC_8192E, 0x0);
2979                                 odm_write_4byte(p_dm_odm, REG_DARFRC_8192E+4, 0x08080707);
2980                         } else {
2981
2982                                 odm_write_4byte(p_dm_odm, REG_DARFRC_8192E, 0x0);
2983                                 odm_write_4byte(p_dm_odm, REG_DARFRC_8192E+4, 0x09090808);
2984                         }
2985                 } else { /* collision_state == 0*/
2986                         if (rate == DESC_RATEMCS12) {
2987
2988                                 odm_write_4byte(p_dm_odm, REG_DARFRC_8192E, 0x05010000);
2989                                 odm_write_4byte(p_dm_odm, REG_DARFRC_8192E+4, 0x09080706);
2990                         } else if (rate == DESC_RATEMCS11) {
2991
2992                                 odm_write_4byte(p_dm_odm, REG_DARFRC_8192E, 0x06050000);
2993                                 odm_write_4byte(p_dm_odm, REG_DARFRC_8192E+4, 0x09080807);
2994                         } else if (rate == DESC_RATEMCS10) {
2995
2996                                 odm_write_4byte(p_dm_odm, REG_DARFRC_8192E, 0x07060000);
2997                                 odm_write_4byte(p_dm_odm, REG_DARFRC_8192E+4, 0x0a090908);
2998                         } else if (rate == DESC_RATEMCS9) {
2999
3000                                 odm_write_4byte(p_dm_odm, REG_DARFRC_8192E, 0x07070000);
3001                                 odm_write_4byte(p_dm_odm, REG_DARFRC_8192E+4, 0x0a090808);
3002                         } else {
3003
3004                                 odm_write_4byte(p_dm_odm, REG_DARFRC_8192E, 0x08080000);
3005                                 odm_write_4byte(p_dm_odm, REG_DARFRC_8192E+4, 0x0b0a0909);
3006                         }
3007                 }
3008         } else { /* MCS13~MCS15,  1SS, G-mode*/
3009                 if (collision_state == 1) {
3010                         if (rate == DESC_RATEMCS15) {
3011
3012                                 odm_write_4byte(p_dm_odm, REG_DARFRC_8192E, 0x00000000);
3013                                 odm_write_4byte(p_dm_odm, REG_DARFRC_8192E+4, 0x05040302);
3014                         } else if (rate == DESC_RATEMCS14) {
3015
3016                                 odm_write_4byte(p_dm_odm, REG_DARFRC_8192E, 0x00000000);
3017                                 odm_write_4byte(p_dm_odm, REG_DARFRC_8192E+4, 0x06050302);
3018                         } else if (rate == DESC_RATEMCS13) {
3019
3020                                 odm_write_4byte(p_dm_odm, REG_DARFRC_8192E, 0x00000000);
3021                                 odm_write_4byte(p_dm_odm, REG_DARFRC_8192E+4, 0x07060502);
3022                         } else {
3023
3024                                 odm_write_4byte(p_dm_odm, REG_DARFRC_8192E, 0x00000000);
3025                                 odm_write_4byte(p_dm_odm, REG_DARFRC_8192E+4, 0x06050402);
3026                         }
3027                 } else { /* collision_state == 0 */
3028                         if (rate == DESC_RATEMCS15) {
3029
3030                                 odm_write_4byte(p_dm_odm, REG_DARFRC_8192E, 0x03020000);
3031                                 odm_write_4byte(p_dm_odm, REG_DARFRC_8192E+4, 0x07060504);
3032                         } else if (rate == DESC_RATEMCS14) {
3033
3034                                 odm_write_4byte(p_dm_odm, REG_DARFRC_8192E, 0x03020000);
3035                                 odm_write_4byte(p_dm_odm, REG_DARFRC_8192E+4, 0x08070605);
3036                         } else if (rate == DESC_RATEMCS13) {
3037
3038                                 odm_write_4byte(p_dm_odm, REG_DARFRC_8192E, 0x05020000);
3039                                 odm_write_4byte(p_dm_odm, REG_DARFRC_8192E+4, 0x09080706);
3040                         } else {
3041
3042                                 odm_write_4byte(p_dm_odm, REG_DARFRC_8192E, 0x04020000);
3043                                 odm_write_4byte(p_dm_odm, REG_DARFRC_8192E+4, 0x08070605);
3044                         }
3045                 }
3046         }
3047         p_ra_table->PT_collision_pre = collision_state;
3048 }
3049 #endif
3050
3051 void
3052 odm_rate_adaptive_state_ap_init(
3053         void            *PADAPTER_VOID,
3054         struct sta_info *p_entry
3055 )
3056 {
3057         struct _ADAPTER         *adapter = (struct _ADAPTER *)PADAPTER_VOID;
3058         p_entry->Ratr_State = DM_RATR_STA_INIT;
3059 }
3060 #elif (DM_ODM_SUPPORT_TYPE == ODM_CE) /*#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)*/
3061
3062 static void
3063 find_minimum_rssi(
3064         struct _ADAPTER *p_adapter
3065 )
3066 {
3067         HAL_DATA_TYPE   *p_hal_data = GET_HAL_DATA(p_adapter);
3068         struct PHY_DM_STRUCT            *p_dm_odm = &(p_hal_data->odmpriv);
3069
3070         /*Determine the minimum RSSI*/
3071
3072         if ((p_dm_odm->is_linked != _TRUE) &&
3073             (p_hal_data->entry_min_undecorated_smoothed_pwdb == 0)) {
3074                 p_hal_data->min_undecorated_pwdb_for_dm = 0;
3075                 /*ODM_RT_TRACE(p_dm_odm,COMP_BB_POWERSAVING, DBG_LOUD, ("Not connected to any\n"));*/
3076         } else
3077                 p_hal_data->min_undecorated_pwdb_for_dm = p_hal_data->entry_min_undecorated_smoothed_pwdb;
3078
3079         /*DBG_8192C("%s=>min_undecorated_pwdb_for_dm(%d)\n",__FUNCTION__,pdmpriv->min_undecorated_pwdb_for_dm);*/
3080         /*ODM_RT_TRACE(p_dm_odm,COMP_DIG, DBG_LOUD, ("min_undecorated_pwdb_for_dm =%d\n",p_hal_data->min_undecorated_pwdb_for_dm));*/
3081 }
3082
3083 u64
3084 phydm_get_rate_bitmap_ex(
3085         void            *p_dm_void,
3086         u32             macid,
3087         u64             ra_mask,
3088         u8              rssi_level,
3089         u64     *dm_ra_mask,
3090         u8      *dm_rte_id
3091 )
3092 {
3093         struct PHY_DM_STRUCT            *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
3094         struct sta_info *p_entry;
3095         u64     rate_bitmap = 0;
3096         u8      wireless_mode;
3097
3098         p_entry = p_dm_odm->p_odm_sta_info[macid];
3099         if (!IS_STA_VALID(p_entry))
3100                 return ra_mask;
3101         wireless_mode = p_entry->wireless_mode;
3102         switch (wireless_mode) {
3103         case ODM_WM_B:
3104                 if (ra_mask & 0x000000000000000c) /* 11M or 5.5M enable */
3105                         rate_bitmap = 0x000000000000000d;
3106                 else
3107                         rate_bitmap = 0x000000000000000f;
3108                 break;
3109
3110         case (ODM_WM_G):
3111         case (ODM_WM_A):
3112                 if (rssi_level == DM_RATR_STA_HIGH)
3113                         rate_bitmap = 0x0000000000000f00;
3114                 else
3115                         rate_bitmap = 0x0000000000000ff0;
3116                 break;
3117
3118         case (ODM_WM_B|ODM_WM_G):
3119                 if (rssi_level == DM_RATR_STA_HIGH)
3120                         rate_bitmap = 0x0000000000000f00;
3121                 else if (rssi_level == DM_RATR_STA_MIDDLE)
3122                         rate_bitmap = 0x0000000000000ff0;
3123                 else
3124                         rate_bitmap = 0x0000000000000ff5;
3125                 break;
3126
3127         case (ODM_WM_B|ODM_WM_G|ODM_WM_N24G):
3128         case (ODM_WM_B|ODM_WM_N24G):
3129         case (ODM_WM_G|ODM_WM_N24G):
3130         case (ODM_WM_A|ODM_WM_N5G):
3131         {
3132                 if (p_dm_odm->rf_type == ODM_1T2R || p_dm_odm->rf_type == ODM_1T1R) {
3133                         if (rssi_level == DM_RATR_STA_HIGH)
3134                                 rate_bitmap = 0x00000000000f0000;
3135                         else if (rssi_level == DM_RATR_STA_MIDDLE)
3136                                 rate_bitmap = 0x00000000000ff000;
3137                         else {
3138                                 if (*(p_dm_odm->p_band_width) == ODM_BW40M)
3139                                         rate_bitmap = 0x00000000000ff015;
3140                                 else
3141                                         rate_bitmap = 0x00000000000ff005;
3142                         }
3143                 } else if (p_dm_odm->rf_type == ODM_2T2R  || p_dm_odm->rf_type == ODM_2T3R  || p_dm_odm->rf_type == ODM_2T4R) {
3144                         if (rssi_level == DM_RATR_STA_HIGH)
3145                                 rate_bitmap = 0x000000000f8f0000;
3146                         else if (rssi_level == DM_RATR_STA_MIDDLE)
3147                                 rate_bitmap = 0x000000000f8ff000;
3148                         else {
3149                                 if (*(p_dm_odm->p_band_width) == ODM_BW40M)
3150                                         rate_bitmap = 0x000000000f8ff015;
3151                                 else
3152                                         rate_bitmap = 0x000000000f8ff005;
3153                         }
3154                 } else {
3155                         if (rssi_level == DM_RATR_STA_HIGH)
3156                                 rate_bitmap = 0x0000000f0f0f0000;
3157                         else if (rssi_level == DM_RATR_STA_MIDDLE)
3158                                 rate_bitmap = 0x0000000fcfcfe000;
3159                         else {
3160                                 if (*(p_dm_odm->p_band_width) == ODM_BW40M)
3161                                         rate_bitmap = 0x0000000ffffff015;
3162                                 else
3163                                         rate_bitmap = 0x0000000ffffff005;
3164                         }
3165                 }
3166         }
3167         break;
3168
3169         case (ODM_WM_AC|ODM_WM_G):
3170                 if (rssi_level == 1)
3171                         rate_bitmap = 0x00000000fc3f0000;
3172                 else if (rssi_level == 2)
3173                         rate_bitmap = 0x00000000fffff000;
3174                 else
3175                         rate_bitmap = 0x00000000ffffffff;
3176                 break;
3177
3178         case (ODM_WM_AC|ODM_WM_A):
3179
3180                 if (p_dm_odm->rf_type == ODM_1T2R || p_dm_odm->rf_type == ODM_1T1R) {
3181                         if (rssi_level == 1)                            /* add by Gary for ac-series */
3182                                 rate_bitmap = 0x00000000003f8000;
3183                         else if (rssi_level == 2)
3184                                 rate_bitmap = 0x00000000003fe000;
3185                         else
3186                                 rate_bitmap = 0x00000000003ff010;
3187                 } else if (p_dm_odm->rf_type == ODM_2T2R  || p_dm_odm->rf_type == ODM_2T3R  || p_dm_odm->rf_type == ODM_2T4R) {
3188                         if (rssi_level == 1)                            /* add by Gary for ac-series */
3189                                 rate_bitmap = 0x00000000fe3f8000;       /* VHT 2SS MCS3~9 */
3190                         else if (rssi_level == 2)
3191                                 rate_bitmap = 0x00000000fffff000;       /* VHT 2SS MCS0~9 */
3192                         else
3193                                 rate_bitmap = 0x00000000fffff010;       /* All */
3194                 } else {
3195                         if (rssi_level == 1)                            /* add by Gary for ac-series */
3196                                 rate_bitmap = 0x000003f8fe3f8000ULL;       /* VHT 3SS MCS3~9 */
3197                         else if (rssi_level == 2)
3198                                 rate_bitmap = 0x000003fffffff000ULL;       /* VHT3SS MCS0~9 */
3199                         else
3200                                 rate_bitmap = 0x000003fffffff010ULL;       /* All */
3201                 }
3202                 break;
3203
3204         default:
3205                 if (p_dm_odm->rf_type == ODM_1T2R || p_dm_odm->rf_type == ODM_1T1R)
3206                         rate_bitmap = 0x00000000000fffff;
3207                 else if (p_dm_odm->rf_type == ODM_2T2R  || p_dm_odm->rf_type == ODM_2T3R  || p_dm_odm->rf_type == ODM_2T4R)
3208                         rate_bitmap = 0x000000000fffffff;
3209                 else
3210                         rate_bitmap = 0x0000003fffffffffULL;
3211                 break;
3212
3213         }
3214         ODM_RT_TRACE(p_dm_odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, (" ==> rssi_level:0x%02x, wireless_mode:0x%02x, rate_bitmap:0x%016llx\n", rssi_level, wireless_mode, rate_bitmap));
3215
3216         return ra_mask & rate_bitmap;
3217 }
3218
3219
3220 u32
3221 odm_get_rate_bitmap(
3222         void            *p_dm_void,
3223         u32             macid,
3224         u32             ra_mask,
3225         u8              rssi_level
3226 )
3227 {
3228         struct PHY_DM_STRUCT            *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
3229         struct sta_info *p_entry;
3230         u32     rate_bitmap = 0;
3231         u8      wireless_mode;
3232         /* u8   wireless_mode =*(p_dm_odm->p_wireless_mode); */
3233
3234
3235         p_entry = p_dm_odm->p_odm_sta_info[macid];
3236         if (!IS_STA_VALID(p_entry))
3237                 return ra_mask;
3238
3239         wireless_mode = p_entry->wireless_mode;
3240
3241         switch (wireless_mode) {
3242         case ODM_WM_B:
3243                 if (ra_mask & 0x0000000c)               /* 11M or 5.5M enable */
3244                         rate_bitmap = 0x0000000d;
3245                 else
3246                         rate_bitmap = 0x0000000f;
3247                 break;
3248
3249         case (ODM_WM_G):
3250         case (ODM_WM_A):
3251                 if (rssi_level == DM_RATR_STA_HIGH)
3252                         rate_bitmap = 0x00000f00;
3253                 else
3254                         rate_bitmap = 0x00000ff0;
3255                 break;
3256
3257         case (ODM_WM_B|ODM_WM_G):
3258                 if (rssi_level == DM_RATR_STA_HIGH)
3259                         rate_bitmap = 0x00000f00;
3260                 else if (rssi_level == DM_RATR_STA_MIDDLE)
3261                         rate_bitmap = 0x00000ff0;
3262                 else
3263                         rate_bitmap = 0x00000ff5;
3264                 break;
3265
3266         case (ODM_WM_B|ODM_WM_G|ODM_WM_N24G):
3267         case (ODM_WM_B|ODM_WM_N24G):
3268         case (ODM_WM_G|ODM_WM_N24G):
3269         case (ODM_WM_A|ODM_WM_N5G):
3270         {
3271                 if (p_dm_odm->rf_type == ODM_1T2R || p_dm_odm->rf_type == ODM_1T1R) {
3272                         if (rssi_level == DM_RATR_STA_HIGH)
3273                                 rate_bitmap = 0x000f0000;
3274                         else if (rssi_level == DM_RATR_STA_MIDDLE)
3275                                 rate_bitmap = 0x000ff000;
3276                         else {
3277                                 if (*(p_dm_odm->p_band_width) == ODM_BW40M)
3278                                         rate_bitmap = 0x000ff015;
3279                                 else
3280                                         rate_bitmap = 0x000ff005;
3281                         }
3282                 } else {
3283                         if (rssi_level == DM_RATR_STA_HIGH)
3284                                 rate_bitmap = 0x0f8f0000;
3285                         else if (rssi_level == DM_RATR_STA_MIDDLE)
3286                                 rate_bitmap = 0x0f8ff000;
3287                         else {
3288                                 if (*(p_dm_odm->p_band_width) == ODM_BW40M)
3289                                         rate_bitmap = 0x0f8ff015;
3290                                 else
3291                                         rate_bitmap = 0x0f8ff005;
3292                         }
3293                 }
3294         }
3295         break;
3296
3297         case (ODM_WM_AC|ODM_WM_G):
3298                 if (rssi_level == 1)
3299                         rate_bitmap = 0xfc3f0000;
3300                 else if (rssi_level == 2)
3301                         rate_bitmap = 0xfffff000;
3302                 else
3303                         rate_bitmap = 0xffffffff;
3304                 break;
3305
3306         case (ODM_WM_AC|ODM_WM_A):
3307
3308                 if (p_dm_odm->rf_type == RF_1T1R) {
3309                         if (rssi_level == 1)                            /* add by Gary for ac-series */
3310                                 rate_bitmap = 0x003f8000;
3311                         else if (rssi_level == 2)
3312                                 rate_bitmap = 0x003ff000;
3313                         else
3314                                 rate_bitmap = 0x003ff010;
3315                 } else {
3316                         if (rssi_level == 1)                            /* add by Gary for ac-series */
3317                                 rate_bitmap = 0xfe3f8000;       /* VHT 2SS MCS3~9 */
3318                         else if (rssi_level == 2)
3319                                 rate_bitmap = 0xfffff000;       /* VHT 2SS MCS0~9 */
3320                         else
3321                                 rate_bitmap = 0xfffff010;       /* All */
3322                 }
3323                 break;
3324
3325         default:
3326                 if (p_dm_odm->rf_type == RF_1T2R)
3327                         rate_bitmap = 0x000fffff;
3328                 else
3329                         rate_bitmap = 0x0fffffff;
3330                 break;
3331
3332         }
3333
3334         ODM_RT_TRACE(p_dm_odm, ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, ("%s ==> rssi_level:0x%02x, wireless_mode:0x%02x, rate_bitmap:0x%08x\n", __func__, rssi_level, wireless_mode, rate_bitmap));
3335         ODM_RT_TRACE(p_dm_odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, (" ==> rssi_level:0x%02x, wireless_mode:0x%02x, rate_bitmap:0x%08x\n", rssi_level, wireless_mode, rate_bitmap));
3336
3337         return ra_mask & rate_bitmap;
3338
3339 }
3340
3341 #endif /* #if (DM_ODM_SUPPORT_TYPE == ODM_CE) */
3342
3343 #elif (DM_ODM_SUPPORT_TYPE & (ODM_AP))
3344
3345
3346 #endif /*#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN| ODM_CE))*/
3347
3348
3349 /* RA_MASK_PHYDMLIZE, will delete it later*/
3350
3351 #if (RA_MASK_PHYDMLIZE_CE || RA_MASK_PHYDMLIZE_AP || RA_MASK_PHYDMLIZE_WIN)
3352
3353 boolean
3354 odm_ra_state_check(
3355         void                    *p_dm_void,
3356         s32                     RSSI,
3357         boolean                 is_force_update,
3358         u8                      *p_ra_tr_state
3359 )
3360 {
3361         struct PHY_DM_STRUCT            *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
3362         struct _ODM_RATE_ADAPTIVE *p_ra = &p_dm_odm->rate_adaptive;
3363         const u8 go_up_gap = 5;
3364         u8 high_rssi_thresh_for_ra = p_ra->high_rssi_thresh;
3365         u8 low_rssi_thresh_for_ra = p_ra->low_rssi_thresh;
3366         u8 ratr_state;
3367
3368         ODM_RT_TRACE(p_dm_odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("RSSI= (( %d )), Current_RSSI_level = (( %d ))\n", RSSI, *p_ra_tr_state));
3369         ODM_RT_TRACE(p_dm_odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("[Ori RA RSSI Thresh]  High= (( %d )), Low = (( %d ))\n", high_rssi_thresh_for_ra, low_rssi_thresh_for_ra));
3370         /* threshold Adjustment:*/
3371         /* when RSSI state trends to go up one or two levels, make sure RSSI is high enough.*/
3372         /* Here go_up_gap is added to solve the boundary's level alternation issue.*/
3373 #if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
3374         u8 ultra_low_rssi_thresh_for_ra = p_ra->ultra_low_rssi_thresh;
3375
3376         if (p_dm_odm->support_ic_type == ODM_RTL8881A)
3377                 low_rssi_thresh_for_ra = 30;            /* for LDPC / BCC switch*/
3378 #endif
3379
3380         switch (*p_ra_tr_state) {
3381         case DM_RATR_STA_INIT:
3382         case DM_RATR_STA_HIGH:
3383                 break;
3384
3385         case DM_RATR_STA_MIDDLE:
3386                 high_rssi_thresh_for_ra += go_up_gap;
3387                 break;
3388
3389         case DM_RATR_STA_LOW:
3390                 high_rssi_thresh_for_ra += go_up_gap;
3391                 low_rssi_thresh_for_ra += go_up_gap;
3392                 break;
3393
3394 #if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
3395         case DM_RATR_STA_ULTRA_LOW:
3396                 high_rssi_thresh_for_ra += go_up_gap;
3397                 low_rssi_thresh_for_ra += go_up_gap;
3398                 ultra_low_rssi_thresh_for_ra += go_up_gap;
3399                 break;
3400 #endif
3401
3402         default:
3403                 ODM_RT_ASSERT(p_dm_odm, false, ("wrong rssi level setting %d !", *p_ra_tr_state));
3404                 break;
3405         }
3406
3407         /* Decide ratr_state by RSSI.*/
3408         if (RSSI > high_rssi_thresh_for_ra)
3409                 ratr_state = DM_RATR_STA_HIGH;
3410         else if (RSSI > low_rssi_thresh_for_ra)
3411                 ratr_state = DM_RATR_STA_MIDDLE;
3412
3413 #if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
3414         else if (RSSI > ultra_low_rssi_thresh_for_ra)
3415                 ratr_state = DM_RATR_STA_LOW;
3416         else
3417                 ratr_state = DM_RATR_STA_ULTRA_LOW;
3418 #else
3419         else
3420                 ratr_state = DM_RATR_STA_LOW;
3421 #endif
3422         ODM_RT_TRACE(p_dm_odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("[Mod RA RSSI Thresh]  High= (( %d )), Low = (( %d ))\n", high_rssi_thresh_for_ra, low_rssi_thresh_for_ra));
3423         /*printk("==>%s,ratr_state:0x%02x,RSSI:%d\n",__FUNCTION__,ratr_state,RSSI);*/
3424
3425         if (*p_ra_tr_state != ratr_state || is_force_update) {
3426                 ODM_RT_TRACE(p_dm_odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("[RSSI Level Update] %d->%d\n", *p_ra_tr_state, ratr_state));
3427                 *p_ra_tr_state = ratr_state;
3428                 return true;
3429         }
3430
3431         return false;
3432 }
3433
3434 #endif