drivers/net/wireless/rockchip_wlan/rtl8723cs/hal/phydm/rtl8703b/halphyrf_8703b.c

   1 /******************************************************************************
   2  *
   3  * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of version 2 of the GNU General Public License as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program; if not, write to the Free Software Foundation, Inc.,
  16  * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  17  *
  18  *
  19  ******************************************************************************/
  20
  21 #include "mp_precomp.h"
  22 #include "../phydm_precomp.h"
  23
  24
  25
  26 /*---------------------------Define Local Constant---------------------------*/
  27 /* IQK */
  28 #define IQK_DELAY_TIME_8703B    10
  29 #define LCK_DELAY_TIME_8703B    100
  30
  31 /* LTE_COEX */
  32 #define REG_LTECOEX_CTRL 0x07C0
  33 #define REG_LTECOEX_WRITE_DATA 0x07C4
  34 #define REG_LTECOEX_READ_DATA 0x07C8
  35 #define REG_LTECOEX_PATH_CONTROL 0x70
  36
  37
  38
  39 /* 2010/04/25 MH Define the max tx power tracking tx agc power. */
  40 #define         ODM_TXPWRTRACK_MAX_IDX8703B             6
  41
  42 #define     idx_0xc94                       0
  43 #define     idx_0xc80                       1
  44 #define     idx_0xc4c                       2
  45
  46 #define     idx_0xc14                       0
  47 #define     idx_0xca0                       1
  48
  49 #define     KEY                             0
  50 #define     VAL                             1
  51
  52 /*---------------------------Define Local Constant---------------------------*/
  53
  54
  55 /* 3============================================================
  56  * 3 Tx Power Tracking
  57  * 3============================================================ */
  58
  59
  60 void set_iqk_matrix_8703b(
  61         struct PHY_DM_STRUCT    *p_dm_odm,
  62         u8              OFDM_index,
  63         u8              rf_path,
  64         s32             iqk_result_x,
  65         s32             iqk_result_y
  66 )
  67 {
  68         s32                     ele_A = 0, ele_D = 0, ele_C = 0, value32, tmp;
  69         s32                     ele_A_ext = 0, ele_C_ext = 0, ele_D_ext = 0;
  70
  71         rf_path = ODM_RF_PATH_A;
  72
  73
  74         if (OFDM_index >= OFDM_TABLE_SIZE)
  75                 OFDM_index = OFDM_TABLE_SIZE - 1;
  76         else if (OFDM_index < 0)
  77                 OFDM_index = 0;
  78
  79         if ((iqk_result_x != 0) && (*(p_dm_odm->p_band_type) == ODM_BAND_2_4G)) {
  80
  81                 /* new element D */
  82                 ele_D = (ofdm_swing_table_new[OFDM_index] & 0xFFC00000) >> 22;
  83                 ele_D_ext = (((iqk_result_x * ele_D) >> 7) & 0x01);
  84
  85                 /* new element A */
  86                 if ((iqk_result_x & 0x00000200) != 0)           /* consider minus */
  87                         iqk_result_x = iqk_result_x | 0xFFFFFC00;
  88                 ele_A = ((iqk_result_x * ele_D) >> 8) & 0x000003FF;
  89                 ele_A_ext = ((iqk_result_x * ele_D) >> 7) & 0x1;
  90                 /* new element C */
  91                 if ((iqk_result_y & 0x00000200) != 0)
  92                         iqk_result_y = iqk_result_y | 0xFFFFFC00;
  93                 ele_C = ((iqk_result_y * ele_D) >> 8) & 0x000003FF;
  94                 ele_C_ext = ((iqk_result_y * ele_D) >> 7) & 0x1;
  95
  96                 switch (rf_path) {
  97                 case ODM_RF_PATH_A:
  98                         /* write new elements A, C, D to regC80, regC94, reg0xc4c, and element B is always 0 */
  99                         /* write 0xc80 */
 100                         value32 = (ele_D << 22) | ((ele_C & 0x3F) << 16) | ele_A;
 101                         odm_set_bb_reg(p_dm_odm, REG_OFDM_0_XA_TX_IQ_IMBALANCE, MASKDWORD, value32);
 102                         /* write 0xc94 */
 103                         value32 = (ele_C & 0x000003C0) >> 6;
 104                         odm_set_bb_reg(p_dm_odm, REG_OFDM_0_XC_TX_AFE, MASKH4BITS, value32);
 105                         /* write 0xc4c */
 106                         value32 = (ele_D_ext << 28) | (ele_A_ext << 31) | (ele_C_ext << 29);
 107                         value32 = (odm_get_bb_reg(p_dm_odm, REG_OFDM_0_ECCA_THRESHOLD, MASKDWORD) & (~(BIT(31) | BIT(29) | BIT(28)))) | value32;
 108                         odm_set_bb_reg(p_dm_odm, REG_OFDM_0_ECCA_THRESHOLD, MASKDWORD, value32);
 109                         break;
 110                 case ODM_RF_PATH_B:
 111                         /* write new elements A, C, D to regC88, regC9C, regC4C, and element B is always 0 */
 112                         /* write 0xc88 */
 113                         value32 = (ele_D << 22) | ((ele_C & 0x3F) << 16) | ele_A;
 114                         odm_set_bb_reg(p_dm_odm, REG_OFDM_0_XB_TX_IQ_IMBALANCE, MASKDWORD, value32);
 115                         /* write 0xc9c */
 116                         value32 = (ele_C & 0x000003C0) >> 6;
 117                         odm_set_bb_reg(p_dm_odm, REG_OFDM_0_XD_TX_AFE, MASKH4BITS, value32);
 118                         /* write 0xc4c */
 119                         value32 = (ele_D_ext << 24) | (ele_A_ext << 27) | (ele_C_ext << 25);
 120                         value32 = (odm_get_bb_reg(p_dm_odm, REG_OFDM_0_ECCA_THRESHOLD, MASKDWORD) & (~(BIT(24) | BIT(27) | BIT(25)))) | value32;
 121                         odm_set_bb_reg(p_dm_odm, REG_OFDM_0_ECCA_THRESHOLD, MASKDWORD, value32);
 122                         break;
 123                 default:
 124                         break;
 125                 }
 126         } else {
 127                 switch (rf_path) {
 128                 case ODM_RF_PATH_A:
 129                         odm_set_bb_reg(p_dm_odm, REG_OFDM_0_XA_TX_IQ_IMBALANCE, MASKDWORD, ofdm_swing_table_new[OFDM_index]);
 130                         odm_set_bb_reg(p_dm_odm, REG_OFDM_0_XC_TX_AFE, MASKH4BITS, 0x00);
 131                         value32 = odm_get_bb_reg(p_dm_odm, REG_OFDM_0_ECCA_THRESHOLD, MASKDWORD) & (~(BIT(31) | BIT(29) | BIT(28)));
 132                         odm_set_bb_reg(p_dm_odm, REG_OFDM_0_ECCA_THRESHOLD, MASKDWORD, value32);
 133                         break;
 134
 135                 case ODM_RF_PATH_B:
 136                         odm_set_bb_reg(p_dm_odm, REG_OFDM_0_XB_TX_IQ_IMBALANCE, MASKDWORD, ofdm_swing_table_new[OFDM_index]);
 137                         odm_set_bb_reg(p_dm_odm, REG_OFDM_0_XD_TX_AFE, MASKH4BITS, 0x00);
 138                         value32 = odm_get_bb_reg(p_dm_odm, REG_OFDM_0_ECCA_THRESHOLD, MASKDWORD) & (~(BIT(24) | BIT(27) | BIT(25)));
 139                         odm_set_bb_reg(p_dm_odm, REG_OFDM_0_ECCA_THRESHOLD, MASKDWORD, value32);
 140                         break;
 141
 142                 default:
 143                         break;
 144                 }
 145         }
 146
 147         ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("TxPwrTracking path %c: X = 0x%x, Y = 0x%x ele_A = 0x%x ele_C = 0x%x ele_D = 0x%x ele_A_ext = 0x%x ele_C_ext = 0x%x ele_D_ext = 0x%x\n",
 148                 (rf_path == ODM_RF_PATH_A ? 'A' : 'B'), (u32)iqk_result_x, (u32)iqk_result_y, (u32)ele_A, (u32)ele_C, (u32)ele_D, (u32)ele_A_ext, (u32)ele_C_ext, (u32)ele_D_ext));
 149 }
 150
 151 void
 152 set_cck_filter_coefficient_8703b(
 153         struct PHY_DM_STRUCT    *p_dm_odm,
 154         u8              cck_swing_index
 155 )
 156 {
 157         odm_write_1byte(p_dm_odm, 0xa22, cck_swing_table_ch1_ch14_88f[cck_swing_index][0]);
 158         odm_write_1byte(p_dm_odm, 0xa23, cck_swing_table_ch1_ch14_88f[cck_swing_index][1]);
 159         odm_write_1byte(p_dm_odm, 0xa24, cck_swing_table_ch1_ch14_88f[cck_swing_index][2]);
 160         odm_write_1byte(p_dm_odm, 0xa25, cck_swing_table_ch1_ch14_88f[cck_swing_index][3]);
 161         odm_write_1byte(p_dm_odm, 0xa26, cck_swing_table_ch1_ch14_88f[cck_swing_index][4]);
 162         odm_write_1byte(p_dm_odm, 0xa27, cck_swing_table_ch1_ch14_88f[cck_swing_index][5]);
 163         odm_write_1byte(p_dm_odm, 0xa28, cck_swing_table_ch1_ch14_88f[cck_swing_index][6]);
 164         odm_write_1byte(p_dm_odm, 0xa29, cck_swing_table_ch1_ch14_88f[cck_swing_index][7]);
 165         odm_write_1byte(p_dm_odm, 0xa9a, cck_swing_table_ch1_ch14_88f[cck_swing_index][8]);
 166         odm_write_1byte(p_dm_odm, 0xa9b, cck_swing_table_ch1_ch14_88f[cck_swing_index][9]);
 167         odm_write_1byte(p_dm_odm, 0xa9c, cck_swing_table_ch1_ch14_88f[cck_swing_index][10]);
 168         odm_write_1byte(p_dm_odm, 0xa9d, cck_swing_table_ch1_ch14_88f[cck_swing_index][11]);
 169         odm_write_1byte(p_dm_odm, 0xaa0, cck_swing_table_ch1_ch14_88f[cck_swing_index][12]);
 170         odm_write_1byte(p_dm_odm, 0xaa1, cck_swing_table_ch1_ch14_88f[cck_swing_index][13]);
 171         odm_write_1byte(p_dm_odm, 0xaa2, cck_swing_table_ch1_ch14_88f[cck_swing_index][14]);
 172         odm_write_1byte(p_dm_odm, 0xaa3, cck_swing_table_ch1_ch14_88f[cck_swing_index][15]);
 173 }
 174
 175 void do_iqk_8703b(
 176         void            *p_dm_void,
 177         u8              delta_thermal_index,
 178         u8              thermal_value,
 179         u8              threshold
 180 )
 181 {
 182         struct PHY_DM_STRUCT    *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
 183
 184 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
 185         struct _ADAPTER         *adapter = p_dm_odm->adapter;
 186 #endif
 187
 188         odm_reset_iqk_result(p_dm_odm);
 189
 190
 191         p_dm_odm->rf_calibrate_info.thermal_value_iqk = thermal_value;
 192 #if (DM_ODM_SUPPORT_TYPE & ODM_AP)
 193         phy_iq_calibrate_8703b(p_dm_odm, false);
 194 #else
 195         phy_iq_calibrate_8703b(adapter, false);
 196 #endif
 197
 198
 199 }
 200
 201 /*-----------------------------------------------------------------------------
 202  * Function:    odm_TxPwrTrackSetPwr88E()
 203  *
 204  * Overview:    88E change all channel tx power accordign to flag.
 205  *                              OFDM & CCK are all different.
 206  *
 207  * Input:               NONE
 208  *
 209  * Output:              NONE
 210  *
 211  * Return:              NONE
 212  *
 213  * Revised History:
 214  *      When            Who             Remark
 215  *      04/23/2012      MHC             Create version 0.
 216  *
 217  *---------------------------------------------------------------------------*/
 218 void
 219 odm_tx_pwr_track_set_pwr_8703b(
 220         void            *p_dm_void,
 221         enum pwrtrack_method    method,
 222         u8                              rf_path,
 223         u8                              channel_mapped_index
 224 )
 225 {
 226         struct PHY_DM_STRUCT            *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
 227         struct _ADAPTER *adapter = p_dm_odm->adapter;
 228         PHAL_DATA_TYPE  p_hal_data = GET_HAL_DATA(adapter);
 229         u8              pwr_tracking_limit_ofdm = 34; /* +0dB */
 230         u8              pwr_tracking_limit_cck = CCK_TABLE_SIZE_88F - 1;   /* -2dB */
 231         u8              tx_rate = 0xFF;
 232         u8              final_ofdm_swing_index = 0;
 233         u8              final_cck_swing_index = 0;
 234         struct odm_rf_calibration_structure     *p_rf_calibrate_info = &(p_dm_odm->rf_calibrate_info);
 235
 236 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN))
 237 #if (MP_DRIVER == 1)    /*win MP */
 238         PMPT_CONTEXT p_mpt_ctx = &(adapter->MptCtx);
 239
 240         tx_rate = MptToMgntRate(p_mpt_ctx->MptRateIndex);
 241 #else   /*win normal*/
 242         PMGNT_INFO              p_mgnt_info = &(adapter->MgntInfo);
 243         if (!p_mgnt_info->ForcedDataRate) {     /*auto rate*/
 244                         tx_rate = adapter->HalFunc.GetHwRateFromMRateHandler(p_dm_odm->tx_rate);
 245         } else
 246                 tx_rate = (u8) p_mgnt_info->ForcedDataRate;
 247 #endif
 248 #elif (DM_ODM_SUPPORT_TYPE & (ODM_CE))
 249         if (p_dm_odm->mp_mode == true) {        /*CE MP*/
 250                 PMPT_CONTEXT            p_mpt_ctx = &(adapter->mppriv.mpt_ctx);
 251
 252                 tx_rate = mpt_to_mgnt_rate(p_mpt_ctx->mpt_rate_index);
 253         } else {        /*CE normal*/
 254                 u16     rate     = *(p_dm_odm->p_forced_data_rate);
 255
 256                 if (!rate) {    /*auto rate*/
 257                         if (p_dm_odm->number_linked_client != 0)
 258                                 tx_rate = hw_rate_to_m_rate(p_dm_odm->tx_rate);
 259                 } else  /*force rate*/
 260                         tx_rate = (u8)rate;
 261         }
 262 #endif
 263
 264
 265         ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("===>ODM_TxPwrTrackSetPwr8703B\n"));
 266
 267         if (tx_rate != 0xFF) {
 268                 /*2 CCK*/
 269                 if (((tx_rate >= MGN_1M) && (tx_rate <= MGN_5_5M)) || (tx_rate == MGN_11M))
 270                         pwr_tracking_limit_cck = CCK_TABLE_SIZE_88F - 1;
 271                 /*2 OFDM*/
 272                 else if ((tx_rate >= MGN_6M) && (tx_rate <= MGN_48M))
 273                         pwr_tracking_limit_ofdm = 36;   /*+3dB*/
 274                 else if (tx_rate == MGN_54M)
 275                         pwr_tracking_limit_ofdm = 34;   /*+2dB*/
 276                 /*2 HT*/
 277                 else if ((tx_rate >= MGN_MCS0) && (tx_rate <= MGN_MCS2))        /*QPSK/BPSK*/
 278                         pwr_tracking_limit_ofdm = 38;   /*+4dB*/
 279                 else if ((tx_rate >= MGN_MCS3) && (tx_rate <= MGN_MCS4))        /*16QAM*/
 280                         pwr_tracking_limit_ofdm = 36;   /*+3dB*/
 281                 else if ((tx_rate >= MGN_MCS5) && (tx_rate <= MGN_MCS7))        /*64QAM*/
 282                         pwr_tracking_limit_ofdm = 34;   /*+2dB*/
 283                 else
 284                         pwr_tracking_limit_ofdm =  p_rf_calibrate_info->default_ofdm_index;   /*Default OFDM index = 30*/
 285         }
 286         ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("tx_rate=0x%x, pwr_tracking_limit=%d\n", tx_rate, pwr_tracking_limit_ofdm));
 287
 288         if (method == TXAGC) {
 289                 u32     pwr = 0, tx_agc = 0;
 290                 struct _ADAPTER *adapter = p_dm_odm->adapter;
 291
 292                 ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("odm_TxPwrTrackSetPwr8703B CH=%d\n", *(p_dm_odm->p_channel)));
 293
 294                 p_rf_calibrate_info->remnant_ofdm_swing_idx[rf_path] = p_rf_calibrate_info->absolute_ofdm_swing_idx[rf_path];
 295
 296 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
 297 #if (MP_DRIVER != 1)
 298                 p_rf_calibrate_info->modify_tx_agc_flag_path_a = true;
 299                 p_rf_calibrate_info->modify_tx_agc_flag_path_a_cck = true;
 300
 301                 odm_set_tx_power_index_by_rate_section(p_dm_odm, rf_path, *p_dm_odm->p_channel, CCK);
 302                 odm_set_tx_power_index_by_rate_section(p_dm_odm, rf_path, *p_dm_odm->p_channel, OFDM);
 303                 odm_set_tx_power_index_by_rate_section(p_dm_odm, rf_path, *p_dm_odm->p_channel, HT_MCS0_MCS7);
 304 #else
 305                 pwr = odm_get_bb_reg(p_dm_odm, REG_TX_AGC_A_RATE18_06, 0xFF);
 306                 pwr += p_rf_calibrate_info->power_index_offset[rf_path];
 307                 odm_set_bb_reg(p_dm_odm, REG_TX_AGC_A_CCK_1_MCS32, MASKBYTE1, pwr);
 308                 tx_agc = (pwr << 16) | (pwr << 8) | (pwr);
 309                 odm_set_bb_reg(p_dm_odm, REG_TX_AGC_B_CCK_11_A_CCK_2_11, 0xffffff00, tx_agc);
 310                 RT_DISP(FPHY, PHY_TXPWR, ("ODM_TxPwrTrackSetPwr8703B: CCK Tx-rf(A) Power = 0x%x\n", tx_agc));
 311
 312                 pwr = odm_get_bb_reg(p_dm_odm, REG_TX_AGC_A_RATE18_06, 0xFF);
 313                 pwr += (p_rf_calibrate_info->bb_swing_idx_ofdm[rf_path] - p_rf_calibrate_info->bb_swing_idx_ofdm_base[rf_path]);
 314                 tx_agc |= ((pwr << 24) | (pwr << 16) | (pwr << 8) | pwr);
 315                 odm_set_bb_reg(p_dm_odm, REG_TX_AGC_A_RATE18_06, MASKDWORD, tx_agc);
 316                 odm_set_bb_reg(p_dm_odm, REG_TX_AGC_A_RATE54_24, MASKDWORD, tx_agc);
 317                 odm_set_bb_reg(p_dm_odm, REG_TX_AGC_A_MCS03_MCS00, MASKDWORD, tx_agc);
 318                 odm_set_bb_reg(p_dm_odm, REG_TX_AGC_A_MCS07_MCS04, MASKDWORD, tx_agc);
 319                 odm_set_bb_reg(p_dm_odm, REG_TX_AGC_A_MCS11_MCS08, MASKDWORD, tx_agc);
 320                 odm_set_bb_reg(p_dm_odm, REG_TX_AGC_A_MCS15_MCS12, MASKDWORD, tx_agc);
 321                 RT_DISP(FPHY, PHY_TXPWR, ("ODM_TxPwrTrackSetPwr8703B: OFDM Tx-rf(A) Power = 0x%x\n", tx_agc));
 322 #endif
 323 #endif
 324         } else if (method == BBSWING) {
 325                 final_ofdm_swing_index = p_rf_calibrate_info->default_ofdm_index + p_rf_calibrate_info->absolute_ofdm_swing_idx[rf_path];
 326                 final_cck_swing_index = p_rf_calibrate_info->default_cck_index + p_rf_calibrate_info->absolute_ofdm_swing_idx[rf_path];
 327
 328                 ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
 329                         (" p_rf_calibrate_info->default_ofdm_index=%d,  p_rf_calibrate_info->DefaultCCKIndex=%d, p_rf_calibrate_info->absolute_ofdm_swing_idx[rf_path]=%d, p_rf_calibrate_info->remnant_cck_swing_idx=%d   rf_path = %d\n",
 330                         p_rf_calibrate_info->default_ofdm_index, p_rf_calibrate_info->default_cck_index, p_rf_calibrate_info->absolute_ofdm_swing_idx[rf_path], p_rf_calibrate_info->remnant_cck_swing_idx, rf_path));
 331
 332                 /* Adjust BB swing by OFDM IQ matrix */
 333                 if (final_ofdm_swing_index >= pwr_tracking_limit_ofdm)
 334                         final_ofdm_swing_index = pwr_tracking_limit_ofdm;
 335                 else if (final_ofdm_swing_index < 0)
 336                         final_ofdm_swing_index = 0;
 337
 338                 if (final_cck_swing_index >= CCK_TABLE_SIZE)
 339                         final_cck_swing_index = CCK_TABLE_SIZE - 1;
 340                 else if (p_rf_calibrate_info->bb_swing_idx_cck < 0)
 341                         final_cck_swing_index = 0;
 342
 343                 set_iqk_matrix_8703b(p_dm_odm, final_ofdm_swing_index, ODM_RF_PATH_A,
 344                         p_rf_calibrate_info->iqk_matrix_reg_setting[channel_mapped_index].value[0][0],
 345                         p_rf_calibrate_info->iqk_matrix_reg_setting[channel_mapped_index].value[0][1]);
 346
 347                 set_cck_filter_coefficient_8703b(p_dm_odm, final_cck_swing_index);
 348
 349         } else if (method == MIX_MODE) {
 350                 ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
 351                         (" p_dm_odm->default_ofdm_index=%d,  p_dm_odm->DefaultCCKIndex=%d, p_dm_odm->absolute_ofdm_swing_idx[rf_path]=%d, p_dm_odm->remnant_cck_swing_idx=%d   rf_path = %d\n",
 352                         p_rf_calibrate_info->default_ofdm_index, p_rf_calibrate_info->default_cck_index, p_rf_calibrate_info->absolute_ofdm_swing_idx[rf_path], p_rf_calibrate_info->remnant_cck_swing_idx, rf_path));
 353
 354                 final_ofdm_swing_index = p_rf_calibrate_info->default_ofdm_index + p_rf_calibrate_info->absolute_ofdm_swing_idx[rf_path];
 355                 final_cck_swing_index  = p_rf_calibrate_info->default_cck_index + p_rf_calibrate_info->absolute_ofdm_swing_idx[rf_path];
 356
 357                 ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
 358                         (" p_dm_odm->default_ofdm_index=%d,  p_dm_odm->DefaultCCKIndex=%d, p_dm_odm->absolute_ofdm_swing_idx[rf_path]=%d   rf_path = %d\n",
 359                         p_rf_calibrate_info->default_ofdm_index, p_rf_calibrate_info->default_cck_index, p_rf_calibrate_info->absolute_ofdm_swing_idx[rf_path], rf_path));
 360
 361                 ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
 362                         (" final_ofdm_swing_index=%d,  final_cck_swing_index=%d rf_path=%d\n",
 363                         final_ofdm_swing_index, final_cck_swing_index, rf_path));
 364
 365
 366                 if (final_ofdm_swing_index > pwr_tracking_limit_ofdm) {   /*BBSwing higher then Limit*/
 367                         p_rf_calibrate_info->remnant_ofdm_swing_idx[rf_path] = final_ofdm_swing_index - pwr_tracking_limit_ofdm;
 368
 369                         set_iqk_matrix_8703b(p_dm_odm, pwr_tracking_limit_ofdm, ODM_RF_PATH_A,
 370                                 p_rf_calibrate_info->iqk_matrix_reg_setting[channel_mapped_index].value[0][0],
 371                                 p_rf_calibrate_info->iqk_matrix_reg_setting[channel_mapped_index].value[0][1]);
 372
 373                         p_rf_calibrate_info->modify_tx_agc_flag_path_a = true;
 374                         odm_set_tx_power_index_by_rate_section(p_dm_odm, rf_path, *p_dm_odm->p_channel, OFDM);
 375                         odm_set_tx_power_index_by_rate_section(p_dm_odm, rf_path, *p_dm_odm->p_channel, HT_MCS0_MCS7);
 376
 377                         ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
 378                                 (" ******Path_A Over BBSwing Limit, pwr_tracking_limit = %d, Remnant tx_agc value = %d\n",
 379                                 pwr_tracking_limit_ofdm, p_rf_calibrate_info->remnant_ofdm_swing_idx[rf_path]));
 380                 } else if (final_ofdm_swing_index < 0) {
 381                         p_rf_calibrate_info->remnant_ofdm_swing_idx[rf_path] = final_ofdm_swing_index;
 382
 383                         set_iqk_matrix_8703b(p_dm_odm, 0, ODM_RF_PATH_A,
 384                                 p_rf_calibrate_info->iqk_matrix_reg_setting[channel_mapped_index].value[0][0],
 385                                 p_rf_calibrate_info->iqk_matrix_reg_setting[channel_mapped_index].value[0][1]);
 386
 387                         p_rf_calibrate_info->modify_tx_agc_flag_path_a = true;
 388                         odm_set_tx_power_index_by_rate_section(p_dm_odm, rf_path, *p_dm_odm->p_channel, OFDM);
 389                         odm_set_tx_power_index_by_rate_section(p_dm_odm, rf_path, *p_dm_odm->p_channel, HT_MCS0_MCS7);
 390
 391                         ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
 392                                 (" ******Path_A Lower then BBSwing lower bound  0, Remnant tx_agc value = %d\n",
 393                                 p_rf_calibrate_info->remnant_ofdm_swing_idx[rf_path]));
 394                 } else {
 395                         set_iqk_matrix_8703b(p_dm_odm, final_ofdm_swing_index, ODM_RF_PATH_A,
 396                                 p_rf_calibrate_info->iqk_matrix_reg_setting[channel_mapped_index].value[0][0],
 397                                 p_rf_calibrate_info->iqk_matrix_reg_setting[channel_mapped_index].value[0][1]);
 398
 399                         ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
 400                                 (" ******Path_A Compensate with BBSwing, final_ofdm_swing_index = %d\n", final_ofdm_swing_index));
 401
 402                         if (p_rf_calibrate_info->modify_tx_agc_flag_path_a) {           /*If tx_agc has changed, reset tx_agc again*/
 403                                 p_rf_calibrate_info->remnant_ofdm_swing_idx[rf_path] = 0;
 404                                 odm_set_tx_power_index_by_rate_section(p_dm_odm, rf_path, *p_dm_odm->p_channel, OFDM);
 405                                 odm_set_tx_power_index_by_rate_section(p_dm_odm, rf_path, *p_dm_odm->p_channel, HT_MCS0_MCS7);
 406                                 p_rf_calibrate_info->modify_tx_agc_flag_path_a = false;
 407
 408                                 ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
 409                                         (" ******Path_A p_dm_odm->Modify_TxAGC_Flag = false\n"));
 410                         }
 411                 }
 412                 if (final_cck_swing_index > pwr_tracking_limit_cck) {
 413                         ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
 414                                 (" final_cck_swing_index(%d) > pwr_tracking_limit_cck(%d)\n", final_cck_swing_index, pwr_tracking_limit_cck));
 415
 416                         p_rf_calibrate_info->remnant_cck_swing_idx = final_cck_swing_index - pwr_tracking_limit_cck;
 417
 418                         set_cck_filter_coefficient_8703b(p_dm_odm, pwr_tracking_limit_cck);
 419
 420                         ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("******Path_A CCK Over Limit, pwr_tracking_limit_cck = %d, p_dm_odm->remnant_cck_swing_idx  = %d\n", pwr_tracking_limit_cck, p_rf_calibrate_info->remnant_cck_swing_idx));
 421
 422                         p_rf_calibrate_info->modify_tx_agc_flag_path_a_cck = true;
 423
 424                         odm_set_tx_power_index_by_rate_section(p_dm_odm, ODM_RF_PATH_A, *p_dm_odm->p_channel, CCK);
 425
 426                 } else if (final_cck_swing_index < 0) {         /* Lowest CCK index = 0 */
 427
 428                         ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
 429                                 (" final_cck_swing_index(%d) < 0      pwr_tracking_limit_cck(%d)\n", final_cck_swing_index, pwr_tracking_limit_cck));
 430
 431                         p_rf_calibrate_info->remnant_cck_swing_idx = final_cck_swing_index;
 432
 433                         set_cck_filter_coefficient_8703b(p_dm_odm, 0);
 434
 435                         ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("******Path_A CCK Under Limit, pwr_tracking_limit_cck = %d, p_dm_odm->remnant_cck_swing_idx  = %d\n", 0, p_rf_calibrate_info->remnant_cck_swing_idx));
 436
 437                         p_rf_calibrate_info->modify_tx_agc_flag_path_a_cck = true;
 438
 439                         odm_set_tx_power_index_by_rate_section(p_dm_odm, ODM_RF_PATH_A, *p_dm_odm->p_channel, CCK);
 440
 441                 } else {
 442
 443                         ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
 444                                 (" else final_cck_swing_index=%d      pwr_tracking_limit_cck(%d)\n", final_cck_swing_index, pwr_tracking_limit_cck));
 445
 446                         set_cck_filter_coefficient_8703b(p_dm_odm, final_cck_swing_index);
 447
 448                         ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("******Path_A CCK Compensate with BBSwing, final_cck_swing_index = %d\n", final_cck_swing_index));
 449
 450                         p_rf_calibrate_info->modify_tx_agc_flag_path_a_cck = false;
 451
 452                         p_rf_calibrate_info->remnant_cck_swing_idx = 0;
 453
 454                         if (p_rf_calibrate_info->modify_tx_agc_flag_path_a_cck) {               /*If tx_agc has changed, reset tx_agc again*/
 455                                 p_rf_calibrate_info->remnant_cck_swing_idx = 0;
 456                                 odm_set_tx_power_index_by_rate_section(p_dm_odm, ODM_RF_PATH_A, *p_dm_odm->p_channel, CCK);
 457                                 p_rf_calibrate_info->modify_tx_agc_flag_path_a_cck = false;
 458                         }
 459
 460
 461
 462                 }
 463
 464         } else {
 465                 return; /* This method is not supported. */
 466         }
 467 }
 468
 469 void
 470 get_delta_swing_table_8703b(
 471         void            *p_dm_void,
 472         u8 **temperature_up_a,
 473         u8 **temperature_down_a,
 474         u8 **temperature_up_b,
 475         u8 **temperature_down_b
 476 )
 477 {
 478         struct PHY_DM_STRUCT    *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
 479         struct _ADAPTER         *adapter                 = p_dm_odm->adapter;
 480         struct odm_rf_calibration_structure     *p_rf_calibrate_info = &(p_dm_odm->rf_calibrate_info);
 481         HAL_DATA_TYPE   *p_hal_data              = GET_HAL_DATA(adapter);
 482         u8                      tx_rate                 = 0xFF;
 483         u8                      channel          = *p_dm_odm->p_channel;
 484
 485
 486         if (p_dm_odm->mp_mode == true) {
 487 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
 488 #if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
 489 #if (MP_DRIVER == 1)
 490                 PMPT_CONTEXT p_mpt_ctx = &(adapter->MptCtx);
 491
 492                 tx_rate = MptToMgntRate(p_mpt_ctx->MptRateIndex);
 493 #endif
 494 #elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
 495                 PMPT_CONTEXT p_mpt_ctx = &(adapter->mppriv.mpt_ctx);
 496
 497                 tx_rate = mpt_to_mgnt_rate(p_mpt_ctx->mpt_rate_index);
 498 #endif
 499 #endif
 500         } else {
 501                 u16     rate     = *(p_dm_odm->p_forced_data_rate);
 502
 503                 if (!rate) { /*auto rate*/
 504 #if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
 505                         tx_rate = adapter->HalFunc.GetHwRateFromMRateHandler(p_dm_odm->tx_rate);
 506 #elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
 507                         if (p_dm_odm->number_linked_client != 0)
 508                                 tx_rate = hw_rate_to_m_rate(p_dm_odm->tx_rate);
 509 #endif
 510                 } else   /*force rate*/
 511                         tx_rate = (u8)rate;
 512         }
 513
 514         ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("Power Tracking tx_rate=0x%X\n", tx_rate));
 515
 516         if (1 <= channel && channel <= 14) {
 517                 if (IS_CCK_RATE(tx_rate)) {
 518                         *temperature_up_a   = p_rf_calibrate_info->delta_swing_table_idx_2g_cck_a_p;
 519                         *temperature_down_a = p_rf_calibrate_info->delta_swing_table_idx_2g_cck_a_n;
 520                         *temperature_up_b   = p_rf_calibrate_info->delta_swing_table_idx_2g_cck_b_p;
 521                         *temperature_down_b = p_rf_calibrate_info->delta_swing_table_idx_2g_cck_b_n;
 522                 } else {
 523                         *temperature_up_a   = p_rf_calibrate_info->delta_swing_table_idx_2ga_p;
 524                         *temperature_down_a = p_rf_calibrate_info->delta_swing_table_idx_2ga_n;
 525                         *temperature_up_b   = p_rf_calibrate_info->delta_swing_table_idx_2gb_p;
 526                         *temperature_down_b = p_rf_calibrate_info->delta_swing_table_idx_2gb_n;
 527                 }
 528         } else {
 529                 *temperature_up_a   = (u8 *)delta_swing_table_idx_2ga_p_8188e;
 530                 *temperature_down_a = (u8 *)delta_swing_table_idx_2ga_n_8188e;
 531                 *temperature_up_b   = (u8 *)delta_swing_table_idx_2ga_p_8188e;
 532                 *temperature_down_b = (u8 *)delta_swing_table_idx_2ga_n_8188e;
 533         }
 534
 535         return;
 536 }
 537
 538
 539
 540 void
 541 get_delta_swing_xtal_table_8703b(
 542         void            *p_dm_void,
 543         s8 **temperature_up_xtal,
 544         s8 **temperature_down_xtal
 545 )
 546 {
 547         struct PHY_DM_STRUCT    *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
 548         struct odm_rf_calibration_structure     *p_rf_calibrate_info = &(p_dm_odm->rf_calibrate_info);
 549
 550         *temperature_up_xtal   = p_rf_calibrate_info->delta_swing_table_xtal_p;
 551         *temperature_down_xtal = p_rf_calibrate_info->delta_swing_table_xtal_n;
 552 }
 553
 554
 555
 556 void
 557 odm_txxtaltrack_set_xtal_8703b(
 558         void            *p_dm_void
 559 )
 560 {
 561         struct PHY_DM_STRUCT            *p_dm_odm               = (struct PHY_DM_STRUCT *)p_dm_void;
 562         struct odm_rf_calibration_structure     *p_rf_calibrate_info    = &(p_dm_odm->rf_calibrate_info);
 563         struct _ADAPTER         *adapter                        = p_dm_odm->adapter;
 564         HAL_DATA_TYPE   *p_hal_data              = GET_HAL_DATA(adapter);
 565
 566         s8      crystal_cap;
 567
 568
 569         crystal_cap = p_hal_data->crystal_cap & 0x3F;
 570         crystal_cap = crystal_cap + p_rf_calibrate_info->xtal_offset;
 571
 572         if (crystal_cap < 0)
 573                 crystal_cap = 0;
 574         else if (crystal_cap > 63)
 575                 crystal_cap = 63;
 576
 577
 578         ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
 579                 ("crystal_cap(%d)= p_hal_data->crystal_cap(%d) + p_rf_calibrate_info->xtal_offset(%d)\n", crystal_cap, p_hal_data->crystal_cap, p_rf_calibrate_info->xtal_offset));
 580
 581         odm_set_bb_reg(p_dm_odm, REG_MAC_PHY_CTRL, 0xFFF000, (crystal_cap | (crystal_cap << 6)));
 582
 583         ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
 584                 ("crystal_cap(0x2c)  0x%X\n", odm_get_bb_reg(p_dm_odm, REG_MAC_PHY_CTRL, 0xFFF000)));
 585
 586
 587 }
 588
 589
 590
 591 void configure_txpower_track_8703b(
 592         struct _TXPWRTRACK_CFG  *p_config
 593 )
 594 {
 595         p_config->swing_table_size_cck = CCK_TABLE_SIZE;
 596         p_config->swing_table_size_ofdm = OFDM_TABLE_SIZE;
 597         p_config->threshold_iqk = IQK_THRESHOLD;
 598         p_config->average_thermal_num = AVG_THERMAL_NUM_8703B;
 599         p_config->rf_path_count = MAX_PATH_NUM_8703B;
 600         p_config->thermal_reg_addr = RF_T_METER_8703B;
 601
 602         p_config->odm_tx_pwr_track_set_pwr = odm_tx_pwr_track_set_pwr_8703b;
 603         p_config->do_iqk = do_iqk_8703b;
 604         p_config->phy_lc_calibrate = phy_lc_calibrate_8703b;
 605         p_config->get_delta_swing_table = get_delta_swing_table_8703b;
 606         p_config->get_delta_swing_xtal_table = get_delta_swing_xtal_table_8703b;
 607         p_config->odm_txxtaltrack_set_xtal = odm_txxtaltrack_set_xtal_8703b;
 608 }
 609
 610
 611
 612 /* 1 7. IQK */
 613 #define MAX_TOLERANCE           5
 614 #define IQK_DELAY_TIME          1               /* ms */
 615
 616 u8                      /* bit0 = 1 => Tx OK, bit1 = 1 => Rx OK */
 617 phy_path_a_iqk_8703b(
 618 #if (DM_ODM_SUPPORT_TYPE & ODM_AP)
 619         struct PHY_DM_STRUCT            *p_dm_odm
 620 #else
 621         struct _ADAPTER *p_adapter
 622 #endif
 623 )
 624 {
 625         u32 reg_eac, reg_e94, reg_e9c, tmp/*, reg_ea4*/;
 626         u8 result = 0x00, ktime;
 627         u32 original_path, original_gnt;
 628
 629 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
 630         HAL_DATA_TYPE   *p_hal_data = GET_HAL_DATA(p_adapter);
 631 #if (DM_ODM_SUPPORT_TYPE == ODM_CE)
 632         struct PHY_DM_STRUCT            *p_dm_odm = &p_hal_data->odmpriv;
 633 #endif
 634 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
 635         struct PHY_DM_STRUCT            *p_dm_odm = &p_hal_data->DM_OutSrc;
 636 #endif
 637 #endif
 638         ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]TX IQK!\n"));
 639
 640         /*8703b IQK v2.0 20150713*/
 641         /*1 Tx IQK*/
 642         /*IQK setting*/
 643         odm_set_bb_reg(p_dm_odm, REG_TX_IQK, MASKDWORD, 0x01007c00);
 644         odm_set_bb_reg(p_dm_odm, REG_RX_IQK, MASKDWORD, 0x01004800);
 645         /*path-A IQK setting*/
 646         odm_set_bb_reg(p_dm_odm, REG_TX_IQK_TONE_A, MASKDWORD, 0x18008c1c);
 647         odm_set_bb_reg(p_dm_odm, REG_RX_IQK_TONE_A, MASKDWORD, 0x38008c1c);
 648         odm_set_bb_reg(p_dm_odm, REG_TX_IQK_TONE_B, MASKDWORD, 0x38008c1c);
 649         odm_set_bb_reg(p_dm_odm, REG_RX_IQK_TONE_B, MASKDWORD, 0x38008c1c);
 650         /*      odm_set_bb_reg(p_dm_odm, REG_TX_IQK_PI_A, MASKDWORD, 0x8214010a);*/
 651         odm_set_bb_reg(p_dm_odm, REG_TX_IQK_PI_A, MASKDWORD, 0x8214030f);
 652         odm_set_bb_reg(p_dm_odm, REG_RX_IQK_PI_A, MASKDWORD, 0x28110000);
 653         odm_set_bb_reg(p_dm_odm, REG_TX_IQK_PI_B, MASKDWORD, 0x82110000);
 654         odm_set_bb_reg(p_dm_odm, REG_RX_IQK_PI_B, MASKDWORD, 0x28110000);
 655
 656         /*LO calibration setting*/
 657         odm_set_bb_reg(p_dm_odm, REG_IQK_AGC_RSP, MASKDWORD, 0x00462911);
 658
 659         /*leave IQK mode*/
 660         odm_set_bb_reg(p_dm_odm, REG_FPGA0_IQK, 0xffffff00, 0x000000);
 661
 662         /*PA, PAD setting*/
 663         odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0xdf, 0x800, 0x1);
 664         odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0x55, 0x0007f, 0x7);
 665         odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0x7f, RFREGOFFSETMASK, 0x0d400);
 666
 667         /*enter IQK mode*/
 668         odm_set_bb_reg(p_dm_odm, REG_FPGA0_IQK, 0xffffff00, 0x808000);
 669
 670 #if 1
 671         /*path setting*/
 672         /*Save Original path Owner, Original GNT*/
 673         original_path = odm_get_mac_reg(p_dm_odm, REG_LTECOEX_PATH_CONTROL, MASKDWORD);  /*save 0x70*/
 674         odm_set_bb_reg(p_dm_odm, REG_LTECOEX_CTRL, MASKDWORD, 0x800f0038);
 675         ODM_delay_ms(1);
 676         original_gnt = odm_get_bb_reg(p_dm_odm, REG_LTECOEX_READ_DATA, MASKDWORD);  /*save 0x38*/
 677
 678         /*set GNT_WL=1/GNT_BT=0  and path owner to WiFi for pause BT traffic*/
 679         odm_set_bb_reg(p_dm_odm, REG_LTECOEX_WRITE_DATA, MASKDWORD, 0x00007700);
 680         odm_set_bb_reg(p_dm_odm, REG_LTECOEX_CTRL, MASKDWORD, 0xc0020038);      /*0x38[15:8] = 0x77*/
 681         odm_set_mac_reg(p_dm_odm, REG_LTECOEX_PATH_CONTROL, BIT(26), 0x1);  /*0x70[26] =1 --> path Owner to WiFi*/
 682 #endif
 683
 684         /*One shot, path A LOK & IQK*/
 685         odm_set_bb_reg(p_dm_odm, REG_IQK_AGC_PTS, MASKDWORD, 0xf9000000);
 686         odm_set_bb_reg(p_dm_odm, REG_IQK_AGC_PTS, MASKDWORD, 0xf8000000);
 687
 688         /* delay x ms */
 689         ODM_delay_ms(IQK_DELAY_TIME_8703B);
 690         ktime = 0;
 691         while ((odm_get_bb_reg(p_dm_odm, 0xe90, MASKDWORD) == 0) && ktime < 10) {
 692                 ODM_delay_ms(5);
 693                 ktime++;
 694         }
 695
 696 #if 1
 697         /*path setting*/
 698         /*Restore GNT_WL/GNT_BT  and path owner*/
 699         odm_set_bb_reg(p_dm_odm, REG_LTECOEX_WRITE_DATA, MASKDWORD, original_gnt);
 700         odm_set_bb_reg(p_dm_odm, REG_LTECOEX_CTRL, MASKDWORD, 0xc00f0038);
 701         odm_set_mac_reg(p_dm_odm, REG_LTECOEX_PATH_CONTROL, 0xffffffff, original_path);
 702
 703         original_path = odm_get_mac_reg(p_dm_odm, REG_LTECOEX_PATH_CONTROL, MASKDWORD);  /*save 0x70*/
 704         odm_set_bb_reg(p_dm_odm, REG_LTECOEX_CTRL, MASKDWORD, 0x800f0038);
 705         ODM_delay_ms(1);
 706         original_gnt = odm_get_bb_reg(p_dm_odm, REG_LTECOEX_READ_DATA, MASKDWORD);  /*save 0x38*/
 707
 708 #endif
 709
 710         /*leave IQK mode*/
 711         odm_set_bb_reg(p_dm_odm, REG_FPGA0_IQK, 0xffffff00, 0x000000);
 712         /*      PA/PAD controlled by 0x0*/
 713         odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0xdf, 0x800, 0x0);
 714
 715         /* Check failed*/
 716         reg_eac = odm_get_bb_reg(p_dm_odm, REG_RX_POWER_AFTER_IQK_A_2, MASKDWORD);
 717         reg_e94 = odm_get_bb_reg(p_dm_odm, REG_TX_POWER_BEFORE_IQK_A, MASKDWORD);
 718         reg_e9c = odm_get_bb_reg(p_dm_odm, REG_TX_POWER_AFTER_IQK_A, MASKDWORD);
 719         ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]0xeac = 0x%x\n", reg_eac));
 720         ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]0xe94 = 0x%x, 0xe9c = 0x%x\n", reg_e94, reg_e9c));
 721         /*monitor image power before & after IQK*/
 722         ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]0xe90(before IQK)= 0x%x, 0xe98(afer IQK) = 0x%x\n",
 723                 odm_get_bb_reg(p_dm_odm, 0xe90, MASKDWORD), odm_get_bb_reg(p_dm_odm, 0xe98, MASKDWORD)));
 724
 725         if (!(reg_eac & BIT(28)) &&
 726             (((reg_e94 & 0x03FF0000) >> 16) != 0x142) &&
 727             (((reg_e9c & 0x03FF0000) >> 16) != 0x42))
 728
 729                 result |= 0x01;
 730
 731         return result;
 732
 733 }
 734
 735 u8                      /* bit0 = 1 => Tx OK, bit1 = 1 => Rx OK */
 736 phy_path_a_rx_iqk_8703b(
 737 #if (DM_ODM_SUPPORT_TYPE & ODM_AP)
 738         struct PHY_DM_STRUCT            *p_dm_odm
 739 #else
 740         struct _ADAPTER *p_adapter
 741 #endif
 742 )
 743 {
 744         u32 reg_eac, reg_e94, reg_e9c, reg_ea4, u4tmp, tmp;
 745         u8 result = 0x00, ktime;
 746         u32 original_path, original_gnt;
 747
 748 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
 749         HAL_DATA_TYPE   *p_hal_data = GET_HAL_DATA(p_adapter);
 750 #if (DM_ODM_SUPPORT_TYPE == ODM_CE)
 751         struct PHY_DM_STRUCT            *p_dm_odm = &p_hal_data->odmpriv;
 752 #endif
 753 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
 754         struct PHY_DM_STRUCT            *p_dm_odm = &p_hal_data->DM_OutSrc;
 755 #endif
 756 #endif
 757
 758
 759         ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]RX IQK:Get TXIMR setting\n"));
 760         /* 1 Get TX_XY */
 761
 762         /* IQK setting */
 763         odm_set_bb_reg(p_dm_odm, REG_TX_IQK, MASKDWORD, 0x01007c00);
 764         odm_set_bb_reg(p_dm_odm, REG_RX_IQK, MASKDWORD, 0x01004800);
 765
 766         /* path-A IQK setting */
 767         odm_set_bb_reg(p_dm_odm, REG_TX_IQK_TONE_A, MASKDWORD, 0x18008c1c);
 768         odm_set_bb_reg(p_dm_odm, REG_RX_IQK_TONE_A, MASKDWORD, 0x38008c1c);
 769         odm_set_bb_reg(p_dm_odm, REG_TX_IQK_TONE_B, MASKDWORD, 0x38008c1c);
 770         odm_set_bb_reg(p_dm_odm, REG_RX_IQK_TONE_B, MASKDWORD, 0x38008c1c);
 771
 772         /*      odm_set_bb_reg(p_dm_odm, REG_TX_IQK_PI_A, MASKDWORD, 0x82160c1f); */
 773         odm_set_bb_reg(p_dm_odm, REG_TX_IQK_PI_A, MASKDWORD, 0x8216000f);
 774         odm_set_bb_reg(p_dm_odm, REG_RX_IQK_PI_A, MASKDWORD, 0x28110000);
 775         odm_set_bb_reg(p_dm_odm, REG_TX_IQK_PI_B, MASKDWORD, 0x82110000);
 776         odm_set_bb_reg(p_dm_odm, REG_RX_IQK_PI_B, MASKDWORD, 0x28110000);
 777
 778         /* LO calibration setting */
 779         odm_set_bb_reg(p_dm_odm, REG_IQK_AGC_RSP, MASKDWORD, 0x0046a911);
 780
 781         /* leave IQK mode */
 782         odm_set_bb_reg(p_dm_odm, REG_FPGA0_IQK, 0xffffff00, 0x000000);
 783
 784         /* modify RXIQK mode table */
 785         odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, RF_WE_LUT, 0x80000, 0x1);
 786         odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, RF_RCK_OS, RFREGOFFSETMASK, 0x30000);
 787         odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, RF_TXPA_G1, RFREGOFFSETMASK, 0x00007);
 788         /*IQK PA off*/
 789         /*      odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, RF_TXPA_G2, RFREGOFFSETMASK, 0xf7fb7); */
 790         odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, RF_TXPA_G2, RFREGOFFSETMASK, 0x57db7);
 791
 792         odm_set_bb_reg(p_dm_odm, REG_FPGA0_IQK, 0xffffff00, 0x808000);
 793
 794 #if 1
 795         /*path setting*/
 796         /*Save Original path Owner, Original GNT*/
 797         original_path = odm_get_mac_reg(p_dm_odm, REG_LTECOEX_PATH_CONTROL, MASKDWORD);  /*save 0x70*/
 798         odm_set_bb_reg(p_dm_odm, REG_LTECOEX_CTRL, MASKDWORD, 0x800f0038);
 799         ODM_delay_ms(1);
 800         original_gnt = odm_get_bb_reg(p_dm_odm, REG_LTECOEX_READ_DATA, MASKDWORD);  /*save 0x38*/
 801
 802         /*set GNT_WL=1/GNT_BT=0  and path owner to WiFi for pause BT traffic*/
 803         odm_set_bb_reg(p_dm_odm, REG_LTECOEX_WRITE_DATA, MASKDWORD, 0x00007700);
 804         odm_set_bb_reg(p_dm_odm, REG_LTECOEX_CTRL, MASKDWORD, 0xc0020038);      /*0x38[15:8] = 0x77*/
 805         odm_set_mac_reg(p_dm_odm, REG_LTECOEX_PATH_CONTROL, BIT(26), 0x1);  /*0x70[26] =1 --> path Owner to WiFi*/
 806 #endif
 807
 808         /* One shot, path A LOK & IQK */
 809         odm_set_bb_reg(p_dm_odm, REG_IQK_AGC_PTS, MASKDWORD, 0xf9000000);
 810         odm_set_bb_reg(p_dm_odm, REG_IQK_AGC_PTS, MASKDWORD, 0xf8000000);
 811
 812         /* delay x ms */
 813         ODM_delay_ms(IQK_DELAY_TIME_8703B);
 814         ktime = 0;
 815         while ((odm_get_bb_reg(p_dm_odm, 0xe90, MASKDWORD) == 0) && ktime < 10) {
 816                 ODM_delay_ms(5);
 817                 ktime++;
 818         }
 819
 820 #if 1
 821         /*path setting*/
 822         /*Restore GNT_WL/GNT_BT  and path owner*/
 823         odm_set_bb_reg(p_dm_odm, REG_LTECOEX_WRITE_DATA, MASKDWORD, original_gnt);
 824         odm_set_bb_reg(p_dm_odm, REG_LTECOEX_CTRL, MASKDWORD, 0xc00f0038);
 825         odm_set_mac_reg(p_dm_odm, REG_LTECOEX_PATH_CONTROL, 0xffffffff, original_path);
 826
 827         original_path = odm_get_mac_reg(p_dm_odm, REG_LTECOEX_PATH_CONTROL, MASKDWORD);  /*save 0x70*/
 828         odm_set_bb_reg(p_dm_odm, REG_LTECOEX_CTRL, MASKDWORD, 0x800f0038);
 829         ODM_delay_ms(1);
 830         original_gnt = odm_get_bb_reg(p_dm_odm, REG_LTECOEX_READ_DATA, MASKDWORD);  /*save 0x38*/
 831
 832
 833 #endif
 834
 835         /* leave IQK mode */
 836         odm_set_bb_reg(p_dm_odm, REG_FPGA0_IQK, 0xffffff00, 0x000000);
 837
 838         /* Check failed */
 839         reg_eac = odm_get_bb_reg(p_dm_odm, REG_RX_POWER_AFTER_IQK_A_2, MASKDWORD);
 840         reg_e94 = odm_get_bb_reg(p_dm_odm, REG_TX_POWER_BEFORE_IQK_A, MASKDWORD);
 841         reg_e9c = odm_get_bb_reg(p_dm_odm, REG_TX_POWER_AFTER_IQK_A, MASKDWORD);
 842         ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]0xeac = 0x%x\n", reg_eac));
 843         ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]0xe94 = 0x%x, 0xe9c = 0x%x\n", reg_e94, reg_e9c));
 844         /*monitor image power before & after IQK*/
 845         ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]0xe90(before IQK)= 0x%x, 0xe98(afer IQK) = 0x%x\n",
 846                 odm_get_bb_reg(p_dm_odm, 0xe90, MASKDWORD), odm_get_bb_reg(p_dm_odm, 0xe98, MASKDWORD)));
 847
 848         /* Allen 20131125 */
 849         tmp = (reg_e9c & 0x03FF0000) >> 16;
 850         if ((tmp & 0x200) > 0)
 851                 tmp = 0x400 - tmp;
 852
 853         if (!(reg_eac & BIT(28)) &&
 854             (((reg_e94 & 0x03FF0000) >> 16) != 0x142) &&
 855             (((reg_e9c & 0x03FF0000) >> 16) != 0x42))
 856
 857                 result |= 0x01;
 858         else                                                    /* if Tx not OK, ignore Rx */
 859                 return result;
 860
 861
 862
 863         u4tmp = 0x80007C00 | (reg_e94 & 0x3FF0000)  | ((reg_e9c & 0x3FF0000) >> 16);
 864         odm_set_bb_reg(p_dm_odm, REG_TX_IQK, MASKDWORD, u4tmp);
 865         ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]0xe40 = 0x%x u4tmp = 0x%x\n", odm_get_bb_reg(p_dm_odm, REG_TX_IQK, MASKDWORD), u4tmp));
 866
 867         /* 1 RX IQK */
 868         ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]RX IQK\n"));
 869
 870         /* IQK setting */
 871         odm_set_bb_reg(p_dm_odm, REG_RX_IQK, MASKDWORD, 0x01004800);
 872
 873         /* path-A IQK setting */
 874         odm_set_bb_reg(p_dm_odm, REG_TX_IQK_TONE_A, MASKDWORD, 0x38008c1c);
 875         odm_set_bb_reg(p_dm_odm, REG_RX_IQK_TONE_A, MASKDWORD, 0x18008c1c);
 876         odm_set_bb_reg(p_dm_odm, REG_TX_IQK_TONE_B, MASKDWORD, 0x38008c1c);
 877         odm_set_bb_reg(p_dm_odm, REG_RX_IQK_TONE_B, MASKDWORD, 0x38008c1c);
 878
 879         odm_set_bb_reg(p_dm_odm, REG_TX_IQK_PI_A, MASKDWORD, 0x82110000);
 880         odm_set_bb_reg(p_dm_odm, REG_RX_IQK_PI_A, MASKDWORD, 0x28160c1f);
 881         /*      odm_set_bb_reg(p_dm_odm, REG_RX_IQK_PI_A, MASKDWORD, 0x2816001f);*/
 882         odm_set_bb_reg(p_dm_odm, REG_TX_IQK_PI_B, MASKDWORD, 0x82110000);
 883         odm_set_bb_reg(p_dm_odm, REG_RX_IQK_PI_B, MASKDWORD, 0x28110000);
 884
 885         /* LO calibration setting */
 886         odm_set_bb_reg(p_dm_odm, REG_IQK_AGC_RSP, MASKDWORD, 0x0046a8d1);
 887
 888
 889         /* modify RXIQK mode table */
 890         odm_set_bb_reg(p_dm_odm, REG_FPGA0_IQK, 0xffffff00, 0x000000);
 891         odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, RF_WE_LUT, 0x80000, 0x1);
 892         odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, RF_RCK_OS, RFREGOFFSETMASK, 0x30000);
 893         odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, RF_TXPA_G1, RFREGOFFSETMASK, 0x00007);
 894         /*PA off*/
 895         odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, RF_TXPA_G2, RFREGOFFSETMASK, 0xf7d77);
 896
 897         /*PA, PAD setting*/
 898         odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0xdf, 0x800, 0x1);
 899         odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0x55, 0x0007f, 0x5);
 900
 901         /*enter IQK mode*/
 902         odm_set_bb_reg(p_dm_odm, REG_FPGA0_IQK, 0xffffff00, 0x808000);
 903
 904 #if 1
 905         /*path setting*/
 906         /*Save Original path Owner, Original GNT*/
 907         original_path = odm_get_mac_reg(p_dm_odm, REG_LTECOEX_PATH_CONTROL, MASKDWORD);  /*save 0x70*/
 908         odm_set_bb_reg(p_dm_odm, REG_LTECOEX_CTRL, MASKDWORD, 0x800f0038);
 909         ODM_delay_ms(1);
 910         original_gnt = odm_get_bb_reg(p_dm_odm, REG_LTECOEX_READ_DATA, MASKDWORD);  /*save 0x38*/
 911
 912         /*set GNT_WL=1/GNT_BT=0  and path owner to WiFi for pause BT traffic*/
 913         odm_set_bb_reg(p_dm_odm, REG_LTECOEX_WRITE_DATA, MASKDWORD, 0x00007700);
 914         odm_set_bb_reg(p_dm_odm, REG_LTECOEX_CTRL, MASKDWORD, 0xc0020038);      /*0x38[15:8] = 0x77*/
 915         odm_set_mac_reg(p_dm_odm, REG_LTECOEX_PATH_CONTROL, BIT(26), 0x1);  /*0x70[26] =1 --> path Owner to WiFi*/
 916 #endif
 917
 918         /* One shot, path A LOK & IQK */
 919         odm_set_bb_reg(p_dm_odm, REG_IQK_AGC_PTS, MASKDWORD, 0xf9000000);
 920         odm_set_bb_reg(p_dm_odm, REG_IQK_AGC_PTS, MASKDWORD, 0xf8000000);
 921
 922         /* delay x ms */
 923         ODM_delay_ms(IQK_DELAY_TIME_8703B);
 924         ktime = 0;
 925         while ((odm_get_bb_reg(p_dm_odm, 0xe90, MASKDWORD) == 0) && ktime < 10) {
 926                 ODM_delay_ms(5);
 927                 ktime++;
 928         }
 929
 930 #if 1
 931         /*path setting*/
 932         /*Restore GNT_WL/GNT_BT  and path owner*/
 933         odm_set_bb_reg(p_dm_odm, REG_LTECOEX_WRITE_DATA, MASKDWORD, original_gnt);
 934         odm_set_bb_reg(p_dm_odm, REG_LTECOEX_CTRL, MASKDWORD, 0xc00f0038);
 935         odm_set_mac_reg(p_dm_odm, REG_LTECOEX_PATH_CONTROL, 0xffffffff, original_path);
 936
 937         original_path = odm_get_mac_reg(p_dm_odm, REG_LTECOEX_PATH_CONTROL, MASKDWORD);  /*save 0x70*/
 938         odm_set_bb_reg(p_dm_odm, REG_LTECOEX_CTRL, MASKDWORD, 0x800f0038);
 939         ODM_delay_ms(1);
 940         original_gnt = odm_get_bb_reg(p_dm_odm, REG_LTECOEX_READ_DATA, MASKDWORD);  /*save 0x38*/
 941
 942
 943 #endif
 944
 945         /*leave IQK mode*/
 946         odm_set_bb_reg(p_dm_odm, REG_FPGA0_IQK, 0xffffff00, 0x000000);
 947         /*      PA/PAD controlled by 0x0 */
 948         odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0xdf, 0x800, 0x0);
 949
 950         /* Check failed */
 951         reg_eac = odm_get_bb_reg(p_dm_odm, REG_RX_POWER_AFTER_IQK_A_2, MASKDWORD);
 952         reg_ea4 = odm_get_bb_reg(p_dm_odm, REG_RX_POWER_BEFORE_IQK_A_2, MASKDWORD);
 953         ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]0xeac = 0x%x\n", reg_eac));
 954         ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]0xea4 = 0x%x, 0xeac = 0x%x\n", reg_ea4, reg_eac));
 955         /* monitor image power before & after IQK */
 956         ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]0xea0(before IQK)= 0x%x, 0xea8(afer IQK) = 0x%x\n",
 957                 odm_get_bb_reg(p_dm_odm, 0xea0, MASKDWORD), odm_get_bb_reg(p_dm_odm, 0xea8, MASKDWORD)));
 958
 959         /* Allen 20131125 */
 960         tmp = (reg_eac & 0x03FF0000) >> 16;
 961         if ((tmp & 0x200) > 0)
 962                 tmp = 0x400 - tmp;
 963
 964         if (!(reg_eac & BIT(27)) &&             /*if Tx is OK, check whether Rx is OK*/
 965             (((reg_ea4 & 0x03FF0000) >> 16) != 0x132) &&
 966             (((reg_eac & 0x03FF0000) >> 16) != 0x36) &&
 967             (((reg_ea4 & 0x03FF0000) >> 16) < 0x11a) &&
 968             (((reg_ea4 & 0x03FF0000) >> 16) > 0xe6) &&
 969             (tmp < 0x1a))
 970                 result |= 0x02;
 971         else                                                    /* if Tx not OK, ignore Rx */
 972                 ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("path A Rx IQK fail!!\n"));
 973
 974         return result;
 975 }
 976
 977
 978 void
 979 _phy_path_a_fill_iqk_matrix8703b(
 980 #if (DM_ODM_SUPPORT_TYPE & ODM_AP)
 981         struct PHY_DM_STRUCT            *p_dm_odm,
 982 #else
 983         struct _ADAPTER *p_adapter,
 984 #endif
 985         boolean is_iqk_ok,
 986         s32             result[][8],
 987         u8              final_candidate,
 988         boolean         is_tx_only
 989 )
 990 {
 991         u32     oldval_0, X, TX0_A, reg, tmp0xc80, tmp0xc94, tmp0xc4c, tmp0xc14, tmp0xca0;
 992         s32     Y, TX0_C;
 993 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
 994         HAL_DATA_TYPE   *p_hal_data = GET_HAL_DATA(p_adapter);
 995 #if (DM_ODM_SUPPORT_TYPE == ODM_CE)
 996         struct PHY_DM_STRUCT            *p_dm_odm = &p_hal_data->odmpriv;
 997 #endif
 998 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
 999         struct PHY_DM_STRUCT            *p_dm_odm = &p_hal_data->DM_OutSrc;
1000 #endif
1001 #endif
1002         struct odm_rf_calibration_structure     *p_rf_calibrate_info = &(p_dm_odm->rf_calibrate_info);
1003
1004         ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]path A IQ Calibration %s !\n", (is_iqk_ok) ? "Success" : "Failed"));
1005
1006         if (final_candidate == 0xFF)
1007                 return;
1008
1009         else if (is_iqk_ok) {
1010
1011                 oldval_0 = (odm_get_bb_reg(p_dm_odm, REG_OFDM_0_XA_TX_IQ_IMBALANCE, MASKDWORD) >> 22) & 0x3FF;
1012
1013                 X = result[final_candidate][0];
1014                 if ((X & 0x00000200) != 0)
1015                         X = X | 0xFFFFFC00;
1016                 TX0_A = (X * oldval_0) >> 8;
1017                 ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]X = 0x%x, TX0_A = 0x%x, oldval_0 0x%x\n", X, TX0_A, oldval_0));
1018                 tmp0xc80 = (odm_get_bb_reg(p_dm_odm, REG_OFDM_0_XA_TX_IQ_IMBALANCE, MASKDWORD) & 0xfffffc00) | (TX0_A & 0x3ff);
1019                 tmp0xc4c = (((X * oldval_0 >> 7) & 0x1) << 31) | (odm_get_bb_reg(p_dm_odm, REG_OFDM_0_ECCA_THRESHOLD, MASKDWORD) & 0x7fffffff);
1020
1021                 Y = result[final_candidate][1];
1022                 if ((Y & 0x00000200) != 0)
1023                         Y = Y | 0xFFFFFC00;
1024
1025                 /* 2 Tx IQC */
1026                 TX0_C = (Y * oldval_0) >> 8;
1027                 ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]Y = 0x%x, TX = 0x%x\n", Y, TX0_C));
1028
1029                 tmp0xc94 = (((TX0_C & 0x3C0) >> 6) << 28) | (odm_get_bb_reg(p_dm_odm, REG_OFDM_0_XC_TX_AFE, MASKDWORD) & 0x0fffffff);
1030
1031                 p_rf_calibrate_info->tx_iqc_8703b[idx_0xc94][KEY] = REG_OFDM_0_XC_TX_AFE;
1032                 p_rf_calibrate_info->tx_iqc_8703b[idx_0xc94][VAL] = tmp0xc94;
1033
1034                 tmp0xc80 = (tmp0xc80 & 0xffc0ffff) | (TX0_C & 0x3F) << 16;
1035
1036                 p_rf_calibrate_info->tx_iqc_8703b[idx_0xc80][KEY] = REG_OFDM_0_XA_TX_IQ_IMBALANCE;
1037                 p_rf_calibrate_info->tx_iqc_8703b[idx_0xc80][VAL] = tmp0xc80;
1038
1039                 tmp0xc4c = (tmp0xc4c & 0xdfffffff) | (((Y * oldval_0 >> 7) & 0x1) << 29);
1040
1041                 p_rf_calibrate_info->tx_iqc_8703b[idx_0xc4c][KEY] = REG_OFDM_0_ECCA_THRESHOLD;
1042                 p_rf_calibrate_info->tx_iqc_8703b[idx_0xc4c][VAL] = tmp0xc4c;
1043
1044                 if (is_tx_only) {
1045                         ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]_phy_path_a_fill_iqk_matrix8703b only Tx OK\n"));
1046
1047                         /* <20130226, Kordan> Saving RxIQC, otherwise not initialized. */
1048                         p_rf_calibrate_info->rx_iqc_8703b[idx_0xca0][KEY] = REG_OFDM_0_RX_IQ_EXT_ANTA;
1049                         p_rf_calibrate_info->rx_iqc_8703b[idx_0xca0][VAL] = 0xfffffff & odm_get_bb_reg(p_dm_odm, REG_OFDM_0_RX_IQ_EXT_ANTA, MASKDWORD);
1050                         p_rf_calibrate_info->rx_iqc_8703b[idx_0xc14][KEY] = REG_OFDM_0_XA_RX_IQ_IMBALANCE;
1051                         p_rf_calibrate_info->rx_iqc_8703b[idx_0xc14][VAL] = 0x40000100;
1052                         return;
1053                 }
1054
1055                 reg = result[final_candidate][2];
1056 #if (DM_ODM_SUPPORT_TYPE == ODM_AP)
1057                 if (RTL_ABS(reg, 0x100) >= 16)
1058                         reg = 0x100;
1059 #endif
1060
1061                 /* 2 Rx IQC */
1062                 tmp0xc14 = (0x40000100 & 0xfffffc00) | reg;
1063
1064                 reg = result[final_candidate][3] & 0x3F;
1065                 tmp0xc14 = (tmp0xc14 & 0xffff03ff) | (reg << 10);
1066
1067                 p_rf_calibrate_info->rx_iqc_8703b[idx_0xc14][KEY] = REG_OFDM_0_XA_RX_IQ_IMBALANCE;
1068                 p_rf_calibrate_info->rx_iqc_8703b[idx_0xc14][VAL] = tmp0xc14;
1069
1070                 reg = (result[final_candidate][3] >> 6) & 0xF;
1071                 tmp0xca0 = odm_get_bb_reg(p_dm_odm, REG_OFDM_0_RX_IQ_EXT_ANTA, 0x0fffffff) | (reg << 28);
1072
1073                 p_rf_calibrate_info->rx_iqc_8703b[idx_0xca0][KEY] = REG_OFDM_0_RX_IQ_EXT_ANTA;
1074                 p_rf_calibrate_info->rx_iqc_8703b[idx_0xca0][VAL] = tmp0xca0;
1075         }
1076 }
1077
1078 #if 0
1079 void
1080 _phy_path_b_fill_iqk_matrix8703b(
1081 #if (DM_ODM_SUPPORT_TYPE & ODM_AP)
1082         struct PHY_DM_STRUCT            *p_dm_odm,
1083 #else
1084         struct _ADAPTER *p_adapter,
1085 #endif
1086         boolean is_iqk_ok,
1087         s32             result[][8],
1088         u8              final_candidate,
1089         boolean         is_tx_only                      /* do Tx only */
1090 )
1091 {
1092         u32     oldval_1, X, TX1_A, reg, tmp0xc80, tmp0xc94, tmp0xc4c, tmp0xc14, tmp0xca0;
1093         s32     Y, TX1_C;
1094 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
1095         HAL_DATA_TYPE   *p_hal_data = GET_HAL_DATA(p_adapter);
1096 #if (DM_ODM_SUPPORT_TYPE == ODM_CE)
1097         struct PHY_DM_STRUCT            *p_dm_odm = &p_hal_data->odmpriv;
1098 #endif
1099 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
1100         struct PHY_DM_STRUCT            *p_dm_odm = &p_hal_data->DM_OutSrc;
1101 #endif
1102 #endif
1103         struct odm_rf_calibration_structure     *p_rf_calibrate_info = &(p_dm_odm->rf_calibrate_info);
1104
1105         ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]path B IQ Calibration %s !\n", (is_iqk_ok) ? "Success" : "Failed"));
1106
1107         if (final_candidate == 0xFF)
1108                 return;
1109
1110         else if (is_iqk_ok) {
1111                 oldval_1 = (odm_get_bb_reg(p_dm_odm, REG_OFDM_0_XA_TX_IQ_IMBALANCE, MASKDWORD) >> 22) & 0x3FF;
1112
1113
1114                 X = result[final_candidate][4];
1115                 if ((X & 0x00000200) != 0)
1116                         X = X | 0xFFFFFC00;
1117                 TX1_A = (X * oldval_1) >> 8;
1118                 ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]X = 0x%x, TX1_A = 0x%x\n", X, TX1_A));
1119
1120                 tmp0xc80 = (odm_get_bb_reg(p_dm_odm, REG_OFDM_0_XA_TX_IQ_IMBALANCE, MASKDWORD) & 0xfffffc00) | (TX1_A & 0x3ff);
1121                 tmp0xc4c = (((X * oldval_1 >> 7) & 0x1) << 31) | (odm_get_bb_reg(p_dm_odm, REG_OFDM_0_ECCA_THRESHOLD, MASKDWORD) & 0x7fffffff);
1122
1123                 Y = result[final_candidate][5];
1124                 if ((Y & 0x00000200) != 0)
1125                         Y = Y | 0xFFFFFC00;
1126
1127                 TX1_C = (Y * oldval_1) >> 8;
1128                 ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]Y = 0x%x, TX1_C = 0x%x\n", Y, TX1_C));
1129
1130                 /*2 Tx IQC*/
1131
1132                 tmp0xc94 = (((TX1_C & 0x3C0) >> 6) << 28) | (odm_get_bb_reg(p_dm_odm, REG_OFDM_0_XC_TX_AFE, MASKDWORD) & 0x0fffffff);
1133
1134                 p_rf_calibrate_info->tx_iqc_8703b[PATH_S0][idx_0xc94][KEY] = REG_OFDM_0_XC_TX_AFE;
1135                 p_rf_calibrate_info->tx_iqc_8703b[PATH_S0][idx_0xc94][VAL] = tmp0xc94;
1136
1137                 tmp0xc80 = (tmp0xc80 & 0xffc0ffff) | (TX1_C & 0x3F) << 16;
1138                 p_rf_calibrate_info->tx_iqc_8703b[PATH_S0][idx_0xc80][KEY] = REG_OFDM_0_XA_TX_IQ_IMBALANCE;
1139                 p_rf_calibrate_info->tx_iqc_8703b[PATH_S0][idx_0xc80][VAL] = tmp0xc80;
1140
1141                 tmp0xc4c = (tmp0xc4c & 0xdfffffff) | (((Y * oldval_1 >> 7) & 0x1) << 29);
1142                 p_rf_calibrate_info->tx_iqc_8703b[PATH_S0][idx_0xc4c][KEY] = REG_OFDM_0_ECCA_THRESHOLD;
1143                 p_rf_calibrate_info->tx_iqc_8703b[PATH_S0][idx_0xc4c][VAL] = tmp0xc4c;
1144
1145                 if (is_tx_only) {
1146                         ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]_phy_path_b_fill_iqk_matrix8703b only Tx OK\n"));
1147
1148                         p_rf_calibrate_info->rx_iqc_8703b[PATH_S0][idx_0xc14][KEY] = REG_OFDM_0_XA_RX_IQ_IMBALANCE;
1149                         p_rf_calibrate_info->rx_iqc_8703b[PATH_S0][idx_0xc14][VAL] = 0x40000100;
1150                         p_rf_calibrate_info->rx_iqc_8703b[PATH_S0][idx_0xca0][KEY] = REG_OFDM_0_RX_IQ_EXT_ANTA;
1151                         p_rf_calibrate_info->rx_iqc_8703b[PATH_S0][idx_0xca0][VAL] = 0x0fffffff & odm_get_bb_reg(p_dm_odm, REG_OFDM_0_RX_IQ_EXT_ANTA, MASKDWORD);
1152                         return;
1153                 }
1154
1155                 /* 2 Rx IQC */
1156                 reg = result[final_candidate][6];
1157                 tmp0xc14 = (0x40000100 & 0xfffffc00) | reg;
1158
1159                 reg = result[final_candidate][7] & 0x3F;
1160                 tmp0xc14 = (tmp0xc14 & 0xffff03ff) | (reg << 10);
1161
1162                 p_rf_calibrate_info->rx_iqc_8703b[PATH_S0][idx_0xc14][KEY] = REG_OFDM_0_XA_RX_IQ_IMBALANCE;
1163                 p_rf_calibrate_info->rx_iqc_8703b[PATH_S0][idx_0xc14][VAL] = tmp0xc14;
1164
1165                 reg = (result[final_candidate][7] >> 6) & 0xF;
1166                 tmp0xca0 = odm_get_bb_reg(p_dm_odm, REG_OFDM_0_RX_IQ_EXT_ANTA, 0x0fffffff) | (reg << 28);
1167
1168                 p_rf_calibrate_info->rx_iqc_8703b[PATH_S0][idx_0xca0][KEY] = REG_OFDM_0_RX_IQ_EXT_ANTA;
1169                 p_rf_calibrate_info->rx_iqc_8703b[PATH_S0][idx_0xca0][VAL] = tmp0xca0;
1170         }
1171 }
1172 #endif
1173
1174 boolean
1175 odm_set_iqc_by_rfpath_8703b(
1176         struct PHY_DM_STRUCT            *p_dm_odm
1177 )
1178 {
1179
1180         struct odm_rf_calibration_structure     *p_rf_calibrate_info = &(p_dm_odm->rf_calibrate_info);
1181
1182
1183         if ((p_rf_calibrate_info->tx_iqc_8703b[idx_0xc80][VAL] != 0x0) && (p_rf_calibrate_info->rx_iqc_8703b[idx_0xc14][VAL] != 0x0)) {
1184
1185                 ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]reload RF IQC!!!\n"));
1186                 ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]0xc80 = 0x%x!!!\n", p_rf_calibrate_info->tx_iqc_8703b[idx_0xc80][VAL]));
1187                 ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]0xc14 = 0x%x!!!\n", p_rf_calibrate_info->tx_iqc_8703b[idx_0xc14][VAL]));
1188
1189                 /* TX IQC */
1190                 odm_set_bb_reg(p_dm_odm, p_rf_calibrate_info->tx_iqc_8703b[idx_0xc94][KEY], MASKH4BITS, (p_rf_calibrate_info->tx_iqc_8703b[idx_0xc94][VAL] >> 28));
1191                 odm_set_bb_reg(p_dm_odm, p_rf_calibrate_info->tx_iqc_8703b[idx_0xc80][KEY], MASKDWORD, p_rf_calibrate_info->tx_iqc_8703b[idx_0xc80][VAL]);
1192                 odm_set_bb_reg(p_dm_odm, p_rf_calibrate_info->tx_iqc_8703b[idx_0xc4c][KEY], BIT(31), (p_rf_calibrate_info->tx_iqc_8703b[idx_0xc4c][VAL] >> 31));
1193                 odm_set_bb_reg(p_dm_odm, p_rf_calibrate_info->tx_iqc_8703b[idx_0xc4c][KEY], BIT(29), ((p_rf_calibrate_info->tx_iqc_8703b[idx_0xc4c][VAL] & BIT(29)) >> 29));
1194
1195                 /* RX IQC */
1196                 odm_set_bb_reg(p_dm_odm, p_rf_calibrate_info->rx_iqc_8703b[idx_0xc14][KEY], MASKDWORD, p_rf_calibrate_info->rx_iqc_8703b[idx_0xc14][VAL]);
1197                 odm_set_bb_reg(p_dm_odm, p_rf_calibrate_info->rx_iqc_8703b[idx_0xca0][KEY], MASKDWORD, p_rf_calibrate_info->rx_iqc_8703b[idx_0xca0][VAL]);
1198                 return true;
1199
1200         } else {
1201                 ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]IQC value invalid!!!\n"));
1202                 return false;
1203         }
1204 }
1205
1206
1207 #if !(DM_ODM_SUPPORT_TYPE & ODM_WIN)
1208 boolean
1209 odm_check_power_status(
1210         struct _ADAPTER         *adapter)
1211 {
1212 #if 0
1213         HAL_DATA_TYPE                   *p_hal_data = GET_HAL_DATA(adapter);
1214         struct PHY_DM_STRUCT                            *p_dm_odm = &p_hal_data->DM_OutSrc;
1215         RT_RF_POWER_STATE       rt_state;
1216         PMGNT_INFO                              p_mgnt_info     = &(adapter->MgntInfo);
1217
1218         /* 2011/07/27 MH We are not testing ready~~!! We may fail to get correct value when init sequence.*/
1219         if (p_mgnt_info->init_adpt_in_progress == true) {
1220                 ODM_RT_TRACE(p_dm_odm, COMP_INIT, DBG_LOUD, ("odm_check_power_status Return true, due to initadapter"));
1221                 return  true;
1222         }
1223
1224
1225         /*      2011/07/19 MH We can not execute tx power tracking/ LLC calibrate or IQK.*/
1226
1227         phydm_get_hw_reg_interface(p_dm_odm, HW_VAR_RF_STATE, (u8 *)(&rt_state));
1228         if (adapter->is_driver_stopped || adapter->is_driver_is_going_to_pnp_set_power_sleep || rt_state == eRfOff) {
1229                 ODM_RT_TRACE(p_dm_odm, COMP_INIT, DBG_LOUD, ("odm_check_power_status Return false, due to %d/%d/%d\n",
1230                         adapter->is_driver_stopped, adapter->is_driver_is_going_to_pnp_set_power_sleep, rt_state));
1231                 return  false;
1232         }
1233 #endif
1234         return  true;
1235 }
1236 #endif
1237
1238 void
1239 _phy_save_adda_registers8703b(
1240 #if (DM_ODM_SUPPORT_TYPE & ODM_AP)
1241         struct PHY_DM_STRUCT            *p_dm_odm,
1242 #else
1243         struct _ADAPTER *p_adapter,
1244 #endif
1245         u32             *adda_reg,
1246         u32             *adda_backup,
1247         u32             register_num
1248 )
1249 {
1250         u32     i;
1251 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
1252         HAL_DATA_TYPE   *p_hal_data = GET_HAL_DATA(p_adapter);
1253 #if (DM_ODM_SUPPORT_TYPE == ODM_CE)
1254         struct PHY_DM_STRUCT            *p_dm_odm = &p_hal_data->odmpriv;
1255 #endif
1256 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
1257         struct PHY_DM_STRUCT            *p_dm_odm = &p_hal_data->DM_OutSrc;
1258 #endif
1259
1260         if (odm_check_power_status(p_adapter) == false)
1261                 return;
1262 #endif
1263
1264         /*      ODM_RT_TRACE(p_dm_odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Save ADDA parameters.\n")); */
1265         for (i = 0; i < register_num; i++)
1266                 adda_backup[i] = odm_get_bb_reg(p_dm_odm, adda_reg[i], MASKDWORD);
1267 }
1268
1269
1270 void
1271 _phy_save_mac_registers8703b(
1272 #if (DM_ODM_SUPPORT_TYPE & ODM_AP)
1273         struct PHY_DM_STRUCT            *p_dm_odm,
1274 #else
1275         struct _ADAPTER *p_adapter,
1276 #endif
1277         u32             *mac_reg,
1278         u32             *mac_backup
1279 )
1280 {
1281         u32     i;
1282 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
1283         HAL_DATA_TYPE   *p_hal_data = GET_HAL_DATA(p_adapter);
1284 #if (DM_ODM_SUPPORT_TYPE == ODM_CE)
1285         struct PHY_DM_STRUCT            *p_dm_odm = &p_hal_data->odmpriv;
1286 #endif
1287 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
1288         struct PHY_DM_STRUCT            *p_dm_odm = &p_hal_data->DM_OutSrc;
1289 #endif
1290 #endif
1291         /*      ODM_RT_TRACE(p_dm_odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Save MAC parameters.\n")); */
1292         for (i = 0; i < (IQK_MAC_REG_NUM - 1); i++)
1293                 mac_backup[i] = odm_read_1byte(p_dm_odm, mac_reg[i]);
1294
1295         mac_backup[i] = odm_read_4byte(p_dm_odm, mac_reg[i]);
1296
1297 }
1298
1299
1300 void
1301 _phy_reload_adda_registers8703b(
1302 #if (DM_ODM_SUPPORT_TYPE & ODM_AP)
1303         struct PHY_DM_STRUCT            *p_dm_odm,
1304 #else
1305         struct _ADAPTER *p_adapter,
1306 #endif
1307         u32             *adda_reg,
1308         u32             *adda_backup,
1309         u32             regiester_num
1310 )
1311 {
1312         u32     i;
1313 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
1314         HAL_DATA_TYPE   *p_hal_data = GET_HAL_DATA(p_adapter);
1315 #if (DM_ODM_SUPPORT_TYPE == ODM_CE)
1316         struct PHY_DM_STRUCT            *p_dm_odm = &p_hal_data->odmpriv;
1317 #endif
1318 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
1319         struct PHY_DM_STRUCT            *p_dm_odm = &p_hal_data->DM_OutSrc;
1320 #endif
1321 #endif
1322
1323         /*      ODM_RT_TRACE(p_dm_odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Reload ADDA power saving parameters !\n")); */
1324         for (i = 0 ; i < regiester_num; i++)
1325                 odm_set_bb_reg(p_dm_odm, adda_reg[i], MASKDWORD, adda_backup[i]);
1326
1327 }
1328
1329 void
1330 _phy_reload_mac_registers8703b(
1331 #if (DM_ODM_SUPPORT_TYPE & ODM_AP)
1332         struct PHY_DM_STRUCT            *p_dm_odm,
1333 #else
1334         struct _ADAPTER *p_adapter,
1335 #endif
1336         u32             *mac_reg,
1337         u32             *mac_backup
1338 )
1339 {
1340         u32     i;
1341 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
1342         HAL_DATA_TYPE   *p_hal_data = GET_HAL_DATA(p_adapter);
1343 #if (DM_ODM_SUPPORT_TYPE == ODM_CE)
1344         struct PHY_DM_STRUCT            *p_dm_odm = &p_hal_data->odmpriv;
1345 #endif
1346 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
1347         struct PHY_DM_STRUCT            *p_dm_odm = &p_hal_data->DM_OutSrc;
1348 #endif
1349 #endif
1350         /*      ODM_RT_TRACE(p_dm_odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD,  ("Reload MAC parameters !\n")); */
1351         for (i = 0 ; i < (IQK_MAC_REG_NUM - 1); i++)
1352                 odm_write_1byte(p_dm_odm, mac_reg[i], (u8)mac_backup[i]);
1353
1354         odm_write_4byte(p_dm_odm, mac_reg[i], mac_backup[i]);
1355 }
1356
1357
1358 void
1359 _phy_path_adda_on8703b(
1360 #if (DM_ODM_SUPPORT_TYPE & ODM_AP)
1361         struct PHY_DM_STRUCT            *p_dm_odm,
1362 #else
1363         struct _ADAPTER *p_adapter,
1364 #endif
1365         u32             *adda_reg,
1366         boolean         is_path_a_on
1367 )
1368 {
1369         u32     path_on;
1370         u32     i;
1371 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
1372         HAL_DATA_TYPE   *p_hal_data = GET_HAL_DATA(p_adapter);
1373 #if (DM_ODM_SUPPORT_TYPE == ODM_CE)
1374         struct PHY_DM_STRUCT            *p_dm_odm = &p_hal_data->odmpriv;
1375 #endif
1376 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
1377         struct PHY_DM_STRUCT            *p_dm_odm = &p_hal_data->DM_OutSrc;
1378 #endif
1379 #endif
1380         /*      ODM_RT_TRACE(p_dm_odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("ADDA ON.\n")); */
1381
1382         path_on = 0x03c00014;
1383
1384
1385         for (i = 0; i < IQK_ADDA_REG_NUM; i++)
1386                 odm_set_bb_reg(p_dm_odm, adda_reg[i], MASKDWORD, path_on);
1387
1388 }
1389
1390 void
1391 _phy_mac_setting_calibration8703b(
1392 #if (DM_ODM_SUPPORT_TYPE & ODM_AP)
1393         struct PHY_DM_STRUCT            *p_dm_odm,
1394 #else
1395         struct _ADAPTER *p_adapter,
1396 #endif
1397         u32             *mac_reg,
1398         u32             *mac_backup
1399 )
1400 {
1401         u32     i = 0;
1402 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
1403         HAL_DATA_TYPE   *p_hal_data = GET_HAL_DATA(p_adapter);
1404 #if (DM_ODM_SUPPORT_TYPE == ODM_CE)
1405         struct PHY_DM_STRUCT            *p_dm_odm = &p_hal_data->odmpriv;
1406 #endif
1407 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
1408         struct PHY_DM_STRUCT            *p_dm_odm = &p_hal_data->DM_OutSrc;
1409 #endif
1410 #endif
1411         /*      ODM_RT_TRACE(p_dm_odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("MAC settings for Calibration.\n")); */
1412
1413         odm_write_1byte(p_dm_odm, mac_reg[i], 0x3F);
1414
1415         for (i = 1 ; i < (IQK_MAC_REG_NUM - 1); i++)
1416                 odm_write_1byte(p_dm_odm, mac_reg[i], (u8)(mac_backup[i] & (~BIT(3))));
1417
1418         odm_write_1byte(p_dm_odm, mac_reg[i], (u8)(mac_backup[i] & (~BIT(5))));
1419
1420 }
1421
1422 boolean
1423 phy_simularity_compare_8703b(
1424 #if (DM_ODM_SUPPORT_TYPE & ODM_AP)
1425         struct PHY_DM_STRUCT            *p_dm_odm,
1426 #else
1427         struct _ADAPTER *p_adapter,
1428 #endif
1429         s32             result[][8],
1430         u8               c1,
1431         u8               c2
1432 )
1433 {
1434         u32             i, j, diff, simularity_bit_map, bound = 0;
1435 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
1436         HAL_DATA_TYPE   *p_hal_data = GET_HAL_DATA(p_adapter);
1437 #if (DM_ODM_SUPPORT_TYPE == ODM_CE)
1438         struct PHY_DM_STRUCT            *p_dm_odm = &p_hal_data->odmpriv;
1439 #endif
1440
1441 #endif
1442         u8              final_candidate[2] = {0xFF, 0xFF};      /* for path A and path B */
1443         boolean         is_result = true;
1444         /* #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) */
1445         /*      bool            is2T = IS_92C_SERIAL( p_hal_data->version_id);
1446          * #else */
1447         boolean         is2T = true;
1448         /* #endif */
1449
1450         s32 tmp1 = 0, tmp2 = 0;
1451
1452         if (is2T)
1453                 bound = 8;
1454         else
1455                 bound = 4;
1456
1457         /*      ODM_RT_TRACE(p_dm_odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("===> IQK:phy_simularity_compare_8192e c1 %d c2 %d!!!\n", c1, c2)); */
1458
1459
1460         simularity_bit_map = 0;
1461
1462         for (i = 0; i < bound; i++) {
1463
1464                 if ((i == 1) || (i == 3) || (i == 5) || (i == 7)) {
1465                         if ((result[c1][i] & 0x00000200) != 0)
1466                                 tmp1 = result[c1][i] | 0xFFFFFC00;
1467                         else
1468                                 tmp1 = result[c1][i];
1469
1470                         if ((result[c2][i] & 0x00000200) != 0)
1471                                 tmp2 = result[c2][i] | 0xFFFFFC00;
1472                         else
1473                                 tmp2 = result[c2][i];
1474                 } else {
1475                         tmp1 = result[c1][i];
1476                         tmp2 = result[c2][i];
1477                 }
1478
1479                 diff = (tmp1 > tmp2) ? (tmp1 - tmp2) : (tmp2 - tmp1);
1480
1481                 if (diff > MAX_TOLERANCE) {
1482                         /*                      ODM_RT_TRACE(p_dm_odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD,  ("IQK:differnece overflow %d index %d compare1 0x%x compare2 0x%x!!!\n",  diff, i, result[c1][i], result[c2][i])); */
1483
1484                         if ((i == 2 || i == 6) && !simularity_bit_map) {
1485                                 if (result[c1][i] + result[c1][i + 1] == 0)
1486                                         final_candidate[(i / 4)] = c2;
1487                                 else if (result[c2][i] + result[c2][i + 1] == 0)
1488                                         final_candidate[(i / 4)] = c1;
1489                                 else
1490                                         simularity_bit_map = simularity_bit_map | (1 << i);
1491                         } else
1492                                 simularity_bit_map = simularity_bit_map | (1 << i);
1493                 }
1494         }
1495
1496         /*      ODM_RT_TRACE(p_dm_odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK:phy_simularity_compare_8192e simularity_bit_map   %x !!!\n", simularity_bit_map)); */
1497
1498         if (simularity_bit_map == 0) {
1499                 for (i = 0; i < (bound / 4); i++) {
1500                         if (final_candidate[i] != 0xFF) {
1501                                 for (j = i * 4; j < (i + 1) * 4 - 2; j++)
1502                                         result[3][j] = result[final_candidate[i]][j];
1503                                 is_result = false;
1504                         }
1505                 }
1506                 return is_result;
1507         } else {
1508
1509                 if (!(simularity_bit_map & 0x03)) {             /*path A TX OK*/
1510                         for (i = 0; i < 2; i++)
1511                                 result[3][i] = result[c1][i];
1512                 }
1513
1514                 if (!(simularity_bit_map & 0x0c)) {             /*path A RX OK*/
1515                         for (i = 2; i < 4; i++)
1516                                 result[3][i] = result[c1][i];
1517                 }
1518
1519                 if (!(simularity_bit_map & 0x30)) {     /*path B TX OK*/
1520                         for (i = 4; i < 6; i++)
1521                                 result[3][i] = result[c1][i];
1522
1523                 }
1524
1525                 if (!(simularity_bit_map & 0xc0)) {     /*path B RX OK*/
1526                         for (i = 6; i < 8; i++)
1527                                 result[3][i] = result[c1][i];
1528                 }
1529                 return false;
1530         }
1531 }
1532
1533
1534
1535 void
1536 _phy_iq_calibrate_8703b(
1537 #if (DM_ODM_SUPPORT_TYPE & ODM_AP)
1538         struct PHY_DM_STRUCT            *p_dm_odm,
1539 #else
1540         struct _ADAPTER *p_adapter,
1541 #endif
1542         s32             result[][8],
1543         u8              t
1544 )
1545 {
1546 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
1547         HAL_DATA_TYPE   *p_hal_data = GET_HAL_DATA(p_adapter);
1548 #if (DM_ODM_SUPPORT_TYPE == ODM_CE)
1549         struct PHY_DM_STRUCT            *p_dm_odm = &p_hal_data->odmpriv;
1550 #endif
1551 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
1552         struct PHY_DM_STRUCT            *p_dm_odm = &p_hal_data->DM_OutSrc;
1553 #endif
1554 #endif
1555         u32                     i;
1556         u8                      path_aok, path_bok;
1557         u8                      tmp0xc50 = (u8)odm_get_bb_reg(p_dm_odm, 0xC50, MASKBYTE0);
1558         u8                      tmp0xc58 = (u8)odm_get_bb_reg(p_dm_odm, 0xC58, MASKBYTE0);
1559         u32                     ADDA_REG[IQK_ADDA_REG_NUM] = {
1560                 REG_FPGA0_XCD_SWITCH_CONTROL,           REG_BLUE_TOOTH,
1561                 REG_RX_WAIT_CCA,                REG_TX_CCK_RFON,
1562                 REG_TX_CCK_BBON,                REG_TX_OFDM_RFON,
1563                 REG_TX_OFDM_BBON,               REG_TX_TO_RX,
1564                 REG_TX_TO_TX,           REG_RX_CCK,
1565                 REG_RX_OFDM,            REG_RX_WAIT_RIFS,
1566                 REG_RX_TO_RX,           REG_STANDBY,
1567                 REG_SLEEP,              REG_PMPD_ANAEN
1568         };
1569         u32                     IQK_MAC_REG[IQK_MAC_REG_NUM] = {
1570                 REG_TXPAUSE,            REG_BCN_CTRL,
1571                 REG_BCN_CTRL_1, REG_GPIO_MUXCFG
1572         };
1573
1574         /*since 92C & 92D have the different define in IQK_BB_REG*/
1575         u32     IQK_BB_REG_92C[IQK_BB_REG_NUM] = {
1576                 REG_OFDM_0_TRX_PATH_ENABLE,             REG_OFDM_0_TR_MUX_PAR,
1577                 REG_FPGA0_XCD_RF_INTERFACE_SW,  REG_CONFIG_ANT_A,       REG_CONFIG_ANT_B,
1578                 REG_FPGA0_XAB_RF_INTERFACE_SW,  REG_FPGA0_XA_RF_INTERFACE_OE,
1579                 REG_FPGA0_XB_RF_INTERFACE_OE,           REG_CCK_0_AFE_SETTING
1580         };
1581
1582
1583
1584 #if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
1585         u32     retry_count = 2;
1586 #else
1587 #if MP_DRIVER
1588         const u32       retry_count = 1;
1589 #else
1590         const u32       retry_count = 2;
1591 #endif
1592 #endif
1593
1594         /* Note: IQ calibration must be performed after loading*/
1595         /*PHY_REG.txt , and radio_a, radio_b.txt*/
1596
1597         /* u32 bbvalue; */
1598
1599 #if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
1600 #ifdef MP_TEST
1601         if (p_dm_odm->priv->pshare->rf_ft_var.mp_specific)
1602                 retry_count = 9;
1603 #endif
1604 #endif
1605
1606
1607         if (t == 0) {
1608                 /*               bbvalue = odm_get_bb_reg(p_dm_odm, REG_FPGA0_RFMOD, MASKDWORD);
1609                  *                      RT_DISP(FINIT, INIT_IQK, ("_phy_iq_calibrate_8188e()==>0x%08x\n",bbvalue)); */
1610
1611                 ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]IQ Calibration for %d times\n", t));
1612
1613                 /* Save ADDA parameters, turn path A ADDA on*/
1614 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
1615                 _phy_save_adda_registers8703b(p_adapter, ADDA_REG, p_dm_odm->rf_calibrate_info.ADDA_backup, IQK_ADDA_REG_NUM);
1616                 _phy_save_mac_registers8703b(p_adapter, IQK_MAC_REG, p_dm_odm->rf_calibrate_info.IQK_MAC_backup);
1617                 _phy_save_adda_registers8703b(p_adapter, IQK_BB_REG_92C, p_dm_odm->rf_calibrate_info.IQK_BB_backup, IQK_BB_REG_NUM);
1618 #else
1619                 _phy_save_adda_registers8703b(p_dm_odm, ADDA_REG, p_dm_odm->rf_calibrate_info.ADDA_backup, IQK_ADDA_REG_NUM);
1620                 _phy_save_mac_registers8703b(p_dm_odm, IQK_MAC_REG, p_dm_odm->rf_calibrate_info.IQK_MAC_backup);
1621                 _phy_save_adda_registers8703b(p_dm_odm, IQK_BB_REG_92C, p_dm_odm->rf_calibrate_info.IQK_BB_backup, IQK_BB_REG_NUM);
1622 #endif
1623         }
1624         ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]IQ Calibration for %d times\n", t));
1625
1626 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
1627
1628         _phy_path_adda_on8703b(p_adapter, ADDA_REG, true);
1629 #else
1630         _phy_path_adda_on8703b(p_dm_odm, ADDA_REG, true);
1631 #endif
1632
1633
1634         /* MAC settings */
1635 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
1636         _phy_mac_setting_calibration8703b(p_adapter, IQK_MAC_REG, p_dm_odm->rf_calibrate_info.IQK_MAC_backup);
1637 #else
1638         _phy_mac_setting_calibration8703b(p_dm_odm, IQK_MAC_REG, p_dm_odm->rf_calibrate_info.IQK_MAC_backup);
1639 #endif
1640
1641         /* BB setting */
1642         /*odm_set_bb_reg(p_dm_odm, REG_FPGA0_RFMOD, BIT24, 0x00);*/
1643         odm_set_bb_reg(p_dm_odm, REG_CCK_0_AFE_SETTING, 0x0f000000, 0xf);
1644         odm_set_bb_reg(p_dm_odm, REG_OFDM_0_TRX_PATH_ENABLE, MASKDWORD, 0x03a05600);
1645         odm_set_bb_reg(p_dm_odm, REG_OFDM_0_TR_MUX_PAR, MASKDWORD, 0x000800e4);
1646         odm_set_bb_reg(p_dm_odm, REG_FPGA0_XCD_RF_INTERFACE_SW, MASKDWORD, 0x25204000);
1647
1648         /* path A TX IQK */
1649 #if 1
1650
1651         for (i = 0 ; i < retry_count ; i++) {
1652 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
1653                 path_aok = phy_path_a_iqk_8703b(p_adapter);
1654 #else
1655                 path_aok = phy_path_a_iqk_8703b(p_dm_odm);
1656 #endif
1657
1658                 if (path_aok == 0x01) {
1659                         ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]Tx IQK Success!!\n"));
1660                         result[t][0] = (odm_get_bb_reg(p_dm_odm, REG_TX_POWER_BEFORE_IQK_A, MASKDWORD) & 0x3FF0000) >> 16;
1661                         result[t][1] = (odm_get_bb_reg(p_dm_odm, REG_TX_POWER_AFTER_IQK_A, MASKDWORD) & 0x3FF0000) >> 16;
1662                         break;
1663                 }
1664
1665         }
1666 #endif
1667
1668         /* path A RXIQK */
1669 #if 1
1670
1671         for (i = 0 ; i < retry_count ; i++) {
1672 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
1673                 path_aok = phy_path_a_rx_iqk_8703b(p_adapter);
1674 #else
1675                 path_aok = phy_path_a_rx_iqk_8703b(p_dm_odm);
1676 #endif
1677                 if (path_aok == 0x03) {
1678                         ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]Rx IQK Success!!\n"));
1679                         /*                      result[t][0] = (odm_get_bb_reg(p_dm_odm, REG_TX_POWER_BEFORE_IQK_A, MASKDWORD)&0x3FF0000)>>16;
1680                          *                      result[t][1] = (odm_get_bb_reg(p_dm_odm, REG_TX_POWER_AFTER_IQK_A, MASKDWORD)&0x3FF0000)>>16; */
1681                         result[t][2] = (odm_get_bb_reg(p_dm_odm, REG_RX_POWER_BEFORE_IQK_A_2, MASKDWORD) & 0x3FF0000) >> 16;
1682                         result[t][3] = (odm_get_bb_reg(p_dm_odm, REG_RX_POWER_AFTER_IQK_A_2, MASKDWORD) & 0x3FF0000) >> 16;
1683                         break;
1684                 } else
1685                         ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]Rx IQK Fail!!\n"));
1686         }
1687
1688         if (0x00 == path_aok)
1689                 ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]IQK failed!!\n"));
1690
1691 #endif
1692
1693
1694         /* path B TX IQK */
1695 #if 0
1696
1697 #if MP_DRIVER != 1
1698         if ((*p_dm_odm->p_is_1_antenna == false) || ((*p_dm_odm->p_is_1_antenna == true) && (*p_dm_odm->p_rf_default_path == 1))
1699             || (p_dm_odm->support_interface == ODM_ITRF_USB))
1700 #endif
1701         {
1702
1703                 for (i = 0 ; i < retry_count ; i++) {
1704 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
1705                         path_bok = phy_path_b_iqk_8703b(p_adapter);
1706 #else
1707                         path_bok = phy_path_b_iqk_8703b(p_dm_odm);
1708 #endif
1709                         /*              if(path_bok == 0x03){ */
1710                         if (path_bok == 0x01) {
1711                                 ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]S0 Tx IQK Success!!\n"));
1712                                 result[t][4] = (odm_get_bb_reg(p_dm_odm, REG_TX_POWER_BEFORE_IQK_A, MASKDWORD) & 0x3FF0000) >> 16;
1713                                 result[t][5] = (odm_get_bb_reg(p_dm_odm, REG_TX_POWER_AFTER_IQK_A, MASKDWORD) & 0x3FF0000) >> 16;
1714                                 break;
1715                         }
1716
1717                 }
1718 #endif
1719
1720                 /* path B RX IQK */
1721 #if 0
1722
1723                 for (i = 0 ; i < retry_count ; i++) {
1724 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
1725                         path_bok = phy_path_b_rx_iqk_8703b(p_adapter);
1726 #else
1727                         path_bok = phy_path_b_rx_iqk_8703b(p_dm_odm);
1728 #endif
1729                         if (path_bok == 0x03) {
1730                                 ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]S0 Rx IQK Success!!\n"));
1731                                 /*                              result[t][0] = (odm_get_bb_reg(p_dm_odm, REG_TX_POWER_BEFORE_IQK_A, MASKDWORD)&0x3FF0000)>>16;
1732                                  *                              result[t][1] = (odm_get_bb_reg(p_dm_odm, REG_TX_POWER_AFTER_IQK_A, MASKDWORD)&0x3FF0000)>>16; */
1733                                 result[t][6] = (odm_get_bb_reg(p_dm_odm, REG_RX_POWER_BEFORE_IQK_A_2, MASKDWORD) & 0x3FF0000) >> 16;
1734                                 result[t][7] = (odm_get_bb_reg(p_dm_odm, REG_RX_POWER_AFTER_IQK_A_2, MASKDWORD) & 0x3FF0000) >> 16;
1735                                 break;
1736
1737                         } else
1738                                 ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]S0 Rx IQK Fail!!\n"));
1739
1740                 }
1741
1742
1743
1744                 if (0x00 == path_bok)
1745                         ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]S0 IQK failed!!\n"));
1746
1747         }
1748 #endif
1749
1750         /* Back to BB mode, load original value */
1751         ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]IQK:Back to BB mode, load original value!\n"));
1752         odm_set_bb_reg(p_dm_odm, REG_FPGA0_IQK, 0xffffff00, 0x000000);
1753
1754         if (t != 0) {
1755 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
1756
1757                 /* Reload ADDA power saving parameters*/
1758                 _phy_reload_adda_registers8703b(p_adapter, ADDA_REG, p_dm_odm->rf_calibrate_info.ADDA_backup, IQK_ADDA_REG_NUM);
1759
1760                 /* Reload MAC parameters*/
1761                 _phy_reload_mac_registers8703b(p_adapter, IQK_MAC_REG, p_dm_odm->rf_calibrate_info.IQK_MAC_backup);
1762
1763                 _phy_reload_adda_registers8703b(p_adapter, IQK_BB_REG_92C, p_dm_odm->rf_calibrate_info.IQK_BB_backup, IQK_BB_REG_NUM);
1764 #else
1765                 /* Reload ADDA power saving parameters*/
1766                 _phy_reload_adda_registers8703b(p_dm_odm, ADDA_REG, p_dm_odm->rf_calibrate_info.ADDA_backup, IQK_ADDA_REG_NUM);
1767
1768                 /* Reload MAC parameters*/
1769                 _phy_reload_mac_registers8703b(p_dm_odm, IQK_MAC_REG, p_dm_odm->rf_calibrate_info.IQK_MAC_backup);
1770
1771                 _phy_reload_adda_registers8703b(p_dm_odm, IQK_BB_REG_92C, p_dm_odm->rf_calibrate_info.IQK_BB_backup, IQK_BB_REG_NUM);
1772 #endif
1773
1774                 /* Allen initial gain 0xc50 */
1775                 /* Restore RX initial gain */
1776                 odm_set_bb_reg(p_dm_odm, 0xc50, MASKBYTE0, 0x50);
1777                 odm_set_bb_reg(p_dm_odm, 0xc50, MASKBYTE0, tmp0xc50);
1778
1779                 /* load 0xe30 IQC default value */
1780                 odm_set_bb_reg(p_dm_odm, REG_TX_IQK_TONE_A, MASKDWORD, 0x01008c00);
1781                 odm_set_bb_reg(p_dm_odm, REG_RX_IQK_TONE_A, MASKDWORD, 0x01008c00);
1782
1783         }
1784         ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]_phy_iq_calibrate_8703b() <==\n"));
1785
1786 }
1787
1788
1789 void
1790 _phy_lc_calibrate_8703b(
1791         struct PHY_DM_STRUCT            *p_dm_odm,
1792         boolean         is2T
1793 )
1794 {
1795         u8      tmp_reg;
1796         u32     rf_amode = 0, rf_bmode = 0, lc_cal, cnt;
1797 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
1798         struct _ADAPTER *p_adapter = p_dm_odm->adapter;
1799 #endif
1800
1801         /*Check continuous TX and Packet TX*/
1802         tmp_reg = odm_read_1byte(p_dm_odm, 0xd03);
1803
1804         if ((tmp_reg & 0x70) != 0)                      /*Deal with contisuous TX case*/
1805                 odm_write_1byte(p_dm_odm, 0xd03, tmp_reg & 0x8F);       /*disable all continuous TX*/
1806         else                                                    /* Deal with Packet TX case*/
1807                 odm_write_1byte(p_dm_odm, REG_TXPAUSE, 0xFF);                   /* block all queues*/
1808
1809
1810         /*backup RF0x18*/
1811         lc_cal = odm_get_rf_reg(p_dm_odm, ODM_RF_PATH_A, RF_CHNLBW, RFREGOFFSETMASK);
1812
1813         /*Start LCK*/
1814         odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, RF_CHNLBW, RFREGOFFSETMASK, lc_cal | 0x08000);
1815
1816         for (cnt = 0; cnt < 100; cnt++) {
1817                 if (odm_get_rf_reg(p_dm_odm, ODM_RF_PATH_A, RF_CHNLBW, 0x8000) != 0x1)
1818                         break;
1819
1820                 ODM_delay_ms(10);
1821         }
1822
1823         /*Recover channel number*/
1824         odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, RF_CHNLBW, RFREGOFFSETMASK, lc_cal);
1825
1826
1827         /*Restore original situation*/
1828         if ((tmp_reg & 0x70) != 0) {
1829                 /*Deal with contisuous TX case*/
1830                 odm_write_1byte(p_dm_odm, 0xd03, tmp_reg);
1831         } else {
1832                 /* Deal with Packet TX case*/
1833                 odm_write_1byte(p_dm_odm, REG_TXPAUSE, 0x00);
1834         }
1835
1836 }
1837
1838 /* IQK version:V0.4*/
1839 /* 1. add coex. related setting*/
1840
1841 void
1842 phy_iq_calibrate_8703b(
1843 #if (DM_ODM_SUPPORT_TYPE & ODM_AP)
1844         struct PHY_DM_STRUCT            *p_dm_odm,
1845 #else
1846         struct _ADAPTER *p_adapter,
1847 #endif
1848         boolean is_recovery
1849 )
1850 {
1851 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
1852         HAL_DATA_TYPE   *p_hal_data = GET_HAL_DATA(p_adapter);
1853
1854 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
1855         struct PHY_DM_STRUCT            *p_dm_odm = &p_hal_data->DM_OutSrc;
1856 #else  /* (DM_ODM_SUPPORT_TYPE == ODM_CE)*/
1857         struct PHY_DM_STRUCT            *p_dm_odm = &p_hal_data->odmpriv;
1858 #endif
1859
1860 #if (MP_DRIVER == 1)
1861 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
1862         PMPT_CONTEXT    p_mpt_ctx = &(p_adapter->mpt_ctx);
1863 #else/* (DM_ODM_SUPPORT_TYPE == ODM_CE)*/
1864         PMPT_CONTEXT    p_mpt_ctx = &(p_adapter->mppriv.mpt_ctx);
1865 #endif
1866 #endif/*(MP_DRIVER == 1)*/
1867
1868         u8                      u1b_tmp;
1869         u16                     count = 0;
1870 #endif
1871
1872         struct odm_rf_calibration_structure     *p_rf_calibrate_info = &(p_dm_odm->rf_calibrate_info);
1873
1874         s32                     result[4][8];   /* last is final result */
1875         u8                      i, final_candidate, indexforchannel;
1876         boolean                 is_patha_ok, is_pathb_ok;
1877         s32                     rege94, rege9c, regea4, regeac, regeb4, regebc, regec4, regecc, reg_tmp = 0;
1878         boolean                 is12simular, is13simular, is23simular;
1879         boolean         is_start_cont_tx = false, is_single_tone = false, is_carrier_suppression = false;
1880         u32                     IQK_BB_REG_92C[IQK_BB_REG_NUM] = {
1881                 REG_OFDM_0_XA_RX_IQ_IMBALANCE,          REG_OFDM_0_XB_RX_IQ_IMBALANCE,
1882                 REG_OFDM_0_ECCA_THRESHOLD,              REG_OFDM_0_AGC_RSSI_TABLE,
1883                 REG_OFDM_0_XA_TX_IQ_IMBALANCE,          REG_OFDM_0_XB_TX_IQ_IMBALANCE,
1884                 REG_OFDM_0_XC_TX_AFE,                   REG_OFDM_0_XD_TX_AFE,
1885                 REG_OFDM_0_RX_IQ_EXT_ANTA
1886         };
1887         boolean                 is_reload_iqk = false;
1888
1889 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
1890         if (odm_check_power_status(p_adapter) == false)
1891                 return;
1892 #else
1893         struct rtl8192cd_priv   *priv = p_dm_odm->priv;
1894
1895 #ifdef MP_TEST
1896         if (priv->pshare->rf_ft_var.mp_specific) {
1897                 if ((OPMODE & WIFI_MP_CTX_PACKET) || (OPMODE & WIFI_MP_CTX_ST))
1898                         return;
1899         }
1900 #endif
1901
1902         if (priv->pshare->IQK_88E_done)
1903                 is_recovery = 1;
1904         priv->pshare->IQK_88E_done = 1;
1905 #endif
1906
1907
1908 #if (DM_ODM_SUPPORT_TYPE == ODM_CE)
1909         if (!(p_dm_odm->support_ability & ODM_RF_CALIBRATION))
1910                 return;
1911
1912 #endif
1913
1914
1915         if (p_dm_odm->mp_mode == true) {
1916 #if MP_DRIVER == 1
1917 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
1918                 /* <VincentL, 131231> Add to determine IQK ON/OFF in certain case, Suggested by Cheng.*/
1919                 if (!p_hal_data->iqk_mp_switch)
1920                         return;
1921 #endif
1922
1923                 is_start_cont_tx = p_mpt_ctx->is_start_cont_tx;
1924                 is_single_tone = p_mpt_ctx->is_single_tone;
1925                 is_carrier_suppression = p_mpt_ctx->is_carrier_suppression;
1926
1927                 /* 20120213<Kordan> Turn on when continuous Tx to pass lab testing. (required by Edlu)*/
1928                 if (is_single_tone || is_carrier_suppression)
1929                         return;
1930 #endif
1931         }
1932
1933 #if DISABLE_BB_RF
1934         return;
1935 #endif
1936
1937
1938         if (p_dm_odm->rf_calibrate_info.is_iqk_in_progress)
1939                 return;
1940
1941 #if (DM_ODM_SUPPORT_TYPE & (ODM_CE | ODM_AP))
1942         if (is_recovery)
1943 #else/* for ODM_WIN */
1944         if (is_recovery && (!p_adapter->bInHctTest)) /* YJ,add for PowerTest,120405 */
1945 #endif
1946         {
1947                 ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("[IQK]phy_iq_calibrate_8703b: Return due to is_recovery!\n"));
1948 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
1949                 _phy_reload_adda_registers8703b(p_adapter, IQK_BB_REG_92C, p_dm_odm->rf_calibrate_info.IQK_BB_backup_recover, 9);
1950 #else
1951                 _phy_reload_adda_registers8703b(p_dm_odm, IQK_BB_REG_92C, p_dm_odm->rf_calibrate_info.IQK_BB_backup_recover, 9);
1952 #endif
1953                 return;
1954         }
1955
1956
1957         if (p_dm_odm->mp_mode == false) {
1958 #if MP_DRIVER != 1
1959                 /* check if IQK had been done before!! */
1960
1961                 ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK] 0xc80 = 0x%x\n", p_rf_calibrate_info->tx_iqc_8703b[idx_0xc80][VAL]));
1962                 if (odm_set_iqc_by_rfpath_8703b(p_dm_odm)) {
1963                         ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]IQK value is reloaded!!!\n"));
1964                         is_reload_iqk = true;
1965                 }
1966
1967                 if (is_reload_iqk)
1968                         return;
1969 #endif
1970         }
1971         /*Check & wait if BT is doing IQK*/
1972
1973         if (p_dm_odm->mp_mode == false) {
1974 #if MP_DRIVER != 1
1975                 /* Set H2C cmd to inform FW (enable). */
1976                 SetFwWiFiCalibrationCmd(p_adapter, 1);
1977                 /* Check 0x1e6 */
1978                 count = 0;
1979                 u1b_tmp = odm_read_1byte(p_dm_odm, 0x1e6);
1980                 while (u1b_tmp != 0x1 && count < 1000) {
1981                         odm_stall_execution(10);
1982                         u1b_tmp = odm_read_1byte(p_dm_odm, 0x1e6);
1983                         count++;
1984                 }
1985
1986                 if (count >= 1000)
1987                         RT_TRACE(COMP_INIT, DBG_LOUD, ("[IQK]Polling 0x1e6 to 1 for WiFi calibration H2C cmd FAIL! count(%d)", count));
1988
1989
1990                 /* Wait BT IQK finished. */
1991                 /* polling 0x1e7[0]=1 or 300ms timeout */
1992                 u1b_tmp = odm_read_1byte(p_dm_odm, 0x1e7);
1993                 while ((!(u1b_tmp & BIT(0))) && count < 6000) {
1994                         odm_stall_execution(50);
1995                         u1b_tmp = odm_read_1byte(p_dm_odm, 0x1e7);
1996                         count++;
1997                 }
1998 #endif
1999         }
2000
2001         /* IQK start!!!!!!!!!! */
2002
2003         ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]IQK:Start!!!\n"));
2004         odm_acquire_spin_lock(p_dm_odm, RT_IQK_SPINLOCK);
2005         p_dm_odm->rf_calibrate_info.is_iqk_in_progress = true;
2006         odm_release_spin_lock(p_dm_odm, RT_IQK_SPINLOCK);
2007
2008
2009         for (i = 0; i < 8; i++) {
2010                 result[0][i] = 0;
2011                 result[1][i] = 0;
2012                 result[2][i] = 0;
2013                 result[3][i] = 0;
2014         }
2015         final_candidate = 0xff;
2016         is_patha_ok = false;
2017         is_pathb_ok = false;
2018         is12simular = false;
2019         is23simular = false;
2020         is13simular = false;
2021
2022
2023         for (i = 0; i < 3; i++) {
2024 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
2025                 _phy_iq_calibrate_8703b(p_adapter, result, i);
2026 #else
2027                 _phy_iq_calibrate_8703b(p_dm_odm, result, i);
2028 #endif
2029
2030
2031                 if (i == 1) {
2032 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
2033                         is12simular = phy_simularity_compare_8703b(p_adapter, result, 0, 1);
2034 #else
2035                         is12simular = phy_simularity_compare_8703b(p_dm_odm, result, 0, 1);
2036 #endif
2037                         if (is12simular) {
2038                                 final_candidate = 0;
2039                                 ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]IQK: is12simular final_candidate is %x\n", final_candidate));
2040                                 break;
2041                         }
2042                 }
2043
2044                 if (i == 2) {
2045 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
2046                         is13simular = phy_simularity_compare_8703b(p_adapter, result, 0, 2);
2047 #else
2048                         is13simular = phy_simularity_compare_8703b(p_dm_odm, result, 0, 2);
2049 #endif
2050                         if (is13simular) {
2051                                 final_candidate = 0;
2052                                 ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]IQK: is13simular final_candidate is %x\n", final_candidate));
2053
2054                                 break;
2055                         }
2056 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
2057                         is23simular = phy_simularity_compare_8703b(p_adapter, result, 1, 2);
2058 #else
2059                         is23simular = phy_simularity_compare_8703b(p_dm_odm, result, 1, 2);
2060 #endif
2061                         if (is23simular) {
2062                                 final_candidate = 1;
2063                                 ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]IQK: is23simular final_candidate is %x\n", final_candidate));
2064                         } else {
2065                                 for (i = 0; i < 8; i++)
2066                                         reg_tmp += result[3][i];
2067
2068                                 if (reg_tmp != 0)
2069                                         final_candidate = 3;
2070                                 else
2071                                         final_candidate = 0xFF;
2072                         }
2073                 }
2074         }
2075         /*      RT_TRACE(COMP_INIT,DBG_LOUD,("Release Mutex in IQCalibrate\n"));*/
2076
2077         for (i = 0; i < 4; i++) {
2078                 rege94 = result[i][0];
2079                 rege9c = result[i][1];
2080                 regea4 = result[i][2];
2081                 regeac = result[i][3];
2082                 regeb4 = result[i][4];
2083                 regebc = result[i][5];
2084                 regec4 = result[i][6];
2085                 regecc = result[i][7];
2086                 ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]IQK: rege94=%x rege9c=%x regea4=%x regeac=%x regeb4=%x regebc=%x regec4=%x regecc=%x\n ", rege94, rege9c, regea4, regeac, regeb4, regebc, regec4, regecc));
2087         }
2088
2089         if (final_candidate != 0xff) {
2090                 p_dm_odm->rf_calibrate_info.rege94 = rege94 = result[final_candidate][0];
2091                 p_dm_odm->rf_calibrate_info.rege9c = rege9c = result[final_candidate][1];
2092                 regea4 = result[final_candidate][2];
2093                 regeac = result[final_candidate][3];
2094                 p_dm_odm->rf_calibrate_info.regeb4 = regeb4 = result[final_candidate][4];
2095                 p_dm_odm->rf_calibrate_info.regebc = regebc = result[final_candidate][5];
2096                 regec4 = result[final_candidate][6];
2097                 regecc = result[final_candidate][7];
2098                 ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]IQK: final_candidate is %x\n", final_candidate));
2099                 ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]IQK: rege94=%x rege9c=%x regea4=%x regeac=%x regeb4=%x regebc=%x regec4=%x regecc=%x\n ", rege94, rege9c, regea4, regeac, regeb4, regebc, regec4, regecc));
2100                 is_patha_ok = is_pathb_ok = true;
2101         } else {
2102                 ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]IQK: FAIL use default value\n"));
2103                 p_dm_odm->rf_calibrate_info.rege94 = p_dm_odm->rf_calibrate_info.regeb4 = 0x100;        /* X default value */
2104                 p_dm_odm->rf_calibrate_info.rege9c = p_dm_odm->rf_calibrate_info.regebc = 0x0;          /* Y default value */
2105         }
2106
2107         /* fill IQK matrix */
2108         if (rege94 != 0)
2109                 _phy_path_a_fill_iqk_matrix8703b(p_adapter, is_patha_ok, result, final_candidate, (regea4 == 0));
2110         /*      if (regeb4 != 0)
2111          *              _phy_path_b_fill_iqk_matrix8703b(p_adapter, is_pathb_ok, result, final_candidate, (regec4 == 0)); */
2112
2113 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
2114         indexforchannel = odm_get_right_chnl_place_for_iqk(*p_dm_odm->p_channel);
2115 #else
2116         indexforchannel = 0;
2117 #endif
2118
2119         /* To Fix BSOD when final_candidate is 0xff
2120          * by sherry 20120321 */
2121         if (final_candidate < 4) {
2122                 for (i = 0; i < iqk_matrix_reg_num; i++)
2123                         p_dm_odm->rf_calibrate_info.iqk_matrix_reg_setting[indexforchannel].value[0][i] = result[final_candidate][i];
2124                 p_dm_odm->rf_calibrate_info.iqk_matrix_reg_setting[indexforchannel].is_iqk_done = true;
2125         }
2126         /* RT_DISP(FINIT, INIT_IQK, ("\nIQK OK indexforchannel %d.\n", indexforchannel)); */
2127         ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]\nIQK OK indexforchannel %d.\n", indexforchannel));
2128
2129
2130 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
2131         _phy_save_adda_registers8703b(p_adapter, IQK_BB_REG_92C, p_dm_odm->rf_calibrate_info.IQK_BB_backup_recover, 9);
2132 #else
2133         _phy_save_adda_registers8703b(p_dm_odm, IQK_BB_REG_92C, p_dm_odm->rf_calibrate_info.IQK_BB_backup_recover, IQK_BB_REG_NUM);
2134 #endif
2135
2136         /* fill IQK register */
2137         odm_set_iqc_by_rfpath_8703b(p_dm_odm);
2138
2139         if (p_dm_odm->mp_mode == false) {
2140 #if MP_DRIVER != 1
2141                 /* Set H2C cmd to inform FW (disable). */
2142                 SetFwWiFiCalibrationCmd(p_adapter, 0);
2143
2144                 /* Check 0x1e6 */
2145                 count = 0;
2146                 u1b_tmp = odm_read_1byte(p_dm_odm, 0x1e6);
2147                 while (u1b_tmp != 0 && count < 1000) {
2148                         odm_stall_execution(10);
2149                         u1b_tmp = odm_read_1byte(p_dm_odm, 0x1e6);
2150                         count++;
2151                 }
2152
2153                 if (count >= 1000)
2154                         RT_TRACE(COMP_INIT, DBG_LOUD, ("[IQK]Polling 0x1e6 to 0 for WiFi calibration H2C cmd FAIL! count(%d)", count));
2155
2156 #endif
2157         }
2158
2159         odm_acquire_spin_lock(p_dm_odm, RT_IQK_SPINLOCK);
2160         p_dm_odm->rf_calibrate_info.is_iqk_in_progress = false;
2161         odm_release_spin_lock(p_dm_odm, RT_IQK_SPINLOCK);
2162
2163         ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]IQK finished\n"));
2164 }
2165
2166
2167 void
2168 phy_lc_calibrate_8703b(
2169         void            *p_dm_void
2170 )
2171 {
2172         boolean         is_start_cont_tx = false, is_single_tone = false, is_carrier_suppression = false;
2173         u32                     timeout = 2000, timecount = 0;
2174         struct PHY_DM_STRUCT    *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
2175 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
2176         struct _ADAPTER *p_adapter = p_dm_odm->adapter;
2177         HAL_DATA_TYPE   *p_hal_data = GET_HAL_DATA(p_adapter);
2178
2179 #if (MP_DRIVER == 1)
2180 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
2181         PMPT_CONTEXT    p_mpt_ctx = &(p_adapter->mpt_ctx);
2182 #else/* (DM_ODM_SUPPORT_TYPE == ODM_CE)*/
2183         PMPT_CONTEXT    p_mpt_ctx = &(p_adapter->mppriv.mpt_ctx);
2184 #endif
2185 #endif/*(MP_DRIVER == 1)*/
2186 #endif
2187
2188
2189
2190
2191 #if MP_DRIVER == 1
2192 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
2193         /* <VincentL, 140319> Add to Disable Default LCK when Cont Tx, For Lab Test Usage. */
2194         if (!p_hal_data->iqk_mp_switch)
2195                 return;
2196 #endif
2197
2198         is_start_cont_tx = p_mpt_ctx->is_start_cont_tx;
2199         is_single_tone = p_mpt_ctx->is_single_tone;
2200         is_carrier_suppression = p_mpt_ctx->is_carrier_suppression;
2201 #endif
2202
2203
2204 #if DISABLE_BB_RF
2205         return;
2206 #endif
2207
2208 #if (DM_ODM_SUPPORT_TYPE == ODM_CE)
2209         if (!(p_dm_odm->support_ability & ODM_RF_CALIBRATION))
2210                 return;
2211
2212 #endif
2213         /* 20120213<Kordan> Turn on when continuous Tx to pass lab testing. (required by Edlu) */
2214         if (is_single_tone || is_carrier_suppression)
2215                 return;
2216
2217         while (*(p_dm_odm->p_is_scan_in_process) && timecount < timeout) {
2218                 ODM_delay_ms(50);
2219                 timecount += 50;
2220         }
2221
2222         p_dm_odm->rf_calibrate_info.is_lck_in_progress = true;
2223
2224
2225         _phy_lc_calibrate_8703b(p_dm_odm, false);
2226
2227
2228         p_dm_odm->rf_calibrate_info.is_lck_in_progress = false;
2229
2230         ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("LCK:Finish!!!interface %d\n", p_dm_odm->interface_index));
2231
2232 }
2233
2234 void _phy_set_rf_path_switch_8703b(
2235 #if (DM_ODM_SUPPORT_TYPE & ODM_AP)
2236         struct PHY_DM_STRUCT            *p_dm_odm,
2237 #else
2238         struct _ADAPTER *p_adapter,
2239 #endif
2240         boolean         is_main,
2241         boolean         is2T
2242 )
2243 {
2244         HAL_DATA_TYPE   *p_hal_data = GET_HAL_DATA(p_adapter);
2245 #if (DM_ODM_SUPPORT_TYPE == ODM_CE)
2246         struct PHY_DM_STRUCT            *p_dm_odm = &p_hal_data->odmpriv;
2247 #endif
2248 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
2249         struct PHY_DM_STRUCT            *p_dm_odm = &p_hal_data->DM_OutSrc;
2250 #endif
2251
2252         if (is_main) {  /*Set WIFI S1*/
2253                 odm_set_bb_reg(p_dm_odm, 0x7C4, MASKLWORD, 0x7703);
2254                 odm_set_bb_reg(p_dm_odm, 0x7C0, MASKDWORD, 0xC00F0038);
2255         } else {                /*Set BT S0*/
2256                 odm_set_bb_reg(p_dm_odm, 0x7C4, MASKLWORD, 0xCC03);
2257                 odm_set_bb_reg(p_dm_odm, 0x7C0, MASKDWORD, 0xC00F0038);
2258         }
2259 }
2260
2261 void phy_set_rf_path_switch_8703b(
2262 #if (DM_ODM_SUPPORT_TYPE & ODM_AP)
2263         struct PHY_DM_STRUCT            *p_dm_odm,
2264 #else
2265         struct _ADAPTER *p_adapter,
2266 #endif
2267         boolean         is_main
2268 )
2269 {
2270
2271         HAL_DATA_TYPE   *p_hal_data = GET_HAL_DATA(p_adapter);
2272 #if (DM_ODM_SUPPORT_TYPE == ODM_CE)
2273         struct PHY_DM_STRUCT            *p_dm_odm = &p_hal_data->odmpriv;
2274 #endif
2275 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
2276         struct PHY_DM_STRUCT            *p_dm_odm = &p_hal_data->DM_OutSrc;
2277 #endif
2278
2279 #if DISABLE_BB_RF
2280         return;
2281 #endif
2282
2283 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
2284         _phy_set_rf_path_switch_8703b(p_adapter, is_main, true);
2285 #endif
2286
2287 }
2288
2289
2290 /*return value true => WIFI(S1); false => BT(S0)*/
2291 boolean _phy_query_rf_path_switch_8703b(
2292 #if (DM_ODM_SUPPORT_TYPE & ODM_AP)
2293         struct PHY_DM_STRUCT            *p_dm_odm,
2294 #else
2295         struct _ADAPTER *p_adapter,
2296 #endif
2297         boolean         is2T
2298 )
2299 {
2300 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
2301         HAL_DATA_TYPE   *p_hal_data = GET_HAL_DATA(p_adapter);
2302 #if (DM_ODM_SUPPORT_TYPE == ODM_CE)
2303         struct PHY_DM_STRUCT            *p_dm_odm = &p_hal_data->odmpriv;
2304 #endif
2305 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
2306         struct PHY_DM_STRUCT            *p_dm_odm = &p_hal_data->DM_OutSrc;
2307 #endif
2308 #endif
2309
2310
2311         if (odm_get_bb_reg(p_dm_odm, 0x7C4, MASKLWORD) == 0x7703)
2312                 return true;
2313         else
2314                 return false;
2315
2316 }
2317
2318
2319
2320 /*return value true => WIFI(S1); false => BT(S0)*/
2321 boolean phy_query_rf_path_switch_8703b(
2322 #if (DM_ODM_SUPPORT_TYPE & ODM_AP)
2323         struct PHY_DM_STRUCT            *p_dm_odm
2324 #else
2325         struct _ADAPTER *p_adapter
2326 #endif
2327 )
2328 {
2329
2330 #if DISABLE_BB_RF
2331         return true;
2332 #endif
2333
2334 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
2335         return _phy_query_rf_path_switch_8703b(p_adapter, false);
2336 #else
2337         return _phy_query_rf_path_switch_8703b(p_dm_odm, false);
2338 #endif
2339
2340 }