drivers/net/wireless/rockchip_wlan/rtl8723cs/hal/phydm/txbf/haltxbf8192e.c

   1 /* ************************************************************
   2  * Description:
   3  *
   4  * This file is for 8192E TXBF mechanism
   5  *
   6  * ************************************************************ */
   7 #include "mp_precomp.h"
   8 #include "../phydm_precomp.h"
   9
  10 #if (BEAMFORMING_SUPPORT == 1)
  11 #if (RTL8192E_SUPPORT == 1)
  12
  13 void
  14 hal_txbf_8192e_set_ndpa_rate(
  15         void                    *p_dm_void,
  16         u8      BW,
  17         u8      rate
  18 )
  19 {
  20         struct PHY_DM_STRUCT    *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
  21
  22         odm_write_1byte(p_dm_odm, REG_NDPA_OPT_CTRL_8192E, (rate << 2 | BW));
  23
  24 }
  25
  26 void
  27 hal_txbf_8192e_rf_mode(
  28         void                    *p_dm_void,
  29         struct _RT_BEAMFORMING_INFO     *p_beam_info
  30 )
  31 {
  32         struct PHY_DM_STRUCT    *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
  33         boolean                         is_self_beamformer = false;
  34         boolean                         is_self_beamformee = false;
  35         enum beamforming_cap    beamform_cap = BEAMFORMING_CAP_NONE;
  36
  37         ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Start!\n", __func__));
  38
  39         if (p_dm_odm->rf_type == ODM_1T1R)
  40                 return;
  41
  42         odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, RF_WE_LUT, 0x80000, 0x1); /*RF mode table write enable*/
  43         odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_B, RF_WE_LUT, 0x80000, 0x1); /*RF mode table write enable*/
  44
  45         if (p_beam_info->beamformee_su_cnt > 0) {
  46                 /*Path_A*/
  47                 odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0x30, 0xfffff, 0x18000);        /*Select RX mode  0x30=0x18000*/
  48                 odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0x31, 0xfffff, 0x0000f);        /*Set Table data*/
  49                 odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0x32, 0xfffff, 0x77fc2);        /*Enable TXIQGEN in RX mode*/
  50                 /*Path_B*/
  51                 odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_B, 0x30, 0xfffff, 0x18000);        /*Select RX mode*/
  52                 odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_B, 0x31, 0xfffff, 0x0000f);        /*Set Table data*/
  53                 odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_B, 0x32, 0xfffff, 0x77fc2);        /*Enable TXIQGEN in RX mode*/
  54         } else {
  55                 /*Path_A*/
  56                 odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0x30, 0xfffff, 0x18000);        /*Select RX mode*/
  57                 odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0x31, 0xfffff, 0x0000f);        /*Set Table data*/
  58                 odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0x32, 0xfffff, 0x77f82);        /*Disable TXIQGEN in RX mode*/
  59                 /*Path_B*/
  60                 odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_B, 0x30, 0xfffff, 0x18000);        /*Select RX mode*/
  61                 odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_B, 0x31, 0xfffff, 0x0000f);        /*Set Table data*/
  62                 odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_B, 0x32, 0xfffff, 0x77f82);        /*Disable TXIQGEN in RX mode*/
  63         }
  64
  65         odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, RF_WE_LUT, 0x80000, 0x0);       /*RF mode table write disable*/
  66         odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_B, RF_WE_LUT, 0x80000, 0x0);       /*RF mode table write disable*/
  67
  68         if (p_beam_info->beamformee_su_cnt > 0) {
  69                 odm_set_bb_reg(p_dm_odm, 0x90c, MASKDWORD, 0x83321333);
  70                 odm_set_bb_reg(p_dm_odm, 0xa04, MASKBYTE3, 0xc1);
  71         } else
  72                 odm_set_bb_reg(p_dm_odm, 0x90c, MASKDWORD, 0x81121313);
  73 }
  74
  75
  76
  77 void
  78 hal_txbf_8192e_fw_txbf_cmd(
  79         void                    *p_dm_void
  80 )
  81 {
  82         struct PHY_DM_STRUCT    *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
  83         u8      idx, period0 = 0, period1 = 0;
  84         u8      PageNum0 = 0xFF, PageNum1 = 0xFF;
  85         u8      u1_tx_bf_parm[3] = {0};
  86         struct _RT_BEAMFORMING_INFO     *p_beam_info = &p_dm_odm->beamforming_info;
  87
  88         for (idx = 0; idx < BEAMFORMEE_ENTRY_NUM; idx++) {
  89                 if (p_beam_info->beamformee_entry[idx].beamform_entry_state == BEAMFORMING_ENTRY_STATE_PROGRESSED) {
  90                         if (idx == 0) {
  91                                 if (p_beam_info->beamformee_entry[idx].is_sound)
  92                                         PageNum0 = 0xFE;
  93                                 else
  94                                         PageNum0 = 0xFF; /* stop sounding */
  95                                 period0 = (u8)(p_beam_info->beamformee_entry[idx].sound_period);
  96                         } else if (idx == 1) {
  97                                 if (p_beam_info->beamformee_entry[idx].is_sound)
  98                                         PageNum1 = 0xFE;
  99                                 else
 100                                         PageNum1 = 0xFF; /* stop sounding */
 101                                 period1 = (u8)(p_beam_info->beamformee_entry[idx].sound_period);
 102                         }
 103                 }
 104         }
 105
 106         u1_tx_bf_parm[0] = PageNum0;
 107         u1_tx_bf_parm[1] = PageNum1;
 108         u1_tx_bf_parm[2] = (period1 << 4) | period0;
 109         odm_fill_h2c_cmd(p_dm_odm, PHYDM_H2C_TXBF, 3, u1_tx_bf_parm);
 110
 111         ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD,
 112                 ("[%s] PageNum0 = %d period0 = %d, PageNum1 = %d period1 %d\n", __func__, PageNum0, period0, PageNum1, period1));
 113 }
 114
 115
 116 void
 117 hal_txbf_8192e_download_ndpa(
 118         void                    *p_dm_void,
 119         u8                              idx
 120 )
 121 {
 122         struct PHY_DM_STRUCT    *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
 123         u8                      u1b_tmp = 0, tmp_reg422 = 0, head_page;
 124         u8                      bcn_valid_reg = 0, count = 0, dl_bcn_count = 0;
 125         boolean                 is_send_beacon = false;
 126         struct _ADAPTER         *adapter = p_dm_odm->adapter;
 127         u8                      tx_page_bndy = LAST_ENTRY_OF_TX_PKT_BUFFER_8812;
 128         /*default reseved 1 page for the IC type which is undefined.*/
 129         struct _RT_BEAMFORMING_INFO     *p_beam_info = &p_dm_odm->beamforming_info;
 130         struct _RT_BEAMFORMEE_ENTRY     *p_beam_entry = p_beam_info->beamformee_entry + idx;
 131
 132         ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Start!\n", __func__));
 133 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
 134         *p_dm_odm->p_is_fw_dw_rsvd_page_in_progress = true;
 135 #endif
 136         if (idx == 0)
 137                 head_page = 0xFE;
 138         else
 139                 head_page = 0xFE;
 140
 141         phydm_get_hal_def_var_handler_interface(p_dm_odm, HAL_DEF_TX_PAGE_BOUNDARY, (u8 *)&tx_page_bndy);
 142
 143         /*Set REG_CR bit 8. DMA beacon by SW.*/
 144         u1b_tmp = odm_read_1byte(p_dm_odm, REG_CR_8192E+1);
 145         odm_write_1byte(p_dm_odm,  REG_CR_8192E+1, (u1b_tmp | BIT(0)));
 146
 147         /*Set FWHW_TXQ_CTRL 0x422[6]=0 to tell Hw the packet is not a real beacon frame.*/
 148         tmp_reg422 = odm_read_1byte(p_dm_odm, REG_FWHW_TXQ_CTRL_8192E+2);
 149         odm_write_1byte(p_dm_odm, REG_FWHW_TXQ_CTRL_8192E+2,  tmp_reg422 & (~BIT(6)));
 150
 151         if (tmp_reg422 & BIT(6)) {
 152                 ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_WARNING, ("%s There is an adapter is sending beacon.\n", __func__));
 153                 is_send_beacon = true;
 154         }
 155
 156         /*TDECTRL[15:8] 0x209[7:0] = 0xFE/0xFD  NDPA Head for TXDMA*/
 157         odm_write_1byte(p_dm_odm, REG_DWBCN0_CTRL_8192E+1, head_page);
 158
 159         do {
 160                 /*Clear beacon valid check bit.*/
 161                 bcn_valid_reg = odm_read_1byte(p_dm_odm, REG_DWBCN0_CTRL_8192E+2);
 162                 odm_write_1byte(p_dm_odm, REG_DWBCN0_CTRL_8192E+2, (bcn_valid_reg | BIT(0)));
 163
 164                 /* download NDPA rsvd page. */
 165                 beamforming_send_ht_ndpa_packet(p_dm_odm, p_beam_entry->mac_addr, p_beam_entry->sound_bw, BEACON_QUEUE);
 166
 167 #if (DEV_BUS_TYPE == RT_PCI_INTERFACE)
 168                 u1b_tmp = odm_read_1byte(p_dm_odm, REG_MGQ_TXBD_NUM_8192E+3);
 169                 count = 0;
 170                 while ((count < 20) && (u1b_tmp & BIT(4))) {
 171                         count++;
 172                         ODM_delay_us(10);
 173                         u1b_tmp = odm_read_1byte(p_dm_odm, REG_MGQ_TXBD_NUM_8192E+3);
 174                 }
 175                 odm_write_1byte(p_dm_odm, REG_MGQ_TXBD_NUM_8192E+3, u1b_tmp | BIT(4));
 176 #endif
 177
 178                 /*check rsvd page download OK.*/
 179                 bcn_valid_reg = odm_read_1byte(p_dm_odm, REG_DWBCN0_CTRL_8192E+2);
 180                 count = 0;
 181                 while (!(bcn_valid_reg & BIT(0)) && count < 20) {
 182                         count++;
 183                         ODM_delay_us(10);
 184                         bcn_valid_reg = odm_read_1byte(p_dm_odm, REG_DWBCN0_CTRL_8192E+2);
 185                 }
 186                 dl_bcn_count++;
 187         } while (!(bcn_valid_reg & BIT(0)) && dl_bcn_count < 5);
 188
 189         if (!(bcn_valid_reg & BIT(0)))
 190                 ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_WARNING, ("%s Download RSVD page failed!\n", __func__));
 191
 192         /*TDECTRL[15:8] 0x209[7:0] = 0xF9       Beacon Head for TXDMA*/
 193         odm_write_1byte(p_dm_odm, REG_DWBCN0_CTRL_8192E+1, tx_page_bndy);
 194
 195         /*To make sure that if there exists an adapter which would like to send beacon.*/
 196         /*If exists, the origianl value of 0x422[6] will be 1, we should check this to*/
 197         /*prevent from setting 0x422[6] to 0 after download reserved page, or it will cause*/
 198         /*the beacon cannot be sent by HW.*/
 199         /*2010.06.23. Added by tynli.*/
 200         if (is_send_beacon)
 201                 odm_write_1byte(p_dm_odm, REG_FWHW_TXQ_CTRL_8192E+2, tmp_reg422);
 202
 203         /*Do not enable HW DMA BCN or it will cause Pcie interface hang by timing issue. 2011.11.24. by tynli.*/
 204         /*Clear CR[8] or beacon packet will not be send to TxBuf anymore.*/
 205         u1b_tmp = odm_read_1byte(p_dm_odm, REG_CR_8192E+1);
 206         odm_write_1byte(p_dm_odm, REG_CR_8192E+1, (u1b_tmp & (~BIT(0))));
 207
 208         p_beam_entry->beamform_entry_state = BEAMFORMING_ENTRY_STATE_PROGRESSED;
 209 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
 210         *p_dm_odm->p_is_fw_dw_rsvd_page_in_progress = false;
 211 #endif
 212 }
 213
 214
 215 void
 216 hal_txbf_8192e_enter(
 217         void                    *p_dm_void,
 218         u8                              bfer_bfee_idx
 219 )
 220 {
 221         struct PHY_DM_STRUCT    *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
 222         u8                                      i = 0;
 223         u8                                      bfer_idx = (bfer_bfee_idx & 0xF0) >> 4;
 224         u8                                      bfee_idx = (bfer_bfee_idx & 0xF);
 225         u32                                     csi_param;
 226         struct _RT_BEAMFORMING_INFO     *p_beamforming_info = &p_dm_odm->beamforming_info;
 227         struct _RT_BEAMFORMEE_ENTRY     beamformee_entry;
 228         struct _RT_BEAMFORMER_ENTRY     beamformer_entry;
 229         u16                                     sta_id = 0;
 230
 231         ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Start!\n", __func__));
 232
 233         hal_txbf_8192e_rf_mode(p_dm_odm, p_beamforming_info);
 234
 235         if (p_dm_odm->rf_type == ODM_2T2R)
 236                 odm_write_4byte(p_dm_odm, 0xd80, 0x00000000);           /*nc =2*/
 237
 238         if ((p_beamforming_info->beamformer_su_cnt > 0) && (bfer_idx < BEAMFORMER_ENTRY_NUM)) {
 239                 beamformer_entry = p_beamforming_info->beamformer_entry[bfer_idx];
 240
 241                 /*Sounding protocol control*/
 242                 odm_write_1byte(p_dm_odm, REG_SND_PTCL_CTRL_8192E, 0xCB);
 243
 244                 /*MAC address/Partial AID of Beamformer*/
 245                 if (bfer_idx == 0) {
 246                         for (i = 0; i < 6 ; i++)
 247                                 odm_write_1byte(p_dm_odm, (REG_ASSOCIATED_BFMER0_INFO_8192E+i), beamformer_entry.mac_addr[i]);
 248                 } else {
 249                         for (i = 0; i < 6 ; i++)
 250                                 odm_write_1byte(p_dm_odm, (REG_ASSOCIATED_BFMER1_INFO_8192E+i), beamformer_entry.mac_addr[i]);
 251                 }
 252
 253                 /*CSI report parameters of Beamformer Default use nc = 2*/
 254                 csi_param = 0x03090309;
 255
 256                 odm_write_4byte(p_dm_odm, REG_CSI_RPT_PARAM_BW20_8192E, csi_param);
 257                 odm_write_4byte(p_dm_odm, REG_CSI_RPT_PARAM_BW40_8192E, csi_param);
 258                 odm_write_4byte(p_dm_odm, REG_CSI_RPT_PARAM_BW80_8192E, csi_param);
 259
 260                 /*Timeout value for MAC to leave NDP_RX_standby_state (60 us, Test chip) (80 us,  MP chip)*/
 261                 odm_write_1byte(p_dm_odm, REG_SND_PTCL_CTRL_8192E+3, 0x50);
 262
 263         }
 264
 265         if ((p_beamforming_info->beamformee_su_cnt > 0) && (bfee_idx < BEAMFORMEE_ENTRY_NUM)) {
 266                 beamformee_entry = p_beamforming_info->beamformee_entry[bfee_idx];
 267
 268                 if (phydm_acting_determine(p_dm_odm, phydm_acting_as_ibss))
 269                         sta_id = beamformee_entry.mac_id;
 270                 else
 271                         sta_id = beamformee_entry.p_aid;
 272
 273                 ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s], sta_id=0x%X\n", __func__, sta_id));
 274
 275                 /*P_AID of Beamformee & enable NDPA transmission & enable NDPA interrupt*/
 276                 if (bfee_idx == 0) {
 277                         odm_write_2byte(p_dm_odm, REG_TXBF_CTRL_8192E, sta_id);
 278                         odm_write_1byte(p_dm_odm, REG_TXBF_CTRL_8192E+3, odm_read_1byte(p_dm_odm, REG_TXBF_CTRL_8192E+3) | BIT(4) | BIT(6) | BIT(7));
 279                 } else
 280                         odm_write_2byte(p_dm_odm, REG_TXBF_CTRL_8192E+2, sta_id | BIT(12) | BIT(14) | BIT(15));
 281
 282                 /*CSI report parameters of Beamformee*/
 283                 if (bfee_idx == 0) {
 284                         /*Get BIT24 & BIT25*/
 285                         u8 tmp = odm_read_1byte(p_dm_odm, REG_ASSOCIATED_BFMEE_SEL_8192E+3) & 0x3;
 286
 287                         odm_write_1byte(p_dm_odm, REG_ASSOCIATED_BFMEE_SEL_8192E+3, tmp | 0x60);
 288                         odm_write_2byte(p_dm_odm, REG_ASSOCIATED_BFMEE_SEL_8192E, sta_id | BIT(9));
 289                 } else {
 290                         /*Set BIT25*/
 291                         odm_write_2byte(p_dm_odm, REG_ASSOCIATED_BFMEE_SEL_8192E+2, sta_id | 0xE200);
 292                 }
 293                 phydm_beamforming_notify(p_dm_odm);
 294
 295         }
 296 }
 297
 298
 299 void
 300 hal_txbf_8192e_leave(
 301         void                    *p_dm_void,
 302         u8                              idx
 303 )
 304 {
 305         struct PHY_DM_STRUCT    *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
 306         struct _RT_BEAMFORMING_INFO     *p_beam_info = &p_dm_odm->beamforming_info;
 307
 308         hal_txbf_8192e_rf_mode(p_dm_odm, p_beam_info);
 309
 310         /*      Clear P_AID of Beamformee
 311         *       Clear MAC addresss of Beamformer
 312         *       Clear Associated Bfmee Sel
 313         */
 314         if (p_beam_info->beamform_cap == BEAMFORMING_CAP_NONE)
 315                 odm_write_1byte(p_dm_odm, REG_SND_PTCL_CTRL_8192E, 0xC8);
 316
 317         if (idx == 0) {
 318                 odm_write_2byte(p_dm_odm, REG_TXBF_CTRL_8192E, 0);
 319                 odm_write_4byte(p_dm_odm, REG_ASSOCIATED_BFMER0_INFO_8192E, 0);
 320                 odm_write_2byte(p_dm_odm, REG_ASSOCIATED_BFMER0_INFO_8192E+4, 0);
 321                 odm_write_2byte(p_dm_odm, REG_ASSOCIATED_BFMEE_SEL_8192E, 0);
 322         } else {
 323                 odm_write_2byte(p_dm_odm, REG_TXBF_CTRL_8192E+2, odm_read_1byte(p_dm_odm, REG_TXBF_CTRL_8192E+2) & 0xF000);
 324                 odm_write_4byte(p_dm_odm, REG_ASSOCIATED_BFMER1_INFO_8192E, 0);
 325                 odm_write_2byte(p_dm_odm, REG_ASSOCIATED_BFMER1_INFO_8192E+4, 0);
 326                 odm_write_2byte(p_dm_odm, REG_ASSOCIATED_BFMEE_SEL_8192E+2, odm_read_2byte(p_dm_odm, REG_ASSOCIATED_BFMEE_SEL_8192E+2) & 0x60);
 327         }
 328
 329         ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] idx %d\n", __func__, idx));
 330 }
 331
 332
 333 void
 334 hal_txbf_8192e_status(
 335         void                    *p_dm_void,
 336         u8                              idx
 337 )
 338 {
 339         struct PHY_DM_STRUCT    *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
 340         u16                                     beam_ctrl_val;
 341         u32                                     beam_ctrl_reg;
 342         struct _RT_BEAMFORMING_INFO     *p_beam_info =  &p_dm_odm->beamforming_info;
 343         struct _RT_BEAMFORMEE_ENTRY     beamform_entry = p_beam_info->beamformee_entry[idx];
 344
 345         if (phydm_acting_determine(p_dm_odm, phydm_acting_as_ibss))
 346                 beam_ctrl_val = beamform_entry.mac_id;
 347         else
 348                 beam_ctrl_val = beamform_entry.p_aid;
 349
 350         if (idx == 0)
 351                 beam_ctrl_reg = REG_TXBF_CTRL_8192E;
 352         else {
 353                 beam_ctrl_reg = REG_TXBF_CTRL_8192E+2;
 354                 beam_ctrl_val |= BIT(12) | BIT(14) | BIT(15);
 355         }
 356
 357         if ((beamform_entry.beamform_entry_state == BEAMFORMING_ENTRY_STATE_PROGRESSED) && (p_beam_info->apply_v_matrix == true)) {
 358                 if (beamform_entry.sound_bw == CHANNEL_WIDTH_20)
 359                         beam_ctrl_val |= BIT(9);
 360                 else if (beamform_entry.sound_bw == CHANNEL_WIDTH_40)
 361                         beam_ctrl_val |= BIT(10);
 362         } else
 363                 beam_ctrl_val &= ~(BIT(9) | BIT(10) | BIT(11));
 364
 365         odm_write_2byte(p_dm_odm, beam_ctrl_reg, beam_ctrl_val);
 366
 367         ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] idx %d beam_ctrl_reg %x beam_ctrl_val %x\n", __func__, idx, beam_ctrl_reg, beam_ctrl_val));
 368 }
 369
 370
 371 void
 372 hal_txbf_8192e_fw_tx_bf(
 373         void                    *p_dm_void,
 374         u8                              idx
 375 )
 376 {
 377         struct PHY_DM_STRUCT    *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
 378         struct _RT_BEAMFORMING_INFO     *p_beam_info = &p_dm_odm->beamforming_info;
 379         struct _RT_BEAMFORMEE_ENTRY     *p_beam_entry = p_beam_info->beamformee_entry + idx;
 380
 381         ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Start!\n", __func__));
 382
 383         if (p_beam_entry->beamform_entry_state == BEAMFORMING_ENTRY_STATE_PROGRESSING)
 384                 hal_txbf_8192e_download_ndpa(p_dm_odm, idx);
 385
 386         hal_txbf_8192e_fw_txbf_cmd(p_dm_odm);
 387 }
 388
 389 #endif  /* #if (RTL8192E_SUPPORT == 1)*/
 390
 391 #endif