drivers/net/wireless/rockchip_wlan/rtl8723cs/hal/rtl8703b/rtl8703b_phycfg.c

   1 /******************************************************************************
   2  *
   3  * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of version 2 of the GNU General Public License as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program; if not, write to the Free Software Foundation, Inc.,
  16  * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  17  *
  18  *
  19  ******************************************************************************/
  20 #define _RTL8703B_PHYCFG_C_
  21
  22 #include <rtl8703b_hal.h>
  23
  24
  25 /*---------------------------Define Local Constant---------------------------*/
  26 /* Channel switch:The size of command tables for switch channel*/
  27 #define MAX_PRECMD_CNT 16
  28 #define MAX_RFDEPENDCMD_CNT 16
  29 #define MAX_POSTCMD_CNT 16
  30
  31 #define MAX_DOZE_WAITING_TIMES_9x 64
  32
  33 /*---------------------------Define Local Constant---------------------------*/
  34
  35
  36 /*------------------------Define global variable-----------------------------*/
  37
  38 /*------------------------Define local variable------------------------------*/
  39
  40
  41 /*--------------------Define export function prototype-----------------------*/
  42 /* Please refer to header file
  43  *--------------------Define export function prototype-----------------------*/
  44
  45 /*----------------------------Function Body----------------------------------*/
  46 /*
  47  * 1. BB register R/W API
  48  *   */
  49
  50 /**
  51 * Function:     phy_CalculateBitShift
  52 *
  53 * OverView:     Get shifted position of the BitMask
  54 *
  55 * Input:
  56 *                       u4Byte          BitMask,
  57 *
  58 * Output:       none
  59 * Return:               u4Byte          Return the shift bit bit position of the mask
  60 */
  61 static  u32
  62 phy_CalculateBitShift(
  63         u32 BitMask
  64 )
  65 {
  66         u32 i;
  67
  68         for (i = 0; i <= 31; i++) {
  69                 if (((BitMask >> i) &  0x1) == 1)
  70                         break;
  71         }
  72
  73         return i;
  74 }
  75
  76
  77 /**
  78 * Function:     PHY_QueryBBReg
  79 *
  80 * OverView:     Read "sepcific bits" from BB register
  81 *
  82 * Input:
  83 *                       PADAPTER                Adapter,
  84 *                       u4Byte                  RegAddr,                //The target address to be readback
  85 *                       u4Byte                  BitMask         //The target bit position in the target address
  86 *                                                                               //to be readback
  87 * Output:       None
  88 * Return:               u4Byte                  Data                    //The readback register value
  89 * Note:         This function is equal to "GetRegSetting" in PHY programming guide
  90 */
  91 u32
  92 PHY_QueryBBReg_8703B(
  93         IN      PADAPTER        Adapter,
  94         IN      u32             RegAddr,
  95         IN      u32             BitMask
  96 )
  97 {
  98         u32     ReturnValue = 0, OriginalValue, BitShift;
  99         u16     BBWaitCounter = 0;
 100
 101 #if (DISABLE_BB_RF == 1)
 102         return 0;
 103 #endif
 104
 105
 106         OriginalValue = rtw_read32(Adapter, RegAddr);
 107         BitShift = phy_CalculateBitShift(BitMask);
 108         ReturnValue = (OriginalValue & BitMask) >> BitShift;
 109
 110         return ReturnValue;
 111
 112 }
 113
 114
 115 /**
 116 * Function:     PHY_SetBBReg
 117 *
 118 * OverView:     Write "Specific bits" to BB register (page 8~)
 119 *
 120 * Input:
 121 *                       PADAPTER                Adapter,
 122 *                       u4Byte                  RegAddr,                //The target address to be modified
 123 *                       u4Byte                  BitMask         //The target bit position in the target address
 124 *                                                                               //to be modified
 125 *                       u4Byte                  Data                    //The new register value in the target bit position
 126 *                                                                               //of the target address
 127 *
 128 * Output:       None
 129 * Return:               None
 130 * Note:         This function is equal to "PutRegSetting" in PHY programming guide
 131 */
 132
 133 VOID
 134 PHY_SetBBReg_8703B(
 135         IN      PADAPTER        Adapter,
 136         IN      u32             RegAddr,
 137         IN      u32             BitMask,
 138         IN      u32             Data
 139 )
 140 {
 141         HAL_DATA_TYPE   *pHalData               = GET_HAL_DATA(Adapter);
 142         /* u16                  BBWaitCounter   = 0; */
 143         u32                     OriginalValue, BitShift;
 144
 145 #if (DISABLE_BB_RF == 1)
 146         return;
 147 #endif
 148
 149
 150         if (BitMask != bMaskDWord) { /* if not "double word" write */
 151                 OriginalValue = rtw_read32(Adapter, RegAddr);
 152                 BitShift = phy_CalculateBitShift(BitMask);
 153                 Data = ((OriginalValue & (~BitMask)) | ((Data << BitShift) & BitMask));
 154         }
 155
 156         rtw_write32(Adapter, RegAddr, Data);
 157
 158 }
 159
 160
 161 /*
 162  * 2. RF register R/W API
 163  *   */
 164
 165 /*-----------------------------------------------------------------------------
 166  * Function:    phy_FwRFSerialRead()
 167  *
 168  * Overview:    We support firmware to execute RF-R/W.
 169  *
 170  * Input:               NONE
 171  *
 172  * Output:              NONE
 173  *
 174  * Return:              NONE
 175  *
 176  * Revised History:
 177  *      When            Who             Remark
 178  *      01/21/2008      MHC             Create Version 0.
 179  *
 180  *---------------------------------------------------------------------------*/
 181 static  u32
 182 phy_FwRFSerialRead(
 183         IN      PADAPTER                        Adapter,
 184         IN      RF_PATH                 eRFPath,
 185         IN      u32                             Offset)
 186 {
 187         u32             retValue = 0;
 188         /* RT_ASSERT(FALSE,("deprecate!\n")); */
 189         return retValue;
 190
 191 }       /* phy_FwRFSerialRead */
 192
 193
 194 /*-----------------------------------------------------------------------------
 195  * Function:    phy_FwRFSerialWrite()
 196  *
 197  * Overview:    We support firmware to execute RF-R/W.
 198  *
 199  * Input:               NONE
 200  *
 201  * Output:              NONE
 202  *
 203  * Return:              NONE
 204  *
 205  * Revised History:
 206  *      When            Who             Remark
 207  *      01/21/2008      MHC             Create Version 0.
 208  *
 209  *---------------------------------------------------------------------------*/
 210 static  VOID
 211 phy_FwRFSerialWrite(
 212         IN      PADAPTER                        Adapter,
 213         IN      RF_PATH                 eRFPath,
 214         IN      u32                             Offset,
 215         IN      u32                             Data)
 216 {
 217         /* RT_ASSERT(FALSE,("deprecate!\n")); */
 218 }
 219
 220 static  u32
 221 phy_RFSerialRead_8703B(
 222         IN      PADAPTER                        Adapter,
 223         IN      RF_PATH                 eRFPath,
 224         IN      u32                             Offset
 225 )
 226 {
 227         u32                                             retValue = 0;
 228         HAL_DATA_TYPE                           *pHalData = GET_HAL_DATA(Adapter);
 229         BB_REGISTER_DEFINITION_T        *pPhyReg = &pHalData->PHYRegDef[eRFPath];
 230         u32                                             NewOffset;
 231         u32                                             tmplong, tmplong2;
 232         u8                                      RfPiEnable = 0;
 233         u4Byte                                          MaskforPhySet = 0;
 234         int i = 0;
 235
 236         _enter_critical_mutex(&(adapter_to_dvobj(Adapter)->rf_read_reg_mutex) , NULL);
 237         /*  */
 238         /* Make sure RF register offset is correct */
 239         /*  */
 240         Offset &= 0xff;
 241
 242         NewOffset = Offset;
 243
 244         if (eRFPath == RF_PATH_A) {
 245                 tmplong2 = phy_query_bb_reg(Adapter, rFPGA0_XA_HSSIParameter2 | MaskforPhySet, bMaskDWord);
 246                 tmplong2 = (tmplong2 & (~bLSSIReadAddress)) | (NewOffset << 23) | bLSSIReadEdge;        /* T65 RF */
 247                 phy_set_bb_reg(Adapter, rFPGA0_XA_HSSIParameter2 | MaskforPhySet, bMaskDWord, tmplong2 & (~bLSSIReadEdge));
 248         } else {
 249                 tmplong2 = phy_query_bb_reg(Adapter, rFPGA0_XB_HSSIParameter2 | MaskforPhySet, bMaskDWord);
 250                 tmplong2 = (tmplong2 & (~bLSSIReadAddress)) | (NewOffset << 23) | bLSSIReadEdge;        /* T65 RF */
 251                 phy_set_bb_reg(Adapter, rFPGA0_XB_HSSIParameter2 | MaskforPhySet, bMaskDWord, tmplong2 & (~bLSSIReadEdge));
 252         }
 253
 254         tmplong2 = phy_query_bb_reg(Adapter, rFPGA0_XA_HSSIParameter2 | MaskforPhySet, bMaskDWord);
 255         phy_set_bb_reg(Adapter, rFPGA0_XA_HSSIParameter2 | MaskforPhySet, bMaskDWord, tmplong2 & (~bLSSIReadEdge));
 256         phy_set_bb_reg(Adapter, rFPGA0_XA_HSSIParameter2 | MaskforPhySet, bMaskDWord, tmplong2 | bLSSIReadEdge);
 257
 258         rtw_udelay_os(10);
 259
 260         for (i = 0; i < 2; i++)
 261                 rtw_udelay_os(MAX_STALL_TIME);
 262         rtw_udelay_os(10);
 263
 264         if (eRFPath == RF_PATH_A)
 265                 RfPiEnable = (u1Byte)phy_query_bb_reg(Adapter, rFPGA0_XA_HSSIParameter1 | MaskforPhySet, BIT8);
 266         else if (eRFPath == RF_PATH_B)
 267                 RfPiEnable = (u1Byte)phy_query_bb_reg(Adapter, rFPGA0_XB_HSSIParameter1 | MaskforPhySet, BIT8);
 268
 269         if (RfPiEnable) {
 270                 /* Read from BBreg8b8, 12 bits for 8190, 20bits for T65 RF */
 271                 retValue = phy_query_bb_reg(Adapter, pPhyReg->rfLSSIReadBackPi | MaskforPhySet, bLSSIReadBackData);
 272
 273                 /* RT_DISP(FINIT, INIT_RF, ("Readback from RF-PI : 0x%x\n", retValue)); */
 274         } else {
 275                 /* Read from BBreg8a0, 12 bits for 8190, 20 bits for T65 RF */
 276                 retValue = phy_query_bb_reg(Adapter, pPhyReg->rfLSSIReadBack | MaskforPhySet, bLSSIReadBackData);
 277
 278                 /* RT_DISP(FINIT, INIT_RF,("Readback from RF-SI : 0x%x\n", retValue)); */
 279         }
 280         _exit_critical_mutex(&(adapter_to_dvobj(Adapter)->rf_read_reg_mutex) , NULL);
 281         return retValue;
 282
 283 }
 284
 285 /**
 286 * Function:     phy_RFSerialWrite_8703B
 287 *
 288 * OverView:     Write data to RF register (page 8~)
 289 *
 290 * Input:
 291 *                       PADAPTER                Adapter,
 292 *                       RF_PATH                 eRFPath,        //Radio path of A/B/C/D
 293 *                       u4Byte                  Offset,         //The target address to be read
 294 *                       u4Byte                  Data                    //The new register Data in the target bit position
 295 *                                                                               //of the target to be read
 296 *
 297 * Output:       None
 298 * Return:               None
 299 * Note:         Threre are three types of serial operations:
 300 *                       1. Software serial write
 301 *                       2. Hardware LSSI-Low Speed Serial Interface
 302 *                       3. Hardware HSSI-High speed
 303 *                       serial write. Driver need to implement (1) and (2).
 304 *                       This function is equal to the combination of RF_ReadReg() and  RFLSSIRead()
 305  *
 306  * Note:                  For RF8256 only
 307  *                       The total count of RTL8256(Zebra4) register is around 36 bit it only employs
 308  *                       4-bit RF address. RTL8256 uses "register mode control bit" (Reg00[12], Reg00[10])
 309  *                       to access register address bigger than 0xf. See "Appendix-4 in PHY Configuration
 310  *                       programming guide" for more details.
 311  *                       Thus, we define a sub-finction for RTL8526 register address conversion
 312  *                     ===========================================================
 313  *                       Register Mode          RegCTL[1]               RegCTL[0]               Note
 314  *                                                              (Reg00[12])             (Reg00[10])
 315  *                     ===========================================================
 316  *                       Reg_Mode0                              0                               x                       Reg 0 ~15(0x0 ~ 0xf)
 317  *                     ------------------------------------------------------------------
 318  *                       Reg_Mode1                              1                               0                       Reg 16 ~30(0x1 ~ 0xf)
 319  *                     ------------------------------------------------------------------
 320  *                       Reg_Mode2                              1                               1                       Reg 31 ~ 45(0x1 ~ 0xf)
 321  *                     ------------------------------------------------------------------
 322  *
 323  *      2008/09/02      MH      Add 92S RF definition
 324  *
 325  *
 326  *
 327 */
 328 static  VOID
 329 phy_RFSerialWrite_8703B(
 330         IN      PADAPTER                        Adapter,
 331         IN      RF_PATH                 eRFPath,
 332         IN      u32                             Offset,
 333         IN      u32                             Data
 334 )
 335 {
 336         u32                                             DataAndAddr = 0;
 337         HAL_DATA_TYPE                           *pHalData = GET_HAL_DATA(Adapter);
 338         BB_REGISTER_DEFINITION_T        *pPhyReg = &pHalData->PHYRegDef[eRFPath];
 339         u32                                             NewOffset;
 340
 341         Offset &= 0xff;
 342
 343         /*  */
 344         /* Shadow Update */
 345         /*  */
 346         /* PHY_RFShadowWrite(Adapter, eRFPath, Offset, Data); */
 347
 348         /*  */
 349         /* Switch page for 8256 RF IC */
 350         /*  */
 351         NewOffset = Offset;
 352
 353         /*  */
 354         /* Put write addr in [5:0]  and write data in [31:16] */
 355         /*  */
 356         /* DataAndAddr = (Data<<16) | (NewOffset&0x3f); */
 357         DataAndAddr = ((NewOffset << 20) | (Data & 0x000fffff)) & 0x0fffffff;   /* T65 RF */
 358
 359         /*  */
 360         /* Write Operation */
 361         /*  */
 362         phy_set_bb_reg(Adapter, pPhyReg->rf3wireOffset, bMaskDWord, DataAndAddr);
 363         /* RTPRINT(FPHY, PHY_RFW, ("RFW-%d Addr[0x%lx]=0x%lx\n", eRFPath, pPhyReg->rf3wireOffset, DataAndAddr)); */
 364
 365 }
 366
 367
 368 /**
 369 * Function:     PHY_QueryRFReg
 370 *
 371 * OverView:     Query "Specific bits" to RF register (page 8~)
 372 *
 373 * Input:
 374 *                       PADAPTER                Adapter,
 375 *                       RF_PATH                 eRFPath,        //Radio path of A/B/C/D
 376 *                       u4Byte                  RegAddr,                //The target address to be read
 377 *                       u4Byte                  BitMask         //The target bit position in the target address
 378 *                                                                               //to be read
 379 *
 380 * Output:       None
 381 * Return:               u4Byte                  Readback value
 382 * Note:         This function is equal to "GetRFRegSetting" in PHY programming guide
 383 */
 384 u32
 385 PHY_QueryRFReg_8703B(
 386         IN      PADAPTER                        Adapter,
 387         IN      u8                      eRFPath,
 388         IN      u32                             RegAddr,
 389         IN      u32                             BitMask
 390 )
 391 {
 392         u32 Original_Value, Readback_Value, BitShift;
 393
 394 #if (DISABLE_BB_RF == 1)
 395         return 0;
 396 #endif
 397
 398         Original_Value = phy_RFSerialRead_8703B(Adapter, eRFPath, RegAddr);
 399
 400         BitShift =  phy_CalculateBitShift(BitMask);
 401         Readback_Value = (Original_Value & BitMask) >> BitShift;
 402
 403         return Readback_Value;
 404 }
 405
 406 /**
 407 * Function:     PHY_SetRFReg
 408 *
 409 * OverView:     Write "Specific bits" to RF register (page 8~)
 410 *
 411 * Input:
 412 *                       PADAPTER                Adapter,
 413 *                       RF_PATH                 eRFPath,        //Radio path of A/B/C/D
 414 *                       u4Byte                  RegAddr,                //The target address to be modified
 415 *                       u4Byte                  BitMask         //The target bit position in the target address
 416 *                                                                               //to be modified
 417 *                       u4Byte                  Data                    //The new register Data in the target bit position
 418 *                                                                               //of the target address
 419 *
 420 * Output:       None
 421 * Return:               None
 422 * Note:         This function is equal to "PutRFRegSetting" in PHY programming guide
 423 */
 424 VOID
 425 PHY_SetRFReg_8703B(
 426         IN      PADAPTER                        Adapter,
 427         IN      u8                              eRFPath,
 428         IN      u32                             RegAddr,
 429         IN      u32                             BitMask,
 430         IN      u32                             Data
 431 )
 432 {
 433         u32             Original_Value, BitShift;
 434
 435 #if (DISABLE_BB_RF == 1)
 436         return;
 437 #endif
 438
 439         /* RF data is 12 bits only */
 440         if (BitMask != bRFRegOffsetMask) {
 441                 Original_Value = phy_RFSerialRead_8703B(Adapter, eRFPath, RegAddr);
 442                 BitShift =  phy_CalculateBitShift(BitMask);
 443                 Data = ((Original_Value & (~BitMask)) | (Data << BitShift));
 444         }
 445
 446         phy_RFSerialWrite_8703B(Adapter, eRFPath, RegAddr, Data);
 447 }
 448
 449
 450 /*
 451  * 3. Initial MAC/BB/RF config by reading MAC/BB/RF txt.
 452  *   */
 453
 454
 455 /*-----------------------------------------------------------------------------
 456  * Function:    PHY_MACConfig8192C
 457  *
 458  * Overview:    Condig MAC by header file or parameter file.
 459  *
 460  * Input:       NONE
 461  *
 462  * Output:      NONE
 463  *
 464  * Return:      NONE
 465  *
 466  * Revised History:
 467  *  When                Who             Remark
 468  *  08/12/2008  MHC             Create Version 0.
 469  *
 470  *---------------------------------------------------------------------------*/
 471 s32 PHY_MACConfig8703B(PADAPTER Adapter)
 472 {
 473         int             rtStatus = _SUCCESS;
 474         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(Adapter);
 475
 476         /*  */
 477         /* Config MAC */
 478         /*  */
 479 #ifdef CONFIG_LOAD_PHY_PARA_FROM_FILE
 480         rtStatus = phy_ConfigMACWithParaFile(Adapter, PHY_FILE_MAC_REG);
 481         if (rtStatus == _FAIL)
 482 #endif
 483         {
 484 #ifdef CONFIG_EMBEDDED_FWIMG
 485                 odm_config_mac_with_header_file(&pHalData->odmpriv);
 486                 rtStatus = _SUCCESS;
 487 #endif/* CONFIG_EMBEDDED_FWIMG */
 488         }
 489
 490         return rtStatus;
 491 }
 492
 493 /**
 494 * Function:     phy_InitBBRFRegisterDefinition
 495 *
 496 * OverView:     Initialize Register definition offset for Radio Path A/B/C/D
 497 *
 498 * Input:
 499 *                       PADAPTER                Adapter,
 500 *
 501 * Output:       None
 502 * Return:               None
 503 * Note:         The initialization value is constant and it should never be changes
 504 */
 505 static  VOID
 506 phy_InitBBRFRegisterDefinition(
 507         IN      PADAPTER                Adapter
 508 )
 509 {
 510         HAL_DATA_TYPE           *pHalData = GET_HAL_DATA(Adapter);
 511
 512         /* RF Interface Sowrtware Control */
 513         pHalData->PHYRegDef[ODM_RF_PATH_A].rfintfs = rFPGA0_XAB_RFInterfaceSW; /* 16 LSBs if read 32-bit from 0x870 */
 514         pHalData->PHYRegDef[ODM_RF_PATH_B].rfintfs = rFPGA0_XAB_RFInterfaceSW; /* 16 MSBs if read 32-bit from 0x870 (16-bit for 0x872) */
 515
 516         /* RF Interface Output (and Enable) */
 517         pHalData->PHYRegDef[ODM_RF_PATH_A].rfintfo = rFPGA0_XA_RFInterfaceOE; /* 16 LSBs if read 32-bit from 0x860 */
 518         pHalData->PHYRegDef[ODM_RF_PATH_B].rfintfo = rFPGA0_XB_RFInterfaceOE; /* 16 LSBs if read 32-bit from 0x864 */
 519
 520         /* RF Interface (Output and)  Enable */
 521         pHalData->PHYRegDef[ODM_RF_PATH_A].rfintfe = rFPGA0_XA_RFInterfaceOE; /* 16 MSBs if read 32-bit from 0x860 (16-bit for 0x862) */
 522         pHalData->PHYRegDef[ODM_RF_PATH_B].rfintfe = rFPGA0_XB_RFInterfaceOE; /* 16 MSBs if read 32-bit from 0x864 (16-bit for 0x866) */
 523
 524         pHalData->PHYRegDef[ODM_RF_PATH_A].rf3wireOffset = rFPGA0_XA_LSSIParameter; /* LSSI Parameter */
 525         pHalData->PHYRegDef[ODM_RF_PATH_B].rf3wireOffset = rFPGA0_XB_LSSIParameter;
 526
 527         pHalData->PHYRegDef[ODM_RF_PATH_A].rfHSSIPara2 = rFPGA0_XA_HSSIParameter2;  /* wire control parameter2 */
 528         pHalData->PHYRegDef[ODM_RF_PATH_B].rfHSSIPara2 = rFPGA0_XB_HSSIParameter2;  /* wire control parameter2 */
 529
 530         /* Tranceiver Readback LSSI/HSPI mode */
 531         pHalData->PHYRegDef[ODM_RF_PATH_A].rfLSSIReadBack = rFPGA0_XA_LSSIReadBack;
 532         pHalData->PHYRegDef[ODM_RF_PATH_B].rfLSSIReadBack = rFPGA0_XB_LSSIReadBack;
 533         pHalData->PHYRegDef[ODM_RF_PATH_A].rfLSSIReadBackPi = TransceiverA_HSPI_Readback;
 534         pHalData->PHYRegDef[ODM_RF_PATH_B].rfLSSIReadBackPi = TransceiverB_HSPI_Readback;
 535
 536 }
 537
 538 static  int
 539 phy_BB8703b_Config_ParaFile(
 540         IN      PADAPTER        Adapter
 541 )
 542 {
 543         HAL_DATA_TYPE           *pHalData = GET_HAL_DATA(Adapter);
 544         int                     rtStatus = _SUCCESS;
 545
 546         /*  */
 547         /* 1. Read PHY_REG.TXT BB INIT!! */
 548         /*  */
 549 #ifdef CONFIG_LOAD_PHY_PARA_FROM_FILE
 550         if (phy_ConfigBBWithParaFile(Adapter, PHY_FILE_PHY_REG, CONFIG_BB_PHY_REG) == _FAIL)
 551 #endif
 552         {
 553 #ifdef CONFIG_EMBEDDED_FWIMG
 554                 if (HAL_STATUS_SUCCESS != odm_config_bb_with_header_file(&pHalData->odmpriv, CONFIG_BB_PHY_REG))
 555                         rtStatus = _FAIL;
 556 #endif
 557         }
 558
 559         if (rtStatus != _SUCCESS) {
 560                 RTW_INFO("%s():Write BB Reg Fail!!", __func__);
 561                 goto phy_BB8190_Config_ParaFile_Fail;
 562         }
 563
 564 #if MP_DRIVER == 1
 565         if (Adapter->registrypriv.mp_mode == 1) {
 566                 /*  */
 567                 /* 1.1 Read PHY_REG_MP.TXT BB INIT!! */
 568                 /*  */
 569 #ifdef CONFIG_LOAD_PHY_PARA_FROM_FILE
 570                 if (phy_ConfigBBWithMpParaFile(Adapter, PHY_FILE_PHY_REG_MP) == _FAIL)
 571 #endif
 572                 {
 573 #ifdef CONFIG_EMBEDDED_FWIMG
 574                         if (HAL_STATUS_SUCCESS != odm_config_bb_with_header_file(&pHalData->odmpriv, CONFIG_BB_PHY_REG_MP))
 575                                 rtStatus = _FAIL;
 576 #endif
 577                 }
 578
 579                 if (rtStatus != _SUCCESS) {
 580                         RTW_INFO("%s():Write BB Reg MP Fail!!", __func__);
 581                         goto phy_BB8190_Config_ParaFile_Fail;
 582                 }
 583         }
 584 #endif  /*  #if (MP_DRIVER == 1) */
 585
 586         /*  */
 587         /* 2. Read BB AGC table Initialization */
 588         /*  */
 589 #ifdef CONFIG_LOAD_PHY_PARA_FROM_FILE
 590         if (phy_ConfigBBWithParaFile(Adapter, PHY_FILE_AGC_TAB, CONFIG_BB_AGC_TAB) == _FAIL)
 591 #endif
 592         {
 593 #ifdef CONFIG_EMBEDDED_FWIMG
 594                 if (HAL_STATUS_SUCCESS != odm_config_bb_with_header_file(&pHalData->odmpriv, CONFIG_BB_AGC_TAB))
 595                         rtStatus = _FAIL;
 596 #endif
 597         }
 598
 599         if (rtStatus != _SUCCESS) {
 600                 RTW_INFO("%s():AGC Table Fail\n", __func__);
 601                 goto phy_BB8190_Config_ParaFile_Fail;
 602         }
 603
 604 phy_BB8190_Config_ParaFile_Fail:
 605
 606         return rtStatus;
 607 }
 608
 609
 610 int
 611 PHY_BBConfig8703B(
 612         IN      PADAPTER        Adapter
 613 )
 614 {
 615         int     rtStatus = _SUCCESS;
 616         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(Adapter);
 617         u32     RegVal;
 618         u8      TmpU1B = 0;
 619         u8      value8;
 620
 621         phy_InitBBRFRegisterDefinition(Adapter);
 622
 623         /* Enable BB and RF */
 624         RegVal = rtw_read16(Adapter, REG_SYS_FUNC_EN);
 625         rtw_write16(Adapter, REG_SYS_FUNC_EN, (u16)(RegVal | BIT13 | BIT0 | BIT1));
 626
 627         rtw_write8(Adapter, REG_RF_CTRL, RF_EN | RF_RSTB | RF_SDMRSTB);
 628
 629         rtw_usleep_os(10);
 630
 631         phy_set_rf_reg(Adapter, ODM_RF_PATH_A, 0x1, 0xfffff, 0x780);
 632
 633 #if 0
 634         /* 20090923 Joseph: Advised by Steven and Jenyu. Power sequence before init RF. */
 635         rtw_write8(Adapter, REG_AFE_PLL_CTRL, 0x83);
 636         rtw_write8(Adapter, REG_AFE_PLL_CTRL + 1, 0xdb);
 637 #endif
 638
 639         rtw_write8(Adapter, REG_SYS_FUNC_EN, FEN_PPLL | FEN_PCIEA | FEN_DIO_PCIE | FEN_BB_GLB_RSTn | FEN_BBRSTB);
 640
 641         rtw_write8(Adapter, REG_AFE_XTAL_CTRL + 1, 0x80);
 642
 643         /*  */
 644         /* Config BB and AGC */
 645         /*  */
 646         rtStatus = phy_BB8703b_Config_ParaFile(Adapter);
 647
 648         hal_set_crystal_cap(Adapter, pHalData->crystal_cap);
 649
 650         return rtStatus;
 651 }
 652
 653 void phy_LCK_8703B(
 654         IN      PADAPTER        Adapter
 655 )
 656 {
 657         phy_set_rf_reg(Adapter, RF_PATH_A, 0xB0, bRFRegOffsetMask, 0xDFBE0);
 658         phy_set_rf_reg(Adapter, RF_PATH_A, RF_CHNLBW, bRFRegOffsetMask, 0x8C01);
 659         rtw_mdelay_os(200);
 660         phy_set_rf_reg(Adapter, RF_PATH_A, 0xB0, bRFRegOffsetMask, 0xDFFE0);
 661 }
 662
 663 #if 0
 664 /* Block & Path enable */
 665 #define         rOFDMCCKEN_Jaguar               0x808 /* OFDM/CCK block enable */
 666 #define         bOFDMEN_Jaguar                  0x20000000
 667 #define         bCCKEN_Jaguar                   0x10000000
 668 #define         rRxPath_Jaguar                  0x808   /* Rx antenna */
 669 #define         bRxPath_Jaguar                  0xff
 670 #define         rTxPath_Jaguar                  0x80c   /* Tx antenna */
 671 #define         bTxPath_Jaguar                  0x0fffffff
 672 #define         rCCK_RX_Jaguar                  0xa04   /* for cck rx path selection */
 673 #define         bCCK_RX_Jaguar                  0x0c000000
 674 #define         rVhtlen_Use_Lsig_Jaguar 0x8c3   /* Use LSIG for VHT length */
 675 VOID
 676 PHY_BB8703B_Config_1T(
 677         IN PADAPTER Adapter
 678 )
 679 {
 680         /* BB OFDM RX Path_A */
 681         phy_set_bb_reg(Adapter, rRxPath_Jaguar, bRxPath_Jaguar, 0x11);
 682         /* BB OFDM TX Path_A */
 683         phy_set_bb_reg(Adapter, rTxPath_Jaguar, bMaskLWord, 0x1111);
 684         /* BB CCK R/Rx Path_A */
 685         phy_set_bb_reg(Adapter, rCCK_RX_Jaguar, bCCK_RX_Jaguar, 0x0);
 686         /* MCS support */
 687         phy_set_bb_reg(Adapter, 0x8bc, 0xc0000060, 0x4);
 688         /* RF Path_B HSSI OFF */
 689         phy_set_bb_reg(Adapter, 0xe00, 0xf, 0x4);
 690         /* RF Path_B Power Down */
 691         phy_set_bb_reg(Adapter, 0xe90, bMaskDWord, 0);
 692         /* ADDA Path_B OFF */
 693         phy_set_bb_reg(Adapter, 0xe60, bMaskDWord, 0);
 694         phy_set_bb_reg(Adapter, 0xe64, bMaskDWord, 0);
 695 }
 696 #endif
 697
 698 int
 699 PHY_RFConfig8703B(
 700         IN      PADAPTER        Adapter
 701 )
 702 {
 703         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(Adapter);
 704         int             rtStatus = _SUCCESS;
 705
 706         /*  */
 707         /* RF config */
 708         /*  */
 709         rtStatus = PHY_RF6052_Config8703B(Adapter);
 710
 711         phy_LCK_8703B(Adapter);
 712         /* PHY_BB8703B_Config_1T(Adapter); */
 713
 714         return rtStatus;
 715 }
 716
 717 /*-----------------------------------------------------------------------------
 718  * Function:    PHY_ConfigRFWithParaFile()
 719  *
 720  * Overview:    This function read RF parameters from general file format, and do RF 3-wire
 721  *
 722  * Input:       PADAPTER                        Adapter
 723  *                      ps1Byte                         pFileName
 724  *                      RF_PATH                         eRFPath
 725  *
 726  * Output:      NONE
 727  *
 728  * Return:      RT_STATUS_SUCCESS: configuration file exist
 729  *
 730  * Note:                Delay may be required for RF configuration
 731  *---------------------------------------------------------------------------*/
 732 int
 733 PHY_ConfigRFWithParaFile_8703B(
 734         IN      PADAPTER                        Adapter,
 735         IN      u8                              *pFileName,
 736         RF_PATH                         eRFPath
 737 )
 738 {
 739         return _SUCCESS;
 740 }
 741
 742 /**************************************************************************************************************
 743  *   Description:
 744  *       The low-level interface to set TxAGC , called by both MP and Normal Driver.
 745  *
 746  *                                                                                    <20120830, Kordan>
 747  **************************************************************************************************************/
 748
 749 VOID
 750 PHY_SetTxPowerIndex_8703B(
 751         IN      PADAPTER                        Adapter,
 752         IN      u32                                     PowerIndex,
 753         IN      u8                                      RFPath,
 754         IN      u8                                      Rate
 755 )
 756 {
 757         if (RFPath == ODM_RF_PATH_A || RFPath == ODM_RF_PATH_B) {
 758                 switch (Rate) {
 759                 case MGN_1M:
 760                         phy_set_bb_reg(Adapter, rTxAGC_A_CCK1_Mcs32,      bMaskByte1, PowerIndex);
 761                         break;
 762                 case MGN_2M:
 763                         phy_set_bb_reg(Adapter, rTxAGC_B_CCK11_A_CCK2_11, bMaskByte1, PowerIndex);
 764                         break;
 765                 case MGN_5_5M:
 766                         phy_set_bb_reg(Adapter, rTxAGC_B_CCK11_A_CCK2_11, bMaskByte2, PowerIndex);
 767                         break;
 768                 case MGN_11M:
 769                         phy_set_bb_reg(Adapter, rTxAGC_B_CCK11_A_CCK2_11, bMaskByte3, PowerIndex);
 770                         break;
 771
 772                 case MGN_6M:
 773                         phy_set_bb_reg(Adapter, rTxAGC_A_Rate18_06, bMaskByte0, PowerIndex);
 774                         break;
 775                 case MGN_9M:
 776                         phy_set_bb_reg(Adapter, rTxAGC_A_Rate18_06, bMaskByte1, PowerIndex);
 777                         break;
 778                 case MGN_12M:
 779                         phy_set_bb_reg(Adapter, rTxAGC_A_Rate18_06, bMaskByte2, PowerIndex);
 780                         break;
 781                 case MGN_18M:
 782                         phy_set_bb_reg(Adapter, rTxAGC_A_Rate18_06, bMaskByte3, PowerIndex);
 783                         break;
 784
 785                 case MGN_24M:
 786                         phy_set_bb_reg(Adapter, rTxAGC_A_Rate54_24, bMaskByte0, PowerIndex);
 787                         break;
 788                 case MGN_36M:
 789                         phy_set_bb_reg(Adapter, rTxAGC_A_Rate54_24, bMaskByte1, PowerIndex);
 790                         break;
 791                 case MGN_48M:
 792                         phy_set_bb_reg(Adapter, rTxAGC_A_Rate54_24, bMaskByte2, PowerIndex);
 793                         break;
 794                 case MGN_54M:
 795                         phy_set_bb_reg(Adapter, rTxAGC_A_Rate54_24, bMaskByte3, PowerIndex);
 796                         break;
 797
 798                 case MGN_MCS0:
 799                         phy_set_bb_reg(Adapter, rTxAGC_A_Mcs03_Mcs00, bMaskByte0, PowerIndex);
 800                         break;
 801                 case MGN_MCS1:
 802                         phy_set_bb_reg(Adapter, rTxAGC_A_Mcs03_Mcs00, bMaskByte1, PowerIndex);
 803                         break;
 804                 case MGN_MCS2:
 805                         phy_set_bb_reg(Adapter, rTxAGC_A_Mcs03_Mcs00, bMaskByte2, PowerIndex);
 806                         break;
 807                 case MGN_MCS3:
 808                         phy_set_bb_reg(Adapter, rTxAGC_A_Mcs03_Mcs00, bMaskByte3, PowerIndex);
 809                         break;
 810
 811                 case MGN_MCS4:
 812                         phy_set_bb_reg(Adapter, rTxAGC_A_Mcs07_Mcs04, bMaskByte0, PowerIndex);
 813                         break;
 814                 case MGN_MCS5:
 815                         phy_set_bb_reg(Adapter, rTxAGC_A_Mcs07_Mcs04, bMaskByte1, PowerIndex);
 816                         break;
 817                 case MGN_MCS6:
 818                         phy_set_bb_reg(Adapter, rTxAGC_A_Mcs07_Mcs04, bMaskByte2, PowerIndex);
 819                         break;
 820                 case MGN_MCS7:
 821                         phy_set_bb_reg(Adapter, rTxAGC_A_Mcs07_Mcs04, bMaskByte3, PowerIndex);
 822                         break;
 823
 824                 default:
 825                         RTW_INFO("Invalid Rate!!\n");
 826                         break;
 827                 }
 828         }
 829 }
 830
 831 u8
 832 phy_GetCurrentTxNum_8703B(
 833         IN      PADAPTER                pAdapter
 834 )
 835 {
 836         return RF_TX_NUM_NONIMPLEMENT;
 837 }
 838
 839 u8
 840 PHY_GetTxPowerIndex_8703B(
 841         IN      PADAPTER                        pAdapter,
 842         IN      u8                                      RFPath,
 843         IN      u8                                      Rate,
 844         IN      u8                                      BandWidth,
 845         IN      u8                                      Channel,
 846         struct txpwr_idx_comp *tic
 847 )
 848 {
 849         PHAL_DATA_TYPE pHalData = GET_HAL_DATA(pAdapter);
 850         u8 base_idx = 0, power_idx = 0;
 851         s8 by_rate_diff = 0, limit = 0, tpt_offset = 0, extra_bias = 0;
 852         BOOLEAN bIn24G = _FALSE;
 853
 854         base_idx = PHY_GetTxPowerIndexBase(pAdapter, RFPath, Rate, BandWidth, Channel, &bIn24G);
 855
 856         by_rate_diff = PHY_GetTxPowerByRate(pAdapter, BAND_ON_2_4G, ODM_RF_PATH_A, RF_1TX, Rate);
 857         limit = PHY_GetTxPowerLimit(pAdapter, pAdapter->registrypriv.RegPwrTblSel, (u8)(!bIn24G), pHalData->current_channel_bw, RFPath, Rate, pHalData->current_channel);
 858
 859         tpt_offset = PHY_GetTxPowerTrackingOffset(pAdapter, RFPath, Rate);
 860
 861         if (tic) {
 862                 tic->base = base_idx;
 863                 tic->by_rate = by_rate_diff;
 864                 tic->limit = limit;
 865                 tic->tpt = tpt_offset;
 866                 tic->ebias = extra_bias;
 867         }
 868
 869         by_rate_diff = by_rate_diff > limit ? limit : by_rate_diff;
 870         power_idx = base_idx + by_rate_diff + tpt_offset + extra_bias;
 871
 872         if (power_idx > MAX_POWER_INDEX)
 873                 power_idx = MAX_POWER_INDEX;
 874
 875         return power_idx;
 876 }
 877
 878 VOID
 879 PHY_SetTxPowerLevel8703B(
 880         IN      PADAPTER                Adapter,
 881         IN      u8                              Channel
 882 )
 883 {
 884         PHAL_DATA_TYPE  pHalData = GET_HAL_DATA(Adapter);
 885         u8                              cur_antenna;
 886         u8                              RFPath = ODM_RF_PATH_A;
 887
 888 #ifdef CONFIG_ANTENNA_DIVERSITY
 889         rtw_hal_get_odm_var(Adapter, HAL_ODM_ANTDIV_SELECT, &cur_antenna, NULL);
 890
 891         if (pHalData->AntDivCfg)  /* antenna diversity Enable */
 892                 RFPath = ((cur_antenna == MAIN_ANT) ? ODM_RF_PATH_A : ODM_RF_PATH_B);
 893         else   /* antenna diversity disable */
 894 #endif
 895                 RFPath = pHalData->ant_path;
 896
 897
 898
 899         phy_set_tx_power_level_by_path(Adapter, Channel, RFPath);
 900
 901 }
 902
 903 VOID
 904 PHY_GetTxPowerLevel8703B(
 905         IN      PADAPTER                Adapter,
 906         OUT s32                         *powerlevel
 907 )
 908 {
 909         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(Adapter);
 910         s32                             TxPwrDbm = 13;
 911 #if 0
 912
 913         if (pMgntInfo->ClientConfigPwrInDbm != UNSPECIFIED_PWR_DBM)
 914                 *powerlevel = pMgntInfo->ClientConfigPwrInDbm;
 915         else
 916                 *powerlevel = TxPwrDbm;
 917 #endif
 918 }
 919
 920
 921 /* <20130321, VincentLan> A workaround to eliminate the 2440MHz & 2480MHz spur of 8703B. (Asked by Rock.) */
 922 VOID
 923 phy_SpurCalibration_8703B(
 924         IN      PADAPTER                                        pAdapter,
 925         IN      u1Byte                                          ToChannel,
 926         IN      u1Byte                                          threshold
 927 )
 928 {
 929         u4Byte          freq[6] = {0xFCCD, 0xFC4D, 0xFFCD, 0xFF4D, 0xFCCD, 0xFF9A}; /* {chnl 5, 6, 7, 8, 13, 14} */
 930         u1Byte          idx = 0;
 931         u1Byte          b_doNotch = FALSE;
 932         u1Byte          initial_gain;
 933         BOOLEAN         bHW_Ctrl = FALSE, bSW_Ctrl = FALSE, bHW_Ctrl_S1 = FALSE, bSW_Ctrl_S1 = FALSE;
 934         u4Byte          reg948;
 935
 936         /* add for notch */
 937         u4Byte                          wlan_channel, CurrentChannel, Is40MHz;
 938         HAL_DATA_TYPE           *pHalData       = GET_HAL_DATA(pAdapter);
 939         /* PMGNT_INFO                   pMgntInfo = &(pAdapter->MgntInfo); */
 940         struct PHY_DM_STRUCT            *pDM_Odm = &(pHalData->odmpriv);
 941         /* struct PHY_DM_STRUCT                 *pDM_Odm = &pHalData->DM_OutSrc; */
 942
 943         /* check threshold */
 944         if (threshold <= 0x0)
 945                 threshold = 0x16;
 946
 947         RTW_INFO("===>phy_SpurCalibration_8703B: Channel = %d\n", ToChannel);
 948
 949         if (ToChannel == 5)
 950                 idx = 0;
 951         else if (ToChannel == 6)
 952                 idx = 1;
 953         else if (ToChannel == 7)
 954                 idx = 2;
 955         else if (ToChannel == 8)
 956                 idx = 3;
 957         else if (ToChannel == 13)
 958                 idx = 4;
 959         else if (ToChannel == 14)
 960                 idx = 5;
 961         else
 962                 idx = 10;
 963
 964         reg948 = phy_query_bb_reg(pAdapter, rS0S1_PathSwitch, bMaskDWord);
 965         if ((reg948 & BIT6) == 0x0)
 966                 bSW_Ctrl = TRUE;
 967         else
 968                 bHW_Ctrl = TRUE;
 969
 970         if (bHW_Ctrl)
 971                 bHW_Ctrl_S1 = (phy_query_bb_reg(pAdapter, rFPGA0_XB_RFInterfaceOE, BIT5 | BIT4 | BIT3) == 0x1) ? TRUE : FALSE;
 972         else if (bSW_Ctrl)
 973                 bSW_Ctrl_S1 = ((reg948 & BIT9) == 0x0) ? TRUE : FALSE;
 974
 975         /* If wlan at S1 (both HW control & SW control) and current channel=5,6,7,8,13,14 */
 976         if ((bHW_Ctrl_S1 || bSW_Ctrl_S1) && (idx <= 5)) {
 977                 initial_gain = (u1Byte)(odm_get_bb_reg(pDM_Odm, rOFDM0_XAAGCCore1, bMaskByte0) & 0x7f);
 978                 odm_write_dig(pDM_Odm, 0x30);
 979                 phy_set_bb_reg(pAdapter, rFPGA0_AnalogParameter4, bMaskDWord, 0xccf000c0);              /* disable 3-wire */
 980
 981                 phy_set_bb_reg(pAdapter, rFPGA0_PSDFunction, bMaskDWord, freq[idx]);                            /* Setup PSD */
 982                 phy_set_bb_reg(pAdapter, rFPGA0_PSDFunction, bMaskDWord, 0x400000 | freq[idx]); /* Start PSD     */
 983
 984                 rtw_msleep_os(30);
 985
 986                 if (phy_query_bb_reg(pAdapter, rFPGA0_PSDReport, bMaskDWord) >= threshold)
 987                         b_doNotch = TRUE;
 988
 989                 phy_set_bb_reg(pAdapter, rFPGA0_PSDFunction, bMaskDWord, freq[idx]); /* turn off PSD */
 990                 phy_set_bb_reg(pAdapter, rFPGA0_AnalogParameter4, bMaskDWord, 0xccc000c0);      /* enable 3-wire */
 991                 odm_write_dig(pDM_Odm, initial_gain);
 992         }
 993
 994         /* --- Notch Filter --- Asked by Rock    */
 995         if (b_doNotch) {
 996                 CurrentChannel = odm_get_rf_reg(pDM_Odm, ODM_RF_PATH_A, RF_CHNLBW, bRFRegOffsetMask);
 997                 wlan_channel   = CurrentChannel & 0x0f;                                             /* Get center frequency */
 998
 999                 switch (wlan_channel) {                                                                                 /* Set notch filter                              */
1000                 case 5:
1001                 case 13:
1002                         odm_set_bb_reg(pDM_Odm, 0xC40, BIT28 | BIT27 | BIT26 | BIT25 | BIT24, 0xB);
1003                         odm_set_bb_reg(pDM_Odm, 0xC40, BIT9, 0x1);                    /* enable notch filter */
1004                         odm_set_bb_reg(pDM_Odm, 0xD40, bMaskDWord, 0x06000000);
1005                         odm_set_bb_reg(pDM_Odm, 0xD44, bMaskDWord, 0x00000000);
1006                         odm_set_bb_reg(pDM_Odm, 0xD48, bMaskDWord, 0x00000000);
1007                         odm_set_bb_reg(pDM_Odm, 0xD4C, bMaskDWord, 0x00000000);
1008                         odm_set_bb_reg(pDM_Odm, 0xD2C, BIT28, 0x1);                   /* enable CSI mask */
1009                         break;
1010                 case 6:
1011                         odm_set_bb_reg(pDM_Odm, 0xC40, BIT28 | BIT27 | BIT26 | BIT25 | BIT24, 0x4);
1012                         odm_set_bb_reg(pDM_Odm, 0xC40, BIT9, 0x1);                   /* enable notch filter */
1013                         odm_set_bb_reg(pDM_Odm, 0xD40, bMaskDWord, 0x00000600);
1014                         odm_set_bb_reg(pDM_Odm, 0xD44, bMaskDWord, 0x00000000);
1015                         odm_set_bb_reg(pDM_Odm, 0xD48, bMaskDWord, 0x00000000);
1016                         odm_set_bb_reg(pDM_Odm, 0xD4C, bMaskDWord, 0x00000000);
1017                         odm_set_bb_reg(pDM_Odm, 0xD2C, BIT28, 0x1);                   /* enable CSI mask */
1018                         break;
1019                 case 7:
1020                         odm_set_bb_reg(pDM_Odm, 0xC40, BIT28 | BIT27 | BIT26 | BIT25 | BIT24, 0x3);
1021                         odm_set_bb_reg(pDM_Odm, 0xC40, BIT9, 0x1);                   /* enable notch filter */
1022                         odm_set_bb_reg(pDM_Odm, 0xD40, bMaskDWord, 0x00000000);
1023                         odm_set_bb_reg(pDM_Odm, 0xD44, bMaskDWord, 0x00000000);
1024                         odm_set_bb_reg(pDM_Odm, 0xD48, bMaskDWord, 0x00000000);
1025                         odm_set_bb_reg(pDM_Odm, 0xD4C, bMaskDWord, 0x06000000);
1026                         odm_set_bb_reg(pDM_Odm, 0xD2C, BIT28, 0x1);                  /* enable CSI mask */
1027                         break;
1028                 case 8:
1029                         odm_set_bb_reg(pDM_Odm, 0xC40, BIT28 | BIT27 | BIT26 | BIT25 | BIT24, 0xA);
1030                         odm_set_bb_reg(pDM_Odm, 0xC40, BIT9, 0x1);                   /* enable notch filter */
1031                         odm_set_bb_reg(pDM_Odm, 0xD40, bMaskDWord, 0x00000000);
1032                         odm_set_bb_reg(pDM_Odm, 0xD44, bMaskDWord, 0x00000000);
1033                         odm_set_bb_reg(pDM_Odm, 0xD48, bMaskDWord, 0x00000000);
1034                         odm_set_bb_reg(pDM_Odm, 0xD4C, bMaskDWord, 0x00000380);
1035                         odm_set_bb_reg(pDM_Odm, 0xD2C, BIT28, 0x1);                  /* enable CSI mask */
1036                         break;
1037                 case 14:
1038                         odm_set_bb_reg(pDM_Odm, 0xC40, BIT28 | BIT27 | BIT26 | BIT25 | BIT24, 0x5);
1039                         odm_set_bb_reg(pDM_Odm, 0xC40, BIT9, 0x1);                   /* enable notch filter */
1040                         odm_set_bb_reg(pDM_Odm, 0xD40, bMaskDWord, 0x00000000);
1041                         odm_set_bb_reg(pDM_Odm, 0xD44, bMaskDWord, 0x00000000);
1042                         odm_set_bb_reg(pDM_Odm, 0xD48, bMaskDWord, 0x00000000);
1043                         odm_set_bb_reg(pDM_Odm, 0xD4C, bMaskDWord, 0x00180000);
1044                         odm_set_bb_reg(pDM_Odm, 0xD2C, BIT28, 0x1);                   /* enable CSI mask */
1045                         break;
1046                 default:
1047                         odm_set_bb_reg(pDM_Odm, 0xC40, BIT9, 0x0);                              /* disable notch filter */
1048                         odm_set_bb_reg(pDM_Odm, 0xD2C, BIT28, 0x0);                  /* disable CSI mask        function */
1049                         break;
1050                 } /* switch(wlan_channel)        */
1051                 return;
1052         }
1053
1054         odm_set_bb_reg(pDM_Odm, 0xC40, BIT9, 0x0);                     /* disable notch filter */
1055         odm_set_bb_reg(pDM_Odm, 0xD2C, BIT28, 0x0);                    /* disable CSI mask */
1056
1057 }
1058
1059 VOID
1060 phy_SetRegBW_8703B(
1061         IN      PADAPTER                Adapter,
1062         CHANNEL_WIDTH   CurrentBW
1063 )
1064 {
1065         u16     RegRfMod_BW, u2tmp = 0;
1066         RegRfMod_BW = rtw_read16(Adapter, REG_TRXPTCL_CTL_8703B);
1067
1068         switch (CurrentBW) {
1069         case CHANNEL_WIDTH_20:
1070                 rtw_write16(Adapter, REG_TRXPTCL_CTL_8703B, (RegRfMod_BW & 0xFE7F)); /* BIT 7 = 0, BIT 8 = 0 */
1071                 break;
1072
1073         case CHANNEL_WIDTH_40:
1074                 u2tmp = RegRfMod_BW | BIT7;
1075                 rtw_write16(Adapter, REG_TRXPTCL_CTL_8703B, (u2tmp & 0xFEFF)); /* BIT 7 = 1, BIT 8 = 0 */
1076                 break;
1077
1078         case CHANNEL_WIDTH_80:
1079                 u2tmp = RegRfMod_BW | BIT8;
1080                 rtw_write16(Adapter, REG_TRXPTCL_CTL_8703B, (u2tmp & 0xFF7F)); /* BIT 7 = 0, BIT 8 = 1 */
1081                 break;
1082
1083         default:
1084                 RTW_INFO("phy_PostSetBWMode8703B():     unknown Bandwidth: %#X\n", CurrentBW);
1085                 break;
1086         }
1087 }
1088
1089 u8
1090 phy_GetSecondaryChnl_8703B(
1091         IN      PADAPTER        Adapter
1092 )
1093 {
1094         u8      SCSettingOf40 = 0, SCSettingOf20 = 0;
1095         PHAL_DATA_TYPE  pHalData = GET_HAL_DATA(Adapter);
1096
1097         if (pHalData->current_channel_bw == CHANNEL_WIDTH_80) {
1098                 if (pHalData->nCur80MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_LOWER)
1099                         SCSettingOf40 = VHT_DATA_SC_40_LOWER_OF_80MHZ;
1100                 else if (pHalData->nCur80MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_UPPER)
1101                         SCSettingOf40 = VHT_DATA_SC_40_UPPER_OF_80MHZ;
1102
1103
1104                 if ((pHalData->nCur40MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_LOWER) && (pHalData->nCur80MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_LOWER))
1105                         SCSettingOf20 = VHT_DATA_SC_20_LOWEST_OF_80MHZ;
1106                 else if ((pHalData->nCur40MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_UPPER) && (pHalData->nCur80MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_LOWER))
1107                         SCSettingOf20 = VHT_DATA_SC_20_LOWER_OF_80MHZ;
1108                 else if ((pHalData->nCur40MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_LOWER) && (pHalData->nCur80MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_UPPER))
1109                         SCSettingOf20 = VHT_DATA_SC_20_UPPER_OF_80MHZ;
1110                 else if ((pHalData->nCur40MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_UPPER) && (pHalData->nCur80MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_UPPER))
1111                         SCSettingOf20 = VHT_DATA_SC_20_UPPERST_OF_80MHZ;
1112
1113         } else if (pHalData->current_channel_bw == CHANNEL_WIDTH_40) {
1114
1115                 if (pHalData->nCur40MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_UPPER)
1116                         SCSettingOf20 = VHT_DATA_SC_20_UPPER_OF_80MHZ;
1117                 else if (pHalData->nCur40MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_LOWER)
1118                         SCSettingOf20 = VHT_DATA_SC_20_LOWER_OF_80MHZ;
1119
1120         }
1121
1122         return (SCSettingOf40 << 4) | SCSettingOf20;
1123 }
1124
1125 VOID
1126 phy_PostSetBwMode8703B(
1127         IN      PADAPTER        Adapter
1128 )
1129 {
1130         u1Byte                  SubChnlNum = 0;
1131         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(Adapter);
1132         u1Byte                  u1TmpVal = 0;
1133
1134         /* 3 Set Reg668 Reg440 BW */
1135         phy_SetRegBW_8703B(Adapter, pHalData->current_channel_bw);
1136
1137         /* 3 Set Reg483 */
1138         SubChnlNum = phy_GetSecondaryChnl_8703B(Adapter);
1139         rtw_write8(Adapter, REG_DATA_SC_8703B, SubChnlNum);
1140
1141         /* 3 */
1142         /* 3 */ /* <2>Set PHY related register */
1143         /* 3 */
1144         switch (pHalData->current_channel_bw) {
1145         /* 20 MHz channel*/
1146         case CHANNEL_WIDTH_20:
1147                 phy_set_bb_reg(Adapter, rFPGA0_RFMOD, bRFMOD, 0x0);
1148
1149                 phy_set_bb_reg(Adapter, rFPGA1_RFMOD, bRFMOD, 0x0);
1150
1151                 /*                      phy_set_bb_reg(Adapter, rFPGA0_AnalogParameter2, BIT10, 1); */
1152
1153                 phy_set_bb_reg(Adapter, rOFDM0_TxPseudoNoiseWgt, (BIT31 | BIT30), 0x0);
1154
1155                 /* 8703B new Add */
1156                 phy_set_bb_reg(Adapter, pHalData->RegForRecover[2].offset, bMaskDWord, pHalData->RegForRecover[2].value);
1157                 phy_set_bb_reg(Adapter, pHalData->RegForRecover[3].offset, bMaskDWord, pHalData->RegForRecover[3].value);
1158                 phy_set_rf_reg(Adapter, ODM_RF_PATH_A, pHalData->RegForRecover[4].offset, bRFRegOffsetMask, pHalData->RegForRecover[4].value);
1159
1160                 break;
1161
1162
1163         /* 40 MHz channel*/
1164         case CHANNEL_WIDTH_40:
1165                 phy_set_bb_reg(Adapter, rFPGA0_RFMOD, bRFMOD, 0x1);
1166
1167                 phy_set_bb_reg(Adapter, rFPGA1_RFMOD, bRFMOD, 0x1);
1168
1169                 /* 8703B new Add*/
1170                 phy_set_bb_reg(Adapter, rBBrx_DFIR, bMaskDWord, 0x40100000);
1171                 phy_set_bb_reg(Adapter, rOFDM0_XATxAFE, bMaskDWord, 0x51F60000);
1172                 phy_set_rf_reg(Adapter, ODM_RF_PATH_A, 0x1E, bRFRegOffsetMask, 0x00C4C);
1173
1174                 /* Set Control channel to upper or lower. These settings are required only for 40MHz*/
1175                 phy_set_bb_reg(Adapter, rCCK0_System, bCCKSideBand, (pHalData->nCur40MhzPrimeSC >> 1));
1176
1177                 phy_set_bb_reg(Adapter, rOFDM1_LSTF, 0xC00, pHalData->nCur40MhzPrimeSC);
1178
1179                 phy_set_bb_reg(Adapter, 0x818, (BIT26 | BIT27), (pHalData->nCur40MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_LOWER) ? 2 : 1);
1180
1181                 u1TmpVal = rtw_read8(Adapter, REG_DATA_SC_8703B);
1182                 u1TmpVal &= 0xF0;
1183                 u1TmpVal |= ((pHalData->nCur40MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_LOWER) ? 2 : 1);
1184                 rtw_write8(Adapter, REG_DATA_SC_8703B, u1TmpVal);
1185
1186                 break;
1187
1188
1189
1190         default:
1191                 break;
1192
1193         }
1194
1195         /* 3<3>Set RF related register */
1196         PHY_RF6052SetBandwidth8703B(Adapter, pHalData->current_channel_bw);
1197 }
1198
1199 VOID
1200 phy_SwChnl8703B(
1201         IN      PADAPTER                                        pAdapter
1202 )
1203 {
1204         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(pAdapter);
1205         u8                      channelToSW = pHalData->current_channel;
1206         u8              i = 0;
1207
1208         if (pHalData->rf_chip == RF_PSEUDO_11N) {
1209                 RTW_INFO("phy_SwChnl8703B: return for PSEUDO\n");
1210                 return;
1211         }
1212
1213         pHalData->RfRegChnlVal[0] = ((pHalData->RfRegChnlVal[0] & 0xfffff00) | channelToSW);
1214         phy_set_rf_reg(pAdapter, ODM_RF_PATH_A, RF_CHNLBW, 0x3FF, pHalData->RfRegChnlVal[0]);
1215         phy_set_rf_reg(pAdapter, ODM_RF_PATH_B, RF_CHNLBW, 0x3FF, pHalData->RfRegChnlVal[0]);
1216
1217         /* BB Setting for some channels (requested by BB Neil) */
1218         switch (channelToSW) {
1219         case 14:
1220                 /*Channel 14 in CCK, need to set 0xA26~0xA29 to 0 */
1221                 phy_set_bb_reg(pAdapter, rCCK0_TxFilter2, bMaskHWord, 0);
1222                 phy_set_bb_reg(pAdapter, rCCK0_DebugPort, bMaskLWord, 0);
1223                 break;
1224         default:
1225                 /*Normal setting for 8703B, just recover to the default setting. */
1226                 /*This hardcore values refer to the parameter which BB team gave. */
1227                 for (i = 0 ; i < 2 ; ++i)
1228                         phy_set_bb_reg(pAdapter, pHalData->RegForRecover[i].offset, bMaskDWord, pHalData->RegForRecover[i].value);
1229         }
1230
1231         phy_SpurCalibration_8703B(pAdapter, channelToSW, 0x16);
1232
1233         RTW_INFO("===>phy_SwChnl8703B: Channel = %d\n", channelToSW);
1234 }
1235
1236 VOID
1237 phy_SwChnlAndSetBwMode8703B(
1238         IN  PADAPTER            Adapter
1239 )
1240 {
1241         HAL_DATA_TYPE           *pHalData = GET_HAL_DATA(Adapter);
1242
1243         if (Adapter->bNotifyChannelChange) {
1244                 RTW_INFO("[%s] bSwChnl=%d, ch=%d, bSetChnlBW=%d, bw=%d\n",
1245                          __FUNCTION__,
1246                          pHalData->bSwChnl,
1247                          pHalData->current_channel,
1248                          pHalData->bSetChnlBW,
1249                          pHalData->current_channel_bw);
1250         }
1251
1252         if (RTW_CANNOT_RUN(Adapter))
1253                 return;
1254
1255         if (pHalData->bSwChnl) {
1256                 phy_SwChnl8703B(Adapter);
1257                 pHalData->bSwChnl = _FALSE;
1258         }
1259
1260         if (pHalData->bSetChnlBW) {
1261                 phy_PostSetBwMode8703B(Adapter);
1262                 pHalData->bSetChnlBW = _FALSE;
1263         }
1264
1265         PHY_SetTxPowerLevel8703B(Adapter, pHalData->current_channel);
1266 }
1267
1268 VOID
1269 PHY_HandleSwChnlAndSetBW8703B(
1270         IN      PADAPTER                        Adapter,
1271         IN      BOOLEAN                         bSwitchChannel,
1272         IN      BOOLEAN                         bSetBandWidth,
1273         IN      u8                                      ChannelNum,
1274         IN      CHANNEL_WIDTH   ChnlWidth,
1275         IN      EXTCHNL_OFFSET  ExtChnlOffsetOf40MHz,
1276         IN      EXTCHNL_OFFSET  ExtChnlOffsetOf80MHz,
1277         IN      u8                                      CenterFrequencyIndex1
1278 )
1279 {
1280         /* static BOOLEAN               bInitialzed = _FALSE; */
1281         PHAL_DATA_TYPE          pHalData = GET_HAL_DATA(Adapter);
1282         u8                                      tmpChannel = pHalData->current_channel;
1283         CHANNEL_WIDTH   tmpBW = pHalData->current_channel_bw;
1284         u8                                      tmpnCur40MhzPrimeSC = pHalData->nCur40MhzPrimeSC;
1285         u8                                      tmpnCur80MhzPrimeSC = pHalData->nCur80MhzPrimeSC;
1286         u8                                      tmpCenterFrequencyIndex1 = pHalData->CurrentCenterFrequencyIndex1;
1287         struct mlme_ext_priv    *pmlmeext = &Adapter->mlmeextpriv;
1288
1289         /* RTW_INFO("=> PHY_HandleSwChnlAndSetBW8812: bSwitchChannel %d, bSetBandWidth %d\n",bSwitchChannel,bSetBandWidth); */
1290
1291         /* check is swchnl or setbw */
1292         if (!bSwitchChannel && !bSetBandWidth) {
1293                 RTW_INFO("PHY_HandleSwChnlAndSetBW8812:  not switch channel and not set bandwidth\n");
1294                 return;
1295         }
1296
1297         /* skip change for channel or bandwidth is the same */
1298         if (bSwitchChannel) {
1299                 /* if(pHalData->current_channel != ChannelNum) */
1300                 {
1301                         if (HAL_IsLegalChannel(Adapter, ChannelNum))
1302                                 pHalData->bSwChnl = _TRUE;
1303                 }
1304         }
1305
1306         if (bSetBandWidth) {
1307 #if 0
1308                 if (bInitialzed == _FALSE) {
1309                         bInitialzed = _TRUE;
1310                         pHalData->bSetChnlBW = _TRUE;
1311                 } else if ((pHalData->current_channel_bw != ChnlWidth) || (pHalData->nCur40MhzPrimeSC != ExtChnlOffsetOf40MHz) || (pHalData->CurrentCenterFrequencyIndex1 != CenterFrequencyIndex1))
1312                         pHalData->bSetChnlBW = _TRUE;
1313 #else
1314                 pHalData->bSetChnlBW = _TRUE;
1315 #endif
1316         }
1317
1318         if (!pHalData->bSetChnlBW && !pHalData->bSwChnl) {
1319                 /* RTW_INFO("<= PHY_HandleSwChnlAndSetBW8812: bSwChnl %d, bSetChnlBW %d\n",pHalData->bSwChnl,pHalData->bSetChnlBW); */
1320                 return;
1321         }
1322
1323
1324         if (pHalData->bSwChnl) {
1325                 pHalData->current_channel = ChannelNum;
1326                 pHalData->CurrentCenterFrequencyIndex1 = ChannelNum;
1327         }
1328
1329
1330         if (pHalData->bSetChnlBW) {
1331                 pHalData->current_channel_bw = ChnlWidth;
1332 #if 0
1333                 if (ExtChnlOffsetOf40MHz == EXTCHNL_OFFSET_LOWER)
1334                         pHalData->nCur40MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_UPPER;
1335                 else if (ExtChnlOffsetOf40MHz == EXTCHNL_OFFSET_UPPER)
1336                         pHalData->nCur40MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_LOWER;
1337                 else
1338                         pHalData->nCur40MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
1339
1340                 if (ExtChnlOffsetOf80MHz == EXTCHNL_OFFSET_LOWER)
1341                         pHalData->nCur80MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_UPPER;
1342                 else if (ExtChnlOffsetOf80MHz == EXTCHNL_OFFSET_UPPER)
1343                         pHalData->nCur80MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_LOWER;
1344                 else
1345                         pHalData->nCur80MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
1346 #else
1347                 pHalData->nCur40MhzPrimeSC = ExtChnlOffsetOf40MHz;
1348                 pHalData->nCur80MhzPrimeSC = ExtChnlOffsetOf80MHz;
1349 #endif
1350
1351                 pHalData->CurrentCenterFrequencyIndex1 = CenterFrequencyIndex1;
1352         }
1353
1354         /* Switch workitem or set timer to do switch channel or setbandwidth operation */
1355         if (!RTW_CANNOT_RUN(Adapter))
1356                 phy_SwChnlAndSetBwMode8703B(Adapter);
1357         else {
1358                 if (pHalData->bSwChnl) {
1359                         pHalData->current_channel = tmpChannel;
1360                         pHalData->CurrentCenterFrequencyIndex1 = tmpChannel;
1361                 }
1362                 if (pHalData->bSetChnlBW) {
1363                         pHalData->current_channel_bw = tmpBW;
1364                         pHalData->nCur40MhzPrimeSC = tmpnCur40MhzPrimeSC;
1365                         pHalData->nCur80MhzPrimeSC = tmpnCur80MhzPrimeSC;
1366                         pHalData->CurrentCenterFrequencyIndex1 = tmpCenterFrequencyIndex1;
1367                 }
1368         }
1369
1370         /* RTW_INFO("Channel %d ChannelBW %d ",pHalData->current_channel, pHalData->current_channel_bw); */
1371         /* RTW_INFO("40MhzPrimeSC %d 80MhzPrimeSC %d ",pHalData->nCur40MhzPrimeSC, pHalData->nCur80MhzPrimeSC); */
1372         /* RTW_INFO("CenterFrequencyIndex1 %d\n",pHalData->CurrentCenterFrequencyIndex1); */
1373
1374         /* RTW_INFO("<= PHY_HandleSwChnlAndSetBW8812: bSwChnl %d, bSetChnlBW %d\n",pHalData->bSwChnl,pHalData->bSetChnlBW); */
1375
1376 }
1377
1378 VOID
1379 PHY_SetSwChnlBWMode8703B(
1380         IN      PADAPTER                        Adapter,
1381         IN      u8                                      channel,
1382         IN      CHANNEL_WIDTH   Bandwidth,
1383         IN      u8                                      Offset40,
1384         IN      u8                                      Offset80
1385 )
1386 {
1387         /* RTW_INFO("%s()===>\n",__FUNCTION__); */
1388
1389         PHY_HandleSwChnlAndSetBW8703B(Adapter, _TRUE, _TRUE, channel, Bandwidth, Offset40, Offset80, channel);
1390
1391         /* RTW_INFO("<==%s()\n",__FUNCTION__); */
1392 }
1393
1394 static VOID
1395 _PHY_DumpRFReg_8703B(IN PADAPTER        pAdapter)
1396 {
1397         u32 rfRegValue, rfRegOffset;
1398
1399
1400         for (rfRegOffset = 0x00; rfRegOffset <= 0x30; rfRegOffset++) {
1401                 rfRegValue = PHY_QueryRFReg_8703B(pAdapter, RF_PATH_A, rfRegOffset, bMaskDWord);
1402         }
1403 }