drivers/net/wireless/rockchip_wlan/rtl8723cs/include/Hal8188EPhyCfg.h

   1 /******************************************************************************
   2  *
   3  * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of version 2 of the GNU General Public License as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program; if not, write to the Free Software Foundation, Inc.,
  16  * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  17  *
  18  *
  19  ******************************************************************************/
  20 #ifndef __INC_HAL8188EPHYCFG_H__
  21 #define __INC_HAL8188EPHYCFG_H__
  22
  23
  24 /*--------------------------Define Parameters-------------------------------*/
  25 #define LOOP_LIMIT                              5
  26 #define MAX_STALL_TIME                  50              /* us */
  27 #define AntennaDiversityValue           0x80    /* (Adapter->bSoftwareAntennaDiversity ? 0x00 : 0x80) */
  28 #define MAX_TXPWR_IDX_NMODE_92S 63
  29 #define Reset_Cnt_Limit                 3
  30
  31 #ifdef CONFIG_PCI_HCI
  32         #define MAX_AGGR_NUM    0x0B
  33 #else
  34         #define MAX_AGGR_NUM    0x07
  35 #endif /* CONFIG_PCI_HCI */
  36
  37
  38 /*--------------------------Define Parameters-------------------------------*/
  39
  40
  41 /*------------------------------Define structure----------------------------*/
  42
  43 #define MAX_TX_COUNT_8188E                      1
  44
  45 /* BB/RF related */
  46
  47
  48 /*------------------------------Define structure----------------------------*/
  49
  50
  51 /*------------------------Export global variable----------------------------*/
  52 /*------------------------Export global variable----------------------------*/
  53
  54
  55 /*------------------------Export Marco Definition---------------------------*/
  56 /*------------------------Export Marco Definition---------------------------*/
  57
  58
  59 /*--------------------------Exported Function prototype---------------------*/
  60 /*
  61  * BB and RF register read/write
  62  *   */
  63 u32     PHY_QueryBBReg8188E(IN  PADAPTER        Adapter,
  64                             IN  u32             RegAddr,
  65                             IN  u32             BitMask);
  66 void    PHY_SetBBReg8188E(IN    PADAPTER        Adapter,
  67                           IN    u32             RegAddr,
  68                           IN    u32             BitMask,
  69                           IN    u32             Data);
  70 u32     PHY_QueryRFReg8188E(IN  PADAPTER        Adapter,
  71                             IN  u8                              eRFPath,
  72                             IN  u32                             RegAddr,
  73                             IN  u32                             BitMask);
  74 void    PHY_SetRFReg8188E(IN    PADAPTER                Adapter,
  75                           IN    u8                              eRFPath,
  76                           IN    u32                             RegAddr,
  77                           IN    u32                             BitMask,
  78                           IN    u32                             Data);
  79
  80 /*
  81  * Initialization related function
  82  */
  83 /* MAC/BB/RF HAL config */
  84 int     PHY_MACConfig8188E(IN   PADAPTER        Adapter);
  85 int     PHY_BBConfig8188E(IN    PADAPTER        Adapter);
  86 int     PHY_RFConfig8188E(IN    PADAPTER        Adapter);
  87
  88 /* RF config */
  89 int     rtl8188e_PHY_ConfigRFWithParaFile(IN PADAPTER Adapter, IN u8 *pFileName, u8 eRFPath);
  90
  91 /*
  92  * RF Power setting
  93  */
  94 /* extern       BOOLEAN PHY_SetRFPowerState(IN  PADAPTER                        Adapter,
  95  *                                                                      IN      RT_RF_POWER_STATE       eRFPowerState); */
  96
  97 /*
  98  * BB TX Power R/W
  99  *   */
 100 void    PHY_GetTxPowerLevel8188E(IN     PADAPTER                Adapter,
 101                                  OUT s32                *powerlevel);
 102 void    PHY_SetTxPowerLevel8188E(IN     PADAPTER                Adapter,
 103                                  IN     u8                      channel);
 104 BOOLEAN PHY_UpdateTxPowerDbm8188E(IN    PADAPTER        Adapter,
 105                                   IN    int             powerInDbm);
 106
 107 VOID
 108 PHY_SetTxPowerIndex_8188E(
 109         IN      PADAPTER                        Adapter,
 110         IN      u32                                     PowerIndex,
 111         IN      u8                                      RFPath,
 112         IN      u8                                      Rate
 113 );
 114
 115 u8
 116 PHY_GetTxPowerIndex_8188E(
 117         IN      PADAPTER                pAdapter,
 118         IN      u8                              RFPath,
 119         IN      u8                              Rate,
 120         IN      u8                              BandWidth,
 121         IN      u8                              Channel,
 122         struct txpwr_idx_comp *tic
 123 );
 124
 125 /*
 126  * Switch bandwidth for 8192S
 127  */
 128 /* extern       void    PHY_SetBWModeCallback8192C(     IN      PRT_TIMER               pTimer  ); */
 129 void    PHY_SetBWMode8188E(IN   PADAPTER                        pAdapter,
 130                            IN   CHANNEL_WIDTH   ChnlWidth,
 131                            IN   unsigned char   Offset);
 132
 133 /*
 134  * Set FW CMD IO for 8192S.
 135  */
 136 /* extern       BOOLEAN HalSetIO8192C(  IN      PADAPTER                        Adapter,
 137  *                                                                      IN      IO_TYPE                         IOType); */
 138
 139 /*
 140  * Set A2 entry to fw for 8192S
 141  *   */
 142 extern  void FillA2Entry8192C(IN        PADAPTER                        Adapter,
 143                               IN        u8                              index,
 144                               IN        u8                              *val);
 145
 146
 147 /*
 148  * channel switch related funciton
 149  */
 150 /* extern       void    PHY_SwChnlCallback8192C(        IN      PRT_TIMER               pTimer  ); */
 151 void    PHY_SwChnl8188E(IN      PADAPTER                pAdapter,
 152                         IN      u8                      channel);
 153
 154 VOID
 155 PHY_SetSwChnlBWMode8188E(
 156         IN      PADAPTER                        Adapter,
 157         IN      u8                                      channel,
 158         IN      CHANNEL_WIDTH   Bandwidth,
 159         IN      u8                                      Offset40,
 160         IN      u8                                      Offset80
 161 );
 162
 163 VOID
 164 PHY_SetRFEReg_8188E(
 165         IN PADAPTER             Adapter
 166 );
 167 /*
 168  * BB/MAC/RF other monitor API
 169  *   */
 170 VOID phy_set_rf_path_switch_8188e(IN    PADAPTER        pAdapter, IN    bool            bMain);
 171
 172 extern  VOID
 173 PHY_SwitchEphyParameter(
 174         IN      PADAPTER                        Adapter
 175 );
 176
 177 extern  VOID
 178 PHY_EnableHostClkReq(
 179         IN      PADAPTER                        Adapter
 180 );
 181
 182 BOOLEAN
 183 SetAntennaConfig92C(
 184         IN      PADAPTER        Adapter,
 185         IN      u8              DefaultAnt
 186 );
 187
 188 /*--------------------------Exported Function prototype---------------------*/
 189
 190 /*
 191  * Initialization related function
 192  *
 193  * MAC/BB/RF HAL config */
 194 /* extern s32 PHY_MACConfig8723(PADAPTER padapter);
 195  * s32 PHY_BBConfig8723(PADAPTER padapter);
 196  * s32 PHY_RFConfig8723(PADAPTER padapter); */
 197
 198
 199
 200 /* ******************************************************************
 201  * Note: If SIC_ENABLE under PCIE, because of the slow operation
 202  *      you should
 203  *      2) "#define RTL8723_FPGA_VERIFICATION   1"                              in Precomp.h.WlanE.Windows
 204  *      3) "#define RTL8190_Download_Firmware_From_Header       0"      in Precomp.h.WlanE.Windows if needed.
 205  *   */
 206 #if (RTL8188E_SUPPORT == 1) && (RTL8188E_FPGA_TRUE_PHY_VERIFICATION == 1)
 207         #define SIC_ENABLE                              1
 208         #define SIC_HW_SUPPORT          1
 209 #else
 210         #define SIC_ENABLE                              0
 211         #define SIC_HW_SUPPORT          0
 212 #endif
 213 /* ****************************************************************** */
 214
 215
 216 #define SIC_MAX_POLL_CNT                5
 217
 218 #if (SIC_HW_SUPPORT == 1)
 219         #define SIC_CMD_READY                   0
 220         #define SIC_CMD_PREWRITE                0x1
 221         #if (RTL8188E_SUPPORT == 1)
 222                 #define SIC_CMD_WRITE                   0x40
 223                 #define SIC_CMD_PREREAD         0x2
 224                 #define SIC_CMD_READ                    0x80
 225                 #define SIC_CMD_INIT                    0xf0
 226                 #define SIC_INIT_VAL                    0xff
 227
 228                 #define SIC_INIT_REG                    0x1b7
 229                 #define SIC_CMD_REG                     0x1EB           /* 1byte */
 230                 #define SIC_ADDR_REG                    0x1E8           /* 1b4~1b5, 2 bytes */
 231                 #define SIC_DATA_REG                    0x1EC           /* 1b0~1b3 */
 232         #else
 233                 #define SIC_CMD_WRITE                   0x11
 234                 #define SIC_CMD_PREREAD         0x2
 235                 #define SIC_CMD_READ                    0x12
 236                 #define SIC_CMD_INIT                    0x1f
 237                 #define SIC_INIT_VAL                    0xff
 238
 239                 #define SIC_INIT_REG                    0x1b7
 240                 #define SIC_CMD_REG                     0x1b6           /* 1byte */
 241                 #define SIC_ADDR_REG                    0x1b4           /* 1b4~1b5, 2 bytes */
 242                 #define SIC_DATA_REG                    0x1b0           /* 1b0~1b3 */
 243         #endif
 244 #else
 245         #define SIC_CMD_READY                   0
 246         #define SIC_CMD_WRITE                   1
 247         #define SIC_CMD_READ                    2
 248
 249         #if (RTL8188E_SUPPORT == 1)
 250                 #define SIC_CMD_REG                     0x1EB           /* 1byte */
 251                 #define SIC_ADDR_REG                    0x1E8           /* 1b9~1ba, 2 bytes */
 252                 #define SIC_DATA_REG                    0x1EC           /* 1bc~1bf */
 253         #else
 254                 #define SIC_CMD_REG                     0x1b8           /* 1byte */
 255                 #define SIC_ADDR_REG                    0x1b9           /* 1b9~1ba, 2 bytes */
 256                 #define SIC_DATA_REG                    0x1bc           /* 1bc~1bf */
 257         #endif
 258 #endif
 259
 260 #if (SIC_ENABLE == 1)
 261         VOID SIC_Init(IN PADAPTER Adapter);
 262 #endif
 263
 264
 265 #endif /* __INC_HAL8192CPHYCFG_H */