1 /******************************************************************************
3 * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
19 ******************************************************************************/
20 #ifndef __INC_HAL8188FPHYREG_H__
21 #define __INC_HAL8188FPHYREG_H__
23 /*--------------------------Define Parameters-------------------------------*/
25 /* ************************************************************
26 * Regsiter offset definition
27 * ************************************************************ */
30 * BB-PHY register PMAC 0x100 PHY 0x800 - 0xEFF
31 * 1. PMAC duplicate register due to connection: RF_Mode, TRxRN, NumOf L-STF
32 * 2. 0x800/0x900/0xA00/0xC00/0xD00/0xE00
33 * 3. RF register 0x00-2E
34 * 4. Bit Mask for BB/RF register
35 * 5. Other defintion for BB/RF R/W
40 * 1. PMAC duplicate register due to connection: RF_Mode, TRxRN, NumOf L-STF
43 #define rPMAC_Reset 0x100
44 #define rPMAC_TxStart 0x104
45 #define rPMAC_TxLegacySIG 0x108
46 #define rPMAC_TxHTSIG1 0x10c
47 #define rPMAC_TxHTSIG2 0x110
48 #define rPMAC_PHYDebug 0x114
49 #define rPMAC_TxPacketNum 0x118
50 #define rPMAC_TxIdle 0x11c
51 #define rPMAC_TxMACHeader0 0x120
52 #define rPMAC_TxMACHeader1 0x124
53 #define rPMAC_TxMACHeader2 0x128
54 #define rPMAC_TxMACHeader3 0x12c
55 #define rPMAC_TxMACHeader4 0x130
56 #define rPMAC_TxMACHeader5 0x134
57 #define rPMAC_TxDataType 0x138
58 #define rPMAC_TxRandomSeed 0x13c
59 #define rPMAC_CCKPLCPPreamble 0x140
60 #define rPMAC_CCKPLCPHeader 0x144
61 #define rPMAC_CCKCRC16 0x148
62 #define rPMAC_OFDMRxCRC32OK 0x170
63 #define rPMAC_OFDMRxCRC32Er 0x174
64 #define rPMAC_OFDMRxParityEr 0x178
65 #define rPMAC_OFDMRxCRC8Er 0x17c
66 #define rPMAC_CCKCRxRC16Er 0x180
67 #define rPMAC_CCKCRxRC32Er 0x184
68 #define rPMAC_CCKCRxRC32OK 0x188
69 #define rPMAC_TxStatus 0x18c
74 * The following two definition are only used for USB interface. */
75 #define RF_BB_CMD_ADDR 0x02c0 /* RF/BB read/write command address. */
76 #define RF_BB_CMD_DATA 0x02c4 /* RF/BB read/write command data. */
81 #define rFPGA0_RFMOD 0x800 /* RF mode & CCK TxSC */ /* RF BW Setting?? */
83 #define rFPGA0_TxInfo 0x804 /* Status report?? */
84 #define rFPGA0_PSDFunction 0x808
86 #define rFPGA0_TxGainStage 0x80c /* Set TX PWR init gain? */
88 #define rFPGA0_RFTiming1 0x810 /* Useless now */
89 #define rFPGA0_RFTiming2 0x814
91 #define rFPGA0_XA_HSSIParameter1 0x820 /* RF 3 wire register */
92 #define rFPGA0_XA_HSSIParameter2 0x824
93 #define rFPGA0_XB_HSSIParameter1 0x828
94 #define rFPGA0_XB_HSSIParameter2 0x82c
95 #define rTxAGC_B_Rate18_06 0x830
96 #define rTxAGC_B_Rate54_24 0x834
97 #define rTxAGC_B_CCK1_55_Mcs32 0x838
98 #define rTxAGC_B_Mcs03_Mcs00 0x83c
100 #define rTxAGC_B_Mcs07_Mcs04 0x848
101 #define rTxAGC_B_Mcs11_Mcs08 0x84c
103 #define rFPGA0_XA_LSSIParameter 0x840
104 #define rFPGA0_XB_LSSIParameter 0x844
106 #define rFPGA0_RFWakeUpParameter 0x850 /* Useless now */
107 #define rFPGA0_RFSleepUpParameter 0x854
109 #define rFPGA0_XAB_SwitchControl 0x858 /* RF Channel switch */
110 #define rFPGA0_XCD_SwitchControl 0x85c
112 #define rFPGA0_XA_RFInterfaceOE 0x860 /* RF Channel switch */
113 #define rFPGA0_XB_RFInterfaceOE 0x864
115 #define rTxAGC_B_Mcs15_Mcs12 0x868
116 #define rTxAGC_B_CCK11_A_CCK2_11 0x86c
118 #define rFPGA0_XAB_RFInterfaceSW 0x870 /* RF Interface Software Control */
119 #define rFPGA0_XCD_RFInterfaceSW 0x874
121 #define rFPGA0_XAB_RFParameter 0x878 /* RF Parameter */
122 #define rFPGA0_XCD_RFParameter 0x87c
124 #define rFPGA0_AnalogParameter1 0x880 /* Crystal cap setting RF-R/W protection for parameter4?? */
125 #define rFPGA0_AnalogParameter2 0x884
126 #define rFPGA0_AnalogParameter3 0x888 /* Useless now */
127 #define rFPGA0_AnalogParameter4 0x88c
129 #define rFPGA0_XA_LSSIReadBack 0x8a0 /* Tranceiver LSSI Readback */
130 #define rFPGA0_XB_LSSIReadBack 0x8a4
131 #define rFPGA0_XC_LSSIReadBack 0x8a8
132 #define rFPGA0_XD_LSSIReadBack 0x8ac
134 #define rFPGA0_PSDReport 0x8b4 /* Useless now */
135 #define TransceiverA_HSPI_Readback 0x8b8 /* Transceiver A HSPI Readback */
136 #define TransceiverB_HSPI_Readback 0x8bc /* Transceiver B HSPI Readback */
137 #define rFPGA0_XAB_RFInterfaceRB 0x8e0 /* Useless now */ /* RF Interface Readback Value */
138 #define rFPGA0_XCD_RFInterfaceRB 0x8e4 /* Useless now */
143 #define rFPGA1_RFMOD 0x900 /* RF mode & OFDM TxSC */ /* RF BW Setting?? */
145 #define rFPGA1_TxBlock 0x904 /* Useless now */
146 #define rFPGA1_DebugSelect 0x908 /* Useless now */
147 #define rFPGA1_TxInfo 0x90c /* Useless now */ /* Status report?? */
148 #define rS0S1_PathSwitch 0x948
153 * Set Control channel to upper or lower. These settings are required only for 40MHz */
154 #define rCCK0_System 0xa00
156 #define rCCK0_AFESetting 0xa04 /* Disable init gain now */ /* Select RX path by RSSI */
157 #define rCCK0_CCA 0xa08 /* Disable init gain now */ /* Init gain */
159 #define rCCK0_RxAGC1 0xa0c /* AGC default value, saturation level */ /* Antenna Diversity, RX AGC, LNA Threshold, RX LNA Threshold useless now. Not the same as 90 series */
160 #define rCCK0_RxAGC2 0xa10 /* AGC & DAGC */
162 #define rCCK0_RxHP 0xa14
164 #define rCCK0_DSPParameter1 0xa18 /* Timing recovery & Channel estimation threshold */
165 #define rCCK0_DSPParameter2 0xa1c /* SQ threshold */
167 #define rCCK0_TxFilter1 0xa20
168 #define rCCK0_TxFilter2 0xa24
169 #define rCCK0_DebugPort 0xa28 /* debug port and Tx filter3 */
170 #define rCCK0_FalseAlarmReport 0xa2c /* 0xa2d useless now 0xa30-a4f channel report */
171 #define rCCK0_TRSSIReport 0xa50
172 #define rCCK0_RxReport 0xa54 /* 0xa57 */
173 #define rCCK0_FACounterLower 0xa5c /* 0xa5b */
174 #define rCCK0_FACounterUpper 0xa58 /* 0xa5c
178 #define rPdp_AntA 0xb00
179 #define rPdp_AntA_4 0xb04
180 #define rConfig_Pmpd_AntA 0xb28
181 #define rConfig_AntA 0xb68
182 #define rConfig_AntB 0xb6c
183 #define rPdp_AntB 0xb70
184 #define rPdp_AntB_4 0xb74
185 #define rConfig_Pmpd_AntB 0xb98
191 #define rOFDM0_LSTF 0xc00
193 #define rOFDM0_TRxPathEnable 0xc04
194 #define rOFDM0_TRMuxPar 0xc08
195 #define rOFDM0_TRSWIsolation 0xc0c
197 #define rOFDM0_XARxAFE 0xc10 /* RxIQ DC offset, Rx digital filter, DC notch filter */
198 #define rOFDM0_XARxIQImbalance 0xc14 /* RxIQ imblance matrix */
199 #define rOFDM0_XBRxAFE 0xc18
200 #define rOFDM0_XBRxIQImbalance 0xc1c
201 #define rOFDM0_XCRxAFE 0xc20
202 #define rOFDM0_XCRxIQImbalance 0xc24
203 #define rOFDM0_XDRxAFE 0xc28
204 #define rOFDM0_XDRxIQImbalance 0xc2c
206 #define rOFDM0_RxDetector1 0xc30 /* PD, BW & SBD */ /* DM tune init gain */
207 #define rOFDM0_RxDetector2 0xc34 /* SBD & Fame Sync. */
208 #define rOFDM0_RxDetector3 0xc38 /* Frame Sync. */
209 #define rOFDM0_RxDetector4 0xc3c /* PD, SBD, Frame Sync & Short-GI */
211 #define rOFDM0_RxDSP 0xc40 /* Rx Sync Path */
212 #define rOFDM0_CFOandDAGC 0xc44 /* CFO & DAGC */
213 #define rOFDM0_CCADropThreshold 0xc48 /* CCA Drop threshold */
214 #define rOFDM0_ECCAThreshold 0xc4c /* energy CCA */
216 #define rOFDM0_XAAGCCore1 0xc50 /* DIG */
217 #define rOFDM0_XAAGCCore2 0xc54
218 #define rOFDM0_XBAGCCore1 0xc58
219 #define rOFDM0_XBAGCCore2 0xc5c
220 #define rOFDM0_XCAGCCore1 0xc60
221 #define rOFDM0_XCAGCCore2 0xc64
222 #define rOFDM0_XDAGCCore1 0xc68
223 #define rOFDM0_XDAGCCore2 0xc6c
225 #define rOFDM0_AGCParameter1 0xc70
226 #define rOFDM0_AGCParameter2 0xc74
227 #define rOFDM0_AGCRSSITable 0xc78
228 #define rOFDM0_HTSTFAGC 0xc7c
230 #define rOFDM0_XATxIQImbalance 0xc80 /* TX PWR TRACK and DIG */
231 #define rOFDM0_XATxAFE 0xc84
232 #define rOFDM0_XBTxIQImbalance 0xc88
233 #define rOFDM0_XBTxAFE 0xc8c
234 #define rOFDM0_XCTxIQImbalance 0xc90
235 #define rOFDM0_XCTxAFE 0xc94
236 #define rOFDM0_XDTxIQImbalance 0xc98
237 #define rOFDM0_XDTxAFE 0xc9c
239 #define rOFDM0_RxIQExtAnta 0xca0
240 #define rOFDM0_TxCoeff1 0xca4
241 #define rOFDM0_TxCoeff2 0xca8
242 #define rOFDM0_TxCoeff3 0xcac
243 #define rOFDM0_TxCoeff4 0xcb0
244 #define rOFDM0_TxCoeff5 0xcb4
245 #define rOFDM0_TxCoeff6 0xcb8
246 #define rOFDM0_RxHPParameter 0xce0
247 #define rOFDM0_TxPseudoNoiseWgt 0xce4
248 #define rOFDM0_FrameSync 0xcf0
249 #define rOFDM0_DFSReport 0xcf4
254 #define rOFDM1_LSTF 0xd00
255 #define rOFDM1_TRxPathEnable 0xd04
257 #define rOFDM1_CFO 0xd08 /* No setting now */
258 #define rOFDM1_CSI1 0xd10
259 #define rOFDM1_SBD 0xd14
260 #define rOFDM1_CSI2 0xd18
261 #define rOFDM1_CFOTracking 0xd2c
262 #define rOFDM1_TRxMesaure1 0xd34
263 #define rOFDM1_IntfDet 0xd3c
264 #define rOFDM1_PseudoNoiseStateAB 0xd50
265 #define rOFDM1_PseudoNoiseStateCD 0xd54
266 #define rOFDM1_RxPseudoNoiseWgt 0xd58
268 #define rOFDM_PHYCounter1 0xda0 /* cca, parity fail */
269 #define rOFDM_PHYCounter2 0xda4 /* rate illegal, crc8 fail */
270 #define rOFDM_PHYCounter3 0xda8 /* MCS not support */
272 #define rOFDM_ShortCFOAB 0xdac /* No setting now */
273 #define rOFDM_ShortCFOCD 0xdb0
274 #define rOFDM_LongCFOAB 0xdb4
275 #define rOFDM_LongCFOCD 0xdb8
276 #define rOFDM_TailCFOAB 0xdbc
277 #define rOFDM_TailCFOCD 0xdc0
278 #define rOFDM_PWMeasure1 0xdc4
279 #define rOFDM_PWMeasure2 0xdc8
280 #define rOFDM_BWReport 0xdcc
281 #define rOFDM_AGCReport 0xdd0
282 #define rOFDM_RxSNR 0xdd4
283 #define rOFDM_RxEVMCSI 0xdd8
284 #define rOFDM_SIGReport 0xddc
290 #define rTxAGC_A_Rate18_06 0xe00
291 #define rTxAGC_A_Rate54_24 0xe04
292 #define rTxAGC_A_CCK1_Mcs32 0xe08
293 #define rTxAGC_A_Mcs03_Mcs00 0xe10
294 #define rTxAGC_A_Mcs07_Mcs04 0xe14
295 #define rTxAGC_A_Mcs11_Mcs08 0xe18
296 #define rTxAGC_A_Mcs15_Mcs12 0xe1c
298 #define rFPGA0_IQK 0xe28
299 #define rTx_IQK_Tone_A 0xe30
300 #define rRx_IQK_Tone_A 0xe34
301 #define rTx_IQK_PI_A 0xe38
302 #define rRx_IQK_PI_A 0xe3c
304 #define rTx_IQK 0xe40
305 #define rRx_IQK 0xe44
306 #define rIQK_AGC_Pts 0xe48
307 #define rIQK_AGC_Rsp 0xe4c
308 #define rTx_IQK_Tone_B 0xe50
309 #define rRx_IQK_Tone_B 0xe54
310 #define rTx_IQK_PI_B 0xe58
311 #define rRx_IQK_PI_B 0xe5c
312 #define rIQK_AGC_Cont 0xe60
314 #define rBlue_Tooth 0xe6c
315 #define rRx_Wait_CCA 0xe70
316 #define rTx_CCK_RFON 0xe74
317 #define rTx_CCK_BBON 0xe78
318 #define rTx_OFDM_RFON 0xe7c
319 #define rTx_OFDM_BBON 0xe80
320 #define rTx_To_Rx 0xe84
321 #define rTx_To_Tx 0xe88
322 #define rRx_CCK 0xe8c
324 #define rTx_Power_Before_IQK_A 0xe94
325 #define rTx_Power_After_IQK_A 0xe9c
327 #define rRx_Power_Before_IQK_A 0xea0
328 #define rRx_Power_Before_IQK_A_2 0xea4
329 #define rRx_Power_After_IQK_A 0xea8
330 #define rRx_Power_After_IQK_A_2 0xeac
332 #define rTx_Power_Before_IQK_B 0xeb4
333 #define rTx_Power_After_IQK_B 0xebc
335 #define rRx_Power_Before_IQK_B 0xec0
336 #define rRx_Power_Before_IQK_B_2 0xec4
337 #define rRx_Power_After_IQK_B 0xec8
338 #define rRx_Power_After_IQK_B_2 0xecc
340 #define rRx_OFDM 0xed0
341 #define rRx_Wait_RIFS 0xed4
342 #define rRx_TO_Rx 0xed8
343 #define rStandby 0xedc
345 #define rPMPD_ANAEN 0xeec
348 * 7. RF Register 0x00-0x2E (RF 8256)
352 #define rZebra1_HSSIEnable 0x0 /* Useless now */
353 #define rZebra1_TRxEnable1 0x1
354 #define rZebra1_TRxEnable2 0x2
355 #define rZebra1_AGC 0x4
356 #define rZebra1_ChargePump 0x5
357 #define rZebra1_Channel 0x7 /* RF channel switch */
360 #define rZebra1_TxGain 0x8 /* Useless now */
361 #define rZebra1_TxLPF 0x9
362 #define rZebra1_RxLPF 0xb
363 #define rZebra1_RxHPFCorner 0xc
366 #define rGlobalCtrl 0 /* Useless now */
367 #define rRTL8256_TxLPF 19
368 #define rRTL8256_RxLPF 11
371 #define rRTL8258_TxLPF 0x11 /* Useless now */
372 #define rRTL8258_RxLPF 0x13
373 #define rRTL8258_RSSILPF 0xa
376 * RL6052 Register definition
378 #define RF_AC 0x00 /* */
380 #define RF_IQADJ_G1 0x01 /* */
381 #define RF_IQADJ_G2 0x02 /* */
382 #define RF_BS_PA_APSET_G1_G4 0x03
383 #define RF_BS_PA_APSET_G5_G8 0x04
384 #define RF_POW_TRSW 0x05 /* */
386 #define RF_GAIN_RX 0x06 /* */
387 #define RF_GAIN_TX 0x07 /* */
389 #define RF_TXM_IDAC 0x08 /* */
390 #define RF_IPA_G 0x09 /* */
391 #define RF_TXBIAS_G 0x0A
392 #define RF_TXPA_AG 0x0B
393 #define RF_IPA_A 0x0C /* */
394 #define RF_TXBIAS_A 0x0D
395 #define RF_BS_PA_APSET_G9_G11 0x0E
396 #define RF_BS_IQGEN 0x0F /* */
398 #define RF_MODE1 0x10 /* */
399 #define RF_MODE2 0x11 /* */
401 #define RF_RX_AGC_HP 0x12 /* */
402 #define RF_TX_AGC 0x13 /* */
403 #define RF_BIAS 0x14 /* */
404 #define RF_IPA 0x15 /* */
405 #define RF_TXBIAS 0x16
406 #define RF_POW_ABILITY 0x17 /* */
407 #define RF_MODE_AG 0x18 /* */
408 #define rRfChannel 0x18 /* RF channel and BW switch */
409 #define RF_CHNLBW 0x18 /* RF channel and BW switch */
410 #define RF_TOP 0x19 /* */
412 #define RF_RX_G1 0x1A /* */
413 #define RF_RX_G2 0x1B /* */
415 #define RF_RX_BB2 0x1C /* */
416 #define RF_RX_BB1 0x1D /* */
418 #define RF_RCK1 0x1E /* */
419 #define RF_RCK2 0x1F /* */
421 #define RF_TX_G1 0x20 /* */
422 #define RF_TX_G2 0x21 /* */
423 #define RF_TX_G3 0x22 /* */
425 #define RF_TX_BB1 0x23 /* */
427 #define RF_T_METER 0x24 /* */
429 #define RF_SYN_G1 0x25 /* RF TX Power control */
430 #define RF_SYN_G2 0x26 /* RF TX Power control */
431 #define RF_SYN_G3 0x27 /* RF TX Power control */
432 #define RF_SYN_G4 0x28 /* RF TX Power control */
433 #define RF_SYN_G5 0x29 /* RF TX Power control */
434 #define RF_SYN_G6 0x2A /* RF TX Power control */
435 #define RF_SYN_G7 0x2B /* RF TX Power control */
436 #define RF_SYN_G8 0x2C /* RF TX Power control */
438 #define RF_RCK_OS 0x30 /* RF TX PA control */
440 #define RF_TXPA_G1 0x31 /* RF TX PA control */
441 #define RF_TXPA_G2 0x32 /* RF TX PA control */
442 #define RF_TXPA_G3 0x33 /* RF TX PA control */
443 #define RF_TX_BIAS_A 0x35
444 #define RF_TX_BIAS_D 0x36
445 #define RF_LOBF_9 0x38
446 #define RF_RXRF_A3 0x3C /* */
449 #define RF_TXRF_A2 0x41
450 #define RF_TXPA_G4 0x46
451 #define RF_TXPA_A4 0x4B
453 #define RF_RXG_MIX_SWBW 0x87
454 #define RF_DBG_LP_RX2 0xDF
455 #define RF_WE_LUT 0xEF
458 #define RF_TX_GAIN_OFFSET_8188F(_val) (abs((_val)) | (((_val) > 0) ? BIT5 : 0))
464 #define bBBResetB 0x100 /* Useless now? */
465 #define bGlobalResetB 0x200
466 #define bOFDMTxStart 0x4
467 #define bCCKTxStart 0x8
468 #define bCRC32Debug 0x100
469 #define bPMACLoopback 0x10
470 #define bTxLSIG 0xffffff
471 #define bOFDMTxRate 0xf
472 #define bOFDMTxReserved 0x10
473 #define bOFDMTxLength 0x1ffe0
474 #define bOFDMTxParity 0x20000
475 #define bTxHTSIG1 0xffffff
476 #define bTxHTMCSRate 0x7f
478 #define bTxHTLength 0xffff00
479 #define bTxHTSIG2 0xffffff
480 #define bTxHTSmoothing 0x1
481 #define bTxHTSounding 0x2
482 #define bTxHTReserved 0x4
483 #define bTxHTAggreation 0x8
484 #define bTxHTSTBC 0x30
485 #define bTxHTAdvanceCoding 0x40
486 #define bTxHTShortGI 0x80
487 #define bTxHTNumberHT_LTF 0x300
488 #define bTxHTCRC8 0x3fc00
489 #define bCounterReset 0x10000
490 #define bNumOfOFDMTx 0xffff
491 #define bNumOfCCKTx 0xffff0000
492 #define bTxIdleInterval 0xffff
493 #define bOFDMService 0xffff0000
494 #define bTxMACHeader 0xffffffff
495 #define bTxDataInit 0xff
496 #define bTxHTMode 0x100
497 #define bTxDataType 0x30000
498 #define bTxRandomSeed 0xffffffff
499 #define bCCKTxPreamble 0x1
500 #define bCCKTxSFD 0xffff0000
501 #define bCCKTxSIG 0xff
502 #define bCCKTxService 0xff00
503 #define bCCKLengthExt 0x8000
504 #define bCCKTxLength 0xffff0000
505 #define bCCKTxCRC16 0xffff
506 #define bCCKTxStatus 0x1
507 #define bOFDMTxStatus 0x2
509 #define IS_BB_REG_OFFSET_92S(_Offset) ((_Offset >= 0x800) && (_Offset <= 0xfff))
511 /* 2. Page8(0x800) */
512 #define bRFMOD 0x1 /* Reg 0x800 rFPGA0_RFMOD */
513 #define bJapanMode 0x2
514 #define bCCKTxSC 0x30
515 #define bCCKEn 0x1000000
516 #define bOFDMEn 0x2000000
518 #define bOFDMRxADCPhase 0x10000 /* Useless now */
519 #define bOFDMTxDACPhase 0x40000
520 #define bXATxAGC 0x3f
522 #define bAntennaSelect 0x0300
524 #define bXBTxAGC 0xf00 /* Reg 80c rFPGA0_TxGainStage */
525 #define bXCTxAGC 0xf000
526 #define bXDTxAGC 0xf0000
528 #define bPAStart 0xf0000000 /* Useless now */
529 #define bTRStart 0x00f00000
530 #define bRFStart 0x0000f000
531 #define bBBStart 0x000000f0
532 #define bBBCCKStart 0x0000000f
533 #define bPAEnd 0xf /* Reg0x814 */
534 #define bTREnd 0x0f000000
535 #define bRFEnd 0x000f0000
536 #define bCCAMask 0x000000f0 /* T2R */
537 #define bR2RCCAMask 0x00000f00
538 #define bHSSI_R2TDelay 0xf8000000
539 #define bHSSI_T2RDelay 0xf80000
540 #define bContTxHSSI 0x400 /* chane gain at continue Tx */
541 #define bIGFromCCK 0x200
542 #define bAGCAddress 0x3f
543 #define bRxHPTx 0x7000
544 #define bRxHPT2R 0x38000
545 #define bRxHPCCKIni 0xc0000
546 #define bAGCTxCode 0xc00000
547 #define bAGCRxCode 0x300000
549 #define b3WireDataLength 0x800 /* Reg 0x820~84f rFPGA0_XA_HSSIParameter1 */
550 #define b3WireAddressLength 0x400
552 #define b3WireRFPowerDown 0x1 /* Useless now
553 * #define bHWSISelect 0x8 */
554 #define b5GPAPEPolarity 0x40000000
555 #define b2GPAPEPolarity 0x80000000
556 #define bRFSW_TxDefaultAnt 0x3
557 #define bRFSW_TxOptionAnt 0x30
558 #define bRFSW_RxDefaultAnt 0x300
559 #define bRFSW_RxOptionAnt 0x3000
560 #define bRFSI_3WireData 0x1
561 #define bRFSI_3WireClock 0x2
562 #define bRFSI_3WireLoad 0x4
563 #define bRFSI_3WireRW 0x8
564 #define bRFSI_3Wire 0xf
566 #define bRFSI_RFENV 0x10 /* Reg 0x870 rFPGA0_XAB_RFInterfaceSW */
568 #define bRFSI_TRSW 0x20 /* Useless now */
569 #define bRFSI_TRSWB 0x40
570 #define bRFSI_ANTSW 0x100
571 #define bRFSI_ANTSWB 0x200
572 #define bRFSI_PAPE 0x400
573 #define bRFSI_PAPE5G 0x800
574 #define bBandSelect 0x1
575 #define bHTSIG2_GI 0x80
576 #define bHTSIG2_Smoothing 0x01
577 #define bHTSIG2_Sounding 0x02
578 #define bHTSIG2_Aggreaton 0x08
579 #define bHTSIG2_STBC 0x30
580 #define bHTSIG2_AdvCoding 0x40
581 #define bHTSIG2_NumOfHTLTF 0x300
582 #define bHTSIG2_CRC8 0x3fc
583 #define bHTSIG1_MCS 0x7f
584 #define bHTSIG1_BandWidth 0x80
585 #define bHTSIG1_HTLength 0xffff
586 #define bLSIG_Rate 0xf
587 #define bLSIG_Reserved 0x10
588 #define bLSIG_Length 0x1fffe
589 #define bLSIG_Parity 0x20
590 #define bCCKRxPhase 0x4
592 #define bLSSIReadAddress 0x7f800000 /* T65 RF */
594 #define bLSSIReadEdge 0x80000000 /* LSSI "Read" edge signal */
596 #define bLSSIReadBackData 0xfffff /* T65 RF */
598 #define bLSSIReadOKFlag 0x1000 /* Useless now */
599 #define bCCKSampleRate 0x8 /* 0: 44MHz, 1:88MHz */
600 #define bRegulator0Standby 0x1
601 #define bRegulatorPLLStandby 0x2
602 #define bRegulator1Standby 0x4
603 #define bPLLPowerUp 0x8
604 #define bDPLLPowerUp 0x10
605 #define bDA10PowerUp 0x20
606 #define bAD7PowerUp 0x200
607 #define bDA6PowerUp 0x2000
608 #define bXtalPowerUp 0x4000
609 #define b40MDClkPowerUP 0x8000
610 #define bDA6DebugMode 0x20000
611 #define bDA6Swing 0x380000
613 #define bADClkPhase 0x4000000 /* Reg 0x880 rFPGA0_AnalogParameter1 20/40 CCK support switch 40/80 BB MHZ */
615 #define b80MClkDelay 0x18000000 /* Useless */
616 #define bAFEWatchDogEnable 0x20000000
618 #define bXtalCap01 0xc0000000 /* Reg 0x884 rFPGA0_AnalogParameter2 Crystal cap */
619 #define bXtalCap23 0x3
620 #define bXtalCap92x 0x0f000000
621 #define bXtalCap 0x0f000000
623 #define bIntDifClkEnable 0x400 /* Useless */
624 #define bExtSigClkEnable 0x800
625 #define bBandgapMbiasPowerUp 0x10000
626 #define bAD11SHGain 0xc0000
627 #define bAD11InputRange 0x700000
628 #define bAD11OPCurrent 0x3800000
629 #define bIPathLoopback 0x4000000
630 #define bQPathLoopback 0x8000000
631 #define bAFELoopback 0x10000000
632 #define bDA10Swing 0x7e0
633 #define bDA10Reverse 0x800
634 #define bDAClkSource 0x1000
635 #define bAD7InputRange 0x6000
636 #define bAD7Gain 0x38000
637 #define bAD7OutputCMMode 0x40000
638 #define bAD7InputCMMode 0x380000
639 #define bAD7Current 0xc00000
640 #define bRegulatorAdjust 0x7000000
641 #define bAD11PowerUpAtTx 0x1
642 #define bDA10PSAtTx 0x10
643 #define bAD11PowerUpAtRx 0x100
644 #define bDA10PSAtRx 0x1000
645 #define bCCKRxAGCFormat 0x200
646 #define bPSDFFTSamplepPoint 0xc000
647 #define bPSDAverageNum 0x3000
648 #define bIQPathControl 0xc00
649 #define bPSDFreq 0x3ff
650 #define bPSDAntennaPath 0x30
651 #define bPSDIQSwitch 0x40
652 #define bPSDRxTrigger 0x400000
653 #define bPSDTxTrigger 0x80000000
654 #define bPSDSineToneScale 0x7f000000
655 #define bPSDReport 0xffff
657 /* 3. Page9(0x900) */
658 #define bOFDMTxSC 0x30000000 /* Useless */
660 #define bOFDMTxOn 0x2
661 #define bDebugPage 0xfff /* reset debug page and also HWord, LWord */
662 #define bDebugItem 0xff /* reset debug page and LWord */
664 #define bAntNonHT 0x100
665 #define bAntHT1 0x1000
666 #define bAntHT2 0x10000
667 #define bAntHT1S1 0x100000
668 #define bAntNonHTS1 0x1000000
670 /* 4. PageA(0xA00) */
671 #define bCCKBBMode 0x3 /* Useless */
672 #define bCCKTxPowerSaving 0x80
673 #define bCCKRxPowerSaving 0x40
675 #define bCCKSideBand 0x10 /* Reg 0xa00 rCCK0_System 20/40 switch */
677 #define bCCKScramble 0x8 /* Useless */
678 #define bCCKAntDiversity 0x8000
679 #define bCCKCarrierRecovery 0x4000
680 #define bCCKTxRate 0x3000
681 #define bCCKDCCancel 0x0800
682 #define bCCKISICancel 0x0400
683 #define bCCKMatchFilter 0x0200
684 #define bCCKEqualizer 0x0100
685 #define bCCKPreambleDetect 0x800000
686 #define bCCKFastFalseCCA 0x400000
687 #define bCCKChEstStart 0x300000
688 #define bCCKCCACount 0x080000
689 #define bCCKcs_lim 0x070000
690 #define bCCKBistMode 0x80000000
691 #define bCCKCCAMask 0x40000000
692 #define bCCKTxDACPhase 0x4
693 #define bCCKRxADCPhase 0x20000000 /* r_rx_clk */
694 #define bCCKr_cp_mode0 0x0100
695 #define bCCKTxDCOffset 0xf0
696 #define bCCKRxDCOffset 0xf
697 #define bCCKCCAMode 0xc000
698 #define bCCKFalseCS_lim 0x3f00
699 #define bCCKCS_ratio 0xc00000
700 #define bCCKCorgBit_sel 0x300000
701 #define bCCKPD_lim 0x0f0000
702 #define bCCKNewCCA 0x80000000
703 #define bCCKRxHPofIG 0x8000
704 #define bCCKRxIG 0x7f00
705 #define bCCKLNAPolarity 0x800000
706 #define bCCKRx1stGain 0x7f0000
707 #define bCCKRFExtend 0x20000000 /* CCK Rx Iinital gain polarity */
708 #define bCCKRxAGCSatLevel 0x1f000000
709 #define bCCKRxAGCSatCount 0xe0
710 #define bCCKRxRFSettle 0x1f /* AGCsamp_dly */
711 #define bCCKFixedRxAGC 0x8000
712 /* #define bCCKRxAGCFormat 0x4000 */ /* remove to HSSI register 0x824 */
713 #define bCCKAntennaPolarity 0x2000
714 #define bCCKTxFilterType 0x0c00
715 #define bCCKRxAGCReportType 0x0300
716 #define bCCKRxDAGCEn 0x80000000
717 #define bCCKRxDAGCPeriod 0x20000000
718 #define bCCKRxDAGCSatLevel 0x1f000000
719 #define bCCKTimingRecovery 0x800000
720 #define bCCKTxC0 0x3f0000
721 #define bCCKTxC1 0x3f000000
722 #define bCCKTxC2 0x3f
723 #define bCCKTxC3 0x3f00
724 #define bCCKTxC4 0x3f0000
725 #define bCCKTxC5 0x3f000000
726 #define bCCKTxC6 0x3f
727 #define bCCKTxC7 0x3f00
728 #define bCCKDebugPort 0xff0000
729 #define bCCKDACDebug 0x0f000000
730 #define bCCKFalseAlarmEnable 0x8000
731 #define bCCKFalseAlarmRead 0x4000
732 #define bCCKTRSSI 0x7f
733 #define bCCKRxAGCReport 0xfe
734 #define bCCKRxReport_AntSel 0x80000000
735 #define bCCKRxReport_MFOff 0x40000000
736 #define bCCKRxRxReport_SQLoss 0x20000000
737 #define bCCKRxReport_Pktloss 0x10000000
738 #define bCCKRxReport_Lockedbit 0x08000000
739 #define bCCKRxReport_RateError 0x04000000
740 #define bCCKRxReport_RxRate 0x03000000
741 #define bCCKRxFACounterLower 0xff
742 #define bCCKRxFACounterUpper 0xff000000
743 #define bCCKRxHPAGCStart 0xe000
744 #define bCCKRxHPAGCFinal 0x1c00
745 #define bCCKRxFalseAlarmEnable 0x8000
746 #define bCCKFACounterFreeze 0x4000
747 #define bCCKTxPathSel 0x10000000
748 #define bCCKDefaultRxPath 0xc000000
749 #define bCCKOptionRxPath 0x3000000
751 /* 5. PageC(0xC00) */
752 #define bNumOfSTF 0x3 /* Useless */
753 #define bShift_L 0xc0
763 #define bTRSSIFreq 0x200
764 #define bADCBackoff 0x3000
765 #define bDFIRBackoff 0xc000
766 #define bTRSSILatchPhase 0x10000
767 #define bRxIDCOffset 0xff
768 #define bRxQDCOffset 0xff00
769 #define bRxDFIRMode 0x1800000
770 #define bRxDCNFType 0xe000000
771 #define bRXIQImb_A 0x3ff
772 #define bRXIQImb_B 0xfc00
773 #define bRXIQImb_C 0x3f0000
774 #define bRXIQImb_D 0xffc00000
775 #define bDC_dc_Notch 0x60000
776 #define bRxNBINotch 0x1f000000
778 #define bPD_TH_Opt2 0xc000
779 #define bPWED_TH 0x700
780 #define bIfMF_Win_L 0x800
781 #define bPD_Option 0x1000
782 #define bMF_Win_L 0xe000
783 #define bBW_Search_L 0x30000
784 #define bwin_enh_L 0xc0000
785 #define bBW_TH 0x700000
786 #define bED_TH2 0x3800000
787 #define bBW_option 0x4000000
788 #define bRatio_TH 0x18000000
789 #define bWindow_L 0xe0000000
790 #define bSBD_Option 0x1
791 #define bFrame_TH 0x1c
792 #define bFS_Option 0x60
793 #define bDC_Slope_check 0x80
794 #define bFGuard_Counter_DC_L 0xe00
795 #define bFrame_Weight_Short 0x7000
796 #define bSub_Tune 0xe00000
797 #define bFrame_DC_Length 0xe000000
798 #define bSBD_start_offset 0x30000000
799 #define bFrame_TH_2 0x7
800 #define bFrame_GI2_TH 0x38
801 #define bGI2_Sync_en 0x40
802 #define bSarch_Short_Early 0x300
803 #define bSarch_Short_Late 0xc00
804 #define bSarch_GI2_Late 0x70000
805 #define bCFOAntSum 0x1
807 #define bCFOStartOffset 0xc
808 #define bCFOLookBack 0x70
809 #define bCFOSumWeight 0x80
810 #define bDAGCEnable 0x10000
811 #define bTXIQImb_A 0x3ff
812 #define bTXIQImb_B 0xfc00
813 #define bTXIQImb_C 0x3f0000
814 #define bTXIQImb_D 0xffc00000
815 #define bTxIDCOffset 0xff
816 #define bTxQDCOffset 0xff00
817 #define bTxDFIRMode 0x10000
818 #define bTxPesudoNoiseOn 0x4000000
819 #define bTxPesudoNoise_A 0xff
820 #define bTxPesudoNoise_B 0xff00
821 #define bTxPesudoNoise_C 0xff0000
822 #define bTxPesudoNoise_D 0xff000000
823 #define bCCADropOption 0x20000
824 #define bCCADropThres 0xfff00000
826 #define bEDCCA_L 0xf0
827 #define bLambda_ED 0x300
828 #define bRxInitialGain 0x7f
829 #define bRxAntDivEn 0x80
830 #define bRxAGCAddressForLNA 0x7f00
831 #define bRxHighPowerFlow 0x8000
832 #define bRxAGCFreezeThres 0xc0000
833 #define bRxFreezeStep_AGC1 0x300000
834 #define bRxFreezeStep_AGC2 0xc00000
835 #define bRxFreezeStep_AGC3 0x3000000
836 #define bRxFreezeStep_AGC0 0xc000000
837 #define bRxRssi_Cmp_En 0x10000000
838 #define bRxQuickAGCEn 0x20000000
839 #define bRxAGCFreezeThresMode 0x40000000
840 #define bRxOverFlowCheckType 0x80000000
841 #define bRxAGCShift 0x7f
842 #define bTRSW_Tri_Only 0x80
843 #define bPowerThres 0x300
845 #define bRxAGCTogetherEn 0x2
846 #define bRxAGCMin 0x4
847 #define bRxHP_Ini 0x7
848 #define bRxHP_TRLNA 0x70
849 #define bRxHP_RSSI 0x700
850 #define bRxHP_BBP1 0x7000
851 #define bRxHP_BBP2 0x70000
852 #define bRxHP_BBP3 0x700000
853 #define bRSSI_H 0x7f0000 /* the threshold for high power */
854 #define bRSSI_Gen 0x7f000000 /* the threshold for ant diversity */
855 #define bRxSettle_TRSW 0x7
856 #define bRxSettle_LNA 0x38
857 #define bRxSettle_RSSI 0x1c0
858 #define bRxSettle_BBP 0xe00
859 #define bRxSettle_RxHP 0x7000
860 #define bRxSettle_AntSW_RSSI 0x38000
861 #define bRxSettle_AntSW 0xc0000
862 #define bRxProcessTime_DAGC 0x300000
863 #define bRxSettle_HSSI 0x400000
864 #define bRxProcessTime_BBPPW 0x800000
865 #define bRxAntennaPowerShift 0x3000000
866 #define bRSSITableSelect 0xc000000
867 #define bRxHP_Final 0x7000000
868 #define bRxHTSettle_BBP 0x7
869 #define bRxHTSettle_HSSI 0x8
870 #define bRxHTSettle_RxHP 0x70
871 #define bRxHTSettle_BBPPW 0x80
872 #define bRxHTSettle_Idle 0x300
873 #define bRxHTSettle_Reserved 0x1c00
874 #define bRxHTRxHPEn 0x8000
875 #define bRxHTAGCFreezeThres 0x30000
876 #define bRxHTAGCTogetherEn 0x40000
877 #define bRxHTAGCMin 0x80000
878 #define bRxHTAGCEn 0x100000
879 #define bRxHTDAGCEn 0x200000
880 #define bRxHTRxHP_BBP 0x1c00000
881 #define bRxHTRxHP_Final 0xe0000000
882 #define bRxPWRatioTH 0x3
883 #define bRxPWRatioEn 0x4
884 #define bRxMFHold 0x3800
885 #define bRxPD_Delay_TH1 0x38
886 #define bRxPD_Delay_TH2 0x1c0
887 #define bRxPD_DC_COUNT_MAX 0x600
888 /* #define bRxMF_Hold 0x3800 */
889 #define bRxPD_Delay_TH 0x8000
890 #define bRxProcess_Delay 0xf0000
891 #define bRxSearchrange_GI2_Early 0x700000
892 #define bRxFrame_Guard_Counter_L 0x3800000
893 #define bRxSGI_Guard_L 0xc000000
894 #define bRxSGI_Search_L 0x30000000
895 #define bRxSGI_TH 0xc0000000
896 #define bDFSCnt0 0xff
897 #define bDFSCnt1 0xff00
898 #define bDFSFlag 0xf0000
899 #define bMFWeightSum 0x300000
900 #define bMinIdxTH 0x7f000000
901 #define bDAFormat 0x40000
902 #define bTxChEmuEnable 0x01000000
903 #define bTRSWIsolation_A 0x7f
904 #define bTRSWIsolation_B 0x7f00
905 #define bTRSWIsolation_C 0x7f0000
906 #define bTRSWIsolation_D 0x7f000000
907 #define bExtLNAGain 0x7c00
909 /* 6. PageE(0xE00) */
910 #define bSTBCEn 0x4 /* Useless */
911 #define bAntennaMapping 0x10
913 #define bCFOAntSumD 0x200
914 #define bPHYCounterReset 0x8000000
915 #define bCFOReportGet 0x4000000
916 #define bOFDMContinueTx 0x10000000
917 #define bOFDMSingleCarrier 0x20000000
918 #define bOFDMSingleTone 0x40000000
919 /* #define bRxPath1 0x01 */
920 /* #define bRxPath2 0x02 */
921 /* #define bRxPath3 0x04 */
922 /* #define bRxPath4 0x08 */
923 /* #define bTxPath1 0x10 */
924 /* #define bTxPath2 0x20 */
925 #define bHTDetect 0x100
926 #define bCFOEn 0x10000
927 #define bCFOValue 0xfff00000
928 #define bSigTone_Re 0x3f
929 #define bSigTone_Im 0x7f00
930 #define bCounter_CCA 0xffff
931 #define bCounter_ParityFail 0xffff0000
932 #define bCounter_RateIllegal 0xffff
933 #define bCounter_CRC8Fail 0xffff0000
934 #define bCounter_MCSNoSupport 0xffff
935 #define bCounter_FastSync 0xffff
936 #define bShortCFO 0xfff
937 #define bShortCFOTLength 12 /* total */
938 #define bShortCFOFLength 11 /* fraction */
939 #define bLongCFO 0x7ff
940 #define bLongCFOTLength 11
941 #define bLongCFOFLength 11
942 #define bTailCFO 0x1fff
943 #define bTailCFOTLength 13
944 #define bTailCFOFLength 12
945 #define bmax_en_pwdB 0xffff
946 #define bCC_power_dB 0xffff0000
947 #define bnoise_pwdB 0xffff
948 #define bPowerMeasTLength 10
949 #define bPowerMeasFLength 3
950 #define bRx_HT_BW 0x1
953 #define bNB_intf_det_on 0x1
954 #define bIntf_win_len_cfg 0x30
955 #define bNB_Intf_TH_cfg 0x1c0
957 #define bTableSel 0x40
959 #define bRxSNR_A 0xff
960 #define bRxSNR_B 0xff00
961 #define bRxSNR_C 0xff0000
962 #define bRxSNR_D 0xff000000
963 #define bSNREVMTLength 8
964 #define bSNREVMFLength 1
966 #define bCSI2nd 0xff00
967 #define bRxEVM1st 0xff0000
968 #define bRxEVM2nd 0xff000000
971 #define bSGIEN 0x10000
973 #define bSFactorQAM1 0xf /* Useless */
974 #define bSFactorQAM2 0xf0
975 #define bSFactorQAM3 0xf00
976 #define bSFactorQAM4 0xf000
977 #define bSFactorQAM5 0xf0000
978 #define bSFactorQAM6 0xf0000
979 #define bSFactorQAM7 0xf00000
980 #define bSFactorQAM8 0xf000000
981 #define bSFactorQAM9 0xf0000000
982 #define bCSIScheme 0x100000
984 #define bNoiseLvlTopSet 0x3 /* Useless */
985 #define bChSmooth 0x4
986 #define bChSmoothCfg1 0x38
987 #define bChSmoothCfg2 0x1c0
988 #define bChSmoothCfg3 0xe00
989 #define bChSmoothCfg4 0x7000
990 #define bMRCMode 0x800000
991 #define bTHEVMCfg 0x7000000
993 #define bLoopFitType 0x1 /* Useless */
995 #define bUpdCFOOffData 0x80
996 #define bAdvUpdCFO 0x100
997 #define bAdvTimeCtrl 0x800
998 #define bUpdClko 0x1000
1000 #define bTrackingMode 0x8000
1001 #define bPhCmpEnable 0x10000
1002 #define bUpdClkoLTF 0x20000
1003 #define bComChCFO 0x40000
1004 #define bCSIEstiMode 0x80000
1005 #define bAdvUpdEqz 0x100000
1006 #define bUChCfg 0x7000000
1007 #define bUpdEqz 0x8000000
1009 /* Rx Pseduo noise */
1010 #define bRxPesudoNoiseOn 0x20000000 /* Useless */
1011 #define bRxPesudoNoise_A 0xff
1012 #define bRxPesudoNoise_B 0xff00
1013 #define bRxPesudoNoise_C 0xff0000
1014 #define bRxPesudoNoise_D 0xff000000
1015 #define bPesudoNoiseState_A 0xffff
1016 #define bPesudoNoiseState_B 0xffff0000
1017 #define bPesudoNoiseState_C 0xffff
1018 #define bPesudoNoiseState_D 0xffff0000
1022 #define bZebra1_HSSIEnable 0x8 /* Useless */
1023 #define bZebra1_TRxControl 0xc00
1024 #define bZebra1_TRxGainSetting 0x07f
1025 #define bZebra1_RxCorner 0xc00
1026 #define bZebra1_TxChargePump 0x38
1027 #define bZebra1_RxChargePump 0x7
1028 #define bZebra1_ChannelNum 0xf80
1029 #define bZebra1_TxLPFBW 0x400
1030 #define bZebra1_RxLPFBW 0x600
1033 #define bRTL8256RegModeCtrl1 0x100 /* Useless */
1034 #define bRTL8256RegModeCtrl0 0x40
1035 #define bRTL8256_TxLPFBW 0x18
1036 #define bRTL8256_RxLPFBW 0x600
1039 #define bRTL8258_TxLPFBW 0xc /* Useless */
1040 #define bRTL8258_RxLPFBW 0xc00
1041 #define bRTL8258_RSSILPFBW 0xc0
1048 /* byte endable for sb_write */
1049 #define bByte0 0x1 /* Useless */
1057 /* for PutRegsetting & GetRegSetting BitMask */
1058 #define bMaskByte0 0xff /* Reg 0xc50 rOFDM0_XAAGCCore~0xC6f */
1059 #define bMaskByte1 0xff00
1060 #define bMaskByte2 0xff0000
1061 #define bMaskByte3 0xff000000
1062 #define bMaskHWord 0xffff0000
1063 #define bMaskLWord 0x0000ffff
1064 #define bMaskDWord 0xffffffff
1065 #define bMaskH3Bytes 0xffffff00
1066 #define bMask12Bits 0xfff
1067 #define bMaskH4Bits 0xf0000000
1068 #define bMaskOFDM_D 0xffc00000
1069 #define bMaskCCK 0x3f3f3f3f
1072 #define bEnable 0x1 /* Useless */
1073 #define bDisable 0x0
1075 #define LeftAntenna 0x0 /* Useless */
1076 #define RightAntenna 0x1
1078 #define tCheckTxStatus 500 /* 500ms */ /* Useless */
1079 #define tUpdateRxCounter 100 /* 100ms */
1081 #define rateCCK 0 /* Useless */
1085 /* define Register-End */
1086 #define bPMAC_End 0x1ff /* Useless */
1087 #define bFPGAPHY0_End 0x8ff
1088 #define bFPGAPHY1_End 0x9ff
1089 #define bCCKPHY0_End 0xaff
1090 #define bOFDMPHY0_End 0xcff
1091 #define bOFDMPHY1_End 0xdff
1093 /* define max debug item in each debug page
1094 * #define bMaxItem_FPGA_PHY0 0x9
1095 * #define bMaxItem_FPGA_PHY1 0x3
1096 * #define bMaxItem_PHY_11B 0x16
1097 * #define bMaxItem_OFDM_PHY0 0x29
1098 * #define bMaxItem_OFDM_PHY1 0x0 */
1100 #define bPMACControl 0x0 /* Useless */
1101 #define bWMACControl 0x1
1102 #define bWNICControl 0x2
1104 #define PathA 0x0 /* Useless */
1109 /*--------------------------Define Parameters-------------------------------*/
1112 /* BB Register Definition
1116 #define rDPDT_control 0x92c
1117 #define rfe_ctrl_anta_src 0x930
1118 #define rS0S1_PathSwitch 0x948
1119 #define BBrx_DFIR 0x954
1120 #define AGC_table_select 0xb2c
1125 #define rPdp_AntA 0xb00
1126 #define rPdp_AntA_4 0xb04
1127 #define rPdp_AntA_8 0xb08
1128 #define rPdp_AntA_C 0xb0c
1129 #define rPdp_AntA_10 0xb10
1130 #define rPdp_AntA_14 0xb14
1131 #define rPdp_AntA_18 0xb18
1132 #define rPdp_AntA_1C 0xb1c
1133 #define rPdp_AntA_20 0xb20
1134 #define rPdp_AntA_24 0xb24
1136 #define rConfig_Pmpd_AntA 0xb28
1137 #define rConfig_ram64x16 0xb2c
1140 #define rHssiPar 0xb34
1142 #define rConfig_AntA 0xb68
1143 #define rConfig_AntB 0xb6c
1145 #define rPdp_AntB 0xb70
1146 #define rPdp_AntB_4 0xb74
1147 #define rPdp_AntB_8 0xb78
1148 #define rPdp_AntB_C 0xb7c
1149 #define rPdp_AntB_10 0xb80
1150 #define rPdp_AntB_14 0xb84
1151 #define rPdp_AntB_18 0xb88
1152 #define rPdp_AntB_1C 0xb8c
1153 #define rPdp_AntB_20 0xb90
1154 #define rPdp_AntB_24 0xb94
1156 #define rConfig_Pmpd_AntB 0xb98
1161 #define rPm_Rx0_AntA 0xbdc
1162 #define rPm_Rx1_AntA 0xbe0
1163 #define rPm_Rx2_AntA 0xbe4
1164 #define rPm_Rx3_AntA 0xbe8
1165 #define rPm_Rx0_AntB 0xbec
1166 #define rPm_Rx1_AntB 0xbf0
1167 #define rPm_Rx2_AntB 0xbf4
1168 #define rPm_Rx3_AntB 0xbf8