drivers/net/wireless/rockchip_wlan/rtl8723cs/include/rtl8821c_spec.h

   1 /******************************************************************************
   2  *
   3  * Copyright(c) 2007 - 2016 Realtek Corporation. All rights reserved.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of version 2 of the GNU General Public License as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program; if not, write to the Free Software Foundation, Inc.,
  16  * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  17  *
  18  *******************************************************************************/
  19 #ifndef __RTL8821C_SPEC_H__
  20 #define __RTL8821C_SPEC_H__
  21
  22 #define EFUSE_MAP_SIZE          HALMAC_EFUSE_SIZE_8821C
  23
  24 /*
  25  * MAC Register definition
  26  */
  27 #define REG_AFE_XTAL_CTRL                       REG_AFE_CTRL1_8821C     /* hal_com.c & phydm */
  28 #define REG_AFE_PLL_CTRL                        REG_AFE_CTRL2_8821C     /* hal_com.c & phydm */
  29 #define REG_MAC_PHY_CTRL                        REG_AFE_CTRL3_8821C     /* phydm only */
  30 #define REG_LEDCFG0                                     REG_LED_CFG_8821C       /* rtw_mp.c */
  31 #define MSR                                                     (REG_CR_8821C + 2)      /* rtw_mp.c */
  32 #define MSR1                                            REG_CR_EXT_8821C        /* rtw_mp.c & hal_com.c */
  33 #define REG_C2HEVT_MSG_NORMAL           0x1A0                   /* hal_com.c */
  34 #define REG_C2HEVT_CLEAR                        0x1AF                   /* hal_com.c */
  35 #define REG_BCN_CTRL_1                          REG_BCN_CTRL_CLINT0_8821C/* hal_com.c */
  36 #define REG_TSFTR1                                      REG_FREERUN_CNT_8821C   /* hal_com.c */
  37 #define REG_RXFLTMAP2                           REG_RXFLTMAP_8821C      /* rtw_mp.c */
  38 #define REG_WOWLAN_WAKE_REASON  0x01C7
  39
  40 /* RXERR_RPT, for rtw_mp.c */
  41 #define RXERR_TYPE_OFDM_PPDU            0
  42 #define RXERR_TYPE_OFDM_FALSE_ALARM     2
  43 #define RXERR_TYPE_OFDM_MPDU_OK         0
  44 #define RXERR_TYPE_OFDM_MPDU_FAIL       1
  45 #define RXERR_TYPE_CCK_PPDU             3
  46 #define RXERR_TYPE_CCK_FALSE_ALARM      5
  47 #define RXERR_TYPE_CCK_MPDU_OK          3
  48 #define RXERR_TYPE_CCK_MPDU_FAIL        4
  49 #define RXERR_TYPE_HT_PPDU              8
  50 #define RXERR_TYPE_HT_FALSE_ALARM       9
  51 #define RXERR_TYPE_HT_MPDU_TOTAL        6
  52 #define RXERR_TYPE_HT_MPDU_OK           6
  53 #define RXERR_TYPE_HT_MPDU_FAIL         7
  54 #define RXERR_TYPE_RX_FULL_DROP         10
  55
  56 #define RXERR_COUNTER_MASK              BIT_MASK_RPT_COUNTER_8821C
  57 #define RXERR_RPT_RST                   BIT_RXERR_RPT_RST_8821C
  58 #define _RXERR_RPT_SEL(type)            (BIT_RXERR_RPT_SEL_V1_3_0_8821C(type) \
  59                 | ((type & 0x10) ? BIT_RXERR_RPT_SEL_V1_4_8821C : 0))
  60
  61 /*
  62  * BB Register definition
  63  */
  64 #define rPMAC_Reset                             0x100   /* hal_mp.c */
  65
  66 #define rFPGA0_RFMOD                            0x800
  67 #define rFPGA0_TxInfo                           0x804
  68 #define rOFDMCCKEN_Jaguar               0x808   /* hal_mp.c */
  69 #define rFPGA0_TxGainStage              0x80C   /* phydm only */
  70 #define rFPGA0_XA_HSSIParameter1        0x820   /* hal_mp.c */
  71 #define rFPGA0_XA_HSSIParameter2        0x824   /* hal_mp.c */
  72 #define rFPGA0_XB_HSSIParameter1        0x828   /* hal_mp.c */
  73 #define rFPGA0_XB_HSSIParameter2        0x82C   /* hal_mp.c */
  74 #define rTxAGC_B_Rate18_06              0x830
  75 #define rTxAGC_B_Rate54_24              0x834
  76 #define rTxAGC_B_CCK1_55_Mcs32  0x838
  77 #define rCCAonSec_Jaguar                        0x838   /* hal_mp.c */
  78 #define rTxAGC_B_Mcs03_Mcs00            0x83C
  79 #define rTxAGC_B_Mcs07_Mcs04            0x848
  80 #define rTxAGC_B_Mcs11_Mcs08            0x84C
  81 #define rFPGA0_XA_RFInterfaceOE         0x860
  82 #define rFPGA0_XB_RFInterfaceOE         0x864
  83 #define rTxAGC_B_Mcs15_Mcs12            0x868
  84 #define rTxAGC_B_CCK11_A_CCK2_11        0x86C
  85 #define rFPGA0_XAB_RFInterfaceSW                0x870
  86 #define rFPGA0_XAB_RFParameter          0x878
  87 #define rFPGA0_AnalogParameter4         0x88C   /* hal_mp.c & phydm */
  88 #define rFPGA0_XB_LSSIReadBack          0x8A4   /* phydm */
  89 #define rHSSIRead_Jaguar                                0x8B0   /* RF read addr (rtl8821c_phy.c) */
  90
  91 #define rC_TxScale_Jaguar2                      0x181C  /* Pah_C TX scaling factor (hal_mp.c) */
  92 #define rC_IGI_Jaguar2                          0x1850  /* Initial Gain for path-C (hal_mp.c) */
  93
  94 #define rFPGA1_TxInfo                                   0x90C   /* hal_mp.c */
  95 #define rSingleTone_ContTx_Jaguar               0x914   /* hal_mp.c */
  96
  97 #define rCCK0_System                                    0xA00
  98 #define rCCK0_AFESetting                                0xA04
  99
 100 #define rCCK0_DSPParameter2                     0xA1C
 101 #define rCCK0_TxFilter1                         0xA20
 102 #define rCCK0_TxFilter2                         0xA24
 103 #define rCCK0_DebugPort                         0xA28
 104 #define rCCK0_FalseAlarmReport          0xA2C
 105
 106 #define rD_TxScale_Jaguar2                      0x1A1C  /* Path_D TX scaling factor (hal_mp.c) */
 107 #define rD_IGI_Jaguar2                          0x1A50  /* Initial Gain for path-D (hal_mp.c) */
 108
 109 #define rOFDM0_TRxPathEnable                    0xC04
 110 #define rOFDM0_TRMuxPar                         0xC08
 111 #define rA_TxScale_Jaguar                               0xC1C   /* Pah_A TX scaling factor (hal_mp.c) */
 112 #define rOFDM0_RxDetector1                      0xC30   /* rtw_mp.c */
 113 #define rOFDM0_ECCAThreshold                    0xC4C   /* phydm only */
 114 #define rOFDM0_XAAGCCore1                       0xC50   /* phydm only */
 115 #define rA_IGI_Jaguar                                   0xC50   /* Initial Gain for path-A (hal_mp.c) */
 116 #define rOFDM0_XBAGCCore1                       0xC58   /* phydm only */
 117 #define rOFDM0_XATxIQImbalance          0xC80   /* phydm only */
 118 #define rA_LSSIWrite_Jaguar                     0xC90   /* RF write addr, LSSI Parameter (rtl8821c_phy.c) */
 119 #define rA_RFE_Pinmux_Jaguar                    0xCB0   /* hal_mp.c */
 120
 121 #define rOFDM1_LSTF                                     0xD00
 122 #define rOFDM1_TRxPathEnable                    0xD04   /* hal_mp.c */
 123 #define rA_PIRead_Jaguar                                0xD04   /* RF readback with PI (rtl8821c_phy.c) */
 124 #define rA_SIRead_Jaguar                                0xD08   /* RF readback with SI (rtl8821c_phy.c) */
 125 #define rB_PIRead_Jaguar                                0xD44   /* RF readback with PI (rtl8821c_phy.c) */
 126 #define rB_SIRead_Jaguar                                0xD48   /* RF readback with SI (rtl8821c_phy.c) */
 127
 128 #define rTxAGC_A_Rate18_06                      0xE00
 129 #define rTxAGC_A_Rate54_24                      0xE04
 130 #define rTxAGC_A_CCK1_Mcs32                     0xE08
 131 #define rTxAGC_A_Mcs03_Mcs00            0xE10
 132 #define rTxAGC_A_Mcs07_Mcs04            0xE14
 133 #define rTxAGC_A_Mcs11_Mcs08            0xE18
 134 #define rTxAGC_A_Mcs15_Mcs12            0xE1C
 135 #define rB_TxScale_Jaguar                               0xE1C   /* Path_B TX scaling factor (hal_mp.c) */
 136 #define rB_IGI_Jaguar                                   0xE50   /* Initial Gain for path-B (hal_mp.c) */
 137 #define rB_LSSIWrite_Jaguar                     0xE90   /* RF write addr, LSSI Parameter (rtl8821c_phy.c) */
 138 #define rB_RFE_Pinmux_Jaguar                    0xEB0   /* hal_mp.c */
 139
 140 /* Page1(0x100) */
 141 #define bBBResetB                                       0x100
 142
 143 /* Page8(0x800) */
 144 #define bCCKEn                                          0x1000000
 145 #define bOFDMEn                                         0x2000000
 146 /* Reg 0x80C rFPGA0_TxGainStage */
 147 #define bXBTxAGC                                                0xF00
 148 #define bXCTxAGC                                                0xF000
 149 #define bXDTxAGC                                                0xF0000
 150
 151 /* PageA(0xA00) */
 152 #define bCCKBBMode                                      0x3
 153
 154 #define bCCKScramble                                    0x8
 155 #define bCCKTxRate                                      0x3000
 156
 157 /* General */
 158 #define bMaskByte0              0xFF            /* mp, rtw_odm.c & phydm */
 159 #define bMaskByte1              0xFF00          /* hal_mp.c & phydm */
 160 #define bMaskByte2              0xFF0000        /* hal_mp.c & phydm */
 161 #define bMaskByte3              0xFF000000      /* hal_mp.c & phydm */
 162 #define bMaskHWord              0xFFFF0000      /* hal_com.c, rtw_mp.c */
 163 #define bMaskLWord              0x0000FFFF      /* mp, hal_com.c & phydm */
 164 #define bMaskDWord              0xFFFFFFFF      /* mp, hal, rtw_odm.c & phydm */
 165
 166 #define bEnable                 0x1             /* hal_mp.c, rtw_mp.c */
 167 #define bDisable                        0x0             /* rtw_mp.c */
 168
 169 #define MAX_STALL_TIME          50              /* unit: us, hal_com_phycfg.c */
 170
 171 #define Rx_Smooth_Factor                20              /* phydm only */
 172
 173 /*
 174  * RF Register definition
 175  */
 176 #define RF_AC                   0x00
 177 #define RF_AC_Jaguar            0x00    /* hal_mp.c */
 178 #define RF_CHNLBW               0x18    /* rtl8821c_phy.c */
 179 #define RF_0x52                 0x52
 180
 181 struct hw_port_reg {
 182         u32 net_type;   /*reg_offset*/
 183         u8 net_type_shift;
 184         u32 macaddr;    /*reg_offset*/
 185         u32 bssid;      /*reg_offset*/
 186         u32 bcn_ctl;                    /*reg_offset*/
 187         u32 tsf_rst;                    /*reg_offset*/
 188         u8 tsf_rst_bit;
 189         u32 bcn_space;          /*reg_offset*/
 190         u8 bcn_space_shift;
 191         u16 bcn_space_mask;
 192         u32     ps_aid;                 /*reg_offset*/
 193 };
 194
 195 #endif /* __RTL8192E_SPEC_H__ */