1 /******************************************************************************
3 * Copyright(c) 2015 - 2016 Realtek Corporation. All rights reserved.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
19 ******************************************************************************/
20 #define _HAL_HALMAC_C_
22 #include <drv_types.h> /* PADAPTER, struct dvobj_priv, SDIO_ERR_VAL8 and etc. */
23 #include <hal_data.h> /* efuse, PHAL_DATA_TYPE and etc. */
24 #include "halmac/halmac_api.h" /* HALMAC_FW_SIZE_MAX_88XX and etc. */
25 #include "hal_halmac.h" /* dvobj_to_halmac() and ect. */
27 #define DEFAULT_INDICATOR_TIMELMT 1000 /* ms */
28 #define FIRMWARE_MAX_SIZE HALMAC_FW_SIZE_MAX_88XX
31 * Driver API for HALMAC operations
34 #ifdef CONFIG_SDIO_HCI
36 static u8 _halmac_sdio_cmd52_read(void *p, u32 offset)
43 d = (struct dvobj_priv *)p;
44 ret = rtw_sdio_read_cmd52(d, offset, &val, 1);
46 RTW_INFO("%s: [ERROR] I/O FAIL!\n", __FUNCTION__);
53 static void _halmac_sdio_cmd52_write(void *p, u32 offset, u8 val)
59 d = (struct dvobj_priv *)p;
60 ret = rtw_sdio_write_cmd52(d, offset, &val, 1);
62 RTW_INFO("%s: [ERROR] I/O FAIL!\n", __FUNCTION__);
65 static u8 _halmac_sdio_reg_read_8(void *p, u32 offset)
73 d = (struct dvobj_priv *)p;
75 pbuf = rtw_zmalloc(1);
79 err = d->intf_ops->read(d, offset, pbuf, 1, 0);
81 RTW_INFO("%s: [ERROR] I/O FAIL!\n", __FUNCTION__);
93 static u16 _halmac_sdio_reg_read_16(void *p, u32 offset)
101 d = (struct dvobj_priv *)p;
102 val = SDIO_ERR_VAL16;
103 pbuf = rtw_zmalloc(2);
107 err = d->intf_ops->read(d, offset, pbuf, 2, 0);
109 RTW_INFO("%s: [ERROR] I/O FAIL!\n", __FUNCTION__);
113 val = le16_to_cpu(*(u16 *)pbuf);
121 static u32 _halmac_sdio_reg_read_32(void *p, u32 offset)
123 struct dvobj_priv *d;
129 d = (struct dvobj_priv *)p;
130 val = SDIO_ERR_VAL32;
131 pbuf = rtw_zmalloc(4);
135 err = d->intf_ops->read(d, offset, pbuf, 4, 0);
137 RTW_INFO("%s: [ERROR] I/O FAIL!\n", __FUNCTION__);
141 val = le32_to_cpu(*(u32 *)pbuf);
149 static u8 _halmac_sdio_reg_read_n(void *p, u32 offset, u32 size, u8 *data)
151 struct dvobj_priv *d = (struct dvobj_priv *)p;
152 PSDIO_DATA psdio = &d->intf_data;
159 sdio_read_size = RND4(size);
160 if (sdio_read_size > psdio->block_transfer_len)
161 sdio_read_size = _RND(sdio_read_size, psdio->block_transfer_len);
163 pbuf = rtw_zmalloc(sdio_read_size);
164 if ((!pbuf) || (!data))
167 err = d->intf_ops->read(d, offset, pbuf, sdio_read_size, 0);
169 RTW_ERR("%s: [ERROR] I/O FAIL!\n", __func__);
173 _rtw_memcpy(data, pbuf, size);
176 rtw_mfree(pbuf, sdio_read_size);
181 static void _halmac_sdio_reg_write_8(void *p, u32 offset, u8 val)
183 struct dvobj_priv *d;
188 d = (struct dvobj_priv *)p;
189 pbuf = rtw_zmalloc(1);
192 _rtw_memcpy(pbuf, &val, 1);
194 err = d->intf_ops->write(d, offset, pbuf, 1, 0);
196 RTW_INFO("%s: [ERROR] I/O FAIL!\n", __FUNCTION__);
201 static void _halmac_sdio_reg_write_16(void *p, u32 offset, u16 val)
203 struct dvobj_priv *d;
208 d = (struct dvobj_priv *)p;
209 val = cpu_to_le16(val);
210 pbuf = rtw_zmalloc(2);
213 _rtw_memcpy(pbuf, &val, 2);
215 err = d->intf_ops->write(d, offset, pbuf, 2, 0);
217 RTW_INFO("%s: [ERROR] I/O FAIL!\n", __FUNCTION__);
222 static void _halmac_sdio_reg_write_32(void *p, u32 offset, u32 val)
224 struct dvobj_priv *d;
229 d = (struct dvobj_priv *)p;
230 val = cpu_to_le32(val);
231 pbuf = rtw_zmalloc(4);
234 _rtw_memcpy(pbuf, &val, 4);
236 err = d->intf_ops->write(d, offset, pbuf, 4, 0);
238 RTW_INFO("%s: [ERROR] I/O FAIL!\n", __FUNCTION__);
243 #else /* !CONFIG_SDIO_HCI */
245 static u8 _halmac_reg_read_8(void *p, u32 offset)
247 struct dvobj_priv *d;
251 d = (struct dvobj_priv *)p;
252 adapter = d->padapters[IFACE_ID0];
254 return rtw_read8(adapter, offset);
257 static u16 _halmac_reg_read_16(void *p, u32 offset)
259 struct dvobj_priv *d;
263 d = (struct dvobj_priv *)p;
264 adapter = d->padapters[IFACE_ID0];
266 return rtw_read16(adapter, offset);
269 static u32 _halmac_reg_read_32(void *p, u32 offset)
271 struct dvobj_priv *d;
275 d = (struct dvobj_priv *)p;
276 adapter = d->padapters[IFACE_ID0];
278 return rtw_read32(adapter, offset);
281 static void _halmac_reg_write_8(void *p, u32 offset, u8 val)
283 struct dvobj_priv *d;
288 d = (struct dvobj_priv *)p;
289 adapter = d->padapters[IFACE_ID0];
291 err = rtw_write8(adapter, offset, val);
293 RTW_INFO("%s: [ERROR] I/O FAIL!\n", __FUNCTION__);
296 static void _halmac_reg_write_16(void *p, u32 offset, u16 val)
298 struct dvobj_priv *d;
303 d = (struct dvobj_priv *)p;
304 adapter = d->padapters[IFACE_ID0];
306 err = rtw_write16(adapter, offset, val);
308 RTW_INFO("%s: [ERROR] I/O FAIL!\n", __FUNCTION__);
311 static void _halmac_reg_write_32(void *p, u32 offset, u32 val)
313 struct dvobj_priv *d;
318 d = (struct dvobj_priv *)p;
319 adapter = d->padapters[IFACE_ID0];
321 err = rtw_write32(adapter, offset, val);
323 RTW_INFO("%s: [ERROR] I/O FAIL!\n", __FUNCTION__);
325 #endif /* !CONFIG_SDIO_HCI */
327 static u8 _halmac_mfree(void *p, void *buffer, u32 size)
329 rtw_mfree(buffer, size);
333 static void *_halmac_malloc(void *p, u32 size)
335 return rtw_zmalloc(size);
338 static u8 _halmac_memcpy(void *p, void *dest, void *src, u32 size)
340 _rtw_memcpy(dest, src, size);
344 static u8 _halmac_memset(void *p, void *addr, u8 value, u32 size)
346 _rtw_memset(addr, value, size);
350 static void _halmac_udelay(void *p, u32 us)
355 static u8 _halmac_mutex_init(void *p, HALMAC_MUTEX *pMutex)
357 _rtw_mutex_init(pMutex);
361 static u8 _halmac_mutex_deinit(void *p, HALMAC_MUTEX *pMutex)
363 _rtw_mutex_free(pMutex);
367 static u8 _halmac_mutex_lock(void *p, HALMAC_MUTEX *pMutex)
371 err = _enter_critical_mutex(pMutex, NULL);
378 static u8 _halmac_mutex_unlock(void *p, HALMAC_MUTEX *pMutex)
380 _exit_critical_mutex(pMutex, NULL);
384 static u8 _halmac_msg_print(void *p, u32 msg_type, u8 msg_level, s8 *fmt, ...)
387 #define MSG_PREFIX "[HALMAC]"
389 u8 str[MSG_LEN] = {0};
396 if (rtw_drv_log_level <= _DRV_ERR_)
397 level = HALMAC_DBG_ERR;
398 else if (rtw_drv_log_level <= _DRV_INFO_)
399 level = HALMAC_DBG_WARN;
401 level = HALMAC_DBG_TRACE;
403 if (!(type & BIT(msg_type)))
405 if (level < msg_level)
409 vsnprintf(str, MSG_LEN, fmt, args);
412 if (msg_level <= HALMAC_DBG_ERR)
413 RTW_ERR(MSG_PREFIX "%s", str);
414 else if (msg_level <= HALMAC_DBG_WARN)
415 RTW_WARN(MSG_PREFIX "%s", str);
417 RTW_DBG(MSG_PREFIX "%s", str);
422 static u8 _halmac_buff_print(void *p, u32 msg_type, u8 msg_level, s8 *buf, u32 size)
424 #define MSG_PREFIX "[HALMAC]"
429 if (rtw_drv_log_level <= _DRV_ERR_)
430 level = HALMAC_DBG_ERR;
431 else if (rtw_drv_log_level <= _DRV_INFO_)
432 level = HALMAC_DBG_WARN;
434 level = HALMAC_DBG_TRACE;
436 if (!(type & BIT(msg_type)))
438 if (level < msg_level)
441 if (msg_level <= HALMAC_DBG_WARN)
442 RTW_INFO_DUMP(MSG_PREFIX, buf, size);
444 RTW_DBG_DUMP(MSG_PREFIX, buf, size);
450 const char *const RTW_HALMAC_FEATURE_NAME[] = {
451 "HALMAC_FEATURE_CFG_PARA",
452 "HALMAC_FEATURE_DUMP_PHYSICAL_EFUSE",
453 "HALMAC_FEATURE_DUMP_LOGICAL_EFUSE",
454 "HALMAC_FEATURE_UPDATE_PACKET",
455 "HALMAC_FEATURE_UPDATE_DATAPACK",
456 "HALMAC_FEATURE_RUN_DATAPACK",
457 "HALMAC_FEATURE_CHANNEL_SWITCH",
458 "HALMAC_FEATURE_IQK",
459 "HALMAC_FEATURE_POWER_TRACKING",
460 "HALMAC_FEATURE_PSD",
464 static inline u8 is_valid_id_status(HALMAC_FEATURE_ID id, HALMAC_CMD_PROCESS_STATUS status)
467 case HALMAC_FEATURE_CFG_PARA:
468 RTW_INFO("%s: %s\n", __FUNCTION__, RTW_HALMAC_FEATURE_NAME[id]);
470 case HALMAC_FEATURE_DUMP_PHYSICAL_EFUSE:
471 RTW_INFO("%s: %s\n", __FUNCTION__, RTW_HALMAC_FEATURE_NAME[id]);
472 if (HALMAC_CMD_PROCESS_DONE != status) {
473 RTW_INFO("%s: <WARN> id(%d) unspecified status(%d)!\n",
474 __FUNCTION__, id, status);
477 case HALMAC_FEATURE_DUMP_LOGICAL_EFUSE:
478 RTW_INFO("%s: %s\n", __FUNCTION__, RTW_HALMAC_FEATURE_NAME[id]);
479 if (HALMAC_CMD_PROCESS_DONE != status) {
480 RTW_INFO("%s: <WARN> id(%d) unspecified status(%d)!\n",
481 __FUNCTION__, id, status);
484 case HALMAC_FEATURE_UPDATE_PACKET:
485 RTW_INFO("%s: %s\n", __FUNCTION__, RTW_HALMAC_FEATURE_NAME[id]);
487 case HALMAC_FEATURE_UPDATE_DATAPACK:
488 RTW_INFO("%s: %s\n", __FUNCTION__, RTW_HALMAC_FEATURE_NAME[id]);
490 case HALMAC_FEATURE_RUN_DATAPACK:
491 RTW_INFO("%s: %s\n", __FUNCTION__, RTW_HALMAC_FEATURE_NAME[id]);
493 case HALMAC_FEATURE_CHANNEL_SWITCH:
494 RTW_INFO("%s: %s\n", __FUNCTION__, RTW_HALMAC_FEATURE_NAME[id]);
496 case HALMAC_FEATURE_IQK:
497 RTW_INFO("%s: %s\n", __FUNCTION__, RTW_HALMAC_FEATURE_NAME[id]);
499 case HALMAC_FEATURE_POWER_TRACKING:
500 RTW_INFO("%s: %s\n", __FUNCTION__, RTW_HALMAC_FEATURE_NAME[id]);
502 case HALMAC_FEATURE_PSD:
503 RTW_INFO("%s: %s\n", __FUNCTION__, RTW_HALMAC_FEATURE_NAME[id]);
505 case HALMAC_FEATURE_ALL:
506 RTW_INFO("%s: %s\n", __FUNCTION__, RTW_HALMAC_FEATURE_NAME[id]);
509 RTW_INFO("%s: unknown feature id(%d)\n", __FUNCTION__, id);
516 static int init_halmac_event_with_waittime(struct dvobj_priv *d, HALMAC_FEATURE_ID id, u8 *buf, u32 size, u32 time)
518 struct submit_ctx *sctx;
521 if (!d->hmpriv.indicator[id].sctx) {
522 sctx = (struct submit_ctx *)rtw_zmalloc(sizeof(*sctx));
526 RTW_INFO("%s: <WARN> id(%d) sctx is not NULL!!\n", __FUNCTION__, id);
527 sctx = d->hmpriv.indicator[id].sctx;
528 d->hmpriv.indicator[id].sctx = NULL;
531 rtw_sctx_init(sctx, time);
532 d->hmpriv.indicator[id].buffer = buf;
533 d->hmpriv.indicator[id].buf_size = size;
534 d->hmpriv.indicator[id].ret_size = 0;
535 d->hmpriv.indicator[id].status = 0;
536 /* fill sctx at least to sure other variables are all ready! */
537 d->hmpriv.indicator[id].sctx = sctx;
542 static inline int init_halmac_event(struct dvobj_priv *d, HALMAC_FEATURE_ID id, u8 *buf, u32 size)
544 return init_halmac_event_with_waittime(d, id, buf, size, DEFAULT_INDICATOR_TIMELMT);
547 static void free_halmac_event(struct dvobj_priv *d, HALMAC_FEATURE_ID id)
549 struct submit_ctx *sctx;
552 if (!d->hmpriv.indicator[id].sctx)
555 sctx = d->hmpriv.indicator[id].sctx;
556 d->hmpriv.indicator[id].sctx = NULL;
557 rtw_mfree((u8 *)sctx, sizeof(*sctx));
560 static int wait_halmac_event(struct dvobj_priv *d, HALMAC_FEATURE_ID id)
562 struct submit_ctx *sctx;
566 sctx = d->hmpriv.indicator[id].sctx;
570 ret = rtw_sctx_wait(sctx, RTW_HALMAC_FEATURE_NAME[id]);
571 free_halmac_event(d, id);
580 * Always return _TRUE, HALMAC don't care the return value.
582 static u8 _halmac_event_indication(void *p, HALMAC_FEATURE_ID feature_id, HALMAC_CMD_PROCESS_STATUS process_status, u8 *buf, u32 size)
584 struct dvobj_priv *d;
587 struct halmac_indicator *tbl, *indicator;
588 struct submit_ctx *sctx;
593 d = (struct dvobj_priv *)p;
594 adapter = d->padapters[IFACE_ID0];
595 hal = GET_HAL_DATA(adapter);
596 tbl = d->hmpriv.indicator;
598 ret = is_valid_id_status(feature_id, process_status);
602 indicator = &tbl[feature_id];
603 indicator->status = process_status;
604 indicator->ret_size = size;
605 if (!indicator->sctx) {
606 RTW_INFO("%s: No feature id(%d) waiting!!\n", __FUNCTION__, feature_id);
609 sctx = indicator->sctx;
611 if (HALMAC_CMD_PROCESS_ERROR == process_status) {
612 RTW_INFO("%s: Something wrong id(%d)!!\n", __FUNCTION__, feature_id);
613 rtw_sctx_done_err(&sctx, RTW_SCTX_DONE_UNKNOWN);
617 if (size > indicator->buf_size) {
618 RTW_INFO("%s: <WARN> id(%d) buffer is not enough(%d<%d), data will be truncated!\n",
619 __FUNCTION__, feature_id, indicator->buf_size, size);
620 cpsz = indicator->buf_size;
623 if (cpsz && indicator->buffer)
624 _rtw_memcpy(indicator->buffer, buf, cpsz);
626 rtw_sctx_done(&sctx);
632 HALMAC_PLATFORM_API rtw_halmac_platform_api = {
634 #ifdef CONFIG_SDIO_HCI
635 .SDIO_CMD52_READ = _halmac_sdio_cmd52_read,
636 .SDIO_CMD53_READ_8 = _halmac_sdio_reg_read_8,
637 .SDIO_CMD53_READ_16 = _halmac_sdio_reg_read_16,
638 .SDIO_CMD53_READ_32 = _halmac_sdio_reg_read_32,
639 .SDIO_CMD53_READ_N = _halmac_sdio_reg_read_n,
640 .SDIO_CMD52_WRITE = _halmac_sdio_cmd52_write,
641 .SDIO_CMD53_WRITE_8 = _halmac_sdio_reg_write_8,
642 .SDIO_CMD53_WRITE_16 = _halmac_sdio_reg_write_16,
643 .SDIO_CMD53_WRITE_32 = _halmac_sdio_reg_write_32,
645 #endif /* CONFIG_SDIO_HCI */
646 #if defined(CONFIG_USB_HCI) || defined(CONFIG_PCIE_HCI)
647 .REG_READ_8 = _halmac_reg_read_8,
648 .REG_READ_16 = _halmac_reg_read_16,
649 .REG_READ_32 = _halmac_reg_read_32,
650 .REG_WRITE_8 = _halmac_reg_write_8,
651 .REG_WRITE_16 = _halmac_reg_write_16,
652 .REG_WRITE_32 = _halmac_reg_write_32,
653 #endif /* CONFIG_USB_HCI || CONFIG_PCIE_HCI */
657 /* impletement in HAL-IC level */
658 .SEND_RSVD_PAGE = sdio_write_data_rsvd_page,
659 .SEND_H2C_PKT = sdio_write_data_h2c,
661 /* Memory allocate */
662 .RTL_FREE = _halmac_mfree,
663 .RTL_MALLOC = _halmac_malloc,
664 .RTL_MEMCPY = _halmac_memcpy,
665 .RTL_MEMSET = _halmac_memset,
668 .RTL_DELAY_US = _halmac_udelay,
670 /* Process Synchronization */
671 .MUTEX_INIT = _halmac_mutex_init,
672 .MUTEX_DEINIT = _halmac_mutex_deinit,
673 .MUTEX_LOCK = _halmac_mutex_lock,
674 .MUTEX_UNLOCK = _halmac_mutex_unlock,
676 .MSG_PRINT = _halmac_msg_print,
677 .BUFF_PRINT = _halmac_buff_print,
678 .EVENT_INDICATION = _halmac_event_indication,
681 u8 rtw_halmac_read8(struct intf_hdl *pintfhdl, u32 addr)
687 /* WARNING: pintf_dev should not be null! */
688 mac = dvobj_to_halmac(pintfhdl->pintf_dev);
689 api = HALMAC_GET_API(mac);
691 return api->halmac_reg_read_8(mac, addr);
694 u16 rtw_halmac_read16(struct intf_hdl *pintfhdl, u32 addr)
700 /* WARNING: pintf_dev should not be null! */
701 mac = dvobj_to_halmac(pintfhdl->pintf_dev);
702 api = HALMAC_GET_API(mac);
704 return api->halmac_reg_read_16(mac, addr);
707 u32 rtw_halmac_read32(struct intf_hdl *pintfhdl, u32 addr)
713 /* WARNING: pintf_dev should not be null! */
714 mac = dvobj_to_halmac(pintfhdl->pintf_dev);
715 api = HALMAC_GET_API(mac);
717 return api->halmac_reg_read_32(mac, addr);
720 void rtw_halmac_read_mem(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *pmem)
722 #if defined(CONFIG_SDIO_HCI)
727 RTW_ERR("pmem is NULL\n");
730 /* WARNING: pintf_dev should not be null! */
731 mac = dvobj_to_halmac(pintfhdl->pintf_dev);
732 api = HALMAC_GET_API(mac);
734 api->halmac_reg_sdio_cmd53_read_n(mac, addr, cnt, pmem);
738 #ifdef CONFIG_SDIO_INDIRECT_ACCESS
739 u8 rtw_halmac_iread8(struct intf_hdl *pintfhdl, u32 addr)
744 /* WARNING: pintf_dev should not be null! */
745 mac = dvobj_to_halmac(pintfhdl->pintf_dev);
746 api = HALMAC_GET_API(mac);
748 /*return api->halmac_reg_read_indirect_8(mac, addr);*/
749 return api->halmac_reg_read_8(mac, addr);
752 u16 rtw_halmac_iread16(struct intf_hdl *pintfhdl, u32 addr)
758 /* WARNING: pintf_dev should not be null! */
759 mac = dvobj_to_halmac(pintfhdl->pintf_dev);
760 api = HALMAC_GET_API(mac);
762 /*return api->halmac_reg_read_indirect_16(mac, addr);*/
763 return api->halmac_reg_read_16(mac, addr);
766 u32 rtw_halmac_iread32(struct intf_hdl *pintfhdl, u32 addr)
772 /* WARNING: pintf_dev should not be null! */
773 mac = dvobj_to_halmac(pintfhdl->pintf_dev);
774 api = HALMAC_GET_API(mac);
776 return api->halmac_reg_read_indirect_32(mac, addr);
780 int rtw_halmac_write8(struct intf_hdl *pintfhdl, u32 addr, u8 value)
784 HALMAC_RET_STATUS status;
787 /* WARNING: pintf_dev should not be null! */
788 mac = dvobj_to_halmac(pintfhdl->pintf_dev);
789 api = HALMAC_GET_API(mac);
791 status = api->halmac_reg_write_8(mac, addr, value);
793 if (status == HALMAC_RET_SUCCESS)
799 int rtw_halmac_write16(struct intf_hdl *pintfhdl, u32 addr, u16 value)
803 HALMAC_RET_STATUS status;
806 /* WARNING: pintf_dev should not be null! */
807 mac = dvobj_to_halmac(pintfhdl->pintf_dev);
808 api = HALMAC_GET_API(mac);
810 status = api->halmac_reg_write_16(mac, addr, value);
812 if (status == HALMAC_RET_SUCCESS)
818 int rtw_halmac_write32(struct intf_hdl *pintfhdl, u32 addr, u32 value)
822 HALMAC_RET_STATUS status;
825 /* WARNING: pintf_dev should not be null! */
826 mac = dvobj_to_halmac(pintfhdl->pintf_dev);
827 api = HALMAC_GET_API(mac);
829 status = api->halmac_reg_write_32(mac, addr, value);
831 if (status == HALMAC_RET_SUCCESS)
837 static int init_priv(struct halmacpriv *priv)
839 struct halmac_indicator *indicator;
843 size = sizeof(*priv);
844 _rtw_memset(priv, 0, size);
846 count = HALMAC_FEATURE_ALL + 1;
847 size = sizeof(*indicator) * count;
848 indicator = (struct halmac_indicator *)rtw_zmalloc(size);
851 priv->indicator = indicator;
856 static void deinit_priv(struct halmacpriv *priv)
858 struct halmac_indicator *indicator;
861 indicator = priv->indicator;
862 priv->indicator = NULL;
866 count = HALMAC_FEATURE_ALL + 1;
867 #ifdef CONFIG_RTW_DEBUG
869 struct submit_ctx *sctx;
872 for (i = 0; i < count; i++) {
873 if (!indicator[i].sctx)
876 RTW_INFO("%s: <WARN> %s id(%d) sctx still exist!!\n",
877 __FUNCTION__, RTW_HALMAC_FEATURE_NAME[i], i);
878 sctx = indicator[i].sctx;
879 indicator[i].sctx = NULL;
880 rtw_mfree((u8 *)sctx, sizeof(*sctx));
883 #endif /* !CONFIG_RTW_DEBUG */
884 size = sizeof(*indicator) * count;
885 rtw_mfree((u8 *)indicator, size);
889 int rtw_halmac_init_adapter(struct dvobj_priv *d, PHALMAC_PLATFORM_API pf_api)
891 PHALMAC_ADAPTER halmac;
893 HALMAC_INTERFACE intf;
894 HALMAC_RET_STATUS status;
898 halmac = dvobj_to_halmac(d);
904 err = init_priv(&d->hmpriv);
908 #ifdef CONFIG_SDIO_HCI
909 intf = HALMAC_INTERFACE_SDIO;
910 #elif defined(CONFIG_USB_HCI)
911 intf = HALMAC_INTERFACE_USB;
912 #elif defined(CONFIG_PCIE_HCI)
913 intf = HALMAC_INTERFACE_PCIE;
915 #warning "INTERFACE(CONFIG_XXX_HCI) not be defined!!"
916 intf = HALMAC_INTERFACE_UNDEFINE;
918 status = halmac_init_adapter(d, pf_api, intf, &halmac, &api);
919 if (HALMAC_RET_SUCCESS != status) {
920 RTW_INFO("%s: halmac_init_adapter fail!(status=%d)\n", __FUNCTION__, status);
925 dvobj_set_halmac(d, halmac);
929 rtw_halmac_deinit_adapter(d);
934 int rtw_halmac_deinit_adapter(struct dvobj_priv *d)
936 PHALMAC_ADAPTER halmac;
937 HALMAC_RET_STATUS status;
941 halmac = dvobj_to_halmac(d);
947 deinit_priv(&d->hmpriv);
949 status = halmac_deinit_adapter(halmac);
950 dvobj_set_halmac(d, NULL);
951 if (status != HALMAC_RET_SUCCESS) {
960 int rtw_halmac_poweron(struct dvobj_priv *d)
962 PHALMAC_ADAPTER halmac;
964 HALMAC_RET_STATUS status;
968 halmac = dvobj_to_halmac(d);
972 api = HALMAC_GET_API(halmac);
974 status = api->halmac_pre_init_system_cfg(halmac);
975 if (status != HALMAC_RET_SUCCESS)
978 status = api->halmac_mac_power_switch(halmac, HALMAC_MAC_POWER_ON);
979 if (status != HALMAC_RET_SUCCESS)
982 status = api->halmac_init_system_cfg(halmac);
983 if (status != HALMAC_RET_SUCCESS)
991 int rtw_halmac_poweroff(struct dvobj_priv *d)
993 PHALMAC_ADAPTER halmac;
995 HALMAC_RET_STATUS status;
999 halmac = dvobj_to_halmac(d);
1003 api = HALMAC_GET_API(halmac);
1005 status = api->halmac_mac_power_switch(halmac, HALMAC_MAC_POWER_OFF);
1006 if (status != HALMAC_RET_SUCCESS)
1016 * When this function return, the register REG_RCR may be changed.
1018 int rtw_halmac_config_rx_info(struct dvobj_priv *d, HALMAC_DRV_INFO info)
1020 PHALMAC_ADAPTER halmac;
1022 HALMAC_RET_STATUS status;
1026 halmac = dvobj_to_halmac(d);
1027 api = HALMAC_GET_API(halmac);
1029 status = api->halmac_cfg_drv_info(halmac, info);
1030 if (status != HALMAC_RET_SUCCESS)
1038 #ifdef CONFIG_SUPPORT_TRX_SHARED
1039 static inline HALMAC_RX_FIFO_EXPANDING_MODE _trx_share_mode_drv2halmac(u8 trx_share_mode)
1041 if (0 == trx_share_mode)
1042 return HALMAC_RX_FIFO_EXPANDING_MODE_DISABLE;
1043 else if (1 == trx_share_mode)
1044 return HALMAC_RX_FIFO_EXPANDING_MODE_1_BLOCK;
1045 else if (2 == trx_share_mode)
1046 return HALMAC_RX_FIFO_EXPANDING_MODE_2_BLOCK;
1047 else if (3 == trx_share_mode)
1048 return HALMAC_RX_FIFO_EXPANDING_MODE_3_BLOCK;
1050 return HALMAC_RX_FIFO_EXPANDING_MODE_DISABLE;
1052 static HALMAC_RX_FIFO_EXPANDING_MODE _rtw_get_trx_share_mode(_adapter *adapter)
1054 struct registry_priv *registry_par = &adapter->registrypriv;
1056 return _trx_share_mode_drv2halmac(registry_par->trx_share_mode);
1058 void dump_trx_share_mode(void *sel, _adapter *adapter)
1060 struct registry_priv *registry_par = &adapter->registrypriv;
1061 u8 mode = _trx_share_mode_drv2halmac(registry_par->trx_share_mode);
1063 if (HALMAC_RX_FIFO_EXPANDING_MODE_1_BLOCK == mode)
1064 RTW_PRINT_SEL(sel, "TRx share mode : %s\n", "RX_FIFO_EXPANDING_MODE_1");
1065 else if (HALMAC_RX_FIFO_EXPANDING_MODE_2_BLOCK == mode)
1066 RTW_PRINT_SEL(sel, "TRx share mode : %s\n", "RX_FIFO_EXPANDING_MODE_2");
1067 else if (HALMAC_RX_FIFO_EXPANDING_MODE_3_BLOCK == mode)
1068 RTW_PRINT_SEL(sel, "TRx share mode : %s\n", "RX_FIFO_EXPANDING_MODE_3");
1070 RTW_PRINT_SEL(sel, "TRx share mode : %s\n", "DISABLE");
1074 static HALMAC_RET_STATUS init_mac_flow(struct dvobj_priv *d)
1077 PHALMAC_ADAPTER halmac;
1079 HALMAC_WLAN_ADDR hwa;
1080 HALMAC_RET_STATUS status;
1086 p = d->padapters[IFACE_ID0];
1087 halmac = dvobj_to_halmac(d);
1088 api = HALMAC_GET_API(halmac);
1089 if (p->registrypriv.wifi_spec)
1092 #ifdef CONFIG_SUPPORT_TRX_SHARED
1093 status = api->halmac_cfg_rx_fifo_expanding_mode(halmac, _rtw_get_trx_share_mode(p));
1094 if (status != HALMAC_RET_SUCCESS)
1099 status = api->halmac_cfg_drv_rsvd_pg_num(halmac, HALMAC_RSVD_PG_NUM16);/*HALMAC_RSVD_PG_NUM24/HALMAC_RSVD_PG_NUM32*/
1100 if (status != HALMAC_RET_SUCCESS)
1104 #ifdef CONFIG_USB_HCI
1105 status = api->halmac_set_bulkout_num(halmac, d->RtNumOutPipes);
1106 if (status != HALMAC_RET_SUCCESS)
1108 #endif /* CONFIG_USB_HCI */
1111 status = api->halmac_init_mac_cfg(halmac, HALMAC_TRX_MODE_WMM);
1113 status = api->halmac_init_mac_cfg(halmac, HALMAC_TRX_MODE_NORMAL);
1114 if (status != HALMAC_RET_SUCCESS)
1117 err = rtw_halmac_rx_agg_switch(d, _TRUE);
1121 nettype = dvobj_to_regsty(d)->wireless_mode;
1122 if (IsSupportedVHT(nettype) == _TRUE)
1123 status = api->halmac_cfg_operation_mode(halmac, HALMAC_WIRELESS_MODE_AC);
1124 else if (IsSupportedHT(nettype) == _TRUE)
1125 status = api->halmac_cfg_operation_mode(halmac, HALMAC_WIRELESS_MODE_N);
1126 else if (IsSupportedTxOFDM(nettype) == _TRUE)
1127 status = api->halmac_cfg_operation_mode(halmac, HALMAC_WIRELESS_MODE_G);
1129 status = api->halmac_cfg_operation_mode(halmac, HALMAC_WIRELESS_MODE_B);
1130 if (status != HALMAC_RET_SUCCESS)
1137 static inline HALMAC_RF_TYPE _rf_type_drv2halmac(RT_RF_TYPE_DEF_E rf_drv)
1139 HALMAC_RF_TYPE rf_mac;
1144 rf_mac = HALMAC_RF_1T2R;
1147 rf_mac = HALMAC_RF_2T4R;
1150 rf_mac = HALMAC_RF_2T2R;
1153 rf_mac = HALMAC_RF_1T1R;
1156 rf_mac = HALMAC_RF_2T2R_GREEN;
1159 rf_mac = HALMAC_RF_2T3R;
1162 rf_mac = HALMAC_RF_3T3R;
1165 rf_mac = HALMAC_RF_3T4R;
1168 rf_mac = HALMAC_RF_4T4R;
1171 rf_mac = (HALMAC_RF_TYPE)rf_drv;
1178 static int _send_general_info(struct dvobj_priv *d)
1182 PHALMAC_ADAPTER halmac;
1184 HALMAC_GENERAL_INFO info;
1185 HALMAC_RET_STATUS status;
1189 adapter = d->padapters[IFACE_ID0];
1190 hal = GET_HAL_DATA(adapter);
1191 halmac = dvobj_to_halmac(d);
1194 api = HALMAC_GET_API(halmac);
1196 _rtw_memset(&info, 0, sizeof(info));
1197 info.rfe_type = (u8)hal->RFEType;
1198 rtw_hal_get_hwreg(adapter, HW_VAR_RF_TYPE, &val8);
1199 info.rf_type = _rf_type_drv2halmac(val8);
1201 status = api->halmac_send_general_info(halmac, &info);
1203 case HALMAC_RET_SUCCESS:
1205 case HALMAC_RET_NO_DLFW:
1206 RTW_WARN("%s: halmac_send_general_info() fail because fw not dl!\n",
1219 * 1. rtw_hal_get_hwreg(HW_VAR_RF_TYPE)
1220 * 2. HAL_DATA_TYPE.rfe_type
1221 * already ready for use before calling this function.
1223 static int _halmac_init_hal(struct dvobj_priv *d, u8 *fw, u32 fwsize)
1226 PHALMAC_ADAPTER halmac;
1228 HALMAC_RET_STATUS status;
1231 int err, err_ret = -1;
1234 adapter = d->padapters[IFACE_ID0];
1235 halmac = dvobj_to_halmac(d);
1238 api = HALMAC_GET_API(halmac);
1242 /* SKIP: halmac_init_adapter (Already done before) */
1244 /* halmac_pre_Init_system_cfg */
1245 /* halmac_mac_power_switch(on) */
1246 /* halmac_Init_system_cfg */
1247 ok = rtw_hal_power_on(adapter);
1254 d->hmpriv.send_general_info = 0;
1256 err = rtw_halmac_dlfw(d, fw, fwsize);
1263 status = init_mac_flow(d);
1264 if (status != HALMAC_RET_SUCCESS)
1267 /* halmac_send_general_info */
1268 if (_TRUE == fw_ok) {
1269 d->hmpriv.send_general_info = 0;
1270 err = _send_general_info(d);
1274 d->hmpriv.send_general_info = 1;
1276 /* Init Phy parameter-MAC */
1277 ok = rtw_hal_init_mac_register(adapter);
1281 /* StateMacInitialized */
1283 /* halmac_cfg_drv_info */
1284 err = rtw_halmac_config_rx_info(d, HALMAC_DRV_INFO_PHY_STATUS);
1288 /* halmac_set_hw_value(HALMAC_HW_EN_BB_RF) */
1290 ok = rtw_hal_init_phy(adapter);
1294 status = api->halmac_init_interface_cfg(halmac);
1295 if (status != HALMAC_RET_SUCCESS)
1298 /* SKIP: halmac_verify_platform_api */
1299 /* SKIP: halmac_h2c_lb */
1308 int rtw_halmac_init_hal(struct dvobj_priv *d)
1310 return _halmac_init_hal(d, NULL, 0);
1316 * 1. rtw_hal_get_hwreg(HW_VAR_RF_TYPE)
1317 * 2. HAL_DATA_TYPE.rfe_type
1318 * already ready for use before calling this function.
1320 int rtw_halmac_init_hal_fw(struct dvobj_priv *d, u8 *fw, u32 fwsize)
1322 return _halmac_init_hal(d, fw, fwsize);
1328 * 1. rtw_hal_get_hwreg(HW_VAR_RF_TYPE)
1329 * 2. HAL_DATA_TYPE.rfe_type
1330 * already ready for use before calling this function.
1332 int rtw_halmac_init_hal_fw_file(struct dvobj_priv *d, u8 *fwpath)
1335 u32 fwmaxsize, size = 0;
1339 fwmaxsize = FIRMWARE_MAX_SIZE;
1340 fw = rtw_zmalloc(fwmaxsize);
1344 size = rtw_retrieve_from_file(fwpath, fw, fwmaxsize);
1350 err = _halmac_init_hal(d, fw, size);
1353 rtw_mfree(fw, fwmaxsize);
1359 int rtw_halmac_deinit_hal(struct dvobj_priv *d)
1362 PHALMAC_ADAPTER halmac;
1364 HALMAC_RET_STATUS status;
1368 adapter = d->padapters[IFACE_ID0];
1369 halmac = dvobj_to_halmac(d);
1372 api = HALMAC_GET_API(halmac);
1374 status = api->halmac_deinit_interface_cfg(halmac);
1375 if (status != HALMAC_RET_SUCCESS)
1378 rtw_hal_power_off(adapter);
1385 int rtw_halmac_self_verify(struct dvobj_priv *d)
1387 PHALMAC_ADAPTER mac;
1389 HALMAC_RET_STATUS status;
1393 mac = dvobj_to_halmac(d);
1394 api = HALMAC_GET_API(mac);
1396 status = api->halmac_verify_platform_api(mac);
1397 if (status != HALMAC_RET_SUCCESS)
1400 status = api->halmac_h2c_lb(mac);
1401 if (status != HALMAC_RET_SUCCESS)
1409 int rtw_halmac_dlfw(struct dvobj_priv *d, u8 *fw, u32 fwsize)
1411 PHALMAC_ADAPTER mac;
1413 HALMAC_RET_STATUS status;
1416 HALMAC_FW_VERSION fw_vesion;
1419 mac = dvobj_to_halmac(d);
1420 api = HALMAC_GET_API(mac);
1421 hal = GET_HAL_DATA(d->padapters[IFACE_ID0]);
1423 if ((!fw) || (!fwsize))
1426 /* 1. Driver Stop Tx */
1429 /* 2. Driver Check Tx FIFO is empty */
1432 /* 3. Config MAX download size */
1433 #ifdef CONFIG_USB_HCI
1434 /* for USB do not exceed MAX_CMDBUF_SZ */
1435 api->halmac_cfg_max_dl_size(mac, 0x1000);
1436 #elif defined CONFIG_PCIE_HCI
1437 /* required a even length from u32 */
1438 api->halmac_cfg_max_dl_size(mac, (MAX_CMDBUF_SZ - TXDESC_OFFSET) & 0xFFFFFFFE);
1441 /* 4. Download Firmware */
1442 status = api->halmac_download_firmware(mac, fw, fwsize);
1443 if (HALMAC_RET_SUCCESS != status)
1446 if (d->hmpriv.send_general_info) {
1447 d->hmpriv.send_general_info = 0;
1448 err = _send_general_info(d);
1451 /* 5. Driver resume TX if needed */
1454 /* 6. Reset driver variables if needed */
1455 hal->LastHMEBoxNum = 0;
1458 /* 7. Get FW version */
1459 status = api->halmac_get_fw_version(mac, &fw_vesion);
1460 if (status == HALMAC_RET_SUCCESS) {
1461 hal->FirmwareVersion = fw_vesion.version;
1462 hal->FirmwareSubVersion = fw_vesion.sub_version;
1468 int rtw_halmac_dlfw_from_file(struct dvobj_priv *d, u8 *fwpath)
1471 u32 fwmaxsize, size = 0;
1475 fwmaxsize = FIRMWARE_MAX_SIZE;
1476 fw = rtw_zmalloc(fwmaxsize);
1480 size = rtw_retrieve_from_file(fwpath, fw, fwmaxsize);
1482 err = rtw_halmac_dlfw(d, fw, size);
1486 rtw_mfree(fw, fwmaxsize);
1494 * Power on/off BB/RF domain.
1497 * enable _TRUE/_FALSE for power on/off
1503 int rtw_halmac_phy_power_switch(struct dvobj_priv *d, u8 enable)
1506 PHALMAC_ADAPTER halmac;
1508 HALMAC_RET_STATUS status;
1511 adapter = d->padapters[IFACE_ID0];
1512 halmac = dvobj_to_halmac(d);
1515 api = HALMAC_GET_API(halmac);
1517 status = api->halmac_set_hw_value(halmac, HALMAC_HW_EN_BB_RF, &enable);
1518 if (status != HALMAC_RET_SUCCESS)
1524 static u8 _is_fw_read_cmd_down(PADAPTER adapter, u8 msgbox_num)
1526 u8 read_down = _FALSE;
1527 int retry_cnts = 100;
1530 /* RTW_INFO("_is_fw_read_cmd_down, reg_1cc(%x), msg_box(%d)...\n", rtw_read8(adapter, REG_HMETFR), msgbox_num); */
1533 valid = rtw_read8(adapter, REG_HMETFR) & BIT(msgbox_num);
1538 } while ((!read_down) && (retry_cnts--));
1543 int rtw_halmac_send_h2c(struct dvobj_priv *d, u8 *h2c)
1545 PADAPTER adapter = d->padapters[IFACE_ID0];
1546 PHAL_DATA_TYPE hal = GET_HAL_DATA(adapter);
1548 u32 msgbox_addr = 0;
1549 u32 msgbox_ex_addr = 0;
1554 if (adapter->bFWReady == _FALSE) {
1555 RTW_INFO("%s: return H2C cmd because fw is not ready\n", __FUNCTION__);
1560 RTW_INFO("%s: pbuf is NULL\n", __FUNCTION__);
1564 if (rtw_is_surprise_removed(adapter)) {
1565 RTW_INFO("%s: surprise removed\n", __FUNCTION__);
1569 _enter_critical_mutex(&d->h2c_fwcmd_mutex, NULL);
1571 /* pay attention to if race condition happened in H2C cmd setting */
1572 h2c_box_num = hal->LastHMEBoxNum;
1574 if (!_is_fw_read_cmd_down(adapter, h2c_box_num)) {
1575 RTW_INFO(" fw read cmd failed...\n");
1579 /* Write Ext command(byte 4 -7) */
1580 msgbox_ex_addr = REG_HMEBOX_E0 + (h2c_box_num * EX_MESSAGE_BOX_SIZE);
1581 _rtw_memcpy((u8 *)(&h2c_cmd_ex), h2c + 4, EX_MESSAGE_BOX_SIZE);
1582 h2c_cmd_ex = le32_to_cpu(h2c_cmd_ex);
1583 rtw_write32(adapter, msgbox_ex_addr, h2c_cmd_ex);
1585 /* Write command (byte 0 -3 ) */
1586 msgbox_addr = REG_HMEBOX0 + (h2c_box_num * MESSAGE_BOX_SIZE);
1587 _rtw_memcpy((u8 *)(&h2c_cmd), h2c, 4);
1588 h2c_cmd = le32_to_cpu(h2c_cmd);
1589 rtw_write32(adapter, msgbox_addr, h2c_cmd);
1591 /* update last msg box number */
1592 hal->LastHMEBoxNum = (h2c_box_num + 1) % MAX_H2C_BOX_NUMS;
1596 _exit_critical_mutex(&d->h2c_fwcmd_mutex, NULL);
1600 int rtw_halmac_c2h_handle(struct dvobj_priv *d, u8 *c2h, u32 size)
1602 PHALMAC_ADAPTER mac;
1604 HALMAC_RET_STATUS status;
1607 mac = dvobj_to_halmac(d);
1608 api = HALMAC_GET_API(mac);
1610 status = api->halmac_get_c2h_info(mac, c2h, size);
1611 if (HALMAC_RET_SUCCESS != status)
1617 int rtw_halmac_get_physical_efuse_size(struct dvobj_priv *d, u32 *size)
1619 PHALMAC_ADAPTER mac;
1621 HALMAC_RET_STATUS status;
1625 mac = dvobj_to_halmac(d);
1626 api = HALMAC_GET_API(mac);
1628 status = api->halmac_get_efuse_size(mac, &val);
1629 if (HALMAC_RET_SUCCESS != status)
1636 int rtw_halmac_read_physical_efuse_map(struct dvobj_priv *d, u8 *map, u32 size)
1638 PHALMAC_ADAPTER mac;
1640 HALMAC_RET_STATUS status;
1641 HALMAC_FEATURE_ID id;
1645 mac = dvobj_to_halmac(d);
1646 api = HALMAC_GET_API(mac);
1647 id = HALMAC_FEATURE_DUMP_PHYSICAL_EFUSE;
1649 ret = init_halmac_event(d, id, map, size);
1653 status = api->halmac_dump_efuse_map(mac, HALMAC_EFUSE_R_AUTO);
1654 if (HALMAC_RET_SUCCESS != status) {
1655 free_halmac_event(d, id);
1659 ret = wait_halmac_event(d, id);
1666 int rtw_halmac_read_physical_efuse(struct dvobj_priv *d, u32 offset, u32 cnt, u8 *data)
1668 PHALMAC_ADAPTER mac;
1670 HALMAC_RET_STATUS status;
1675 mac = dvobj_to_halmac(d);
1676 api = HALMAC_GET_API(mac);
1678 for (i = 0; i < cnt; i++) {
1679 status = api->halmac_read_efuse(mac, offset + i, &v);
1680 if (HALMAC_RET_SUCCESS != status)
1688 int rtw_halmac_write_physical_efuse(struct dvobj_priv *d, u32 offset, u32 cnt, u8 *data)
1690 PHALMAC_ADAPTER mac;
1692 HALMAC_RET_STATUS status;
1696 mac = dvobj_to_halmac(d);
1697 api = HALMAC_GET_API(mac);
1699 for (i = 0; i < cnt; i++) {
1700 status = api->halmac_write_efuse(mac, offset + i, data[i]);
1701 if (HALMAC_RET_SUCCESS != status)
1708 int rtw_halmac_get_logical_efuse_size(struct dvobj_priv *d, u32 *size)
1710 PHALMAC_ADAPTER mac;
1712 HALMAC_RET_STATUS status;
1716 mac = dvobj_to_halmac(d);
1717 api = HALMAC_GET_API(mac);
1719 status = api->halmac_get_logical_efuse_size(mac, &val);
1720 if (HALMAC_RET_SUCCESS != status)
1727 int rtw_halmac_read_logical_efuse_map(struct dvobj_priv *d, u8 *map, u32 size)
1729 PHALMAC_ADAPTER mac;
1731 HALMAC_RET_STATUS status;
1732 HALMAC_FEATURE_ID id;
1736 mac = dvobj_to_halmac(d);
1737 api = HALMAC_GET_API(mac);
1738 id = HALMAC_FEATURE_DUMP_LOGICAL_EFUSE;
1740 ret = init_halmac_event(d, id, map, size);
1744 status = api->halmac_dump_logical_efuse_map(mac, HALMAC_EFUSE_R_AUTO);
1745 if (HALMAC_RET_SUCCESS != status) {
1746 free_halmac_event(d, id);
1750 ret = wait_halmac_event(d, id);
1757 int rtw_halmac_write_logical_efuse_map(struct dvobj_priv *d, u8 *map, u32 size, u8 *maskmap, u32 masksize)
1759 PHALMAC_ADAPTER mac;
1761 HALMAC_PG_EFUSE_INFO pginfo;
1762 HALMAC_RET_STATUS status;
1765 mac = dvobj_to_halmac(d);
1766 api = HALMAC_GET_API(mac);
1768 pginfo.pEfuse_map = map;
1769 pginfo.efuse_map_size = size;
1770 pginfo.pEfuse_mask = maskmap;
1771 pginfo.efuse_mask_size = masksize;
1773 status = api->halmac_pg_efuse_by_map(mac, &pginfo, HALMAC_EFUSE_R_AUTO);
1774 if (HALMAC_RET_SUCCESS != status)
1780 int rtw_halmac_read_logical_efuse(struct dvobj_priv *d, u32 offset, u32 cnt, u8 *data)
1782 PHALMAC_ADAPTER mac;
1784 HALMAC_RET_STATUS status;
1789 mac = dvobj_to_halmac(d);
1790 api = HALMAC_GET_API(mac);
1792 for (i = 0; i < cnt; i++) {
1793 status = api->halmac_read_logical_efuse(mac, offset + i, &v);
1794 if (HALMAC_RET_SUCCESS != status)
1802 int rtw_halmac_write_logical_efuse(struct dvobj_priv *d, u32 offset, u32 cnt, u8 *data)
1804 PHALMAC_ADAPTER mac;
1806 HALMAC_RET_STATUS status;
1810 mac = dvobj_to_halmac(d);
1811 api = HALMAC_GET_API(mac);
1813 for (i = 0; i < cnt; i++) {
1814 status = api->halmac_write_logical_efuse(mac, offset + i, data[i]);
1815 if (HALMAC_RET_SUCCESS != status)
1822 int rtw_halmac_write_bt_physical_efuse(struct dvobj_priv *d, u32 offset, u32 cnt, u8 *data)
1824 PHALMAC_ADAPTER mac;
1826 HALMAC_RET_STATUS status;
1830 mac = dvobj_to_halmac(d);
1831 api = HALMAC_GET_API(mac);
1833 for (i = 0; i < cnt; i++) {
1834 status = api->halmac_write_efuse_bt(mac, offset + i, data[i], bank);
1835 if (HALMAC_RET_SUCCESS != status) {
1836 printk("%s: halmac_write_efuse_bt status = %d\n", __FUNCTION__, status);
1840 printk("%s: halmac_write_efuse_bt status = HALMAC_RET_SUCCESS %d\n", __FUNCTION__, status);
1845 int rtw_halmac_read_bt_physical_efuse_map(struct dvobj_priv *d, u8 *map, u32 size)
1847 PHALMAC_ADAPTER mac;
1849 HALMAC_RET_STATUS status;
1850 HALMAC_FEATURE_ID id;
1854 mac = dvobj_to_halmac(d);
1855 api = HALMAC_GET_API(mac);
1857 status = api->halmac_dump_efuse_map_bt(mac, bank, size, map);
1858 if (HALMAC_RET_SUCCESS != status) {
1859 printk("%s: halmac_dump_efuse_map_bt fail!\n", __FUNCTION__);
1863 printk("%s: OK!\n", __FUNCTION__);
1868 static inline u8 _hw_port_drv2halmac(enum _hw_port hwport)
1897 int rtw_halmac_set_mac_address(struct dvobj_priv *d, enum _hw_port hwport, u8 *addr)
1899 PHALMAC_ADAPTER halmac;
1902 HALMAC_WLAN_ADDR hwa;
1903 HALMAC_RET_STATUS status;
1907 halmac = dvobj_to_halmac(d);
1908 api = HALMAC_GET_API(halmac);
1910 port = _hw_port_drv2halmac(hwport);
1911 _rtw_memset(&hwa, 0, sizeof(hwa));
1912 _rtw_memcpy(hwa.Address, addr, 6);
1914 status = api->halmac_cfg_mac_addr(halmac, port, &hwa);
1915 if (status != HALMAC_RET_SUCCESS)
1923 int rtw_halmac_set_bssid(struct dvobj_priv *d, enum _hw_port hwport, u8 *addr)
1925 PHALMAC_ADAPTER halmac;
1928 HALMAC_WLAN_ADDR hwa;
1929 HALMAC_RET_STATUS status;
1932 halmac = dvobj_to_halmac(d);
1933 api = HALMAC_GET_API(halmac);
1934 port = _hw_port_drv2halmac(hwport);
1936 _rtw_memset(&hwa, 0, sizeof(HALMAC_WLAN_ADDR));
1937 _rtw_memcpy(hwa.Address, addr, 6);
1938 status = api->halmac_cfg_bssid(halmac, port, &hwa);
1939 if (status != HALMAC_RET_SUCCESS)
1947 int rtw_halmac_set_bandwidth(struct dvobj_priv *d, u8 channel, u8 pri_ch_idx, u8 bw)
1949 PHALMAC_ADAPTER mac;
1951 HALMAC_RET_STATUS status;
1954 mac = dvobj_to_halmac(d);
1955 api = HALMAC_GET_API(mac);
1957 status = api->halmac_cfg_ch_bw(mac, channel, pri_ch_idx, bw);
1958 if (HALMAC_RET_SUCCESS != status)
1964 int rtw_halmac_get_hw_value(struct dvobj_priv *d, HALMAC_HW_ID hw_id, VOID *pvalue)
1966 PHALMAC_ADAPTER mac;
1968 HALMAC_RET_STATUS status;
1971 mac = dvobj_to_halmac(d);
1972 api = HALMAC_GET_API(mac);
1974 status = api->halmac_get_hw_value(mac, hw_id, pvalue);
1975 if (HALMAC_RET_SUCCESS != status)
1981 int rtw_halmac_dump_fifo(struct dvobj_priv *d, HAL_FIFO_SEL halmac_fifo_sel)
1983 PHALMAC_ADAPTER mac;
1985 HALMAC_RET_STATUS status;
1986 u8 *pfifo_map = NULL;
1990 mac = dvobj_to_halmac(d);
1991 api = HALMAC_GET_API(mac);
1993 fifo_size = api->halmac_get_fifo_size(mac, halmac_fifo_sel);
1995 pfifo_map = rtw_vmalloc(fifo_size);
1996 if (pfifo_map == NULL)
1999 status = api->halmac_dump_fifo(mac, halmac_fifo_sel, pfifo_map, fifo_size);
2000 if (HALMAC_RET_SUCCESS != status) {
2007 rtw_vmfree(pfifo_map, fifo_size);
2012 int rtw_halmac_rx_agg_switch(struct dvobj_priv *d, u8 enable)
2016 PHALMAC_ADAPTER halmac;
2018 HALMAC_RXAGG_CFG rxaggcfg;
2019 HALMAC_RET_STATUS status;
2023 adapter = d->padapters[IFACE_ID0];
2024 hal = GET_HAL_DATA(adapter);
2025 halmac = dvobj_to_halmac(d);
2026 api = HALMAC_GET_API(halmac);
2027 _rtw_memset((void *)&rxaggcfg, 0, sizeof(rxaggcfg));
2029 if (_TRUE == enable) {
2030 #ifdef CONFIG_SDIO_HCI
2031 rxaggcfg.mode = HALMAC_RX_AGG_MODE_DMA;
2032 rxaggcfg.threshold.drv_define = 0;
2033 #elif defined(CONFIG_USB_HCI) && defined(CONFIG_USB_RX_AGGREGATION)
2034 switch (hal->rxagg_mode) {
2035 case RX_AGG_DISABLE:
2036 rxaggcfg.mode = HALMAC_RX_AGG_MODE_NONE;
2040 rxaggcfg.mode = HALMAC_RX_AGG_MODE_DMA;
2041 if (hal->rxagg_dma_size || hal->rxagg_dma_timeout) {
2042 rxaggcfg.threshold.drv_define = 1;
2043 rxaggcfg.threshold.timeout = hal->rxagg_dma_timeout;
2044 rxaggcfg.threshold.size = hal->rxagg_dma_size;
2050 rxaggcfg.mode = HALMAC_RX_AGG_MODE_USB;
2051 if (hal->rxagg_usb_size || hal->rxagg_usb_timeout) {
2052 rxaggcfg.threshold.drv_define = 1;
2053 rxaggcfg.threshold.timeout = hal->rxagg_usb_timeout;
2054 rxaggcfg.threshold.size = hal->rxagg_usb_size;
2058 #endif /* CONFIG_USB_HCI */
2060 rxaggcfg.mode = HALMAC_RX_AGG_MODE_NONE;
2062 status = api->halmac_cfg_rx_aggregation(halmac, &rxaggcfg);
2063 if (status != HALMAC_RET_SUCCESS)
2071 int rtw_halmac_get_wow_reason(struct dvobj_priv *d, u8 *reason)
2078 adapter = d->padapters[IFACE_ID0];
2080 val8 = rtw_read8(adapter, 0x1C7);
2092 * Get RX driver info size. RX driver info is a small memory space between
2093 * scriptor and RX payload.
2095 * +-------------------------+
2097 * | usually 24 bytes |
2098 * +-------------------------+
2099 * | RX driver info |
2100 * | depends on driver cfg |
2101 * +-------------------------+
2104 * +-------------------------+
2107 * d pointer to struct dvobj_priv of driver
2108 * sz rx driver info size in bytes.
2114 int rtw_halmac_get_drv_info_sz(struct dvobj_priv *d, u8 *sz)
2116 HALMAC_RET_STATUS status;
2117 PHALMAC_ADAPTER halmac = dvobj_to_halmac(d);
2118 PHALMAC_API api = HALMAC_GET_API(halmac);
2121 status = api->halmac_get_hw_value(halmac, HALMAC_HW_DRV_INFO_SIZE, &dw);
2122 if (status != HALMAC_RET_SUCCESS)
2128 int rtw_halmac_get_rsvd_drv_pg_bndy(struct dvobj_priv *dvobj, u16 *drv_pg)
2130 HALMAC_RET_STATUS status;
2131 PHALMAC_ADAPTER halmac = dvobj_to_halmac(dvobj);
2132 PHALMAC_API api = HALMAC_GET_API(halmac);
2134 status = api->halmac_get_hw_value(halmac, HALMAC_HW_RSVD_PG_BNDY, drv_pg);
2135 if (status != HALMAC_RET_SUCCESS)
2141 int rtw_halmac_download_rsvd_page(struct dvobj_priv *dvobj, u8 pg_offset, u8 *pbuf, u32 size)
2143 HALMAC_RET_STATUS status = HALMAC_RET_SUCCESS;
2144 PHALMAC_ADAPTER halmac = dvobj_to_halmac(dvobj);
2145 PHALMAC_API api = HALMAC_GET_API(halmac);
2147 status = api->halmac_dl_drv_rsvd_page(halmac, pg_offset, pbuf, size);
2148 if (status != HALMAC_RET_SUCCESS)
2155 #ifdef CONFIG_SDIO_HCI
2159 * Update queue allocated page number to driver
2162 * d pointer to struct dvobj_priv of driver
2165 * 0 Success, "page" is valid.
2166 * others Fail, "page" is invalid.
2168 int rtw_halmac_query_tx_page_num(struct dvobj_priv *d)
2171 struct halmacpriv *hmpriv;
2172 PHALMAC_ADAPTER halmac;
2174 HALMAC_RQPN_MAP rqpn;
2175 HALMAC_DMA_MAPPING dmaqueue;
2176 HALMAC_TXFF_ALLOCATION fifosize;
2177 HALMAC_RET_STATUS status;
2181 adapter = d->padapters[IFACE_ID0];
2182 hmpriv = &d->hmpriv;
2183 halmac = dvobj_to_halmac(d);
2184 api = HALMAC_GET_API(halmac);
2185 _rtw_memset((void *)&rqpn, 0, sizeof(rqpn));
2186 _rtw_memset((void *)&fifosize, 0, sizeof(fifosize));
2188 status = api->halmac_get_hw_value(halmac, HALMAC_HW_RQPN_MAPPING, &rqpn);
2189 if (status != HALMAC_RET_SUCCESS)
2191 status = api->halmac_get_hw_value(halmac, HALMAC_HW_TXFF_ALLOCATION, &fifosize);
2192 if (status != HALMAC_RET_SUCCESS)
2195 for (i = 0; i < HW_QUEUE_ENTRY; i++) {
2196 hmpriv->txpage[i] = 0;
2198 /* Driver index mapping to HALMAC DMA queue */
2199 dmaqueue = HALMAC_DMA_MAPPING_UNDEFINE;
2202 dmaqueue = rqpn.dma_map_vo;
2205 dmaqueue = rqpn.dma_map_vi;
2208 dmaqueue = rqpn.dma_map_be;
2211 dmaqueue = rqpn.dma_map_bk;
2214 dmaqueue = rqpn.dma_map_mg;
2216 case HIGH_QUEUE_INX:
2217 dmaqueue = rqpn.dma_map_hi;
2220 case TXCMD_QUEUE_INX:
2222 hmpriv->txpage[i] = 0xFFFF;
2227 case HALMAC_DMA_MAPPING_EXTRA:
2228 hmpriv->txpage[i] = fifosize.extra_queue_pg_num;
2230 case HALMAC_DMA_MAPPING_LOW:
2231 hmpriv->txpage[i] = fifosize.low_queue_pg_num;
2233 case HALMAC_DMA_MAPPING_NORMAL:
2234 hmpriv->txpage[i] = fifosize.normal_queue_pg_num;
2236 case HALMAC_DMA_MAPPING_HIGH:
2237 hmpriv->txpage[i] = fifosize.high_queue_pg_num;
2239 case HALMAC_DMA_MAPPING_UNDEFINE:
2242 hmpriv->txpage[i] += fifosize.pub_queue_pg_num;
2250 * Get specific queue allocated page number
2253 * d pointer to struct dvobj_priv of driver
2254 * queue target queue to query, VO/VI/BE/BK/.../TXCMD_QUEUE_INX
2255 * page return allocated page number
2258 * 0 Success, "page" is valid.
2259 * others Fail, "page" is invalid.
2261 int rtw_halmac_get_tx_queue_page_num(struct dvobj_priv *d, u8 queue, u32 *page)
2264 if (queue < HW_QUEUE_ENTRY)
2265 *page = d->hmpriv.txpage[queue];
2272 * address for SDIO command
2274 u32 rtw_halmac_sdio_get_tx_addr(struct dvobj_priv *d, u8 *desc, u32 size)
2276 PHALMAC_ADAPTER mac;
2278 HALMAC_RET_STATUS status;
2282 mac = dvobj_to_halmac(d);
2283 api = HALMAC_GET_API(mac);
2285 status = api->halmac_get_sdio_tx_addr(mac, desc, size, &addr);
2286 if (HALMAC_RET_SUCCESS != status)
2292 int rtw_halmac_sdio_tx_allowed(struct dvobj_priv *d, u8 *buf, u32 size)
2294 PHALMAC_ADAPTER mac;
2296 HALMAC_RET_STATUS status;
2299 mac = dvobj_to_halmac(d);
2300 api = HALMAC_GET_API(mac);
2302 status = api->halmac_tx_allowed_sdio(mac, buf, size);
2303 if (HALMAC_RET_SUCCESS != status)
2309 u32 rtw_halmac_sdio_get_rx_addr(struct dvobj_priv *d, u8 *seq)
2313 #define RTW_SDIO_ADDR_RX_RX0FF_PRFIX 0x0E000
2314 #define RTW_SDIO_ADDR_RX_RX0FF_GEN(a) (RTW_SDIO_ADDR_RX_RX0FF_PRFIX|(a&0x3))
2318 return RTW_SDIO_ADDR_RX_RX0FF_GEN(id);
2320 #endif /* CONFIG_SDIO_HCI */
2322 #ifdef CONFIG_USB_HCI
2323 u8 rtw_halmac_usb_get_bulkout_id(struct dvobj_priv *d, u8 *buf, u32 size)
2325 PHALMAC_ADAPTER mac;
2327 HALMAC_RET_STATUS status;
2331 mac = dvobj_to_halmac(d);
2332 api = HALMAC_GET_API(mac);
2334 status = api->halmac_get_usb_bulkout_id(mac, buf, size, &bulkout_id);
2335 if (HALMAC_RET_SUCCESS != status)
2341 static inline HALMAC_USB_MODE _usb_mode_drv2halmac(enum RTW_USB_SPEED usb_mode)
2343 HALMAC_USB_MODE halmac_usb_mode = HALMAC_USB_MODE_U2;
2346 case RTW_USB_SPEED_2:
2347 halmac_usb_mode = HALMAC_USB_MODE_U2;
2349 case RTW_USB_SPEED_3:
2350 halmac_usb_mode = HALMAC_USB_MODE_U3;
2353 halmac_usb_mode = HALMAC_USB_MODE_U2;
2357 return halmac_usb_mode;
2360 u8 rtw_halmac_switch_usb_mode(struct dvobj_priv *d, enum RTW_USB_SPEED usb_mode)
2362 PHALMAC_ADAPTER mac;
2364 HALMAC_RET_STATUS status;
2366 HALMAC_USB_MODE halmac_usb_mode;
2368 adapter = d->padapters[IFACE_ID0];
2369 mac = dvobj_to_halmac(d);
2370 api = HALMAC_GET_API(mac);
2371 halmac_usb_mode = _usb_mode_drv2halmac(usb_mode);
2372 status = api->halmac_set_hw_value(mac, HALMAC_HW_USB_MODE, (void *)&halmac_usb_mode);
2374 if (HALMAC_RET_SUCCESS != status)
2379 #endif /* CONFIG_USB_HCI */