drivers/net/wireless/rockchip_wlan/rtl8723ds/hal/hal_mp.c

   1 /******************************************************************************
   2  *
   3  * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of version 2 of the GNU General Public License as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program; if not, write to the Free Software Foundation, Inc.,
  16  * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  17  *
  18  *
  19  ******************************************************************************/
  20 #define _HAL_MP_C_
  21
  22 #include <drv_types.h>
  23
  24 #ifdef CONFIG_MP_INCLUDED
  25
  26 #ifdef RTW_HALMAC
  27         #include <hal_data.h>           /* struct HAL_DATA_TYPE, RF register definition and etc. */
  28 #else /* !RTW_HALMAC */
  29         #ifdef CONFIG_RTL8188E
  30                 #include <rtl8188e_hal.h>
  31         #endif
  32         #ifdef CONFIG_RTL8723B
  33                 #include <rtl8723b_hal.h>
  34         #endif
  35         #ifdef CONFIG_RTL8192E
  36                 #include <rtl8192e_hal.h>
  37         #endif
  38         #ifdef CONFIG_RTL8814A
  39                 #include <rtl8814a_hal.h>
  40         #endif
  41         #if defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A)
  42                 #include <rtl8812a_hal.h>
  43         #endif
  44         #ifdef CONFIG_RTL8703B
  45                 #include <rtl8703b_hal.h>
  46         #endif
  47         #ifdef CONFIG_RTL8723D
  48                 #include <rtl8723d_hal.h>
  49         #endif
  50         #ifdef CONFIG_RTL8188F
  51                 #include <rtl8188f_hal.h>
  52         #endif
  53 #endif /* !RTW_HALMAC */
  54
  55
  56 u8 MgntQuery_NssTxRate(u16 Rate)
  57 {
  58         u8      NssNum = RF_TX_NUM_NONIMPLEMENT;
  59
  60         if ((Rate >= MGN_MCS8 && Rate <= MGN_MCS15) ||
  61             (Rate >= MGN_VHT2SS_MCS0 && Rate <= MGN_VHT2SS_MCS9))
  62                 NssNum = RF_2TX;
  63         else if ((Rate >= MGN_MCS16 && Rate <= MGN_MCS23) ||
  64                  (Rate >= MGN_VHT3SS_MCS0 && Rate <= MGN_VHT3SS_MCS9))
  65                 NssNum = RF_3TX;
  66         else if ((Rate >= MGN_MCS24 && Rate <= MGN_MCS31) ||
  67                  (Rate >= MGN_VHT4SS_MCS0 && Rate <= MGN_VHT4SS_MCS9))
  68                 NssNum = RF_4TX;
  69         else
  70                 NssNum = RF_1TX;
  71
  72         return NssNum;
  73 }
  74
  75 void hal_mpt_SwitchRfSetting(PADAPTER   pAdapter)
  76 {
  77         HAL_DATA_TYPE           *pHalData = GET_HAL_DATA(pAdapter);
  78         PMPT_CONTEXT            pMptCtx = &(pAdapter->mppriv.MptCtx);
  79         u8                              ChannelToSw = pMptCtx->MptChannelToSw;
  80         ULONG                           ulRateIdx = pMptCtx->MptRateIndex;
  81         ULONG                           ulbandwidth = pMptCtx->MptBandWidth;
  82
  83         /* <20120525, Kordan> Dynamic mechanism for APK, asked by Dennis.*/
  84         if (IS_HARDWARE_TYPE_8188ES(pAdapter) && (1 <= ChannelToSw && ChannelToSw <= 11) &&
  85             (ulRateIdx == MPT_RATE_MCS0 || ulRateIdx == MPT_RATE_1M || ulRateIdx == MPT_RATE_6M)) {
  86                 pMptCtx->backup0x52_RF_A = (u1Byte)PHY_QueryRFReg(pAdapter, ODM_RF_PATH_A, RF_0x52, 0x000F0);
  87                 pMptCtx->backup0x52_RF_B = (u1Byte)PHY_QueryRFReg(pAdapter, ODM_RF_PATH_B, RF_0x52, 0x000F0);
  88
  89                 if ((PlatformEFIORead4Byte(pAdapter, 0xF4) & BIT29) == BIT29) {
  90                         PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, RF_0x52, 0x000F0, 0xB);
  91                         PHY_SetRFReg(pAdapter, ODM_RF_PATH_B, RF_0x52, 0x000F0, 0xB);
  92                 } else {
  93                         PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, RF_0x52, 0x000F0, 0xD);
  94                         PHY_SetRFReg(pAdapter, ODM_RF_PATH_B, RF_0x52, 0x000F0, 0xD);
  95                 }
  96         } else if (IS_HARDWARE_TYPE_8188EE(pAdapter)) { /* <20140903, VincentL> Asked by RF Eason and Edlu*/
  97                 if (ChannelToSw == 3 && ulbandwidth == MPT_BW_40MHZ) {
  98                         PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, RF_0x52, 0x000F0, 0xB); /*RF 0x52 = 0x0007E4BD*/
  99                         PHY_SetRFReg(pAdapter, ODM_RF_PATH_B, RF_0x52, 0x000F0, 0xB); /*RF 0x52 = 0x0007E4BD*/
 100                 } else {
 101                         PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, RF_0x52, 0x000F0, 0x9); /*RF 0x52 = 0x0007E49D*/
 102                         PHY_SetRFReg(pAdapter, ODM_RF_PATH_B, RF_0x52, 0x000F0, 0x9); /*RF 0x52 = 0x0007E49D*/
 103                 }
 104         } else if (IS_HARDWARE_TYPE_8188E(pAdapter)) {
 105                 PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, RF_0x52, 0x000F0, pMptCtx->backup0x52_RF_A);
 106                 PHY_SetRFReg(pAdapter, ODM_RF_PATH_B, RF_0x52, 0x000F0, pMptCtx->backup0x52_RF_B);
 107         }
 108 }
 109
 110 s32 hal_mpt_SetPowerTracking(PADAPTER padapter, u8 enable)
 111 {
 112         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(padapter);
 113         PDM_ODM_T               pDM_Odm = &(pHalData->odmpriv);
 114
 115
 116         if (!netif_running(padapter->pnetdev)) {
 117                 return _FAIL;
 118         }
 119
 120         if (check_fwstate(&padapter->mlmepriv, WIFI_MP_STATE) == _FALSE) {
 121                 return _FAIL;
 122         }
 123         if (enable)
 124                 pDM_Odm->RFCalibrateInfo.TxPowerTrackControl = _TRUE;
 125         else
 126                 pDM_Odm->RFCalibrateInfo.TxPowerTrackControl = _FALSE;
 127
 128         return _SUCCESS;
 129 }
 130
 131 void hal_mpt_GetPowerTracking(PADAPTER padapter, u8 *enable)
 132 {
 133         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(padapter);
 134         PDM_ODM_T               pDM_Odm = &(pHalData->odmpriv);
 135
 136
 137         *enable = pDM_Odm->RFCalibrateInfo.TxPowerTrackControl;
 138 }
 139
 140
 141 void hal_mpt_CCKTxPowerAdjust(PADAPTER Adapter, BOOLEAN bInCH14)
 142 {
 143         u32             TempVal = 0, TempVal2 = 0, TempVal3 = 0;
 144         u32             CurrCCKSwingVal = 0, CCKSwingIndex = 12;
 145         u8              i;
 146         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(Adapter);
 147         PMPT_CONTEXT            pMptCtx = &(Adapter->mppriv.MptCtx);
 148         u1Byte                          u1Channel = pHalData->CurrentChannel;
 149         ULONG                           ulRateIdx = pMptCtx->MptRateIndex;
 150         u1Byte                          DataRate = 0xFF;
 151
 152         /* Suggested by BB David. 2015.04.27*/
 153         if(IS_HARDWARE_TYPE_8188F(Adapter))
 154                 return;
 155
 156         /* Do not modify CCK TX filter parameters for 8822B*/
 157         if(IS_HARDWARE_TYPE_8822B(Adapter) || IS_HARDWARE_TYPE_8821C(Adapter) || IS_HARDWARE_TYPE_8723D(Adapter))
 158                 return;
 159
 160         DataRate = MptToMgntRate(ulRateIdx);
 161
 162         if (u1Channel == 14 && IS_CCK_RATE(DataRate))
 163                 pHalData->bCCKinCH14 = TRUE;
 164         else
 165                 pHalData->bCCKinCH14 = FALSE;
 166
 167         if (IS_HARDWARE_TYPE_8703B(Adapter)) {
 168                 if ((u1Channel == 14) && IS_CCK_RATE(DataRate)) {
 169                         /* Channel 14 in CCK, need to set 0xA26~0xA29 to 0 for 8703B */
 170                         PHY_SetBBReg(Adapter, rCCK0_TxFilter2, bMaskHWord, 0);
 171                         PHY_SetBBReg(Adapter, rCCK0_DebugPort, bMaskLWord, 0);
 172
 173                 } else {
 174                         /* Normal setting for 8703B, just recover to the default setting. */
 175                         /* This hardcore values reference from the parameter which BB team gave. */
 176                         for (i = 0 ; i < 2 ; ++i)
 177                                 PHY_SetBBReg(Adapter, pHalData->RegForRecover[i].offset, bMaskDWord, pHalData->RegForRecover[i].value);
 178
 179                 }
 180         } else if (IS_HARDWARE_TYPE_8723D(Adapter)) {
 181                 /* 2.4G CCK TX DFIR */
 182                 /* 2016.01.20 Suggest from RS BB mingzhi*/
 183                 if ((u1Channel == 14)) {
 184                         PHY_SetBBReg(Adapter, rCCK0_TxFilter2, bMaskDWord, 0x0000B81C);
 185                         PHY_SetBBReg(Adapter, rCCK0_DebugPort, bMaskDWord, 0x00000000);
 186                         PHY_SetBBReg(Adapter, 0xAAC, bMaskDWord, 0x00003667);
 187                 } else {
 188                         for (i = 0 ; i < 3 ; ++i) {
 189                                 PHY_SetBBReg(Adapter,
 190                                              pHalData->RegForRecover[i].offset,
 191                                              bMaskDWord,
 192                                              pHalData->RegForRecover[i].value);
 193                         }
 194                 }
 195         } else {
 196
 197                 /* get current cck swing value and check 0xa22 & 0xa23 later to match the table.*/
 198                 CurrCCKSwingVal = read_bbreg(Adapter, rCCK0_TxFilter1, bMaskHWord);
 199
 200                 if (!pHalData->bCCKinCH14) {
 201                         /* Readback the current bb cck swing value and compare with the table to */
 202                         /* get the current swing index */
 203                         for (i = 0; i < CCK_TABLE_SIZE; i++) {
 204                                 if (((CurrCCKSwingVal & 0xff) == (u32)CCKSwingTable_Ch1_Ch13[i][0]) &&
 205                                     (((CurrCCKSwingVal & 0xff00) >> 8) == (u32)CCKSwingTable_Ch1_Ch13[i][1])) {
 206                                         CCKSwingIndex = i;
 207                                         break;
 208                                 }
 209                         }
 210
 211                         /*Write 0xa22 0xa23*/
 212                         TempVal = CCKSwingTable_Ch1_Ch13[CCKSwingIndex][0] +
 213                                 (CCKSwingTable_Ch1_Ch13[CCKSwingIndex][1] << 8);
 214
 215
 216                         /*Write 0xa24 ~ 0xa27*/
 217                         TempVal2 = 0;
 218                         TempVal2 = CCKSwingTable_Ch1_Ch13[CCKSwingIndex][2] +
 219                                 (CCKSwingTable_Ch1_Ch13[CCKSwingIndex][3] << 8) +
 220                                 (CCKSwingTable_Ch1_Ch13[CCKSwingIndex][4] << 16) +
 221                                 (CCKSwingTable_Ch1_Ch13[CCKSwingIndex][5] << 24);
 222
 223                         /*Write 0xa28  0xa29*/
 224                         TempVal3 = 0;
 225                         TempVal3 = CCKSwingTable_Ch1_Ch13[CCKSwingIndex][6] +
 226                                 (CCKSwingTable_Ch1_Ch13[CCKSwingIndex][7] << 8);
 227                 }  else {
 228                         for (i = 0; i < CCK_TABLE_SIZE; i++) {
 229                                 if (((CurrCCKSwingVal & 0xff) == (u32)CCKSwingTable_Ch14[i][0]) &&
 230                                     (((CurrCCKSwingVal & 0xff00) >> 8) == (u32)CCKSwingTable_Ch14[i][1])) {
 231                                         CCKSwingIndex = i;
 232                                         break;
 233                                 }
 234                         }
 235
 236                         /*Write 0xa22 0xa23*/
 237                         TempVal = CCKSwingTable_Ch14[CCKSwingIndex][0] +
 238                                   (CCKSwingTable_Ch14[CCKSwingIndex][1] << 8);
 239
 240                         /*Write 0xa24 ~ 0xa27*/
 241                         TempVal2 = 0;
 242                         TempVal2 = CCKSwingTable_Ch14[CCKSwingIndex][2] +
 243                                    (CCKSwingTable_Ch14[CCKSwingIndex][3] << 8) +
 244                                 (CCKSwingTable_Ch14[CCKSwingIndex][4] << 16) +
 245                                    (CCKSwingTable_Ch14[CCKSwingIndex][5] << 24);
 246
 247                         /*Write 0xa28  0xa29*/
 248                         TempVal3 = 0;
 249                         TempVal3 = CCKSwingTable_Ch14[CCKSwingIndex][6] +
 250                                    (CCKSwingTable_Ch14[CCKSwingIndex][7] << 8);
 251                 }
 252
 253                 write_bbreg(Adapter, rCCK0_TxFilter1, bMaskHWord, TempVal);
 254                 write_bbreg(Adapter, rCCK0_TxFilter2, bMaskDWord, TempVal2);
 255                 write_bbreg(Adapter, rCCK0_DebugPort, bMaskLWord, TempVal3);
 256         }
 257
 258 }
 259
 260 void hal_mpt_SetChannel(PADAPTER pAdapter)
 261 {
 262         u8 eRFPath;
 263         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(pAdapter);
 264         PDM_ODM_T               pDM_Odm = &(pHalData->odmpriv);
 265         struct mp_priv  *pmp = &pAdapter->mppriv;
 266         u8              channel = pmp->channel;
 267         u8              bandwidth = pmp->bandwidth;
 268
 269         hal_mpt_SwitchRfSetting(pAdapter);
 270
 271         pHalData->bSwChnl = _TRUE;
 272         pHalData->bSetChnlBW = _TRUE;
 273         rtw_hal_set_chnl_bw(pAdapter, channel, bandwidth, 0, 0);
 274
 275         hal_mpt_CCKTxPowerAdjust(pAdapter, pHalData->bCCKinCH14);
 276
 277 }
 278
 279 /*
 280  * Notice
 281  *      Switch bandwitdth may change center frequency(channel)
 282  */
 283 void hal_mpt_SetBandwidth(PADAPTER pAdapter)
 284 {
 285         struct mp_priv *pmp = &pAdapter->mppriv;
 286         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(pAdapter);
 287
 288         u8              channel = pmp->channel;
 289         u8              bandwidth = pmp->bandwidth;
 290
 291         pHalData->bSwChnl = _TRUE;
 292         pHalData->bSetChnlBW = _TRUE;
 293         rtw_hal_set_chnl_bw(pAdapter, channel, bandwidth, 0, 0);
 294
 295         hal_mpt_SwitchRfSetting(pAdapter);
 296 }
 297
 298 void mpt_SetTxPower_Old(PADAPTER pAdapter, MPT_TXPWR_DEF Rate, u8 *pTxPower)
 299 {
 300         switch (Rate) {
 301         case MPT_CCK: {
 302                 u4Byte  TxAGC = 0, pwr = 0;
 303                 u1Byte  rf;
 304
 305                 pwr = pTxPower[ODM_RF_PATH_A];
 306                 if (pwr < 0x3f) {
 307                         TxAGC = (pwr << 16) | (pwr << 8) | (pwr);
 308                         PHY_SetBBReg(pAdapter, rTxAGC_A_CCK1_Mcs32, bMaskByte1, pTxPower[ODM_RF_PATH_A]);
 309                         PHY_SetBBReg(pAdapter, rTxAGC_B_CCK11_A_CCK2_11, 0xffffff00, TxAGC);
 310                 }
 311                 pwr = pTxPower[ODM_RF_PATH_B];
 312                 if (pwr < 0x3f) {
 313                         TxAGC = (pwr << 16) | (pwr << 8) | (pwr);
 314                         PHY_SetBBReg(pAdapter, rTxAGC_B_CCK11_A_CCK2_11, bMaskByte0, pTxPower[ODM_RF_PATH_B]);
 315                         PHY_SetBBReg(pAdapter, rTxAGC_B_CCK1_55_Mcs32, 0xffffff00, TxAGC);
 316                 }
 317         }
 318         break;
 319
 320         case MPT_OFDM_AND_HT: {
 321                 u4Byte  TxAGC = 0;
 322                 u1Byte  pwr = 0, rf;
 323
 324                 pwr = pTxPower[0];
 325                 if (pwr < 0x3f) {
 326                         TxAGC |= ((pwr << 24) | (pwr << 16) | (pwr << 8) | pwr);
 327                         RTW_INFO("HT Tx-rf(A) Power = 0x%x\n", TxAGC);
 328                         PHY_SetBBReg(pAdapter, rTxAGC_A_Rate18_06, bMaskDWord, TxAGC);
 329                         PHY_SetBBReg(pAdapter, rTxAGC_A_Rate54_24, bMaskDWord, TxAGC);
 330                         PHY_SetBBReg(pAdapter, rTxAGC_A_Mcs03_Mcs00, bMaskDWord, TxAGC);
 331                         PHY_SetBBReg(pAdapter, rTxAGC_A_Mcs07_Mcs04, bMaskDWord, TxAGC);
 332                         PHY_SetBBReg(pAdapter, rTxAGC_A_Mcs11_Mcs08, bMaskDWord, TxAGC);
 333                         PHY_SetBBReg(pAdapter, rTxAGC_A_Mcs15_Mcs12, bMaskDWord, TxAGC);
 334                 }
 335                 TxAGC = 0;
 336                 pwr = pTxPower[1];
 337                 if (pwr < 0x3f) {
 338                         TxAGC |= ((pwr << 24) | (pwr << 16) | (pwr << 8) | pwr);
 339                         RTW_INFO("HT Tx-rf(B) Power = 0x%x\n", TxAGC);
 340                         PHY_SetBBReg(pAdapter, rTxAGC_B_Rate18_06, bMaskDWord, TxAGC);
 341                         PHY_SetBBReg(pAdapter, rTxAGC_B_Rate54_24, bMaskDWord, TxAGC);
 342                         PHY_SetBBReg(pAdapter, rTxAGC_B_Mcs03_Mcs00, bMaskDWord, TxAGC);
 343                         PHY_SetBBReg(pAdapter, rTxAGC_B_Mcs07_Mcs04, bMaskDWord, TxAGC);
 344                         PHY_SetBBReg(pAdapter, rTxAGC_B_Mcs11_Mcs08, bMaskDWord, TxAGC);
 345                         PHY_SetBBReg(pAdapter, rTxAGC_B_Mcs15_Mcs12, bMaskDWord, TxAGC);
 346                 }
 347         }
 348         break;
 349
 350         default:
 351                 break;
 352         }
 353         RTW_INFO("<===mpt_SetTxPower_Old()\n");
 354 }
 355
 356 void
 357 mpt_SetTxPower(
 358         PADAPTER                pAdapter,
 359         MPT_TXPWR_DEF   Rate,
 360         pu1Byte pTxPower
 361 )
 362 {
 363         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(pAdapter);
 364
 365         u1Byte path = 0 , i = 0, MaxRate = MGN_6M;
 366         u1Byte StartPath = ODM_RF_PATH_A, EndPath = ODM_RF_PATH_B;
 367
 368         if (IS_HARDWARE_TYPE_8814A(pAdapter))
 369                 EndPath = ODM_RF_PATH_D;
 370         else if (IS_HARDWARE_TYPE_8188F(pAdapter) || IS_HARDWARE_TYPE_8723D(pAdapter) || IS_HARDWARE_TYPE_8821C(pAdapter))
 371                 EndPath = ODM_RF_PATH_A;
 372
 373         switch (Rate) {
 374         case MPT_CCK: {
 375                 u1Byte rate[] = {MGN_1M, MGN_2M, MGN_5_5M, MGN_11M};
 376
 377                 for (path = StartPath; path <= EndPath; path++)
 378                         for (i = 0; i < sizeof(rate); ++i)
 379                                 PHY_SetTxPowerIndex(pAdapter, pTxPower[path], path, rate[i]);
 380         }
 381         break;
 382         case MPT_OFDM: {
 383                 u1Byte rate[] = {
 384                         MGN_6M, MGN_9M, MGN_12M, MGN_18M,
 385                         MGN_24M, MGN_36M, MGN_48M, MGN_54M,
 386                 };
 387
 388                 for (path = StartPath; path <= EndPath; path++)
 389                         for (i = 0; i < sizeof(rate); ++i)
 390                                 PHY_SetTxPowerIndex(pAdapter, pTxPower[path], path, rate[i]);
 391         }
 392         break;
 393         case MPT_HT: {
 394                 u1Byte rate[] = {
 395                         MGN_MCS0, MGN_MCS1, MGN_MCS2, MGN_MCS3, MGN_MCS4,
 396                         MGN_MCS5, MGN_MCS6, MGN_MCS7, MGN_MCS8, MGN_MCS9,
 397                         MGN_MCS10, MGN_MCS11, MGN_MCS12, MGN_MCS13, MGN_MCS14,
 398                         MGN_MCS15, MGN_MCS16, MGN_MCS17, MGN_MCS18, MGN_MCS19,
 399                         MGN_MCS20, MGN_MCS21, MGN_MCS22, MGN_MCS23, MGN_MCS24,
 400                         MGN_MCS25, MGN_MCS26, MGN_MCS27, MGN_MCS28, MGN_MCS29,
 401                         MGN_MCS30, MGN_MCS31,
 402                 };
 403                 if (pHalData->rf_type == RF_3T3R)
 404                         MaxRate = MGN_MCS23;
 405                 else if (pHalData->rf_type == RF_2T2R)
 406                         MaxRate = MGN_MCS15;
 407                 else
 408                         MaxRate = MGN_MCS7;
 409                 for (path = StartPath; path <= EndPath; path++) {
 410                         for (i = 0; i < sizeof(rate); ++i) {
 411                                 if (rate[i] > MaxRate)
 412                                         break;
 413                                 PHY_SetTxPowerIndex(pAdapter, pTxPower[path], path, rate[i]);
 414                         }
 415                 }
 416         }
 417         break;
 418         case MPT_VHT: {
 419                 u1Byte rate[] = {
 420                         MGN_VHT1SS_MCS0, MGN_VHT1SS_MCS1, MGN_VHT1SS_MCS2, MGN_VHT1SS_MCS3, MGN_VHT1SS_MCS4,
 421                         MGN_VHT1SS_MCS5, MGN_VHT1SS_MCS6, MGN_VHT1SS_MCS7, MGN_VHT1SS_MCS8, MGN_VHT1SS_MCS9,
 422                         MGN_VHT2SS_MCS0, MGN_VHT2SS_MCS1, MGN_VHT2SS_MCS2, MGN_VHT2SS_MCS3, MGN_VHT2SS_MCS4,
 423                         MGN_VHT2SS_MCS5, MGN_VHT2SS_MCS6, MGN_VHT2SS_MCS7, MGN_VHT2SS_MCS8, MGN_VHT2SS_MCS9,
 424                         MGN_VHT3SS_MCS0, MGN_VHT3SS_MCS1, MGN_VHT3SS_MCS2, MGN_VHT3SS_MCS3, MGN_VHT3SS_MCS4,
 425                         MGN_VHT3SS_MCS5, MGN_VHT3SS_MCS6, MGN_VHT3SS_MCS7, MGN_VHT3SS_MCS8, MGN_VHT3SS_MCS9,
 426                         MGN_VHT4SS_MCS0, MGN_VHT4SS_MCS1, MGN_VHT4SS_MCS2, MGN_VHT4SS_MCS3, MGN_VHT4SS_MCS4,
 427                         MGN_VHT4SS_MCS5, MGN_VHT4SS_MCS6, MGN_VHT4SS_MCS7, MGN_VHT4SS_MCS8, MGN_VHT4SS_MCS9,
 428                 };
 429                 if (pHalData->rf_type == RF_3T3R)
 430                         MaxRate = MGN_VHT3SS_MCS9;
 431                 else if (pHalData->rf_type == RF_2T2R || pHalData->rf_type == RF_2T4R)
 432                         MaxRate = MGN_VHT2SS_MCS9;
 433                 else
 434                         MaxRate = MGN_VHT1SS_MCS9;
 435
 436                 for (path = StartPath; path <= EndPath; path++) {
 437                         for (i = 0; i < sizeof(rate); ++i) {
 438                                 if (rate[i] > MaxRate)
 439                                         break;
 440                                 PHY_SetTxPowerIndex(pAdapter, pTxPower[path], path, rate[i]);
 441                         }
 442                 }
 443         }
 444         break;
 445         default:
 446                 RTW_INFO("<===mpt_SetTxPower: Illegal channel!!\n");
 447                 break;
 448         }
 449 }
 450
 451 void hal_mpt_SetTxPower(PADAPTER pAdapter)
 452 {
 453         HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
 454         PMPT_CONTEXT            pMptCtx = &(pAdapter->mppriv.MptCtx);
 455         PDM_ODM_T               pDM_Odm = &pHalData->odmpriv;
 456
 457         if (pHalData->rf_chip < RF_TYPE_MAX) {
 458                 if (IS_HARDWARE_TYPE_8188E(pAdapter) ||
 459                     IS_HARDWARE_TYPE_8723B(pAdapter) ||
 460                     IS_HARDWARE_TYPE_8192E(pAdapter) ||
 461                     IS_HARDWARE_TYPE_8703B(pAdapter) ||
 462                     IS_HARDWARE_TYPE_8188F(pAdapter)) {
 463                         u8 path = (pHalData->AntennaTxPath == ANTENNA_A) ? (ODM_RF_PATH_A) : (ODM_RF_PATH_B);
 464
 465                         RTW_INFO("===> MPT_ProSetTxPower: Old\n");
 466
 467                         mpt_SetTxPower_Old(pAdapter, MPT_CCK, pMptCtx->TxPwrLevel);
 468                         mpt_SetTxPower_Old(pAdapter, MPT_OFDM_AND_HT, pMptCtx->TxPwrLevel);
 469
 470                 } else {
 471                         RTW_INFO("===> MPT_ProSetTxPower: Jaguar/Jaguar2\n");
 472                         mpt_SetTxPower(pAdapter, MPT_CCK, pMptCtx->TxPwrLevel);
 473                         mpt_SetTxPower(pAdapter, MPT_OFDM, pMptCtx->TxPwrLevel);
 474                         mpt_SetTxPower(pAdapter, MPT_HT, pMptCtx->TxPwrLevel);
 475                         mpt_SetTxPower(pAdapter, MPT_VHT, pMptCtx->TxPwrLevel);
 476
 477                 }
 478         } else
 479                 RTW_INFO("RFChipID < RF_TYPE_MAX, the RF chip is not supported - %d\n", pHalData->rf_chip);
 480
 481         ODM_ClearTxPowerTrackingState(pDM_Odm);
 482 }
 483
 484 void hal_mpt_SetDataRate(PADAPTER pAdapter)
 485 {
 486         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(pAdapter);
 487         PMPT_CONTEXT            pMptCtx = &(pAdapter->mppriv.MptCtx);
 488         u32 DataRate;
 489
 490         DataRate = MptToMgntRate(pMptCtx->MptRateIndex);
 491
 492         hal_mpt_SwitchRfSetting(pAdapter);
 493
 494         hal_mpt_CCKTxPowerAdjust(pAdapter, pHalData->bCCKinCH14);
 495 #ifdef CONFIG_RTL8723B
 496         if (IS_HARDWARE_TYPE_8723B(pAdapter) || IS_HARDWARE_TYPE_8188F(pAdapter)) {
 497                 if (IS_CCK_RATE(DataRate)) {
 498                         if (pMptCtx->MptRfPath == ODM_RF_PATH_A)
 499                                 PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, 0x51, 0xF, 0x6);
 500                         else
 501                                 PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, 0x71, 0xF, 0x6);
 502                 } else {
 503                         if (pMptCtx->MptRfPath == ODM_RF_PATH_A)
 504                                 PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, 0x51, 0xF, 0xE);
 505                         else
 506                                 PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, 0x71, 0xF, 0xE);
 507                 }
 508         }
 509
 510         if ((IS_HARDWARE_TYPE_8723BS(pAdapter) &&
 511              ((pHalData->PackageType == PACKAGE_TFBGA79) || (pHalData->PackageType == PACKAGE_TFBGA90)))) {
 512                 if (pMptCtx->MptRfPath == ODM_RF_PATH_A)
 513                         PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, 0x51, 0xF, 0xE);
 514                 else
 515                         PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, 0x71, 0xF, 0xE);
 516         }
 517 #endif
 518 }
 519
 520 #define RF_PATH_AB      22
 521
 522 #ifdef CONFIG_RTL8814A
 523 VOID mpt_ToggleIG_8814A(PADAPTER        pAdapter)
 524 {
 525         u1Byte Path = 0;
 526         u4Byte IGReg = rA_IGI_Jaguar, IGvalue = 0;
 527
 528         for (Path; Path <= ODM_RF_PATH_D; Path++) {
 529                 switch (Path) {
 530                 case ODM_RF_PATH_B:
 531                         IGReg = rB_IGI_Jaguar;
 532                         break;
 533                 case ODM_RF_PATH_C:
 534                         IGReg = rC_IGI_Jaguar2;
 535                         break;
 536                 case ODM_RF_PATH_D:
 537                         IGReg = rD_IGI_Jaguar2;
 538                         break;
 539                 default:
 540                         IGReg = rA_IGI_Jaguar;
 541                         break;
 542                 }
 543
 544                 IGvalue = PHY_QueryBBReg(pAdapter, IGReg, bMaskByte0);
 545                 PHY_SetBBReg(pAdapter, IGReg, bMaskByte0, IGvalue + 2);
 546                 PHY_SetBBReg(pAdapter, IGReg, bMaskByte0, IGvalue);
 547         }
 548 }
 549
 550 VOID mpt_SetRFPath_8814A(PADAPTER       pAdapter)
 551 {
 552
 553         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(pAdapter);
 554         PMPT_CONTEXT    pMptCtx = &pAdapter->mppriv.MptCtx;
 555         R_ANTENNA_SELECT_OFDM   *p_ofdm_tx;     /* OFDM Tx register */
 556         R_ANTENNA_SELECT_CCK    *p_cck_txrx;
 557         u8      ForcedDataRate = MptToMgntRate(pMptCtx->MptRateIndex);
 558         u8      HtStbcCap = pAdapter->registrypriv.stbc_cap;
 559         /*/PRT_HIGH_THROUGHPUT          pHTInfo = GET_HT_INFO(pMgntInfo);*/
 560         /*/PRT_VERY_HIGH_THROUGHPUT     pVHTInfo = GET_VHT_INFO(pMgntInfo);*/
 561
 562         u32     ulAntennaTx = pHalData->AntennaTxPath;
 563         u32     ulAntennaRx = pHalData->AntennaRxPath;
 564         u8      NssforRate = MgntQuery_NssTxRate(ForcedDataRate);
 565
 566         if ((NssforRate == RF_2TX) || ((NssforRate == RF_1TX) && IS_HT_RATE(ForcedDataRate)) || ((NssforRate == RF_1TX) && IS_VHT_RATE(ForcedDataRate))) {
 567                 RTW_INFO("===> SetAntenna 2T ForcedDataRate %d NssforRate %d AntennaTx %d\n", ForcedDataRate, NssforRate, ulAntennaTx);
 568
 569                 switch (ulAntennaTx) {
 570                 case ANTENNA_BC:
 571                         pMptCtx->MptRfPath = ODM_RF_PATH_BC;
 572                         /*pHalData->ValidTxPath = 0x06; linux no use */
 573                         PHY_SetBBReg(pAdapter, rTxAnt_23Nsts_Jaguar2, 0x0000fff0, 0x106);       /*/ 0x940[15:4]=12'b0000_0100_0011*/
 574                         break;
 575
 576                 case ANTENNA_CD:
 577                         pMptCtx->MptRfPath = ODM_RF_PATH_CD;
 578                         /*pHalData->ValidTxPath = 0x0C;*/
 579                         PHY_SetBBReg(pAdapter, rTxAnt_23Nsts_Jaguar2, 0x0000fff0, 0x40c);       /*/ 0x940[15:4]=12'b0000_0100_0011*/
 580                         break;
 581                 case ANTENNA_AB:
 582                 default:
 583                         pMptCtx->MptRfPath = ODM_RF_PATH_AB;
 584                         /*pHalData->ValidTxPath = 0x03;*/
 585                         PHY_SetBBReg(pAdapter, rTxAnt_23Nsts_Jaguar2, 0x0000fff0, 0x043);       /*/ 0x940[15:4]=12'b0000_0100_0011*/
 586                         break;
 587                 }
 588
 589         } else if (NssforRate == RF_3TX) {
 590                 RTW_INFO("===> SetAntenna 3T ForcedDataRate %d NssforRate %d AntennaTx %d\n", ForcedDataRate, NssforRate, ulAntennaTx);
 591
 592                 switch (ulAntennaTx) {
 593                 case ANTENNA_BCD:
 594                         pMptCtx->MptRfPath = ODM_RF_PATH_BCD;
 595                         /*pHalData->ValidTxPath = 0x0e;*/
 596                         PHY_SetBBReg(pAdapter, rTxAnt_23Nsts_Jaguar2, 0x0fff0000, 0x90e);       /*/ 0x940[27:16]=12'b0010_0100_0111*/
 597                         break;
 598
 599                 case ANTENNA_ABC:
 600                 default:
 601                         pMptCtx->MptRfPath = ODM_RF_PATH_ABC;
 602                         /*pHalData->ValidTxPath = 0x0d;*/
 603                         PHY_SetBBReg(pAdapter, rTxAnt_23Nsts_Jaguar2, 0x0fff0000, 0x247);       /*/ 0x940[27:16]=12'b0010_0100_0111*/
 604                         break;
 605                 }
 606
 607         } else { /*/if(NssforRate == RF_1TX)*/
 608                 RTW_INFO("===> SetAntenna 1T ForcedDataRate %d NssforRate %d AntennaTx %d\n", ForcedDataRate, NssforRate, ulAntennaTx);
 609                 switch (ulAntennaTx) {
 610                 case ANTENNA_BCD:
 611                         pMptCtx->MptRfPath = ODM_RF_PATH_BCD;
 612                         /*pHalData->ValidTxPath = 0x0e;*/
 613                         PHY_SetBBReg(pAdapter, rCCK_RX_Jaguar, 0xf0000000, 0x7);
 614                         PHY_SetBBReg(pAdapter, rTxAnt_1Nsts_Jaguar2, 0x000f00000, 0xe);
 615                         PHY_SetBBReg(pAdapter, rTxPath_Jaguar, 0xf0, 0xe);
 616                         break;
 617
 618                 case ANTENNA_BC:
 619                         pMptCtx->MptRfPath = ODM_RF_PATH_BC;
 620                         /*pHalData->ValidTxPath = 0x06;*/
 621                         PHY_SetBBReg(pAdapter, rCCK_RX_Jaguar, 0xf0000000, 0x6);
 622                         PHY_SetBBReg(pAdapter, rTxAnt_1Nsts_Jaguar2, 0x000f00000, 0x6);
 623                         PHY_SetBBReg(pAdapter, rTxPath_Jaguar, 0xf0, 0x6);
 624                         break;
 625                 case ANTENNA_B:
 626                         pMptCtx->MptRfPath = ODM_RF_PATH_B;
 627                         /*pHalData->ValidTxPath = 0x02;*/
 628                         PHY_SetBBReg(pAdapter, rCCK_RX_Jaguar, 0xf0000000, 0x4);                        /*/ 0xa07[7:4] = 4'b0100*/
 629                         PHY_SetBBReg(pAdapter, rTxAnt_1Nsts_Jaguar2, 0xfff00000, 0x002);        /*/ 0x93C[31:20]=12'b0000_0000_0010*/
 630                         PHY_SetBBReg(pAdapter, rTxPath_Jaguar, 0xf0, 0x2);                                      /* 0x80C[7:4] = 4'b0010*/
 631                         break;
 632
 633                 case ANTENNA_C:
 634                         pMptCtx->MptRfPath = ODM_RF_PATH_C;
 635                         /*pHalData->ValidTxPath = 0x04;*/
 636                         PHY_SetBBReg(pAdapter, rCCK_RX_Jaguar, 0xf0000000, 0x2);                        /*/ 0xa07[7:4] = 4'b0010*/
 637                         PHY_SetBBReg(pAdapter, rTxAnt_1Nsts_Jaguar2, 0xfff00000, 0x004);        /*/ 0x93C[31:20]=12'b0000_0000_0100*/
 638                         PHY_SetBBReg(pAdapter, rTxPath_Jaguar, 0xf0, 0x4);                                      /*/ 0x80C[7:4] = 4'b0100*/
 639                         break;
 640
 641                 case ANTENNA_D:
 642                         pMptCtx->MptRfPath = ODM_RF_PATH_D;
 643                         /*pHalData->ValidTxPath = 0x08;*/
 644                         PHY_SetBBReg(pAdapter, rCCK_RX_Jaguar, 0xf0000000, 0x1);                        /*/ 0xa07[7:4] = 4'b0001*/
 645                         PHY_SetBBReg(pAdapter, rTxAnt_1Nsts_Jaguar2, 0xfff00000, 0x008);        /*/ 0x93C[31:20]=12'b0000_0000_1000*/
 646                         PHY_SetBBReg(pAdapter, rTxPath_Jaguar, 0xf0, 0x8);                                      /*/ 0x80C[7:4] = 4'b1000*/
 647                         break;
 648
 649                 case ANTENNA_A:
 650                 default:
 651                         pMptCtx->MptRfPath = ODM_RF_PATH_A;
 652                         /*pHalData->ValidTxPath = 0x01;*/
 653                         PHY_SetBBReg(pAdapter, rCCK_RX_Jaguar, 0xf0000000, 0x8);                        /*/ 0xa07[7:4] = 4'b1000*/
 654                         PHY_SetBBReg(pAdapter, rTxAnt_1Nsts_Jaguar2, 0xfff00000, 0x001);        /*/ 0x93C[31:20]=12'b0000_0000_0001*/
 655                         PHY_SetBBReg(pAdapter, rTxPath_Jaguar, 0xf0, 0x1);                                      /*/ 0x80C[7:4] = 4'b0001*/
 656                         break;
 657                 }
 658         }
 659
 660         switch (ulAntennaRx) {
 661         case ANTENNA_A:
 662                 /*pHalData->ValidRxPath = 0x01;*/
 663                 PHY_SetBBReg(pAdapter, 0x1000, bMaskByte2, 0x2);
 664                 PHY_SetBBReg(pAdapter, rRxPath_Jaguar, bMaskByte0, 0x11);
 665                 PHY_SetBBReg(pAdapter, 0x1000, bMaskByte2, 0x3);
 666                 PHY_SetBBReg(pAdapter, rCCK_RX_Jaguar, 0x0C000000, 0x0);
 667                 PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_A_0x0[19:16] = 3, RX mode*/
 668                 PHY_SetRFReg(pAdapter, ODM_RF_PATH_B, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_B_0x0[19:16] = 1, Standby mode*/
 669                 PHY_SetRFReg(pAdapter, ODM_RF_PATH_C, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_C_0x0[19:16] = 1, Standby mode*/
 670                 PHY_SetRFReg(pAdapter, ODM_RF_PATH_D, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_D_0x0[19:16] = 1, Standby mode*/
 671                 /*/ CCA related PD_delay_th*/
 672                 PHY_SetBBReg(pAdapter, rAGC_table_Jaguar, 0x0F000000, 0x5);
 673                 PHY_SetBBReg(pAdapter, rPwed_TH_Jaguar, 0x0000000F, 0xA);
 674                 break;
 675
 676         case ANTENNA_B:
 677                 /*pHalData->ValidRxPath = 0x02;*/
 678                 PHY_SetBBReg(pAdapter, 0x1000, bMaskByte2, 0x2);
 679                 PHY_SetBBReg(pAdapter, rRxPath_Jaguar, bMaskByte0, 0x22);
 680                 PHY_SetBBReg(pAdapter, 0x1000, bMaskByte2, 0x3);
 681                 PHY_SetBBReg(pAdapter, rCCK_RX_Jaguar, 0x0C000000, 0x1);
 682                 PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_A_0x0[19:16] = 1, Standby mode*/
 683                 PHY_SetRFReg(pAdapter, ODM_RF_PATH_B, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_B_0x0[19:16] = 3, RX mode*/
 684                 PHY_SetRFReg(pAdapter, ODM_RF_PATH_C, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_C_0x0[19:16] = 1, Standby mode*/
 685                 PHY_SetRFReg(pAdapter, ODM_RF_PATH_D, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_D_0x0[19:16] = 1, Standby mode*/
 686                 /*/ CCA related PD_delay_th*/
 687                 PHY_SetBBReg(pAdapter, rAGC_table_Jaguar, 0x0F000000, 0x5);
 688                 PHY_SetBBReg(pAdapter, rPwed_TH_Jaguar, 0x0000000F, 0xA);
 689                 break;
 690
 691         case ANTENNA_C:
 692                 /*pHalData->ValidRxPath = 0x04;*/
 693                 PHY_SetBBReg(pAdapter, 0x1000, bMaskByte2, 0x2);
 694                 PHY_SetBBReg(pAdapter, rRxPath_Jaguar, bMaskByte0, 0x44);
 695                 PHY_SetBBReg(pAdapter, 0x1000, bMaskByte2, 0x3);
 696                 PHY_SetBBReg(pAdapter, rCCK_RX_Jaguar, 0x0C000000, 0x2);
 697                 PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_A_0x0[19:16] = 1, Standby mode*/
 698                 PHY_SetRFReg(pAdapter, ODM_RF_PATH_B, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_B_0x0[19:16] = 1, Standby mode*/
 699                 PHY_SetRFReg(pAdapter, ODM_RF_PATH_C, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_C_0x0[19:16] = 3, RX mode*/
 700                 PHY_SetRFReg(pAdapter, ODM_RF_PATH_D, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_D_0x0[19:16] = 1, Standby mode*/
 701                 /*/ CCA related PD_delay_th*/
 702                 PHY_SetBBReg(pAdapter, rAGC_table_Jaguar, 0x0F000000, 0x5);
 703                 PHY_SetBBReg(pAdapter, rPwed_TH_Jaguar, 0x0000000F, 0xA);
 704                 break;
 705
 706         case ANTENNA_D:
 707                 /*pHalData->ValidRxPath = 0x08;*/
 708                 PHY_SetBBReg(pAdapter, 0x1000, bMaskByte2, 0x2);
 709                 PHY_SetBBReg(pAdapter, rRxPath_Jaguar, bMaskByte0, 0x88);
 710                 PHY_SetBBReg(pAdapter, 0x1000, bMaskByte2, 0x3);
 711                 PHY_SetBBReg(pAdapter, rCCK_RX_Jaguar, 0x0C000000, 0x3);
 712                 PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_A_0x0[19:16] = 1, Standby mode*/
 713                 PHY_SetRFReg(pAdapter, ODM_RF_PATH_B, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_B_0x0[19:16] = 1, Standby mode*/
 714                 PHY_SetRFReg(pAdapter, ODM_RF_PATH_C, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_C_0x0[19:16] = 1, Standby mode*/
 715                 PHY_SetRFReg(pAdapter, ODM_RF_PATH_D, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_D_0x0[19:16] = 3, RX mode*/
 716                 /*/ CCA related PD_delay_th*/
 717                 PHY_SetBBReg(pAdapter, rAGC_table_Jaguar, 0x0F000000, 0x5);
 718                 PHY_SetBBReg(pAdapter, rPwed_TH_Jaguar, 0x0000000F, 0xA);
 719                 break;
 720
 721         case ANTENNA_BC:
 722                 /*pHalData->ValidRxPath = 0x06;*/
 723                 PHY_SetBBReg(pAdapter, 0x1000, bMaskByte2, 0x2);
 724                 PHY_SetBBReg(pAdapter, rRxPath_Jaguar, bMaskByte0, 0x66);
 725                 PHY_SetBBReg(pAdapter, 0x1000, bMaskByte2, 0x3);
 726                 PHY_SetBBReg(pAdapter, rCCK_RX_Jaguar, 0x0f000000, 0x6);
 727                 PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_A_0x0[19:16] = 1, Standby mode*/
 728                 PHY_SetRFReg(pAdapter, ODM_RF_PATH_B, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_B_0x0[19:16] = 3, RX mode*/
 729                 PHY_SetRFReg(pAdapter, ODM_RF_PATH_C, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_C_0x0[19:16] = 3, Rx mode*/
 730                 PHY_SetRFReg(pAdapter, ODM_RF_PATH_D, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_D_0x0[19:16] = 1, Standby mode*/
 731                 /*/ CCA related PD_delay_th*/
 732                 PHY_SetBBReg(pAdapter, rAGC_table_Jaguar, 0x0F000000, 0x5);
 733                 PHY_SetBBReg(pAdapter, rPwed_TH_Jaguar, 0x0000000F, 0xA);
 734                 break;
 735
 736         case ANTENNA_CD:
 737                 /*pHalData->ValidRxPath = 0x0C;*/
 738                 PHY_SetBBReg(pAdapter, 0x1000, bMaskByte2, 0x2);
 739                 PHY_SetBBReg(pAdapter, rRxPath_Jaguar, bMaskByte0, 0xcc);
 740                 PHY_SetBBReg(pAdapter, 0x1000, bMaskByte2, 0x3);
 741                 PHY_SetBBReg(pAdapter, rCCK_RX_Jaguar, 0x0f000000, 0xB);
 742                 PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_A_0x0[19:16] = 1, Standby mode*/
 743                 PHY_SetRFReg(pAdapter, ODM_RF_PATH_B, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_B_0x0[19:16] = 1, Standby mode*/
 744                 PHY_SetRFReg(pAdapter, ODM_RF_PATH_C, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_C_0x0[19:16] = 3, Rx mode*/
 745                 PHY_SetRFReg(pAdapter, ODM_RF_PATH_D, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_D_0x0[19:16] = 3, RX mode*/
 746                 /*/ CCA related PD_delay_th*/
 747                 PHY_SetBBReg(pAdapter, rAGC_table_Jaguar, 0x0F000000, 0x5);
 748                 PHY_SetBBReg(pAdapter, rPwed_TH_Jaguar, 0x0000000F, 0xA);
 749                 break;
 750
 751         case ANTENNA_BCD:
 752                 /*pHalData->ValidRxPath = 0x0e;*/
 753                 PHY_SetBBReg(pAdapter, 0x1000, bMaskByte2, 0x2);
 754                 PHY_SetBBReg(pAdapter, rRxPath_Jaguar, bMaskByte0, 0xee);
 755                 PHY_SetBBReg(pAdapter, 0x1000, bMaskByte2, 0x3);
 756                 PHY_SetBBReg(pAdapter, rCCK_RX_Jaguar, 0x0f000000, 0x6);
 757                 PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_A_0x0[19:16] = 1, Standby mode*/
 758                 PHY_SetRFReg(pAdapter, ODM_RF_PATH_B, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_B_0x0[19:16] = 3, RX mode*/
 759                 PHY_SetRFReg(pAdapter, ODM_RF_PATH_C, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_C_0x0[19:16] = 3, RX mode*/
 760                 PHY_SetRFReg(pAdapter, ODM_RF_PATH_D, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_D_0x0[19:16] = 3, Rx mode*/
 761                 /*/ CCA related PD_delay_th*/
 762                 PHY_SetBBReg(pAdapter, rAGC_table_Jaguar, 0x0F000000, 0x3);
 763                 PHY_SetBBReg(pAdapter, rPwed_TH_Jaguar, 0x0000000F, 0x8);
 764                 break;
 765
 766         case ANTENNA_ABCD:
 767                 /*pHalData->ValidRxPath = 0x0f;*/
 768                 PHY_SetBBReg(pAdapter, 0x1000, bMaskByte2, 0x2);
 769                 PHY_SetBBReg(pAdapter, rRxPath_Jaguar, bMaskByte0, 0xff);
 770                 PHY_SetBBReg(pAdapter, 0x1000, bMaskByte2, 0x3);
 771                 PHY_SetBBReg(pAdapter, rCCK_RX_Jaguar, 0x0f000000, 0x1);
 772                 PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_A_0x0[19:16] = 3, RX mode*/
 773                 PHY_SetRFReg(pAdapter, ODM_RF_PATH_B, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_B_0x0[19:16] = 3, RX mode*/
 774                 PHY_SetRFReg(pAdapter, ODM_RF_PATH_C, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_C_0x0[19:16] = 3, RX mode*/
 775                 PHY_SetRFReg(pAdapter, ODM_RF_PATH_D, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_D_0x0[19:16] = 3, RX mode*/
 776                 /*/ CCA related PD_delay_th*/
 777                 PHY_SetBBReg(pAdapter, rAGC_table_Jaguar, 0x0F000000, 0x3);
 778                 PHY_SetBBReg(pAdapter, rPwed_TH_Jaguar, 0x0000000F, 0x8);
 779                 break;
 780
 781         default:
 782                 break;
 783         }
 784
 785         PHY_Set_SecCCATH_by_RXANT_8814A(pAdapter, ulAntennaRx);
 786
 787         mpt_ToggleIG_8814A(pAdapter);
 788 }
 789 #endif /* CONFIG_RTL8814A */
 790 #if defined(CONFIG_RTL8814A) || defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8821C)
 791 VOID
 792 mpt_SetSingleTone_8814A(
 793         IN      PADAPTER        pAdapter,
 794         IN      BOOLEAN bSingleTone,
 795         IN      BOOLEAN bEnPMacTx)
 796 {
 797
 798         PMPT_CONTEXT    pMptCtx = &(pAdapter->mppriv.MptCtx);
 799         u1Byte StartPath = ODM_RF_PATH_A,  EndPath = ODM_RF_PATH_A;
 800         static u4Byte           regIG0 = 0, regIG1 = 0, regIG2 = 0, regIG3 = 0;
 801
 802         if (bSingleTone) {
 803                 regIG0 = PHY_QueryBBReg(pAdapter, rA_TxScale_Jaguar, bMaskDWord);               /*/ 0xC1C[31:21]*/
 804                 regIG1 = PHY_QueryBBReg(pAdapter, rB_TxScale_Jaguar, bMaskDWord);               /*/ 0xE1C[31:21]*/
 805                 regIG2 = PHY_QueryBBReg(pAdapter, rC_TxScale_Jaguar2, bMaskDWord);      /*/ 0x181C[31:21]*/
 806                 regIG3 = PHY_QueryBBReg(pAdapter, rD_TxScale_Jaguar2, bMaskDWord);      /*/ 0x1A1C[31:21]*/
 807
 808                 switch (pMptCtx->MptRfPath) {
 809                 case ODM_RF_PATH_A:
 810                 case ODM_RF_PATH_B:
 811                 case ODM_RF_PATH_C:
 812                 case ODM_RF_PATH_D:
 813                         StartPath = pMptCtx->MptRfPath;
 814                         EndPath = pMptCtx->MptRfPath;
 815                         break;
 816                 case ODM_RF_PATH_AB:
 817                         EndPath = ODM_RF_PATH_B;
 818                         break;
 819                 case ODM_RF_PATH_BC:
 820                         StartPath = ODM_RF_PATH_B;
 821                         EndPath = ODM_RF_PATH_C;
 822                         break;
 823                 case ODM_RF_PATH_ABC:
 824                         EndPath = ODM_RF_PATH_C;
 825                         break;
 826                 case ODM_RF_PATH_BCD:
 827                         StartPath = ODM_RF_PATH_B;
 828                         EndPath = ODM_RF_PATH_D;
 829                         break;
 830                 case ODM_RF_PATH_ABCD:
 831                         EndPath = ODM_RF_PATH_D;
 832                         break;
 833                 }
 834
 835                 if (bEnPMacTx == FALSE) {
 836                         hal_mpt_SetOFDMContinuousTx(pAdapter, _TRUE);
 837                         issue_nulldata(pAdapter, NULL, 1, 3, 500);
 838                 }
 839
 840                 PHY_SetBBReg(pAdapter, rCCAonSec_Jaguar, BIT1, 0x1); /*/ Disable CCA*/
 841
 842                 for (StartPath; StartPath <= EndPath; StartPath++) {
 843                         PHY_SetRFReg(pAdapter, StartPath, RF_AC_Jaguar, 0xF0000, 0x2); /*/ Tx mode: RF0x00[19:16]=4'b0010 */
 844                         PHY_SetRFReg(pAdapter, StartPath, RF_AC_Jaguar, 0x1F, 0x0); /*/ Lowest RF gain index: RF_0x0[4:0] = 0*/
 845
 846                         PHY_SetRFReg(pAdapter, StartPath, LNA_Low_Gain_3, BIT1, 0x1); /*/ RF LO enabled*/
 847                 }
 848
 849                 PHY_SetBBReg(pAdapter, rA_TxScale_Jaguar, 0xFFE00000, 0); /*/ 0xC1C[31:21]*/
 850                 PHY_SetBBReg(pAdapter, rB_TxScale_Jaguar, 0xFFE00000, 0); /*/ 0xE1C[31:21]*/
 851                 PHY_SetBBReg(pAdapter, rC_TxScale_Jaguar2, 0xFFE00000, 0); /*/ 0x181C[31:21]*/
 852                 PHY_SetBBReg(pAdapter, rD_TxScale_Jaguar2, 0xFFE00000, 0); /*/ 0x1A1C[31:21]*/
 853         } else {
 854                 switch (pMptCtx->MptRfPath) {
 855                 case ODM_RF_PATH_A:
 856                 case ODM_RF_PATH_B:
 857                 case ODM_RF_PATH_C:
 858                 case ODM_RF_PATH_D:
 859                         StartPath = pMptCtx->MptRfPath;
 860                         EndPath = pMptCtx->MptRfPath;
 861                         break;
 862                 case ODM_RF_PATH_AB:
 863                         EndPath = ODM_RF_PATH_B;
 864                         break;
 865                 case ODM_RF_PATH_BC:
 866                         StartPath = ODM_RF_PATH_B;
 867                         EndPath = ODM_RF_PATH_C;
 868                         break;
 869                 case ODM_RF_PATH_ABC:
 870                         EndPath = ODM_RF_PATH_C;
 871                         break;
 872                 case ODM_RF_PATH_BCD:
 873                         StartPath = ODM_RF_PATH_B;
 874                         EndPath = ODM_RF_PATH_D;
 875                         break;
 876                 case ODM_RF_PATH_ABCD:
 877                         EndPath = ODM_RF_PATH_D;
 878                         break;
 879                 }
 880                 for (StartPath; StartPath <= EndPath; StartPath++)
 881                         PHY_SetRFReg(pAdapter, StartPath, LNA_Low_Gain_3, BIT1, 0x0); /* RF LO disabled */
 882
 883                 PHY_SetBBReg(pAdapter, rCCAonSec_Jaguar, BIT1, 0x0); /* Enable CCA*/
 884
 885                 if (bEnPMacTx == FALSE)
 886                         hal_mpt_SetOFDMContinuousTx(pAdapter, _FALSE);
 887
 888                 PHY_SetBBReg(pAdapter, rA_TxScale_Jaguar, bMaskDWord, regIG0); /* 0xC1C[31:21]*/
 889                 PHY_SetBBReg(pAdapter, rB_TxScale_Jaguar, bMaskDWord, regIG1); /* 0xE1C[31:21]*/
 890                 PHY_SetBBReg(pAdapter, rC_TxScale_Jaguar2, bMaskDWord, regIG2); /* 0x181C[31:21]*/
 891                 PHY_SetBBReg(pAdapter, rD_TxScale_Jaguar2, bMaskDWord, regIG3); /* 0x1A1C[31:21]*/
 892         }
 893 }
 894
 895 #endif
 896
 897 #if     defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A)
 898 void mpt_SetRFPath_8812A(PADAPTER pAdapter)
 899 {
 900         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(pAdapter);
 901         PMPT_CONTEXT    pMptCtx = &pAdapter->mppriv.MptCtx;
 902         struct mp_priv *pmp = &pAdapter->mppriv;
 903         u8              channel = pmp->channel;
 904         u8              bandwidth = pmp->bandwidth;
 905         u8              eLNA_2g = pHalData->ExternalLNA_2G;
 906         u32             ulAntennaTx, ulAntennaRx;
 907
 908         ulAntennaTx = pHalData->AntennaTxPath;
 909         ulAntennaRx = pHalData->AntennaRxPath;
 910
 911         switch (ulAntennaTx) {
 912         case ANTENNA_A:
 913                 pMptCtx->MptRfPath = ODM_RF_PATH_A;
 914                 PHY_SetBBReg(pAdapter, rTxPath_Jaguar, bMaskLWord, 0x1111);
 915                 if (pHalData->RFEType == 3 && IS_HARDWARE_TYPE_8812(pAdapter))
 916                         PHY_SetBBReg(pAdapter, r_ANTSEL_SW_Jaguar, bMask_AntselPathFollow_Jaguar, 0x0);
 917                 break;
 918         case ANTENNA_B:
 919                 pMptCtx->MptRfPath = ODM_RF_PATH_B;
 920                 PHY_SetBBReg(pAdapter, rTxPath_Jaguar, bMaskLWord, 0x2222);
 921                 if (pHalData->RFEType == 3 && IS_HARDWARE_TYPE_8812(pAdapter))
 922                         PHY_SetBBReg(pAdapter,  r_ANTSEL_SW_Jaguar, bMask_AntselPathFollow_Jaguar, 0x1);
 923                 break;
 924         case ANTENNA_AB:
 925                 pMptCtx->MptRfPath = ODM_RF_PATH_AB;
 926                 PHY_SetBBReg(pAdapter, rTxPath_Jaguar, bMaskLWord, 0x3333);
 927                 if (pHalData->RFEType == 3 && IS_HARDWARE_TYPE_8812(pAdapter))
 928                         PHY_SetBBReg(pAdapter, r_ANTSEL_SW_Jaguar, bMask_AntselPathFollow_Jaguar, 0x0);
 929                 break;
 930         default:
 931                 pMptCtx->MptRfPath = ODM_RF_PATH_AB;
 932                 RTW_INFO("Unknown Tx antenna.\n");
 933                 break;
 934         }
 935
 936         switch (ulAntennaRx) {
 937                 u32 reg0xC50 = 0;
 938         case ANTENNA_A:
 939                 PHY_SetBBReg(pAdapter, rRxPath_Jaguar, bMaskByte0, 0x11);
 940                 PHY_SetRFReg(pAdapter, ODM_RF_PATH_B, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_B_0x0[19:16] = 1, Standby mode*/
 941                 PHY_SetBBReg(pAdapter, rCCK_RX_Jaguar, bCCK_RX_Jaguar, 0x0);
 942                 PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, RF_AC_Jaguar, BIT19 | BIT18 | BIT17 | BIT16, 0x3);
 943
 944                 /*/ <20121101, Kordan> To prevent gain table from not switched, asked by Ynlin.*/
 945                 reg0xC50 = PHY_QueryBBReg(pAdapter, rA_IGI_Jaguar, bMaskByte0);
 946                 PHY_SetBBReg(pAdapter, rA_IGI_Jaguar, bMaskByte0, reg0xC50 + 2);
 947                 PHY_SetBBReg(pAdapter, rA_IGI_Jaguar, bMaskByte0, reg0xC50);
 948
 949                 /* set PWED_TH for BB Yn user guide R29 */
 950                 if (IS_HARDWARE_TYPE_8812(pAdapter)) {
 951                         if (channel <= 14) { /* 2.4G */
 952                                 if (bandwidth == CHANNEL_WIDTH_20
 953                                     && eLNA_2g == 0) {
 954                                         /* 0x830[3:1]=3'b010 */
 955                                         PHY_SetBBReg(pAdapter, rPwed_TH_Jaguar, BIT1 | BIT2 | BIT3, 0x02);
 956                                 } else
 957                                         /* 0x830[3:1]=3'b100 */
 958                                         PHY_SetBBReg(pAdapter, rPwed_TH_Jaguar, BIT1 | BIT2 | BIT3, 0x04);
 959                         } else
 960                                 /* 0x830[3:1]=3'b100 for 5G */
 961                                 PHY_SetBBReg(pAdapter, rPwed_TH_Jaguar, BIT1 | BIT2 | BIT3, 0x04);
 962                 }
 963                 break;
 964         case ANTENNA_B:
 965                 PHY_SetBBReg(pAdapter, rRxPath_Jaguar, bMaskByte0, 0x22);
 966                 PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, RF_AC_Jaguar, 0xF0000, 0x1);/*/ RF_A_0x0[19:16] = 1, Standby mode */
 967                 PHY_SetBBReg(pAdapter, rCCK_RX_Jaguar, bCCK_RX_Jaguar, 0x1);
 968                 PHY_SetRFReg(pAdapter, ODM_RF_PATH_B, RF_AC_Jaguar, BIT19 | BIT18 | BIT17 | BIT16, 0x3);
 969
 970                 /*/ <20121101, Kordan> To prevent gain table from not switched, asked by Ynlin.*/
 971                 reg0xC50 = PHY_QueryBBReg(pAdapter, rB_IGI_Jaguar, bMaskByte0);
 972                 PHY_SetBBReg(pAdapter, rB_IGI_Jaguar, bMaskByte0, reg0xC50 + 2);
 973                 PHY_SetBBReg(pAdapter, rB_IGI_Jaguar, bMaskByte0, reg0xC50);
 974
 975                 /* set PWED_TH for BB Yn user guide R29 */
 976                 if (IS_HARDWARE_TYPE_8812(pAdapter)) {
 977                         if (channel <= 14) {
 978                                 if (bandwidth == CHANNEL_WIDTH_20
 979                                     && eLNA_2g == 0) {
 980                                         /* 0x830[3:1]=3'b010 */
 981                                         PHY_SetBBReg(pAdapter, rPwed_TH_Jaguar, BIT1 | BIT2 | BIT3, 0x02);
 982                                 } else
 983                                         /* 0x830[3:1]=3'b100 */
 984                                         PHY_SetBBReg(pAdapter, rPwed_TH_Jaguar, BIT1 | BIT2 | BIT3, 0x04);
 985                         } else
 986                                 /* 0x830[3:1]=3'b100 for 5G */
 987                                 PHY_SetBBReg(pAdapter, rPwed_TH_Jaguar, BIT1 | BIT2 | BIT3, 0x04);
 988                 }
 989                 break;
 990         case ANTENNA_AB:
 991                 PHY_SetBBReg(pAdapter, rRxPath_Jaguar, bMaskByte0, 0x33);
 992                 PHY_SetRFReg(pAdapter, ODM_RF_PATH_B, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_B_0x0[19:16] = 3, Rx mode*/
 993                 PHY_SetBBReg(pAdapter, rCCK_RX_Jaguar, bCCK_RX_Jaguar, 0x0);
 994                 /* set PWED_TH for BB Yn user guide R29 */
 995                 PHY_SetBBReg(pAdapter, rPwed_TH_Jaguar, BIT1 | BIT2 | BIT3, 0x04);
 996                 break;
 997         default:
 998                 RTW_INFO("Unknown Rx antenna.\n");
 999                 break;
1000         }
1001 }
1002 #endif
1003
1004 #ifdef CONFIG_RTL8723B
1005 void mpt_SetRFPath_8723B(PADAPTER pAdapter)
1006 {
1007         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(pAdapter);
1008         u32             ulAntennaTx, ulAntennaRx;
1009         PMPT_CONTEXT    pMptCtx = &(pAdapter->mppriv.MptCtx);
1010         PDM_ODM_T       pDM_Odm = &pHalData->odmpriv;
1011         PODM_RF_CAL_T   pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo);
1012
1013         ulAntennaTx = pHalData->AntennaTxPath;
1014         ulAntennaRx = pHalData->AntennaRxPath;
1015
1016         if (pHalData->rf_chip >= RF_TYPE_MAX) {
1017                 RTW_INFO("This RF chip ID is not supported\n");
1018                 return;
1019         }
1020
1021         switch (pAdapter->mppriv.antenna_tx) {
1022                 u8 p = 0, i = 0;
1023         case ANTENNA_A: { /*/ Actually path S1  (Wi-Fi)*/
1024                 pMptCtx->MptRfPath = ODM_RF_PATH_A;
1025                 PHY_SetBBReg(pAdapter, rS0S1_PathSwitch, BIT9 | BIT8 | BIT7, 0x0);
1026                 PHY_SetBBReg(pAdapter, 0xB2C, BIT31, 0x0); /* AGC Table Sel*/
1027
1028                 /*/<20130522, Kordan> 0x51 and 0x71 should be set immediately after path switched, or they might be overwritten.*/
1029                 if ((pHalData->PackageType == PACKAGE_TFBGA79) || (pHalData->PackageType == PACKAGE_TFBGA90))
1030                         PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, 0x51, bRFRegOffsetMask, 0x6B10E);
1031                 else
1032                         PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, 0x51, bRFRegOffsetMask, 0x6B04E);
1033
1034                 for (i = 0; i < 3; ++i) {
1035                         u4Byte offset = pRFCalibrateInfo->TxIQC_8723B[ODM_RF_PATH_A][i][0];
1036                         u4Byte data = pRFCalibrateInfo->TxIQC_8723B[ODM_RF_PATH_A][i][1];
1037
1038                         if (offset != 0) {
1039                                 PHY_SetBBReg(pAdapter, offset, bMaskDWord, data);
1040                                 RTW_INFO("Switch to S1 TxIQC(offset, data) = (0x%X, 0x%X)\n", offset, data);
1041                         }
1042                 }
1043                 for (i = 0; i < 2; ++i) {
1044                         u4Byte offset = pRFCalibrateInfo->RxIQC_8723B[ODM_RF_PATH_A][i][0];
1045                         u4Byte data = pRFCalibrateInfo->RxIQC_8723B[ODM_RF_PATH_A][i][1];
1046
1047                         if (offset != 0) {
1048                                 PHY_SetBBReg(pAdapter, offset, bMaskDWord, data);
1049                                 RTW_INFO("Switch to S1 RxIQC (offset, data) = (0x%X, 0x%X)\n", offset, data);
1050                         }
1051                 }
1052         }
1053         break;
1054         case ANTENNA_B: { /*/ Actually path S0 (BT)*/
1055                 u4Byte offset;
1056                 u4Byte data;
1057
1058                 pMptCtx->MptRfPath = ODM_RF_PATH_B;
1059                 PHY_SetBBReg(pAdapter, rS0S1_PathSwitch, BIT9 | BIT8 | BIT7, 0x5);
1060                 PHY_SetBBReg(pAdapter, 0xB2C, BIT31, 0x1); /*/ AGC Table Sel.*/
1061                 /* <20130522, Kordan> 0x51 and 0x71 should be set immediately after path switched, or they might be overwritten.*/
1062                 if ((pHalData->PackageType == PACKAGE_TFBGA79) || (pHalData->PackageType == PACKAGE_TFBGA90))
1063                         PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, 0x51, bRFRegOffsetMask, 0x6B10E);
1064                 else
1065                         PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, 0x51, bRFRegOffsetMask, 0x6B04E);
1066
1067                 for (i = 0; i < 3; ++i) {
1068                         /*/ <20130603, Kordan> Because BB suppors only 1T1R, we restore IQC  to S1 instead of S0.*/
1069                         offset = pRFCalibrateInfo->TxIQC_8723B[ODM_RF_PATH_A][i][0];
1070                         data = pRFCalibrateInfo->TxIQC_8723B[ODM_RF_PATH_B][i][1];
1071                         if (pRFCalibrateInfo->TxIQC_8723B[ODM_RF_PATH_B][i][0] != 0) {
1072                                 PHY_SetBBReg(pAdapter, offset, bMaskDWord, data);
1073                                 RTW_INFO("Switch to S0 TxIQC (offset, data) = (0x%X, 0x%X)\n", offset, data);
1074                         }
1075                 }
1076                 /*/ <20130603, Kordan> Because BB suppors only 1T1R, we restore IQC to S1 instead of S0.*/
1077                 for (i = 0; i < 2; ++i) {
1078                         offset = pRFCalibrateInfo->RxIQC_8723B[ODM_RF_PATH_A][i][0];
1079                         data = pRFCalibrateInfo->RxIQC_8723B[ODM_RF_PATH_B][i][1];
1080                         if (pRFCalibrateInfo->RxIQC_8723B[ODM_RF_PATH_B][i][0] != 0) {
1081                                 PHY_SetBBReg(pAdapter, offset, bMaskDWord, data);
1082                                 RTW_INFO("Switch to S0 RxIQC (offset, data) = (0x%X, 0x%X)\n", offset, data);
1083                         }
1084                 }
1085         }
1086         break;
1087         default:
1088                 pMptCtx->MptRfPath = RF_PATH_AB;
1089                 break;
1090         }
1091 }
1092 #endif
1093
1094 #ifdef CONFIG_RTL8703B
1095 void mpt_SetRFPath_8703B(PADAPTER pAdapter)
1096 {
1097         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(pAdapter);
1098         u4Byte                                  ulAntennaTx, ulAntennaRx;
1099         PMPT_CONTEXT            pMptCtx = &(pAdapter->mppriv.MptCtx);
1100         PDM_ODM_T               pDM_Odm = &pHalData->odmpriv;
1101         PODM_RF_CAL_T                   pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo);
1102
1103         ulAntennaTx = pHalData->AntennaTxPath;
1104         ulAntennaRx = pHalData->AntennaRxPath;
1105
1106         if (pHalData->rf_chip >= RF_TYPE_MAX) {
1107                 RTW_INFO("This RF chip ID is not supported\n");
1108                 return;
1109         }
1110
1111         switch (pAdapter->mppriv.antenna_tx) {
1112                 u1Byte p = 0, i = 0;
1113
1114         case ANTENNA_A: { /* Actually path S1  (Wi-Fi) */
1115                 pMptCtx->MptRfPath = ODM_RF_PATH_A;
1116                 PHY_SetBBReg(pAdapter, rS0S1_PathSwitch, BIT9 | BIT8 | BIT7, 0x0);
1117                 PHY_SetBBReg(pAdapter, 0xB2C, BIT31, 0x0); /* AGC Table Sel*/
1118
1119                 for (i = 0; i < 3; ++i) {
1120                         u4Byte offset = pRFCalibrateInfo->TxIQC_8703B[i][0];
1121                         u4Byte data = pRFCalibrateInfo->TxIQC_8703B[i][1];
1122
1123                         if (offset != 0) {
1124                                 PHY_SetBBReg(pAdapter, offset, bMaskDWord, data);
1125                                 RTW_INFO("Switch to S1 TxIQC(offset, data) = (0x%X, 0x%X)\n", offset, data);
1126                         }
1127
1128                 }
1129                 for (i = 0; i < 2; ++i) {
1130                         u4Byte offset = pRFCalibrateInfo->RxIQC_8703B[i][0];
1131                         u4Byte data = pRFCalibrateInfo->RxIQC_8703B[i][1];
1132
1133                         if (offset != 0) {
1134                                 PHY_SetBBReg(pAdapter, offset, bMaskDWord, data);
1135                                 RTW_INFO("Switch to S1 RxIQC (offset, data) = (0x%X, 0x%X)\n", offset, data);
1136                         }
1137                 }
1138         }
1139         break;
1140         case ANTENNA_B: { /* Actually path S0 (BT)*/
1141                 pMptCtx->MptRfPath = ODM_RF_PATH_B;
1142                 PHY_SetBBReg(pAdapter, rS0S1_PathSwitch, BIT9 | BIT8 | BIT7, 0x5);
1143                 PHY_SetBBReg(pAdapter, 0xB2C, BIT31, 0x1); /* AGC Table Sel */
1144
1145                 for (i = 0; i < 3; ++i) {
1146                         u4Byte offset = pRFCalibrateInfo->TxIQC_8703B[i][0];
1147                         u4Byte data = pRFCalibrateInfo->TxIQC_8703B[i][1];
1148
1149                         if (pRFCalibrateInfo->TxIQC_8703B[i][0] != 0) {
1150                                 PHY_SetBBReg(pAdapter, offset, bMaskDWord, data);
1151                                 RTW_INFO("Switch to S0 TxIQC (offset, data) = (0x%X, 0x%X)\n", offset, data);
1152                         }
1153                 }
1154                 for (i = 0; i < 2; ++i) {
1155                         u4Byte offset = pRFCalibrateInfo->RxIQC_8703B[i][0];
1156                         u4Byte data = pRFCalibrateInfo->RxIQC_8703B[i][1];
1157
1158                         if (pRFCalibrateInfo->RxIQC_8703B[i][0] != 0) {
1159                                 PHY_SetBBReg(pAdapter, offset, bMaskDWord, data);
1160                                 RTW_INFO("Switch to S0 RxIQC (offset, data) = (0x%X, 0x%X)\n", offset, data);
1161                         }
1162                 }
1163         }
1164         break;
1165         default:
1166                 pMptCtx->MptRfPath = RF_PATH_AB;
1167                 break;
1168         }
1169
1170 }
1171 #endif
1172
1173 #ifdef CONFIG_RTL8723D
1174 void mpt_SetRFPath_8723D(PADAPTER pAdapter)
1175 {
1176         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(pAdapter);
1177         u1Byte  p = 0, i = 0;
1178         u4Byte  ulAntennaTx, ulAntennaRx, offset = 0, data = 0, val32 = 0;
1179         PMPT_CONTEXT    pMptCtx = &(pAdapter->mppriv.MptCtx);
1180         PDM_ODM_T       pDM_Odm = &pHalData->odmpriv;
1181         PODM_RF_CAL_T   pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo);
1182
1183         ulAntennaTx = pHalData->AntennaTxPath;
1184         ulAntennaRx = pHalData->AntennaRxPath;
1185
1186         if (pHalData->rf_chip >= RF_TYPE_MAX) {
1187                 RTW_INFO("This RF chip ID is not supported\n");
1188                 return;
1189         }
1190
1191         switch (pAdapter->mppriv.antenna_tx) {
1192         /* Actually path S1  (Wi-Fi) */
1193         case ANTENNA_A: {
1194                 pMptCtx->MptRfPath = ODM_RF_PATH_A;
1195                 PHY_SetBBReg(pAdapter, rS0S1_PathSwitch, BIT9|BIT8|BIT7|BIT6, 0);
1196         }
1197         break;
1198         /* Actually path S0 (BT) */
1199         case ANTENNA_B: {
1200                 pMptCtx->MptRfPath = ODM_RF_PATH_B;
1201                 PHY_SetBBReg(pAdapter, rS0S1_PathSwitch, BIT9|BIT8|BIT7|BIT6, 0xA);
1202
1203         }
1204         break;
1205         default:
1206                 pMptCtx->MptRfPath = RF_PATH_AB;
1207                 break;
1208         }
1209 }
1210 #endif
1211
1212 VOID mpt_SetRFPath_819X(PADAPTER        pAdapter)
1213 {
1214         HAL_DATA_TYPE                   *pHalData       = GET_HAL_DATA(pAdapter);
1215         PMPT_CONTEXT            pMptCtx = &(pAdapter->mppriv.MptCtx);
1216         u4Byte                  ulAntennaTx, ulAntennaRx;
1217         R_ANTENNA_SELECT_OFDM   *p_ofdm_tx;     /* OFDM Tx register */
1218         R_ANTENNA_SELECT_CCK    *p_cck_txrx;
1219         u1Byte          r_rx_antenna_ofdm = 0, r_ant_select_cck_val = 0;
1220         u1Byte          chgTx = 0, chgRx = 0;
1221         u4Byte          r_ant_sel_cck_val = 0, r_ant_select_ofdm_val = 0, r_ofdm_tx_en_val = 0;
1222
1223         ulAntennaTx = pHalData->AntennaTxPath;
1224         ulAntennaRx = pHalData->AntennaRxPath;
1225
1226         p_ofdm_tx = (R_ANTENNA_SELECT_OFDM *)&r_ant_select_ofdm_val;
1227         p_cck_txrx = (R_ANTENNA_SELECT_CCK *)&r_ant_select_cck_val;
1228
1229         p_ofdm_tx->r_ant_ht1                    = 0x1;
1230         p_ofdm_tx->r_ant_ht2                    = 0x2;/*Second TX RF path is A*/
1231         p_ofdm_tx->r_ant_non_ht                 = 0x3;/*/ 0x1+0x2=0x3 */
1232
1233         switch (ulAntennaTx) {
1234         case ANTENNA_A:
1235                 p_ofdm_tx->r_tx_antenna         = 0x1;
1236                 r_ofdm_tx_en_val                = 0x1;
1237                 p_ofdm_tx->r_ant_l              = 0x1;
1238                 p_ofdm_tx->r_ant_ht_s1          = 0x1;
1239                 p_ofdm_tx->r_ant_non_ht_s1      = 0x1;
1240                 p_cck_txrx->r_ccktx_enable      = 0x8;
1241                 chgTx = 1;
1242                 /*/ From SD3 Willis suggestion !!! Set RF A=TX and B as standby*/
1243                 /*/if (IS_HARDWARE_TYPE_8192S(pAdapter))*/
1244                 {
1245                         PHY_SetBBReg(pAdapter, rFPGA0_XA_HSSIParameter2, 0xe, 2);
1246                         PHY_SetBBReg(pAdapter, rFPGA0_XB_HSSIParameter2, 0xe, 1);
1247                         r_ofdm_tx_en_val                        = 0x3;
1248                         /*/ Power save*/
1249                         /*/cosa r_ant_select_ofdm_val = 0x11111111;*/
1250                         /*/ We need to close RFB by SW control*/
1251                         if (pHalData->rf_type == RF_2T2R) {
1252                                 PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFInterfaceSW, BIT10, 0);
1253                                 PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFInterfaceSW, BIT26, 1);
1254                                 PHY_SetBBReg(pAdapter, rFPGA0_XB_RFInterfaceOE, BIT10, 0);
1255                                 PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFParameter, BIT1, 1);
1256                                 PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFParameter, BIT17, 0);
1257                         }
1258                 }
1259                 pMptCtx->MptRfPath = ODM_RF_PATH_A;
1260                 break;
1261         case ANTENNA_B:
1262                 p_ofdm_tx->r_tx_antenna         = 0x2;
1263                 r_ofdm_tx_en_val                = 0x2;
1264                 p_ofdm_tx->r_ant_l              = 0x2;
1265                 p_ofdm_tx->r_ant_ht_s1          = 0x2;
1266                 p_ofdm_tx->r_ant_non_ht_s1      = 0x2;
1267                 p_cck_txrx->r_ccktx_enable      = 0x4;
1268                 chgTx = 1;
1269                 /*/ From SD3 Willis suggestion !!! Set RF A as standby*/
1270                 /*/if (IS_HARDWARE_TYPE_8192S(pAdapter))*/
1271                 {
1272                         PHY_SetBBReg(pAdapter, rFPGA0_XA_HSSIParameter2, 0xe, 1);
1273                         PHY_SetBBReg(pAdapter, rFPGA0_XB_HSSIParameter2, 0xe, 2);
1274
1275                         /*/ 2008/10/31 MH From SD3 Willi's suggestion. We must read RF 1T table.*/
1276                         /*/ 2009/01/08 MH From Sd3 Willis. We need to close RFA by SW control*/
1277                         if (pHalData->rf_type == RF_2T2R || pHalData->rf_type == RF_1T2R) {
1278                                 PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFInterfaceSW, BIT10, 1);
1279                                 PHY_SetBBReg(pAdapter, rFPGA0_XA_RFInterfaceOE, BIT10, 0);
1280                                 PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFInterfaceSW, BIT26, 0);
1281                                 /*/PHY_SetBBReg(pAdapter, rFPGA0_XB_RFInterfaceOE, BIT10, 0);*/
1282                                 PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFParameter, BIT1, 0);
1283                                 PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFParameter, BIT17, 1);
1284                         }
1285                 }
1286                 pMptCtx->MptRfPath = ODM_RF_PATH_B;
1287                 break;
1288         case ANTENNA_AB:/*/ For 8192S*/
1289                 p_ofdm_tx->r_tx_antenna         = 0x3;
1290                 r_ofdm_tx_en_val                = 0x3;
1291                 p_ofdm_tx->r_ant_l              = 0x3;
1292                 p_ofdm_tx->r_ant_ht_s1          = 0x3;
1293                 p_ofdm_tx->r_ant_non_ht_s1      = 0x3;
1294                 p_cck_txrx->r_ccktx_enable      = 0xC;
1295                 chgTx = 1;
1296                 /*/ From SD3Willis suggestion !!! Set RF B as standby*/
1297                 /*/if (IS_HARDWARE_TYPE_8192S(pAdapter))*/
1298                 {
1299                         PHY_SetBBReg(pAdapter, rFPGA0_XA_HSSIParameter2, 0xe, 2);
1300                         PHY_SetBBReg(pAdapter, rFPGA0_XB_HSSIParameter2, 0xe, 2);
1301                         /* Disable Power save*/
1302                         /*cosa r_ant_select_ofdm_val = 0x3321333;*/
1303                         /* 2009/01/08 MH From Sd3 Willis. We need to enable RFA/B by SW control*/
1304                         if (pHalData->rf_type == RF_2T2R) {
1305                                 PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFInterfaceSW, BIT10, 0);
1306
1307                                 PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFInterfaceSW, BIT26, 0);
1308                                 /*/PHY_SetBBReg(pAdapter, rFPGA0_XB_RFInterfaceOE, BIT10, 0);*/
1309                                 PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFParameter, BIT1, 1);
1310                                 PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFParameter, BIT17, 1);
1311                         }
1312                 }
1313                 pMptCtx->MptRfPath = ODM_RF_PATH_AB;
1314                 break;
1315         default:
1316                 break;
1317         }
1318 #if 0
1319         /*  r_rx_antenna_ofdm, bit0=A, bit1=B, bit2=C, bit3=D */
1320         /*  r_cckrx_enable : CCK default, 0=A, 1=B, 2=C, 3=D */
1321         /* r_cckrx_enable_2 : CCK option, 0=A, 1=B, 2=C, 3=D     */
1322 #endif
1323         switch (ulAntennaRx) {
1324         case ANTENNA_A:
1325                 r_rx_antenna_ofdm               = 0x1;  /* A*/
1326                 p_cck_txrx->r_cckrx_enable      = 0x0;  /* default: A*/
1327                 p_cck_txrx->r_cckrx_enable_2    = 0x0;  /* option: A*/
1328                 chgRx = 1;
1329                 break;
1330         case ANTENNA_B:
1331                 r_rx_antenna_ofdm                       = 0x2;  /*/ B*/
1332                 p_cck_txrx->r_cckrx_enable      = 0x1;  /*/ default: B*/
1333                 p_cck_txrx->r_cckrx_enable_2    = 0x1;  /*/ option: B*/
1334                 chgRx = 1;
1335                 break;
1336         case ANTENNA_AB:/*/ For 8192S and 8192E/U...*/
1337                 r_rx_antenna_ofdm               = 0x3;/*/ AB*/
1338                 p_cck_txrx->r_cckrx_enable      = 0x0;/*/ default:A*/
1339                 p_cck_txrx->r_cckrx_enable_2    = 0x1;/*/ option:B*/
1340                 chgRx = 1;
1341                 break;
1342         default:
1343                 break;
1344         }
1345
1346
1347         if (chgTx && chgRx) {
1348                 switch (pHalData->rf_chip) {
1349                 case RF_8225:
1350                 case RF_8256:
1351                 case RF_6052:
1352                         /*/r_ant_sel_cck_val = r_ant_select_cck_val;*/
1353                         PHY_SetBBReg(pAdapter, rFPGA1_TxInfo, 0x7fffffff, r_ant_select_ofdm_val);               /*/OFDM Tx*/
1354                         PHY_SetBBReg(pAdapter, rFPGA0_TxInfo, 0x0000000f, r_ofdm_tx_en_val);            /*/OFDM Tx*/
1355                         PHY_SetBBReg(pAdapter, rOFDM0_TRxPathEnable, 0x0000000f, r_rx_antenna_ofdm);    /*/OFDM Rx*/
1356                         PHY_SetBBReg(pAdapter, rOFDM1_TRxPathEnable, 0x0000000f, r_rx_antenna_ofdm);    /*/OFDM Rx*/
1357                         if (IS_HARDWARE_TYPE_8192E(pAdapter)) {
1358                                 PHY_SetBBReg(pAdapter, rOFDM0_TRxPathEnable, 0x000000F0, r_rx_antenna_ofdm);    /*/OFDM Rx*/
1359                                 PHY_SetBBReg(pAdapter, rOFDM1_TRxPathEnable, 0x000000F0, r_rx_antenna_ofdm);    /*/OFDM Rx*/
1360                         }
1361                         PHY_SetBBReg(pAdapter, rCCK0_AFESetting, bMaskByte3, r_ant_select_cck_val);/*/r_ant_sel_cck_val); /CCK TxRx*/
1362                         break;
1363
1364                 default:
1365                         RTW_INFO("Unsupported RFChipID for switching antenna.\n");
1366                         break;
1367                 }
1368         }
1369 }       /* MPT_ProSetRFPath */
1370
1371
1372 void hal_mpt_SetAntenna(PADAPTER        pAdapter)
1373
1374 {
1375         RTW_INFO("Do %s\n", __func__);
1376 #ifdef CONFIG_RTL8814A
1377         if (IS_HARDWARE_TYPE_8814A(pAdapter)) {
1378                 mpt_SetRFPath_8814A(pAdapter);
1379                 return;
1380         }
1381 #endif
1382 #ifdef CONFIG_RTL8822B
1383         if (IS_HARDWARE_TYPE_8822B(pAdapter)) {
1384                 rtl8822b_mp_config_rfpath(pAdapter);
1385                 return;
1386         }
1387 #endif
1388 #ifdef CONFIG_RTL8821C
1389         if (IS_HARDWARE_TYPE_8821C(pAdapter)) {
1390                 rtl8821c_mp_config_rfpath(pAdapter);
1391                 return;
1392         }
1393 #endif
1394 #if     defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A)
1395         if (IS_HARDWARE_TYPE_JAGUAR(pAdapter)) {
1396                 mpt_SetRFPath_8812A(pAdapter);
1397                 return;
1398         }
1399 #endif
1400 #ifdef CONFIG_RTL8723B
1401         if (IS_HARDWARE_TYPE_8723B(pAdapter)) {
1402                 mpt_SetRFPath_8723B(pAdapter);
1403                 return;
1404         }
1405 #endif
1406
1407 #ifdef CONFIG_RTL8703B
1408         if (IS_HARDWARE_TYPE_8703B(pAdapter)) {
1409                 mpt_SetRFPath_8703B(pAdapter);
1410                 return;
1411         }
1412 #endif
1413
1414 #ifdef CONFIG_RTL8723D
1415         if (IS_HARDWARE_TYPE_8723D(pAdapter)) {
1416                 mpt_SetRFPath_8723D(pAdapter);
1417                 return;
1418         }
1419 #endif
1420         /*      else if (IS_HARDWARE_TYPE_8821B(pAdapter))
1421                         mpt_SetRFPath_8821B(pAdapter);
1422                 Prepare for 8822B
1423                 else if (IS_HARDWARE_TYPE_8822B(Context))
1424                         mpt_SetRFPath_8822B(Context);
1425         */
1426         mpt_SetRFPath_819X(pAdapter);
1427         RTW_INFO("mpt_SetRFPath_819X Do %s\n", __func__);
1428 }
1429
1430 s32 hal_mpt_SetThermalMeter(PADAPTER pAdapter, u8 target_ther)
1431 {
1432         HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
1433
1434         if (!netif_running(pAdapter->pnetdev)) {
1435                 return _FAIL;
1436         }
1437
1438
1439         if (check_fwstate(&pAdapter->mlmepriv, WIFI_MP_STATE) == _FALSE) {
1440                 return _FAIL;
1441         }
1442
1443
1444         target_ther &= 0xff;
1445         if (target_ther < 0x07)
1446                 target_ther = 0x07;
1447         else if (target_ther > 0x1d)
1448                 target_ther = 0x1d;
1449
1450         pHalData->EEPROMThermalMeter = target_ther;
1451
1452         return _SUCCESS;
1453 }
1454
1455
1456 void hal_mpt_TriggerRFThermalMeter(PADAPTER pAdapter)
1457 {
1458         PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, 0x42, BIT17 | BIT16, 0x03);
1459
1460 }
1461
1462
1463 u8 hal_mpt_ReadRFThermalMeter(PADAPTER pAdapter)
1464
1465 {
1466         u32 ThermalValue = 0;
1467
1468         ThermalValue = (u1Byte)PHY_QueryRFReg(pAdapter, ODM_RF_PATH_A, 0x42, 0xfc00);   /*0x42: RF Reg[15:10]*/
1469         return (u8)ThermalValue;
1470
1471 }
1472
1473
1474 void hal_mpt_GetThermalMeter(PADAPTER pAdapter, u8 *value)
1475 {
1476 #if 0
1477         fw_cmd(pAdapter, IOCMD_GET_THERMAL_METER);
1478         rtw_msleep_os(1000);
1479         fw_cmd_data(pAdapter, value, 1);
1480         *value &= 0xFF;
1481 #else
1482         hal_mpt_TriggerRFThermalMeter(pAdapter);
1483         rtw_msleep_os(1000);
1484         *value = hal_mpt_ReadRFThermalMeter(pAdapter);
1485 #endif
1486
1487 }
1488
1489
1490 void hal_mpt_SetSingleCarrierTx(PADAPTER pAdapter, u8 bStart)
1491 {
1492         HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
1493
1494         pAdapter->mppriv.MptCtx.bSingleCarrier = bStart;
1495
1496         if (bStart) {/*/ Start Single Carrier.*/
1497                 /*/ Start Single Carrier.*/
1498                 /*/ 1. if OFDM block on?*/
1499                 if (!PHY_QueryBBReg(pAdapter, rFPGA0_RFMOD, bOFDMEn))
1500                         PHY_SetBBReg(pAdapter, rFPGA0_RFMOD, bOFDMEn, 1); /*set OFDM block on*/
1501
1502                 /*/ 2. set CCK test mode off, set to CCK normal mode*/
1503                 PHY_SetBBReg(pAdapter, rCCK0_System, bCCKBBMode, 0);
1504
1505                 /*/ 3. turn on scramble setting*/
1506                 PHY_SetBBReg(pAdapter, rCCK0_System, bCCKScramble, 1);
1507
1508                 /*/ 4. Turn On Continue Tx and turn off the other test modes.*/
1509 #if defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A) || defined(CONFIG_RTL8814A) || defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8821C)
1510                 if (IS_HARDWARE_TYPE_JAGUAR_AND_JAGUAR2(pAdapter))
1511                         PHY_SetBBReg(pAdapter, rSingleTone_ContTx_Jaguar, BIT18 | BIT17 | BIT16, OFDM_SingleCarrier);
1512                 else
1513 #endif /* CONFIG_RTL8812A || CONFIG_RTL8821A || CONFIG_RTL8814A || CONFIG_RTL8822B || CONFIG_RTL8821C */
1514                         PHY_SetBBReg(pAdapter, rOFDM1_LSTF, BIT30 | BIT29 | BIT28, OFDM_SingleCarrier);
1515
1516         } else {
1517                 /*/ Stop Single Carrier.*/
1518                 /*/ Stop Single Carrier.*/
1519                 /*/ Turn off all test modes.*/
1520 #if defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A) || defined(CONFIG_RTL8814A) || defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8821C)
1521                 if (IS_HARDWARE_TYPE_JAGUAR_AND_JAGUAR2(pAdapter))
1522                         PHY_SetBBReg(pAdapter, rSingleTone_ContTx_Jaguar, BIT18 | BIT17 | BIT16, OFDM_ALL_OFF);
1523                 else
1524 #endif /* CONFIG_RTL8812A || CONFIG_RTL8821A || CONFIG_RTL8814A || CONFIG_RTL8822B || CONFIG_RTL8821C */
1525                         PHY_SetBBReg(pAdapter, rOFDM1_LSTF, BIT30 | BIT29 | BIT28, OFDM_ALL_OFF);
1526
1527                 rtw_msleep_os(10);
1528                 /*/BB Reset*/
1529                 PHY_SetBBReg(pAdapter, rPMAC_Reset, bBBResetB, 0x0);
1530                 PHY_SetBBReg(pAdapter, rPMAC_Reset, bBBResetB, 0x1);
1531         }
1532 }
1533
1534
1535 void hal_mpt_SetSingleToneTx(PADAPTER pAdapter, u8 bStart)
1536 {
1537         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(pAdapter);
1538         PMPT_CONTEXT            pMptCtx = &(pAdapter->mppriv.MptCtx);
1539         u4Byte                  ulAntennaTx = pHalData->AntennaTxPath;
1540         static u4Byte           regRF = 0, regBB0 = 0, regBB1 = 0, regBB2 = 0, regBB3 = 0;
1541         u8 rfPath;
1542
1543         switch (ulAntennaTx) {
1544         case ANTENNA_B:
1545                 rfPath = ODM_RF_PATH_B;
1546                 break;
1547         case ANTENNA_C:
1548                 rfPath = ODM_RF_PATH_C;
1549                 break;
1550         case ANTENNA_D:
1551                 rfPath = ODM_RF_PATH_D;
1552                 break;
1553         case ANTENNA_A:
1554         default:
1555                 rfPath = ODM_RF_PATH_A;
1556                 break;
1557         }
1558
1559         pAdapter->mppriv.MptCtx.bSingleTone = bStart;
1560         if (bStart) {
1561                 /*/ Start Single Tone.*/
1562                 /*/ <20120326, Kordan> To amplify the power of tone for Xtal calibration. (asked by Edlu)*/
1563                 if (IS_HARDWARE_TYPE_8188E(pAdapter)) {
1564                         regRF = PHY_QueryRFReg(pAdapter, rfPath, LNA_Low_Gain_3, bRFRegOffsetMask);
1565                         PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, LNA_Low_Gain_3, BIT1, 0x1); /*/ RF LO enabled*/
1566                         PHY_SetBBReg(pAdapter, rFPGA0_RFMOD, bCCKEn, 0x0);
1567                         PHY_SetBBReg(pAdapter, rFPGA0_RFMOD, bOFDMEn, 0x0);
1568                 } else if (IS_HARDWARE_TYPE_8192E(pAdapter)) { /*/ USB need to do RF LO disable first, PCIE isn't required to follow this order.*/
1569                         /*/Set MAC REG 88C: Prevent SingleTone Fail*/
1570                         PHY_SetMacReg(pAdapter, 0x88C, 0xF00000, 0xF);
1571                         PHY_SetRFReg(pAdapter, pMptCtx->MptRfPath, LNA_Low_Gain_3, BIT1, 0x1); /*/ RF LO disabled*/
1572                         PHY_SetRFReg(pAdapter, pMptCtx->MptRfPath, RF_AC, 0xF0000, 0x2); /*/ Tx mode*/
1573                 } else if (IS_HARDWARE_TYPE_8723B(pAdapter)) {
1574                         if (pMptCtx->MptRfPath == ODM_RF_PATH_A) {
1575                                 PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, RF_AC, 0xF0000, 0x2); /*/ Tx mode*/
1576                                 PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, 0x56, 0xF, 0x1); /*/ RF LO enabled*/
1577                         } else {
1578                                 /*/ S0/S1 both use PATH A to configure*/
1579                                 PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, RF_AC, 0xF0000, 0x2); /*/ Tx mode*/
1580                                 PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, 0x76, 0xF, 0x1); /*/ RF LO enabled*/
1581                         }
1582                 } else if (IS_HARDWARE_TYPE_8703B(pAdapter)) {
1583                         if (pMptCtx->MptRfPath == ODM_RF_PATH_A) {
1584                                 PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, RF_AC, 0xF0000, 0x2); /* Tx mode */
1585                                 PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, 0x53, 0xF000, 0x1); /* RF LO enabled */
1586                         }
1587                 } else if (IS_HARDWARE_TYPE_8188F(pAdapter)) {
1588                         /*Set BB REG 88C: Prevent SingleTone Fail*/
1589                         PHY_SetBBReg(pAdapter, rFPGA0_AnalogParameter4, 0xF00000, 0xF);
1590                         PHY_SetRFReg(pAdapter, pMptCtx->MptRfPath, LNA_Low_Gain_3, BIT1, 0x1);
1591                         PHY_SetRFReg(pAdapter, pMptCtx->MptRfPath, RF_AC, 0xF0000, 0x2);
1592
1593                 } else if (IS_HARDWARE_TYPE_8723D(pAdapter)) {
1594                         if (pMptCtx->MptRfPath == ODM_RF_PATH_A) {
1595                                 PHY_SetBBReg(pAdapter, rFPGA0_RFMOD, bCCKEn|bOFDMEn, 0);
1596                                 PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, RF_AC, BIT16, 0x0);
1597                                 PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, 0x53, BIT0, 0x1);
1598                         } else {/* S0/S1 both use PATH A to configure */
1599                                 PHY_SetBBReg(pAdapter, rFPGA0_RFMOD, bCCKEn|bOFDMEn, 0);
1600                                 PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, RF_AC, BIT16, 0x0);
1601                                 PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, 0x63, BIT0, 0x1);
1602                         }
1603                 } else if (IS_HARDWARE_TYPE_JAGUAR(pAdapter) || IS_HARDWARE_TYPE_8822B(pAdapter)) {
1604 #if defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A) || defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8821C)
1605                         u1Byte p = ODM_RF_PATH_A;
1606
1607                         regRF = PHY_QueryRFReg(pAdapter, ODM_RF_PATH_A, RF_AC_Jaguar, bRFRegOffsetMask);
1608                         regBB0 = PHY_QueryBBReg(pAdapter, rA_RFE_Pinmux_Jaguar, bMaskDWord);
1609                         regBB1 = PHY_QueryBBReg(pAdapter, rB_RFE_Pinmux_Jaguar, bMaskDWord);
1610                         regBB2 = PHY_QueryBBReg(pAdapter, rA_RFE_Pinmux_Jaguar + 4, bMaskDWord);
1611                         regBB3 = PHY_QueryBBReg(pAdapter, rB_RFE_Pinmux_Jaguar + 4, bMaskDWord);
1612
1613                         PHY_SetBBReg(pAdapter, rOFDMCCKEN_Jaguar, BIT29 | BIT28, 0x0); /*/ Disable CCK and OFDM*/
1614
1615                         if (pMptCtx->MptRfPath == ODM_RF_PATH_AB) {
1616                                 for (p = ODM_RF_PATH_A; p <= ODM_RF_PATH_B; ++p) {
1617                                         PHY_SetRFReg(pAdapter, p, RF_AC_Jaguar, 0xF0000, 0x2); /*/ Tx mode: RF0x00[19:16]=4'b0010 */
1618                                         PHY_SetRFReg(pAdapter, p, RF_AC_Jaguar, 0x1F, 0x0); /*/ Lowest RF gain index: RF_0x0[4:0] = 0*/
1619                                         PHY_SetRFReg(pAdapter, p, LNA_Low_Gain_3, BIT1, 0x1); /*/ RF LO enabled*/
1620                                 }
1621                         } else {
1622                                 PHY_SetRFReg(pAdapter, pMptCtx->MptRfPath, RF_AC_Jaguar, 0xF0000, 0x2); /*/ Tx mode: RF0x00[19:16]=4'b0010 */
1623                                 PHY_SetRFReg(pAdapter, pMptCtx->MptRfPath, RF_AC_Jaguar, 0x1F, 0x0); /*/ Lowest RF gain index: RF_0x0[4:0] = 0*/
1624                                 PHY_SetRFReg(pAdapter, pMptCtx->MptRfPath, LNA_Low_Gain_3, BIT1, 0x1); /*/ RF LO enabled*/
1625                         }
1626
1627                         PHY_SetBBReg(pAdapter, rA_RFE_Pinmux_Jaguar, 0xFF00F0, 0x77007);  /*/ 0xCB0[[23:16, 7:4] = 0x77007*/
1628                         PHY_SetBBReg(pAdapter, rB_RFE_Pinmux_Jaguar, 0xFF00F0, 0x77007);  /*/ 0xCB0[[23:16, 7:4] = 0x77007*/
1629
1630                         if (pHalData->ExternalPA_5G) {
1631                                 PHY_SetBBReg(pAdapter, rA_RFE_Pinmux_Jaguar + 4, 0xFF00000, 0x12); /*/ 0xCB4[23:16] = 0x12*/
1632                                 PHY_SetBBReg(pAdapter, rB_RFE_Pinmux_Jaguar + 4, 0xFF00000, 0x12); /*/ 0xEB4[23:16] = 0x12*/
1633                         } else if (pHalData->ExternalPA_2G) {
1634                                 PHY_SetBBReg(pAdapter, rA_RFE_Pinmux_Jaguar + 4, 0xFF00000, 0x11); /*/ 0xCB4[23:16] = 0x11*/
1635                                 PHY_SetBBReg(pAdapter, rB_RFE_Pinmux_Jaguar + 4, 0xFF00000, 0x11); /*/ 0xEB4[23:16] = 0x11*/
1636                         }
1637 #endif
1638                 }
1639 #ifdef CONFIG_RTL8814A
1640                 else if (IS_HARDWARE_TYPE_8814A(pAdapter))
1641                         mpt_SetSingleTone_8814A(pAdapter, TRUE, FALSE);
1642 #endif
1643                 else    /*/ Turn On SingleTone and turn off the other test modes.*/
1644                         PHY_SetBBReg(pAdapter, rOFDM1_LSTF, BIT30 | BIT29 | BIT28, OFDM_SingleTone);
1645
1646                 write_bbreg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000500);
1647                 write_bbreg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000500);
1648
1649         } else {/*/ Stop Single Ton e.*/
1650
1651                 if (IS_HARDWARE_TYPE_8188E(pAdapter)) {
1652                         PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, LNA_Low_Gain_3, bRFRegOffsetMask, regRF);
1653                         PHY_SetBBReg(pAdapter, rFPGA0_RFMOD, bCCKEn, 0x1);
1654                         PHY_SetBBReg(pAdapter, rFPGA0_RFMOD, bOFDMEn, 0x1);
1655                 } else if (IS_HARDWARE_TYPE_8192E(pAdapter)) {
1656                         PHY_SetRFReg(pAdapter, pMptCtx->MptRfPath, RF_AC, 0xF0000, 0x3);/*/ Tx mode*/
1657                         PHY_SetRFReg(pAdapter, pMptCtx->MptRfPath, LNA_Low_Gain_3, BIT1, 0x0);/*/ RF LO disabled */
1658                         /*/ RESTORE MAC REG 88C: Enable RF Functions*/
1659                         PHY_SetMacReg(pAdapter, 0x88C, 0xF00000, 0x0);
1660                 } else if (IS_HARDWARE_TYPE_8723B(pAdapter)) {
1661                         if (pMptCtx->MptRfPath == ODM_RF_PATH_A) {
1662                                 PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, RF_AC, 0xF0000, 0x3); /*/ Rx mode*/
1663                                 PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, 0x56, 0xF, 0x0); /*/ RF LO disabled*/
1664                         } else {
1665                                 /*/ S0/S1 both use PATH A to configure*/
1666                                 PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, RF_AC, 0xF0000, 0x3); /*/ Rx mode*/
1667                                 PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, 0x76, 0xF, 0x0); /*/ RF LO disabled*/
1668                         }
1669                 } else if (IS_HARDWARE_TYPE_8703B(pAdapter)) {
1670                         if (pMptCtx->MptRfPath == ODM_RF_PATH_A) {
1671                                 PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, RF_AC, 0xF0000, 0x3); /* Rx mode */
1672                                 PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, 0x53, 0xF000, 0x0); /* RF LO disabled */
1673                         }
1674                 } else if (IS_HARDWARE_TYPE_8188F(pAdapter)) {
1675                         PHY_SetRFReg(pAdapter, pMptCtx->MptRfPath, RF_AC, 0xF0000, 0x3); /*Tx mode*/
1676                         PHY_SetRFReg(pAdapter, pMptCtx->MptRfPath, LNA_Low_Gain_3, BIT1, 0x0); /*RF LO disabled*/
1677                         /*Set BB REG 88C: Prevent SingleTone Fail*/
1678                         PHY_SetBBReg(pAdapter, rFPGA0_AnalogParameter4, 0xF00000, 0xc);
1679                 } else if (IS_HARDWARE_TYPE_8723D(pAdapter)) {
1680                         if (pMptCtx->MptRfPath == ODM_RF_PATH_A) {
1681                                 PHY_SetBBReg(pAdapter, rFPGA0_RFMOD, bCCKEn|bOFDMEn, 0x3);
1682                                 PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, RF_AC, BIT16, 0x1);
1683                                 PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, 0x53, BIT0, 0x0);
1684                         } else {        /* S0/S1 both use PATH A to configure */
1685                                 PHY_SetBBReg(pAdapter, rFPGA0_RFMOD, bCCKEn|bOFDMEn, 0x3);
1686                                 PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, RF_AC, BIT16, 0x1);
1687                                 PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, 0x63, BIT0, 0x0);
1688                         }
1689                 } else if (IS_HARDWARE_TYPE_JAGUAR(pAdapter) || IS_HARDWARE_TYPE_8822B(pAdapter)) {
1690 #if defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A) || defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8821C)
1691                         u1Byte p = ODM_RF_PATH_A;
1692
1693                         PHY_SetBBReg(pAdapter, rOFDMCCKEN_Jaguar, BIT29 | BIT28, 0x3); /*/ Disable CCK and OFDM*/
1694
1695                         if (pMptCtx->MptRfPath == ODM_RF_PATH_AB) {
1696                                 for (p = ODM_RF_PATH_A; p <= ODM_RF_PATH_B; ++p) {
1697                                         PHY_SetRFReg(pAdapter, p, RF_AC_Jaguar, bRFRegOffsetMask, regRF);
1698                                         PHY_SetRFReg(pAdapter, p, LNA_Low_Gain_3, BIT1, 0x0); /*/ RF LO disabled*/
1699                                 }
1700                         } else {
1701                                 PHY_SetRFReg(pAdapter, p, RF_AC_Jaguar, bRFRegOffsetMask, regRF);
1702                                 PHY_SetRFReg(pAdapter, p, LNA_Low_Gain_3, BIT1, 0x0); /*/ RF LO disabled*/
1703                         }
1704
1705                         PHY_SetBBReg(pAdapter, rA_RFE_Pinmux_Jaguar, bMaskDWord, regBB0);
1706                         PHY_SetBBReg(pAdapter, rB_RFE_Pinmux_Jaguar, bMaskDWord, regBB1);
1707                         PHY_SetBBReg(pAdapter, rA_RFE_Pinmux_Jaguar + 4, bMaskDWord, regBB2);
1708                         PHY_SetBBReg(pAdapter, rB_RFE_Pinmux_Jaguar + 4, bMaskDWord, regBB3);
1709 #endif
1710                 }
1711 #if defined(CONFIG_RTL8814A) || defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8821C)
1712                 else if (IS_HARDWARE_TYPE_8814A(pAdapter))
1713                         mpt_SetSingleTone_8814A(pAdapter, FALSE, FALSE);
1714
1715                 else/*/ Turn off all test modes.*/
1716                         PHY_SetBBReg(pAdapter, rSingleTone_ContTx_Jaguar, BIT18 | BIT17 | BIT16, OFDM_ALL_OFF);
1717 #endif
1718                 write_bbreg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000100);
1719                 write_bbreg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000100);
1720
1721         }
1722 }
1723
1724 void hal_mpt_SetCarrierSuppressionTx(PADAPTER pAdapter, u8 bStart)
1725 {
1726         u8 Rate;
1727
1728         pAdapter->mppriv.MptCtx.bCarrierSuppression = bStart;
1729
1730         Rate = HwRateToMPTRate(pAdapter->mppriv.rateidx);
1731         if (bStart) {/* Start Carrier Suppression.*/
1732                 if (Rate <= MPT_RATE_11M) {
1733                         /*/ 1. if CCK block on?*/
1734                         if (!read_bbreg(pAdapter, rFPGA0_RFMOD, bCCKEn))
1735                                 write_bbreg(pAdapter, rFPGA0_RFMOD, bCCKEn, bEnable);/*set CCK block on*/
1736
1737                         /*/Turn Off All Test Mode*/
1738                         if (IS_HARDWARE_TYPE_JAGUAR(pAdapter) || IS_HARDWARE_TYPE_8814A(pAdapter) /*|| IS_HARDWARE_TYPE_8822B(pAdapter)*/)
1739                                 PHY_SetBBReg(pAdapter, 0x914, BIT18 | BIT17 | BIT16, OFDM_ALL_OFF); /* rSingleTone_ContTx_Jaguar*/
1740                         else
1741                                 PHY_SetBBReg(pAdapter, rOFDM1_LSTF, BIT30 | BIT29 | BIT28, OFDM_ALL_OFF);
1742
1743                         write_bbreg(pAdapter, rCCK0_System, bCCKBBMode, 0x2);    /*/transmit mode*/
1744                         write_bbreg(pAdapter, rCCK0_System, bCCKScramble, 0x0);  /*/turn off scramble setting*/
1745
1746                         /*/Set CCK Tx Test Rate*/
1747                         write_bbreg(pAdapter, rCCK0_System, bCCKTxRate, 0x0);    /*/Set FTxRate to 1Mbps*/
1748                 }
1749
1750                 /*Set for dynamic set Power index*/
1751                 write_bbreg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000500);
1752                 write_bbreg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000500);
1753
1754         } else {/* Stop Carrier Suppression.*/
1755
1756                 if (Rate <= MPT_RATE_11M) {
1757                         write_bbreg(pAdapter, rCCK0_System, bCCKBBMode, 0x0);    /*normal mode*/
1758                         write_bbreg(pAdapter, rCCK0_System, bCCKScramble, 0x1);  /*turn on scramble setting*/
1759
1760                         /*BB Reset*/
1761                         write_bbreg(pAdapter, rPMAC_Reset, bBBResetB, 0x0);
1762                         write_bbreg(pAdapter, rPMAC_Reset, bBBResetB, 0x1);
1763                 }
1764                 /*Stop for dynamic set Power index*/
1765                 write_bbreg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000100);
1766                 write_bbreg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000100);
1767         }
1768         RTW_INFO("\n MPT_ProSetCarrierSupp() is finished.\n");
1769 }
1770
1771 void hal_mpt_SetCCKContinuousTx(PADAPTER pAdapter, u8 bStart)
1772 {
1773         u32 cckrate;
1774
1775         if (bStart) {
1776
1777                 /*/ 1. if CCK block on?*/
1778                 if (!read_bbreg(pAdapter, rFPGA0_RFMOD, bCCKEn))
1779                         write_bbreg(pAdapter, rFPGA0_RFMOD, bCCKEn, bEnable);/*set CCK block on*/
1780
1781                 /*/Turn Off All Test Mode*/
1782                 if (IS_HARDWARE_TYPE_JAGUAR_AND_JAGUAR2(pAdapter))
1783                         PHY_SetBBReg(pAdapter, 0x914, BIT18 | BIT17 | BIT16, OFDM_ALL_OFF); /*rSingleTone_ContTx_Jaguar*/
1784                 else
1785                         PHY_SetBBReg(pAdapter, rOFDM1_LSTF, BIT30 | BIT29 | BIT28, OFDM_ALL_OFF);
1786
1787                 /*/Set CCK Tx Test Rate*/
1788
1789                 cckrate  = pAdapter->mppriv.rateidx;
1790
1791                 write_bbreg(pAdapter, rCCK0_System, bCCKTxRate, cckrate);
1792                 write_bbreg(pAdapter, rCCK0_System, bCCKBBMode, 0x2);   /*/transmit mode*/
1793                 write_bbreg(pAdapter, rCCK0_System, bCCKScramble, bEnable);     /*/turn on scramble setting*/
1794
1795                 if (!IS_HARDWARE_TYPE_JAGUAR_AND_JAGUAR2(pAdapter)) {
1796                         PHY_SetBBReg(pAdapter, 0xa14, 0x300, 0x3);  /* rCCK0_RxHP 0xa15[1:0] = 11 force cck rxiq = 0*/
1797                         PHY_SetBBReg(pAdapter, rOFDM0_TRMuxPar, 0x10000, 0x1);          /*/ 0xc08[16] = 1 force ofdm rxiq = ofdm txiq*/
1798                         PHY_SetBBReg(pAdapter, rFPGA0_XA_HSSIParameter2, BIT14, 1);
1799                         PHY_SetBBReg(pAdapter, 0x0B34, BIT14, 1);
1800                 }
1801
1802                 write_bbreg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000500);
1803                 write_bbreg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000500);
1804
1805         } else {
1806
1807                 write_bbreg(pAdapter, rCCK0_System, bCCKBBMode, 0x0);   /*/normal mode*/
1808                 write_bbreg(pAdapter, rCCK0_System, bCCKScramble, bEnable);     /*/turn on scramble setting*/
1809
1810                 if (!IS_HARDWARE_TYPE_JAGUAR(pAdapter)  && !IS_HARDWARE_TYPE_8814A(pAdapter) /* && !IS_HARDWARE_TYPE_8822B(pAdapter) */) {
1811                         PHY_SetBBReg(pAdapter, 0xa14, 0x300, 0x0);/* rCCK0_RxHP 0xa15[1:0] = 2b00*/
1812                         PHY_SetBBReg(pAdapter, rOFDM0_TRMuxPar, 0x10000, 0x0);          /*/ 0xc08[16] = 0*/
1813                         PHY_SetBBReg(pAdapter, rFPGA0_XA_HSSIParameter2, BIT14, 0);
1814                         PHY_SetBBReg(pAdapter, 0x0B34, BIT14, 0);
1815                 }
1816
1817                 /*/BB Reset*/
1818                 write_bbreg(pAdapter, rPMAC_Reset, bBBResetB, 0x0);
1819                 write_bbreg(pAdapter, rPMAC_Reset, bBBResetB, 0x1);
1820
1821                 write_bbreg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000100);
1822                 write_bbreg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000100);
1823         }
1824
1825         pAdapter->mppriv.MptCtx.bCckContTx = bStart;
1826         pAdapter->mppriv.MptCtx.bOfdmContTx = _FALSE;
1827 }
1828
1829 void hal_mpt_SetOFDMContinuousTx(PADAPTER pAdapter, u8 bStart)
1830 {
1831         HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
1832
1833         if (bStart) {
1834                 if (!PHY_QueryBBReg(pAdapter, rFPGA0_RFMOD, bOFDMEn))
1835                         PHY_SetBBReg(pAdapter, rFPGA0_RFMOD, bOFDMEn, 1);/*/set OFDM block on*/
1836
1837                 /*/ 2. set CCK test mode off, set to CCK normal mode*/
1838                 PHY_SetBBReg(pAdapter, rCCK0_System, bCCKBBMode, 0);
1839
1840                 /*/ 3. turn on scramble setting*/
1841                 PHY_SetBBReg(pAdapter, rCCK0_System, bCCKScramble, 1);
1842
1843                 if (!IS_HARDWARE_TYPE_JAGUAR(pAdapter) && !IS_HARDWARE_TYPE_8814A(pAdapter) /*&& !IS_HARDWARE_TYPE_8822B(pAdapter)*/) {
1844                         PHY_SetBBReg(pAdapter, 0xa14, 0x300, 0x3);                      /* rCCK0_RxHP 0xa15[1:0] = 2b'11*/
1845                         PHY_SetBBReg(pAdapter, rOFDM0_TRMuxPar, 0x10000, 0x1);          /* 0xc08[16] = 1*/
1846                 }
1847
1848                 /*/ 4. Turn On Continue Tx and turn off the other test modes.*/
1849                 if (IS_HARDWARE_TYPE_JAGUAR(pAdapter) || IS_HARDWARE_TYPE_8814A(pAdapter) /*|| IS_HARDWARE_TYPE_8822B(pAdapter)*/)
1850                         PHY_SetBBReg(pAdapter, 0x914, BIT18 | BIT17 | BIT16, OFDM_ContinuousTx); /*rSingleTone_ContTx_Jaguar*/
1851                 else
1852                         PHY_SetBBReg(pAdapter, rOFDM1_LSTF, BIT30 | BIT29 | BIT28, OFDM_ContinuousTx);
1853
1854                 write_bbreg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000500);
1855                 write_bbreg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000500);
1856
1857         } else {
1858                 if (IS_HARDWARE_TYPE_JAGUAR(pAdapter) || IS_HARDWARE_TYPE_8814A(pAdapter) /*|| IS_HARDWARE_TYPE_8822B(pAdapter)*/)
1859                         PHY_SetBBReg(pAdapter, 0x914, BIT18 | BIT17 | BIT16, OFDM_ALL_OFF);
1860                 else
1861                         PHY_SetBBReg(pAdapter, rOFDM1_LSTF, BIT30 | BIT29 | BIT28, OFDM_ALL_OFF);
1862                 /*/Delay 10 ms*/
1863                 rtw_msleep_os(10);
1864
1865                 if (!IS_HARDWARE_TYPE_JAGUAR(pAdapter) && !IS_HARDWARE_TYPE_8814A(pAdapter) /*&&! IS_HARDWARE_TYPE_8822B(pAdapter)*/) {
1866                         PHY_SetBBReg(pAdapter, 0xa14, 0x300, 0x0);/*/ 0xa15[1:0] = 0*/
1867                         PHY_SetBBReg(pAdapter, rOFDM0_TRMuxPar, 0x10000, 0x0);/*/ 0xc08[16] = 0*/
1868                 }
1869
1870                 /*/BB Reset*/
1871                 PHY_SetBBReg(pAdapter, rPMAC_Reset, bBBResetB, 0x0);
1872                 PHY_SetBBReg(pAdapter, rPMAC_Reset, bBBResetB, 0x1);
1873
1874                 write_bbreg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000100);
1875                 write_bbreg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000100);
1876         }
1877
1878         pAdapter->mppriv.MptCtx.bCckContTx = _FALSE;
1879         pAdapter->mppriv.MptCtx.bOfdmContTx = bStart;
1880 }
1881
1882 void hal_mpt_SetContinuousTx(PADAPTER pAdapter, u8 bStart)
1883 {
1884         u8 Rate;
1885
1886         Rate = HwRateToMPTRate(pAdapter->mppriv.rateidx);
1887         pAdapter->mppriv.MptCtx.bStartContTx = bStart;
1888
1889         if (Rate <= MPT_RATE_11M)
1890                 hal_mpt_SetCCKContinuousTx(pAdapter, bStart);
1891         else if (Rate >= MPT_RATE_6M)
1892                 hal_mpt_SetOFDMContinuousTx(pAdapter, bStart);
1893 }
1894
1895 u32 hal_mpt_query_phytxok(PADAPTER      pAdapter)
1896 {
1897         PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.MptCtx);
1898         RT_PMAC_TX_INFO PMacTxInfo = pMptCtx->PMacTxInfo;
1899         u16 count = 0;
1900
1901         if (IS_MPT_CCK_RATE(PMacTxInfo.TX_RATE))
1902                 count = PHY_QueryBBReg(pAdapter, 0xF50, bMaskLWord); /* [15:0]*/
1903         else
1904                 count = PHY_QueryBBReg(pAdapter, 0xF50, bMaskHWord); /* [31:16]*/
1905
1906         if (count > 50000) {
1907                 rtw_reset_phy_trx_ok_counters(pAdapter);
1908                 pAdapter->mppriv.tx.sended += count;
1909                 count = 0;
1910         }
1911
1912         return pAdapter->mppriv.tx.sended + count;
1913
1914 }
1915
1916 #if defined(CONFIG_RTL8814A) || defined(CONFIG_RTL8821B) || defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8821C)
1917 /* for HW TX mode */
1918 static  VOID mpt_StopCckContTx(
1919         PADAPTER        pAdapter
1920 )
1921 {
1922         HAL_DATA_TYPE   *pHalData       = GET_HAL_DATA(pAdapter);
1923         PMPT_CONTEXT    pMptCtx = &(pAdapter->mppriv.MptCtx);
1924         u1Byte                  u1bReg;
1925
1926         pMptCtx->bCckContTx = FALSE;
1927         pMptCtx->bOfdmContTx = FALSE;
1928
1929         PHY_SetBBReg(pAdapter, rCCK0_System, bCCKBBMode, 0x0);  /*normal mode*/
1930         PHY_SetBBReg(pAdapter, rCCK0_System, bCCKScramble, 0x1);        /*turn on scramble setting*/
1931
1932         if (!IS_HARDWARE_TYPE_JAGUAR(pAdapter) && !IS_HARDWARE_TYPE_JAGUAR2(pAdapter)) {
1933                 PHY_SetBBReg(pAdapter, 0xa14, 0x300, 0x0);                      /* 0xa15[1:0] = 2b00*/
1934                 PHY_SetBBReg(pAdapter, rOFDM0_TRMuxPar, 0x10000, 0x0);          /* 0xc08[16] = 0*/
1935
1936                 PHY_SetBBReg(pAdapter, rFPGA0_XA_HSSIParameter2, BIT14, 0);
1937                 PHY_SetBBReg(pAdapter, 0x0B34, BIT14, 0);
1938         }
1939
1940         /*BB Reset*/
1941         PHY_SetBBReg(pAdapter, rPMAC_Reset, bBBResetB, 0x0);
1942         PHY_SetBBReg(pAdapter, rPMAC_Reset, bBBResetB, 0x1);
1943
1944         PHY_SetBBReg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000100);
1945         PHY_SetBBReg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000100);
1946
1947 }       /* mpt_StopCckContTx */
1948
1949
1950 static  VOID mpt_StopOfdmContTx(
1951         PADAPTER        pAdapter
1952 )
1953 {
1954         HAL_DATA_TYPE   *pHalData       = GET_HAL_DATA(pAdapter);
1955         PMPT_CONTEXT    pMptCtx = &(pAdapter->mppriv.MptCtx);
1956         u1Byte                  u1bReg;
1957         u4Byte                  data;
1958
1959         pMptCtx->bCckContTx = FALSE;
1960         pMptCtx->bOfdmContTx = FALSE;
1961
1962         if (IS_HARDWARE_TYPE_JAGUAR(pAdapter) || IS_HARDWARE_TYPE_JAGUAR2(pAdapter))
1963                 PHY_SetBBReg(pAdapter, 0x914, BIT18 | BIT17 | BIT16, OFDM_ALL_OFF);
1964         else
1965                 PHY_SetBBReg(pAdapter, rOFDM1_LSTF, BIT30 | BIT29 | BIT28, OFDM_ALL_OFF);
1966
1967         rtw_mdelay_os(10);
1968
1969         if (!IS_HARDWARE_TYPE_JAGUAR(pAdapter) && !IS_HARDWARE_TYPE_JAGUAR2(pAdapter)) {
1970                 PHY_SetBBReg(pAdapter, 0xa14, 0x300, 0x0);                      /* 0xa15[1:0] = 0*/
1971                 PHY_SetBBReg(pAdapter, rOFDM0_TRMuxPar, 0x10000, 0x0);          /* 0xc08[16] = 0*/
1972         }
1973
1974         /*BB Reset*/
1975         PHY_SetBBReg(pAdapter, rPMAC_Reset, bBBResetB, 0x0);
1976         PHY_SetBBReg(pAdapter, rPMAC_Reset, bBBResetB, 0x1);
1977
1978         PHY_SetBBReg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000100);
1979         PHY_SetBBReg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000100);
1980 }       /* mpt_StopOfdmContTx */
1981
1982
1983 static  VOID mpt_StartCckContTx(
1984         PADAPTER                pAdapter
1985 )
1986 {
1987         HAL_DATA_TYPE   *pHalData       = GET_HAL_DATA(pAdapter);
1988         PMPT_CONTEXT    pMptCtx = &(pAdapter->mppriv.MptCtx);
1989         u4Byte                  cckrate;
1990
1991         /* 1. if CCK block on */
1992         if (!PHY_QueryBBReg(pAdapter, rFPGA0_RFMOD, bCCKEn))
1993                 PHY_SetBBReg(pAdapter, rFPGA0_RFMOD, bCCKEn, 1);/*set CCK block on*/
1994
1995         /*Turn Off All Test Mode*/
1996         if (IS_HARDWARE_TYPE_JAGUAR_AND_JAGUAR2(pAdapter))
1997                 PHY_SetBBReg(pAdapter, 0x914, BIT18 | BIT17 | BIT16, OFDM_ALL_OFF);
1998         else
1999                 PHY_SetBBReg(pAdapter, rOFDM1_LSTF, BIT30 | BIT29 | BIT28, OFDM_ALL_OFF);
2000
2001         cckrate  = pAdapter->mppriv.rateidx;
2002
2003         PHY_SetBBReg(pAdapter, rCCK0_System, bCCKTxRate, cckrate);
2004
2005         PHY_SetBBReg(pAdapter, rCCK0_System, bCCKBBMode, 0x2);  /*transmit mode*/
2006         PHY_SetBBReg(pAdapter, rCCK0_System, bCCKScramble, 0x1);        /*turn on scramble setting*/
2007
2008         if (!IS_HARDWARE_TYPE_JAGUAR_AND_JAGUAR2(pAdapter)) {
2009                 PHY_SetBBReg(pAdapter, 0xa14, 0x300, 0x3);                      /* 0xa15[1:0] = 11 force cck rxiq = 0*/
2010                 PHY_SetBBReg(pAdapter, rOFDM0_TRMuxPar, 0x10000, 0x1);          /* 0xc08[16] = 1 force ofdm rxiq = ofdm txiq*/
2011                 PHY_SetBBReg(pAdapter, rFPGA0_XA_HSSIParameter2, BIT14, 1);
2012                 PHY_SetBBReg(pAdapter, 0x0B34, BIT14, 1);
2013         }
2014
2015         PHY_SetBBReg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000500);
2016         PHY_SetBBReg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000500);
2017
2018         pMptCtx->bCckContTx = TRUE;
2019         pMptCtx->bOfdmContTx = FALSE;
2020
2021 }       /* mpt_StartCckContTx */
2022
2023
2024 static  VOID mpt_StartOfdmContTx(
2025         PADAPTER                pAdapter
2026 )
2027 {
2028         HAL_DATA_TYPE   *pHalData       = GET_HAL_DATA(pAdapter);
2029         PMPT_CONTEXT    pMptCtx = &(pAdapter->mppriv.MptCtx);
2030
2031         /* 1. if OFDM block on?*/
2032         if (!PHY_QueryBBReg(pAdapter, rFPGA0_RFMOD, bOFDMEn))
2033                 PHY_SetBBReg(pAdapter, rFPGA0_RFMOD, bOFDMEn, 1);/*set OFDM block on*/
2034
2035         /* 2. set CCK test mode off, set to CCK normal mode*/
2036         PHY_SetBBReg(pAdapter, rCCK0_System, bCCKBBMode, 0);
2037
2038         /* 3. turn on scramble setting*/
2039         PHY_SetBBReg(pAdapter, rCCK0_System, bCCKScramble, 1);
2040
2041         if (!IS_HARDWARE_TYPE_JAGUAR(pAdapter) && !IS_HARDWARE_TYPE_JAGUAR2(pAdapter)) {
2042                 PHY_SetBBReg(pAdapter, 0xa14, 0x300, 0x3);                      /* 0xa15[1:0] = 2b'11*/
2043                 PHY_SetBBReg(pAdapter, rOFDM0_TRMuxPar, 0x10000, 0x1);          /* 0xc08[16] = 1*/
2044         }
2045
2046         /* 4. Turn On Continue Tx and turn off the other test modes.*/
2047         if (IS_HARDWARE_TYPE_JAGUAR(pAdapter) || IS_HARDWARE_TYPE_JAGUAR2(pAdapter))
2048                 PHY_SetBBReg(pAdapter, 0x914, BIT18 | BIT17 | BIT16, OFDM_ContinuousTx);
2049         else
2050                 PHY_SetBBReg(pAdapter, rOFDM1_LSTF, BIT30 | BIT29 | BIT28, OFDM_ContinuousTx);
2051
2052         PHY_SetBBReg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000500);
2053         PHY_SetBBReg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000500);
2054
2055         pMptCtx->bCckContTx = FALSE;
2056         pMptCtx->bOfdmContTx = TRUE;
2057 }       /* mpt_StartOfdmContTx */
2058
2059
2060 void mpt_ProSetPMacTx(PADAPTER  Adapter)
2061 {
2062         PMPT_CONTEXT    pMptCtx         =       &(Adapter->mppriv.MptCtx);
2063         RT_PMAC_TX_INFO PMacTxInfo      =       pMptCtx->PMacTxInfo;
2064         u32                     u4bTmp;
2065
2066         DbgPrint("SGI %d bSPreamble %d bSTBC %d bLDPC %d NDP_sound %d\n", PMacTxInfo.bSGI, PMacTxInfo.bSPreamble, PMacTxInfo.bSTBC, PMacTxInfo.bLDPC, PMacTxInfo.NDP_sound);
2067         DbgPrint("TXSC %d BandWidth %d PacketPeriod %d PacketCount %d PacketLength %d PacketPattern %d\n", PMacTxInfo.TX_SC, PMacTxInfo.BandWidth, PMacTxInfo.PacketPeriod, PMacTxInfo.PacketCount,
2068                  PMacTxInfo.PacketLength, PMacTxInfo.PacketPattern);
2069 #if 0
2070         PRINT_DATA("LSIG ", PMacTxInfo.LSIG, 3);
2071         PRINT_DATA("HT_SIG", PMacTxInfo.HT_SIG, 6);
2072         PRINT_DATA("VHT_SIG_A", PMacTxInfo.VHT_SIG_A, 6);
2073         PRINT_DATA("VHT_SIG_B", PMacTxInfo.VHT_SIG_B, 4);
2074         DbgPrint("VHT_SIG_B_CRC %x\n", PMacTxInfo.VHT_SIG_B_CRC);
2075         PRINT_DATA("VHT_Delimiter", PMacTxInfo.VHT_Delimiter, 4);
2076
2077         PRINT_DATA("Src Address", Adapter->mac_addr, 6);
2078         PRINT_DATA("Dest Address", PMacTxInfo.MacAddress, 6);
2079 #endif
2080
2081         if (PMacTxInfo.bEnPMacTx == FALSE) {
2082                 if (PMacTxInfo.Mode == CONTINUOUS_TX) {
2083                         PHY_SetBBReg(Adapter, 0xb04, 0xf, 2);                   /*      TX Stop*/
2084                         if (IS_MPT_CCK_RATE(PMacTxInfo.TX_RATE))
2085                                 mpt_StopCckContTx(Adapter);
2086                         else
2087                                 mpt_StopOfdmContTx(Adapter);
2088                 } else if (IS_MPT_CCK_RATE(PMacTxInfo.TX_RATE)) {
2089                         u4bTmp = PHY_QueryBBReg(Adapter, 0xf50, bMaskLWord);
2090                         PHY_SetBBReg(Adapter, 0xb1c, bMaskLWord, u4bTmp + 50);
2091                         PHY_SetBBReg(Adapter, 0xb04, 0xf, 2);           /*TX Stop*/
2092                 } else
2093                         PHY_SetBBReg(Adapter, 0xb04, 0xf, 2);           /*      TX Stop*/
2094
2095                 if (PMacTxInfo.Mode == OFDM_Single_Tone_TX) {
2096                         /* Stop HW TX -> Stop Continuous TX -> Stop RF Setting*/
2097                         if (IS_MPT_CCK_RATE(PMacTxInfo.TX_RATE))
2098                                 mpt_StopCckContTx(Adapter);
2099                         else
2100                                 mpt_StopOfdmContTx(Adapter);
2101
2102                         mpt_SetSingleTone_8814A(Adapter, FALSE, TRUE);
2103                 }
2104
2105                 return;
2106         }
2107
2108         if (PMacTxInfo.Mode == CONTINUOUS_TX) {
2109                 PMacTxInfo.PacketCount = 1;
2110
2111                 if (IS_MPT_CCK_RATE(PMacTxInfo.TX_RATE))
2112                         mpt_StartCckContTx(Adapter);
2113                 else
2114                         mpt_StartOfdmContTx(Adapter);
2115         } else if (PMacTxInfo.Mode == OFDM_Single_Tone_TX) {
2116                 /* Continuous TX -> HW TX -> RF Setting */
2117                 PMacTxInfo.PacketCount = 1;
2118
2119                 if (IS_MPT_CCK_RATE(PMacTxInfo.TX_RATE))
2120                         mpt_StartCckContTx(Adapter);
2121                 else
2122                         mpt_StartOfdmContTx(Adapter);
2123         } else if (PMacTxInfo.Mode == PACKETS_TX) {
2124                 if (IS_MPT_CCK_RATE(PMacTxInfo.TX_RATE) && PMacTxInfo.PacketCount == 0)
2125                         PMacTxInfo.PacketCount = 0xffff;
2126         }
2127
2128         if (IS_MPT_CCK_RATE(PMacTxInfo.TX_RATE)) {
2129                 /* 0xb1c[0:15] TX packet count 0xb1C[31:16]     SFD*/
2130                 u4bTmp = PMacTxInfo.PacketCount | (PMacTxInfo.SFD << 16);
2131                 PHY_SetBBReg(Adapter, 0xb1c, bMaskDWord, u4bTmp);
2132                 /* 0xb40 7:0 SIGNAL     15:8 SERVICE    31:16 LENGTH*/
2133                 u4bTmp = PMacTxInfo.SignalField | (PMacTxInfo.ServiceField << 8) | (PMacTxInfo.LENGTH << 16);
2134                 PHY_SetBBReg(Adapter, 0xb40, bMaskDWord, u4bTmp);
2135                 u4bTmp = PMacTxInfo.CRC16[0] | (PMacTxInfo.CRC16[1] << 8);
2136                 PHY_SetBBReg(Adapter, 0xb44, bMaskLWord, u4bTmp);
2137
2138                 if (PMacTxInfo.bSPreamble)
2139                         PHY_SetBBReg(Adapter, 0xb0c, BIT27, 0);
2140                 else
2141                         PHY_SetBBReg(Adapter, 0xb0c, BIT27, 1);
2142         } else {
2143                 PHY_SetBBReg(Adapter, 0xb18, 0xfffff, PMacTxInfo.PacketCount);
2144
2145                 u4bTmp = PMacTxInfo.LSIG[0] | ((PMacTxInfo.LSIG[1]) << 8) | ((PMacTxInfo.LSIG[2]) << 16) | ((PMacTxInfo.PacketPattern) << 24);
2146                 PHY_SetBBReg(Adapter, 0xb08, bMaskDWord, u4bTmp);       /*      Set 0xb08[23:0] = LSIG, 0xb08[31:24] =  Data init octet*/
2147
2148                 if (PMacTxInfo.PacketPattern == 0x12)
2149                         u4bTmp = 0x3000000;
2150                 else
2151                         u4bTmp = 0;
2152         }
2153
2154         if (IS_MPT_HT_RATE(PMacTxInfo.TX_RATE)) {
2155                 u4bTmp |= PMacTxInfo.HT_SIG[0] | ((PMacTxInfo.HT_SIG[1]) << 8) | ((PMacTxInfo.HT_SIG[2]) << 16);
2156                 PHY_SetBBReg(Adapter, 0xb0c, bMaskDWord, u4bTmp);
2157                 u4bTmp = PMacTxInfo.HT_SIG[3] | ((PMacTxInfo.HT_SIG[4]) << 8) | ((PMacTxInfo.HT_SIG[5]) << 16);
2158                 PHY_SetBBReg(Adapter, 0xb10, 0xffffff, u4bTmp);
2159         } else if (IS_MPT_VHT_RATE(PMacTxInfo.TX_RATE)) {
2160                 u4bTmp |= PMacTxInfo.VHT_SIG_A[0] | ((PMacTxInfo.VHT_SIG_A[1]) << 8) | ((PMacTxInfo.VHT_SIG_A[2]) << 16);
2161                 PHY_SetBBReg(Adapter, 0xb0c, bMaskDWord, u4bTmp);
2162                 u4bTmp = PMacTxInfo.VHT_SIG_A[3] | ((PMacTxInfo.VHT_SIG_A[4]) << 8) | ((PMacTxInfo.VHT_SIG_A[5]) << 16);
2163                 PHY_SetBBReg(Adapter, 0xb10, 0xffffff, u4bTmp);
2164
2165                 _rtw_memcpy(&u4bTmp, PMacTxInfo.VHT_SIG_B, 4);
2166                 PHY_SetBBReg(Adapter, 0xb14, bMaskDWord, u4bTmp);
2167         }
2168
2169         if (IS_MPT_VHT_RATE(PMacTxInfo.TX_RATE)) {
2170                 u4bTmp = (PMacTxInfo.VHT_SIG_B_CRC << 24) | PMacTxInfo.PacketPeriod;    /* for TX interval */
2171                 PHY_SetBBReg(Adapter, 0xb20, bMaskDWord, u4bTmp);
2172
2173                 _rtw_memcpy(&u4bTmp, PMacTxInfo.VHT_Delimiter, 4);
2174                 PHY_SetBBReg(Adapter, 0xb24, bMaskDWord, u4bTmp);
2175
2176                 /* 0xb28 - 0xb34 24 byte Probe Request MAC Header*/
2177                 /*& Duration & Frame control*/
2178                 PHY_SetBBReg(Adapter, 0xb28, bMaskDWord, 0x00000040);
2179
2180                 /* Address1 [0:3]*/
2181                 u4bTmp = PMacTxInfo.MacAddress[0] | (PMacTxInfo.MacAddress[1] << 8) | (PMacTxInfo.MacAddress[2] << 16) | (PMacTxInfo.MacAddress[3] << 24);
2182                 PHY_SetBBReg(Adapter, 0xb2C, bMaskDWord, u4bTmp);
2183
2184                 /* Address3 [3:0]*/
2185                 PHY_SetBBReg(Adapter, 0xb38, bMaskDWord, u4bTmp);
2186
2187                 /* Address2[0:1] & Address1 [5:4]*/
2188                 u4bTmp = PMacTxInfo.MacAddress[4] | (PMacTxInfo.MacAddress[5] << 8) | (Adapter->mac_addr[0] << 16) | (Adapter->mac_addr[1] << 24);
2189                 PHY_SetBBReg(Adapter, 0xb30, bMaskDWord, u4bTmp);
2190
2191                 /* Address2 [5:2]*/
2192                 u4bTmp = Adapter->mac_addr[2] | (Adapter->mac_addr[3] << 8) | (Adapter->mac_addr[4] << 16) | (Adapter->mac_addr[5] << 24);
2193                 PHY_SetBBReg(Adapter, 0xb34, bMaskDWord, u4bTmp);
2194
2195                 /* Sequence Control & Address3 [5:4]*/
2196                 /*u4bTmp = PMacTxInfo.MacAddress[4]|(PMacTxInfo.MacAddress[5] << 8) ;*/
2197                 /*PHY_SetBBReg(Adapter, 0xb38, bMaskDWord, u4bTmp);*/
2198         } else {
2199                 PHY_SetBBReg(Adapter, 0xb20, bMaskDWord, PMacTxInfo.PacketPeriod);      /* for TX interval*/
2200                 /* & Duration & Frame control */
2201                 PHY_SetBBReg(Adapter, 0xb24, bMaskDWord, 0x00000040);
2202
2203                 /* 0xb24 - 0xb38 24 byte Probe Request MAC Header*/
2204                 /* Address1 [0:3]*/
2205                 u4bTmp = PMacTxInfo.MacAddress[0] | (PMacTxInfo.MacAddress[1] << 8) | (PMacTxInfo.MacAddress[2] << 16) | (PMacTxInfo.MacAddress[3] << 24);
2206                 PHY_SetBBReg(Adapter, 0xb28, bMaskDWord, u4bTmp);
2207
2208                 /* Address3 [3:0]*/
2209                 PHY_SetBBReg(Adapter, 0xb34, bMaskDWord, u4bTmp);
2210
2211                 /* Address2[0:1] & Address1 [5:4]*/
2212                 u4bTmp = PMacTxInfo.MacAddress[4] | (PMacTxInfo.MacAddress[5] << 8) | (Adapter->mac_addr[0] << 16) | (Adapter->mac_addr[1] << 24);
2213                 PHY_SetBBReg(Adapter, 0xb2c, bMaskDWord, u4bTmp);
2214
2215                 /* Address2 [5:2] */
2216                 u4bTmp = Adapter->mac_addr[2] | (Adapter->mac_addr[3] << 8) | (Adapter->mac_addr[4] << 16) | (Adapter->mac_addr[5] << 24);
2217                 PHY_SetBBReg(Adapter, 0xb30, bMaskDWord, u4bTmp);
2218
2219                 /* Sequence Control & Address3 [5:4]*/
2220                 u4bTmp = PMacTxInfo.MacAddress[4] | (PMacTxInfo.MacAddress[5] << 8);
2221                 PHY_SetBBReg(Adapter, 0xb38, bMaskDWord, u4bTmp);
2222         }
2223
2224         PHY_SetBBReg(Adapter, 0xb48, bMaskByte3, PMacTxInfo.TX_RATE_HEX);
2225
2226         /* 0xb4c 3:0 TXSC       5:4     BW      7:6 m_STBC      8 NDP_Sound*/
2227         u4bTmp = (PMacTxInfo.TX_SC) | ((PMacTxInfo.BandWidth) << 4) | ((PMacTxInfo.m_STBC - 1) << 6) | ((PMacTxInfo.NDP_sound) << 8);
2228         PHY_SetBBReg(Adapter, 0xb4c, 0x1ff, u4bTmp);
2229
2230         if (IS_HARDWARE_TYPE_8814A(Adapter) || IS_HARDWARE_TYPE_8822B(Adapter)) {
2231                 u4Byte offset = 0xb44;
2232
2233                 if (IS_MPT_OFDM_RATE(PMacTxInfo.TX_RATE))
2234                         PHY_SetBBReg(Adapter, offset, 0xc0000000, 0);
2235                 else if (IS_MPT_HT_RATE(PMacTxInfo.TX_RATE))
2236                         PHY_SetBBReg(Adapter, offset, 0xc0000000, 1);
2237                 else if (IS_MPT_VHT_RATE(PMacTxInfo.TX_RATE))
2238                         PHY_SetBBReg(Adapter, offset, 0xc0000000, 2);
2239         }
2240
2241         PHY_SetBBReg(Adapter, 0xb00, BIT8, 1);          /*      Turn on PMAC*/
2242         /* PHY_SetBBReg(Adapter, 0xb04, 0xf, 2);                                 */ /* TX Stop */
2243         if (IS_MPT_CCK_RATE(PMacTxInfo.TX_RATE)) {
2244                 PHY_SetBBReg(Adapter, 0xb04, 0xf, 8);           /*TX CCK ON*/
2245                 PHY_SetBBReg(Adapter, 0xA84, BIT31, 0);
2246         } else
2247                 PHY_SetBBReg(Adapter, 0xb04, 0xf, 4);           /*      TX Ofdm ON      */
2248
2249         if (PMacTxInfo.Mode == OFDM_Single_Tone_TX)
2250                 mpt_SetSingleTone_8814A(Adapter, TRUE, TRUE);
2251
2252 }
2253 #endif
2254
2255 #endif /* CONFIG_MP_INCLUDE*/