drivers/net/wireless/rockchip_wlan/rtl8723ds/hal/phydm/phydm_adaptivity.c

   1 /******************************************************************************\r
   2  *\r
   3  * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.\r
   4  *\r
   5  * This program is free software; you can redistribute it and/or modify it\r
   6  * under the terms of version 2 of the GNU General Public License as\r
   7  * published by the Free Software Foundation.\r
   8  *\r
   9  * This program is distributed in the hope that it will be useful, but WITHOUT\r
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\r
  11  * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\r
  12  * more details.\r
  13  *\r
  14  * You should have received a copy of the GNU General Public License along with\r
  15  * this program; if not, write to the Free Software Foundation, Inc.,\r
  16  * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA\r
  17  *\r
  18  *\r
  19  ******************************************************************************/\r
  20 \r
  21 //============================================================\r
  22 // include files\r
  23 //============================================================\r
  24 #include "mp_precomp.h"\r
  25 #include "phydm_precomp.h"\r
  26 \r
  27 #if (DM_ODM_SUPPORT_TYPE & ODM_WIN)\r
  28 #if WPP_SOFTWARE_TRACE\r
  29 #include "PhyDM_Adaptivity.tmh"\r
  30 #endif\r
  31 #endif\r
  32 \r
  33 \r
  34 VOID\r
  35 Phydm_CheckAdaptivity(\r
  36         IN              PVOID                   pDM_VOID\r
  37 )\r
  38 {\r
  39         PDM_ODM_T               pDM_Odm = (PDM_ODM_T)pDM_VOID;\r
  40         PADAPTIVITY_STATISTICS  Adaptivity = (PADAPTIVITY_STATISTICS)PhyDM_Get_Structure(pDM_Odm, PHYDM_ADAPTIVITY);\r
  41         \r
  42         if (pDM_Odm->SupportAbility & ODM_BB_ADAPTIVITY) {\r
  43 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)\r
  44                 if (pDM_Odm->APTotalNum > Adaptivity->APNumTH) {\r
  45                         pDM_Odm->Adaptivity_enable = FALSE;\r
  46                         pDM_Odm->adaptivity_flag = FALSE;\r
  47                         ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("AP total num > %d!!, disable adaptivity\n", Adaptivity->APNumTH));\r
  48                 } else\r
  49 #endif\r
  50                 {\r
  51                         if (Adaptivity->DynamicLinkAdaptivity || Adaptivity->AcsForAdaptivity) {\r
  52                                 if (pDM_Odm->bLinked && Adaptivity->bCheck == FALSE) {\r
  53                                         Phydm_NHMCounterStatistics(pDM_Odm);\r
  54                                         Phydm_CheckEnvironment(pDM_Odm);\r
  55                                 } else if (!pDM_Odm->bLinked)\r
  56                                         Adaptivity->bCheck = FALSE;\r
  57                         } else {\r
  58                                 pDM_Odm->Adaptivity_enable = TRUE;\r
  59 \r
  60                                 if (pDM_Odm->SupportICType & (ODM_IC_11AC_GAIN_IDX_EDCCA | ODM_IC_11N_GAIN_IDX_EDCCA))\r
  61                                         pDM_Odm->adaptivity_flag = FALSE;\r
  62                                 else\r
  63                                         pDM_Odm->adaptivity_flag = TRUE;\r
  64                         }\r
  65                 }\r
  66         } else {\r
  67                 pDM_Odm->Adaptivity_enable = FALSE;\r
  68                 pDM_Odm->adaptivity_flag = FALSE;\r
  69         }\r
  70 \r
  71         \r
  72 \r
  73 }\r
  74 \r
  75 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)\r
  76 BOOLEAN\r
  77 Phydm_CheckChannelPlan(\r
  78         IN              PVOID                   pDM_VOID\r
  79 )\r
  80 {\r
  81         PDM_ODM_T               pDM_Odm = (PDM_ODM_T)pDM_VOID;\r
  82         PADAPTER                pAdapter        = pDM_Odm->Adapter;\r
  83         PMGNT_INFO              pMgntInfo = &(pAdapter->MgntInfo);\r
  84         \r
  85         if (pMgntInfo->RegEnableAdaptivity == 2) {\r
  86                 if (pDM_Odm->Carrier_Sense_enable == FALSE) {           /*check domain Code for Adaptivity or CarrierSense*/\r
  87                         if ((*pDM_Odm->pBandType == ODM_BAND_5G) &&\r
  88                             !(pDM_Odm->odm_Regulation5G == REGULATION_ETSI || pDM_Odm->odm_Regulation5G == REGULATION_WW)) {\r
  89                                 ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("Adaptivity skip 5G domain code : %d\n", pDM_Odm->odm_Regulation5G));\r
  90                                 pDM_Odm->Adaptivity_enable = FALSE;\r
  91                                 pDM_Odm->adaptivity_flag = FALSE;\r
  92                                 return TRUE;\r
  93                         } else if ((*pDM_Odm->pBandType == ODM_BAND_2_4G) &&\r
  94                                    !(pDM_Odm->odm_Regulation2_4G == REGULATION_ETSI || pDM_Odm->odm_Regulation2_4G == REGULATION_WW)) {\r
  95                                 ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("Adaptivity skip 2.4G domain code : %d\n", pDM_Odm->odm_Regulation2_4G));\r
  96                                 pDM_Odm->Adaptivity_enable = FALSE;\r
  97                                 pDM_Odm->adaptivity_flag = FALSE;\r
  98                                 return TRUE;\r
  99 \r
 100                         } else if ((*pDM_Odm->pBandType != ODM_BAND_2_4G) && (*pDM_Odm->pBandType != ODM_BAND_5G)) {\r
 101                                 ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("Adaptivity neither 2G nor 5G band, return\n"));\r
 102                                 pDM_Odm->Adaptivity_enable = FALSE;\r
 103                                 pDM_Odm->adaptivity_flag = FALSE;\r
 104                                 return TRUE;\r
 105                         }\r
 106                 } else {\r
 107                         if ((*pDM_Odm->pBandType == ODM_BAND_5G) &&\r
 108                             !(pDM_Odm->odm_Regulation5G == REGULATION_MKK || pDM_Odm->odm_Regulation5G == REGULATION_WW)) {\r
 109                                 ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("CarrierSense skip 5G domain code : %d\n", pDM_Odm->odm_Regulation5G));\r
 110                                 pDM_Odm->Adaptivity_enable = FALSE;\r
 111                                 pDM_Odm->adaptivity_flag = FALSE;\r
 112                                 return TRUE;\r
 113                         }\r
 114 \r
 115                         else if ((*pDM_Odm->pBandType == ODM_BAND_2_4G) &&\r
 116                                    !(pDM_Odm->odm_Regulation2_4G == REGULATION_MKK  || pDM_Odm->odm_Regulation2_4G == REGULATION_WW)) {\r
 117                                 ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("CarrierSense skip 2.4G domain code : %d\n", pDM_Odm->odm_Regulation2_4G));\r
 118                                 pDM_Odm->Adaptivity_enable = FALSE;\r
 119                                 pDM_Odm->adaptivity_flag = FALSE;\r
 120                                 return TRUE;\r
 121 \r
 122                         } else if ((*pDM_Odm->pBandType != ODM_BAND_2_4G) && (*pDM_Odm->pBandType != ODM_BAND_5G)) {\r
 123                                 ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("CarrierSense neither 2G nor 5G band, return\n"));\r
 124                                 pDM_Odm->Adaptivity_enable = FALSE;\r
 125                                 pDM_Odm->adaptivity_flag = FALSE;\r
 126                                 return TRUE;\r
 127                         }\r
 128                 }\r
 129         }\r
 130 \r
 131         return FALSE;\r
 132 \r
 133 }\r
 134 #endif\r
 135 \r
 136 VOID\r
 137 Phydm_NHMCounterStatisticsInit(\r
 138         IN              PVOID                   pDM_VOID\r
 139 )\r
 140 {\r
 141         PDM_ODM_T               pDM_Odm = (PDM_ODM_T)pDM_VOID;\r
 142 \r
 143         if (pDM_Odm->SupportICType & ODM_IC_11N_SERIES) {\r
 144                 /*PHY parameters initialize for n series*/\r
 145                 ODM_Write2Byte(pDM_Odm, ODM_REG_CCX_PERIOD_11N+ 2, 0xC350);                     /*0x894[31:16]=0x0xC350 Time duration for NHM unit: us, 0xc350=200ms*/\r
 146                 ODM_Write2Byte(pDM_Odm, ODM_REG_NHM_TH9_TH10_11N + 2, 0xffff);          /*0x890[31:16]=0xffff           th_9, th_10*/\r
 147                 ODM_Write4Byte(pDM_Odm, ODM_REG_NHM_TH3_TO_TH0_11N, 0xffffff50);                /*0x898=0xffffff52                      th_3, th_2, th_1, th_0*/\r
 148                 ODM_Write4Byte(pDM_Odm, ODM_REG_NHM_TH7_TO_TH4_11N, 0xffffffff);                /*0x89c=0xffffffff                      th_7, th_6, th_5, th_4*/\r
 149                 ODM_SetBBReg(pDM_Odm, ODM_REG_FPGA0_IQK_11N, bMaskByte0, 0xff);         /*0xe28[7:0]=0xff                       th_8*/\r
 150                 ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH9_TH10_11N, BIT10 | BIT9 | BIT8, 0x1);      /*0x890[10:8]=1                 ignoreCCA ignore PHYTXON enable CCX*/\r
 151                 ODM_SetBBReg(pDM_Odm, ODM_REG_OFDM_FA_RSTC_11N, BIT7, 0x1);                     /*0xc0c[7]=1                            max power among all RX ants*/\r
 152         }\r
 153 #if (RTL8195A_SUPPORT == 0)\r
 154         else if (pDM_Odm->SupportICType & ODM_IC_11AC_SERIES) {\r
 155                 /*PHY parameters initialize for ac series*/\r
 156                 ODM_Write2Byte(pDM_Odm, ODM_REG_CCX_PERIOD_11AC+ 2, 0xC350);                    /*0x990[31:16]=0xC350   Time duration for NHM unit: us, 0xc350=200ms*/\r
 157                 ODM_Write2Byte(pDM_Odm, ODM_REG_NHM_TH9_TH10_11AC + 2, 0xffff);         /*0x994[31:16]=0xffff           th_9, th_10*/\r
 158                 ODM_Write4Byte(pDM_Odm, ODM_REG_NHM_TH3_TO_TH0_11AC, 0xffffff50);       /*0x998=0xffffff52                      th_3, th_2, th_1, th_0*/\r
 159                 ODM_Write4Byte(pDM_Odm, ODM_REG_NHM_TH7_TO_TH4_11AC, 0xffffffff);       /*0x99c=0xffffffff                      th_7, th_6, th_5, th_4*/\r
 160                 ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH8_11AC, bMaskByte0, 0xff);          /*0x9a0[7:0]=0xff                       th_8*/\r
 161                 ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH9_TH10_11AC, BIT8 | BIT9 | BIT10, 0x1); /*0x994[10:8]=1                     ignoreCCA ignore PHYTXON        enable CCX*/\r
 162                 ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_9E8_11AC, BIT0, 0x1);                         /*0x9e8[7]=1                            max power among all RX ants*/\r
 163 \r
 164         }\r
 165 #endif\r
 166 }\r
 167 \r
 168 VOID\r
 169 Phydm_NHMCounterStatistics(\r
 170         IN              PVOID                   pDM_VOID\r
 171 )\r
 172 {\r
 173         PDM_ODM_T       pDM_Odm = (PDM_ODM_T)pDM_VOID;\r
 174 \r
 175         if (!(pDM_Odm->SupportAbility & ODM_BB_NHM_CNT))\r
 176                 return;\r
 177 \r
 178         /*Get NHM report*/\r
 179         Phydm_GetNHMCounterStatistics(pDM_Odm);\r
 180 \r
 181         /*Reset NHM counter*/\r
 182         Phydm_NHMCounterStatisticsReset(pDM_Odm);\r
 183 }\r
 184 \r
 185 VOID\r
 186 Phydm_GetNHMCounterStatistics(\r
 187         IN              PVOID                   pDM_VOID\r
 188 )\r
 189 {\r
 190         PDM_ODM_T       pDM_Odm = (PDM_ODM_T)pDM_VOID;\r
 191         u4Byte          value32 = 0;\r
 192 #if (RTL8195A_SUPPORT == 0)\r
 193         if (pDM_Odm->SupportICType & ODM_IC_11AC_SERIES)\r
 194                 value32 = ODM_GetBBReg(pDM_Odm, ODM_REG_NHM_CNT_11AC, bMaskDWord);\r
 195         else if (pDM_Odm->SupportICType & ODM_IC_11N_SERIES)\r
 196 #endif\r
 197                 value32 = ODM_GetBBReg(pDM_Odm, ODM_REG_NHM_CNT_11N, bMaskDWord);\r
 198 \r
 199         pDM_Odm->NHM_cnt_0 = (u1Byte)(value32 & bMaskByte0);\r
 200         pDM_Odm->NHM_cnt_1 = (u1Byte)((value32 & bMaskByte1) >> 8);\r
 201 \r
 202 }\r
 203 \r
 204 VOID\r
 205 Phydm_NHMCounterStatisticsReset(\r
 206         IN              PVOID                   pDM_VOID\r
 207 )\r
 208 {\r
 209         PDM_ODM_T       pDM_Odm = (PDM_ODM_T)pDM_VOID;\r
 210 \r
 211         if (pDM_Odm->SupportICType & ODM_IC_11N_SERIES) {\r
 212                 ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH9_TH10_11N, BIT1, 0);\r
 213                 ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH9_TH10_11N, BIT1, 1);\r
 214         }\r
 215 #if (RTL8195A_SUPPORT == 0)\r
 216         else if (pDM_Odm->SupportICType & ODM_IC_11AC_SERIES) {\r
 217                 ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH9_TH10_11AC, BIT1, 0);\r
 218                 ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH9_TH10_11AC, BIT1, 1);\r
 219         }\r
 220 \r
 221 #endif\r
 222 \r
 223 }\r
 224 \r
 225 VOID\r
 226 Phydm_SetEDCCAThreshold(\r
 227         IN      PVOID   pDM_VOID,\r
 228         IN      s1Byte  H2L,\r
 229         IN      s1Byte  L2H\r
 230 )\r
 231 {\r
 232         PDM_ODM_T               pDM_Odm = (PDM_ODM_T)pDM_VOID;\r
 233 \r
 234         if (pDM_Odm->SupportICType & ODM_IC_11N_SERIES)\r
 235                 ODM_SetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, bMaskByte2|bMaskByte0, (u4Byte)((u1Byte)L2H|(u1Byte)H2L<<16));\r
 236 #if (RTL8195A_SUPPORT == 0)\r
 237         else if (pDM_Odm->SupportICType & ODM_IC_11AC_SERIES)\r
 238                 ODM_SetBBReg(pDM_Odm, rFPGA0_XB_LSSIReadBack, bMaskLWord, (u2Byte)((u1Byte)L2H|(u1Byte)H2L<<8));\r
 239 #endif\r
 240 \r
 241 }\r
 242 \r
 243 VOID\r
 244 Phydm_SetLNA(\r
 245         IN      PVOID                           pDM_VOID,\r
 246         IN      PhyDM_set_LNA   type\r
 247 )\r
 248 {\r
 249         PDM_ODM_T               pDM_Odm = (PDM_ODM_T)pDM_VOID;\r
 250         \r
 251         if (pDM_Odm->SupportICType & (ODM_RTL8188E | ODM_RTL8192E)) {\r
 252                 if (type == PhyDM_disable_LNA) {\r
 253                         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xef, 0x80000, 0x1);\r
 254                         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x30, 0xfffff, 0x18000);   /*select Rx mode*/\r
 255                         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x31, 0xfffff, 0x0000f);\r
 256                         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x32, 0xfffff, 0x37f82);   /*disable LNA*/\r
 257                         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xef, 0x80000, 0x0);\r
 258                         if (pDM_Odm->RFType > ODM_1T1R) {\r
 259                                 ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0xef, 0x80000, 0x1);\r
 260                                 ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x30, 0xfffff, 0x18000);\r
 261                                 ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x31, 0xfffff, 0x0000f);\r
 262                                 ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x32, 0xfffff, 0x37f82);\r
 263                                 ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0xef, 0x80000, 0x0);\r
 264                         }\r
 265                 } else if (type == PhyDM_enable_LNA) {\r
 266                         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xef, 0x80000, 0x1);\r
 267                         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x30, 0xfffff, 0x18000);   /*select Rx mode*/\r
 268                         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x31, 0xfffff, 0x0000f);\r
 269                         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x32, 0xfffff, 0x77f82);   /*back to normal*/\r
 270                         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xef, 0x80000, 0x0);\r
 271                         if (pDM_Odm->RFType > ODM_1T1R) {\r
 272                                 ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0xef, 0x80000, 0x1);\r
 273                                 ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x30, 0xfffff, 0x18000);\r
 274                                 ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x31, 0xfffff, 0x0000f);\r
 275                                 ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x32, 0xfffff, 0x77f82);\r
 276                                 ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0xef, 0x80000, 0x0);\r
 277                         }\r
 278                 }\r
 279         } else if (pDM_Odm->SupportICType & ODM_RTL8723B) {\r
 280                 if (type == PhyDM_disable_LNA) {\r
 281                         /*S0*/\r
 282                         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xef, 0x80000, 0x1);\r
 283                         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x30, 0xfffff, 0x18000);   /*select Rx mode*/\r
 284                         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x31, 0xfffff, 0x0001f);\r
 285                         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x32, 0xfffff, 0xe6137);   /*disable LNA*/\r
 286                         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xef, 0x80000, 0x0);\r
 287                         /*S1*/\r
 288                         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xed, 0x00020, 0x1);\r
 289                         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x43, 0xfffff, 0x3008d);   /*select Rx mode and disable LNA*/\r
 290                         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xed, 0x00020, 0x0);\r
 291                 } else if (type == PhyDM_enable_LNA) {\r
 292                         /*S0*/\r
 293                         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xef, 0x80000, 0x1);\r
 294                         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x30, 0xfffff, 0x18000);   /*select Rx mode*/\r
 295                         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x31, 0xfffff, 0x0001f);\r
 296                         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x32, 0xfffff, 0xe6177);   /*disable LNA*/\r
 297                         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xef, 0x80000, 0x0);\r
 298                         /*S1*/\r
 299                         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xed, 0x00020, 0x1);\r
 300                         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x43, 0xfffff, 0x300bd);   /*select Rx mode and disable LNA*/\r
 301                         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xed, 0x00020, 0x0);\r
 302                 }\r
 303         \r
 304         } else if (pDM_Odm->SupportICType & ODM_RTL8812) {\r
 305                 if (type == PhyDM_disable_LNA) {\r
 306                         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xef, 0x80000, 0x1);\r
 307                         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x30, 0xfffff, 0x18000);   /*select Rx mode*/\r
 308                         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x31, 0xfffff, 0x3f7ff);\r
 309                         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x32, 0xfffff, 0xc22bf);   /*disable LNA*/\r
 310                         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xef, 0x80000, 0x0);\r
 311                                 if (pDM_Odm->RFType > ODM_1T1R) {\r
 312                                         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0xef, 0x80000, 0x1);\r
 313                                         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x30, 0xfffff, 0x18000);   /*select Rx mode*/\r
 314                                         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x31, 0xfffff, 0x3f7ff);\r
 315                                         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x32, 0xfffff, 0xc22bf);   /*disable LNA*/\r
 316                                         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0xef, 0x80000, 0x0);\r
 317                                 }\r
 318                 } else if (type == PhyDM_enable_LNA) {\r
 319                         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xef, 0x80000, 0x1);\r
 320                         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x30, 0xfffff, 0x18000);   /*select Rx mode*/\r
 321                         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x31, 0xfffff, 0x3f7ff);\r
 322                         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x32, 0xfffff, 0xc26bf);   /*disable LNA*/\r
 323                         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xef, 0x80000, 0x0);\r
 324                                 if (pDM_Odm->RFType > ODM_1T1R) {\r
 325                                         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0xef, 0x80000, 0x1);\r
 326                                         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x30, 0xfffff, 0x18000);   /*select Rx mode*/\r
 327                                         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x31, 0xfffff, 0x3f7ff);\r
 328                                         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x32, 0xfffff, 0xc26bf);   /*disable LNA*/\r
 329                                         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0xef, 0x80000, 0x0);\r
 330                                 }\r
 331                 }\r
 332         } else if (pDM_Odm->SupportICType & (ODM_RTL8821 | ODM_RTL8881A)) {\r
 333                 if (type == PhyDM_disable_LNA) {\r
 334                         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xef, 0x80000, 0x1);\r
 335                         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x30, 0xfffff, 0x18000);   /*select Rx mode*/\r
 336                         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x31, 0xfffff, 0x0002f);\r
 337                         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x32, 0xfffff, 0xfb09b);   /*disable LNA*/\r
 338                         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xef, 0x80000, 0x0);\r
 339                 } else if (type == PhyDM_enable_LNA) {\r
 340                         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xef, 0x80000, 0x1);\r
 341                         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x30, 0xfffff, 0x18000);   /*select Rx mode*/\r
 342                         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x31, 0xfffff, 0x0002f);\r
 343                         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x32, 0xfffff, 0xfb0bb);   /*disable LNA*/\r
 344                         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xef, 0x80000, 0x0);       \r
 345                 }\r
 346         }\r
 347 }\r
 348 \r
 349 \r
 350 \r
 351 VOID\r
 352 Phydm_SetTRxMux(\r
 353         IN      PVOID                           pDM_VOID,\r
 354         IN      PhyDM_Trx_MUX_Type      txMode,\r
 355         IN      PhyDM_Trx_MUX_Type      rxMode\r
 356 )\r
 357 {\r
 358         PDM_ODM_T               pDM_Odm = (PDM_ODM_T)pDM_VOID;\r
 359 \r
 360         if (pDM_Odm->SupportICType & ODM_IC_11N_SERIES) {\r
 361                 ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_RPT_FORMAT_11N, BIT3 | BIT2 | BIT1, txMode);                  /*set TXmod to standby mode to remove outside noise affect*/\r
 362                 ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_RPT_FORMAT_11N, BIT22 | BIT21 | BIT20, rxMode);               /*set RXmod to standby mode to remove outside noise affect*/\r
 363                 if (pDM_Odm->RFType > ODM_1T1R) {\r
 364                         ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_RPT_FORMAT_11N_B, BIT3 | BIT2 | BIT1, txMode);                /*set TXmod to standby mode to remove outside noise affect*/\r
 365                         ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_RPT_FORMAT_11N_B, BIT22 | BIT21 | BIT20, rxMode);     /*set RXmod to standby mode to remove outside noise affect*/\r
 366                 }\r
 367         }\r
 368 #if (RTL8195A_SUPPORT == 0)\r
 369         else if (pDM_Odm->SupportICType & ODM_IC_11AC_SERIES) {\r
 370                 ODM_SetBBReg(pDM_Odm, ODM_REG_TRMUX_11AC, BIT11 | BIT10 | BIT9 | BIT8, txMode);                         /*set TXmod to standby mode to remove outside noise affect*/\r
 371                 ODM_SetBBReg(pDM_Odm, ODM_REG_TRMUX_11AC, BIT7 | BIT6 | BIT5 | BIT4, rxMode);                           /*set RXmod to standby mode to remove outside noise affect*/\r
 372                 if (pDM_Odm->RFType > ODM_1T1R) {\r
 373                         ODM_SetBBReg(pDM_Odm, ODM_REG_TRMUX_11AC_B, BIT11 | BIT10 | BIT9 | BIT8, txMode);               /*set TXmod to standby mode to remove outside noise affect*/\r
 374                         ODM_SetBBReg(pDM_Odm, ODM_REG_TRMUX_11AC_B, BIT7 | BIT6 | BIT5 | BIT4, rxMode);                 /*set RXmod to standby mode to remove outside noise affect*/\r
 375                 }\r
 376         }\r
 377 #endif\r
 378 \r
 379 }\r
 380 \r
 381 VOID\r
 382 Phydm_MACEDCCAState(\r
 383         IN      PVOID                                   pDM_VOID,\r
 384         IN      PhyDM_MACEDCCA_Type             State\r
 385 )\r
 386 {\r
 387         PDM_ODM_T               pDM_Odm = (PDM_ODM_T)pDM_VOID;\r
 388         if (State == PhyDM_IGNORE_EDCCA) {\r
 389                 ODM_SetMACReg(pDM_Odm, REG_TX_PTCL_CTRL, BIT15, 1);     /*ignore EDCCA  reg520[15]=1*/\r
 390 /*              ODM_SetMACReg(pDM_Odm, REG_RD_CTRL, BIT11, 0);                  *//*reg524[11]=0*/\r
 391         } else {        /*don't set MAC ignore EDCCA signal*/\r
 392                 ODM_SetMACReg(pDM_Odm, REG_TX_PTCL_CTRL, BIT15, 0);     /*don't ignore EDCCA     reg520[15]=0\14*/\r
 393 /*              ODM_SetMACReg(pDM_Odm, REG_RD_CTRL, BIT11, 1);                  *//*reg524[11]=1        */\r
 394         }\r
 395         ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("EDCCA enable State = %d\n", State));\r
 396 \r
 397 }\r
 398 \r
 399 BOOLEAN\r
 400 Phydm_CalNHMcnt(\r
 401         IN              PVOID           pDM_VOID\r
 402 )\r
 403 {\r
 404         PDM_ODM_T               pDM_Odm = (PDM_ODM_T)pDM_VOID;\r
 405         u2Byte                  Base = 0;\r
 406 \r
 407         Base = pDM_Odm->NHM_cnt_0 + pDM_Odm->NHM_cnt_1;\r
 408 \r
 409         if (Base != 0) {\r
 410                 pDM_Odm->NHM_cnt_0 = ((pDM_Odm->NHM_cnt_0) << 8) / Base;\r
 411                 pDM_Odm->NHM_cnt_1 = ((pDM_Odm->NHM_cnt_1) << 8) / Base;\r
 412         }\r
 413         if ((pDM_Odm->NHM_cnt_0 - pDM_Odm->NHM_cnt_1) >= 100)\r
 414                 return TRUE;                    /*clean environment*/\r
 415         else\r
 416                 return FALSE;           /*noisy environment*/\r
 417 \r
 418 }\r
 419 \r
 420 \r
 421 VOID\r
 422 Phydm_CheckEnvironment(\r
 423         IN      PVOID   pDM_VOID\r
 424 )\r
 425 {\r
 426         PDM_ODM_T       pDM_Odm = (PDM_ODM_T)pDM_VOID;\r
 427         PADAPTIVITY_STATISTICS  Adaptivity = (PADAPTIVITY_STATISTICS)PhyDM_Get_Structure(pDM_Odm, PHYDM_ADAPTIVITY);\r
 428         BOOLEAN         isCleanEnvironment = FALSE;\r
 429 #if (DM_ODM_SUPPORT_TYPE & ODM_AP)\r
 430         prtl8192cd_priv priv = pDM_Odm->priv;\r
 431 #endif\r
 432 \r
 433         if (Adaptivity->bFirstLink == TRUE) {\r
 434                 if (pDM_Odm->SupportICType & (ODM_IC_11AC_GAIN_IDX_EDCCA | ODM_IC_11N_GAIN_IDX_EDCCA))\r
 435                         pDM_Odm->adaptivity_flag = FALSE;\r
 436                 else\r
 437                         pDM_Odm->adaptivity_flag = TRUE;\r
 438 \r
 439                 Adaptivity->bFirstLink = FALSE;\r
 440                 return;\r
 441         } else {\r
 442                 if (Adaptivity->NHMWait < 3) {          /*Start enter NHM after 4 NHMWait*/\r
 443                         Adaptivity->NHMWait++;\r
 444                         Phydm_NHMCounterStatistics(pDM_Odm);\r
 445                         return;\r
 446                 } else {\r
 447                         Phydm_NHMCounterStatistics(pDM_Odm);\r
 448                         isCleanEnvironment = Phydm_CalNHMcnt(pDM_Odm);\r
 449                         if (isCleanEnvironment == TRUE) {\r
 450                                 pDM_Odm->TH_L2H_ini = Adaptivity->TH_L2H_ini_backup;                    /*adaptivity mode*/\r
 451                                 pDM_Odm->TH_EDCCA_HL_diff = Adaptivity->TH_EDCCA_HL_diff_backup;\r
 452 \r
 453                                 pDM_Odm->Adaptivity_enable = TRUE;\r
 454 \r
 455                                 if (pDM_Odm->SupportICType & (ODM_IC_11AC_GAIN_IDX_EDCCA | ODM_IC_11N_GAIN_IDX_EDCCA))\r
 456                                         pDM_Odm->adaptivity_flag = FALSE;\r
 457                                 else\r
 458                                         pDM_Odm->adaptivity_flag = TRUE;\r
 459 #if (DM_ODM_SUPPORT_TYPE & ODM_AP)                              \r
 460                                 priv->pshare->rf_ft_var.isCleanEnvironment = TRUE;\r
 461 #endif\r
 462                         } else {\r
 463                                 if (!Adaptivity->AcsForAdaptivity) {                    \r
 464                                         pDM_Odm->TH_L2H_ini = pDM_Odm->TH_L2H_ini_mode2;                        /*mode2*/\r
 465                                         pDM_Odm->TH_EDCCA_HL_diff = pDM_Odm->TH_EDCCA_HL_diff_mode2;\r
 466 \r
 467                                         pDM_Odm->adaptivity_flag = FALSE;\r
 468                                         pDM_Odm->Adaptivity_enable = FALSE;\r
 469                                 }\r
 470 #if (DM_ODM_SUPPORT_TYPE & ODM_AP)\r
 471                                 priv->pshare->rf_ft_var.isCleanEnvironment = FALSE;\r
 472 #endif\r
 473                         }\r
 474                         Adaptivity->NHMWait = 0;\r
 475                         Adaptivity->bFirstLink = TRUE;\r
 476                         Adaptivity->bCheck = TRUE;\r
 477                 }\r
 478 \r
 479         }\r
 480 \r
 481 \r
 482 }\r
 483 \r
 484 VOID\r
 485 Phydm_SearchPwdBLowerBound(\r
 486         IN              PVOID           pDM_VOID\r
 487 )\r
 488 {\r
 489         PDM_ODM_T               pDM_Odm = (PDM_ODM_T)pDM_VOID;\r
 490         PADAPTIVITY_STATISTICS  Adaptivity = (PADAPTIVITY_STATISTICS)PhyDM_Get_Structure(pDM_Odm, PHYDM_ADAPTIVITY);\r
 491         u4Byte                  value32 = 0;\r
 492         u1Byte                  cnt;\r
 493         u1Byte                  txEdcca1 = 0, txEdcca0 = 0;\r
 494         BOOLEAN                 bAdjust = TRUE;\r
 495         s1Byte                  TH_L2H_dmc, TH_H2L_dmc, IGI_target = 0x32;\r
 496         s1Byte                  Diff;\r
 497         u1Byte                  IGI = Adaptivity->IGI_Base + 30 + (u1Byte)pDM_Odm->TH_L2H_ini - (u1Byte)pDM_Odm->TH_EDCCA_HL_diff;\r
 498 \r
 499         if (pDM_Odm->SupportICType & (ODM_RTL8723B | ODM_RTL8188E | ODM_RTL8192E | ODM_RTL8812 | ODM_RTL8821 | ODM_RTL8881A))\r
 500                 Phydm_SetLNA(pDM_Odm, PhyDM_disable_LNA);\r
 501         else {\r
 502                 Phydm_SetTRxMux(pDM_Odm, PhyDM_STANDBY_MODE, PhyDM_STANDBY_MODE);\r
 503                 odm_PauseDIG(pDM_Odm, PHYDM_PAUSE, PHYDM_PAUSE_LEVEL_0, 0x7e);\r
 504         }\r
 505 \r
 506         Diff = IGI_target - (s1Byte)IGI;\r
 507         TH_L2H_dmc = pDM_Odm->TH_L2H_ini + Diff;\r
 508         if (TH_L2H_dmc > 10)\r
 509                 TH_L2H_dmc = 10;\r
 510         TH_H2L_dmc = TH_L2H_dmc - pDM_Odm->TH_EDCCA_HL_diff;\r
 511 \r
 512         Phydm_SetEDCCAThreshold(pDM_Odm, TH_H2L_dmc, TH_L2H_dmc);\r
 513         ODM_delay_ms(5);\r
 514 \r
 515         while (bAdjust) {\r
 516                 for (cnt = 0; cnt < 20; cnt++) {\r
 517                         if (pDM_Odm->SupportICType & ODM_IC_11N_SERIES)\r
 518                                 value32 = ODM_GetBBReg(pDM_Odm, ODM_REG_RPT_11N, bMaskDWord);\r
 519 #if (RTL8195A_SUPPORT == 0)\r
 520                         else if (pDM_Odm->SupportICType & ODM_IC_11AC_SERIES)\r
 521                                 value32 = ODM_GetBBReg(pDM_Odm, ODM_REG_RPT_11AC, bMaskDWord);\r
 522 #endif\r
 523                         if (value32 & BIT30 && (pDM_Odm->SupportICType & (ODM_RTL8723B | ODM_RTL8188E)))\r
 524                                 txEdcca1 = txEdcca1 + 1;\r
 525                         else if (value32 & BIT29)\r
 526                                 txEdcca1 = txEdcca1 + 1;\r
 527                         else\r
 528                                 txEdcca0 = txEdcca0 + 1;\r
 529                 }\r
 530 \r
 531                 if (txEdcca1 > 1) {\r
 532                         IGI = IGI - 1;\r
 533                         TH_L2H_dmc = TH_L2H_dmc + 1;\r
 534                         if (TH_L2H_dmc > 10)\r
 535                                 TH_L2H_dmc = 10;\r
 536                         TH_H2L_dmc = TH_L2H_dmc - pDM_Odm->TH_EDCCA_HL_diff;\r
 537 \r
 538                         Phydm_SetEDCCAThreshold(pDM_Odm, TH_H2L_dmc, TH_L2H_dmc);\r
 539                         if (TH_L2H_dmc == 10) {\r
 540                                 bAdjust = FALSE;\r
 541                                 Adaptivity->H2L_lb = TH_H2L_dmc;\r
 542                                 Adaptivity->L2H_lb = TH_L2H_dmc;\r
 543                                 pDM_Odm->Adaptivity_IGI_upper = IGI;\r
 544                         }\r
 545 \r
 546                         txEdcca1 = 0;\r
 547                         txEdcca0 = 0;\r
 548 \r
 549                 } else {\r
 550                         bAdjust = FALSE;\r
 551                         Adaptivity->H2L_lb = TH_H2L_dmc;\r
 552                         Adaptivity->L2H_lb = TH_L2H_dmc;\r
 553                         pDM_Odm->Adaptivity_IGI_upper = IGI;\r
 554                         txEdcca1 = 0;\r
 555                         txEdcca0 = 0;\r
 556                 }\r
 557         }\r
 558 \r
 559         pDM_Odm->Adaptivity_IGI_upper = pDM_Odm->Adaptivity_IGI_upper - pDM_Odm->DCbackoff;\r
 560         Adaptivity->H2L_lb = Adaptivity->H2L_lb + pDM_Odm->DCbackoff;\r
 561         Adaptivity->L2H_lb = Adaptivity->L2H_lb + pDM_Odm->DCbackoff;\r
 562 \r
 563         if (pDM_Odm->SupportICType & (ODM_RTL8723B | ODM_RTL8188E | ODM_RTL8192E | ODM_RTL8812 | ODM_RTL8821 | ODM_RTL8881A))\r
 564                 Phydm_SetLNA(pDM_Odm, PhyDM_enable_LNA);\r
 565         else {\r
 566                 Phydm_SetTRxMux(pDM_Odm, PhyDM_TX_MODE, PhyDM_RX_MODE);\r
 567                 odm_PauseDIG(pDM_Odm, PHYDM_RESUME, PHYDM_PAUSE_LEVEL_0, NONE);\r
 568         }\r
 569         \r
 570         Phydm_SetEDCCAThreshold(pDM_Odm, 0x7f, 0x7f);                           /*resume to no link state*/\r
 571 }\r
 572 \r
 573 BOOLEAN\r
 574 phydm_reSearchCondition(\r
 575         IN      PVOID                           pDM_VOID\r
 576 )\r
 577 {\r
 578         PDM_ODM_T               pDM_Odm = (PDM_ODM_T)pDM_VOID;\r
 579         /*PADAPTIVITY_STATISTICS        Adaptivity = (PADAPTIVITY_STATISTICS)PhyDM_Get_Structure(pDM_Odm, PHYDM_ADAPTIVITY);*/\r
 580         u1Byte                  Adaptivity_IGI_upper;\r
 581         /*s1Byte                TH_L2H_dmc, IGI_target = 0x32;*/\r
 582         /*s1Byte                Diff;*/\r
 583 \r
 584         Adaptivity_IGI_upper = pDM_Odm->Adaptivity_IGI_upper + pDM_Odm->DCbackoff;\r
 585         \r
 586         /*TH_L2H_dmc = 10;*/\r
 587 \r
 588         /*Diff = TH_L2H_dmc - pDM_Odm->TH_L2H_ini;*/\r
 589         /*lowest_IGI_upper = IGI_target - Diff;*/\r
 590 \r
 591         /*if ((Adaptivity_IGI_upper - lowest_IGI_upper) <= 5)*/\r
 592         if (Adaptivity_IGI_upper <= 0x26)\r
 593                 return TRUE;\r
 594         else\r
 595                 return FALSE;\r
 596         \r
 597 }\r
 598 \r
 599 VOID\r
 600 phydm_adaptivityInfoInit(\r
 601         IN      PVOID                           pDM_VOID,\r
 602         IN      PHYDM_ADAPINFO_E        CmnInfo,\r
 603         IN      u4Byte                          Value   \r
 604         )\r
 605 {\r
 606         PDM_ODM_T               pDM_Odm = (PDM_ODM_T)pDM_VOID;\r
 607         PADAPTIVITY_STATISTICS  Adaptivity = (PADAPTIVITY_STATISTICS)PhyDM_Get_Structure(pDM_Odm, PHYDM_ADAPTIVITY);\r
 608 \r
 609         switch (CmnInfo)        {\r
 610         case PHYDM_ADAPINFO_CARRIER_SENSE_ENABLE:\r
 611                 pDM_Odm->Carrier_Sense_enable = (BOOLEAN)Value;\r
 612         break;\r
 613 \r
 614         case PHYDM_ADAPINFO_DCBACKOFF:\r
 615                 pDM_Odm->DCbackoff = (u1Byte)Value;\r
 616         break;\r
 617 \r
 618         case PHYDM_ADAPINFO_DYNAMICLINKADAPTIVITY:\r
 619                 Adaptivity->DynamicLinkAdaptivity = (BOOLEAN)Value;\r
 620         break;\r
 621 \r
 622         case PHYDM_ADAPINFO_TH_L2H_INI:\r
 623                 pDM_Odm->TH_L2H_ini = (s1Byte)Value;\r
 624         break;\r
 625 \r
 626         case PHYDM_ADAPINFO_TH_EDCCA_HL_DIFF:\r
 627                 pDM_Odm->TH_EDCCA_HL_diff = (s1Byte)Value;\r
 628         break;\r
 629 \r
 630         case PHYDM_ADAPINFO_AP_NUM_TH:\r
 631                 Adaptivity->APNumTH = (u1Byte)Value;\r
 632         break;\r
 633 \r
 634         default:\r
 635         break;  \r
 636                 \r
 637         }\r
 638 \r
 639 }\r
 640 \r
 641 \r
 642 \r
 643 VOID\r
 644 Phydm_AdaptivityInit(\r
 645         IN      PVOID           pDM_VOID\r
 646 )\r
 647 {\r
 648         PDM_ODM_T               pDM_Odm = (PDM_ODM_T)pDM_VOID;\r
 649         PADAPTIVITY_STATISTICS  Adaptivity = (PADAPTIVITY_STATISTICS)PhyDM_Get_Structure(pDM_Odm, PHYDM_ADAPTIVITY);\r
 650         s1Byte  IGItarget = 0x32;\r
 651         /*pDIG_T pDM_DigTable = &pDM_Odm->DM_DigTable;*/\r
 652 \r
 653 #if(DM_ODM_SUPPORT_TYPE & (ODM_CE|ODM_WIN))\r
 654 \r
 655         if (pDM_Odm->Carrier_Sense_enable == FALSE) {\r
 656                 if (pDM_Odm->TH_L2H_ini == 0)\r
 657                         pDM_Odm->TH_L2H_ini = 0xf5;\r
 658         } else\r
 659                         pDM_Odm->TH_L2H_ini = 0xa;\r
 660 \r
 661         if (pDM_Odm->TH_EDCCA_HL_diff == 0)\r
 662                 pDM_Odm->TH_EDCCA_HL_diff = 7;\r
 663 #if(DM_ODM_SUPPORT_TYPE & (ODM_CE))\r
 664         if (pDM_Odm->WIFITest == TRUE || pDM_Odm->mp_mode == TRUE)\r
 665 #else\r
 666         if ((pDM_Odm->WIFITest & RT_WIFI_LOGO) == TRUE)\r
 667 #endif\r
 668                 pDM_Odm->EDCCA_enable = FALSE;          /*even no adaptivity, we still enable EDCCA, AP side use mib control*/\r
 669         else\r
 670                 pDM_Odm->EDCCA_enable = TRUE;\r
 671 \r
 672 #elif (DM_ODM_SUPPORT_TYPE & ODM_AP)\r
 673         prtl8192cd_priv priv = pDM_Odm->priv;\r
 674 \r
 675         if (pDM_Odm->Carrier_Sense_enable) {\r
 676                 pDM_Odm->TH_L2H_ini = 0xa;\r
 677                 pDM_Odm->TH_EDCCA_HL_diff = 7;\r
 678         } else {\r
 679                 pDM_Odm->TH_L2H_ini = pDM_Odm->TH_L2H_default;  /*set by mib*/\r
 680                 pDM_Odm->TH_EDCCA_HL_diff = pDM_Odm->TH_EDCCA_HL_diff_default;\r
 681         }\r
 682 \r
 683         if (priv->pshare->rf_ft_var.adaptivity_enable == 3)\r
 684                 Adaptivity->AcsForAdaptivity = TRUE;\r
 685         else \r
 686                 Adaptivity->AcsForAdaptivity = FALSE;\r
 687 \r
 688         if (priv->pshare->rf_ft_var.adaptivity_enable == 2)\r
 689                 Adaptivity->DynamicLinkAdaptivity = TRUE;\r
 690         else\r
 691                 Adaptivity->DynamicLinkAdaptivity = FALSE;\r
 692 \r
 693         priv->pshare->rf_ft_var.isCleanEnvironment = FALSE;\r
 694 \r
 695 #endif\r
 696 \r
 697         pDM_Odm->Adaptivity_IGI_upper = 0;\r
 698         pDM_Odm->Adaptivity_enable = FALSE;     /*use this flag to decide enable or disable*/\r
 699 \r
 700         pDM_Odm->TH_L2H_ini_mode2 = 20;\r
 701         pDM_Odm->TH_EDCCA_HL_diff_mode2 = 8;\r
 702         Adaptivity->TH_L2H_ini_backup = pDM_Odm->TH_L2H_ini;\r
 703         Adaptivity->TH_EDCCA_HL_diff_backup = pDM_Odm->TH_EDCCA_HL_diff;\r
 704         \r
 705         Adaptivity->IGI_Base = 0x32;\r
 706         Adaptivity->IGI_target = 0x1c;\r
 707         Adaptivity->H2L_lb = 0;\r
 708         Adaptivity->L2H_lb = 0;\r
 709         Adaptivity->NHMWait = 0;\r
 710         Adaptivity->bCheck = FALSE;\r
 711         Adaptivity->bFirstLink = TRUE;\r
 712         Adaptivity->AdajustIGILevel = 0;\r
 713         Adaptivity->bStopEDCCA = FALSE;\r
 714         Adaptivity->backupH2L = 0;\r
 715         Adaptivity->backupL2H = 0;\r
 716 \r
 717         Phydm_MACEDCCAState(pDM_Odm, PhyDM_DONT_IGNORE_EDCCA);\r
 718 \r
 719         /*Search pwdB lower bound*/\r
 720         if (pDM_Odm->SupportICType & ODM_IC_11N_SERIES)\r
 721                 ODM_SetBBReg(pDM_Odm, ODM_REG_DBG_RPT_11N, bMaskDWord, 0x208);\r
 722 #if (RTL8195A_SUPPORT == 0)\r
 723         else if (pDM_Odm->SupportICType & ODM_IC_11AC_SERIES)\r
 724                 ODM_SetBBReg(pDM_Odm, ODM_REG_DBG_RPT_11AC, bMaskDWord, 0x209);\r
 725 #endif\r
 726 \r
 727         if (pDM_Odm->SupportICType & ODM_IC_11N_GAIN_IDX_EDCCA) {\r
 728                 /*ODM_SetBBReg(pDM_Odm, ODM_REG_EDCCA_DOWN_OPT_11N, BIT12 | BIT11 | BIT10, 0x7);*/              /*interfernce need > 2^x us, and then EDCCA will be 1*/\r
 729                 if (pDM_Odm->SupportICType & ODM_RTL8197F) {\r
 730                         ODM_SetBBReg(pDM_Odm, ODM_REG_PAGE_B1_97F, BIT30, 0x1);                                                         /*set to page B1*/\r
 731                         ODM_SetBBReg(pDM_Odm, ODM_REG_EDCCA_DCNF_97F, BIT27 | BIT26, 0x1);              /*0:rx_dfir, 1: dcnf_out, 2 :rx_iq, 3: rx_nbi_nf_out*/\r
 732                         ODM_SetBBReg(pDM_Odm, ODM_REG_PAGE_B1_97F, BIT30, 0x0);\r
 733 #if (DM_ODM_SUPPORT_TYPE & ODM_AP)\r
 734                         if (priv->pshare->rf_ft_var.adaptivity_enable == 1)\r
 735                                 ODM_SetBBReg(pDM_Odm, 0xce8, BIT13, 0x1);                                               /*0: mean, 1:max pwdB*/\r
 736 #endif\r
 737                 } else\r
 738                 ODM_SetBBReg(pDM_Odm, ODM_REG_EDCCA_DCNF_11N, BIT21 | BIT20, 0x1);              /*0:rx_dfir, 1: dcnf_out, 2 :rx_iq, 3: rx_nbi_nf_out*/\r
 739         }\r
 740 #if (RTL8195A_SUPPORT == 0)\r
 741         if (pDM_Odm->SupportICType & ODM_IC_11AC_GAIN_IDX_EDCCA) {              /*8814a no need to find pwdB lower bound, maybe*/\r
 742                 /*ODM_SetBBReg(pDM_Odm, ODM_REG_EDCCA_DOWN_OPT, BIT30 | BIT29 | BIT28, 0x7);*/          /*interfernce need > 2^x us, and then EDCCA will be 1*/\r
 743                 ODM_SetBBReg(pDM_Odm, ODM_REG_ACBB_EDCCA_ENHANCE, BIT29 | BIT28, 0x1);          /*0:rx_dfir, 1: dcnf_out, 2 :rx_iq, 3: rx_nbi_nf_out*/\r
 744         }\r
 745 \r
 746         if (!(pDM_Odm->SupportICType & (ODM_IC_11AC_GAIN_IDX_EDCCA | ODM_IC_11N_GAIN_IDX_EDCCA))) {\r
 747                 Phydm_SearchPwdBLowerBound(pDM_Odm);\r
 748                 if (phydm_reSearchCondition(pDM_Odm))\r
 749                         Phydm_SearchPwdBLowerBound(pDM_Odm);\r
 750         }\r
 751 #endif\r
 752 \r
 753 /*we need to consider PwdB upper bound for 8814 later IC*/\r
 754         Adaptivity->AdajustIGILevel = (u1Byte)((pDM_Odm->TH_L2H_ini + IGItarget) - PwdBUpperBound + DFIRloss);  /*IGI = L2H - PwdB - DFIRloss*/\r
 755 \r
 756         ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("TH_L2H_ini = 0x%x, TH_EDCCA_HL_diff = 0x%x, Adaptivity->AdajustIGILevel = 0x%x\n", pDM_Odm->TH_L2H_ini, pDM_Odm->TH_EDCCA_HL_diff, Adaptivity->AdajustIGILevel));\r
 757 \r
 758         /*Check this later on Windows*/\r
 759         /*phydm_setEDCCAThresholdAPI(pDM_Odm, pDM_DigTable->CurIGValue);*/\r
 760 \r
 761 }\r
 762 \r
 763 \r
 764 VOID\r
 765 Phydm_Adaptivity(\r
 766         IN              PVOID                   pDM_VOID,\r
 767         IN              u1Byte                  IGI\r
 768 )\r
 769 {\r
 770         PDM_ODM_T               pDM_Odm = (PDM_ODM_T)pDM_VOID;\r
 771         s1Byte                  TH_L2H_dmc, TH_H2L_dmc;\r
 772         s1Byte                  Diff = 0, IGI_target;\r
 773         PADAPTIVITY_STATISTICS  Adaptivity = (PADAPTIVITY_STATISTICS)PhyDM_Get_Structure(pDM_Odm, PHYDM_ADAPTIVITY);\r
 774 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)\r
 775         PADAPTER                pAdapter        = pDM_Odm->Adapter;\r
 776         BOOLEAN                 bFwCurrentInPSMode = FALSE;\r
 777 \r
 778         pAdapter->HalFunc.GetHwRegHandler(pAdapter, HW_VAR_FW_PSMODE_STATUS, (pu1Byte)(&bFwCurrentInPSMode));\r
 779 \r
 780         /*Disable EDCCA mode while under LPS mode, added by Roger, 2012.09.14.*/\r
 781         if (bFwCurrentInPSMode)\r
 782                 return;\r
 783 #endif\r
 784 \r
 785         if ((pDM_Odm->EDCCA_enable == FALSE) || (Adaptivity->bStopEDCCA == TRUE)) {\r
 786                 ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("Disable EDCCA!!!\n"));\r
 787                 return;\r
 788         }\r
 789 \r
 790         if (!(pDM_Odm->SupportAbility & ODM_BB_ADAPTIVITY)) {\r
 791                 ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("adaptivity disable, enable EDCCA mode!!!\n"));\r
 792                 pDM_Odm->TH_L2H_ini = pDM_Odm->TH_L2H_ini_mode2;\r
 793                 pDM_Odm->TH_EDCCA_HL_diff = pDM_Odm->TH_EDCCA_HL_diff_mode2;\r
 794         }\r
 795 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)\r
 796         else{\r
 797                 if (Phydm_CheckChannelPlan(pDM_Odm) || (pDM_Odm->APTotalNum > Adaptivity->APNumTH)) {\r
 798                         pDM_Odm->TH_L2H_ini = pDM_Odm->TH_L2H_ini_mode2;\r
 799                         pDM_Odm->TH_EDCCA_HL_diff = pDM_Odm->TH_EDCCA_HL_diff_mode2;\r
 800                 } else {\r
 801                         pDM_Odm->TH_L2H_ini = Adaptivity->TH_L2H_ini_backup;\r
 802                         pDM_Odm->TH_EDCCA_HL_diff = Adaptivity->TH_EDCCA_HL_diff_backup;\r
 803                 }\r
 804         }\r
 805 #endif\r
 806 \r
 807         ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("odm_Adaptivity() =====>\n"));\r
 808         ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("IGI_Base=0x%x, TH_L2H_ini = %d, TH_EDCCA_HL_diff = %d\n",\r
 809                          Adaptivity->IGI_Base, pDM_Odm->TH_L2H_ini, pDM_Odm->TH_EDCCA_HL_diff));\r
 810 #if (RTL8195A_SUPPORT == 0)\r
 811         if (pDM_Odm->SupportICType & ODM_IC_11AC_SERIES) {\r
 812                 /*fix AC series when enable EDCCA hang issue*/\r
 813                 ODM_SetBBReg(pDM_Odm, 0x800, BIT10, 1); /*ADC_mask disable*/\r
 814                 ODM_SetBBReg(pDM_Odm, 0x800, BIT10, 0); /*ADC_mask enable*/\r
 815         }\r
 816 #endif\r
 817         if (*pDM_Odm->pBandWidth == ODM_BW20M)          /*CHANNEL_WIDTH_20*/\r
 818                 IGI_target = Adaptivity->IGI_Base;\r
 819         else if (*pDM_Odm->pBandWidth == ODM_BW40M)\r
 820                 IGI_target = Adaptivity->IGI_Base + 2;\r
 821 #if (RTL8195A_SUPPORT == 0)\r
 822         else if (*pDM_Odm->pBandWidth == ODM_BW80M)\r
 823                 IGI_target = Adaptivity->IGI_Base + 2;\r
 824 #endif\r
 825         else\r
 826                 IGI_target = Adaptivity->IGI_Base;\r
 827         Adaptivity->IGI_target = (u1Byte) IGI_target;\r
 828 \r
 829         ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("BandWidth=%s, IGI_target=0x%x, DynamicLinkAdaptivity = %d, AcsForAdaptivity = %d\n",\r
 830                          (*pDM_Odm->pBandWidth == ODM_BW80M) ? "80M" : ((*pDM_Odm->pBandWidth == ODM_BW40M) ? "40M" : "20M"), IGI_target, Adaptivity->DynamicLinkAdaptivity, Adaptivity->AcsForAdaptivity));\r
 831         ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("RSSI_min = %d, Adaptivity->AdajustIGILevel= 0x%x, adaptivity_flag = %d, Adaptivity_enable = %d\n",\r
 832                          pDM_Odm->RSSI_Min, Adaptivity->AdajustIGILevel, pDM_Odm->adaptivity_flag, pDM_Odm->Adaptivity_enable));\r
 833 \r
 834         if ((Adaptivity->DynamicLinkAdaptivity == TRUE) && (!pDM_Odm->bLinked) && (pDM_Odm->Adaptivity_enable == FALSE)) {\r
 835                 Phydm_SetEDCCAThreshold(pDM_Odm, 0x7f, 0x7f);\r
 836                 ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("In DynamicLink mode(noisy) and No link, Turn off EDCCA!!\n"));\r
 837                 return;\r
 838         }\r
 839 \r
 840         if (pDM_Odm->SupportICType & (ODM_IC_11AC_GAIN_IDX_EDCCA | ODM_IC_11N_GAIN_IDX_EDCCA)) {\r
 841                 if ((Adaptivity->AdajustIGILevel > IGI) && (pDM_Odm->Adaptivity_enable == TRUE)) \r
 842                         Diff = Adaptivity->AdajustIGILevel - IGI;\r
 843                 \r
 844                 TH_L2H_dmc = pDM_Odm->TH_L2H_ini - Diff + IGI_target;\r
 845                 TH_H2L_dmc = TH_L2H_dmc - pDM_Odm->TH_EDCCA_HL_diff;\r
 846         }\r
 847 #if (RTL8195A_SUPPORT == 0)\r
 848         else    {\r
 849                 Diff = IGI_target - (s1Byte)IGI;\r
 850                 TH_L2H_dmc = pDM_Odm->TH_L2H_ini + Diff;\r
 851                 if (TH_L2H_dmc > 10 && (pDM_Odm->Adaptivity_enable == TRUE))\r
 852                         TH_L2H_dmc = 10;\r
 853 \r
 854                 TH_H2L_dmc = TH_L2H_dmc - pDM_Odm->TH_EDCCA_HL_diff;\r
 855 \r
 856                 /*replace lower bound to prevent EDCCA always equal 1*/\r
 857                 if (TH_H2L_dmc < Adaptivity->H2L_lb)\r
 858                         TH_H2L_dmc = Adaptivity->H2L_lb;\r
 859                 if (TH_L2H_dmc < Adaptivity->L2H_lb)\r
 860                         TH_L2H_dmc = Adaptivity->L2H_lb;\r
 861         }\r
 862 #endif\r
 863         ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("IGI=0x%x, TH_L2H_dmc = %d, TH_H2L_dmc = %d\n", IGI, TH_L2H_dmc, TH_H2L_dmc));\r
 864         ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("Adaptivity_IGI_upper=0x%x, H2L_lb = 0x%x, L2H_lb = 0x%x\n", pDM_Odm->Adaptivity_IGI_upper, Adaptivity->H2L_lb, Adaptivity->L2H_lb));\r
 865 \r
 866         Phydm_SetEDCCAThreshold(pDM_Odm, TH_H2L_dmc, TH_L2H_dmc);\r
 867         \r
 868         if (pDM_Odm->Adaptivity_enable == TRUE)\r
 869                 ODM_SetMACReg(pDM_Odm, REG_RD_CTRL, BIT11, 1);\r
 870         \r
 871         return;\r
 872 }\r
 873 \r
 874 \r
 875 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)\r
 876 \r
 877 VOID\r
 878 Phydm_AdaptivityBSOD(\r
 879         IN              PVOID           pDM_VOID\r
 880 )\r
 881 {\r
 882         PDM_ODM_T               pDM_Odm = (PDM_ODM_T)pDM_VOID;\r
 883         PADAPTER                pAdapter = pDM_Odm->Adapter;\r
 884         PMGNT_INFO              pMgntInfo = &(pAdapter->MgntInfo);\r
 885         u1Byte                  count = 0;\r
 886         u4Byte                  u4Value;\r
 887 \r
 888         /*\r
 889         1. turn off RF (TRX Mux in standby mode)\r
 890         2. H2C mac id drop\r
 891         3. ignore EDCCA\r
 892         4. wait for clear FIFO\r
 893         5. don't ignore EDCCA\r
 894         6. turn on RF (TRX Mux in TRx mdoe)\r
 895         7. H2C mac id resume\r
 896         */\r
 897 \r
 898         RT_TRACE(COMP_MLME, DBG_WARNING, ("MAC id drop packet!!!!!\n"));\r
 899 \r
 900         pAdapter->dropPktByMacIdCnt++;\r
 901         pMgntInfo->bDropPktInProgress = TRUE;\r
 902 \r
 903         pAdapter->HalFunc.GetHwRegHandler(pAdapter, HW_VAR_MAX_Q_PAGE_NUM, (pu1Byte)(&u4Value));\r
 904         RT_TRACE(COMP_INIT, DBG_LOUD, ("Queue Reserved Page Number = 0x%08x\n", u4Value));\r
 905         pAdapter->HalFunc.GetHwRegHandler(pAdapter, HW_VAR_AVBL_Q_PAGE_NUM, (pu1Byte)(&u4Value));\r
 906         RT_TRACE(COMP_INIT, DBG_LOUD, ("Available Queue Page Number = 0x%08x\n", u4Value));\r
 907 \r
 908         /*Standby mode*/\r
 909         Phydm_SetTRxMux(pDM_Odm, PhyDM_STANDBY_MODE, PhyDM_STANDBY_MODE);\r
 910         ODM_Write_DIG(pDM_Odm, 0x20);\r
 911 \r
 912         /*H2C mac id drop*/\r
 913         MacIdIndicateDisconnect(pAdapter);\r
 914 \r
 915         /*Ignore EDCCA*/\r
 916         Phydm_MACEDCCAState(pDM_Odm, PhyDM_IGNORE_EDCCA);\r
 917 \r
 918         delay_ms(50);\r
 919         count = 5;\r
 920 \r
 921         /*Resume EDCCA*/\r
 922         Phydm_MACEDCCAState(pDM_Odm, PhyDM_DONT_IGNORE_EDCCA);\r
 923 \r
 924         /*Turn on TRx mode*/\r
 925         Phydm_SetTRxMux(pDM_Odm, PhyDM_TX_MODE, PhyDM_RX_MODE);\r
 926         ODM_Write_DIG(pDM_Odm, 0x20);\r
 927 \r
 928         /*Resume H2C macid*/\r
 929         MacIdRecoverMediaStatus(pAdapter);\r
 930 \r
 931         pAdapter->HalFunc.GetHwRegHandler(pAdapter, HW_VAR_AVBL_Q_PAGE_NUM, (pu1Byte)(&u4Value));\r
 932         RT_TRACE(COMP_INIT, DBG_LOUD, ("Available Queue Page Number = 0x%08x\n", u4Value));\r
 933 \r
 934         pMgntInfo->bDropPktInProgress = FALSE;\r
 935         RT_TRACE(COMP_MLME, DBG_WARNING, ("End of MAC id drop packet, spent %dms\n", count * 10));\r
 936 \r
 937 }\r
 938 \r
 939 #endif\r
 940 \r
 941 /*This API is for solving USB can't Tx problem due to USB3.0 interference in 2.4G*/\r
 942 VOID\r
 943 phydm_pauseEDCCA(\r
 944         IN      PVOID   pDM_VOID,\r
 945         IN      BOOLEAN bPasueEDCCA\r
 946 )\r
 947 {\r
 948         PDM_ODM_T       pDM_Odm = (PDM_ODM_T)pDM_VOID;\r
 949         PADAPTIVITY_STATISTICS  Adaptivity = (PADAPTIVITY_STATISTICS)PhyDM_Get_Structure(pDM_Odm, PHYDM_ADAPTIVITY);\r
 950         pDIG_T  pDM_DigTable = &pDM_Odm->DM_DigTable;\r
 951         u1Byte  IGI = pDM_DigTable->CurIGValue;\r
 952         s1Byte  Diff = 0;\r
 953 \r
 954         if (bPasueEDCCA) {\r
 955                 Adaptivity->bStopEDCCA = TRUE;\r
 956 \r
 957                 if (pDM_Odm->SupportICType & (ODM_IC_11AC_GAIN_IDX_EDCCA | ODM_IC_11N_GAIN_IDX_EDCCA)) {\r
 958                                 if (Adaptivity->AdajustIGILevel > IGI)\r
 959                                         Diff = Adaptivity->AdajustIGILevel - IGI;\r
 960                                 \r
 961                                 Adaptivity->backupL2H = pDM_Odm->TH_L2H_ini - Diff + Adaptivity->IGI_target;\r
 962                                 Adaptivity->backupH2L = Adaptivity->backupL2H - pDM_Odm->TH_EDCCA_HL_diff;\r
 963                         }\r
 964 #if (RTL8195A_SUPPORT == 0)\r
 965                         else {\r
 966                                 Diff = Adaptivity->IGI_target - (s1Byte)IGI;\r
 967                                 Adaptivity->backupL2H = pDM_Odm->TH_L2H_ini + Diff;\r
 968                                 if (Adaptivity->backupL2H > 10)\r
 969                                         Adaptivity->backupL2H = 10;\r
 970 \r
 971                                 Adaptivity->backupH2L = Adaptivity->backupL2H - pDM_Odm->TH_EDCCA_HL_diff;\r
 972 \r
 973                                 /*replace lower bound to prevent EDCCA always equal 1*/\r
 974                                 if (Adaptivity->backupH2L < Adaptivity->H2L_lb)\r
 975                                         Adaptivity->backupH2L = Adaptivity->H2L_lb;\r
 976                                 if (Adaptivity->backupL2H < Adaptivity->L2H_lb)\r
 977                                         Adaptivity->backupL2H = Adaptivity->L2H_lb;\r
 978                         }\r
 979 #endif\r
 980                 ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("pauseEDCCA : L2Hbak = 0x%x, H2Lbak = 0x%x, IGI = 0x%x\n", Adaptivity->backupL2H, Adaptivity->backupH2L, IGI));\r
 981 \r
 982                 /*Disable EDCCA*/\r
 983 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)\r
 984                 if (PlatformIsWorkItemScheduled(&(Adaptivity->phydm_pauseEDCCAWorkItem)) == FALSE)\r
 985                         PlatformScheduleWorkItem(&(Adaptivity->phydm_pauseEDCCAWorkItem));\r
 986 #else\r
 987                 phydm_pauseEDCCA_WorkItemCallback(pDM_Odm);\r
 988 #endif\r
 989         \r
 990         } else {\r
 991 \r
 992                 Adaptivity->bStopEDCCA = FALSE;\r
 993                 ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("resumeEDCCA : L2Hbak = 0x%x, H2Lbak = 0x%x, IGI = 0x%x\n", Adaptivity->backupL2H, Adaptivity->backupH2L, IGI));\r
 994                 /*Resume EDCCA*/\r
 995 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)\r
 996                 if (PlatformIsWorkItemScheduled(&(Adaptivity->phydm_resumeEDCCAWorkItem)) == FALSE)\r
 997                         PlatformScheduleWorkItem(&(Adaptivity->phydm_resumeEDCCAWorkItem));\r
 998 #else\r
 999                 phydm_resumeEDCCA_WorkItemCallback(pDM_Odm);\r
1000 #endif\r
1001 \r
1002         }\r
1003 \r
1004 }\r
1005 \r
1006 \r
1007 VOID\r
1008 phydm_pauseEDCCA_WorkItemCallback(\r
1009 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)\r
1010         IN      PADAPTER                Adapter\r
1011 #else\r
1012         IN PVOID                        pDM_VOID\r
1013 #endif\r
1014 )\r
1015 {\r
1016 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)\r
1017         PHAL_DATA_TYPE  pHalData = GET_HAL_DATA(Adapter);\r
1018         PDM_ODM_T               pDM_Odm = &pHalData->DM_OutSrc;\r
1019 #else\r
1020         PDM_ODM_T       pDM_Odm = (PDM_ODM_T)pDM_VOID;\r
1021 #endif\r
1022 \r
1023         if (pDM_Odm->SupportICType & ODM_IC_11N_SERIES)\r
1024                 ODM_SetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, bMaskByte2|bMaskByte0, (u4Byte)(0x7f|0x7f<<16));\r
1025 #if (RTL8195A_SUPPORT == 0)\r
1026         else if (pDM_Odm->SupportICType & ODM_IC_11AC_SERIES)\r
1027                 ODM_SetBBReg(pDM_Odm, rFPGA0_XB_LSSIReadBack, bMaskLWord, (u2Byte)(0x7f|0x7f<<8));\r
1028 #endif\r
1029 \r
1030 }\r
1031 \r
1032 VOID\r
1033 phydm_resumeEDCCA_WorkItemCallback(\r
1034 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)\r
1035         IN      PADAPTER                Adapter\r
1036 #else\r
1037         IN PVOID                        pDM_VOID\r
1038 #endif\r
1039 )\r
1040 {\r
1041 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)\r
1042         PHAL_DATA_TYPE  pHalData = GET_HAL_DATA(Adapter);\r
1043         PDM_ODM_T               pDM_Odm = &pHalData->DM_OutSrc;\r
1044 #else\r
1045         PDM_ODM_T       pDM_Odm = (PDM_ODM_T)pDM_VOID;\r
1046 #endif\r
1047         PADAPTIVITY_STATISTICS  Adaptivity = (PADAPTIVITY_STATISTICS)PhyDM_Get_Structure(pDM_Odm, PHYDM_ADAPTIVITY);\r
1048         \r
1049         if (pDM_Odm->SupportICType & ODM_IC_11N_SERIES)\r
1050                 ODM_SetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, bMaskByte2|bMaskByte0, (u4Byte)((u1Byte)Adaptivity->backupL2H|(u1Byte)Adaptivity->backupH2L<<16));\r
1051 #if (RTL8195A_SUPPORT == 0)\r
1052         else if (pDM_Odm->SupportICType & ODM_IC_11AC_SERIES)\r
1053                 ODM_SetBBReg(pDM_Odm, rFPGA0_XB_LSSIReadBack, bMaskLWord, (u2Byte)((u1Byte)Adaptivity->backupL2H|(u1Byte)Adaptivity->backupH2L<<8));\r
1054 #endif\r
1055 \r
1056 }\r
1057 \r
1058 \r
1059 VOID\r
1060 phydm_setEDCCAThresholdAPI(\r
1061         IN      PVOID   pDM_VOID,\r
1062         IN      u1Byte  IGI\r
1063 )\r
1064 {\r
1065         PDM_ODM_T       pDM_Odm = (PDM_ODM_T)pDM_VOID;\r
1066         PADAPTIVITY_STATISTICS  Adaptivity = (PADAPTIVITY_STATISTICS)PhyDM_Get_Structure(pDM_Odm, PHYDM_ADAPTIVITY);\r
1067         s1Byte                  TH_L2H_dmc, TH_H2L_dmc;\r
1068         s1Byte                  Diff = 0, IGI_target = 0x32;\r
1069 \r
1070         if (pDM_Odm->SupportAbility & ODM_BB_ADAPTIVITY) {\r
1071                 if (pDM_Odm->SupportICType & (ODM_IC_11AC_GAIN_IDX_EDCCA | ODM_IC_11N_GAIN_IDX_EDCCA)) {\r
1072                         if (Adaptivity->AdajustIGILevel > IGI) \r
1073                                 Diff = Adaptivity->AdajustIGILevel - IGI;\r
1074                         \r
1075                         TH_L2H_dmc = pDM_Odm->TH_L2H_ini - Diff + IGI_target;\r
1076                         TH_H2L_dmc = TH_L2H_dmc - pDM_Odm->TH_EDCCA_HL_diff;\r
1077                 }\r
1078 #if (RTL8195A_SUPPORT == 0)\r
1079                 else    {\r
1080                         Diff = IGI_target - (s1Byte)IGI;\r
1081                         TH_L2H_dmc = pDM_Odm->TH_L2H_ini + Diff;\r
1082                         if (TH_L2H_dmc > 10)\r
1083                                 TH_L2H_dmc = 10;\r
1084 \r
1085                         TH_H2L_dmc = TH_L2H_dmc - pDM_Odm->TH_EDCCA_HL_diff;\r
1086 \r
1087                         /*replace lower bound to prevent EDCCA always equal 1*/\r
1088                         if (TH_H2L_dmc < Adaptivity->H2L_lb)\r
1089                                 TH_H2L_dmc = Adaptivity->H2L_lb;\r
1090                         if (TH_L2H_dmc < Adaptivity->L2H_lb)\r
1091                                 TH_L2H_dmc = Adaptivity->L2H_lb;\r
1092                 }\r
1093 #endif\r
1094                 ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("API :IGI=0x%x, TH_L2H_dmc = %d, TH_H2L_dmc = %d\n", IGI, TH_L2H_dmc, TH_H2L_dmc));\r
1095                 ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("API :Adaptivity_IGI_upper=0x%x, H2L_lb = 0x%x, L2H_lb = 0x%x\n", pDM_Odm->Adaptivity_IGI_upper, Adaptivity->H2L_lb, Adaptivity->L2H_lb));\r
1096 \r
1097                 Phydm_SetEDCCAThreshold(pDM_Odm, TH_H2L_dmc, TH_L2H_dmc);\r
1098         }\r
1099 \r
1100 }\r
1101 \r