1 /******************************************************************************
3 * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
19 ******************************************************************************/
21 #include "Mp_Precomp.h"
22 #include "../phydm_precomp.h"
24 #if (RTL8723D_SUPPORT == 1)
27 odm_ConfigRFReg_8723D(
31 IN ODM_RF_RADIO_PATH_E RF_PATH,
35 if(Addr == 0xfe || Addr == 0xffe)
37 #ifdef CONFIG_LONG_DELAY_ISSUE
45 ODM_SetRFReg(pDM_Odm, RF_PATH, RegAddr, bRFRegOffsetMask, Data);
46 // Add 1us delay between BB/RF register setting.
53 odm_ConfigRF_RadioA_8723D(
59 u4Byte content = 0x1000; // RF_Content: radioa_txt
60 u4Byte maskforPhySet= (u4Byte)(content&0xE000);
62 odm_ConfigRFReg_8723D(pDM_Odm, Addr, Data, ODM_RF_PATH_A, Addr|maskforPhySet);
64 ODM_RT_TRACE(pDM_Odm,ODM_COMP_INIT, ODM_DBG_TRACE, ("===> ODM_ConfigRFWithHeaderFile: [RadioA] %08X %08X\n", Addr, Data));
68 odm_ConfigRF_RadioB_8723D(
74 u4Byte content = 0x1001; // RF_Content: radiob_txt
75 u4Byte maskforPhySet= (u4Byte)(content&0xE000);
77 odm_ConfigRFReg_8723D(pDM_Odm, Addr, Data, ODM_RF_PATH_B, Addr|maskforPhySet);
79 ODM_RT_TRACE(pDM_Odm,ODM_COMP_INIT, ODM_DBG_TRACE, ("===> ODM_ConfigRFWithHeaderFile: [RadioB] %08X %08X\n", Addr, Data));
90 ODM_Write1Byte(pDM_Odm, Addr, Data);
91 ODM_RT_TRACE(pDM_Odm,ODM_COMP_INIT, ODM_DBG_TRACE, ("===> ODM_ConfigMACWithHeaderFile: [MAC_REG] %08X %08X\n", Addr, Data));
95 odm_ConfigBB_AGC_8723D(
102 ODM_SetBBReg(pDM_Odm, Addr, Bitmask, Data);
103 // Add 1us delay between BB/RF register setting.
106 ODM_RT_TRACE(pDM_Odm,ODM_COMP_INIT, ODM_DBG_TRACE, ("===> ODM_ConfigBBWithHeaderFile: [AGC_TAB] %08X %08X\n", Addr, Data));
110 odm_ConfigBB_PHY_REG_PG_8723D(
111 IN PDM_ODM_T pDM_Odm,
120 if (Addr == 0xfe || Addr == 0xffe)
121 #ifdef CONFIG_LONG_DELAY_ISSUE
128 #if !(DM_ODM_SUPPORT_TYPE&ODM_AP)
129 PHY_StoreTxPowerByRate(pDM_Odm->Adapter, Band, RfPath, TxNum, Addr, Bitmask, Data);
132 ODM_RT_TRACE(pDM_Odm,ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ConfigBBWithHeaderFile: [PHY_REG] %08X %08X %08X\n", Addr, Bitmask, Data));
136 odm_ConfigBB_PHY_8723D(
137 IN PDM_ODM_T pDM_Odm,
143 /*DbgPrint("odm_ConfigBB_PHY_8723D(), Addr = 0x%x, data = 0x%x\n", Addr, Data);*/
145 #ifdef CONFIG_LONG_DELAY_ISSUE
150 else if (Addr == 0xfd)
152 else if (Addr == 0xfc)
154 else if (Addr == 0xfb)
156 else if (Addr == 0xfa)
158 else if (Addr == 0xf9)
162 ODM_SetBBReg(pDM_Odm, Addr, Bitmask, Data);
165 // Add 1us delay between BB/RF register setting.
167 ODM_RT_TRACE(pDM_Odm,ODM_COMP_INIT, ODM_DBG_TRACE, ("===> ODM_ConfigBBWithHeaderFile: [PHY_REG] %08X %08X\n", Addr, Data));
171 odm_ConfigBB_TXPWR_LMT_8723D(
172 IN PDM_ODM_T pDM_Odm,
173 IN pu1Byte Regulation,
175 IN pu1Byte Bandwidth,
176 IN pu1Byte RateSection,
179 IN pu1Byte PowerLimit
182 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE))
183 PHY_SetTxPowerLimit(pDM_Odm, Regulation, Band,
184 Bandwidth, RateSection, RfPath, Channel, PowerLimit);