drivers/net/wireless/rockchip_wlan/rtl8723ds/hal/phydm/txbf/haltxbf8192e.c

   1 //============================================================\r
   2 // Description:\r
   3 //\r
   4 // This file is for 8192E TXBF mechanism\r
   5 //\r
   6 //============================================================\r
   7 #include "mp_precomp.h"\r
   8 #include "../phydm_precomp.h"\r
   9 \r
  10 #if (BEAMFORMING_SUPPORT == 1)\r
  11 #if (RTL8192E_SUPPORT == 1)\r
  12 \r
  13 VOID\r
  14 HalTxbf8192E_setNDPArate(\r
  15         IN PVOID                        pDM_VOID,\r
  16         IN u1Byte       BW,\r
  17         IN u1Byte       Rate\r
  18 )\r
  19 {\r
  20         PDM_ODM_T       pDM_Odm = (PDM_ODM_T)pDM_VOID;\r
  21         \r
  22         ODM_Write1Byte(pDM_Odm, REG_NDPA_OPT_CTRL_8192E,  (Rate << 2 | BW));    \r
  23 \r
  24 }\r
  25 \r
  26 VOID\r
  27 halTxbf8192E_RfMode(\r
  28         IN PVOID                        pDM_VOID,\r
  29         IN PRT_BEAMFORMING_INFO pBeamInfo\r
  30 )\r
  31 {\r
  32         PDM_ODM_T       pDM_Odm = (PDM_ODM_T)pDM_VOID;\r
  33         BOOLEAN                         bSelfBeamformer = FALSE;\r
  34         BOOLEAN                         bSelfBeamformee = FALSE;\r
  35         BEAMFORMING_CAP BeamformCap = BEAMFORMING_CAP_NONE;\r
  36 \r
  37         ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Start!\n", __func__));\r
  38 \r
  39         if (pDM_Odm->RFType == ODM_1T1R)\r
  40                 return;\r
  41 \r
  42         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_WE_LUT, 0x80000, 0x1); /*RF Mode table write enable*/\r
  43         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_WE_LUT, 0x80000, 0x1); /*RF Mode table write enable*/\r
  44         \r
  45         if (pBeamInfo->beamformee_su_cnt > 0) {\r
  46                 /*Path_A*/\r
  47                 ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_ModeTableAddr, 0xfffff, 0x18000);       /*Select RX mode  0x30=0x18000*/\r
  48                 ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_ModeTableData0, 0xfffff, 0x0000f);      /*Set Table data*/\r
  49                 ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_ModeTableData1, 0xfffff, 0x77fc2);      /*Enable TXIQGEN in RX mode*/\r
  50                 /*Path_B*/\r
  51                 ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_ModeTableAddr, 0xfffff, 0x18000);       /*Select RX mode*/\r
  52                 ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_ModeTableData0, 0xfffff, 0x0000f);      /*Set Table data*/\r
  53                 ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_ModeTableData1, 0xfffff, 0x77fc2);      /*Enable TXIQGEN in RX mode*/\r
  54         } else {\r
  55                 /*Path_A*/\r
  56                 ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_ModeTableAddr, 0xfffff, 0x18000);       /*Select RX mode*/\r
  57                 ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_ModeTableData0, 0xfffff, 0x0000f);      /*Set Table data*/\r
  58                 ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_ModeTableData1, 0xfffff, 0x77f82);      /*Disable TXIQGEN in RX mode*/\r
  59                 /*Path_B*/\r
  60                 ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_ModeTableAddr, 0xfffff, 0x18000);       /*Select RX mode*/\r
  61                 ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_ModeTableData0, 0xfffff, 0x0000f);      /*Set Table data*/\r
  62                 ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_ModeTableData1, 0xfffff, 0x77f82);      /*Disable TXIQGEN in RX mode*/\r
  63         }\r
  64 \r
  65         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_WE_LUT, 0x80000, 0x0);  /*RF Mode table write disable*/\r
  66         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_WE_LUT, 0x80000, 0x0);  /*RF Mode table write disable*/\r
  67 \r
  68         if (pBeamInfo->beamformee_su_cnt > 0) {\r
  69                 ODM_SetBBReg(pDM_Odm, rFPGA1_TxInfo, bMaskDWord, 0x83321333);\r
  70                 ODM_SetBBReg(pDM_Odm, rCCK0_AFESetting, bMaskByte3, 0xc1);\r
  71         } else\r
  72                 ODM_SetBBReg(pDM_Odm, rFPGA1_TxInfo, bMaskDWord, 0x81121313);\r
  73 }\r
  74 \r
  75 \r
  76 \r
  77 VOID\r
  78 halTxbf8192E_FwTxBFCmd(\r
  79         IN PVOID                        pDM_VOID\r
  80 )\r
  81 {\r
  82         PDM_ODM_T       pDM_Odm = (PDM_ODM_T)pDM_VOID;\r
  83         u1Byte  Idx, Period0 = 0, Period1 = 0;\r
  84         u1Byte  PageNum0 = 0xFF, PageNum1 = 0xFF;\r
  85         u1Byte  u1TxBFParm[3] = {0};\r
  86         PRT_BEAMFORMING_INFO    pBeamInfo = &pDM_Odm->BeamformingInfo;\r
  87 \r
  88         for (Idx = 0; Idx < BEAMFORMEE_ENTRY_NUM; Idx++) {\r
  89                 if (pBeamInfo->BeamformeeEntry[Idx].BeamformEntryState == BEAMFORMING_ENTRY_STATE_PROGRESSED) {\r
  90                         if (Idx == 0) {\r
  91                                 if (pBeamInfo->BeamformeeEntry[Idx].bSound)\r
  92                                         PageNum0 = 0xFE;\r
  93                                 else\r
  94                                         PageNum0 = 0xFF; //stop sounding\r
  95                                 Period0 = (u1Byte)(pBeamInfo->BeamformeeEntry[Idx].SoundPeriod);\r
  96                         } else if (Idx == 1) {\r
  97                                 if (pBeamInfo->BeamformeeEntry[Idx].bSound)\r
  98                                         PageNum1 = 0xFE;\r
  99                                 else\r
 100                                         PageNum1 = 0xFF; //stop sounding\r
 101                                 Period1 = (u1Byte)(pBeamInfo->BeamformeeEntry[Idx].SoundPeriod);\r
 102                         }\r
 103                 }\r
 104         }\r
 105 \r
 106         u1TxBFParm[0] = PageNum0;\r
 107         u1TxBFParm[1] = PageNum1;\r
 108         u1TxBFParm[2] = (Period1 << 4) | Period0;\r
 109         ODM_FillH2CCmd(pDM_Odm, PHYDM_H2C_TXBF, 3, u1TxBFParm);\r
 110 \r
 111         ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, \r
 112                 ("[%s] PageNum0 = %d Period0 = %d, PageNum1 = %d Period1 %d\n", __func__, PageNum0, Period0, PageNum1, Period1));\r
 113 }\r
 114 \r
 115 \r
 116 VOID\r
 117 halTxbf8192E_DownloadNDPA(\r
 118         IN PVOID                        pDM_VOID,\r
 119         IN      u1Byte                          Idx\r
 120 )\r
 121 {\r
 122         PDM_ODM_T       pDM_Odm = (PDM_ODM_T)pDM_VOID;\r
 123         u1Byte                  u1bTmp = 0, tmpReg422 = 0, Head_Page;\r
 124         u1Byte                  BcnValidReg = 0, count = 0, DLBcnCount = 0;\r
 125         BOOLEAN                 bSendBeacon = FALSE;\r
 126         PADAPTER                Adapter = pDM_Odm->Adapter;\r
 127         u1Byte                  TxPageBndy = LAST_ENTRY_OF_TX_PKT_BUFFER_8812;  \r
 128         /*default reseved 1 page for the IC type which is undefined.*/\r
 129         PRT_BEAMFORMING_INFO    pBeamInfo = &pDM_Odm->BeamformingInfo;\r
 130         PRT_BEAMFORMEE_ENTRY    pBeamEntry = pBeamInfo->BeamformeeEntry + Idx;\r
 131         \r
 132         ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Start!\n", __func__));\r
 133 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)\r
 134         *pDM_Odm->pbFwDwRsvdPageInProgress = TRUE;\r
 135 #endif\r
 136         if (Idx == 0)\r
 137                 Head_Page = 0xFE;\r
 138         else\r
 139                 Head_Page = 0xFE;\r
 140 \r
 141         Adapter->HalFunc.GetHalDefVarHandler(Adapter, HAL_DEF_TX_PAGE_BOUNDARY, (pu1Byte)&TxPageBndy);\r
 142 \r
 143         /*Set REG_CR bit 8. DMA beacon by SW.*/\r
 144         u1bTmp = ODM_Read1Byte(pDM_Odm, REG_CR_8192E+1);\r
 145         ODM_Write1Byte(pDM_Odm,  REG_CR_8192E+1, (u1bTmp | BIT0));\r
 146 \r
 147         /*Set FWHW_TXQ_CTRL 0x422[6]=0 to tell Hw the packet is not a real beacon frame.*/\r
 148         tmpReg422 = ODM_Read1Byte(pDM_Odm, REG_FWHW_TXQ_CTRL_8192E+2);\r
 149         ODM_Write1Byte(pDM_Odm, REG_FWHW_TXQ_CTRL_8192E+2,  tmpReg422 & (~BIT6));\r
 150 \r
 151         if (tmpReg422 & BIT6) {\r
 152                 ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_WARNING, ("%s There is an Adapter is sending beacon.\n", __func__));\r
 153                 bSendBeacon = TRUE;\r
 154         }\r
 155 \r
 156         /*TDECTRL[15:8] 0x209[7:0] = 0xFE/0xFD  NDPA Head for TXDMA*/\r
 157         ODM_Write1Byte(pDM_Odm, REG_DWBCN0_CTRL_8192E+1, Head_Page);\r
 158 \r
 159         do {\r
 160                 /*Clear beacon valid check bit.*/\r
 161                 BcnValidReg = ODM_Read1Byte(pDM_Odm, REG_DWBCN0_CTRL_8192E+2);\r
 162                 ODM_Write1Byte(pDM_Odm, REG_DWBCN0_CTRL_8192E+2, (BcnValidReg | BIT0));\r
 163 \r
 164                 // download NDPA rsvd page.\r
 165                 Beamforming_SendHTNDPAPacket(pDM_Odm, pBeamEntry->MacAddr, pBeamEntry->SoundBW, BEACON_QUEUE);\r
 166 \r
 167 #if(DEV_BUS_TYPE == RT_PCI_INTERFACE)\r
 168                 u1bTmp = ODM_Read1Byte(pDM_Odm, REG_MGQ_TXBD_NUM_8192E+3);\r
 169                 count = 0;\r
 170                 while ((count < 20) && (u1bTmp & BIT4)) {\r
 171                         count++;\r
 172                         ODM_delay_us(10);\r
 173                         u1bTmp = ODM_Read1Byte(pDM_Odm, REG_MGQ_TXBD_NUM_8192E+3);\r
 174                 }\r
 175                 ODM_Write1Byte(pDM_Odm, REG_MGQ_TXBD_NUM_8192E+3, u1bTmp | BIT4);\r
 176 #endif\r
 177 \r
 178                 /*check rsvd page download OK.*/\r
 179                 BcnValidReg = ODM_Read1Byte(pDM_Odm, REG_DWBCN0_CTRL_8192E+2);\r
 180                 count = 0;\r
 181                 while (!(BcnValidReg & BIT0) && count < 20) {\r
 182                         count++;\r
 183                         ODM_delay_us(10);\r
 184                         BcnValidReg = ODM_Read1Byte(pDM_Odm, REG_DWBCN0_CTRL_8192E+2);\r
 185                 }\r
 186                 DLBcnCount++;\r
 187         } while (!(BcnValidReg & BIT0) && DLBcnCount < 5);\r
 188 \r
 189         if (!(BcnValidReg & BIT0))\r
 190                 ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_WARNING, ("%s Download RSVD page failed!\n", __func__));\r
 191 \r
 192         /*TDECTRL[15:8] 0x209[7:0] = 0xF9       Beacon Head for TXDMA*/\r
 193         ODM_Write1Byte(pDM_Odm, REG_DWBCN0_CTRL_8192E+1, TxPageBndy);\r
 194 \r
 195         /*To make sure that if there exists an adapter which would like to send beacon.*/\r
 196         /*If exists, the origianl value of 0x422[6] will be 1, we should check this to*/\r
 197         /*prevent from setting 0x422[6] to 0 after download reserved page, or it will cause*/\r
 198         /*the beacon cannot be sent by HW.*/\r
 199         /*2010.06.23. Added by tynli.*/\r
 200         if (bSendBeacon)\r
 201                 ODM_Write1Byte(pDM_Odm, REG_FWHW_TXQ_CTRL_8192E+2, tmpReg422);\r
 202 \r
 203         /*Do not enable HW DMA BCN or it will cause Pcie interface hang by timing issue. 2011.11.24. by tynli.*/\r
 204         /*Clear CR[8] or beacon packet will not be send to TxBuf anymore.*/\r
 205         u1bTmp = ODM_Read1Byte(pDM_Odm, REG_CR_8192E+1);\r
 206         ODM_Write1Byte(pDM_Odm, REG_CR_8192E+1, (u1bTmp & (~BIT0)));\r
 207 \r
 208         pBeamEntry->BeamformEntryState = BEAMFORMING_ENTRY_STATE_PROGRESSED;\r
 209 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)\r
 210         *pDM_Odm->pbFwDwRsvdPageInProgress = FALSE;\r
 211 #endif\r
 212 }\r
 213 \r
 214 \r
 215 VOID\r
 216 HalTxbf8192E_Enter(\r
 217         IN PVOID                        pDM_VOID,\r
 218         IN u1Byte                               BFerBFeeIdx\r
 219 )\r
 220 {\r
 221         PDM_ODM_T       pDM_Odm = (PDM_ODM_T)pDM_VOID;\r
 222         u1Byte                                  i = 0;\r
 223         u1Byte                                  BFerIdx = (BFerBFeeIdx & 0xF0) >> 4;\r
 224         u1Byte                                  BFeeIdx = (BFerBFeeIdx & 0xF);\r
 225         u4Byte                                  CSI_Param;\r
 226         PRT_BEAMFORMING_INFO    pBeamformingInfo = &pDM_Odm->BeamformingInfo;\r
 227         RT_BEAMFORMEE_ENTRY     BeamformeeEntry;\r
 228         RT_BEAMFORMER_ENTRY     BeamformerEntry;\r
 229         u2Byte                                  STAid = 0;\r
 230 \r
 231         ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Start!\n", __func__));\r
 232 \r
 233         halTxbf8192E_RfMode(pDM_Odm, pBeamformingInfo);\r
 234 \r
 235         if (pDM_Odm->RFType == ODM_2T2R)\r
 236                 ODM_Write4Byte(pDM_Odm, 0xd80, 0x00000000);             /*Nc =2*/\r
 237 \r
 238         if ((pBeamformingInfo->beamformer_su_cnt > 0) && (BFerIdx < BEAMFORMER_ENTRY_NUM)) {\r
 239                 BeamformerEntry = pBeamformingInfo->BeamformerEntry[BFerIdx];\r
 240 \r
 241                 /*Sounding protocol control*/\r
 242                 ODM_Write1Byte(pDM_Odm, REG_SND_PTCL_CTRL_8192E, 0xCB);\r
 243 \r
 244                 /*MAC address/Partial AID of Beamformer*/\r
 245                 if (BFerIdx == 0) {\r
 246                         for (i = 0; i < 6 ; i++)\r
 247                                 ODM_Write1Byte(pDM_Odm, (REG_ASSOCIATED_BFMER0_INFO_8192E+i), BeamformerEntry.MacAddr[i]);\r
 248                 } else {\r
 249                         for (i = 0; i < 6 ; i++)\r
 250                                 ODM_Write1Byte(pDM_Odm, (REG_ASSOCIATED_BFMER1_INFO_8192E+i), BeamformerEntry.MacAddr[i]);\r
 251                 }\r
 252 \r
 253                 /*CSI report parameters of Beamformer Default use Nc = 2*/\r
 254                 CSI_Param = 0x03090309;\r
 255 \r
 256                 ODM_Write4Byte(pDM_Odm, REG_CSI_RPT_PARAM_BW20_8192E, CSI_Param);\r
 257                 ODM_Write4Byte(pDM_Odm, REG_CSI_RPT_PARAM_BW40_8192E, CSI_Param);\r
 258                 ODM_Write4Byte(pDM_Odm, REG_CSI_RPT_PARAM_BW80_8192E, CSI_Param);\r
 259 \r
 260                 /*Timeout value for MAC to leave NDP_RX_standby_state (60 us, Test chip) (80 us,  MP chip)*/\r
 261                 ODM_Write1Byte(pDM_Odm, REG_SND_PTCL_CTRL_8192E+3, 0x50);\r
 262 \r
 263         }\r
 264 \r
 265         if ((pBeamformingInfo->beamformee_su_cnt > 0) && (BFeeIdx < BEAMFORMEE_ENTRY_NUM)) {\r
 266                 BeamformeeEntry = pBeamformingInfo->BeamformeeEntry[BFeeIdx];\r
 267 \r
 268                 if (phydm_actingDetermine(pDM_Odm, PhyDM_ACTING_AS_IBSS))\r
 269                         STAid = BeamformeeEntry.MacId;\r
 270                 else\r
 271                         STAid = BeamformeeEntry.P_AID;\r
 272 \r
 273                 ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s], STAid=0x%X\n", __func__, STAid));\r
 274 \r
 275                 /*P_AID of Beamformee & enable NDPA transmission & enable NDPA interrupt*/\r
 276                 if (BFeeIdx == 0) {\r
 277                         ODM_Write2Byte(pDM_Odm, REG_TXBF_CTRL_8192E, STAid);\r
 278                         ODM_Write1Byte(pDM_Odm, REG_TXBF_CTRL_8192E+3, ODM_Read1Byte(pDM_Odm, REG_TXBF_CTRL_8192E+3) | BIT4 | BIT6 | BIT7);\r
 279                 } else\r
 280                         ODM_Write2Byte(pDM_Odm, REG_TXBF_CTRL_8192E+2, STAid | BIT12 | BIT14 | BIT15);\r
 281 \r
 282                 /*CSI report parameters of Beamformee*/\r
 283                 if (BFeeIdx == 0) {\r
 284                         /*Get BIT24 & BIT25*/\r
 285                         u1Byte tmp = ODM_Read1Byte(pDM_Odm, REG_ASSOCIATED_BFMEE_SEL_8192E+3) & 0x3;\r
 286                         \r
 287                         ODM_Write1Byte(pDM_Odm, REG_ASSOCIATED_BFMEE_SEL_8192E+3, tmp | 0x60);\r
 288                         ODM_Write2Byte(pDM_Odm, REG_ASSOCIATED_BFMEE_SEL_8192E, STAid | BIT9);\r
 289                 } else {\r
 290                         /*Set BIT25*/\r
 291                         ODM_Write2Byte(pDM_Odm, REG_ASSOCIATED_BFMEE_SEL_8192E+2, STAid | 0xE200);\r
 292                 }\r
 293                         phydm_Beamforming_Notify(pDM_Odm);\r
 294 \r
 295         }\r
 296 }\r
 297 \r
 298 \r
 299 VOID\r
 300 HalTxbf8192E_Leave(\r
 301         IN PVOID                        pDM_VOID,\r
 302         IN u1Byte                               Idx\r
 303 )\r
 304 {\r
 305         PDM_ODM_T       pDM_Odm = (PDM_ODM_T)pDM_VOID;\r
 306         PRT_BEAMFORMING_INFO    pBeamInfo = &pDM_Odm->BeamformingInfo;\r
 307 \r
 308         halTxbf8192E_RfMode(pDM_Odm, pBeamInfo);\r
 309 \r
 310         /*      Clear P_AID of Beamformee\r
 311         *       Clear MAC addresss of Beamformer\r
 312         *       Clear Associated Bfmee Sel\r
 313         */\r
 314         if (pBeamInfo->BeamformCap == BEAMFORMING_CAP_NONE)\r
 315                 ODM_Write1Byte(pDM_Odm, REG_SND_PTCL_CTRL_8192E, 0xC8);\r
 316 \r
 317         if (Idx == 0) {\r
 318                 ODM_Write2Byte(pDM_Odm, REG_TXBF_CTRL_8192E, 0);\r
 319                 ODM_Write4Byte(pDM_Odm, REG_ASSOCIATED_BFMER0_INFO_8192E, 0);\r
 320                 ODM_Write2Byte(pDM_Odm, REG_ASSOCIATED_BFMER0_INFO_8192E+4, 0);\r
 321                 ODM_Write2Byte(pDM_Odm, REG_ASSOCIATED_BFMEE_SEL_8192E, 0);\r
 322         } else {\r
 323                 ODM_Write2Byte(pDM_Odm, REG_TXBF_CTRL_8192E+2, ODM_Read1Byte(pDM_Odm, REG_TXBF_CTRL_8192E+2) & 0xF000);\r
 324                 ODM_Write4Byte(pDM_Odm, REG_ASSOCIATED_BFMER1_INFO_8192E, 0);\r
 325                 ODM_Write2Byte(pDM_Odm, REG_ASSOCIATED_BFMER1_INFO_8192E+4, 0);\r
 326                 ODM_Write2Byte(pDM_Odm, REG_ASSOCIATED_BFMEE_SEL_8192E+2, ODM_Read2Byte(pDM_Odm, REG_ASSOCIATED_BFMEE_SEL_8192E+2) & 0x60);\r
 327         }\r
 328 \r
 329         ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Idx %d\n", __func__, Idx));\r
 330 }\r
 331 \r
 332 \r
 333 VOID\r
 334 HalTxbf8192E_Status(\r
 335         IN PVOID                        pDM_VOID,\r
 336         IN u1Byte                               Idx\r
 337 )\r
 338 {\r
 339         PDM_ODM_T       pDM_Odm = (PDM_ODM_T)pDM_VOID;\r
 340         u2Byte                                  BeamCtrlVal;\r
 341         u4Byte                                  BeamCtrlReg;\r
 342         PRT_BEAMFORMING_INFO    pBeamInfo =  &pDM_Odm->BeamformingInfo;\r
 343         RT_BEAMFORMEE_ENTRY     BeamformEntry = pBeamInfo->BeamformeeEntry[Idx];\r
 344 \r
 345         if (phydm_actingDetermine(pDM_Odm, PhyDM_ACTING_AS_IBSS))\r
 346                 BeamCtrlVal = BeamformEntry.MacId;\r
 347         else\r
 348                 BeamCtrlVal = BeamformEntry.P_AID;\r
 349 \r
 350         if (Idx == 0)\r
 351                 BeamCtrlReg = REG_TXBF_CTRL_8192E;\r
 352         else {\r
 353                 BeamCtrlReg = REG_TXBF_CTRL_8192E+2;\r
 354                 BeamCtrlVal |= BIT12 | BIT14 | BIT15;\r
 355         }\r
 356 \r
 357         if ((BeamformEntry.BeamformEntryState == BEAMFORMING_ENTRY_STATE_PROGRESSED) && (pBeamInfo->applyVmatrix == TRUE)) {\r
 358                 if (BeamformEntry.SoundBW == CHANNEL_WIDTH_20)\r
 359                         BeamCtrlVal |= BIT9;\r
 360                 else if (BeamformEntry.SoundBW == CHANNEL_WIDTH_40)\r
 361                         BeamCtrlVal |= BIT10;\r
 362         } else\r
 363                 BeamCtrlVal &= ~(BIT9 | BIT10 | BIT11);\r
 364 \r
 365         ODM_Write2Byte(pDM_Odm, BeamCtrlReg, BeamCtrlVal);\r
 366 \r
 367         ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Idx %d BeamCtrlReg %x BeamCtrlVal %x\n", __func__, Idx, BeamCtrlReg, BeamCtrlVal));\r
 368 }\r
 369 \r
 370 \r
 371 VOID\r
 372 HalTxbf8192E_FwTxBF(\r
 373         IN PVOID                        pDM_VOID,\r
 374         IN      u1Byte                          Idx\r
 375 )\r
 376 {\r
 377         PDM_ODM_T       pDM_Odm = (PDM_ODM_T)pDM_VOID;\r
 378         PRT_BEAMFORMING_INFO    pBeamInfo = &pDM_Odm->BeamformingInfo;\r
 379         PRT_BEAMFORMEE_ENTRY    pBeamEntry = pBeamInfo->BeamformeeEntry + Idx;\r
 380 \r
 381         ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Start!\n", __func__));\r
 382 \r
 383         if (pBeamEntry->BeamformEntryState == BEAMFORMING_ENTRY_STATE_PROGRESSING)\r
 384                 halTxbf8192E_DownloadNDPA(pDM_Odm, Idx);\r
 385 \r
 386         halTxbf8192E_FwTxBFCmd(pDM_Odm);\r
 387 }\r
 388 \r
 389 #endif  /* #if (RTL8192E_SUPPORT == 1)*/\r
 390 \r
 391 #endif\r
 392 \r