drivers/net/wireless/rockchip_wlan/rtl8723ds/hal/rtl8723d/rtl8723d_phycfg.c

   1 /******************************************************************************
   2  *
   3  * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of version 2 of the GNU General Public License as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program; if not, write to the Free Software Foundation, Inc.,
  16  * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  17  *
  18  *
  19  ******************************************************************************/
  20 #define _RTL8723D_PHYCFG_C_
  21
  22 #include <rtl8723d_hal.h>
  23
  24
  25 /*---------------------------Define Local Constant---------------------------*/
  26 /* Channel switch:The size of command tables for switch channel*/
  27 #define MAX_PRECMD_CNT 16
  28 #define MAX_RFDEPENDCMD_CNT 16
  29 #define MAX_POSTCMD_CNT 16
  30
  31 #define MAX_DOZE_WAITING_TIMES_9x 64
  32
  33 /*---------------------------Define Local Constant---------------------------*/
  34
  35
  36 /*------------------------Define global variable-----------------------------*/
  37
  38 /*------------------------Define local variable------------------------------*/
  39
  40
  41 /*--------------------Define export function prototype-----------------------*/
  42 /* Please refer to header file
  43  *--------------------Define export function prototype-----------------------*/
  44
  45 /*----------------------------Function Body----------------------------------*/
  46 /*
  47  * 1. BB register R/W API
  48  *   */
  49
  50 /**
  51 * Function:     phy_CalculateBitShift
  52 *
  53 * OverView:     Get shifted position of the BitMask
  54 *
  55 * Input:
  56 *                       u4Byte          BitMask,
  57 *
  58 * Output:       none
  59 * Return:               u4Byte          Return the shift bit bit position of the mask
  60 */
  61 static  u32
  62 phy_CalculateBitShift(
  63         u32 BitMask
  64 )
  65 {
  66         u32 i;
  67
  68         for (i = 0; i <= 31; i++) {
  69                 if (((BitMask >> i) &  0x1) == 1)
  70                         break;
  71         }
  72
  73         return i;
  74 }
  75
  76
  77 /**
  78 * Function:     PHY_QueryBBReg
  79 *
  80 * OverView:     Read "sepcific bits" from BB register
  81 *
  82 * Input:
  83 *                       PADAPTER                Adapter,
  84 *                       u4Byte                  RegAddr,
  85 *                       u4Byte                  BitMask
  86 *
  87 * Output:       None
  88 * Return:               u4Byte                  Data
  89 * Note:         This function is equal to "GetRegSetting" in PHY programming guide
  90 */
  91 u32
  92 PHY_QueryBBReg_8723D(
  93         IN      PADAPTER        Adapter,
  94         IN      u32             RegAddr,
  95         IN      u32             BitMask
  96 )
  97 {
  98         u32     ReturnValue = 0, OriginalValue, BitShift;
  99         u16     BBWaitCounter = 0;
 100
 101 #if (DISABLE_BB_RF == 1)
 102         return 0;
 103 #endif
 104
 105
 106         OriginalValue = rtw_read32(Adapter, RegAddr);
 107         BitShift = phy_CalculateBitShift(BitMask);
 108         ReturnValue = (OriginalValue & BitMask) >> BitShift;
 109
 110         return ReturnValue;
 111
 112 }
 113
 114
 115 /**
 116 * Function:     PHY_SetBBReg
 117 *
 118 * OverView:     Write "Specific bits" to BB register (page 8~)
 119 *
 120 * Input:
 121 *                       PADAPTER                Adapter,
 122 *                       u4Byte                  RegAddr,
 123 *                       u4Byte                  BitMask
 124 *
 125 *                       u4Byte                  Data
 126 *
 127 *
 128 * Output:       None
 129 * Return:               None
 130 * Note:         This function is equal to "PutRegSetting" in PHY programming guide
 131 */
 132
 133 VOID
 134 PHY_SetBBReg_8723D(
 135         IN      PADAPTER        Adapter,
 136         IN      u32             RegAddr,
 137         IN      u32             BitMask,
 138         IN      u32             Data
 139 )
 140 {
 141         HAL_DATA_TYPE   *pHalData               = GET_HAL_DATA(Adapter);
 142         /* u16                  BBWaitCounter   = 0; */
 143         u32                     OriginalValue, BitShift;
 144
 145 #if (DISABLE_BB_RF == 1)
 146         return;
 147 #endif
 148
 149
 150         if (BitMask != bMaskDWord) { /* if not "double word" write */
 151                 OriginalValue = rtw_read32(Adapter, RegAddr);
 152                 BitShift = phy_CalculateBitShift(BitMask);
 153                 Data = ((OriginalValue & (~BitMask)) | ((Data << BitShift) & BitMask));
 154         }
 155
 156         rtw_write32(Adapter, RegAddr, Data);
 157
 158 }
 159
 160
 161 /*
 162  * 2. RF register R/W API
 163  *   */
 164
 165 /*-----------------------------------------------------------------------------
 166  * Function:    phy_FwRFSerialRead()
 167  *
 168  * Overview:    We support firmware to execute RF-R/W.
 169  *
 170  * Input:               NONE
 171  *
 172  * Output:              NONE
 173  *
 174  * Return:              NONE
 175  *
 176  * Revised History:
 177  *      When            Who             Remark
 178  *      01/21/2008      MHC             Create Version 0.
 179  *
 180  *---------------------------------------------------------------------------*/
 181 static  u32
 182 phy_FwRFSerialRead(
 183         IN      PADAPTER                        Adapter,
 184         IN      RF_PATH                 eRFPath,
 185         IN      u32                             Offset)
 186 {
 187         u32             retValue = 0;
 188         /* RT_ASSERT(FALSE,("deprecate!\n")); */
 189         return  retValue;
 190
 191 }       /* phy_FwRFSerialRead */
 192
 193
 194 /*-----------------------------------------------------------------------------
 195  * Function:    phy_FwRFSerialWrite()
 196  *
 197  * Overview:    We support firmware to execute RF-R/W.
 198  *
 199  * Input:               NONE
 200  *
 201  * Output:              NONE
 202  *
 203  * Return:              NONE
 204  *
 205  * Revised History:
 206  *      When            Who             Remark
 207  *      01/21/2008      MHC             Create Version 0.
 208  *
 209  *---------------------------------------------------------------------------*/
 210 static  VOID
 211 phy_FwRFSerialWrite(
 212         IN      PADAPTER                        Adapter,
 213         IN      RF_PATH                 eRFPath,
 214         IN      u32                             Offset,
 215         IN      u32                             Data)
 216 {
 217         /* RT_ASSERT(FALSE,("deprecate!\n")); */
 218 }
 219
 220 static  u32
 221 phy_RFSerialRead_8723D(
 222         IN      PADAPTER                        Adapter,
 223         IN      RF_PATH                 eRFPath,
 224         IN      u32                             Offset
 225 )
 226 {
 227         u32                                             retValue = 0;
 228         HAL_DATA_TYPE                           *pHalData = GET_HAL_DATA(Adapter);
 229         BB_REGISTER_DEFINITION_T        *pPhyReg = &pHalData->PHYRegDef[eRFPath];
 230         u32                                             NewOffset;
 231         u32                                             tmplong, tmplong2;
 232         u8                                      RfPiEnable = 0;
 233         u4Byte                                          MaskforPhySet = 0;
 234         int i = 0;
 235
 236         _enter_critical_mutex(&(adapter_to_dvobj(Adapter)->rf_read_reg_mutex) , NULL);
 237         /* */
 238         /* Make sure RF register offset is correct */
 239         /* */
 240         Offset &= 0xff;
 241
 242         NewOffset = Offset;
 243
 244         if (eRFPath == RF_PATH_A) {
 245                 tmplong2 = PHY_QueryBBReg(Adapter, rFPGA0_XA_HSSIParameter2 | MaskforPhySet, bMaskDWord);
 246                 tmplong2 = (tmplong2 & (~bLSSIReadAddress)) | (NewOffset << 23) | bLSSIReadEdge;        /* T65 RF */
 247                 PHY_SetBBReg(Adapter, rFPGA0_XA_HSSIParameter2 | MaskforPhySet, bMaskDWord, tmplong2 & (~bLSSIReadEdge));
 248         } else {
 249                 tmplong2 = PHY_QueryBBReg(Adapter, rFPGA0_XB_HSSIParameter2 | MaskforPhySet, bMaskDWord);
 250                 tmplong2 = (tmplong2 & (~bLSSIReadAddress)) | (NewOffset << 23) | bLSSIReadEdge;        /* T65 RF */
 251                 PHY_SetBBReg(Adapter, rFPGA0_XB_HSSIParameter2 | MaskforPhySet, bMaskDWord, tmplong2 & (~bLSSIReadEdge));
 252         }
 253
 254         tmplong2 = PHY_QueryBBReg(Adapter, rFPGA0_XA_HSSIParameter2 | MaskforPhySet, bMaskDWord);
 255         PHY_SetBBReg(Adapter, rFPGA0_XA_HSSIParameter2 | MaskforPhySet, bMaskDWord, tmplong2 & (~bLSSIReadEdge));
 256         PHY_SetBBReg(Adapter, rFPGA0_XA_HSSIParameter2 | MaskforPhySet, bMaskDWord, tmplong2 | bLSSIReadEdge);
 257
 258         rtw_udelay_os(10);
 259
 260         for (i = 0; i < 2; i++)
 261                 rtw_udelay_os(MAX_STALL_TIME);
 262         rtw_udelay_os(10);
 263
 264         if (eRFPath == RF_PATH_A)
 265                 RfPiEnable = (u1Byte)PHY_QueryBBReg(Adapter, rFPGA0_XA_HSSIParameter1 | MaskforPhySet, BIT(8));
 266         else if (eRFPath == RF_PATH_B)
 267                 RfPiEnable = (u1Byte)PHY_QueryBBReg(Adapter, rFPGA0_XB_HSSIParameter1 | MaskforPhySet, BIT(8));
 268
 269         if (RfPiEnable) {
 270                 /* Read from BBreg8b8, 12 bits for 8190, 20bits for T65 RF */
 271                 retValue = PHY_QueryBBReg(Adapter, pPhyReg->rfLSSIReadBackPi | MaskforPhySet, bLSSIReadBackData);
 272
 273                 /* RT_DISP(FINIT, INIT_RF, ("Readback from RF-PI : 0x%x\n", retValue)); */
 274         } else {
 275                 /* Read from BBreg8a0, 12 bits for 8190, 20 bits for T65 RF */
 276                 retValue = PHY_QueryBBReg(Adapter, pPhyReg->rfLSSIReadBack | MaskforPhySet, bLSSIReadBackData);
 277
 278                 /* RT_DISP(FINIT, INIT_RF,("Readback from RF-SI : 0x%x\n", retValue)); */
 279         }
 280         _exit_critical_mutex(&(adapter_to_dvobj(Adapter)->rf_read_reg_mutex) , NULL);
 281         return retValue;
 282
 283 }
 284
 285 /**
 286 * Function:     phy_RFSerialWrite_8723D
 287 *
 288 * OverView:     Write data to RF register (page 8~)
 289 *
 290 * Input:
 291 *                       PADAPTER                Adapter,
 292 *                       RF_PATH                 eRFPath,
 293 *                       u4Byte                  Offset,
 294 *                       u4Byte                  Data
 295 *
 296 *
 297 * Output:       None
 298 * Return:               None
 299 * Note:         Threre are three types of serial operations:
 300 *                       1. Software serial write
 301 *                       2. Hardware LSSI-Low Speed Serial Interface
 302 *                       3. Hardware HSSI-High speed
 303 *                       serial write. Driver need to implement (1) and (2).
 304 *                       This function is equal to the combination of RF_ReadReg() and  RFLSSIRead()
 305  *
 306  * Note:                  For RF8256 only
 307  *                       The total count of RTL8256(Zebra4) register is around 36 bit it only employs
 308  *                       4-bit RF address. RTL8256 uses "register mode control bit" (Reg00[12], Reg00[10])
 309  *                       to access register address bigger than 0xf. See "Appendix-4 in PHY Configuration
 310  *                       programming guide" for more details.
 311  *                       Thus, we define a sub-finction for RTL8526 register address conversion
 312  *                     ===========================================================
 313  *                       Register Mode          RegCTL[1]               RegCTL[0]               Note
 314  *                                                              (Reg00[12])             (Reg00[10])
 315  *                     ===========================================================
 316  *                       Reg_Mode0                              0                               x                       Reg 0 ~15(0x0 ~ 0xf)
 317  *                     ------------------------------------------------------------------
 318  *                       Reg_Mode1                              1                               0                       Reg 16 ~30(0x1 ~ 0xf)
 319  *                     ------------------------------------------------------------------
 320  *                       Reg_Mode2                              1                               1                       Reg 31 ~ 45(0x1 ~ 0xf)
 321  *                     ------------------------------------------------------------------
 322  *
 323  *      2008/09/02      MH      Add 92S RF definition
 324  *
 325  *
 326  *
 327 */
 328 static  VOID
 329 phy_RFSerialWrite_8723D(
 330         IN      PADAPTER                        Adapter,
 331         IN      RF_PATH                 eRFPath,
 332         IN      u32                             Offset,
 333         IN      u32                             Data
 334 )
 335 {
 336         u32                                             DataAndAddr = 0;
 337         HAL_DATA_TYPE                           *pHalData = GET_HAL_DATA(Adapter);
 338         BB_REGISTER_DEFINITION_T        *pPhyReg = &pHalData->PHYRegDef[eRFPath];
 339         u32                                             NewOffset;
 340
 341         Offset &= 0xff;
 342
 343         /* */
 344         /* Shadow Update */
 345         /* */
 346         /* PHY_RFShadowWrite(Adapter, eRFPath, Offset, Data); */
 347
 348         /* */
 349         /* Switch page for 8256 RF IC */
 350         /* */
 351         NewOffset = Offset;
 352
 353         /* */
 354         /* Put write addr in [5:0]  and write data in [31:16] */
 355         /* */
 356         /* DataAndAddr = (Data<<16) | (NewOffset&0x3f); */
 357         DataAndAddr = ((NewOffset << 20) | (Data & 0x000fffff)) & 0x0fffffff;   /* T65 RF */
 358
 359         /* */
 360         /* Write Operation */
 361         /* */
 362         PHY_SetBBReg(Adapter, pPhyReg->rf3wireOffset, bMaskDWord, DataAndAddr);
 363         /* RTPRINT(FPHY, PHY_RFW, ("RFW-%d Addr[0x%lx]=0x%lx\n", eRFPath, pPhyReg->rf3wireOffset, DataAndAddr)); */
 364
 365 }
 366
 367
 368 /**
 369 * Function:     PHY_QueryRFReg
 370 *
 371 * OverView:     Query "Specific bits" to RF register (page 8~)
 372 *
 373 * Input:
 374 *                       PADAPTER                Adapter,
 375 *                       RF_PATH                 eRFPath,
 376 *                       u4Byte                  RegAddr,
 377 *                       u4Byte                  BitMask
 378 *
 379 *
 380 * Output:       None
 381 * Return:               u4Byte                  Readback value
 382 * Note:         This function is equal to "GetRFRegSetting" in PHY programming guide
 383 */
 384 u32
 385 PHY_QueryRFReg_8723D(
 386         IN      PADAPTER                        Adapter,
 387         IN      u8                      eRFPath,
 388         IN      u32                             RegAddr,
 389         IN      u32                             BitMask
 390 )
 391 {
 392         u32 Original_Value, Readback_Value, BitShift;
 393
 394 #if (DISABLE_BB_RF == 1)
 395         return 0;
 396 #endif
 397
 398         Original_Value = phy_RFSerialRead_8723D(Adapter, eRFPath, RegAddr);
 399
 400         BitShift =  phy_CalculateBitShift(BitMask);
 401         Readback_Value = (Original_Value & BitMask) >> BitShift;
 402
 403         return Readback_Value;
 404 }
 405
 406 /**
 407 * Function:     PHY_SetRFReg
 408 *
 409 * OverView:     Write "Specific bits" to RF register (page 8~)
 410 *
 411 * Input:
 412 *                       PADAPTER                Adapter,
 413 *                       RF_PATH                 eRFPath,
 414 *                       u4Byte                  RegAddr,
 415 *                       u4Byte                  BitMask
 416 *
 417 *                       u4Byte                  Data
 418 *
 419 *
 420 * Output:       None
 421 * Return:               None
 422 * Note:         This function is equal to "PutRFRegSetting" in PHY programming guide
 423 */
 424 VOID
 425 PHY_SetRFReg_8723D(
 426         IN      PADAPTER                        Adapter,
 427         IN      u8                              eRFPath,
 428         IN      u32                             RegAddr,
 429         IN      u32                             BitMask,
 430         IN      u32                             Data
 431 )
 432 {
 433         u32             Original_Value, BitShift;
 434
 435 #if (DISABLE_BB_RF == 1)
 436         return;
 437 #endif
 438
 439         /* RF data is 12 bits only */
 440         if (BitMask != bRFRegOffsetMask) {
 441                 Original_Value = phy_RFSerialRead_8723D(Adapter, eRFPath, RegAddr);
 442                 BitShift =  phy_CalculateBitShift(BitMask);
 443                 Data = ((Original_Value & (~BitMask)) | (Data << BitShift));
 444         }
 445
 446         phy_RFSerialWrite_8723D(Adapter, eRFPath, RegAddr, Data);
 447 }
 448
 449
 450 /*
 451  * 3. Initial MAC/BB/RF config by reading MAC/BB/RF txt.
 452  *   */
 453
 454
 455 /*-----------------------------------------------------------------------------
 456  * Function:    PHY_MACConfig8192C
 457  *
 458  * Overview:    Condig MAC by header file or parameter file.
 459  *
 460  * Input:       NONE
 461  *
 462  * Output:      NONE
 463  *
 464  * Return:      NONE
 465  *
 466  * Revised History:
 467  *  When                Who             Remark
 468  *  08/12/2008  MHC             Create Version 0.
 469  *
 470  *---------------------------------------------------------------------------*/
 471 s32 PHY_MACConfig8723D(PADAPTER Adapter)
 472 {
 473         int             rtStatus = _SUCCESS;
 474         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(Adapter);
 475
 476         /* */
 477         /* Config MAC */
 478         /* */
 479 #ifdef CONFIG_LOAD_PHY_PARA_FROM_FILE
 480         rtStatus = phy_ConfigMACWithParaFile(Adapter, PHY_FILE_MAC_REG);
 481         if (rtStatus == _FAIL)
 482 #endif
 483         {
 484 #ifdef CONFIG_EMBEDDED_FWIMG
 485                 ODM_ConfigMACWithHeaderFile(&pHalData->odmpriv);
 486                 rtStatus = _SUCCESS;
 487 #endif/* CONFIG_EMBEDDED_FWIMG */
 488         }
 489
 490         return rtStatus;
 491 }
 492
 493 /**
 494 * Function:     phy_InitBBRFRegisterDefinition
 495 *
 496 * OverView:     Initialize Register definition offset for Radio Path A/B/C/D
 497 *
 498 * Input:
 499 *                       PADAPTER                Adapter,
 500 *
 501 * Output:       None
 502 * Return:               None
 503 * Note:         The initialization value is constant and it should never be changes
 504 */
 505 static  VOID
 506 phy_InitBBRFRegisterDefinition(
 507         IN      PADAPTER                Adapter
 508 )
 509 {
 510         HAL_DATA_TYPE           *pHalData = GET_HAL_DATA(Adapter);
 511
 512         /* RF Interface Sowrtware Control */
 513         pHalData->PHYRegDef[ODM_RF_PATH_A].rfintfs = rFPGA0_XAB_RFInterfaceSW; /* 16 LSBs if read 32-bit from 0x870 */
 514         pHalData->PHYRegDef[ODM_RF_PATH_B].rfintfs = rFPGA0_XAB_RFInterfaceSW; /* 16 MSBs if read 32-bit from 0x870 (16-bit for 0x872) */
 515
 516         /* RF Interface Output (and Enable) */
 517         pHalData->PHYRegDef[ODM_RF_PATH_A].rfintfo = rFPGA0_XA_RFInterfaceOE; /* 16 LSBs if read 32-bit from 0x860 */
 518         pHalData->PHYRegDef[ODM_RF_PATH_B].rfintfo = rFPGA0_XB_RFInterfaceOE; /* 16 LSBs if read 32-bit from 0x864 */
 519
 520         /* RF Interface (Output and)  Enable */
 521         pHalData->PHYRegDef[ODM_RF_PATH_A].rfintfe = rFPGA0_XA_RFInterfaceOE; /* 16 MSBs if read 32-bit from 0x860 (16-bit for 0x862) */
 522         pHalData->PHYRegDef[ODM_RF_PATH_B].rfintfe = rFPGA0_XB_RFInterfaceOE; /* 16 MSBs if read 32-bit from 0x864 (16-bit for 0x866) */
 523
 524         pHalData->PHYRegDef[ODM_RF_PATH_A].rf3wireOffset = rFPGA0_XA_LSSIParameter; /* LSSI Parameter */
 525         pHalData->PHYRegDef[ODM_RF_PATH_B].rf3wireOffset = rFPGA0_XB_LSSIParameter;
 526
 527         pHalData->PHYRegDef[ODM_RF_PATH_A].rfHSSIPara2 = rFPGA0_XA_HSSIParameter2;  /* wire control parameter2 */
 528         pHalData->PHYRegDef[ODM_RF_PATH_B].rfHSSIPara2 = rFPGA0_XB_HSSIParameter2;  /* wire control parameter2 */
 529
 530         /* Tranceiver Readback LSSI/HSPI mode */
 531         pHalData->PHYRegDef[ODM_RF_PATH_A].rfLSSIReadBack = rFPGA0_XA_LSSIReadBack;
 532         pHalData->PHYRegDef[ODM_RF_PATH_B].rfLSSIReadBack = rFPGA0_XB_LSSIReadBack;
 533         pHalData->PHYRegDef[ODM_RF_PATH_A].rfLSSIReadBackPi = TransceiverA_HSPI_Readback;
 534         pHalData->PHYRegDef[ODM_RF_PATH_B].rfLSSIReadBackPi = TransceiverB_HSPI_Readback;
 535
 536 }
 537
 538 static  int
 539 phy_BB8723d_Config_ParaFile(
 540         IN      PADAPTER        Adapter
 541 )
 542 {
 543         HAL_DATA_TYPE           *pHalData = GET_HAL_DATA(Adapter);
 544         int                     rtStatus = _SUCCESS;
 545
 546         /* */
 547         /* 1. Read PHY_REG.TXT BB INIT!! */
 548         /* */
 549 #ifdef CONFIG_LOAD_PHY_PARA_FROM_FILE
 550         if (phy_ConfigBBWithParaFile(Adapter, PHY_FILE_PHY_REG, CONFIG_BB_PHY_REG) == _FAIL)
 551 #endif
 552         {
 553 #ifdef CONFIG_EMBEDDED_FWIMG
 554                 if (HAL_STATUS_SUCCESS != ODM_ConfigBBWithHeaderFile(&pHalData->odmpriv, CONFIG_BB_PHY_REG))
 555                         rtStatus = _FAIL;
 556 #endif
 557         }
 558
 559         if (rtStatus != _SUCCESS) {
 560                 RTW_INFO("%s():Write BB Reg Fail!!", __func__);
 561                 goto phy_BB8190_Config_ParaFile_Fail;
 562         }
 563
 564 #if MP_DRIVER == 1
 565         if (Adapter->registrypriv.mp_mode == 1) {
 566                 /*20160504, Suggested by jessica_wang. To Fix CCK ACPR issue*/
 567                 PHY_SetBBReg(Adapter, 0xCE0, BIT1|BIT0, 0);/*RXHP=low corner*/
 568                 PHY_SetBBReg(Adapter, 0xC3C, 0xFF, 0xCC);/*make sure low rate sensitivity*/
 569         }
 570 #endif  /*  #if (MP_DRIVER == 1) */
 571
 572         /* */
 573         /* 2. Read BB AGC table Initialization */
 574         /* */
 575 #ifdef CONFIG_LOAD_PHY_PARA_FROM_FILE
 576         if (phy_ConfigBBWithParaFile(Adapter, PHY_FILE_AGC_TAB, CONFIG_BB_AGC_TAB) == _FAIL)
 577 #endif
 578         {
 579 #ifdef CONFIG_EMBEDDED_FWIMG
 580                 if (HAL_STATUS_SUCCESS != ODM_ConfigBBWithHeaderFile(&pHalData->odmpriv, CONFIG_BB_AGC_TAB))
 581                         rtStatus = _FAIL;
 582 #endif
 583         }
 584
 585         if (rtStatus != _SUCCESS) {
 586                 RTW_INFO("%s():AGC Table Fail\n", __func__);
 587                 goto phy_BB8190_Config_ParaFile_Fail;
 588         }
 589
 590 phy_BB8190_Config_ParaFile_Fail:
 591
 592         return rtStatus;
 593 }
 594
 595
 596 int
 597 PHY_BBConfig8723D(
 598         IN PADAPTER Adapter
 599 )
 600 {
 601         int     rtStatus = _SUCCESS;
 602         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(Adapter);
 603         u32     RegVal;
 604         u8      TmpU1B = 0;
 605         u8      value8;
 606
 607         phy_InitBBRFRegisterDefinition(Adapter);
 608
 609         /* Enable BB and RF */
 610         RegVal = rtw_read16(Adapter, REG_SYS_FUNC_EN);
 611         rtw_write16(Adapter, REG_SYS_FUNC_EN, (u16)(RegVal | BIT(13) | BIT(0) | BIT(1)));
 612
 613         rtw_write8(Adapter, REG_RF_CTRL, RF_EN | RF_RSTB | RF_SDMRSTB);
 614
 615 #if (DEV_BUS_TYPE == RT_USB_INTERFACE)
 616         rtw_write8(Adapter, REG_SYS_FUNC_EN, FEN_USBA | FEN_USBD | FEN_BB_GLB_RSTn | FEN_BBRSTB);
 617 #else
 618         rtw_write8(Adapter, REG_SYS_FUNC_EN, FEN_PPLL | FEN_PCIEA | FEN_DIO_PCIE | FEN_BB_GLB_RSTn | FEN_BBRSTB);
 619 #endif
 620
 621 #if DEV_BUS_TYPE == RT_USB_INTERFACE
 622         /* To Fix MAC loopback mode fail. Suggested by SD4 Johnny. 2010.03.23. */
 623         PlatformEFIOWrite1Byte(Adapter, REG_LDOHCI12_CTRL, 0x0f);
 624         PlatformEFIOWrite1Byte(Adapter, 0x15, 0xe9);
 625 #endif
 626
 627         rtw_write8(Adapter, REG_AFE_XTAL_CTRL + 1, 0x80);
 628
 629         /*
 630          * Config BB and AGC
 631          */
 632         rtStatus = phy_BB8723d_Config_ParaFile(Adapter);
 633
 634         hal_set_crystal_cap(Adapter, pHalData->CrystalCap);
 635
 636         return rtStatus;
 637 }
 638 #if 0
 639 /* Block & Path enable */
 640 #define         rOFDMCCKEN_Jaguar               0x808 /* OFDM/CCK block enable */
 641 #define         bOFDMEN_Jaguar                  0x20000000
 642 #define         bCCKEN_Jaguar                   0x10000000
 643 #define         rRxPath_Jaguar                  0x808   /* Rx antenna */
 644 #define         bRxPath_Jaguar                  0xff
 645 #define         rTxPath_Jaguar                  0x80c   /* Tx antenna */
 646 #define         bTxPath_Jaguar                  0x0fffffff
 647 #define         rCCK_RX_Jaguar                  0xa04   /* for cck rx path selection */
 648 #define         bCCK_RX_Jaguar                  0x0c000000
 649 #define         rVhtlen_Use_Lsig_Jaguar 0x8c3   /* Use LSIG for VHT length */
 650 VOID
 651 PHY_BB8723D_Config_1T(
 652         IN PADAPTER Adapter
 653 )
 654 {
 655         /* BB OFDM RX Path_A */
 656         PHY_SetBBReg(Adapter, rRxPath_Jaguar, bRxPath_Jaguar, 0x11);
 657         /* BB OFDM TX Path_A */
 658         PHY_SetBBReg(Adapter, rTxPath_Jaguar, bMaskLWord, 0x1111);
 659         /* BB CCK R/Rx Path_A */
 660         PHY_SetBBReg(Adapter, rCCK_RX_Jaguar, bCCK_RX_Jaguar, 0x0);
 661         /* MCS support */
 662         PHY_SetBBReg(Adapter, 0x8bc, 0xc0000060, 0x4);
 663         /* RF Path_B HSSI OFF */
 664         PHY_SetBBReg(Adapter, 0xe00, 0xf, 0x4);
 665         /* RF Path_B Power Down */
 666         PHY_SetBBReg(Adapter, 0xe90, bMaskDWord, 0);
 667         /* ADDA Path_B OFF */
 668         PHY_SetBBReg(Adapter, 0xe60, bMaskDWord, 0);
 669         PHY_SetBBReg(Adapter, 0xe64, bMaskDWord, 0);
 670 }
 671 #endif
 672
 673 int
 674 PHY_RFConfig8723D(
 675         IN      PADAPTER        Adapter
 676 )
 677 {
 678         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(Adapter);
 679         int             rtStatus = _SUCCESS;
 680
 681         /* */
 682         /* RF config */
 683         /* */
 684         rtStatus = PHY_RF6052_Config8723D(Adapter);
 685         /* 20151207 LCK done at RadioA table */
 686         /* PHY_BB8723D_Config_1T(Adapter); */
 687
 688         return rtStatus;
 689 }
 690
 691 /*-----------------------------------------------------------------------------
 692  * Function:    PHY_ConfigRFWithParaFile()
 693  *
 694  * Overview:    This function read RF parameters from general file format, and do RF 3-wire
 695  *
 696  * Input:       PADAPTER                        Adapter
 697  *                      ps1Byte                         pFileName
 698  *                      RF_PATH                         eRFPath
 699  *
 700  * Output:      NONE
 701  *
 702  * Return:      RT_STATUS_SUCCESS: configuration file exist
 703  *
 704  * Note:                Delay may be required for RF configuration
 705  *---------------------------------------------------------------------------*/
 706 int
 707 PHY_ConfigRFWithParaFile_8723D(
 708         IN      PADAPTER                        Adapter,
 709         IN      u8                              *pFileName,
 710         RF_PATH                         eRFPath
 711 )
 712 {
 713         return _SUCCESS;
 714 }
 715
 716 /**************************************************************************************************************
 717  *   Description:
 718  *       The low-level interface to set TxAGC , called by both MP and Normal Driver.
 719  *
 720  *                                                                                    <20120830, Kordan>
 721  **************************************************************************************************************/
 722
 723 VOID
 724 PHY_SetTxPowerIndex_8723D(
 725         IN      PADAPTER                        Adapter,
 726         IN      u32                                     PowerIndex,
 727         IN      u8                                      RFPath,
 728         IN      u8                                      Rate
 729 )
 730 {
 731         if (RFPath == ODM_RF_PATH_A || RFPath == ODM_RF_PATH_B) {
 732                 switch (Rate) {
 733                 case MGN_1M:
 734                         PHY_SetBBReg(Adapter, rTxAGC_A_CCK1_Mcs32,      bMaskByte1, PowerIndex);
 735                         break;
 736                 case MGN_2M:
 737                         PHY_SetBBReg(Adapter, rTxAGC_B_CCK11_A_CCK2_11, bMaskByte1, PowerIndex);
 738                         break;
 739                 case MGN_5_5M:
 740                         PHY_SetBBReg(Adapter, rTxAGC_B_CCK11_A_CCK2_11, bMaskByte2, PowerIndex);
 741                         break;
 742                 case MGN_11M:
 743                         PHY_SetBBReg(Adapter, rTxAGC_B_CCK11_A_CCK2_11, bMaskByte3, PowerIndex);
 744                         break;
 745
 746                 case MGN_6M:
 747                         PHY_SetBBReg(Adapter, rTxAGC_A_Rate18_06, bMaskByte0, PowerIndex);
 748                         break;
 749                 case MGN_9M:
 750                         PHY_SetBBReg(Adapter, rTxAGC_A_Rate18_06, bMaskByte1, PowerIndex);
 751                         break;
 752                 case MGN_12M:
 753                         PHY_SetBBReg(Adapter, rTxAGC_A_Rate18_06, bMaskByte2, PowerIndex);
 754                         break;
 755                 case MGN_18M:
 756                         PHY_SetBBReg(Adapter, rTxAGC_A_Rate18_06, bMaskByte3, PowerIndex);
 757                         break;
 758
 759                 case MGN_24M:
 760                         PHY_SetBBReg(Adapter, rTxAGC_A_Rate54_24, bMaskByte0, PowerIndex);
 761                         break;
 762                 case MGN_36M:
 763                         PHY_SetBBReg(Adapter, rTxAGC_A_Rate54_24, bMaskByte1, PowerIndex);
 764                         break;
 765                 case MGN_48M:
 766                         PHY_SetBBReg(Adapter, rTxAGC_A_Rate54_24, bMaskByte2, PowerIndex);
 767                         break;
 768                 case MGN_54M:
 769                         PHY_SetBBReg(Adapter, rTxAGC_A_Rate54_24, bMaskByte3, PowerIndex);
 770                         break;
 771
 772                 case MGN_MCS0:
 773                         PHY_SetBBReg(Adapter, rTxAGC_A_Mcs03_Mcs00, bMaskByte0, PowerIndex);
 774                         break;
 775                 case MGN_MCS1:
 776                         PHY_SetBBReg(Adapter, rTxAGC_A_Mcs03_Mcs00, bMaskByte1, PowerIndex);
 777                         break;
 778                 case MGN_MCS2:
 779                         PHY_SetBBReg(Adapter, rTxAGC_A_Mcs03_Mcs00, bMaskByte2, PowerIndex);
 780                         break;
 781                 case MGN_MCS3:
 782                         PHY_SetBBReg(Adapter, rTxAGC_A_Mcs03_Mcs00, bMaskByte3, PowerIndex);
 783                         break;
 784
 785                 case MGN_MCS4:
 786                         PHY_SetBBReg(Adapter, rTxAGC_A_Mcs07_Mcs04, bMaskByte0, PowerIndex);
 787                         break;
 788                 case MGN_MCS5:
 789                         PHY_SetBBReg(Adapter, rTxAGC_A_Mcs07_Mcs04, bMaskByte1, PowerIndex);
 790                         break;
 791                 case MGN_MCS6:
 792                         PHY_SetBBReg(Adapter, rTxAGC_A_Mcs07_Mcs04, bMaskByte2, PowerIndex);
 793                         break;
 794                 case MGN_MCS7:
 795                         PHY_SetBBReg(Adapter, rTxAGC_A_Mcs07_Mcs04, bMaskByte3, PowerIndex);
 796                         break;
 797
 798                 default:
 799                         RTW_INFO("Invalid Rate!!\n");
 800                         break;
 801                 }
 802         }
 803 }
 804
 805 u8
 806 phy_GetCurrentTxNum_8723D(
 807         IN      PADAPTER                pAdapter
 808 )
 809 {
 810         return RF_TX_NUM_NONIMPLEMENT;
 811 }
 812
 813 u8
 814 PHY_GetTxPowerIndex_8723D(
 815         IN      PADAPTER                        pAdapter,
 816         IN      u8                                      RFPath,
 817         IN      u8                                      Rate,
 818         IN      u8                                      BandWidth,
 819         IN      u8                                      Channel,
 820         struct txpwr_idx_comp *tic
 821 )
 822 {
 823         PHAL_DATA_TYPE pHalData = GET_HAL_DATA(pAdapter);
 824         u8 base_idx = 0, power_idx = 0;
 825         s8 by_rate_diff = 0, limit = 0, tpt_offset = 0, extra_bias = 0;
 826         BOOLEAN bIn24G = _FALSE;
 827
 828         base_idx = PHY_GetTxPowerIndexBase(pAdapter, RFPath, Rate, BandWidth, Channel, &bIn24G);
 829
 830         by_rate_diff = PHY_GetTxPowerByRate(pAdapter, BAND_ON_2_4G, ODM_RF_PATH_A, RF_1TX, Rate);
 831         limit = PHY_GetTxPowerLimit(pAdapter, pAdapter->registrypriv.RegPwrTblSel, (u8)(!bIn24G), pHalData->CurrentChannelBW, RFPath, Rate, pHalData->CurrentChannel);
 832
 833         tpt_offset = PHY_GetTxPowerTrackingOffset(pAdapter, RFPath, Rate);
 834
 835         if (tic) {
 836                 tic->base = base_idx;
 837                 tic->by_rate = by_rate_diff;
 838                 tic->limit = limit;
 839                 tic->tpt = tpt_offset;
 840                 tic->ebias = extra_bias;
 841         }
 842
 843         by_rate_diff = by_rate_diff > limit ? limit : by_rate_diff;
 844         power_idx = base_idx + by_rate_diff + tpt_offset + extra_bias;
 845
 846         if (power_idx > MAX_POWER_INDEX)
 847                 power_idx = MAX_POWER_INDEX;
 848
 849         return power_idx;
 850 }
 851
 852 VOID
 853 PHY_SetTxPowerLevel8723D(
 854         IN      PADAPTER                Adapter,
 855         IN      u8                              Channel
 856 )
 857 {
 858         PHAL_DATA_TYPE  pHalData = GET_HAL_DATA(Adapter);
 859         u8                              cur_antenna;
 860         u8                              RFPath = ODM_RF_PATH_A;
 861
 862 #ifdef CONFIG_ANTENNA_DIVERSITY
 863         rtw_hal_get_odm_var(Adapter, HAL_ODM_ANTDIV_SELECT, &cur_antenna, NULL);
 864
 865         if (pHalData->AntDivCfg)  /* antenna diversity Enable */
 866                 RFPath = ((cur_antenna == MAIN_ANT) ? ODM_RF_PATH_A : ODM_RF_PATH_B);
 867         else   /* antenna diversity disable */
 868 #endif
 869                 RFPath = pHalData->ant_path;
 870
 871
 872
 873         PHY_SetTxPowerLevelByPath(Adapter, Channel, RFPath);
 874
 875 }
 876
 877 VOID
 878 PHY_GetTxPowerLevel8723D(
 879         IN      PADAPTER                Adapter,
 880         OUT s32                         *powerlevel
 881 )
 882 {
 883         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(Adapter);
 884         s32                             TxPwrDbm = 13;
 885 #if 0
 886
 887         if (pMgntInfo->ClientConfigPwrInDbm != UNSPECIFIED_PWR_DBM)
 888                 *powerlevel = pMgntInfo->ClientConfigPwrInDbm;
 889         else
 890                 *powerlevel = TxPwrDbm;
 891 #endif
 892 }
 893
 894
 895 /* <20160217, Jessica> A workaround to eliminate the 2472MHz & 2484MHz spur of 8723D. */
 896 VOID
 897 phy_SpurCalibration_8723D(
 898         IN      PADAPTER                                        pAdapter,
 899         IN      u1Byte                                          ToChannel,
 900         IN      u1Byte                                          threshold
 901 )
 902 {
 903         u4Byte          freq[2] = {0xFCCD, 0xFF9A}; /* {chnl 13, 14} */
 904         u1Byte          idx = 0xFF;
 905         u1Byte          b_doNotch = FALSE;
 906         u1Byte          initial_gain;
 907
 908         /* add for notch */
 909         u4Byte                          wlan_channel, CurrentChannel;
 910         HAL_DATA_TYPE           *pHalData       = GET_HAL_DATA(pAdapter);
 911         PDM_ODM_T               pDM_Odm = &(pHalData->odmpriv);
 912
 913         /* check threshold */
 914         if (threshold <= 0x0)
 915                 threshold = 0x16;
 916
 917         RTW_INFO("===>phy_SpurCalibration_8723D: Channel = %d\n", ToChannel);
 918
 919         if (ToChannel == 13)
 920                 idx = 0;
 921         else if (ToChannel == 14)
 922                 idx = 1;
 923
 924         /* If current channel=13,14 */
 925         if (idx < 0xFF) {
 926                 initial_gain = (u1Byte)(ODM_GetBBReg(pDM_Odm, rOFDM0_XAAGCCore1, bMaskByte0) & 0x7f);
 927                 odm_PauseDIG(pDM_Odm, PHYDM_PAUSE, PHYDM_PAUSE_LEVEL_1, 0x30);
 928                 PHY_SetBBReg(pAdapter, rFPGA0_AnalogParameter4, bMaskDWord, 0xccf000c0);                /* disable 3-wire */
 929
 930                 PHY_SetBBReg(pAdapter, rFPGA0_PSDFunction, bMaskDWord, freq[idx]);                              /* Setup PSD */
 931                 PHY_SetBBReg(pAdapter, rFPGA0_PSDFunction, bMaskDWord, 0x400000 | freq[idx]); /* Start PSD       */
 932
 933                 rtw_msleep_os(30);
 934
 935                 if (PHY_QueryBBReg(pAdapter, rFPGA0_PSDReport, bMaskDWord) >= threshold)
 936                         b_doNotch = TRUE;
 937
 938                 PHY_SetBBReg(pAdapter, rFPGA0_PSDFunction, bMaskDWord, freq[idx]); /* turn off PSD */
 939                 PHY_SetBBReg(pAdapter, rFPGA0_AnalogParameter4, bMaskDWord, 0xccc000c0);        /* enable 3-wire */
 940                 odm_PauseDIG(pDM_Odm, PHYDM_RESUME, PHYDM_PAUSE_LEVEL_1, NONE);
 941         }
 942
 943         /* --- Notch Filter --- Asked by Rock    */
 944         if (b_doNotch) {
 945                 CurrentChannel = ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_CHNLBW, bRFRegOffsetMask);
 946                 wlan_channel   = CurrentChannel & 0x0f;                                             /* Get center frequency */
 947
 948                 switch (wlan_channel) {                                                                                 /* Set notch filter                              */
 949                 case 13:
 950                         ODM_SetBBReg(pDM_Odm, 0xC40, BIT(28) | BIT(27) | BIT(26) | BIT(25) | BIT(24), 0xB);
 951                         ODM_SetBBReg(pDM_Odm, 0xC40, BIT(9), 0x1);                    /* enable notch filter */
 952                         ODM_SetBBReg(pDM_Odm, 0xD40, bMaskDWord, 0x04000000);
 953                         ODM_SetBBReg(pDM_Odm, 0xD44, bMaskDWord, 0x00000000);
 954                         ODM_SetBBReg(pDM_Odm, 0xD48, bMaskDWord, 0x00000000);
 955                         ODM_SetBBReg(pDM_Odm, 0xD4C, bMaskDWord, 0x00000000);
 956                         ODM_SetBBReg(pDM_Odm, 0xD2C, BIT(28), 0x1);                   /* enable CSI mask */
 957                         break;
 958                 case 14:
 959                         ODM_SetBBReg(pDM_Odm, 0xC40, BIT(28) | BIT(27) | BIT(26) | BIT(25) | BIT(24), 0x5);
 960                         ODM_SetBBReg(pDM_Odm, 0xC40, BIT(9), 0x1);                   /* enable notch filter */
 961                         ODM_SetBBReg(pDM_Odm, 0xD40, bMaskDWord, 0x00000000);
 962                         ODM_SetBBReg(pDM_Odm, 0xD44, bMaskDWord, 0x00000000);
 963                         ODM_SetBBReg(pDM_Odm, 0xD48, bMaskDWord, 0x00000000);
 964                         ODM_SetBBReg(pDM_Odm, 0xD4C, bMaskDWord, 0x00080000);
 965                         ODM_SetBBReg(pDM_Odm, 0xD2C, BIT(28), 0x1);                   /* enable CSI mask */
 966                         break;
 967                 default:
 968                         ODM_SetBBReg(pDM_Odm, 0xC40, BIT(9), 0x0);                                              /* disable notch filter */
 969                         ODM_SetBBReg(pDM_Odm, 0xD2C, BIT(28), 0x0);                   /* disable CSI mask       function */
 970                         break;
 971                 } /* switch(wlan_channel)        */
 972                 return;
 973         }
 974
 975         ODM_SetBBReg(pDM_Odm, 0xC40, BIT(28) | BIT(27) | BIT(26) | BIT(25) | BIT(24), 0x1f);
 976         ODM_SetBBReg(pDM_Odm, 0xC40, BIT(9), 0x0);                     /* disable notch filter */
 977         ODM_SetBBReg(pDM_Odm, 0xD40, bMaskDWord, 0x00000000);
 978         ODM_SetBBReg(pDM_Odm, 0xD44, bMaskDWord, 0x00000000);
 979         ODM_SetBBReg(pDM_Odm, 0xD48, bMaskDWord, 0x00000000);
 980         ODM_SetBBReg(pDM_Odm, 0xD4C, bMaskDWord, 0x00000000);
 981         ODM_SetBBReg(pDM_Odm, 0xD2C, BIT(28), 0x0);                    /* disable CSI mask */
 982 }
 983
 984 VOID
 985 phy_SetRegBW_8723D(
 986         IN      PADAPTER                Adapter,
 987         CHANNEL_WIDTH   CurrentBW
 988 )
 989 {
 990         u16     RegRfMod_BW, u2tmp = 0;
 991
 992         RegRfMod_BW = rtw_read16(Adapter, REG_TRXPTCL_CTL_8723D);
 993
 994         switch (CurrentBW) {
 995         case CHANNEL_WIDTH_20:
 996                 rtw_write16(Adapter, REG_TRXPTCL_CTL_8723D, (RegRfMod_BW & 0xFE7F)); /* BIT 7 = 0, BIT 8 = 0 */
 997                 break;
 998
 999         case CHANNEL_WIDTH_40:
1000                 u2tmp = RegRfMod_BW | BIT(7);
1001                 rtw_write16(Adapter, REG_TRXPTCL_CTL_8723D, (u2tmp & 0xFEFF)); /* BIT 7 = 1, BIT 8 = 0 */
1002                 break;
1003
1004         case CHANNEL_WIDTH_80:
1005                 u2tmp = RegRfMod_BW | BIT(8);
1006                 rtw_write16(Adapter, REG_TRXPTCL_CTL_8723D, (u2tmp & 0xFF7F)); /* BIT 7 = 0, BIT 8 = 1 */
1007                 break;
1008
1009         default:
1010                 RTW_INFO("phy_PostSetBWMode8723D():     unknown Bandwidth: %#X\n", CurrentBW);
1011                 break;
1012         }
1013 }
1014
1015 u8
1016 phy_GetSecondaryChnl_8723D(
1017         IN      PADAPTER        Adapter
1018 )
1019 {
1020         u8      SCSettingOf40 = 0, SCSettingOf20 = 0;
1021         PHAL_DATA_TYPE  pHalData = GET_HAL_DATA(Adapter);
1022
1023         if (pHalData->CurrentChannelBW == CHANNEL_WIDTH_80) {
1024                 if (pHalData->nCur80MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_LOWER)
1025                         SCSettingOf40 = VHT_DATA_SC_40_LOWER_OF_80MHZ;
1026                 else if (pHalData->nCur80MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_UPPER)
1027                         SCSettingOf40 = VHT_DATA_SC_40_UPPER_OF_80MHZ;
1028
1029
1030                 if ((pHalData->nCur40MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_LOWER) && (pHalData->nCur80MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_LOWER))
1031                         SCSettingOf20 = VHT_DATA_SC_20_LOWEST_OF_80MHZ;
1032                 else if ((pHalData->nCur40MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_UPPER) && (pHalData->nCur80MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_LOWER))
1033                         SCSettingOf20 = VHT_DATA_SC_20_LOWER_OF_80MHZ;
1034                 else if ((pHalData->nCur40MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_LOWER) && (pHalData->nCur80MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_UPPER))
1035                         SCSettingOf20 = VHT_DATA_SC_20_UPPER_OF_80MHZ;
1036                 else if ((pHalData->nCur40MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_UPPER) && (pHalData->nCur80MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_UPPER))
1037                         SCSettingOf20 = VHT_DATA_SC_20_UPPERST_OF_80MHZ;
1038
1039         } else if (pHalData->CurrentChannelBW == CHANNEL_WIDTH_40) {
1040
1041                 if (pHalData->nCur40MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_UPPER)
1042                         SCSettingOf20 = VHT_DATA_SC_20_UPPER_OF_80MHZ;
1043                 else if (pHalData->nCur40MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_LOWER)
1044                         SCSettingOf20 = VHT_DATA_SC_20_LOWER_OF_80MHZ;
1045
1046         }
1047
1048         return (SCSettingOf40 << 4) | SCSettingOf20;
1049 }
1050
1051 void
1052 phy_PostSetBwMode8723D(
1053         IN PADAPTER padapter
1054 )
1055 {
1056         u1Byte SubChnlNum = 0;
1057         HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
1058
1059         /* 2 Set Reg668 Reg440 BW */
1060         phy_SetRegBW_8723D(padapter, pHalData->CurrentChannelBW);
1061
1062         /* 3 Set Reg483 */
1063         SubChnlNum = phy_GetSecondaryChnl_8723D(padapter);
1064         rtw_write8(padapter, REG_DATA_SC_8723D, SubChnlNum);
1065
1066         switch (pHalData->CurrentChannelBW) {
1067         /* 20 MHz channel*/
1068         case CHANNEL_WIDTH_20:
1069                 /*
1070                 0x800[0]=1'b0
1071                 0x900[0]=1'b0
1072                 0x954[19]=1'b1
1073                 0x954[27:24]= 10
1074                 */
1075                 PHY_SetBBReg(padapter, rFPGA0_RFMOD, bRFMOD, 0x0);
1076                 PHY_SetBBReg(padapter, rFPGA1_RFMOD, bRFMOD, 0x0);
1077                 PHY_SetBBReg(padapter, rBBrx_DFIR, BIT(19), 1);
1078                 PHY_SetBBReg(padapter, rBBrx_DFIR,
1079                              (BIT(27) | BIT(26) | BIT(25) | BIT(24)), 0xa);
1080                 break;
1081         /* 40 MHz channel*/
1082         case CHANNEL_WIDTH_40:
1083                 /*
1084                 0x800[0]=1'b1
1085                 0x900[0]=1'b1
1086                 0x954[19]=1'b0
1087                 0x954[23:20]=2'b11(For ACPR)
1088                 0xa00[4]=1/0
1089                 */
1090                 PHY_SetBBReg(padapter, rFPGA0_RFMOD, bRFMOD, 0x1);
1091                 PHY_SetBBReg(padapter, rFPGA1_RFMOD, bRFMOD, 0x1);
1092                 PHY_SetBBReg(padapter, rBBrx_DFIR, BIT(19), 0);
1093                 PHY_SetBBReg(padapter, rCCK0_System, bCCKSideBand,
1094                              (pHalData->nCur40MhzPrimeSC >> 1));
1095
1096                 break;
1097         default:
1098                 break;
1099         }
1100
1101         /*3<3>Set RF related register */
1102         PHY_RF6052SetBandwidth8723D(padapter, pHalData->CurrentChannelBW);
1103 }
1104
1105 VOID
1106 phy_SwChnl8723D(
1107         IN      PADAPTER                                        pAdapter
1108 )
1109 {
1110         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(pAdapter);
1111         u8              channelToSW = pHalData->CurrentChannel;
1112         u8              i = 0;
1113
1114         if (pHalData->rf_chip == RF_PSEUDO_11N) {
1115                 RTW_INFO("phy_SwChnl8723D: return for PSEUDO\n");
1116                 return;
1117         }
1118
1119         pHalData->RfRegChnlVal[0] =
1120                 ((pHalData->RfRegChnlVal[0] & 0xfffff00) | channelToSW);
1121         PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, RF_CHNLBW,
1122                      0x3FF, pHalData->RfRegChnlVal[0]);
1123         PHY_SetRFReg(pAdapter, ODM_RF_PATH_B, RF_CHNLBW,
1124                      0x3FF, pHalData->RfRegChnlVal[0]);
1125
1126         phy_SpurCalibration_8723D(pAdapter, channelToSW, 0x16);
1127
1128         /* 2.4G CCK TX DFIR */
1129         /* 2016.01.20 Suggest from RS BB mingzhi*/
1130         if (channelToSW >= 1 && channelToSW <= 13) {
1131                 if (pHalData->need_restore == _TRUE) {
1132                         for (i = 0 ; i < 3 ; i++) {
1133                                 PHY_SetBBReg(pAdapter,
1134                                              pHalData->RegForRecover[i].offset,
1135                                              bMaskDWord,
1136                                              pHalData->RegForRecover[i].value);
1137                         }
1138                         pHalData->need_restore = _FALSE;
1139                 }
1140         } else if (channelToSW == 14) {
1141                 pHalData->need_restore = _TRUE;
1142                 PHY_SetBBReg(pAdapter, rCCK0_TxFilter2, bMaskDWord, 0x0000B81C);
1143                 PHY_SetBBReg(pAdapter, rCCK0_DebugPort, bMaskDWord, 0x00000000);
1144                 PHY_SetBBReg(pAdapter, 0xAAC, bMaskDWord, 0x00003667);
1145         }
1146
1147         RTW_INFO("===>phy_SwChnl8723D: Channel = %d\n", channelToSW);
1148 }
1149
1150 VOID
1151 phy_SwChnlAndSetBwMode8723D(
1152         IN  PADAPTER            Adapter
1153 )
1154 {
1155         HAL_DATA_TYPE           *pHalData = GET_HAL_DATA(Adapter);
1156
1157         if (Adapter->bNotifyChannelChange) {
1158                 RTW_INFO("[%s] bSwChnl=%d, ch=%d, bSetChnlBW=%d, bw=%d\n",
1159                          __func__,
1160                          pHalData->bSwChnl,
1161                          pHalData->CurrentChannel,
1162                          pHalData->bSetChnlBW,
1163                          pHalData->CurrentChannelBW);
1164         }
1165
1166         if (RTW_CANNOT_RUN(Adapter))
1167                 return;
1168
1169         if (pHalData->bSwChnl) {
1170                 phy_SwChnl8723D(Adapter);
1171                 pHalData->bSwChnl = _FALSE;
1172         }
1173
1174         if (pHalData->bSetChnlBW) {
1175                 phy_PostSetBwMode8723D(Adapter);
1176                 pHalData->bSetChnlBW = _FALSE;
1177         }
1178
1179         PHY_SetTxPowerLevel8723D(Adapter, pHalData->CurrentChannel);
1180 }
1181
1182 VOID
1183 PHY_HandleSwChnlAndSetBW8723D(
1184         IN      PADAPTER                        Adapter,
1185         IN      BOOLEAN                         bSwitchChannel,
1186         IN      BOOLEAN                         bSetBandWidth,
1187         IN      u8                                      ChannelNum,
1188         IN      CHANNEL_WIDTH   ChnlWidth,
1189         IN      EXTCHNL_OFFSET  ExtChnlOffsetOf40MHz,
1190         IN      EXTCHNL_OFFSET  ExtChnlOffsetOf80MHz,
1191         IN      u8                                      CenterFrequencyIndex1
1192 )
1193 {
1194         /* static BOOLEAN               bInitialzed = _FALSE; */
1195         PHAL_DATA_TYPE          pHalData = GET_HAL_DATA(Adapter);
1196         u8                                      tmpChannel = pHalData->CurrentChannel;
1197         CHANNEL_WIDTH   tmpBW = pHalData->CurrentChannelBW;
1198         u8                                      tmpnCur40MhzPrimeSC = pHalData->nCur40MhzPrimeSC;
1199         u8                                      tmpnCur80MhzPrimeSC = pHalData->nCur80MhzPrimeSC;
1200         u8                                      tmpCenterFrequencyIndex1 = pHalData->CurrentCenterFrequencyIndex1;
1201         struct mlme_ext_priv    *pmlmeext = &Adapter->mlmeextpriv;
1202
1203         /* RTW_INFO("=> PHY_HandleSwChnlAndSetBW8812: bSwitchChannel %d, bSetBandWidth %d\n",bSwitchChannel,bSetBandWidth); */
1204
1205         /* check is swchnl or setbw */
1206         if (!bSwitchChannel && !bSetBandWidth) {
1207                 RTW_INFO("PHY_HandleSwChnlAndSetBW8812:  not switch channel and not set bandwidth\n");
1208                 return;
1209         }
1210
1211         /* skip change for channel or bandwidth is the same */
1212         if (bSwitchChannel) {
1213                 /* if(pHalData->CurrentChannel != ChannelNum) */
1214                 {
1215                         if (HAL_IsLegalChannel(Adapter, ChannelNum))
1216                                 pHalData->bSwChnl = _TRUE;
1217                 }
1218         }
1219
1220         if (bSetBandWidth) {
1221 #if 0
1222                 if (bInitialzed == _FALSE) {
1223                         bInitialzed = _TRUE;
1224                         pHalData->bSetChnlBW = _TRUE;
1225                 } else if ((pHalData->CurrentChannelBW != ChnlWidth) || (pHalData->nCur40MhzPrimeSC != ExtChnlOffsetOf40MHz) || (pHalData->CurrentCenterFrequencyIndex1 != CenterFrequencyIndex1))
1226                         pHalData->bSetChnlBW = _TRUE;
1227 #else
1228                 pHalData->bSetChnlBW = _TRUE;
1229 #endif
1230         }
1231
1232         if (!pHalData->bSetChnlBW && !pHalData->bSwChnl) {
1233                 /* RTW_INFO("<= PHY_HandleSwChnlAndSetBW8812: bSwChnl %d, bSetChnlBW %d\n",pHalData->bSwChnl,pHalData->bSetChnlBW); */
1234                 return;
1235         }
1236
1237
1238         if (pHalData->bSwChnl) {
1239                 pHalData->CurrentChannel = ChannelNum;
1240                 pHalData->CurrentCenterFrequencyIndex1 = ChannelNum;
1241         }
1242
1243
1244         if (pHalData->bSetChnlBW) {
1245                 pHalData->CurrentChannelBW = ChnlWidth;
1246 #if 0
1247                 if (ExtChnlOffsetOf40MHz == EXTCHNL_OFFSET_LOWER)
1248                         pHalData->nCur40MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_UPPER;
1249                 else if (ExtChnlOffsetOf40MHz == EXTCHNL_OFFSET_UPPER)
1250                         pHalData->nCur40MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_LOWER;
1251                 else
1252                         pHalData->nCur40MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
1253
1254                 if (ExtChnlOffsetOf80MHz == EXTCHNL_OFFSET_LOWER)
1255                         pHalData->nCur80MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_UPPER;
1256                 else if (ExtChnlOffsetOf80MHz == EXTCHNL_OFFSET_UPPER)
1257                         pHalData->nCur80MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_LOWER;
1258                 else
1259                         pHalData->nCur80MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
1260 #else
1261                 pHalData->nCur40MhzPrimeSC = ExtChnlOffsetOf40MHz;
1262                 pHalData->nCur80MhzPrimeSC = ExtChnlOffsetOf80MHz;
1263 #endif
1264
1265                 pHalData->CurrentCenterFrequencyIndex1 = CenterFrequencyIndex1;
1266         }
1267
1268         /* Switch workitem or set timer to do switch channel or setbandwidth operation */
1269         if (!RTW_CANNOT_RUN(Adapter))
1270                 phy_SwChnlAndSetBwMode8723D(Adapter);
1271         else {
1272                 if (pHalData->bSwChnl) {
1273                         pHalData->CurrentChannel = tmpChannel;
1274                         pHalData->CurrentCenterFrequencyIndex1 = tmpChannel;
1275                 }
1276                 if (pHalData->bSetChnlBW) {
1277                         pHalData->CurrentChannelBW = tmpBW;
1278                         pHalData->nCur40MhzPrimeSC = tmpnCur40MhzPrimeSC;
1279                         pHalData->nCur80MhzPrimeSC = tmpnCur80MhzPrimeSC;
1280                         pHalData->CurrentCenterFrequencyIndex1 = tmpCenterFrequencyIndex1;
1281                 }
1282         }
1283
1284         /* RTW_INFO("Channel %d ChannelBW %d ",pHalData->CurrentChannel, pHalData->CurrentChannelBW); */
1285         /* RTW_INFO("40MhzPrimeSC %d 80MhzPrimeSC %d ",pHalData->nCur40MhzPrimeSC, pHalData->nCur80MhzPrimeSC); */
1286         /* RTW_INFO("CenterFrequencyIndex1 %d\n",pHalData->CurrentCenterFrequencyIndex1); */
1287
1288         /* RTW_INFO("<= PHY_HandleSwChnlAndSetBW8812: bSwChnl %d, bSetChnlBW %d\n",pHalData->bSwChnl,pHalData->bSetChnlBW); */
1289
1290 }
1291
1292 VOID
1293 PHY_SetSwChnlBWMode8723D(
1294         IN      PADAPTER                        Adapter,
1295         IN      u8                                      channel,
1296         IN      CHANNEL_WIDTH   Bandwidth,
1297         IN      u8                                      Offset40,
1298         IN      u8                                      Offset80
1299 )
1300 {
1301         /* RTW_INFO("%s()===>\n",__FUNCTION__); */
1302
1303         PHY_HandleSwChnlAndSetBW8723D(Adapter, _TRUE, _TRUE, channel, Bandwidth, Offset40, Offset80, channel);
1304
1305         /* RTW_INFO("<==%s()\n",__FUNCTION__); */
1306 }
1307
1308 static VOID
1309 _PHY_DumpRFReg_8723D(IN PADAPTER        pAdapter)
1310 {
1311         u32 rfRegValue, rfRegOffset;
1312
1313
1314         for (rfRegOffset = 0x00; rfRegOffset <= 0x30; rfRegOffset++) {
1315                 rfRegValue = PHY_QueryRFReg_8723D(pAdapter, RF_PATH_A, rfRegOffset, bMaskDWord);
1316         }
1317 }