drivers/net/wireless/rockchip_wlan/rtl8723ds/include/hal_data.h

   1 /******************************************************************************
   2  *
   3  * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of version 2 of the GNU General Public License as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program; if not, write to the Free Software Foundation, Inc.,
  16  * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  17  *
  18  *
  19  ******************************************************************************/
  20 #ifndef __HAL_DATA_H__
  21 #define __HAL_DATA_H__
  22
  23 #if 1/* def  CONFIG_SINGLE_IMG */
  24
  25 #include "../hal/phydm/phydm_precomp.h"
  26 #ifdef CONFIG_BT_COEXIST
  27         #include <hal_btcoex.h>
  28 #endif
  29
  30 #ifdef CONFIG_SDIO_HCI
  31         #include <hal_sdio.h>
  32 #endif
  33 #ifdef CONFIG_GSPI_HCI
  34         #include <hal_gspi.h>
  35 #endif
  36 /*
  37  * <Roger_Notes> For RTL8723 WiFi/BT/GPS multi-function configuration. 2010.10.06.
  38  *   */
  39 typedef enum _RT_MULTI_FUNC {
  40         RT_MULTI_FUNC_NONE      = 0x00,
  41         RT_MULTI_FUNC_WIFI      = 0x01,
  42         RT_MULTI_FUNC_BT                = 0x02,
  43         RT_MULTI_FUNC_GPS       = 0x04,
  44 } RT_MULTI_FUNC, *PRT_MULTI_FUNC;
  45 /*
  46  * <Roger_Notes> For RTL8723 WiFi PDn/GPIO polarity control configuration. 2010.10.08.
  47  *   */
  48 typedef enum _RT_POLARITY_CTL {
  49         RT_POLARITY_LOW_ACT     = 0,
  50         RT_POLARITY_HIGH_ACT    = 1,
  51 } RT_POLARITY_CTL, *PRT_POLARITY_CTL;
  52
  53 /* For RTL8723 regulator mode. by tynli. 2011.01.14. */
  54 typedef enum _RT_REGULATOR_MODE {
  55         RT_SWITCHING_REGULATOR  = 0,
  56         RT_LDO_REGULATOR                        = 1,
  57 } RT_REGULATOR_MODE, *PRT_REGULATOR_MODE;
  58
  59 /*
  60  * Interface type.
  61  *   */
  62 typedef enum _INTERFACE_SELECT_PCIE {
  63         INTF_SEL0_SOLO_MINICARD                 = 0,            /* WiFi solo-mCard */
  64         INTF_SEL1_BT_COMBO_MINICARD             = 1,            /* WiFi+BT combo-mCard */
  65         INTF_SEL2_PCIe                                          = 2,            /* PCIe Card */
  66 } INTERFACE_SELECT_PCIE, *PINTERFACE_SELECT_PCIE;
  67
  68
  69 typedef enum _INTERFACE_SELECT_USB {
  70         INTF_SEL0_USB                           = 0,            /* USB */
  71         INTF_SEL1_USB_High_Power        = 1,            /* USB with high power PA */
  72         INTF_SEL2_MINICARD                      = 2,            /* Minicard */
  73         INTF_SEL3_USB_Solo              = 3,            /* USB solo-Slim module */
  74         INTF_SEL4_USB_Combo             = 4,            /* USB Combo-Slim module */
  75         INTF_SEL5_USB_Combo_MF  = 5,            /* USB WiFi+BT Multi-Function Combo, i.e., Proprietary layout(AS-VAU) which is the same as SDIO card */
  76 } INTERFACE_SELECT_USB, *PINTERFACE_SELECT_USB;
  77
  78 typedef enum _RT_AMPDU_BRUST_MODE {
  79         RT_AMPDU_BRUST_NONE             = 0,
  80         RT_AMPDU_BRUST_92D              = 1,
  81         RT_AMPDU_BRUST_88E              = 2,
  82         RT_AMPDU_BRUST_8812_4   = 3,
  83         RT_AMPDU_BRUST_8812_8   = 4,
  84         RT_AMPDU_BRUST_8812_12  = 5,
  85         RT_AMPDU_BRUST_8812_15  = 6,
  86         RT_AMPDU_BRUST_8723B            = 7,
  87 } RT_AMPDU_BRUST, *PRT_AMPDU_BRUST_MODE;
  88
  89 /* Tx Power Limit Table Size */
  90 #define MAX_REGULATION_NUM                                              4
  91 #define MAX_RF_PATH_NUM_IN_POWER_LIMIT_TABLE    4
  92 #define MAX_2_4G_BANDWIDTH_NUM                                  2
  93 #define MAX_RATE_SECTION_NUM                                            10
  94 #define MAX_5G_BANDWIDTH_NUM                                            4
  95
  96 #define MAX_BASE_NUM_IN_PHY_REG_PG_2_4G                 10 /* CCK:1, OFDM:1, HT:4, VHT:4 */
  97 #define MAX_BASE_NUM_IN_PHY_REG_PG_5G                   9 /* OFDM:1, HT:4, VHT:4 */
  98
  99
 100 /* ###### duplicate code,will move to ODM ######### */
 101 /* #define IQK_MAC_REG_NUM              4 */
 102 /* #define IQK_ADDA_REG_NUM             16 */
 103
 104 /* #define IQK_BB_REG_NUM                       10 */
 105 #define IQK_BB_REG_NUM_92C      9
 106 #define IQK_BB_REG_NUM_92D      10
 107 #define IQK_BB_REG_NUM_test     6
 108
 109 #define IQK_Matrix_Settings_NUM_92D     (1+24+21)
 110
 111 /* #define HP_THERMAL_NUM               8 */
 112 /* ###### duplicate code,will move to ODM ######### */
 113
 114 #ifdef RTW_RX_AGGREGATION
 115 typedef enum _RX_AGG_MODE {
 116         RX_AGG_DISABLE,
 117         RX_AGG_DMA,
 118         RX_AGG_USB,
 119         RX_AGG_MIX
 120 } RX_AGG_MODE;
 121
 122 /* #define MAX_RX_DMA_BUFFER_SIZE       10240 */                /* 10K for 8192C RX DMA buffer */
 123
 124 #endif /* RTW_RX_AGGREGATION */
 125
 126 /* E-Fuse */
 127 #ifdef CONFIG_RTL8188E
 128         #define EFUSE_MAP_SIZE  512
 129 #endif
 130 #if defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A) || defined(CONFIG_RTL8814A)
 131         #define EFUSE_MAP_SIZE  512
 132 #endif
 133 #ifdef CONFIG_RTL8192E
 134         #define EFUSE_MAP_SIZE  512
 135 #endif
 136 #ifdef CONFIG_RTL8723B
 137         #define EFUSE_MAP_SIZE  512
 138 #endif
 139 #ifdef CONFIG_RTL8814A
 140         #define EFUSE_MAP_SIZE  512
 141 #endif
 142 #ifdef CONFIG_RTL8703B
 143         #define EFUSE_MAP_SIZE  512
 144 #endif
 145 #ifdef CONFIG_RTL8723D
 146         #define EFUSE_MAP_SIZE  512
 147 #endif
 148 #ifdef CONFIG_RTL8188F
 149         #define EFUSE_MAP_SIZE  512
 150 #endif
 151
 152 #if defined(CONFIG_RTL8814A) || defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8821C)
 153         #define EFUSE_MAX_SIZE  1024
 154 #elif defined(CONFIG_RTL8188E) || defined(CONFIG_RTL8188F) || defined(CONFIG_RTL8703B)
 155         #define EFUSE_MAX_SIZE  256
 156 #else
 157         #define EFUSE_MAX_SIZE  512
 158 #endif
 159 /* end of E-Fuse */
 160
 161 #define Mac_OFDM_OK                     0x00000000
 162 #define Mac_OFDM_Fail           0x10000000
 163 #define Mac_OFDM_FasleAlarm     0x20000000
 164 #define Mac_CCK_OK                      0x30000000
 165 #define Mac_CCK_Fail            0x40000000
 166 #define Mac_CCK_FasleAlarm      0x50000000
 167 #define Mac_HT_OK                       0x60000000
 168 #define Mac_HT_Fail                     0x70000000
 169 #define Mac_HT_FasleAlarm       0x90000000
 170 #define Mac_DropPacket          0xA0000000
 171
 172 #ifdef CONFIG_RF_POWER_TRIM
 173 #if defined(CONFIG_RTL8723B)
 174         #define REG_RF_BB_GAIN_OFFSET   0x7f
 175         #define RF_GAIN_OFFSET_MASK             0xfffff
 176 #elif defined(CONFIG_RTL8188E)
 177         #define REG_RF_BB_GAIN_OFFSET   0x55
 178         #define RF_GAIN_OFFSET_MASK             0xfffff
 179 #else
 180         #define REG_RF_BB_GAIN_OFFSET   0x55
 181         #define RF_GAIN_OFFSET_MASK             0xfffff
 182 #endif /* CONFIG_RTL8723B */
 183 #endif /*CONFIG_RF_POWER_TRIM*/
 184
 185 /* For store initial value of BB register */
 186 typedef struct _BB_INIT_REGISTER {
 187         u16     offset;
 188         u32     value;
 189
 190 } BB_INIT_REGISTER, *PBB_INIT_REGISTER;
 191
 192 #define PAGE_SIZE_128   128
 193 #define PAGE_SIZE_256   256
 194 #define PAGE_SIZE_512   512
 195
 196 #define HCI_SUS_ENTER           0
 197 #define HCI_SUS_LEAVING         1
 198 #define HCI_SUS_LEAVE           2
 199 #define HCI_SUS_ENTERING        3
 200 #define HCI_SUS_ERR                     4
 201
 202 #ifdef CONFIG_AUTO_CHNL_SEL_NHM
 203 typedef enum _ACS_OP {
 204         ACS_INIT,               /*ACS - Variable init*/
 205         ACS_RESET,              /*ACS - NHM Counter reset*/
 206         ACS_SELECT,             /*ACS - NHM Counter Statistics */
 207 } ACS_OP;
 208
 209 typedef enum _ACS_STATE {
 210         ACS_DISABLE,
 211         ACS_ENABLE,
 212 } ACS_STATE;
 213
 214 struct auto_chan_sel {
 215         ATOMIC_T state;
 216         u8      ch; /* previous channel*/
 217 };
 218 #endif /*CONFIG_AUTO_CHNL_SEL_NHM*/
 219
 220 #define EFUSE_FILE_UNUSED 0
 221 #define EFUSE_FILE_FAILED 1
 222 #define EFUSE_FILE_LOADED 2
 223
 224 #define MACADDR_FILE_UNUSED 0
 225 #define MACADDR_FILE_FAILED 1
 226 #define MACADDR_FILE_LOADED 2
 227
 228 #define KFREE_FLAG_ON                           BIT0
 229 #define KFREE_FLAG_THERMAL_K_ON         BIT1
 230
 231 #define MAX_IQK_INFO_BACKUP_CHNL_NUM    5
 232 #define MAX_IQK_INFO_BACKUP_REG_NUM             10
 233
 234 struct kfree_data_t {
 235         u8 flag;
 236         s8 bb_gain[BB_GAIN_NUM][RF_PATH_MAX];
 237
 238 #ifdef CONFIG_IEEE80211_BAND_5GHZ
 239         s8 pa_bias_5g[RF_PATH_MAX];
 240         s8 pad_bias_5g[RF_PATH_MAX];
 241 #endif
 242         s8 thermal;
 243 };
 244
 245 bool kfree_data_is_bb_gain_empty(struct kfree_data_t *data);
 246
 247 struct hal_spec_t {
 248         char *ic_name;
 249         u8 macid_num;
 250
 251         u8 sec_cam_ent_num;
 252         u8 sec_cap;
 253
 254         u8 rfpath_num_2g:4;     /* used for tx power index path */
 255         u8 rfpath_num_5g:4;     /* used for tx power index path */
 256
 257         u8 max_tx_cnt;
 258         u8 nss_num;
 259         u8 band_cap;    /* value of BAND_CAP_XXX */
 260         u8 bw_cap;              /* value of BW_CAP_XXX */
 261         u8 port_num;
 262         u8 proto_cap;   /* value of PROTO_CAP_XXX */
 263         u8 wl_func;             /* value of WL_FUNC_XXX */
 264 };
 265
 266 #define HAL_SPEC_CHK_RF_PATH_2G(_spec, _path) ((_spec)->rfpath_num_2g > (_path))
 267 #define HAL_SPEC_CHK_RF_PATH_5G(_spec, _path) ((_spec)->rfpath_num_5g > (_path))
 268 #define HAL_SPEC_CHK_RF_PATH(_spec, _band, _path) ( \
 269         _band == BAND_ON_2_4G ? HAL_SPEC_CHK_RF_PATH_2G(_spec, _path) : \
 270         _band == BAND_ON_5G ? HAL_SPEC_CHK_RF_PATH_5G(_spec, _path) : 0)
 271
 272 #define HAL_SPEC_CHK_TX_CNT(_spec, _cnt_idx) ((_spec)->max_tx_cnt > (_cnt_idx))
 273
 274 struct hal_iqk_reg_backup {
 275         u8 central_chnl;
 276         u8 bw_mode;
 277         u32 reg_backup[MAX_RF_PATH][MAX_IQK_INFO_BACKUP_REG_NUM];
 278 };
 279
 280 typedef struct hal_com_data {
 281         HAL_VERSION                     VersionID;
 282         RT_MULTI_FUNC           MultiFunc; /* For multi-function consideration. */
 283         RT_POLARITY_CTL         PolarityCtl; /* For Wifi PDn Polarity control. */
 284         RT_REGULATOR_MODE       RegulatorMode; /* switching regulator or LDO */
 285         u8      hw_init_completed;
 286         /****** FW related ******/
 287         u16     FirmwareVersion;
 288         u16     FirmwareVersionRev;
 289         u16     FirmwareSubVersion;
 290         u16     FirmwareSignature;
 291         u8      RegFWOffload;
 292         u8      fw_ractrl;
 293         u8      FwRsvdPageStartOffset; /* 2010.06.23. Added by tynli. Reserve page start offset except beacon in TxQ.*/
 294         u8      LastHMEBoxNum;  /* H2C - for host message to fw */
 295
 296         /****** current WIFI_PHY values ******/
 297         WIRELESS_MODE   CurrentWirelessMode;
 298         CHANNEL_WIDTH   CurrentChannelBW;
 299         BAND_TYPE               CurrentBandType;        /* 0:2.4G, 1:5G */
 300         BAND_TYPE               BandSet;
 301         u8                              CurrentChannel;
 302         u8                              cch_20;
 303         u8                              cch_40;
 304         u8                              cch_80;
 305         u8                              CurrentCenterFrequencyIndex1;
 306         u8                              nCur40MhzPrimeSC;       /* Control channel sub-carrier */
 307         u8                              nCur80MhzPrimeSC;   /* used for primary 40MHz of 80MHz mode */
 308         BOOLEAN         bSwChnlAndSetBWInProgress;
 309         u8                              bDisableSWChannelPlan; /* flag of disable software change channel plan   */
 310         u16                             BasicRateSet;
 311         u32                             ReceiveConfig;
 312         u8                              rx_tsf_addr_filter_config; /* for 8822B/8821C USE */
 313         BOOLEAN                 bSwChnl;
 314         BOOLEAN                 bSetChnlBW;
 315         BOOLEAN                 bSWToBW40M;
 316         BOOLEAN                 bSWToBW80M;
 317         BOOLEAN                 bChnlBWInitialized;
 318         u32                             BackUp_BB_REG_4_2nd_CCA[3];
 319 #ifdef CONFIG_AUTO_CHNL_SEL_NHM
 320         struct auto_chan_sel acs;
 321 #endif
 322         /****** rf_ctrl *****/
 323         u8      rf_chip;
 324         u8      rf_type;
 325         u8      PackageType;
 326         u8      NumTotalRFPath;
 327
 328         /****** Debug ******/
 329         u16     ForcedDataRate; /* Force Data Rate. 0: Auto, 0x02: 1M ~ 0x6C: 54M. */
 330         u8      u1ForcedIgiLb;  /* forced IGI lower bound */
 331         u8      bDumpRxPkt;
 332         u8      bDumpTxPkt;
 333         u8      bDisableTXPowerTraining;
 334
 335
 336         /****** EEPROM setting.******/
 337         u8      bautoload_fail_flag;
 338         u8      efuse_file_status;
 339         u8      macaddr_file_status;
 340         u8      EepromOrEfuse;
 341         u8      efuse_eeprom_data[EEPROM_MAX_SIZE]; /*92C:256bytes, 88E:512bytes, we use union set (512bytes)*/
 342         u8      InterfaceSel; /* board type kept in eFuse */
 343         u16     CustomerID;
 344
 345         u16     EEPROMVID;
 346         u16     EEPROMSVID;
 347 #ifdef CONFIG_USB_HCI
 348         u8      EEPROMUsbSwitch;
 349         u16     EEPROMPID;
 350         u16     EEPROMSDID;
 351 #endif
 352 #ifdef CONFIG_PCI_HCI
 353         u16     EEPROMDID;
 354         u16     EEPROMSMID;
 355 #endif
 356
 357         u8      EEPROMCustomerID;
 358         u8      EEPROMSubCustomerID;
 359         u8      EEPROMVersion;
 360         u8      EEPROMRegulatory;
 361         u8      EEPROMThermalMeter;
 362         u8      EEPROMBluetoothCoexist;
 363         u8      EEPROMBluetoothType;
 364         u8      EEPROMBluetoothAntNum;
 365         u8      EEPROMBluetoothAntIsolation;
 366         u8      EEPROMBluetoothRadioShared;
 367         u8      EEPROMMACAddr[ETH_ALEN];
 368
 369 #ifdef CONFIG_RF_POWER_TRIM
 370         u8      EEPROMRFGainOffset;
 371         u8      EEPROMRFGainVal;
 372         struct kfree_data_t kfree_data;
 373 #endif /*CONFIG_RF_POWER_TRIM*/
 374
 375 #if defined(CONFIG_RTL8723B) || defined(CONFIG_RTL8703B) || \
 376         defined(CONFIG_RTL8723D)
 377         u8      adjuseVoltageVal;
 378         u8      need_restore;
 379 #endif
 380         u8      EfuseUsedPercentage;
 381         u16     EfuseUsedBytes;
 382         /*u8            EfuseMap[2][HWSET_MAX_SIZE_JAGUAR];*/
 383         EFUSE_HAL       EfuseHal;
 384
 385         /*---------------------------------------------------------------------------------*/
 386         /* 2.4G TX power info for target TX power*/
 387         u8      Index24G_CCK_Base[MAX_RF_PATH][CENTER_CH_2G_NUM];
 388         u8      Index24G_BW40_Base[MAX_RF_PATH][CENTER_CH_2G_NUM];
 389         s8      CCK_24G_Diff[MAX_RF_PATH][MAX_TX_COUNT];
 390         s8      OFDM_24G_Diff[MAX_RF_PATH][MAX_TX_COUNT];
 391         s8      BW20_24G_Diff[MAX_RF_PATH][MAX_TX_COUNT];
 392         s8      BW40_24G_Diff[MAX_RF_PATH][MAX_TX_COUNT];
 393
 394         /* 5G TX power info for target TX power*/
 395 #ifdef CONFIG_IEEE80211_BAND_5GHZ
 396         u8      Index5G_BW40_Base[MAX_RF_PATH][CENTER_CH_5G_ALL_NUM];
 397         u8      Index5G_BW80_Base[MAX_RF_PATH][CENTER_CH_5G_80M_NUM];
 398         s8      OFDM_5G_Diff[MAX_RF_PATH][MAX_TX_COUNT];
 399         s8      BW20_5G_Diff[MAX_RF_PATH][MAX_TX_COUNT];
 400         s8      BW40_5G_Diff[MAX_RF_PATH][MAX_TX_COUNT];
 401         s8      BW80_5G_Diff[MAX_RF_PATH][MAX_TX_COUNT];
 402 #endif
 403
 404         u8      Regulation2_4G;
 405         u8      Regulation5G;
 406
 407         /********************************
 408         *       TX power by rate table at most 4RF path.
 409         *       The register is
 410         *
 411         *       VHT TX power by rate off setArray =
 412         *       Band:-2G&5G = 0 / 1
 413         *       RF: at most 4*4 = ABCD=0/1/2/3
 414         *       CCK=0 OFDM=1/2 HT-MCS 0-15=3/4/56 VHT=7/8/9/10/11
 415         **********************************/
 416
 417         u8 txpwr_by_rate_undefined_band_path[TX_PWR_BY_RATE_NUM_BAND]
 418                 [TX_PWR_BY_RATE_NUM_RF];
 419
 420         s8      TxPwrByRateOffset[TX_PWR_BY_RATE_NUM_BAND]
 421                 [TX_PWR_BY_RATE_NUM_RF]
 422                 [TX_PWR_BY_RATE_NUM_RF]
 423                 [TX_PWR_BY_RATE_NUM_RATE];
 424
 425 #ifdef CONFIG_PHYDM_POWERTRACK_BY_TSSI
 426         s8      TxPwrByRate[TX_PWR_BY_RATE_NUM_BAND]
 427                 [TX_PWR_BY_RATE_NUM_RF]
 428                 [TX_PWR_BY_RATE_NUM_RF]
 429                 [TX_PWR_BY_RATE_NUM_RATE];
 430 #endif
 431         /* --------------------------------------------------------------------------------- */
 432
 433         u8 tx_pwr_lmt_5g_20_40_ref;
 434
 435         /* Power Limit Table for 2.4G */
 436         s8      TxPwrLimit_2_4G[MAX_REGULATION_NUM]
 437                 [MAX_2_4G_BANDWIDTH_NUM]
 438                 [MAX_RATE_SECTION_NUM]
 439                 [CENTER_CH_2G_NUM]
 440                 [MAX_RF_PATH];
 441
 442         /* Power Limit Table for 5G */
 443         s8      TxPwrLimit_5G[MAX_REGULATION_NUM]
 444                 [MAX_5G_BANDWIDTH_NUM]
 445                 [MAX_RATE_SECTION_NUM]
 446                 [CENTER_CH_5G_ALL_NUM]
 447                 [MAX_RF_PATH];
 448
 449
 450 #ifdef CONFIG_PHYDM_POWERTRACK_BY_TSSI
 451         s8      TxPwrLimit_2_4G_Original[MAX_REGULATION_NUM]
 452                 [MAX_2_4G_BANDWIDTH_NUM]
 453                 [MAX_RATE_SECTION_NUM]
 454                 [CENTER_CH_2G_NUM]
 455                 [MAX_RF_PATH];
 456
 457
 458         s8      TxPwrLimit_5G_Original[MAX_REGULATION_NUM]
 459                 [MAX_5G_BANDWIDTH_NUM]
 460                 [MAX_RATE_SECTION_NUM]
 461                 [CENTER_CH_5G_ALL_NUM]
 462                 [MAX_RF_PATH];
 463
 464 #endif
 465
 466         /* Store the original power by rate value of the base of each rate section of rf path A & B */
 467         u8      TxPwrByRateBase2_4G[TX_PWR_BY_RATE_NUM_RF]
 468                 [TX_PWR_BY_RATE_NUM_RF]
 469                 [MAX_BASE_NUM_IN_PHY_REG_PG_2_4G];
 470         u8      TxPwrByRateBase5G[TX_PWR_BY_RATE_NUM_RF]
 471                 [TX_PWR_BY_RATE_NUM_RF]
 472                 [MAX_BASE_NUM_IN_PHY_REG_PG_5G];
 473
 474         u8      txpwr_by_rate_loaded:1;
 475         u8      txpwr_by_rate_from_file:1;
 476         u8      txpwr_limit_loaded:1;
 477         u8      txpwr_limit_from_file:1;
 478         u8      RfPowerTrackingType;
 479
 480         /* Read/write are allow for following hardware information variables     */
 481         u8      CrystalCap;
 482
 483         u8      PAType_2G;
 484         u8      PAType_5G;
 485         u8      LNAType_2G;
 486         u8      LNAType_5G;
 487         u8      ExternalPA_2G;
 488         u8      ExternalLNA_2G;
 489         u8      ExternalPA_5G;
 490         u8      ExternalLNA_5G;
 491         u16     TypeGLNA;
 492         u16     TypeGPA;
 493         u16     TypeALNA;
 494         u16     TypeAPA;
 495         u16     RFEType;
 496
 497         u8      bLedOpenDrain; /* Support Open-drain arrangement for controlling the LED. Added by Roger, 2009.10.16. */
 498         u32     AcParam_BE; /* Original parameter for BE, use for EDCA turbo.   */
 499
 500         BB_REGISTER_DEFINITION_T        PHYRegDef[MAX_RF_PATH]; /* Radio A/B/C/D */
 501
 502         u32     RfRegChnlVal[MAX_RF_PATH];
 503
 504         /* RDG enable */
 505         BOOLEAN  bRDGEnable;
 506
 507         u8      RegTxPause;
 508         /* Beacon function related global variable. */
 509         u8      RegBcnCtrlVal;
 510         u8      RegFwHwTxQCtrl;
 511         u8      RegReg542;
 512         u8      RegCR_1;
 513         u8      Reg837;
 514         u16     RegRRSR;
 515
 516         /****** antenna diversity ******/
 517         u8      AntDivCfg;
 518         u8      with_extenal_ant_switch;
 519         u8      b_fix_tx_ant;
 520         u8      AntDetection;
 521         u8      TRxAntDivType;
 522         u8      ant_path; /* for 8723B s0/s1 selection   */
 523         u32     AntennaTxPath;                                  /* Antenna path Tx */
 524         u32     AntennaRxPath;                                  /* Antenna path Rx */
 525         u8 sw_antdiv_bl_state;
 526
 527         /******** PHY DM & DM Section **********/
 528         u8                      DM_Type;
 529         _lock           IQKSpinLock;
 530         u8                      INIDATA_RATE[MACID_NUM_SW_LIMIT];
 531         /* Upper and Lower Signal threshold for Rate Adaptive*/
 532         int                     EntryMinUndecoratedSmoothedPWDB;
 533         int                     EntryMaxUndecoratedSmoothedPWDB;
 534         int                     MinUndecoratedPWDBForDM;
 535         DM_ODM_T        odmpriv;
 536         u8                      bIQKInitialized;
 537         u8                      bNeedIQK;
 538         u8              IQK_MP_Switch;
 539         /******** PHY DM & DM Section **********/
 540
 541
 542
 543         /* 2010/08/09 MH Add CU power down mode. */
 544         BOOLEAN         pwrdown;
 545
 546         /* Add for dual MAC  0--Mac0 1--Mac1 */
 547         u32     interfaceIndex;
 548
 549 #ifdef CONFIG_P2P
 550         u8      p2p_ps_offload;
 551 #endif
 552         /* Auto FSM to Turn On, include clock, isolation, power control for MAC only */
 553         u8      bMacPwrCtrlOn;
 554         u8 hci_sus_state;
 555
 556         u8      RegIQKFWOffload;
 557         struct submit_ctx       iqk_sctx;
 558
 559         RT_AMPDU_BRUST          AMPDUBurstMode; /* 92C maybe not use, but for compile successfully */
 560
 561         u8      OutEpQueueSel;
 562         u8      OutEpNumber;
 563
 564 #ifdef RTW_RX_AGGREGATION
 565         RX_AGG_MODE rxagg_mode;
 566
 567         /* For RX Aggregation DMA Mode */
 568         u8 rxagg_dma_size;
 569         u8 rxagg_dma_timeout;
 570 #endif /* RTW_RX_AGGREGATION */
 571
 572 #if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
 573         /*  */
 574         /* For SDIO Interface HAL related */
 575         /*  */
 576
 577         /*  */
 578         /* SDIO ISR Related */
 579         /*
 580         *       u32                     IntrMask[1];
 581         *       u32                     IntrMaskToSet[1];
 582         *       LOG_INTERRUPT           InterruptLog; */
 583         u32                     sdio_himr;
 584         u32                     sdio_hisr;
 585 #ifndef RTW_HALMAC
 586         /*  */
 587         /* SDIO Tx FIFO related. */
 588         /*  */
 589         /* HIQ, MID, LOW, PUB free pages; padapter->xmitpriv.free_txpg */
 590         u8                      SdioTxFIFOFreePage[SDIO_TX_FREE_PG_QUEUE];
 591         _lock           SdioTxFIFOFreePageLock;
 592         u8                      SdioTxOQTMaxFreeSpace;
 593         u8                      SdioTxOQTFreeSpace;
 594 #else /* RTW_HALMAC */
 595         u16                     SdioTxOQTFreeSpace;
 596 #endif /* RTW_HALMAC */
 597
 598         /*  */
 599         /* SDIO Rx FIFO related. */
 600         /*  */
 601         u8                      SdioRxFIFOCnt;
 602         u16                     SdioRxFIFOSize;
 603
 604 #ifndef RTW_HALMAC
 605         u32                     sdio_tx_max_len[SDIO_MAX_TX_QUEUE];/* H, N, L, used for sdio tx aggregation max length per queue */
 606 #else
 607 #ifdef CONFIG_RTL8821C
 608         u16                     tx_high_page;
 609         u16                     tx_low_page;
 610         u16                     tx_normal_page;
 611         u16                     tx_extra_page;
 612         u16                     tx_pub_page;
 613         u16                     max_oqt_page;
 614         u32                     max_xmit_size_vovi;
 615         u32                     max_xmit_size_bebk;
 616 #endif
 617 #endif /* !RTW_HALMAC */
 618 #endif /* CONFIG_SDIO_HCI */
 619
 620 #ifdef CONFIG_USB_HCI
 621
 622         /* 2010/12/10 MH Add for USB aggreation mode dynamic shceme. */
 623         BOOLEAN         UsbRxHighSpeedMode;
 624         BOOLEAN         UsbTxVeryHighSpeedMode;
 625         u32                     UsbBulkOutSize;
 626         BOOLEAN         bSupportUSB3;
 627         u8                      usb_intf_start;
 628
 629         /* Interrupt relatd register information. */
 630         u32                     IntArray[3];/* HISR0,HISR1,HSISR */
 631         u32                     IntrMask[3];
 632 #ifdef CONFIG_USB_TX_AGGREGATION
 633         u8                      UsbTxAggMode;
 634         u8                      UsbTxAggDescNum;
 635 #endif /* CONFIG_USB_TX_AGGREGATION */
 636
 637 #ifdef CONFIG_USB_RX_AGGREGATION
 638         u16                     HwRxPageSize;                           /* Hardware setting */
 639
 640         /* For RX Aggregation USB Mode */
 641         u8                      rxagg_usb_size;
 642         u8                      rxagg_usb_timeout;
 643 #endif/* CONFIG_USB_RX_AGGREGATION */
 644 #endif /* CONFIG_USB_HCI */
 645
 646
 647 #ifdef CONFIG_PCI_HCI
 648         /*  */
 649         /* EEPROM setting. */
 650         /*  */
 651         u32                     TransmitConfig;
 652         u32                     IntrMaskToSet[2];
 653         u32                     IntArray[4];
 654         u32                     IntrMask[4];
 655         u32                     SysIntArray[1];
 656         u32                     SysIntrMask[1];
 657         u32                     IntrMaskReg[2];
 658         u32                     IntrMaskDefault[4];
 659
 660         BOOLEAN         bL1OffSupport;
 661         BOOLEAN bSupportBackDoor;
 662
 663         u8                      bDefaultAntenna;
 664
 665         u8                      bInterruptMigration;
 666         u8                      bDisableTxInt;
 667
 668         u16                     RxTag;
 669 #endif /* CONFIG_PCI_HCI */
 670
 671
 672 #ifdef DBG_CONFIG_ERROR_DETECT
 673         struct sreset_priv srestpriv;
 674 #endif /* #ifdef DBG_CONFIG_ERROR_DETECT */
 675
 676 #ifdef CONFIG_BT_COEXIST
 677         /* For bluetooth co-existance */
 678         BT_COEXIST              bt_coexist;
 679 #endif /* CONFIG_BT_COEXIST */
 680
 681 #if defined(CONFIG_RTL8723B) || defined(CONFIG_RTL8703B) \
 682         || defined(CONFIG_RTL8188F) || defined(CONFIG_RTL8723D)
 683 #ifndef CONFIG_PCI_HCI  /* mutual exclusive with PCI -- so they're SDIO and GSPI */
 684         /* Interrupt relatd register information. */
 685         u32                     SysIntrStatus;
 686         u32                     SysIntrMask;
 687 #endif
 688 #endif /*endif CONFIG_RTL8723B  */
 689
 690 #ifdef CONFIG_LOAD_PHY_PARA_FROM_FILE
 691         char    para_file_buf[MAX_PARA_FILE_BUF_LEN];
 692         char *mac_reg;
 693         u32     mac_reg_len;
 694         char *bb_phy_reg;
 695         u32     bb_phy_reg_len;
 696         char *bb_agc_tab;
 697         u32     bb_agc_tab_len;
 698         char *bb_phy_reg_pg;
 699         u32     bb_phy_reg_pg_len;
 700         char *bb_phy_reg_mp;
 701         u32     bb_phy_reg_mp_len;
 702         char *rf_radio_a;
 703         u32     rf_radio_a_len;
 704         char *rf_radio_b;
 705         u32     rf_radio_b_len;
 706         char *rf_tx_pwr_track;
 707         u32     rf_tx_pwr_track_len;
 708         char *rf_tx_pwr_lmt;
 709         u32     rf_tx_pwr_lmt_len;
 710 #endif
 711
 712 #ifdef CONFIG_BACKGROUND_NOISE_MONITOR
 713         s16 noise[ODM_MAX_CHANNEL_NUM];
 714 #endif
 715
 716         struct hal_spec_t hal_spec;
 717
 718         u8      RfKFreeEnable;
 719         u8      RfKFree_ch_group;
 720         BOOLEAN                         bCCKinCH14;
 721         BB_INIT_REGISTER        RegForRecover[5];
 722
 723 #if defined(CONFIG_PCI_HCI) && defined(RTL8814AE_SW_BCN)
 724         BOOLEAN bCorrectBCN;
 725 #endif
 726         u32 RxGainOffset[4]; /*{2G, 5G_Low, 5G_Middle, G_High}*/
 727         u8 BackUp_IG_REG_4_Chnl_Section[4]; /*{A,B,C,D}*/
 728
 729         struct hal_iqk_reg_backup iqk_reg_backup[MAX_IQK_INFO_BACKUP_CHNL_NUM];
 730
 731 #ifdef CONFIG_BEAMFORMING
 732 #ifdef RTW_BEAMFORMING_VERSION_2
 733         struct beamforming_info beamforming_info;
 734 #endif /* RTW_BEAMFORMING_VERSION_2 */
 735 #endif /* CONFIG_BEAMFORMING */
 736 } HAL_DATA_COMMON, *PHAL_DATA_COMMON;
 737
 738
 739
 740 typedef struct hal_com_data HAL_DATA_TYPE, *PHAL_DATA_TYPE;
 741 #define GET_HAL_DATA(__pAdapter)                        ((HAL_DATA_TYPE *)((__pAdapter)->HalData))
 742 #define GET_HAL_SPEC(__pAdapter)                        (&(GET_HAL_DATA((__pAdapter))->hal_spec))
 743 #define GET_ODM(__pAdapter)                     (&(GET_HAL_DATA((__pAdapter))->odmpriv))
 744
 745 #define GET_HAL_RFPATH_NUM(__pAdapter)          (((HAL_DATA_TYPE *)((__pAdapter)->HalData))->NumTotalRFPath)
 746 #define RT_GetInterfaceSelection(_Adapter)              (GET_HAL_DATA(_Adapter)->InterfaceSel)
 747 #define GET_RF_TYPE(__pAdapter)                         (GET_HAL_DATA(__pAdapter)->rf_type)
 748 #define GET_KFREE_DATA(_adapter) (&(GET_HAL_DATA((_adapter))->kfree_data))
 749
 750 #define SUPPORT_HW_RADIO_DETECT(Adapter)        (RT_GetInterfaceSelection(Adapter) == INTF_SEL2_MINICARD || \
 751                 RT_GetInterfaceSelection(Adapter) == INTF_SEL3_USB_Solo || \
 752                 RT_GetInterfaceSelection(Adapter) == INTF_SEL4_USB_Combo)
 753
 754 #define get_hal_mac_addr(adapter)                               (GET_HAL_DATA(adapter)->EEPROMMACAddr)
 755 #define is_boot_from_eeprom(adapter)                    (GET_HAL_DATA(adapter)->EepromOrEfuse)
 756 #define rtw_get_hw_init_completed(adapter)              (GET_HAL_DATA(adapter)->hw_init_completed)
 757 #define rtw_is_hw_init_completed(adapter)               (GET_HAL_DATA(adapter)->hw_init_completed == _TRUE)
 758 #endif
 759
 760 #ifdef CONFIG_AUTO_CHNL_SEL_NHM
 761 #define GET_ACS_STATE(padapter)                                 (ATOMIC_READ(&GET_HAL_DATA(padapter)->acs.state))
 762 #define SET_ACS_STATE(padapter, set_state)                      (ATOMIC_SET(&GET_HAL_DATA(padapter)->acs.state, set_state))
 763 #define rtw_get_acs_channel(padapter)                           (GET_HAL_DATA(padapter)->acs.ch)
 764 #define rtw_set_acs_channel(padapter, survey_ch)        (GET_HAL_DATA(padapter)->acs.ch = survey_ch)
 765 #endif /*CONFIG_AUTO_CHNL_SEL_NHM*/
 766
 767 #ifdef RTW_HALMAC
 768 int rtw_halmac_deinit_adapter(struct dvobj_priv *);
 769 #endif /* RTW_HALMAC */
 770
 771 #endif /* __HAL_DATA_H__ */