1 /******************************************************************************
3 * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
18 *******************************************************************************/
19 #ifndef __RTL8703B_SPEC_H__
20 #define __RTL8703B_SPEC_H__
25 #define HAL_NAV_UPPER_UNIT_8703B 128 /* micro-second */
27 /* -----------------------------------------------------
29 * 0x0000h ~ 0x00FFh System Configuration
31 * ----------------------------------------------------- */
32 #define REG_SYS_ISO_CTRL_8703B 0x0000 /* 2 Byte */
33 #define REG_SYS_FUNC_EN_8703B 0x0002 /* 2 Byte */
34 #define REG_APS_FSMCO_8703B 0x0004 /* 4 Byte */
35 #define REG_SYS_CLKR_8703B 0x0008 /* 2 Byte */
36 #define REG_9346CR_8703B 0x000A /* 2 Byte */
37 #define REG_EE_VPD_8703B 0x000C /* 2 Byte */
38 #define REG_AFE_MISC_8703B 0x0010 /* 1 Byte */
39 #define REG_SPS0_CTRL_8703B 0x0011 /* 7 Byte */
40 #define REG_SPS_OCP_CFG_8703B 0x0018 /* 4 Byte */
41 #define REG_RSV_CTRL_8703B 0x001C /* 3 Byte */
42 #define REG_RF_CTRL_8703B 0x001F /* 1 Byte */
43 #define REG_LPLDO_CTRL_8703B 0x0023 /* 1 Byte */
44 #define REG_AFE_XTAL_CTRL_8703B 0x0024 /* 4 Byte */
45 #define REG_AFE_PLL_CTRL_8703B 0x0028 /* 4 Byte */
46 #define REG_MAC_PLL_CTRL_EXT_8703B 0x002c /* 4 Byte */
47 #define REG_EFUSE_CTRL_8703B 0x0030
48 #define REG_EFUSE_TEST_8703B 0x0034
49 #define REG_PWR_DATA_8703B 0x0038
50 #define REG_CAL_TIMER_8703B 0x003C
51 #define REG_ACLK_MON_8703B 0x003E
52 #define REG_GPIO_MUXCFG_8703B 0x0040
53 #define REG_GPIO_IO_SEL_8703B 0x0042
54 #define REG_MAC_PINMUX_CFG_8703B 0x0043
55 #define REG_GPIO_PIN_CTRL_8703B 0x0044
56 #define REG_GPIO_INTM_8703B 0x0048
57 #define REG_LEDCFG0_8703B 0x004C
58 #define REG_LEDCFG1_8703B 0x004D
59 #define REG_LEDCFG2_8703B 0x004E
60 #define REG_LEDCFG3_8703B 0x004F
61 #define REG_FSIMR_8703B 0x0050
62 #define REG_FSISR_8703B 0x0054
63 #define REG_HSIMR_8703B 0x0058
64 #define REG_HSISR_8703B 0x005c
65 #define REG_GPIO_EXT_CTRL 0x0060
66 #define REG_PAD_CTRL1_8703B 0x0064
67 #define REG_MULTI_FUNC_CTRL_8703B 0x0068
68 #define REG_GPIO_STATUS_8703B 0x006C
69 #define REG_SDIO_CTRL_8703B 0x0070
70 #define REG_OPT_CTRL_8703B 0x0074
71 #define REG_AFE_CTRL_4_8703B 0x0078
72 #define REG_MCUFWDL_8703B 0x0080
73 #define REG_HMEBOX_DBG_0_8703B 0x0088
74 #define REG_HMEBOX_DBG_1_8703B 0x008A
75 #define REG_HMEBOX_DBG_2_8703B 0x008C
76 #define REG_HMEBOX_DBG_3_8703B 0x008E
77 #define REG_HIMR0_8703B 0x00B0
78 #define REG_HISR0_8703B 0x00B4
79 #define REG_HIMR1_8703B 0x00B8
80 #define REG_HISR1_8703B 0x00BC
81 #define REG_PMC_DBG_CTRL2_8703B 0x00CC
82 #define REG_EFUSE_BURN_GNT_8703B 0x00CF
83 #define REG_HPON_FSM_8703B 0x00EC
84 #define REG_SYS_CFG_8703B 0x00F0
85 #define REG_SYS_CFG1_8703B 0x00FC
86 #define REG_ROM_VERSION 0x00FD
88 /* -----------------------------------------------------
90 * 0x0100h ~ 0x01FFh MACTOP General Configuration
92 * ----------------------------------------------------- */
93 #define REG_C2HEVT_CMD_ID_8703B 0x01A0
94 #define REG_C2HEVT_CMD_SEQ_88XX 0x01A1
95 #define REG_C2hEVT_CMD_CONTENT_88XX 0x01A2
96 #define REG_C2HEVT_CMD_LEN_8703B 0x01AE
97 #define REG_C2HEVT_CMD_LEN_88XX REG_C2HEVT_CMD_LEN_8703B
98 #define REG_C2HEVT_CLEAR_8703B 0x01AF
99 #define REG_MCUTST_1_8703B 0x01C0
100 #define REG_WOWLAN_WAKE_REASON 0x01C7
101 #define REG_FMETHR_8703B 0x01C8
102 #define REG_HMETFR_8703B 0x01CC
103 #define REG_HMEBOX_0_8703B 0x01D0
104 #define REG_HMEBOX_1_8703B 0x01D4
105 #define REG_HMEBOX_2_8703B 0x01D8
106 #define REG_HMEBOX_3_8703B 0x01DC
107 #define REG_LLT_INIT_8703B 0x01E0
108 #define REG_HMEBOX_EXT0_8703B 0x01F0
109 #define REG_HMEBOX_EXT1_8703B 0x01F4
110 #define REG_HMEBOX_EXT2_8703B 0x01F8
111 #define REG_HMEBOX_EXT3_8703B 0x01FC
113 /* -----------------------------------------------------
115 * 0x0200h ~ 0x027Fh TXDMA Configuration
117 * ----------------------------------------------------- */
118 #define REG_RQPN_8703B 0x0200
119 #define REG_FIFOPAGE_8703B 0x0204
120 #define REG_DWBCN0_CTRL_8703B REG_TDECTRL
121 #define REG_TXDMA_OFFSET_CHK_8703B 0x020C
122 #define REG_TXDMA_STATUS_8703B 0x0210
123 #define REG_RQPN_NPQ_8703B 0x0214
124 #define REG_DWBCN1_CTRL_8703B 0x0228
127 /* -----------------------------------------------------
129 * 0x0280h ~ 0x02FFh RXDMA Configuration
131 * ----------------------------------------------------- */
132 #define REG_RXDMA_AGG_PG_TH_8703B 0x0280
133 #define REG_FW_UPD_RDPTR_8703B 0x0284 /* FW shall update this register before FW write RXPKT_RELEASE_POLL to 1 */
134 #define REG_RXDMA_CONTROL_8703B 0x0286 /* Control the RX DMA. */
135 #define REG_RXPKT_NUM_8703B 0x0287 /* The number of packets in RXPKTBUF. */
136 #define REG_RXDMA_STATUS_8703B 0x0288
137 #define REG_RXDMA_MODE_CTRL_8703B 0x0290
138 #define REG_EARLY_MODE_CONTROL_8703B 0x02BC
139 #define REG_RSVD5_8703B 0x02F0
140 #define REG_RSVD6_8703B 0x02F4
142 /* -----------------------------------------------------
144 * 0x0300h ~ 0x03FFh PCIe
146 * ----------------------------------------------------- */
147 #define REG_PCIE_CTRL_REG_8703B 0x0300
148 #define REG_INT_MIG_8703B 0x0304 /* Interrupt Migration */
149 #define REG_BCNQ_DESA_8703B 0x0308 /* TX Beacon Descriptor Address */
150 #define REG_HQ_DESA_8703B 0x0310 /* TX High Queue Descriptor Address */
151 #define REG_MGQ_DESA_8703B 0x0318 /* TX Manage Queue Descriptor Address */
152 #define REG_VOQ_DESA_8703B 0x0320 /* TX VO Queue Descriptor Address */
153 #define REG_VIQ_DESA_8703B 0x0328 /* TX VI Queue Descriptor Address */
154 #define REG_BEQ_DESA_8703B 0x0330 /* TX BE Queue Descriptor Address */
155 #define REG_BKQ_DESA_8703B 0x0338 /* TX BK Queue Descriptor Address */
156 #define REG_RX_DESA_8703B 0x0340 /* RX Queue Descriptor Address */
157 #define REG_DBI_WDATA_8703B 0x0348 /* DBI Write Data */
158 #define REG_DBI_RDATA_8703B 0x034C /* DBI Read Data */
159 #define REG_DBI_ADDR_8703B 0x0350 /* DBI Address */
160 #define REG_DBI_FLAG_8703B 0x0352 /* DBI Read/Write Flag */
161 #define REG_MDIO_WDATA_8703B 0x0354 /* MDIO for Write PCIE PHY */
162 #define REG_MDIO_RDATA_8703B 0x0356 /* MDIO for Reads PCIE PHY */
163 #define REG_MDIO_CTL_8703B 0x0358 /* MDIO for Control */
164 #define REG_DBG_SEL_8703B 0x0360 /* Debug Selection Register */
165 #define REG_PCIE_HRPWM_8703B 0x0361 /* PCIe RPWM */
166 #define REG_PCIE_HCPWM_8703B 0x0363 /* PCIe CPWM */
167 #define REG_PCIE_MULTIFET_CTRL_8703B 0x036A /* PCIE Multi-Fethc Control */
169 /* -----------------------------------------------------
171 * 0x0400h ~ 0x047Fh Protocol Configuration
173 * ----------------------------------------------------- */
174 #define REG_VOQ_INFORMATION_8703B 0x0400
175 #define REG_VIQ_INFORMATION_8703B 0x0404
176 #define REG_BEQ_INFORMATION_8703B 0x0408
177 #define REG_BKQ_INFORMATION_8703B 0x040C
178 #define REG_MGQ_INFORMATION_8703B 0x0410
179 #define REG_HGQ_INFORMATION_8703B 0x0414
180 #define REG_BCNQ_INFORMATION_8703B 0x0418
181 #define REG_TXPKT_EMPTY_8703B 0x041A
183 #define REG_FWHW_TXQ_CTRL_8703B 0x0420
184 #define REG_HWSEQ_CTRL_8703B 0x0423
185 #define REG_TXPKTBUF_BCNQ_BDNY_8703B 0x0424
186 #define REG_TXPKTBUF_MGQ_BDNY_8703B 0x0425
187 #define REG_LIFECTRL_CTRL_8703B 0x0426
188 #define REG_MULTI_BCNQ_OFFSET_8703B 0x0427
189 #define REG_SPEC_SIFS_8703B 0x0428
190 #define REG_RL_8703B 0x042A
191 #define REG_TXBF_CTRL_8703B 0x042C
192 #define REG_DARFRC_8703B 0x0430
193 #define REG_RARFRC_8703B 0x0438
194 #define REG_RRSR_8703B 0x0440
195 #define REG_ARFR0_8703B 0x0444
196 #define REG_ARFR1_8703B 0x044C
197 #define REG_CCK_CHECK_8703B 0x0454
198 #define REG_AMPDU_MAX_TIME_8703B 0x0456
199 #define REG_TXPKTBUF_BCNQ_BDNY1_8703B 0x0457
201 #define REG_AMPDU_MAX_LENGTH_8703B 0x0458
202 #define REG_TXPKTBUF_WMAC_LBK_BF_HD_8703B 0x045D
203 #define REG_NDPA_OPT_CTRL_8703B 0x045F
204 #define REG_FAST_EDCA_CTRL_8703B 0x0460
205 #define REG_RD_RESP_PKT_TH_8703B 0x0463
206 #define REG_DATA_SC_8703B 0x0483
208 #define REG_TXPKTBUF_IV_LOW 0x0484
209 #define REG_TXPKTBUF_IV_HIGH 0x0488
211 #define REG_TXRPT_START_OFFSET 0x04AC
212 #define REG_POWER_STAGE1_8703B 0x04B4
213 #define REG_POWER_STAGE2_8703B 0x04B8
214 #define REG_AMPDU_BURST_MODE_8703B 0x04BC
215 #define REG_PKT_VO_VI_LIFE_TIME_8703B 0x04C0
216 #define REG_PKT_BE_BK_LIFE_TIME_8703B 0x04C2
217 #define REG_STBC_SETTING_8703B 0x04C4
218 #define REG_HT_SINGLE_AMPDU_8703B 0x04C7
219 #define REG_PROT_MODE_CTRL_8703B 0x04C8
220 #define REG_MAX_AGGR_NUM_8703B 0x04CA
221 #define REG_RTS_MAX_AGGR_NUM_8703B 0x04CB
222 #define REG_BAR_MODE_CTRL_8703B 0x04CC
223 #define REG_RA_TRY_RATE_AGG_LMT_8703B 0x04CF
224 #define REG_MACID_PKT_DROP0_8703B 0x04D0
225 #define REG_MACID_PKT_SLEEP_8703B 0x04D4
227 /* -----------------------------------------------------
229 * 0x0500h ~ 0x05FFh EDCA Configuration
231 * ----------------------------------------------------- */
232 #define REG_EDCA_VO_PARAM_8703B 0x0500
233 #define REG_EDCA_VI_PARAM_8703B 0x0504
234 #define REG_EDCA_BE_PARAM_8703B 0x0508
235 #define REG_EDCA_BK_PARAM_8703B 0x050C
236 #define REG_BCNTCFG_8703B 0x0510
237 #define REG_PIFS_8703B 0x0512
238 #define REG_RDG_PIFS_8703B 0x0513
239 #define REG_SIFS_CTX_8703B 0x0514
240 #define REG_SIFS_TRX_8703B 0x0516
241 #define REG_AGGR_BREAK_TIME_8703B 0x051A
242 #define REG_SLOT_8703B 0x051B
243 #define REG_TX_PTCL_CTRL_8703B 0x0520
244 #define REG_TXPAUSE_8703B 0x0522
245 #define REG_DIS_TXREQ_CLR_8703B 0x0523
246 #define REG_RD_CTRL_8703B 0x0524
248 * Format for offset 540h-542h:
249 * [3:0]: TBTT prohibit setup in unit of 32us. The time for HW getting beacon content before TBTT.
251 * [19:8]: TBTT prohibit hold in unit of 32us. The time for HW holding to send the beacon packet.
255 * |<--Setup--|--Hold------------>|
256 * --------------|----------------------
259 * Note: We cannot update beacon content to HW or send any AC packets during the time between Setup and Hold.
260 * Described by Designer Tim and Bruce, 2011-01-14.
262 #define REG_TBTT_PROHIBIT_8703B 0x0540
263 #define REG_RD_NAV_NXT_8703B 0x0544
264 #define REG_NAV_PROT_LEN_8703B 0x0546
265 #define REG_BCN_CTRL_8703B 0x0550
266 #define REG_BCN_CTRL_1_8703B 0x0551
267 #define REG_MBID_NUM_8703B 0x0552
268 #define REG_DUAL_TSF_RST_8703B 0x0553
269 #define REG_BCN_INTERVAL_8703B 0x0554
270 #define REG_DRVERLYINT_8703B 0x0558
271 #define REG_BCNDMATIM_8703B 0x0559
272 #define REG_ATIMWND_8703B 0x055A
273 #define REG_USTIME_TSF_8703B 0x055C
274 #define REG_BCN_MAX_ERR_8703B 0x055D
275 #define REG_RXTSF_OFFSET_CCK_8703B 0x055E
276 #define REG_RXTSF_OFFSET_OFDM_8703B 0x055F
277 #define REG_TSFTR_8703B 0x0560
278 #define REG_CTWND_8703B 0x0572
279 #define REG_SECONDARY_CCA_CTRL_8703B 0x0577
280 #define REG_PSTIMER_8703B 0x0580
281 #define REG_TIMER0_8703B 0x0584
282 #define REG_TIMER1_8703B 0x0588
283 #define REG_ACMHWCTRL_8703B 0x05C0
284 #define REG_SCH_TXCMD_8703B 0x05F8
286 /* -----------------------------------------------------
288 * 0x0600h ~ 0x07FFh WMAC Configuration
290 * ----------------------------------------------------- */
291 #define REG_MAC_CR_8703B 0x0600
292 #define REG_TCR_8703B 0x0604
293 #define REG_RCR_8703B 0x0608
294 #define REG_RX_PKT_LIMIT_8703B 0x060C
295 #define REG_RX_DLK_TIME_8703B 0x060D
296 #define REG_RX_DRVINFO_SZ_8703B 0x060F
298 #define REG_MACID_8703B 0x0610
299 #define REG_BSSID_8703B 0x0618
300 #define REG_MAR_8703B 0x0620
301 #define REG_MBIDCAMCFG_8703B 0x0628
302 #define REG_WOWLAN_GTK_DBG1 0x630
303 #define REG_WOWLAN_GTK_DBG2 0x634
305 #define REG_USTIME_EDCA_8703B 0x0638
306 #define REG_MAC_SPEC_SIFS_8703B 0x063A
307 #define REG_RESP_SIFP_CCK_8703B 0x063C
308 #define REG_RESP_SIFS_OFDM_8703B 0x063E
309 #define REG_ACKTO_8703B 0x0640
310 #define REG_CTS2TO_8703B 0x0641
311 #define REG_EIFS_8703B 0x0642
313 #define REG_NAV_UPPER_8703B 0x0652 /* unit of 128 */
314 #define REG_TRXPTCL_CTL_8703B 0x0668
317 #define REG_CAMCMD_8703B 0x0670
318 #define REG_CAMWRITE_8703B 0x0674
319 #define REG_CAMREAD_8703B 0x0678
320 #define REG_CAMDBG_8703B 0x067C
321 #define REG_SECCFG_8703B 0x0680
324 #define REG_WOW_CTRL_8703B 0x0690
325 #define REG_PS_RX_INFO_8703B 0x0692
326 #define REG_UAPSD_TID_8703B 0x0693
327 #define REG_WKFMCAM_CMD_8703B 0x0698
328 #define REG_WKFMCAM_NUM_8703B 0x0698
329 #define REG_WKFMCAM_RWD_8703B 0x069C
330 #define REG_RXFLTMAP0_8703B 0x06A0
331 #define REG_RXFLTMAP1_8703B 0x06A2
332 #define REG_RXFLTMAP2_8703B 0x06A4
333 #define REG_BCN_PSR_RPT_8703B 0x06A8
334 #define REG_BT_COEX_TABLE_8703B 0x06C0
335 #define REG_BFMER0_INFO_8703B 0x06E4
336 #define REG_BFMER1_INFO_8703B 0x06EC
337 #define REG_CSI_RPT_PARAM_BW20_8703B 0x06F4
338 #define REG_CSI_RPT_PARAM_BW40_8703B 0x06F8
339 #define REG_CSI_RPT_PARAM_BW80_8703B 0x06FC
341 /* Hardware Port 2 */
342 #define REG_MACID1_8703B 0x0700
343 #define REG_BSSID1_8703B 0x0708
344 #define REG_BFMEE_SEL_8703B 0x0714
345 #define REG_SND_PTCL_CTRL_8703B 0x0718
348 #define REG_LTECOEX_CTRL 0x07C0
349 #define REG_LTECOEX_WRITE_DATA 0x07C4
350 #define REG_LTECOEX_READ_DATA 0x07C8
351 #define REG_LTECOEX_PATH_CONTROL 0x70
353 /* ************************************************************
354 * SDIO Bus Specification
355 * ************************************************************ */
357 /* -----------------------------------------------------
358 * SDIO CMD Address Mapping
359 * ----------------------------------------------------- */
361 /* -----------------------------------------------------
362 * I/O bus domain (Host)
363 * ----------------------------------------------------- */
365 /* -----------------------------------------------------
367 * ----------------------------------------------------- */
368 #define SDIO_REG_HCPWM1_8703B 0x025 /* HCI Current Power Mode 1 */
371 /* ****************************************************************************
372 * 8703 Regsiter Bit and Content definition
373 * **************************************************************************** */
375 #define BIT_USB_RXDMA_AGG_EN BIT(31)
376 #define RXDMA_AGG_MODE_EN BIT(1)
379 #define RXPKT_RELEASE_POLL BIT(16)
380 #define RXDMA_IDLE BIT(17)
381 #define RW_RELEASE_EN BIT(18)
385 * interrupt mask which needs to clear */
386 #define MASK_HSISR_CLEAR (HSISR_GPIO12_0_INT |\
393 /* ----------------------------------------------------------------------------
394 * 8703B REG_CCK_CHECK (offset 0x454)
395 * ---------------------------------------------------------------------------- */
396 #define BIT_BCN_PORT_SEL BIT5
398 #ifdef CONFIG_RF_POWER_TRIM
400 #ifdef CONFIG_RTL8703B
401 #define EEPROM_RF_GAIN_OFFSET 0xC1
404 #define EEPROM_RF_GAIN_VAL 0x1F6
405 #endif /*CONFIG_RF_POWER_TRIM*/
408 /* ----------------------------------------------------------------------------
409 * 8195 IMR/ISR bits (offset 0xB0, 8bits)
410 * ---------------------------------------------------------------------------- */
411 #define IMR_DISABLED_8703B 0
412 /* IMR DW0(0x00B0-00B3) Bit 0-31 */
413 #define IMR_TIMER2_8703B BIT31 /* Timeout interrupt 2 */
414 #define IMR_TIMER1_8703B BIT30 /* Timeout interrupt 1 */
415 #define IMR_PSTIMEOUT_8703B BIT29 /* Power Save Time Out Interrupt */
416 #define IMR_GTINT4_8703B BIT28 /* When GTIMER4 expires, this bit is set to 1 */
417 #define IMR_GTINT3_8703B BIT27 /* When GTIMER3 expires, this bit is set to 1 */
418 #define IMR_TXBCN0ERR_8703B BIT26 /* Transmit Beacon0 Error */
419 #define IMR_TXBCN0OK_8703B BIT25 /* Transmit Beacon0 OK */
420 #define IMR_TSF_BIT32_TOGGLE_8703B BIT24 /* TSF Timer BIT32 toggle indication interrupt */
421 #define IMR_BCNDMAINT0_8703B BIT20 /* Beacon DMA Interrupt 0 */
422 #define IMR_BCNDERR0_8703B BIT16 /* Beacon Queue DMA OK0 */
423 #define IMR_HSISR_IND_ON_INT_8703B BIT15 /* HSISR Indicator (HSIMR & HSISR is true, this bit is set to 1) */
424 #define IMR_BCNDMAINT_E_8703B BIT14 /* Beacon DMA Interrupt Extension for Win7 */
425 #define IMR_ATIMEND_8703B BIT12 /* CTWidnow End or ATIM Window End */
426 #define IMR_C2HCMD_8703B BIT10 /* CPU to Host Command INT Status, Write 1 clear */
427 #define IMR_CPWM2_8703B BIT9 /* CPU power Mode exchange INT Status, Write 1 clear */
428 #define IMR_CPWM_8703B BIT8 /* CPU power Mode exchange INT Status, Write 1 clear */
429 #define IMR_HIGHDOK_8703B BIT7 /* High Queue DMA OK */
430 #define IMR_MGNTDOK_8703B BIT6 /* Management Queue DMA OK */
431 #define IMR_BKDOK_8703B BIT5 /* AC_BK DMA OK */
432 #define IMR_BEDOK_8703B BIT4 /* AC_BE DMA OK */
433 #define IMR_VIDOK_8703B BIT3 /* AC_VI DMA OK */
434 #define IMR_VODOK_8703B BIT2 /* AC_VO DMA OK */
435 #define IMR_RDU_8703B BIT1 /* Rx Descriptor Unavailable */
436 #define IMR_ROK_8703B BIT0 /* Receive DMA OK */
438 /* IMR DW1(0x00B4-00B7) Bit 0-31 */
439 #define IMR_BCNDMAINT7_8703B BIT27 /* Beacon DMA Interrupt 7 */
440 #define IMR_BCNDMAINT6_8703B BIT26 /* Beacon DMA Interrupt 6 */
441 #define IMR_BCNDMAINT5_8703B BIT25 /* Beacon DMA Interrupt 5 */
442 #define IMR_BCNDMAINT4_8703B BIT24 /* Beacon DMA Interrupt 4 */
443 #define IMR_BCNDMAINT3_8703B BIT23 /* Beacon DMA Interrupt 3 */
444 #define IMR_BCNDMAINT2_8703B BIT22 /* Beacon DMA Interrupt 2 */
445 #define IMR_BCNDMAINT1_8703B BIT21 /* Beacon DMA Interrupt 1 */
446 #define IMR_BCNDOK7_8703B BIT20 /* Beacon Queue DMA OK Interrup 7 */
447 #define IMR_BCNDOK6_8703B BIT19 /* Beacon Queue DMA OK Interrup 6 */
448 #define IMR_BCNDOK5_8703B BIT18 /* Beacon Queue DMA OK Interrup 5 */
449 #define IMR_BCNDOK4_8703B BIT17 /* Beacon Queue DMA OK Interrup 4 */
450 #define IMR_BCNDOK3_8703B BIT16 /* Beacon Queue DMA OK Interrup 3 */
451 #define IMR_BCNDOK2_8703B BIT15 /* Beacon Queue DMA OK Interrup 2 */
452 #define IMR_BCNDOK1_8703B BIT14 /* Beacon Queue DMA OK Interrup 1 */
453 #define IMR_ATIMEND_E_8703B BIT13 /* ATIM Window End Extension for Win7 */
454 #define IMR_TXERR_8703B BIT11 /* Tx Error Flag Interrupt Status, write 1 clear. */
455 #define IMR_RXERR_8703B BIT10 /* Rx Error Flag INT Status, Write 1 clear */
456 #define IMR_TXFOVW_8703B BIT9 /* Transmit FIFO Overflow */
457 #define IMR_RXFOVW_8703B BIT8 /* Receive FIFO Overflow */
459 #ifdef CONFIG_PCI_HCI
460 /* #define IMR_RX_MASK (IMR_ROK_8703B|IMR_RDU_8703B|IMR_RXFOVW_8703B) */
461 #define IMR_TX_MASK (IMR_VODOK_8703B | IMR_VIDOK_8703B | IMR_BEDOK_8703B | IMR_BKDOK_8703B | IMR_MGNTDOK_8703B | IMR_HIGHDOK_8703B)
463 #define RT_BCN_INT_MASKS (IMR_BCNDMAINT0_8703B | IMR_TXBCN0OK_8703B | IMR_TXBCN0ERR_8703B | IMR_BCNDERR0_8703B)
465 #define RT_AC_INT_MASKS (IMR_VIDOK_8703B | IMR_VODOK_8703B | IMR_BEDOK_8703B | IMR_BKDOK_8703B)
468 /* ********************************************************
469 * General definitions
470 * ******************************************************** */
472 #define MACID_NUM_8703B 16
473 #define SEC_CAM_ENT_NUM_8703B 16
474 #define HW_PORT_NUM_8703B 2
475 #define NSS_NUM_8703B 1
476 #define BAND_CAP_8703B (BAND_CAP_2G)
477 #define BW_CAP_8703B (BW_CAP_20M | BW_CAP_40M)
478 #define PROTO_CAP_8703B (PROTO_CAP_11B | PROTO_CAP_11G | PROTO_CAP_11N)
480 #endif /* __RTL8703B_SPEC_H__ */
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