drivers/net/wireless/rt2x00/rt2500pci.c

   1 /*
   2         Copyright (C) 2004 - 2008 rt2x00 SourceForge Project
   3         <http://rt2x00.serialmonkey.com>
   4
   5         This program is free software; you can redistribute it and/or modify
   6         it under the terms of the GNU General Public License as published by
   7         the Free Software Foundation; either version 2 of the License, or
   8         (at your option) any later version.
   9
  10         This program is distributed in the hope that it will be useful,
  11         but WITHOUT ANY WARRANTY; without even the implied warranty of
  12         MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13         GNU General Public License for more details.
  14
  15         You should have received a copy of the GNU General Public License
  16         along with this program; if not, write to the
  17         Free Software Foundation, Inc.,
  18         59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  19  */
  20
  21 /*
  22         Module: rt2500pci
  23         Abstract: rt2500pci device specific routines.
  24         Supported chipsets: RT2560.
  25  */
  26
  27 #include <linux/delay.h>
  28 #include <linux/etherdevice.h>
  29 #include <linux/init.h>
  30 #include <linux/kernel.h>
  31 #include <linux/module.h>
  32 #include <linux/pci.h>
  33 #include <linux/eeprom_93cx6.h>
  34
  35 #include "rt2x00.h"
  36 #include "rt2x00pci.h"
  37 #include "rt2500pci.h"
  38
  39 /*
  40  * Register access.
  41  * All access to the CSR registers will go through the methods
  42  * rt2x00pci_register_read and rt2x00pci_register_write.
  43  * BBP and RF register require indirect register access,
  44  * and use the CSR registers BBPCSR and RFCSR to achieve this.
  45  * These indirect registers work with busy bits,
  46  * and we will try maximal REGISTER_BUSY_COUNT times to access
  47  * the register while taking a REGISTER_BUSY_DELAY us delay
  48  * between each attampt. When the busy bit is still set at that time,
  49  * the access attempt is considered to have failed,
  50  * and we will print an error.
  51  */
  52 static u32 rt2500pci_bbp_check(struct rt2x00_dev *rt2x00dev)
  53 {
  54         u32 reg;
  55         unsigned int i;
  56
  57         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
  58                 rt2x00pci_register_read(rt2x00dev, BBPCSR, &reg);
  59                 if (!rt2x00_get_field32(reg, BBPCSR_BUSY))
  60                         break;
  61                 udelay(REGISTER_BUSY_DELAY);
  62         }
  63
  64         return reg;
  65 }
  66
  67 static void rt2500pci_bbp_write(struct rt2x00_dev *rt2x00dev,
  68                                 const unsigned int word, const u8 value)
  69 {
  70         u32 reg;
  71
  72         /*
  73          * Wait until the BBP becomes ready.
  74          */
  75         reg = rt2500pci_bbp_check(rt2x00dev);
  76         if (rt2x00_get_field32(reg, BBPCSR_BUSY)) {
  77                 ERROR(rt2x00dev, "BBPCSR register busy. Write failed.\n");
  78                 return;
  79         }
  80
  81         /*
  82          * Write the data into the BBP.
  83          */
  84         reg = 0;
  85         rt2x00_set_field32(&reg, BBPCSR_VALUE, value);
  86         rt2x00_set_field32(&reg, BBPCSR_REGNUM, word);
  87         rt2x00_set_field32(&reg, BBPCSR_BUSY, 1);
  88         rt2x00_set_field32(&reg, BBPCSR_WRITE_CONTROL, 1);
  89
  90         rt2x00pci_register_write(rt2x00dev, BBPCSR, reg);
  91 }
  92
  93 static void rt2500pci_bbp_read(struct rt2x00_dev *rt2x00dev,
  94                                const unsigned int word, u8 *value)
  95 {
  96         u32 reg;
  97
  98         /*
  99          * Wait until the BBP becomes ready.
 100          */
 101         reg = rt2500pci_bbp_check(rt2x00dev);
 102         if (rt2x00_get_field32(reg, BBPCSR_BUSY)) {
 103                 ERROR(rt2x00dev, "BBPCSR register busy. Read failed.\n");
 104                 return;
 105         }
 106
 107         /*
 108          * Write the request into the BBP.
 109          */
 110         reg = 0;
 111         rt2x00_set_field32(&reg, BBPCSR_REGNUM, word);
 112         rt2x00_set_field32(&reg, BBPCSR_BUSY, 1);
 113         rt2x00_set_field32(&reg, BBPCSR_WRITE_CONTROL, 0);
 114
 115         rt2x00pci_register_write(rt2x00dev, BBPCSR, reg);
 116
 117         /*
 118          * Wait until the BBP becomes ready.
 119          */
 120         reg = rt2500pci_bbp_check(rt2x00dev);
 121         if (rt2x00_get_field32(reg, BBPCSR_BUSY)) {
 122                 ERROR(rt2x00dev, "BBPCSR register busy. Read failed.\n");
 123                 *value = 0xff;
 124                 return;
 125         }
 126
 127         *value = rt2x00_get_field32(reg, BBPCSR_VALUE);
 128 }
 129
 130 static void rt2500pci_rf_write(struct rt2x00_dev *rt2x00dev,
 131                                const unsigned int word, const u32 value)
 132 {
 133         u32 reg;
 134         unsigned int i;
 135
 136         if (!word)
 137                 return;
 138
 139         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
 140                 rt2x00pci_register_read(rt2x00dev, RFCSR, &reg);
 141                 if (!rt2x00_get_field32(reg, RFCSR_BUSY))
 142                         goto rf_write;
 143                 udelay(REGISTER_BUSY_DELAY);
 144         }
 145
 146         ERROR(rt2x00dev, "RFCSR register busy. Write failed.\n");
 147         return;
 148
 149 rf_write:
 150         reg = 0;
 151         rt2x00_set_field32(&reg, RFCSR_VALUE, value);
 152         rt2x00_set_field32(&reg, RFCSR_NUMBER_OF_BITS, 20);
 153         rt2x00_set_field32(&reg, RFCSR_IF_SELECT, 0);
 154         rt2x00_set_field32(&reg, RFCSR_BUSY, 1);
 155
 156         rt2x00pci_register_write(rt2x00dev, RFCSR, reg);
 157         rt2x00_rf_write(rt2x00dev, word, value);
 158 }
 159
 160 static void rt2500pci_eepromregister_read(struct eeprom_93cx6 *eeprom)
 161 {
 162         struct rt2x00_dev *rt2x00dev = eeprom->data;
 163         u32 reg;
 164
 165         rt2x00pci_register_read(rt2x00dev, CSR21, &reg);
 166
 167         eeprom->reg_data_in = !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_IN);
 168         eeprom->reg_data_out = !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_OUT);
 169         eeprom->reg_data_clock =
 170             !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_CLOCK);
 171         eeprom->reg_chip_select =
 172             !!rt2x00_get_field32(reg, CSR21_EEPROM_CHIP_SELECT);
 173 }
 174
 175 static void rt2500pci_eepromregister_write(struct eeprom_93cx6 *eeprom)
 176 {
 177         struct rt2x00_dev *rt2x00dev = eeprom->data;
 178         u32 reg = 0;
 179
 180         rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_IN, !!eeprom->reg_data_in);
 181         rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_OUT, !!eeprom->reg_data_out);
 182         rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_CLOCK,
 183                            !!eeprom->reg_data_clock);
 184         rt2x00_set_field32(&reg, CSR21_EEPROM_CHIP_SELECT,
 185                            !!eeprom->reg_chip_select);
 186
 187         rt2x00pci_register_write(rt2x00dev, CSR21, reg);
 188 }
 189
 190 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
 191 #define CSR_OFFSET(__word)      ( CSR_REG_BASE + ((__word) * sizeof(u32)) )
 192
 193 static void rt2500pci_read_csr(struct rt2x00_dev *rt2x00dev,
 194                                const unsigned int word, u32 *data)
 195 {
 196         rt2x00pci_register_read(rt2x00dev, CSR_OFFSET(word), data);
 197 }
 198
 199 static void rt2500pci_write_csr(struct rt2x00_dev *rt2x00dev,
 200                                 const unsigned int word, u32 data)
 201 {
 202         rt2x00pci_register_write(rt2x00dev, CSR_OFFSET(word), data);
 203 }
 204
 205 static const struct rt2x00debug rt2500pci_rt2x00debug = {
 206         .owner  = THIS_MODULE,
 207         .csr    = {
 208                 .read           = rt2500pci_read_csr,
 209                 .write          = rt2500pci_write_csr,
 210                 .word_size      = sizeof(u32),
 211                 .word_count     = CSR_REG_SIZE / sizeof(u32),
 212         },
 213         .eeprom = {
 214                 .read           = rt2x00_eeprom_read,
 215                 .write          = rt2x00_eeprom_write,
 216                 .word_size      = sizeof(u16),
 217                 .word_count     = EEPROM_SIZE / sizeof(u16),
 218         },
 219         .bbp    = {
 220                 .read           = rt2500pci_bbp_read,
 221                 .write          = rt2500pci_bbp_write,
 222                 .word_size      = sizeof(u8),
 223                 .word_count     = BBP_SIZE / sizeof(u8),
 224         },
 225         .rf     = {
 226                 .read           = rt2x00_rf_read,
 227                 .write          = rt2500pci_rf_write,
 228                 .word_size      = sizeof(u32),
 229                 .word_count     = RF_SIZE / sizeof(u32),
 230         },
 231 };
 232 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
 233
 234 #ifdef CONFIG_RT2X00_LIB_RFKILL
 235 static int rt2500pci_rfkill_poll(struct rt2x00_dev *rt2x00dev)
 236 {
 237         u32 reg;
 238
 239         rt2x00pci_register_read(rt2x00dev, GPIOCSR, &reg);
 240         return rt2x00_get_field32(reg, GPIOCSR_BIT0);
 241 }
 242 #else
 243 #define rt2500pci_rfkill_poll   NULL
 244 #endif /* CONFIG_RT2X00_LIB_RFKILL */
 245
 246 #ifdef CONFIG_RT2X00_LIB_LEDS
 247 static void rt2500pci_brightness_set(struct led_classdev *led_cdev,
 248                                      enum led_brightness brightness)
 249 {
 250         struct rt2x00_led *led =
 251             container_of(led_cdev, struct rt2x00_led, led_dev);
 252         unsigned int enabled = brightness != LED_OFF;
 253         u32 reg;
 254
 255         rt2x00pci_register_read(led->rt2x00dev, LEDCSR, &reg);
 256
 257         if (led->type == LED_TYPE_RADIO || led->type == LED_TYPE_ASSOC)
 258                 rt2x00_set_field32(&reg, LEDCSR_LINK, enabled);
 259         else if (led->type == LED_TYPE_ACTIVITY)
 260                 rt2x00_set_field32(&reg, LEDCSR_ACTIVITY, enabled);
 261
 262         rt2x00pci_register_write(led->rt2x00dev, LEDCSR, reg);
 263 }
 264
 265 static int rt2500pci_blink_set(struct led_classdev *led_cdev,
 266                                unsigned long *delay_on,
 267                                unsigned long *delay_off)
 268 {
 269         struct rt2x00_led *led =
 270             container_of(led_cdev, struct rt2x00_led, led_dev);
 271         u32 reg;
 272
 273         rt2x00pci_register_read(led->rt2x00dev, LEDCSR, &reg);
 274         rt2x00_set_field32(&reg, LEDCSR_ON_PERIOD, *delay_on);
 275         rt2x00_set_field32(&reg, LEDCSR_OFF_PERIOD, *delay_off);
 276         rt2x00pci_register_write(led->rt2x00dev, LEDCSR, reg);
 277
 278         return 0;
 279 }
 280
 281 static void rt2500pci_init_led(struct rt2x00_dev *rt2x00dev,
 282                                struct rt2x00_led *led,
 283                                enum led_type type)
 284 {
 285         led->rt2x00dev = rt2x00dev;
 286         led->type = type;
 287         led->led_dev.brightness_set = rt2500pci_brightness_set;
 288         led->led_dev.blink_set = rt2500pci_blink_set;
 289         led->flags = LED_INITIALIZED;
 290 }
 291 #endif /* CONFIG_RT2X00_LIB_LEDS */
 292
 293 /*
 294  * Configuration handlers.
 295  */
 296 static void rt2500pci_config_filter(struct rt2x00_dev *rt2x00dev,
 297                                     const unsigned int filter_flags)
 298 {
 299         u32 reg;
 300
 301         /*
 302          * Start configuration steps.
 303          * Note that the version error will always be dropped
 304          * and broadcast frames will always be accepted since
 305          * there is no filter for it at this time.
 306          */
 307         rt2x00pci_register_read(rt2x00dev, RXCSR0, &reg);
 308         rt2x00_set_field32(&reg, RXCSR0_DROP_CRC,
 309                            !(filter_flags & FIF_FCSFAIL));
 310         rt2x00_set_field32(&reg, RXCSR0_DROP_PHYSICAL,
 311                            !(filter_flags & FIF_PLCPFAIL));
 312         rt2x00_set_field32(&reg, RXCSR0_DROP_CONTROL,
 313                            !(filter_flags & FIF_CONTROL));
 314         rt2x00_set_field32(&reg, RXCSR0_DROP_NOT_TO_ME,
 315                            !(filter_flags & FIF_PROMISC_IN_BSS));
 316         rt2x00_set_field32(&reg, RXCSR0_DROP_TODS,
 317                            !(filter_flags & FIF_PROMISC_IN_BSS) &&
 318                            !rt2x00dev->intf_ap_count);
 319         rt2x00_set_field32(&reg, RXCSR0_DROP_VERSION_ERROR, 1);
 320         rt2x00_set_field32(&reg, RXCSR0_DROP_MCAST,
 321                            !(filter_flags & FIF_ALLMULTI));
 322         rt2x00_set_field32(&reg, RXCSR0_DROP_BCAST, 0);
 323         rt2x00pci_register_write(rt2x00dev, RXCSR0, reg);
 324 }
 325
 326 static void rt2500pci_config_intf(struct rt2x00_dev *rt2x00dev,
 327                                   struct rt2x00_intf *intf,
 328                                   struct rt2x00intf_conf *conf,
 329                                   const unsigned int flags)
 330 {
 331         struct data_queue *queue = rt2x00queue_get_queue(rt2x00dev, QID_BEACON);
 332         unsigned int bcn_preload;
 333         u32 reg;
 334
 335         if (flags & CONFIG_UPDATE_TYPE) {
 336                 /*
 337                  * Enable beacon config
 338                  */
 339                 bcn_preload = PREAMBLE + get_duration(IEEE80211_HEADER, 20);
 340                 rt2x00pci_register_read(rt2x00dev, BCNCSR1, &reg);
 341                 rt2x00_set_field32(&reg, BCNCSR1_PRELOAD, bcn_preload);
 342                 rt2x00_set_field32(&reg, BCNCSR1_BEACON_CWMIN, queue->cw_min);
 343                 rt2x00pci_register_write(rt2x00dev, BCNCSR1, reg);
 344
 345                 /*
 346                  * Enable synchronisation.
 347                  */
 348                 rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
 349                 rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 1);
 350                 rt2x00_set_field32(&reg, CSR14_TSF_SYNC, conf->sync);
 351                 rt2x00_set_field32(&reg, CSR14_TBCN, 1);
 352                 rt2x00pci_register_write(rt2x00dev, CSR14, reg);
 353         }
 354
 355         if (flags & CONFIG_UPDATE_MAC)
 356                 rt2x00pci_register_multiwrite(rt2x00dev, CSR3,
 357                                               conf->mac, sizeof(conf->mac));
 358
 359         if (flags & CONFIG_UPDATE_BSSID)
 360                 rt2x00pci_register_multiwrite(rt2x00dev, CSR5,
 361                                               conf->bssid, sizeof(conf->bssid));
 362 }
 363
 364 static void rt2500pci_config_erp(struct rt2x00_dev *rt2x00dev,
 365                                  struct rt2x00lib_erp *erp)
 366 {
 367         int preamble_mask;
 368         u32 reg;
 369
 370         /*
 371          * When short preamble is enabled, we should set bit 0x08
 372          */
 373         preamble_mask = erp->short_preamble << 3;
 374
 375         rt2x00pci_register_read(rt2x00dev, TXCSR1, &reg);
 376         rt2x00_set_field32(&reg, TXCSR1_ACK_TIMEOUT,
 377                            erp->ack_timeout);
 378         rt2x00_set_field32(&reg, TXCSR1_ACK_CONSUME_TIME,
 379                            erp->ack_consume_time);
 380         rt2x00pci_register_write(rt2x00dev, TXCSR1, reg);
 381
 382         rt2x00pci_register_read(rt2x00dev, ARCSR2, &reg);
 383         rt2x00_set_field32(&reg, ARCSR2_SIGNAL, 0x00);
 384         rt2x00_set_field32(&reg, ARCSR2_SERVICE, 0x04);
 385         rt2x00_set_field32(&reg, ARCSR2_LENGTH, get_duration(ACK_SIZE, 10));
 386         rt2x00pci_register_write(rt2x00dev, ARCSR2, reg);
 387
 388         rt2x00pci_register_read(rt2x00dev, ARCSR3, &reg);
 389         rt2x00_set_field32(&reg, ARCSR3_SIGNAL, 0x01 | preamble_mask);
 390         rt2x00_set_field32(&reg, ARCSR3_SERVICE, 0x04);
 391         rt2x00_set_field32(&reg, ARCSR2_LENGTH, get_duration(ACK_SIZE, 20));
 392         rt2x00pci_register_write(rt2x00dev, ARCSR3, reg);
 393
 394         rt2x00pci_register_read(rt2x00dev, ARCSR4, &reg);
 395         rt2x00_set_field32(&reg, ARCSR4_SIGNAL, 0x02 | preamble_mask);
 396         rt2x00_set_field32(&reg, ARCSR4_SERVICE, 0x04);
 397         rt2x00_set_field32(&reg, ARCSR2_LENGTH, get_duration(ACK_SIZE, 55));
 398         rt2x00pci_register_write(rt2x00dev, ARCSR4, reg);
 399
 400         rt2x00pci_register_read(rt2x00dev, ARCSR5, &reg);
 401         rt2x00_set_field32(&reg, ARCSR5_SIGNAL, 0x03 | preamble_mask);
 402         rt2x00_set_field32(&reg, ARCSR5_SERVICE, 0x84);
 403         rt2x00_set_field32(&reg, ARCSR2_LENGTH, get_duration(ACK_SIZE, 110));
 404         rt2x00pci_register_write(rt2x00dev, ARCSR5, reg);
 405
 406         rt2x00pci_register_write(rt2x00dev, ARCSR1, erp->basic_rates);
 407
 408         rt2x00pci_register_read(rt2x00dev, CSR11, &reg);
 409         rt2x00_set_field32(&reg, CSR11_SLOT_TIME, erp->slot_time);
 410         rt2x00pci_register_write(rt2x00dev, CSR11, reg);
 411
 412         rt2x00pci_register_read(rt2x00dev, CSR18, &reg);
 413         rt2x00_set_field32(&reg, CSR18_SIFS, erp->sifs);
 414         rt2x00_set_field32(&reg, CSR18_PIFS, erp->pifs);
 415         rt2x00pci_register_write(rt2x00dev, CSR18, reg);
 416
 417         rt2x00pci_register_read(rt2x00dev, CSR19, &reg);
 418         rt2x00_set_field32(&reg, CSR19_DIFS, erp->difs);
 419         rt2x00_set_field32(&reg, CSR19_EIFS, erp->eifs);
 420         rt2x00pci_register_write(rt2x00dev, CSR19, reg);
 421 }
 422
 423 static void rt2500pci_config_ant(struct rt2x00_dev *rt2x00dev,
 424                                  struct antenna_setup *ant)
 425 {
 426         u32 reg;
 427         u8 r14;
 428         u8 r2;
 429
 430         /*
 431          * We should never come here because rt2x00lib is supposed
 432          * to catch this and send us the correct antenna explicitely.
 433          */
 434         BUG_ON(ant->rx == ANTENNA_SW_DIVERSITY ||
 435                ant->tx == ANTENNA_SW_DIVERSITY);
 436
 437         rt2x00pci_register_read(rt2x00dev, BBPCSR1, &reg);
 438         rt2500pci_bbp_read(rt2x00dev, 14, &r14);
 439         rt2500pci_bbp_read(rt2x00dev, 2, &r2);
 440
 441         /*
 442          * Configure the TX antenna.
 443          */
 444         switch (ant->tx) {
 445         case ANTENNA_A:
 446                 rt2x00_set_field8(&r2, BBP_R2_TX_ANTENNA, 0);
 447                 rt2x00_set_field32(&reg, BBPCSR1_CCK, 0);
 448                 rt2x00_set_field32(&reg, BBPCSR1_OFDM, 0);
 449                 break;
 450         case ANTENNA_B:
 451         default:
 452                 rt2x00_set_field8(&r2, BBP_R2_TX_ANTENNA, 2);
 453                 rt2x00_set_field32(&reg, BBPCSR1_CCK, 2);
 454                 rt2x00_set_field32(&reg, BBPCSR1_OFDM, 2);
 455                 break;
 456         }
 457
 458         /*
 459          * Configure the RX antenna.
 460          */
 461         switch (ant->rx) {
 462         case ANTENNA_A:
 463                 rt2x00_set_field8(&r14, BBP_R14_RX_ANTENNA, 0);
 464                 break;
 465         case ANTENNA_B:
 466         default:
 467                 rt2x00_set_field8(&r14, BBP_R14_RX_ANTENNA, 2);
 468                 break;
 469         }
 470
 471         /*
 472          * RT2525E and RT5222 need to flip TX I/Q
 473          */
 474         if (rt2x00_rf(&rt2x00dev->chip, RF2525E) ||
 475             rt2x00_rf(&rt2x00dev->chip, RF5222)) {
 476                 rt2x00_set_field8(&r2, BBP_R2_TX_IQ_FLIP, 1);
 477                 rt2x00_set_field32(&reg, BBPCSR1_CCK_FLIP, 1);
 478                 rt2x00_set_field32(&reg, BBPCSR1_OFDM_FLIP, 1);
 479
 480                 /*
 481                  * RT2525E does not need RX I/Q Flip.
 482                  */
 483                 if (rt2x00_rf(&rt2x00dev->chip, RF2525E))
 484                         rt2x00_set_field8(&r14, BBP_R14_RX_IQ_FLIP, 0);
 485         } else {
 486                 rt2x00_set_field32(&reg, BBPCSR1_CCK_FLIP, 0);
 487                 rt2x00_set_field32(&reg, BBPCSR1_OFDM_FLIP, 0);
 488         }
 489
 490         rt2x00pci_register_write(rt2x00dev, BBPCSR1, reg);
 491         rt2500pci_bbp_write(rt2x00dev, 14, r14);
 492         rt2500pci_bbp_write(rt2x00dev, 2, r2);
 493 }
 494
 495 static void rt2500pci_config_channel(struct rt2x00_dev *rt2x00dev,
 496                                      struct rf_channel *rf, const int txpower)
 497 {
 498         u8 r70;
 499
 500         /*
 501          * Set TXpower.
 502          */
 503         rt2x00_set_field32(&rf->rf3, RF3_TXPOWER, TXPOWER_TO_DEV(txpower));
 504
 505         /*
 506          * Switch on tuning bits.
 507          * For RT2523 devices we do not need to update the R1 register.
 508          */
 509         if (!rt2x00_rf(&rt2x00dev->chip, RF2523))
 510                 rt2x00_set_field32(&rf->rf1, RF1_TUNER, 1);
 511         rt2x00_set_field32(&rf->rf3, RF3_TUNER, 1);
 512
 513         /*
 514          * For RT2525 we should first set the channel to half band higher.
 515          */
 516         if (rt2x00_rf(&rt2x00dev->chip, RF2525)) {
 517                 static const u32 vals[] = {
 518                         0x00080cbe, 0x00080d02, 0x00080d06, 0x00080d0a,
 519                         0x00080d0e, 0x00080d12, 0x00080d16, 0x00080d1a,
 520                         0x00080d1e, 0x00080d22, 0x00080d26, 0x00080d2a,
 521                         0x00080d2e, 0x00080d3a
 522                 };
 523
 524                 rt2500pci_rf_write(rt2x00dev, 1, rf->rf1);
 525                 rt2500pci_rf_write(rt2x00dev, 2, vals[rf->channel - 1]);
 526                 rt2500pci_rf_write(rt2x00dev, 3, rf->rf3);
 527                 if (rf->rf4)
 528                         rt2500pci_rf_write(rt2x00dev, 4, rf->rf4);
 529         }
 530
 531         rt2500pci_rf_write(rt2x00dev, 1, rf->rf1);
 532         rt2500pci_rf_write(rt2x00dev, 2, rf->rf2);
 533         rt2500pci_rf_write(rt2x00dev, 3, rf->rf3);
 534         if (rf->rf4)
 535                 rt2500pci_rf_write(rt2x00dev, 4, rf->rf4);
 536
 537         /*
 538          * Channel 14 requires the Japan filter bit to be set.
 539          */
 540         r70 = 0x46;
 541         rt2x00_set_field8(&r70, BBP_R70_JAPAN_FILTER, rf->channel == 14);
 542         rt2500pci_bbp_write(rt2x00dev, 70, r70);
 543
 544         msleep(1);
 545
 546         /*
 547          * Switch off tuning bits.
 548          * For RT2523 devices we do not need to update the R1 register.
 549          */
 550         if (!rt2x00_rf(&rt2x00dev->chip, RF2523)) {
 551                 rt2x00_set_field32(&rf->rf1, RF1_TUNER, 0);
 552                 rt2500pci_rf_write(rt2x00dev, 1, rf->rf1);
 553         }
 554
 555         rt2x00_set_field32(&rf->rf3, RF3_TUNER, 0);
 556         rt2500pci_rf_write(rt2x00dev, 3, rf->rf3);
 557
 558         /*
 559          * Clear false CRC during channel switch.
 560          */
 561         rt2x00pci_register_read(rt2x00dev, CNT0, &rf->rf1);
 562 }
 563
 564 static void rt2500pci_config_txpower(struct rt2x00_dev *rt2x00dev,
 565                                      const int txpower)
 566 {
 567         u32 rf3;
 568
 569         rt2x00_rf_read(rt2x00dev, 3, &rf3);
 570         rt2x00_set_field32(&rf3, RF3_TXPOWER, TXPOWER_TO_DEV(txpower));
 571         rt2500pci_rf_write(rt2x00dev, 3, rf3);
 572 }
 573
 574 static void rt2500pci_config_retry_limit(struct rt2x00_dev *rt2x00dev,
 575                                          struct rt2x00lib_conf *libconf)
 576 {
 577         u32 reg;
 578
 579         rt2x00pci_register_read(rt2x00dev, CSR11, &reg);
 580         rt2x00_set_field32(&reg, CSR11_LONG_RETRY,
 581                            libconf->conf->long_frame_max_tx_count);
 582         rt2x00_set_field32(&reg, CSR11_SHORT_RETRY,
 583                            libconf->conf->short_frame_max_tx_count);
 584         rt2x00pci_register_write(rt2x00dev, CSR11, reg);
 585 }
 586
 587 static void rt2500pci_config_duration(struct rt2x00_dev *rt2x00dev,
 588                                       struct rt2x00lib_conf *libconf)
 589 {
 590         u32 reg;
 591
 592         rt2x00pci_register_read(rt2x00dev, TXCSR1, &reg);
 593         rt2x00_set_field32(&reg, TXCSR1_TSF_OFFSET, IEEE80211_HEADER);
 594         rt2x00_set_field32(&reg, TXCSR1_AUTORESPONDER, 1);
 595         rt2x00pci_register_write(rt2x00dev, TXCSR1, reg);
 596
 597         rt2x00pci_register_read(rt2x00dev, CSR12, &reg);
 598         rt2x00_set_field32(&reg, CSR12_BEACON_INTERVAL,
 599                            libconf->conf->beacon_int * 16);
 600         rt2x00_set_field32(&reg, CSR12_CFP_MAX_DURATION,
 601                            libconf->conf->beacon_int * 16);
 602         rt2x00pci_register_write(rt2x00dev, CSR12, reg);
 603 }
 604
 605 static void rt2500pci_config(struct rt2x00_dev *rt2x00dev,
 606                              struct rt2x00lib_conf *libconf,
 607                              const unsigned int flags)
 608 {
 609         if (flags & IEEE80211_CONF_CHANGE_CHANNEL)
 610                 rt2500pci_config_channel(rt2x00dev, &libconf->rf,
 611                                          libconf->conf->power_level);
 612         if ((flags & IEEE80211_CONF_CHANGE_POWER) &&
 613             !(flags & IEEE80211_CONF_CHANGE_CHANNEL))
 614                 rt2500pci_config_txpower(rt2x00dev,
 615                                          libconf->conf->power_level);
 616         if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
 617                 rt2500pci_config_retry_limit(rt2x00dev, libconf);
 618         if (flags & IEEE80211_CONF_CHANGE_BEACON_INTERVAL)
 619                 rt2500pci_config_duration(rt2x00dev, libconf);
 620 }
 621
 622 /*
 623  * Link tuning
 624  */
 625 static void rt2500pci_link_stats(struct rt2x00_dev *rt2x00dev,
 626                                  struct link_qual *qual)
 627 {
 628         u32 reg;
 629
 630         /*
 631          * Update FCS error count from register.
 632          */
 633         rt2x00pci_register_read(rt2x00dev, CNT0, &reg);
 634         qual->rx_failed = rt2x00_get_field32(reg, CNT0_FCS_ERROR);
 635
 636         /*
 637          * Update False CCA count from register.
 638          */
 639         rt2x00pci_register_read(rt2x00dev, CNT3, &reg);
 640         qual->false_cca = rt2x00_get_field32(reg, CNT3_FALSE_CCA);
 641 }
 642
 643 static void rt2500pci_reset_tuner(struct rt2x00_dev *rt2x00dev)
 644 {
 645         rt2500pci_bbp_write(rt2x00dev, 17, 0x48);
 646         rt2x00dev->link.vgc_level = 0x48;
 647 }
 648
 649 static void rt2500pci_link_tuner(struct rt2x00_dev *rt2x00dev)
 650 {
 651         int rssi = rt2x00_get_link_rssi(&rt2x00dev->link);
 652         u8 r17;
 653
 654         /*
 655          * To prevent collisions with MAC ASIC on chipsets
 656          * up to version C the link tuning should halt after 20
 657          * seconds while being associated.
 658          */
 659         if (rt2x00_rev(&rt2x00dev->chip) < RT2560_VERSION_D &&
 660             rt2x00dev->intf_associated &&
 661             rt2x00dev->link.count > 20)
 662                 return;
 663
 664         rt2500pci_bbp_read(rt2x00dev, 17, &r17);
 665
 666         /*
 667          * Chipset versions C and lower should directly continue
 668          * to the dynamic CCA tuning. Chipset version D and higher
 669          * should go straight to dynamic CCA tuning when they
 670          * are not associated.
 671          */
 672         if (rt2x00_rev(&rt2x00dev->chip) < RT2560_VERSION_D ||
 673             !rt2x00dev->intf_associated)
 674                 goto dynamic_cca_tune;
 675
 676         /*
 677          * A too low RSSI will cause too much false CCA which will
 678          * then corrupt the R17 tuning. To remidy this the tuning should
 679          * be stopped (While making sure the R17 value will not exceed limits)
 680          */
 681         if (rssi < -80 && rt2x00dev->link.count > 20) {
 682                 if (r17 >= 0x41) {
 683                         r17 = rt2x00dev->link.vgc_level;
 684                         rt2500pci_bbp_write(rt2x00dev, 17, r17);
 685                 }
 686                 return;
 687         }
 688
 689         /*
 690          * Special big-R17 for short distance
 691          */
 692         if (rssi >= -58) {
 693                 if (r17 != 0x50)
 694                         rt2500pci_bbp_write(rt2x00dev, 17, 0x50);
 695                 return;
 696         }
 697
 698         /*
 699          * Special mid-R17 for middle distance
 700          */
 701         if (rssi >= -74) {
 702                 if (r17 != 0x41)
 703                         rt2500pci_bbp_write(rt2x00dev, 17, 0x41);
 704                 return;
 705         }
 706
 707         /*
 708          * Leave short or middle distance condition, restore r17
 709          * to the dynamic tuning range.
 710          */
 711         if (r17 >= 0x41) {
 712                 rt2500pci_bbp_write(rt2x00dev, 17, rt2x00dev->link.vgc_level);
 713                 return;
 714         }
 715
 716 dynamic_cca_tune:
 717
 718         /*
 719          * R17 is inside the dynamic tuning range,
 720          * start tuning the link based on the false cca counter.
 721          */
 722         if (rt2x00dev->link.qual.false_cca > 512 && r17 < 0x40) {
 723                 rt2500pci_bbp_write(rt2x00dev, 17, ++r17);
 724                 rt2x00dev->link.vgc_level = r17;
 725         } else if (rt2x00dev->link.qual.false_cca < 100 && r17 > 0x32) {
 726                 rt2500pci_bbp_write(rt2x00dev, 17, --r17);
 727                 rt2x00dev->link.vgc_level = r17;
 728         }
 729 }
 730
 731 /*
 732  * Initialization functions.
 733  */
 734 static void rt2500pci_init_rxentry(struct rt2x00_dev *rt2x00dev,
 735                                    struct queue_entry *entry)
 736 {
 737         struct queue_entry_priv_pci *entry_priv = entry->priv_data;
 738         struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
 739         u32 word;
 740
 741         rt2x00_desc_read(entry_priv->desc, 1, &word);
 742         rt2x00_set_field32(&word, RXD_W1_BUFFER_ADDRESS, skbdesc->skb_dma);
 743         rt2x00_desc_write(entry_priv->desc, 1, word);
 744
 745         rt2x00_desc_read(entry_priv->desc, 0, &word);
 746         rt2x00_set_field32(&word, RXD_W0_OWNER_NIC, 1);
 747         rt2x00_desc_write(entry_priv->desc, 0, word);
 748 }
 749
 750 static void rt2500pci_init_txentry(struct rt2x00_dev *rt2x00dev,
 751                                    struct queue_entry *entry)
 752 {
 753         struct queue_entry_priv_pci *entry_priv = entry->priv_data;
 754         u32 word;
 755
 756         rt2x00_desc_read(entry_priv->desc, 0, &word);
 757         rt2x00_set_field32(&word, TXD_W0_VALID, 0);
 758         rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 0);
 759         rt2x00_desc_write(entry_priv->desc, 0, word);
 760 }
 761
 762 static int rt2500pci_init_queues(struct rt2x00_dev *rt2x00dev)
 763 {
 764         struct queue_entry_priv_pci *entry_priv;
 765         u32 reg;
 766
 767         /*
 768          * Initialize registers.
 769          */
 770         rt2x00pci_register_read(rt2x00dev, TXCSR2, &reg);
 771         rt2x00_set_field32(&reg, TXCSR2_TXD_SIZE, rt2x00dev->tx[0].desc_size);
 772         rt2x00_set_field32(&reg, TXCSR2_NUM_TXD, rt2x00dev->tx[1].limit);
 773         rt2x00_set_field32(&reg, TXCSR2_NUM_ATIM, rt2x00dev->bcn[1].limit);
 774         rt2x00_set_field32(&reg, TXCSR2_NUM_PRIO, rt2x00dev->tx[0].limit);
 775         rt2x00pci_register_write(rt2x00dev, TXCSR2, reg);
 776
 777         entry_priv = rt2x00dev->tx[1].entries[0].priv_data;
 778         rt2x00pci_register_read(rt2x00dev, TXCSR3, &reg);
 779         rt2x00_set_field32(&reg, TXCSR3_TX_RING_REGISTER,
 780                            entry_priv->desc_dma);
 781         rt2x00pci_register_write(rt2x00dev, TXCSR3, reg);
 782
 783         entry_priv = rt2x00dev->tx[0].entries[0].priv_data;
 784         rt2x00pci_register_read(rt2x00dev, TXCSR5, &reg);
 785         rt2x00_set_field32(&reg, TXCSR5_PRIO_RING_REGISTER,
 786                            entry_priv->desc_dma);
 787         rt2x00pci_register_write(rt2x00dev, TXCSR5, reg);
 788
 789         entry_priv = rt2x00dev->bcn[1].entries[0].priv_data;
 790         rt2x00pci_register_read(rt2x00dev, TXCSR4, &reg);
 791         rt2x00_set_field32(&reg, TXCSR4_ATIM_RING_REGISTER,
 792                            entry_priv->desc_dma);
 793         rt2x00pci_register_write(rt2x00dev, TXCSR4, reg);
 794
 795         entry_priv = rt2x00dev->bcn[0].entries[0].priv_data;
 796         rt2x00pci_register_read(rt2x00dev, TXCSR6, &reg);
 797         rt2x00_set_field32(&reg, TXCSR6_BEACON_RING_REGISTER,
 798                            entry_priv->desc_dma);
 799         rt2x00pci_register_write(rt2x00dev, TXCSR6, reg);
 800
 801         rt2x00pci_register_read(rt2x00dev, RXCSR1, &reg);
 802         rt2x00_set_field32(&reg, RXCSR1_RXD_SIZE, rt2x00dev->rx->desc_size);
 803         rt2x00_set_field32(&reg, RXCSR1_NUM_RXD, rt2x00dev->rx->limit);
 804         rt2x00pci_register_write(rt2x00dev, RXCSR1, reg);
 805
 806         entry_priv = rt2x00dev->rx->entries[0].priv_data;
 807         rt2x00pci_register_read(rt2x00dev, RXCSR2, &reg);
 808         rt2x00_set_field32(&reg, RXCSR2_RX_RING_REGISTER,
 809                            entry_priv->desc_dma);
 810         rt2x00pci_register_write(rt2x00dev, RXCSR2, reg);
 811
 812         return 0;
 813 }
 814
 815 static int rt2500pci_init_registers(struct rt2x00_dev *rt2x00dev)
 816 {
 817         u32 reg;
 818
 819         rt2x00pci_register_write(rt2x00dev, PSCSR0, 0x00020002);
 820         rt2x00pci_register_write(rt2x00dev, PSCSR1, 0x00000002);
 821         rt2x00pci_register_write(rt2x00dev, PSCSR2, 0x00020002);
 822         rt2x00pci_register_write(rt2x00dev, PSCSR3, 0x00000002);
 823
 824         rt2x00pci_register_read(rt2x00dev, TIMECSR, &reg);
 825         rt2x00_set_field32(&reg, TIMECSR_US_COUNT, 33);
 826         rt2x00_set_field32(&reg, TIMECSR_US_64_COUNT, 63);
 827         rt2x00_set_field32(&reg, TIMECSR_BEACON_EXPECT, 0);
 828         rt2x00pci_register_write(rt2x00dev, TIMECSR, reg);
 829
 830         rt2x00pci_register_read(rt2x00dev, CSR9, &reg);
 831         rt2x00_set_field32(&reg, CSR9_MAX_FRAME_UNIT,
 832                            rt2x00dev->rx->data_size / 128);
 833         rt2x00pci_register_write(rt2x00dev, CSR9, reg);
 834
 835         /*
 836          * Always use CWmin and CWmax set in descriptor.
 837          */
 838         rt2x00pci_register_read(rt2x00dev, CSR11, &reg);
 839         rt2x00_set_field32(&reg, CSR11_CW_SELECT, 0);
 840         rt2x00pci_register_write(rt2x00dev, CSR11, reg);
 841
 842         rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
 843         rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 0);
 844         rt2x00_set_field32(&reg, CSR14_TSF_SYNC, 0);
 845         rt2x00_set_field32(&reg, CSR14_TBCN, 0);
 846         rt2x00_set_field32(&reg, CSR14_TCFP, 0);
 847         rt2x00_set_field32(&reg, CSR14_TATIMW, 0);
 848         rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 0);
 849         rt2x00_set_field32(&reg, CSR14_CFP_COUNT_PRELOAD, 0);
 850         rt2x00_set_field32(&reg, CSR14_TBCM_PRELOAD, 0);
 851         rt2x00pci_register_write(rt2x00dev, CSR14, reg);
 852
 853         rt2x00pci_register_write(rt2x00dev, CNT3, 0);
 854
 855         rt2x00pci_register_read(rt2x00dev, TXCSR8, &reg);
 856         rt2x00_set_field32(&reg, TXCSR8_BBP_ID0, 10);
 857         rt2x00_set_field32(&reg, TXCSR8_BBP_ID0_VALID, 1);
 858         rt2x00_set_field32(&reg, TXCSR8_BBP_ID1, 11);
 859         rt2x00_set_field32(&reg, TXCSR8_BBP_ID1_VALID, 1);
 860         rt2x00_set_field32(&reg, TXCSR8_BBP_ID2, 13);
 861         rt2x00_set_field32(&reg, TXCSR8_BBP_ID2_VALID, 1);
 862         rt2x00_set_field32(&reg, TXCSR8_BBP_ID3, 12);
 863         rt2x00_set_field32(&reg, TXCSR8_BBP_ID3_VALID, 1);
 864         rt2x00pci_register_write(rt2x00dev, TXCSR8, reg);
 865
 866         rt2x00pci_register_read(rt2x00dev, ARTCSR0, &reg);
 867         rt2x00_set_field32(&reg, ARTCSR0_ACK_CTS_1MBS, 112);
 868         rt2x00_set_field32(&reg, ARTCSR0_ACK_CTS_2MBS, 56);
 869         rt2x00_set_field32(&reg, ARTCSR0_ACK_CTS_5_5MBS, 20);
 870         rt2x00_set_field32(&reg, ARTCSR0_ACK_CTS_11MBS, 10);
 871         rt2x00pci_register_write(rt2x00dev, ARTCSR0, reg);
 872
 873         rt2x00pci_register_read(rt2x00dev, ARTCSR1, &reg);
 874         rt2x00_set_field32(&reg, ARTCSR1_ACK_CTS_6MBS, 45);
 875         rt2x00_set_field32(&reg, ARTCSR1_ACK_CTS_9MBS, 37);
 876         rt2x00_set_field32(&reg, ARTCSR1_ACK_CTS_12MBS, 33);
 877         rt2x00_set_field32(&reg, ARTCSR1_ACK_CTS_18MBS, 29);
 878         rt2x00pci_register_write(rt2x00dev, ARTCSR1, reg);
 879
 880         rt2x00pci_register_read(rt2x00dev, ARTCSR2, &reg);
 881         rt2x00_set_field32(&reg, ARTCSR2_ACK_CTS_24MBS, 29);
 882         rt2x00_set_field32(&reg, ARTCSR2_ACK_CTS_36MBS, 25);
 883         rt2x00_set_field32(&reg, ARTCSR2_ACK_CTS_48MBS, 25);
 884         rt2x00_set_field32(&reg, ARTCSR2_ACK_CTS_54MBS, 25);
 885         rt2x00pci_register_write(rt2x00dev, ARTCSR2, reg);
 886
 887         rt2x00pci_register_read(rt2x00dev, RXCSR3, &reg);
 888         rt2x00_set_field32(&reg, RXCSR3_BBP_ID0, 47); /* CCK Signal */
 889         rt2x00_set_field32(&reg, RXCSR3_BBP_ID0_VALID, 1);
 890         rt2x00_set_field32(&reg, RXCSR3_BBP_ID1, 51); /* Rssi */
 891         rt2x00_set_field32(&reg, RXCSR3_BBP_ID1_VALID, 1);
 892         rt2x00_set_field32(&reg, RXCSR3_BBP_ID2, 42); /* OFDM Rate */
 893         rt2x00_set_field32(&reg, RXCSR3_BBP_ID2_VALID, 1);
 894         rt2x00_set_field32(&reg, RXCSR3_BBP_ID3, 51); /* RSSI */
 895         rt2x00_set_field32(&reg, RXCSR3_BBP_ID3_VALID, 1);
 896         rt2x00pci_register_write(rt2x00dev, RXCSR3, reg);
 897
 898         rt2x00pci_register_read(rt2x00dev, PCICSR, &reg);
 899         rt2x00_set_field32(&reg, PCICSR_BIG_ENDIAN, 0);
 900         rt2x00_set_field32(&reg, PCICSR_RX_TRESHOLD, 0);
 901         rt2x00_set_field32(&reg, PCICSR_TX_TRESHOLD, 3);
 902         rt2x00_set_field32(&reg, PCICSR_BURST_LENTH, 1);
 903         rt2x00_set_field32(&reg, PCICSR_ENABLE_CLK, 1);
 904         rt2x00_set_field32(&reg, PCICSR_READ_MULTIPLE, 1);
 905         rt2x00_set_field32(&reg, PCICSR_WRITE_INVALID, 1);
 906         rt2x00pci_register_write(rt2x00dev, PCICSR, reg);
 907
 908         rt2x00pci_register_write(rt2x00dev, PWRCSR0, 0x3f3b3100);
 909
 910         rt2x00pci_register_write(rt2x00dev, GPIOCSR, 0x0000ff00);
 911         rt2x00pci_register_write(rt2x00dev, TESTCSR, 0x000000f0);
 912
 913         if (rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_AWAKE))
 914                 return -EBUSY;
 915
 916         rt2x00pci_register_write(rt2x00dev, MACCSR0, 0x00213223);
 917         rt2x00pci_register_write(rt2x00dev, MACCSR1, 0x00235518);
 918
 919         rt2x00pci_register_read(rt2x00dev, MACCSR2, &reg);
 920         rt2x00_set_field32(&reg, MACCSR2_DELAY, 64);
 921         rt2x00pci_register_write(rt2x00dev, MACCSR2, reg);
 922
 923         rt2x00pci_register_read(rt2x00dev, RALINKCSR, &reg);
 924         rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_DATA0, 17);
 925         rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_ID0, 26);
 926         rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_VALID0, 1);
 927         rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_DATA1, 0);
 928         rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_ID1, 26);
 929         rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_VALID1, 1);
 930         rt2x00pci_register_write(rt2x00dev, RALINKCSR, reg);
 931
 932         rt2x00pci_register_write(rt2x00dev, BBPCSR1, 0x82188200);
 933
 934         rt2x00pci_register_write(rt2x00dev, TXACKCSR0, 0x00000020);
 935
 936         rt2x00pci_register_read(rt2x00dev, CSR1, &reg);
 937         rt2x00_set_field32(&reg, CSR1_SOFT_RESET, 1);
 938         rt2x00_set_field32(&reg, CSR1_BBP_RESET, 0);
 939         rt2x00_set_field32(&reg, CSR1_HOST_READY, 0);
 940         rt2x00pci_register_write(rt2x00dev, CSR1, reg);
 941
 942         rt2x00pci_register_read(rt2x00dev, CSR1, &reg);
 943         rt2x00_set_field32(&reg, CSR1_SOFT_RESET, 0);
 944         rt2x00_set_field32(&reg, CSR1_HOST_READY, 1);
 945         rt2x00pci_register_write(rt2x00dev, CSR1, reg);
 946
 947         /*
 948          * We must clear the FCS and FIFO error count.
 949          * These registers are cleared on read,
 950          * so we may pass a useless variable to store the value.
 951          */
 952         rt2x00pci_register_read(rt2x00dev, CNT0, &reg);
 953         rt2x00pci_register_read(rt2x00dev, CNT4, &reg);
 954
 955         return 0;
 956 }
 957
 958 static int rt2500pci_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)
 959 {
 960         unsigned int i;
 961         u8 value;
 962
 963         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
 964                 rt2500pci_bbp_read(rt2x00dev, 0, &value);
 965                 if ((value != 0xff) && (value != 0x00))
 966                         return 0;
 967                 udelay(REGISTER_BUSY_DELAY);
 968         }
 969
 970         ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
 971         return -EACCES;
 972 }
 973
 974 static int rt2500pci_init_bbp(struct rt2x00_dev *rt2x00dev)
 975 {
 976         unsigned int i;
 977         u16 eeprom;
 978         u8 reg_id;
 979         u8 value;
 980
 981         if (unlikely(rt2500pci_wait_bbp_ready(rt2x00dev)))
 982                 return -EACCES;
 983
 984         rt2500pci_bbp_write(rt2x00dev, 3, 0x02);
 985         rt2500pci_bbp_write(rt2x00dev, 4, 0x19);
 986         rt2500pci_bbp_write(rt2x00dev, 14, 0x1c);
 987         rt2500pci_bbp_write(rt2x00dev, 15, 0x30);
 988         rt2500pci_bbp_write(rt2x00dev, 16, 0xac);
 989         rt2500pci_bbp_write(rt2x00dev, 18, 0x18);
 990         rt2500pci_bbp_write(rt2x00dev, 19, 0xff);
 991         rt2500pci_bbp_write(rt2x00dev, 20, 0x1e);
 992         rt2500pci_bbp_write(rt2x00dev, 21, 0x08);
 993         rt2500pci_bbp_write(rt2x00dev, 22, 0x08);
 994         rt2500pci_bbp_write(rt2x00dev, 23, 0x08);
 995         rt2500pci_bbp_write(rt2x00dev, 24, 0x70);
 996         rt2500pci_bbp_write(rt2x00dev, 25, 0x40);
 997         rt2500pci_bbp_write(rt2x00dev, 26, 0x08);
 998         rt2500pci_bbp_write(rt2x00dev, 27, 0x23);
 999         rt2500pci_bbp_write(rt2x00dev, 30, 0x10);
1000         rt2500pci_bbp_write(rt2x00dev, 31, 0x2b);
1001         rt2500pci_bbp_write(rt2x00dev, 32, 0xb9);
1002         rt2500pci_bbp_write(rt2x00dev, 34, 0x12);
1003         rt2500pci_bbp_write(rt2x00dev, 35, 0x50);
1004         rt2500pci_bbp_write(rt2x00dev, 39, 0xc4);
1005         rt2500pci_bbp_write(rt2x00dev, 40, 0x02);
1006         rt2500pci_bbp_write(rt2x00dev, 41, 0x60);
1007         rt2500pci_bbp_write(rt2x00dev, 53, 0x10);
1008         rt2500pci_bbp_write(rt2x00dev, 54, 0x18);
1009         rt2500pci_bbp_write(rt2x00dev, 56, 0x08);
1010         rt2500pci_bbp_write(rt2x00dev, 57, 0x10);
1011         rt2500pci_bbp_write(rt2x00dev, 58, 0x08);
1012         rt2500pci_bbp_write(rt2x00dev, 61, 0x6d);
1013         rt2500pci_bbp_write(rt2x00dev, 62, 0x10);
1014
1015         for (i = 0; i < EEPROM_BBP_SIZE; i++) {
1016                 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
1017
1018                 if (eeprom != 0xffff && eeprom != 0x0000) {
1019                         reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
1020                         value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
1021                         rt2500pci_bbp_write(rt2x00dev, reg_id, value);
1022                 }
1023         }
1024
1025         return 0;
1026 }
1027
1028 /*
1029  * Device state switch handlers.
1030  */
1031 static void rt2500pci_toggle_rx(struct rt2x00_dev *rt2x00dev,
1032                                 enum dev_state state)
1033 {
1034         u32 reg;
1035
1036         rt2x00pci_register_read(rt2x00dev, RXCSR0, &reg);
1037         rt2x00_set_field32(&reg, RXCSR0_DISABLE_RX,
1038                            (state == STATE_RADIO_RX_OFF) ||
1039                            (state == STATE_RADIO_RX_OFF_LINK));
1040         rt2x00pci_register_write(rt2x00dev, RXCSR0, reg);
1041 }
1042
1043 static void rt2500pci_toggle_irq(struct rt2x00_dev *rt2x00dev,
1044                                  enum dev_state state)
1045 {
1046         int mask = (state == STATE_RADIO_IRQ_OFF);
1047         u32 reg;
1048
1049         /*
1050          * When interrupts are being enabled, the interrupt registers
1051          * should clear the register to assure a clean state.
1052          */
1053         if (state == STATE_RADIO_IRQ_ON) {
1054                 rt2x00pci_register_read(rt2x00dev, CSR7, &reg);
1055                 rt2x00pci_register_write(rt2x00dev, CSR7, reg);
1056         }
1057
1058         /*
1059          * Only toggle the interrupts bits we are going to use.
1060          * Non-checked interrupt bits are disabled by default.
1061          */
1062         rt2x00pci_register_read(rt2x00dev, CSR8, &reg);
1063         rt2x00_set_field32(&reg, CSR8_TBCN_EXPIRE, mask);
1064         rt2x00_set_field32(&reg, CSR8_TXDONE_TXRING, mask);
1065         rt2x00_set_field32(&reg, CSR8_TXDONE_ATIMRING, mask);
1066         rt2x00_set_field32(&reg, CSR8_TXDONE_PRIORING, mask);
1067         rt2x00_set_field32(&reg, CSR8_RXDONE, mask);
1068         rt2x00pci_register_write(rt2x00dev, CSR8, reg);
1069 }
1070
1071 static int rt2500pci_enable_radio(struct rt2x00_dev *rt2x00dev)
1072 {
1073         /*
1074          * Initialize all registers.
1075          */
1076         if (unlikely(rt2500pci_init_queues(rt2x00dev) ||
1077                      rt2500pci_init_registers(rt2x00dev) ||
1078                      rt2500pci_init_bbp(rt2x00dev)))
1079                 return -EIO;
1080
1081         return 0;
1082 }
1083
1084 static void rt2500pci_disable_radio(struct rt2x00_dev *rt2x00dev)
1085 {
1086         u32 reg;
1087
1088         rt2x00pci_register_write(rt2x00dev, PWRCSR0, 0);
1089
1090         /*
1091          * Disable synchronisation.
1092          */
1093         rt2x00pci_register_write(rt2x00dev, CSR14, 0);
1094
1095         /*
1096          * Cancel RX and TX.
1097          */
1098         rt2x00pci_register_read(rt2x00dev, TXCSR0, &reg);
1099         rt2x00_set_field32(&reg, TXCSR0_ABORT, 1);
1100         rt2x00pci_register_write(rt2x00dev, TXCSR0, reg);
1101 }
1102
1103 static int rt2500pci_set_state(struct rt2x00_dev *rt2x00dev,
1104                                enum dev_state state)
1105 {
1106         u32 reg;
1107         unsigned int i;
1108         char put_to_sleep;
1109         char bbp_state;
1110         char rf_state;
1111
1112         put_to_sleep = (state != STATE_AWAKE);
1113
1114         rt2x00pci_register_read(rt2x00dev, PWRCSR1, &reg);
1115         rt2x00_set_field32(&reg, PWRCSR1_SET_STATE, 1);
1116         rt2x00_set_field32(&reg, PWRCSR1_BBP_DESIRE_STATE, state);
1117         rt2x00_set_field32(&reg, PWRCSR1_RF_DESIRE_STATE, state);
1118         rt2x00_set_field32(&reg, PWRCSR1_PUT_TO_SLEEP, put_to_sleep);
1119         rt2x00pci_register_write(rt2x00dev, PWRCSR1, reg);
1120
1121         /*
1122          * Device is not guaranteed to be in the requested state yet.
1123          * We must wait until the register indicates that the
1124          * device has entered the correct state.
1125          */
1126         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1127                 rt2x00pci_register_read(rt2x00dev, PWRCSR1, &reg);
1128                 bbp_state = rt2x00_get_field32(reg, PWRCSR1_BBP_CURR_STATE);
1129                 rf_state = rt2x00_get_field32(reg, PWRCSR1_RF_CURR_STATE);
1130                 if (bbp_state == state && rf_state == state)
1131                         return 0;
1132                 msleep(10);
1133         }
1134
1135         return -EBUSY;
1136 }
1137
1138 static int rt2500pci_set_device_state(struct rt2x00_dev *rt2x00dev,
1139                                       enum dev_state state)
1140 {
1141         int retval = 0;
1142
1143         switch (state) {
1144         case STATE_RADIO_ON:
1145                 retval = rt2500pci_enable_radio(rt2x00dev);
1146                 break;
1147         case STATE_RADIO_OFF:
1148                 rt2500pci_disable_radio(rt2x00dev);
1149                 break;
1150         case STATE_RADIO_RX_ON:
1151         case STATE_RADIO_RX_ON_LINK:
1152         case STATE_RADIO_RX_OFF:
1153         case STATE_RADIO_RX_OFF_LINK:
1154                 rt2500pci_toggle_rx(rt2x00dev, state);
1155                 break;
1156         case STATE_RADIO_IRQ_ON:
1157         case STATE_RADIO_IRQ_OFF:
1158                 rt2500pci_toggle_irq(rt2x00dev, state);
1159                 break;
1160         case STATE_DEEP_SLEEP:
1161         case STATE_SLEEP:
1162         case STATE_STANDBY:
1163         case STATE_AWAKE:
1164                 retval = rt2500pci_set_state(rt2x00dev, state);
1165                 break;
1166         default:
1167                 retval = -ENOTSUPP;
1168                 break;
1169         }
1170
1171         if (unlikely(retval))
1172                 ERROR(rt2x00dev, "Device failed to enter state %d (%d).\n",
1173                       state, retval);
1174
1175         return retval;
1176 }
1177
1178 /*
1179  * TX descriptor initialization
1180  */
1181 static void rt2500pci_write_tx_desc(struct rt2x00_dev *rt2x00dev,
1182                                     struct sk_buff *skb,
1183                                     struct txentry_desc *txdesc)
1184 {
1185         struct skb_frame_desc *skbdesc = get_skb_frame_desc(skb);
1186         struct queue_entry_priv_pci *entry_priv = skbdesc->entry->priv_data;
1187         __le32 *txd = skbdesc->desc;
1188         u32 word;
1189
1190         /*
1191          * Start writing the descriptor words.
1192          */
1193         rt2x00_desc_read(entry_priv->desc, 1, &word);
1194         rt2x00_set_field32(&word, TXD_W1_BUFFER_ADDRESS, skbdesc->skb_dma);
1195         rt2x00_desc_write(entry_priv->desc, 1, word);
1196
1197         rt2x00_desc_read(txd, 2, &word);
1198         rt2x00_set_field32(&word, TXD_W2_IV_OFFSET, IEEE80211_HEADER);
1199         rt2x00_set_field32(&word, TXD_W2_AIFS, txdesc->aifs);
1200         rt2x00_set_field32(&word, TXD_W2_CWMIN, txdesc->cw_min);
1201         rt2x00_set_field32(&word, TXD_W2_CWMAX, txdesc->cw_max);
1202         rt2x00_desc_write(txd, 2, word);
1203
1204         rt2x00_desc_read(txd, 3, &word);
1205         rt2x00_set_field32(&word, TXD_W3_PLCP_SIGNAL, txdesc->signal);
1206         rt2x00_set_field32(&word, TXD_W3_PLCP_SERVICE, txdesc->service);
1207         rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_LOW, txdesc->length_low);
1208         rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_HIGH, txdesc->length_high);
1209         rt2x00_desc_write(txd, 3, word);
1210
1211         rt2x00_desc_read(txd, 10, &word);
1212         rt2x00_set_field32(&word, TXD_W10_RTS,
1213                            test_bit(ENTRY_TXD_RTS_FRAME, &txdesc->flags));
1214         rt2x00_desc_write(txd, 10, word);
1215
1216         rt2x00_desc_read(txd, 0, &word);
1217         rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 1);
1218         rt2x00_set_field32(&word, TXD_W0_VALID, 1);
1219         rt2x00_set_field32(&word, TXD_W0_MORE_FRAG,
1220                            test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
1221         rt2x00_set_field32(&word, TXD_W0_ACK,
1222                            test_bit(ENTRY_TXD_ACK, &txdesc->flags));
1223         rt2x00_set_field32(&word, TXD_W0_TIMESTAMP,
1224                            test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
1225         rt2x00_set_field32(&word, TXD_W0_OFDM,
1226                            test_bit(ENTRY_TXD_OFDM_RATE, &txdesc->flags));
1227         rt2x00_set_field32(&word, TXD_W0_CIPHER_OWNER, 1);
1228         rt2x00_set_field32(&word, TXD_W0_IFS, txdesc->ifs);
1229         rt2x00_set_field32(&word, TXD_W0_RETRY_MODE,
1230                            test_bit(ENTRY_TXD_RETRY_MODE, &txdesc->flags));
1231         rt2x00_set_field32(&word, TXD_W0_DATABYTE_COUNT, skb->len);
1232         rt2x00_set_field32(&word, TXD_W0_CIPHER_ALG, CIPHER_NONE);
1233         rt2x00_desc_write(txd, 0, word);
1234 }
1235
1236 /*
1237  * TX data initialization
1238  */
1239 static void rt2500pci_write_beacon(struct queue_entry *entry)
1240 {
1241         struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
1242         struct queue_entry_priv_pci *entry_priv = entry->priv_data;
1243         struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
1244         u32 word;
1245         u32 reg;
1246
1247         /*
1248          * Disable beaconing while we are reloading the beacon data,
1249          * otherwise we might be sending out invalid data.
1250          */
1251         rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
1252         rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 0);
1253         rt2x00_set_field32(&reg, CSR14_TBCN, 0);
1254         rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 0);
1255         rt2x00pci_register_write(rt2x00dev, CSR14, reg);
1256
1257         /*
1258          * Replace rt2x00lib allocated descriptor with the
1259          * pointer to the _real_ hardware descriptor.
1260          * After that, map the beacon to DMA and update the
1261          * descriptor.
1262          */
1263         memcpy(entry_priv->desc, skbdesc->desc, skbdesc->desc_len);
1264         skbdesc->desc = entry_priv->desc;
1265
1266         rt2x00queue_map_txskb(rt2x00dev, entry->skb);
1267
1268         rt2x00_desc_read(entry_priv->desc, 1, &word);
1269         rt2x00_set_field32(&word, TXD_W1_BUFFER_ADDRESS, skbdesc->skb_dma);
1270         rt2x00_desc_write(entry_priv->desc, 1, word);
1271 }
1272
1273 static void rt2500pci_kick_tx_queue(struct rt2x00_dev *rt2x00dev,
1274                                     const enum data_queue_qid queue)
1275 {
1276         u32 reg;
1277
1278         if (queue == QID_BEACON) {
1279                 rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
1280                 if (!rt2x00_get_field32(reg, CSR14_BEACON_GEN)) {
1281                         rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 1);
1282                         rt2x00_set_field32(&reg, CSR14_TBCN, 1);
1283                         rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 1);
1284                         rt2x00pci_register_write(rt2x00dev, CSR14, reg);
1285                 }
1286                 return;
1287         }
1288
1289         rt2x00pci_register_read(rt2x00dev, TXCSR0, &reg);
1290         rt2x00_set_field32(&reg, TXCSR0_KICK_PRIO, (queue == QID_AC_BE));
1291         rt2x00_set_field32(&reg, TXCSR0_KICK_TX, (queue == QID_AC_BK));
1292         rt2x00_set_field32(&reg, TXCSR0_KICK_ATIM, (queue == QID_ATIM));
1293         rt2x00pci_register_write(rt2x00dev, TXCSR0, reg);
1294 }
1295
1296 /*
1297  * RX control handlers
1298  */
1299 static void rt2500pci_fill_rxdone(struct queue_entry *entry,
1300                                   struct rxdone_entry_desc *rxdesc)
1301 {
1302         struct queue_entry_priv_pci *entry_priv = entry->priv_data;
1303         u32 word0;
1304         u32 word2;
1305
1306         rt2x00_desc_read(entry_priv->desc, 0, &word0);
1307         rt2x00_desc_read(entry_priv->desc, 2, &word2);
1308
1309         if (rt2x00_get_field32(word0, RXD_W0_CRC_ERROR))
1310                 rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC;
1311         if (rt2x00_get_field32(word0, RXD_W0_PHYSICAL_ERROR))
1312                 rxdesc->flags |= RX_FLAG_FAILED_PLCP_CRC;
1313
1314         /*
1315          * Obtain the status about this packet.
1316          * When frame was received with an OFDM bitrate,
1317          * the signal is the PLCP value. If it was received with
1318          * a CCK bitrate the signal is the rate in 100kbit/s.
1319          */
1320         rxdesc->signal = rt2x00_get_field32(word2, RXD_W2_SIGNAL);
1321         rxdesc->rssi = rt2x00_get_field32(word2, RXD_W2_RSSI) -
1322             entry->queue->rt2x00dev->rssi_offset;
1323         rxdesc->size = rt2x00_get_field32(word0, RXD_W0_DATABYTE_COUNT);
1324
1325         if (rt2x00_get_field32(word0, RXD_W0_OFDM))
1326                 rxdesc->dev_flags |= RXDONE_SIGNAL_PLCP;
1327         else
1328                 rxdesc->dev_flags |= RXDONE_SIGNAL_BITRATE;
1329         if (rt2x00_get_field32(word0, RXD_W0_MY_BSS))
1330                 rxdesc->dev_flags |= RXDONE_MY_BSS;
1331 }
1332
1333 /*
1334  * Interrupt functions.
1335  */
1336 static void rt2500pci_txdone(struct rt2x00_dev *rt2x00dev,
1337                              const enum data_queue_qid queue_idx)
1338 {
1339         struct data_queue *queue = rt2x00queue_get_queue(rt2x00dev, queue_idx);
1340         struct queue_entry_priv_pci *entry_priv;
1341         struct queue_entry *entry;
1342         struct txdone_entry_desc txdesc;
1343         u32 word;
1344
1345         while (!rt2x00queue_empty(queue)) {
1346                 entry = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
1347                 entry_priv = entry->priv_data;
1348                 rt2x00_desc_read(entry_priv->desc, 0, &word);
1349
1350                 if (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) ||
1351                     !rt2x00_get_field32(word, TXD_W0_VALID))
1352                         break;
1353
1354                 /*
1355                  * Obtain the status about this packet.
1356                  */
1357                 txdesc.flags = 0;
1358                 switch (rt2x00_get_field32(word, TXD_W0_RESULT)) {
1359                 case 0: /* Success */
1360                 case 1: /* Success with retry */
1361                         __set_bit(TXDONE_SUCCESS, &txdesc.flags);
1362                         break;
1363                 case 2: /* Failure, excessive retries */
1364                         __set_bit(TXDONE_EXCESSIVE_RETRY, &txdesc.flags);
1365                         /* Don't break, this is a failed frame! */
1366                 default: /* Failure */
1367                         __set_bit(TXDONE_FAILURE, &txdesc.flags);
1368                 }
1369                 txdesc.retry = rt2x00_get_field32(word, TXD_W0_RETRY_COUNT);
1370
1371                 rt2x00lib_txdone(entry, &txdesc);
1372         }
1373 }
1374
1375 static irqreturn_t rt2500pci_interrupt(int irq, void *dev_instance)
1376 {
1377         struct rt2x00_dev *rt2x00dev = dev_instance;
1378         u32 reg;
1379
1380         /*
1381          * Get the interrupt sources & saved to local variable.
1382          * Write register value back to clear pending interrupts.
1383          */
1384         rt2x00pci_register_read(rt2x00dev, CSR7, &reg);
1385         rt2x00pci_register_write(rt2x00dev, CSR7, reg);
1386
1387         if (!reg)
1388                 return IRQ_NONE;
1389
1390         if (!test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
1391                 return IRQ_HANDLED;
1392
1393         /*
1394          * Handle interrupts, walk through all bits
1395          * and run the tasks, the bits are checked in order of
1396          * priority.
1397          */
1398
1399         /*
1400          * 1 - Beacon timer expired interrupt.
1401          */
1402         if (rt2x00_get_field32(reg, CSR7_TBCN_EXPIRE))
1403                 rt2x00lib_beacondone(rt2x00dev);
1404
1405         /*
1406          * 2 - Rx ring done interrupt.
1407          */
1408         if (rt2x00_get_field32(reg, CSR7_RXDONE))
1409                 rt2x00pci_rxdone(rt2x00dev);
1410
1411         /*
1412          * 3 - Atim ring transmit done interrupt.
1413          */
1414         if (rt2x00_get_field32(reg, CSR7_TXDONE_ATIMRING))
1415                 rt2500pci_txdone(rt2x00dev, QID_ATIM);
1416
1417         /*
1418          * 4 - Priority ring transmit done interrupt.
1419          */
1420         if (rt2x00_get_field32(reg, CSR7_TXDONE_PRIORING))
1421                 rt2500pci_txdone(rt2x00dev, QID_AC_BE);
1422
1423         /*
1424          * 5 - Tx ring transmit done interrupt.
1425          */
1426         if (rt2x00_get_field32(reg, CSR7_TXDONE_TXRING))
1427                 rt2500pci_txdone(rt2x00dev, QID_AC_BK);
1428
1429         return IRQ_HANDLED;
1430 }
1431
1432 /*
1433  * Device probe functions.
1434  */
1435 static int rt2500pci_validate_eeprom(struct rt2x00_dev *rt2x00dev)
1436 {
1437         struct eeprom_93cx6 eeprom;
1438         u32 reg;
1439         u16 word;
1440         u8 *mac;
1441
1442         rt2x00pci_register_read(rt2x00dev, CSR21, &reg);
1443
1444         eeprom.data = rt2x00dev;
1445         eeprom.register_read = rt2500pci_eepromregister_read;
1446         eeprom.register_write = rt2500pci_eepromregister_write;
1447         eeprom.width = rt2x00_get_field32(reg, CSR21_TYPE_93C46) ?
1448             PCI_EEPROM_WIDTH_93C46 : PCI_EEPROM_WIDTH_93C66;
1449         eeprom.reg_data_in = 0;
1450         eeprom.reg_data_out = 0;
1451         eeprom.reg_data_clock = 0;
1452         eeprom.reg_chip_select = 0;
1453
1454         eeprom_93cx6_multiread(&eeprom, EEPROM_BASE, rt2x00dev->eeprom,
1455                                EEPROM_SIZE / sizeof(u16));
1456
1457         /*
1458          * Start validation of the data that has been read.
1459          */
1460         mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
1461         if (!is_valid_ether_addr(mac)) {
1462                 random_ether_addr(mac);
1463                 EEPROM(rt2x00dev, "MAC: %pM\n", mac);
1464         }
1465
1466         rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word);
1467         if (word == 0xffff) {
1468                 rt2x00_set_field16(&word, EEPROM_ANTENNA_NUM, 2);
1469                 rt2x00_set_field16(&word, EEPROM_ANTENNA_TX_DEFAULT,
1470                                    ANTENNA_SW_DIVERSITY);
1471                 rt2x00_set_field16(&word, EEPROM_ANTENNA_RX_DEFAULT,
1472                                    ANTENNA_SW_DIVERSITY);
1473                 rt2x00_set_field16(&word, EEPROM_ANTENNA_LED_MODE,
1474                                    LED_MODE_DEFAULT);
1475                 rt2x00_set_field16(&word, EEPROM_ANTENNA_DYN_TXAGC, 0);
1476                 rt2x00_set_field16(&word, EEPROM_ANTENNA_HARDWARE_RADIO, 0);
1477                 rt2x00_set_field16(&word, EEPROM_ANTENNA_RF_TYPE, RF2522);
1478                 rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
1479                 EEPROM(rt2x00dev, "Antenna: 0x%04x\n", word);
1480         }
1481
1482         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &word);
1483         if (word == 0xffff) {
1484                 rt2x00_set_field16(&word, EEPROM_NIC_CARDBUS_ACCEL, 0);
1485                 rt2x00_set_field16(&word, EEPROM_NIC_DYN_BBP_TUNE, 0);
1486                 rt2x00_set_field16(&word, EEPROM_NIC_CCK_TX_POWER, 0);
1487                 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC, word);
1488                 EEPROM(rt2x00dev, "NIC: 0x%04x\n", word);
1489         }
1490
1491         rt2x00_eeprom_read(rt2x00dev, EEPROM_CALIBRATE_OFFSET, &word);
1492         if (word == 0xffff) {
1493                 rt2x00_set_field16(&word, EEPROM_CALIBRATE_OFFSET_RSSI,
1494                                    DEFAULT_RSSI_OFFSET);
1495                 rt2x00_eeprom_write(rt2x00dev, EEPROM_CALIBRATE_OFFSET, word);
1496                 EEPROM(rt2x00dev, "Calibrate offset: 0x%04x\n", word);
1497         }
1498
1499         return 0;
1500 }
1501
1502 static int rt2500pci_init_eeprom(struct rt2x00_dev *rt2x00dev)
1503 {
1504         u32 reg;
1505         u16 value;
1506         u16 eeprom;
1507
1508         /*
1509          * Read EEPROM word for configuration.
1510          */
1511         rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
1512
1513         /*
1514          * Identify RF chipset.
1515          */
1516         value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
1517         rt2x00pci_register_read(rt2x00dev, CSR0, &reg);
1518         rt2x00_set_chip(rt2x00dev, RT2560, value, reg);
1519
1520         if (!rt2x00_rf(&rt2x00dev->chip, RF2522) &&
1521             !rt2x00_rf(&rt2x00dev->chip, RF2523) &&
1522             !rt2x00_rf(&rt2x00dev->chip, RF2524) &&
1523             !rt2x00_rf(&rt2x00dev->chip, RF2525) &&
1524             !rt2x00_rf(&rt2x00dev->chip, RF2525E) &&
1525             !rt2x00_rf(&rt2x00dev->chip, RF5222)) {
1526                 ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
1527                 return -ENODEV;
1528         }
1529
1530         /*
1531          * Identify default antenna configuration.
1532          */
1533         rt2x00dev->default_ant.tx =
1534             rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TX_DEFAULT);
1535         rt2x00dev->default_ant.rx =
1536             rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_DEFAULT);
1537
1538         /*
1539          * Store led mode, for correct led behaviour.
1540          */
1541 #ifdef CONFIG_RT2X00_LIB_LEDS
1542         value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_LED_MODE);
1543
1544         rt2500pci_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO);
1545         if (value == LED_MODE_TXRX_ACTIVITY)
1546                 rt2500pci_init_led(rt2x00dev, &rt2x00dev->led_qual,
1547                                    LED_TYPE_ACTIVITY);
1548 #endif /* CONFIG_RT2X00_LIB_LEDS */
1549
1550         /*
1551          * Detect if this device has an hardware controlled radio.
1552          */
1553 #ifdef CONFIG_RT2X00_LIB_RFKILL
1554         if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_HARDWARE_RADIO))
1555                 __set_bit(CONFIG_SUPPORT_HW_BUTTON, &rt2x00dev->flags);
1556 #endif /* CONFIG_RT2X00_LIB_RFKILL */
1557
1558         /*
1559          * Check if the BBP tuning should be enabled.
1560          */
1561         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
1562
1563         if (rt2x00_get_field16(eeprom, EEPROM_NIC_DYN_BBP_TUNE))
1564                 __set_bit(CONFIG_DISABLE_LINK_TUNING, &rt2x00dev->flags);
1565
1566         /*
1567          * Read the RSSI <-> dBm offset information.
1568          */
1569         rt2x00_eeprom_read(rt2x00dev, EEPROM_CALIBRATE_OFFSET, &eeprom);
1570         rt2x00dev->rssi_offset =
1571             rt2x00_get_field16(eeprom, EEPROM_CALIBRATE_OFFSET_RSSI);
1572
1573         return 0;
1574 }
1575
1576 /*
1577  * RF value list for RF2522
1578  * Supports: 2.4 GHz
1579  */
1580 static const struct rf_channel rf_vals_bg_2522[] = {
1581         { 1,  0x00002050, 0x000c1fda, 0x00000101, 0 },
1582         { 2,  0x00002050, 0x000c1fee, 0x00000101, 0 },
1583         { 3,  0x00002050, 0x000c2002, 0x00000101, 0 },
1584         { 4,  0x00002050, 0x000c2016, 0x00000101, 0 },
1585         { 5,  0x00002050, 0x000c202a, 0x00000101, 0 },
1586         { 6,  0x00002050, 0x000c203e, 0x00000101, 0 },
1587         { 7,  0x00002050, 0x000c2052, 0x00000101, 0 },
1588         { 8,  0x00002050, 0x000c2066, 0x00000101, 0 },
1589         { 9,  0x00002050, 0x000c207a, 0x00000101, 0 },
1590         { 10, 0x00002050, 0x000c208e, 0x00000101, 0 },
1591         { 11, 0x00002050, 0x000c20a2, 0x00000101, 0 },
1592         { 12, 0x00002050, 0x000c20b6, 0x00000101, 0 },
1593         { 13, 0x00002050, 0x000c20ca, 0x00000101, 0 },
1594         { 14, 0x00002050, 0x000c20fa, 0x00000101, 0 },
1595 };
1596
1597 /*
1598  * RF value list for RF2523
1599  * Supports: 2.4 GHz
1600  */
1601 static const struct rf_channel rf_vals_bg_2523[] = {
1602         { 1,  0x00022010, 0x00000c9e, 0x000e0111, 0x00000a1b },
1603         { 2,  0x00022010, 0x00000ca2, 0x000e0111, 0x00000a1b },
1604         { 3,  0x00022010, 0x00000ca6, 0x000e0111, 0x00000a1b },
1605         { 4,  0x00022010, 0x00000caa, 0x000e0111, 0x00000a1b },
1606         { 5,  0x00022010, 0x00000cae, 0x000e0111, 0x00000a1b },
1607         { 6,  0x00022010, 0x00000cb2, 0x000e0111, 0x00000a1b },
1608         { 7,  0x00022010, 0x00000cb6, 0x000e0111, 0x00000a1b },
1609         { 8,  0x00022010, 0x00000cba, 0x000e0111, 0x00000a1b },
1610         { 9,  0x00022010, 0x00000cbe, 0x000e0111, 0x00000a1b },
1611         { 10, 0x00022010, 0x00000d02, 0x000e0111, 0x00000a1b },
1612         { 11, 0x00022010, 0x00000d06, 0x000e0111, 0x00000a1b },
1613         { 12, 0x00022010, 0x00000d0a, 0x000e0111, 0x00000a1b },
1614         { 13, 0x00022010, 0x00000d0e, 0x000e0111, 0x00000a1b },
1615         { 14, 0x00022010, 0x00000d1a, 0x000e0111, 0x00000a03 },
1616 };
1617
1618 /*
1619  * RF value list for RF2524
1620  * Supports: 2.4 GHz
1621  */
1622 static const struct rf_channel rf_vals_bg_2524[] = {
1623         { 1,  0x00032020, 0x00000c9e, 0x00000101, 0x00000a1b },
1624         { 2,  0x00032020, 0x00000ca2, 0x00000101, 0x00000a1b },
1625         { 3,  0x00032020, 0x00000ca6, 0x00000101, 0x00000a1b },
1626         { 4,  0x00032020, 0x00000caa, 0x00000101, 0x00000a1b },
1627         { 5,  0x00032020, 0x00000cae, 0x00000101, 0x00000a1b },
1628         { 6,  0x00032020, 0x00000cb2, 0x00000101, 0x00000a1b },
1629         { 7,  0x00032020, 0x00000cb6, 0x00000101, 0x00000a1b },
1630         { 8,  0x00032020, 0x00000cba, 0x00000101, 0x00000a1b },
1631         { 9,  0x00032020, 0x00000cbe, 0x00000101, 0x00000a1b },
1632         { 10, 0x00032020, 0x00000d02, 0x00000101, 0x00000a1b },
1633         { 11, 0x00032020, 0x00000d06, 0x00000101, 0x00000a1b },
1634         { 12, 0x00032020, 0x00000d0a, 0x00000101, 0x00000a1b },
1635         { 13, 0x00032020, 0x00000d0e, 0x00000101, 0x00000a1b },
1636         { 14, 0x00032020, 0x00000d1a, 0x00000101, 0x00000a03 },
1637 };
1638
1639 /*
1640  * RF value list for RF2525
1641  * Supports: 2.4 GHz
1642  */
1643 static const struct rf_channel rf_vals_bg_2525[] = {
1644         { 1,  0x00022020, 0x00080c9e, 0x00060111, 0x00000a1b },
1645         { 2,  0x00022020, 0x00080ca2, 0x00060111, 0x00000a1b },
1646         { 3,  0x00022020, 0x00080ca6, 0x00060111, 0x00000a1b },
1647         { 4,  0x00022020, 0x00080caa, 0x00060111, 0x00000a1b },
1648         { 5,  0x00022020, 0x00080cae, 0x00060111, 0x00000a1b },
1649         { 6,  0x00022020, 0x00080cb2, 0x00060111, 0x00000a1b },
1650         { 7,  0x00022020, 0x00080cb6, 0x00060111, 0x00000a1b },
1651         { 8,  0x00022020, 0x00080cba, 0x00060111, 0x00000a1b },
1652         { 9,  0x00022020, 0x00080cbe, 0x00060111, 0x00000a1b },
1653         { 10, 0x00022020, 0x00080d02, 0x00060111, 0x00000a1b },
1654         { 11, 0x00022020, 0x00080d06, 0x00060111, 0x00000a1b },
1655         { 12, 0x00022020, 0x00080d0a, 0x00060111, 0x00000a1b },
1656         { 13, 0x00022020, 0x00080d0e, 0x00060111, 0x00000a1b },
1657         { 14, 0x00022020, 0x00080d1a, 0x00060111, 0x00000a03 },
1658 };
1659
1660 /*
1661  * RF value list for RF2525e
1662  * Supports: 2.4 GHz
1663  */
1664 static const struct rf_channel rf_vals_bg_2525e[] = {
1665         { 1,  0x00022020, 0x00081136, 0x00060111, 0x00000a0b },
1666         { 2,  0x00022020, 0x0008113a, 0x00060111, 0x00000a0b },
1667         { 3,  0x00022020, 0x0008113e, 0x00060111, 0x00000a0b },
1668         { 4,  0x00022020, 0x00081182, 0x00060111, 0x00000a0b },
1669         { 5,  0x00022020, 0x00081186, 0x00060111, 0x00000a0b },
1670         { 6,  0x00022020, 0x0008118a, 0x00060111, 0x00000a0b },
1671         { 7,  0x00022020, 0x0008118e, 0x00060111, 0x00000a0b },
1672         { 8,  0x00022020, 0x00081192, 0x00060111, 0x00000a0b },
1673         { 9,  0x00022020, 0x00081196, 0x00060111, 0x00000a0b },
1674         { 10, 0x00022020, 0x0008119a, 0x00060111, 0x00000a0b },
1675         { 11, 0x00022020, 0x0008119e, 0x00060111, 0x00000a0b },
1676         { 12, 0x00022020, 0x000811a2, 0x00060111, 0x00000a0b },
1677         { 13, 0x00022020, 0x000811a6, 0x00060111, 0x00000a0b },
1678         { 14, 0x00022020, 0x000811ae, 0x00060111, 0x00000a1b },
1679 };
1680
1681 /*
1682  * RF value list for RF5222
1683  * Supports: 2.4 GHz & 5.2 GHz
1684  */
1685 static const struct rf_channel rf_vals_5222[] = {
1686         { 1,  0x00022020, 0x00001136, 0x00000101, 0x00000a0b },
1687         { 2,  0x00022020, 0x0000113a, 0x00000101, 0x00000a0b },
1688         { 3,  0x00022020, 0x0000113e, 0x00000101, 0x00000a0b },
1689         { 4,  0x00022020, 0x00001182, 0x00000101, 0x00000a0b },
1690         { 5,  0x00022020, 0x00001186, 0x00000101, 0x00000a0b },
1691         { 6,  0x00022020, 0x0000118a, 0x00000101, 0x00000a0b },
1692         { 7,  0x00022020, 0x0000118e, 0x00000101, 0x00000a0b },
1693         { 8,  0x00022020, 0x00001192, 0x00000101, 0x00000a0b },
1694         { 9,  0x00022020, 0x00001196, 0x00000101, 0x00000a0b },
1695         { 10, 0x00022020, 0x0000119a, 0x00000101, 0x00000a0b },
1696         { 11, 0x00022020, 0x0000119e, 0x00000101, 0x00000a0b },
1697         { 12, 0x00022020, 0x000011a2, 0x00000101, 0x00000a0b },
1698         { 13, 0x00022020, 0x000011a6, 0x00000101, 0x00000a0b },
1699         { 14, 0x00022020, 0x000011ae, 0x00000101, 0x00000a1b },
1700
1701         /* 802.11 UNI / HyperLan 2 */
1702         { 36, 0x00022010, 0x00018896, 0x00000101, 0x00000a1f },
1703         { 40, 0x00022010, 0x0001889a, 0x00000101, 0x00000a1f },
1704         { 44, 0x00022010, 0x0001889e, 0x00000101, 0x00000a1f },
1705         { 48, 0x00022010, 0x000188a2, 0x00000101, 0x00000a1f },
1706         { 52, 0x00022010, 0x000188a6, 0x00000101, 0x00000a1f },
1707         { 66, 0x00022010, 0x000188aa, 0x00000101, 0x00000a1f },
1708         { 60, 0x00022010, 0x000188ae, 0x00000101, 0x00000a1f },
1709         { 64, 0x00022010, 0x000188b2, 0x00000101, 0x00000a1f },
1710
1711         /* 802.11 HyperLan 2 */
1712         { 100, 0x00022010, 0x00008802, 0x00000101, 0x00000a0f },
1713         { 104, 0x00022010, 0x00008806, 0x00000101, 0x00000a0f },
1714         { 108, 0x00022010, 0x0000880a, 0x00000101, 0x00000a0f },
1715         { 112, 0x00022010, 0x0000880e, 0x00000101, 0x00000a0f },
1716         { 116, 0x00022010, 0x00008812, 0x00000101, 0x00000a0f },
1717         { 120, 0x00022010, 0x00008816, 0x00000101, 0x00000a0f },
1718         { 124, 0x00022010, 0x0000881a, 0x00000101, 0x00000a0f },
1719         { 128, 0x00022010, 0x0000881e, 0x00000101, 0x00000a0f },
1720         { 132, 0x00022010, 0x00008822, 0x00000101, 0x00000a0f },
1721         { 136, 0x00022010, 0x00008826, 0x00000101, 0x00000a0f },
1722
1723         /* 802.11 UNII */
1724         { 140, 0x00022010, 0x0000882a, 0x00000101, 0x00000a0f },
1725         { 149, 0x00022020, 0x000090a6, 0x00000101, 0x00000a07 },
1726         { 153, 0x00022020, 0x000090ae, 0x00000101, 0x00000a07 },
1727         { 157, 0x00022020, 0x000090b6, 0x00000101, 0x00000a07 },
1728         { 161, 0x00022020, 0x000090be, 0x00000101, 0x00000a07 },
1729 };
1730
1731 static int rt2500pci_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
1732 {
1733         struct hw_mode_spec *spec = &rt2x00dev->spec;
1734         struct channel_info *info;
1735         char *tx_power;
1736         unsigned int i;
1737
1738         /*
1739          * Initialize all hw fields.
1740          */
1741         rt2x00dev->hw->flags = IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
1742                                IEEE80211_HW_SIGNAL_DBM;
1743
1744         rt2x00dev->hw->extra_tx_headroom = 0;
1745
1746         SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev);
1747         SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
1748                                 rt2x00_eeprom_addr(rt2x00dev,
1749                                                    EEPROM_MAC_ADDR_0));
1750
1751         /*
1752          * Initialize hw_mode information.
1753          */
1754         spec->supported_bands = SUPPORT_BAND_2GHZ;
1755         spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM;
1756
1757         if (rt2x00_rf(&rt2x00dev->chip, RF2522)) {
1758                 spec->num_channels = ARRAY_SIZE(rf_vals_bg_2522);
1759                 spec->channels = rf_vals_bg_2522;
1760         } else if (rt2x00_rf(&rt2x00dev->chip, RF2523)) {
1761                 spec->num_channels = ARRAY_SIZE(rf_vals_bg_2523);
1762                 spec->channels = rf_vals_bg_2523;
1763         } else if (rt2x00_rf(&rt2x00dev->chip, RF2524)) {
1764                 spec->num_channels = ARRAY_SIZE(rf_vals_bg_2524);
1765                 spec->channels = rf_vals_bg_2524;
1766         } else if (rt2x00_rf(&rt2x00dev->chip, RF2525)) {
1767                 spec->num_channels = ARRAY_SIZE(rf_vals_bg_2525);
1768                 spec->channels = rf_vals_bg_2525;
1769         } else if (rt2x00_rf(&rt2x00dev->chip, RF2525E)) {
1770                 spec->num_channels = ARRAY_SIZE(rf_vals_bg_2525e);
1771                 spec->channels = rf_vals_bg_2525e;
1772         } else if (rt2x00_rf(&rt2x00dev->chip, RF5222)) {
1773                 spec->supported_bands |= SUPPORT_BAND_5GHZ;
1774                 spec->num_channels = ARRAY_SIZE(rf_vals_5222);
1775                 spec->channels = rf_vals_5222;
1776         }
1777
1778         /*
1779          * Create channel information array
1780          */
1781         info = kzalloc(spec->num_channels * sizeof(*info), GFP_KERNEL);
1782         if (!info)
1783                 return -ENOMEM;
1784
1785         spec->channels_info = info;
1786
1787         tx_power = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_START);
1788         for (i = 0; i < 14; i++)
1789                 info[i].tx_power1 = TXPOWER_FROM_DEV(tx_power[i]);
1790
1791         if (spec->num_channels > 14) {
1792                 for (i = 14; i < spec->num_channels; i++)
1793                         info[i].tx_power1 = DEFAULT_TXPOWER;
1794         }
1795
1796         return 0;
1797 }
1798
1799 static int rt2500pci_probe_hw(struct rt2x00_dev *rt2x00dev)
1800 {
1801         int retval;
1802
1803         /*
1804          * Allocate eeprom data.
1805          */
1806         retval = rt2500pci_validate_eeprom(rt2x00dev);
1807         if (retval)
1808                 return retval;
1809
1810         retval = rt2500pci_init_eeprom(rt2x00dev);
1811         if (retval)
1812                 return retval;
1813
1814         /*
1815          * Initialize hw specifications.
1816          */
1817         retval = rt2500pci_probe_hw_mode(rt2x00dev);
1818         if (retval)
1819                 return retval;
1820
1821         /*
1822          * This device requires the atim queue and DMA-mapped skbs.
1823          */
1824         __set_bit(DRIVER_REQUIRE_ATIM_QUEUE, &rt2x00dev->flags);
1825         __set_bit(DRIVER_REQUIRE_DMA, &rt2x00dev->flags);
1826
1827         /*
1828          * Set the rssi offset.
1829          */
1830         rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
1831
1832         return 0;
1833 }
1834
1835 /*
1836  * IEEE80211 stack callback functions.
1837  */
1838 static u64 rt2500pci_get_tsf(struct ieee80211_hw *hw)
1839 {
1840         struct rt2x00_dev *rt2x00dev = hw->priv;
1841         u64 tsf;
1842         u32 reg;
1843
1844         rt2x00pci_register_read(rt2x00dev, CSR17, &reg);
1845         tsf = (u64) rt2x00_get_field32(reg, CSR17_HIGH_TSFTIMER) << 32;
1846         rt2x00pci_register_read(rt2x00dev, CSR16, &reg);
1847         tsf |= rt2x00_get_field32(reg, CSR16_LOW_TSFTIMER);
1848
1849         return tsf;
1850 }
1851
1852 static int rt2500pci_tx_last_beacon(struct ieee80211_hw *hw)
1853 {
1854         struct rt2x00_dev *rt2x00dev = hw->priv;
1855         u32 reg;
1856
1857         rt2x00pci_register_read(rt2x00dev, CSR15, &reg);
1858         return rt2x00_get_field32(reg, CSR15_BEACON_SENT);
1859 }
1860
1861 static const struct ieee80211_ops rt2500pci_mac80211_ops = {
1862         .tx                     = rt2x00mac_tx,
1863         .start                  = rt2x00mac_start,
1864         .stop                   = rt2x00mac_stop,
1865         .add_interface          = rt2x00mac_add_interface,
1866         .remove_interface       = rt2x00mac_remove_interface,
1867         .config                 = rt2x00mac_config,
1868         .config_interface       = rt2x00mac_config_interface,
1869         .configure_filter       = rt2x00mac_configure_filter,
1870         .get_stats              = rt2x00mac_get_stats,
1871         .bss_info_changed       = rt2x00mac_bss_info_changed,
1872         .conf_tx                = rt2x00mac_conf_tx,
1873         .get_tx_stats           = rt2x00mac_get_tx_stats,
1874         .get_tsf                = rt2500pci_get_tsf,
1875         .tx_last_beacon         = rt2500pci_tx_last_beacon,
1876 };
1877
1878 static const struct rt2x00lib_ops rt2500pci_rt2x00_ops = {
1879         .irq_handler            = rt2500pci_interrupt,
1880         .probe_hw               = rt2500pci_probe_hw,
1881         .initialize             = rt2x00pci_initialize,
1882         .uninitialize           = rt2x00pci_uninitialize,
1883         .init_rxentry           = rt2500pci_init_rxentry,
1884         .init_txentry           = rt2500pci_init_txentry,
1885         .set_device_state       = rt2500pci_set_device_state,
1886         .rfkill_poll            = rt2500pci_rfkill_poll,
1887         .link_stats             = rt2500pci_link_stats,
1888         .reset_tuner            = rt2500pci_reset_tuner,
1889         .link_tuner             = rt2500pci_link_tuner,
1890         .write_tx_desc          = rt2500pci_write_tx_desc,
1891         .write_tx_data          = rt2x00pci_write_tx_data,
1892         .write_beacon           = rt2500pci_write_beacon,
1893         .kick_tx_queue          = rt2500pci_kick_tx_queue,
1894         .fill_rxdone            = rt2500pci_fill_rxdone,
1895         .config_filter          = rt2500pci_config_filter,
1896         .config_intf            = rt2500pci_config_intf,
1897         .config_erp             = rt2500pci_config_erp,
1898         .config_ant             = rt2500pci_config_ant,
1899         .config                 = rt2500pci_config,
1900 };
1901
1902 static const struct data_queue_desc rt2500pci_queue_rx = {
1903         .entry_num              = RX_ENTRIES,
1904         .data_size              = DATA_FRAME_SIZE,
1905         .desc_size              = RXD_DESC_SIZE,
1906         .priv_size              = sizeof(struct queue_entry_priv_pci),
1907 };
1908
1909 static const struct data_queue_desc rt2500pci_queue_tx = {
1910         .entry_num              = TX_ENTRIES,
1911         .data_size              = DATA_FRAME_SIZE,
1912         .desc_size              = TXD_DESC_SIZE,
1913         .priv_size              = sizeof(struct queue_entry_priv_pci),
1914 };
1915
1916 static const struct data_queue_desc rt2500pci_queue_bcn = {
1917         .entry_num              = BEACON_ENTRIES,
1918         .data_size              = MGMT_FRAME_SIZE,
1919         .desc_size              = TXD_DESC_SIZE,
1920         .priv_size              = sizeof(struct queue_entry_priv_pci),
1921 };
1922
1923 static const struct data_queue_desc rt2500pci_queue_atim = {
1924         .entry_num              = ATIM_ENTRIES,
1925         .data_size              = DATA_FRAME_SIZE,
1926         .desc_size              = TXD_DESC_SIZE,
1927         .priv_size              = sizeof(struct queue_entry_priv_pci),
1928 };
1929
1930 static const struct rt2x00_ops rt2500pci_ops = {
1931         .name           = KBUILD_MODNAME,
1932         .max_sta_intf   = 1,
1933         .max_ap_intf    = 1,
1934         .eeprom_size    = EEPROM_SIZE,
1935         .rf_size        = RF_SIZE,
1936         .tx_queues      = NUM_TX_QUEUES,
1937         .rx             = &rt2500pci_queue_rx,
1938         .tx             = &rt2500pci_queue_tx,
1939         .bcn            = &rt2500pci_queue_bcn,
1940         .atim           = &rt2500pci_queue_atim,
1941         .lib            = &rt2500pci_rt2x00_ops,
1942         .hw             = &rt2500pci_mac80211_ops,
1943 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
1944         .debugfs        = &rt2500pci_rt2x00debug,
1945 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
1946 };
1947
1948 /*
1949  * RT2500pci module information.
1950  */
1951 static struct pci_device_id rt2500pci_device_table[] = {
1952         { PCI_DEVICE(0x1814, 0x0201), PCI_DEVICE_DATA(&rt2500pci_ops) },
1953         { 0, }
1954 };
1955
1956 MODULE_AUTHOR(DRV_PROJECT);
1957 MODULE_VERSION(DRV_VERSION);
1958 MODULE_DESCRIPTION("Ralink RT2500 PCI & PCMCIA Wireless LAN driver.");
1959 MODULE_SUPPORTED_DEVICE("Ralink RT2560 PCI & PCMCIA chipset based cards");
1960 MODULE_DEVICE_TABLE(pci, rt2500pci_device_table);
1961 MODULE_LICENSE("GPL");
1962
1963 static struct pci_driver rt2500pci_driver = {
1964         .name           = KBUILD_MODNAME,
1965         .id_table       = rt2500pci_device_table,
1966         .probe          = rt2x00pci_probe,
1967         .remove         = __devexit_p(rt2x00pci_remove),
1968         .suspend        = rt2x00pci_suspend,
1969         .resume         = rt2x00pci_resume,
1970 };
1971
1972 static int __init rt2500pci_init(void)
1973 {
1974         return pci_register_driver(&rt2500pci_driver);
1975 }
1976
1977 static void __exit rt2500pci_exit(void)
1978 {
1979         pci_unregister_driver(&rt2500pci_driver);
1980 }
1981
1982 module_init(rt2500pci_init);
1983 module_exit(rt2500pci_exit);