drivers/net/wireless/rt2x00/rt2800lib.c

   1 /*
   2         Copyright (C) 2010 Willow Garage <http://www.willowgarage.com>
   3         Copyright (C) 2010 Ivo van Doorn <IvDoorn@gmail.com>
   4         Copyright (C) 2009 Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>
   5         Copyright (C) 2009 Gertjan van Wingerde <gwingerde@gmail.com>
   6
   7         Based on the original rt2800pci.c and rt2800usb.c.
   8           Copyright (C) 2009 Alban Browaeys <prahal@yahoo.com>
   9           Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org>
  10           Copyright (C) 2009 Luis Correia <luis.f.correia@gmail.com>
  11           Copyright (C) 2009 Mattias Nissler <mattias.nissler@gmx.de>
  12           Copyright (C) 2009 Mark Asselstine <asselsm@gmail.com>
  13           Copyright (C) 2009 Xose Vazquez Perez <xose.vazquez@gmail.com>
  14           <http://rt2x00.serialmonkey.com>
  15
  16         This program is free software; you can redistribute it and/or modify
  17         it under the terms of the GNU General Public License as published by
  18         the Free Software Foundation; either version 2 of the License, or
  19         (at your option) any later version.
  20
  21         This program is distributed in the hope that it will be useful,
  22         but WITHOUT ANY WARRANTY; without even the implied warranty of
  23         MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  24         GNU General Public License for more details.
  25
  26         You should have received a copy of the GNU General Public License
  27         along with this program; if not, write to the
  28         Free Software Foundation, Inc.,
  29         59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  30  */
  31
  32 /*
  33         Module: rt2800lib
  34         Abstract: rt2800 generic device routines.
  35  */
  36
  37 #include <linux/crc-ccitt.h>
  38 #include <linux/kernel.h>
  39 #include <linux/module.h>
  40 #include <linux/slab.h>
  41
  42 #include "rt2x00.h"
  43 #include "rt2800lib.h"
  44 #include "rt2800.h"
  45
  46 /*
  47  * Register access.
  48  * All access to the CSR registers will go through the methods
  49  * rt2800_register_read and rt2800_register_write.
  50  * BBP and RF register require indirect register access,
  51  * and use the CSR registers BBPCSR and RFCSR to achieve this.
  52  * These indirect registers work with busy bits,
  53  * and we will try maximal REGISTER_BUSY_COUNT times to access
  54  * the register while taking a REGISTER_BUSY_DELAY us delay
  55  * between each attampt. When the busy bit is still set at that time,
  56  * the access attempt is considered to have failed,
  57  * and we will print an error.
  58  * The _lock versions must be used if you already hold the csr_mutex
  59  */
  60 #define WAIT_FOR_BBP(__dev, __reg) \
  61         rt2800_regbusy_read((__dev), BBP_CSR_CFG, BBP_CSR_CFG_BUSY, (__reg))
  62 #define WAIT_FOR_RFCSR(__dev, __reg) \
  63         rt2800_regbusy_read((__dev), RF_CSR_CFG, RF_CSR_CFG_BUSY, (__reg))
  64 #define WAIT_FOR_RF(__dev, __reg) \
  65         rt2800_regbusy_read((__dev), RF_CSR_CFG0, RF_CSR_CFG0_BUSY, (__reg))
  66 #define WAIT_FOR_MCU(__dev, __reg) \
  67         rt2800_regbusy_read((__dev), H2M_MAILBOX_CSR, \
  68                             H2M_MAILBOX_CSR_OWNER, (__reg))
  69
  70 static inline bool rt2800_is_305x_soc(struct rt2x00_dev *rt2x00dev)
  71 {
  72         /* check for rt2872 on SoC */
  73         if (!rt2x00_is_soc(rt2x00dev) ||
  74             !rt2x00_rt(rt2x00dev, RT2872))
  75                 return false;
  76
  77         /* we know for sure that these rf chipsets are used on rt305x boards */
  78         if (rt2x00_rf(rt2x00dev, RF3020) ||
  79             rt2x00_rf(rt2x00dev, RF3021) ||
  80             rt2x00_rf(rt2x00dev, RF3022))
  81                 return true;
  82
  83         WARNING(rt2x00dev, "Unknown RF chipset on rt305x\n");
  84         return false;
  85 }
  86
  87 static void rt2800_bbp_write(struct rt2x00_dev *rt2x00dev,
  88                              const unsigned int word, const u8 value)
  89 {
  90         u32 reg;
  91
  92         mutex_lock(&rt2x00dev->csr_mutex);
  93
  94         /*
  95          * Wait until the BBP becomes available, afterwards we
  96          * can safely write the new data into the register.
  97          */
  98         if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
  99                 reg = 0;
 100                 rt2x00_set_field32(&reg, BBP_CSR_CFG_VALUE, value);
 101                 rt2x00_set_field32(&reg, BBP_CSR_CFG_REGNUM, word);
 102                 rt2x00_set_field32(&reg, BBP_CSR_CFG_BUSY, 1);
 103                 rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 0);
 104                 rt2x00_set_field32(&reg, BBP_CSR_CFG_BBP_RW_MODE, 1);
 105
 106                 rt2800_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg);
 107         }
 108
 109         mutex_unlock(&rt2x00dev->csr_mutex);
 110 }
 111
 112 static void rt2800_bbp_read(struct rt2x00_dev *rt2x00dev,
 113                             const unsigned int word, u8 *value)
 114 {
 115         u32 reg;
 116
 117         mutex_lock(&rt2x00dev->csr_mutex);
 118
 119         /*
 120          * Wait until the BBP becomes available, afterwards we
 121          * can safely write the read request into the register.
 122          * After the data has been written, we wait until hardware
 123          * returns the correct value, if at any time the register
 124          * doesn't become available in time, reg will be 0xffffffff
 125          * which means we return 0xff to the caller.
 126          */
 127         if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
 128                 reg = 0;
 129                 rt2x00_set_field32(&reg, BBP_CSR_CFG_REGNUM, word);
 130                 rt2x00_set_field32(&reg, BBP_CSR_CFG_BUSY, 1);
 131                 rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 1);
 132                 rt2x00_set_field32(&reg, BBP_CSR_CFG_BBP_RW_MODE, 1);
 133
 134                 rt2800_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg);
 135
 136                 WAIT_FOR_BBP(rt2x00dev, &reg);
 137         }
 138
 139         *value = rt2x00_get_field32(reg, BBP_CSR_CFG_VALUE);
 140
 141         mutex_unlock(&rt2x00dev->csr_mutex);
 142 }
 143
 144 static void rt2800_rfcsr_write(struct rt2x00_dev *rt2x00dev,
 145                                const unsigned int word, const u8 value)
 146 {
 147         u32 reg;
 148
 149         mutex_lock(&rt2x00dev->csr_mutex);
 150
 151         /*
 152          * Wait until the RFCSR becomes available, afterwards we
 153          * can safely write the new data into the register.
 154          */
 155         if (WAIT_FOR_RFCSR(rt2x00dev, &reg)) {
 156                 reg = 0;
 157                 rt2x00_set_field32(&reg, RF_CSR_CFG_DATA, value);
 158                 rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM, word);
 159                 rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE, 1);
 160                 rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY, 1);
 161
 162                 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
 163         }
 164
 165         mutex_unlock(&rt2x00dev->csr_mutex);
 166 }
 167
 168 static void rt2800_rfcsr_read(struct rt2x00_dev *rt2x00dev,
 169                               const unsigned int word, u8 *value)
 170 {
 171         u32 reg;
 172
 173         mutex_lock(&rt2x00dev->csr_mutex);
 174
 175         /*
 176          * Wait until the RFCSR becomes available, afterwards we
 177          * can safely write the read request into the register.
 178          * After the data has been written, we wait until hardware
 179          * returns the correct value, if at any time the register
 180          * doesn't become available in time, reg will be 0xffffffff
 181          * which means we return 0xff to the caller.
 182          */
 183         if (WAIT_FOR_RFCSR(rt2x00dev, &reg)) {
 184                 reg = 0;
 185                 rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM, word);
 186                 rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE, 0);
 187                 rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY, 1);
 188
 189                 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
 190
 191                 WAIT_FOR_RFCSR(rt2x00dev, &reg);
 192         }
 193
 194         *value = rt2x00_get_field32(reg, RF_CSR_CFG_DATA);
 195
 196         mutex_unlock(&rt2x00dev->csr_mutex);
 197 }
 198
 199 static void rt2800_rf_write(struct rt2x00_dev *rt2x00dev,
 200                             const unsigned int word, const u32 value)
 201 {
 202         u32 reg;
 203
 204         mutex_lock(&rt2x00dev->csr_mutex);
 205
 206         /*
 207          * Wait until the RF becomes available, afterwards we
 208          * can safely write the new data into the register.
 209          */
 210         if (WAIT_FOR_RF(rt2x00dev, &reg)) {
 211                 reg = 0;
 212                 rt2x00_set_field32(&reg, RF_CSR_CFG0_REG_VALUE_BW, value);
 213                 rt2x00_set_field32(&reg, RF_CSR_CFG0_STANDBYMODE, 0);
 214                 rt2x00_set_field32(&reg, RF_CSR_CFG0_SEL, 0);
 215                 rt2x00_set_field32(&reg, RF_CSR_CFG0_BUSY, 1);
 216
 217                 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG0, reg);
 218                 rt2x00_rf_write(rt2x00dev, word, value);
 219         }
 220
 221         mutex_unlock(&rt2x00dev->csr_mutex);
 222 }
 223
 224 static int rt2800_enable_wlan_rt3290(struct rt2x00_dev *rt2x00dev)
 225 {
 226         u32 reg;
 227         int i, count;
 228
 229         rt2800_register_read(rt2x00dev, WLAN_FUN_CTRL, &reg);
 230         if (rt2x00_get_field32(reg, WLAN_EN))
 231                 return 0;
 232
 233         rt2x00_set_field32(&reg, WLAN_GPIO_OUT_OE_BIT_ALL, 0xff);
 234         rt2x00_set_field32(&reg, FRC_WL_ANT_SET, 1);
 235         rt2x00_set_field32(&reg, WLAN_CLK_EN, 0);
 236         rt2x00_set_field32(&reg, WLAN_EN, 1);
 237         rt2800_register_write(rt2x00dev, WLAN_FUN_CTRL, reg);
 238
 239         udelay(REGISTER_BUSY_DELAY);
 240
 241         count = 0;
 242         do {
 243                 /*
 244                  * Check PLL_LD & XTAL_RDY.
 245                  */
 246                 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
 247                         rt2800_register_read(rt2x00dev, CMB_CTRL, &reg);
 248                         if (rt2x00_get_field32(reg, PLL_LD) &&
 249                             rt2x00_get_field32(reg, XTAL_RDY))
 250                                 break;
 251                         udelay(REGISTER_BUSY_DELAY);
 252                 }
 253
 254                 if (i >= REGISTER_BUSY_COUNT) {
 255
 256                         if (count >= 10)
 257                                 return -EIO;
 258
 259                         rt2800_register_write(rt2x00dev, 0x58, 0x018);
 260                         udelay(REGISTER_BUSY_DELAY);
 261                         rt2800_register_write(rt2x00dev, 0x58, 0x418);
 262                         udelay(REGISTER_BUSY_DELAY);
 263                         rt2800_register_write(rt2x00dev, 0x58, 0x618);
 264                         udelay(REGISTER_BUSY_DELAY);
 265                         count++;
 266                 } else {
 267                         count = 0;
 268                 }
 269
 270                 rt2800_register_read(rt2x00dev, WLAN_FUN_CTRL, &reg);
 271                 rt2x00_set_field32(&reg, PCIE_APP0_CLK_REQ, 0);
 272                 rt2x00_set_field32(&reg, WLAN_CLK_EN, 1);
 273                 rt2x00_set_field32(&reg, WLAN_RESET, 1);
 274                 rt2800_register_write(rt2x00dev, WLAN_FUN_CTRL, reg);
 275                 udelay(10);
 276                 rt2x00_set_field32(&reg, WLAN_RESET, 0);
 277                 rt2800_register_write(rt2x00dev, WLAN_FUN_CTRL, reg);
 278                 udelay(10);
 279                 rt2800_register_write(rt2x00dev, INT_SOURCE_CSR, 0x7fffffff);
 280         } while (count != 0);
 281
 282         return 0;
 283 }
 284
 285 void rt2800_mcu_request(struct rt2x00_dev *rt2x00dev,
 286                         const u8 command, const u8 token,
 287                         const u8 arg0, const u8 arg1)
 288 {
 289         u32 reg;
 290
 291         /*
 292          * SOC devices don't support MCU requests.
 293          */
 294         if (rt2x00_is_soc(rt2x00dev))
 295                 return;
 296
 297         mutex_lock(&rt2x00dev->csr_mutex);
 298
 299         /*
 300          * Wait until the MCU becomes available, afterwards we
 301          * can safely write the new data into the register.
 302          */
 303         if (WAIT_FOR_MCU(rt2x00dev, &reg)) {
 304                 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_OWNER, 1);
 305                 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_CMD_TOKEN, token);
 306                 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG0, arg0);
 307                 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG1, arg1);
 308                 rt2800_register_write_lock(rt2x00dev, H2M_MAILBOX_CSR, reg);
 309
 310                 reg = 0;
 311                 rt2x00_set_field32(&reg, HOST_CMD_CSR_HOST_COMMAND, command);
 312                 rt2800_register_write_lock(rt2x00dev, HOST_CMD_CSR, reg);
 313         }
 314
 315         mutex_unlock(&rt2x00dev->csr_mutex);
 316 }
 317 EXPORT_SYMBOL_GPL(rt2800_mcu_request);
 318
 319 int rt2800_wait_csr_ready(struct rt2x00_dev *rt2x00dev)
 320 {
 321         unsigned int i = 0;
 322         u32 reg;
 323
 324         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
 325                 rt2800_register_read(rt2x00dev, MAC_CSR0, &reg);
 326                 if (reg && reg != ~0)
 327                         return 0;
 328                 msleep(1);
 329         }
 330
 331         ERROR(rt2x00dev, "Unstable hardware.\n");
 332         return -EBUSY;
 333 }
 334 EXPORT_SYMBOL_GPL(rt2800_wait_csr_ready);
 335
 336 int rt2800_wait_wpdma_ready(struct rt2x00_dev *rt2x00dev)
 337 {
 338         unsigned int i;
 339         u32 reg;
 340
 341         /*
 342          * Some devices are really slow to respond here. Wait a whole second
 343          * before timing out.
 344          */
 345         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
 346                 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
 347                 if (!rt2x00_get_field32(reg, WPDMA_GLO_CFG_TX_DMA_BUSY) &&
 348                     !rt2x00_get_field32(reg, WPDMA_GLO_CFG_RX_DMA_BUSY))
 349                         return 0;
 350
 351                 msleep(10);
 352         }
 353
 354         ERROR(rt2x00dev, "WPDMA TX/RX busy [0x%08x].\n", reg);
 355         return -EACCES;
 356 }
 357 EXPORT_SYMBOL_GPL(rt2800_wait_wpdma_ready);
 358
 359 void rt2800_disable_wpdma(struct rt2x00_dev *rt2x00dev)
 360 {
 361         u32 reg;
 362
 363         rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
 364         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
 365         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
 366         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
 367         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
 368         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
 369         rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
 370 }
 371 EXPORT_SYMBOL_GPL(rt2800_disable_wpdma);
 372
 373 static bool rt2800_check_firmware_crc(const u8 *data, const size_t len)
 374 {
 375         u16 fw_crc;
 376         u16 crc;
 377
 378         /*
 379          * The last 2 bytes in the firmware array are the crc checksum itself,
 380          * this means that we should never pass those 2 bytes to the crc
 381          * algorithm.
 382          */
 383         fw_crc = (data[len - 2] << 8 | data[len - 1]);
 384
 385         /*
 386          * Use the crc ccitt algorithm.
 387          * This will return the same value as the legacy driver which
 388          * used bit ordering reversion on the both the firmware bytes
 389          * before input input as well as on the final output.
 390          * Obviously using crc ccitt directly is much more efficient.
 391          */
 392         crc = crc_ccitt(~0, data, len - 2);
 393
 394         /*
 395          * There is a small difference between the crc-itu-t + bitrev and
 396          * the crc-ccitt crc calculation. In the latter method the 2 bytes
 397          * will be swapped, use swab16 to convert the crc to the correct
 398          * value.
 399          */
 400         crc = swab16(crc);
 401
 402         return fw_crc == crc;
 403 }
 404
 405 int rt2800_check_firmware(struct rt2x00_dev *rt2x00dev,
 406                           const u8 *data, const size_t len)
 407 {
 408         size_t offset = 0;
 409         size_t fw_len;
 410         bool multiple;
 411
 412         /*
 413          * PCI(e) & SOC devices require firmware with a length
 414          * of 8kb. USB devices require firmware files with a length
 415          * of 4kb. Certain USB chipsets however require different firmware,
 416          * which Ralink only provides attached to the original firmware
 417          * file. Thus for USB devices, firmware files have a length
 418          * which is a multiple of 4kb. The firmware for rt3290 chip also
 419          * have a length which is a multiple of 4kb.
 420          */
 421         if (rt2x00_is_usb(rt2x00dev) || rt2x00_rt(rt2x00dev, RT3290))
 422                 fw_len = 4096;
 423         else
 424                 fw_len = 8192;
 425
 426         multiple = true;
 427         /*
 428          * Validate the firmware length
 429          */
 430         if (len != fw_len && (!multiple || (len % fw_len) != 0))
 431                 return FW_BAD_LENGTH;
 432
 433         /*
 434          * Check if the chipset requires one of the upper parts
 435          * of the firmware.
 436          */
 437         if (rt2x00_is_usb(rt2x00dev) &&
 438             !rt2x00_rt(rt2x00dev, RT2860) &&
 439             !rt2x00_rt(rt2x00dev, RT2872) &&
 440             !rt2x00_rt(rt2x00dev, RT3070) &&
 441             ((len / fw_len) == 1))
 442                 return FW_BAD_VERSION;
 443
 444         /*
 445          * 8kb firmware files must be checked as if it were
 446          * 2 separate firmware files.
 447          */
 448         while (offset < len) {
 449                 if (!rt2800_check_firmware_crc(data + offset, fw_len))
 450                         return FW_BAD_CRC;
 451
 452                 offset += fw_len;
 453         }
 454
 455         return FW_OK;
 456 }
 457 EXPORT_SYMBOL_GPL(rt2800_check_firmware);
 458
 459 int rt2800_load_firmware(struct rt2x00_dev *rt2x00dev,
 460                          const u8 *data, const size_t len)
 461 {
 462         unsigned int i;
 463         u32 reg;
 464         int retval;
 465
 466         if (rt2x00_rt(rt2x00dev, RT3290)) {
 467                 retval = rt2800_enable_wlan_rt3290(rt2x00dev);
 468                 if (retval)
 469                         return -EBUSY;
 470         }
 471
 472         /*
 473          * If driver doesn't wake up firmware here,
 474          * rt2800_load_firmware will hang forever when interface is up again.
 475          */
 476         rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0x00000000);
 477
 478         /*
 479          * Wait for stable hardware.
 480          */
 481         if (rt2800_wait_csr_ready(rt2x00dev))
 482                 return -EBUSY;
 483
 484         if (rt2x00_is_pci(rt2x00dev)) {
 485                 if (rt2x00_rt(rt2x00dev, RT3290) ||
 486                     rt2x00_rt(rt2x00dev, RT3572) ||
 487                     rt2x00_rt(rt2x00dev, RT5390) ||
 488                     rt2x00_rt(rt2x00dev, RT5392)) {
 489                         rt2800_register_read(rt2x00dev, AUX_CTRL, &reg);
 490                         rt2x00_set_field32(&reg, AUX_CTRL_FORCE_PCIE_CLK, 1);
 491                         rt2x00_set_field32(&reg, AUX_CTRL_WAKE_PCIE_EN, 1);
 492                         rt2800_register_write(rt2x00dev, AUX_CTRL, reg);
 493                 }
 494                 rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000002);
 495         }
 496
 497         rt2800_disable_wpdma(rt2x00dev);
 498
 499         /*
 500          * Write firmware to the device.
 501          */
 502         rt2800_drv_write_firmware(rt2x00dev, data, len);
 503
 504         /*
 505          * Wait for device to stabilize.
 506          */
 507         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
 508                 rt2800_register_read(rt2x00dev, PBF_SYS_CTRL, &reg);
 509                 if (rt2x00_get_field32(reg, PBF_SYS_CTRL_READY))
 510                         break;
 511                 msleep(1);
 512         }
 513
 514         if (i == REGISTER_BUSY_COUNT) {
 515                 ERROR(rt2x00dev, "PBF system register not ready.\n");
 516                 return -EBUSY;
 517         }
 518
 519         /*
 520          * Disable DMA, will be reenabled later when enabling
 521          * the radio.
 522          */
 523         rt2800_disable_wpdma(rt2x00dev);
 524
 525         /*
 526          * Initialize firmware.
 527          */
 528         rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
 529         rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
 530         if (rt2x00_is_usb(rt2x00dev))
 531                 rt2800_register_write(rt2x00dev, H2M_INT_SRC, 0);
 532         msleep(1);
 533
 534         return 0;
 535 }
 536 EXPORT_SYMBOL_GPL(rt2800_load_firmware);
 537
 538 void rt2800_write_tx_data(struct queue_entry *entry,
 539                           struct txentry_desc *txdesc)
 540 {
 541         __le32 *txwi = rt2800_drv_get_txwi(entry);
 542         u32 word;
 543
 544         /*
 545          * Initialize TX Info descriptor
 546          */
 547         rt2x00_desc_read(txwi, 0, &word);
 548         rt2x00_set_field32(&word, TXWI_W0_FRAG,
 549                            test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
 550         rt2x00_set_field32(&word, TXWI_W0_MIMO_PS,
 551                            test_bit(ENTRY_TXD_HT_MIMO_PS, &txdesc->flags));
 552         rt2x00_set_field32(&word, TXWI_W0_CF_ACK, 0);
 553         rt2x00_set_field32(&word, TXWI_W0_TS,
 554                            test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
 555         rt2x00_set_field32(&word, TXWI_W0_AMPDU,
 556                            test_bit(ENTRY_TXD_HT_AMPDU, &txdesc->flags));
 557         rt2x00_set_field32(&word, TXWI_W0_MPDU_DENSITY,
 558                            txdesc->u.ht.mpdu_density);
 559         rt2x00_set_field32(&word, TXWI_W0_TX_OP, txdesc->u.ht.txop);
 560         rt2x00_set_field32(&word, TXWI_W0_MCS, txdesc->u.ht.mcs);
 561         rt2x00_set_field32(&word, TXWI_W0_BW,
 562                            test_bit(ENTRY_TXD_HT_BW_40, &txdesc->flags));
 563         rt2x00_set_field32(&word, TXWI_W0_SHORT_GI,
 564                            test_bit(ENTRY_TXD_HT_SHORT_GI, &txdesc->flags));
 565         rt2x00_set_field32(&word, TXWI_W0_STBC, txdesc->u.ht.stbc);
 566         rt2x00_set_field32(&word, TXWI_W0_PHYMODE, txdesc->rate_mode);
 567         rt2x00_desc_write(txwi, 0, word);
 568
 569         rt2x00_desc_read(txwi, 1, &word);
 570         rt2x00_set_field32(&word, TXWI_W1_ACK,
 571                            test_bit(ENTRY_TXD_ACK, &txdesc->flags));
 572         rt2x00_set_field32(&word, TXWI_W1_NSEQ,
 573                            test_bit(ENTRY_TXD_GENERATE_SEQ, &txdesc->flags));
 574         rt2x00_set_field32(&word, TXWI_W1_BW_WIN_SIZE, txdesc->u.ht.ba_size);
 575         rt2x00_set_field32(&word, TXWI_W1_WIRELESS_CLI_ID,
 576                            test_bit(ENTRY_TXD_ENCRYPT, &txdesc->flags) ?
 577                            txdesc->key_idx : txdesc->u.ht.wcid);
 578         rt2x00_set_field32(&word, TXWI_W1_MPDU_TOTAL_BYTE_COUNT,
 579                            txdesc->length);
 580         rt2x00_set_field32(&word, TXWI_W1_PACKETID_QUEUE, entry->queue->qid);
 581         rt2x00_set_field32(&word, TXWI_W1_PACKETID_ENTRY, (entry->entry_idx % 3) + 1);
 582         rt2x00_desc_write(txwi, 1, word);
 583
 584         /*
 585          * Always write 0 to IV/EIV fields, hardware will insert the IV
 586          * from the IVEIV register when TXD_W3_WIV is set to 0.
 587          * When TXD_W3_WIV is set to 1 it will use the IV data
 588          * from the descriptor. The TXWI_W1_WIRELESS_CLI_ID indicates which
 589          * crypto entry in the registers should be used to encrypt the frame.
 590          */
 591         _rt2x00_desc_write(txwi, 2, 0 /* skbdesc->iv[0] */);
 592         _rt2x00_desc_write(txwi, 3, 0 /* skbdesc->iv[1] */);
 593 }
 594 EXPORT_SYMBOL_GPL(rt2800_write_tx_data);
 595
 596 static int rt2800_agc_to_rssi(struct rt2x00_dev *rt2x00dev, u32 rxwi_w2)
 597 {
 598         s8 rssi0 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI0);
 599         s8 rssi1 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI1);
 600         s8 rssi2 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI2);
 601         u16 eeprom;
 602         u8 offset0;
 603         u8 offset1;
 604         u8 offset2;
 605
 606         if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ) {
 607                 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG, &eeprom);
 608                 offset0 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG_OFFSET0);
 609                 offset1 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG_OFFSET1);
 610                 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &eeprom);
 611                 offset2 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG2_OFFSET2);
 612         } else {
 613                 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A, &eeprom);
 614                 offset0 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A_OFFSET0);
 615                 offset1 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A_OFFSET1);
 616                 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &eeprom);
 617                 offset2 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A2_OFFSET2);
 618         }
 619
 620         /*
 621          * Convert the value from the descriptor into the RSSI value
 622          * If the value in the descriptor is 0, it is considered invalid
 623          * and the default (extremely low) rssi value is assumed
 624          */
 625         rssi0 = (rssi0) ? (-12 - offset0 - rt2x00dev->lna_gain - rssi0) : -128;
 626         rssi1 = (rssi1) ? (-12 - offset1 - rt2x00dev->lna_gain - rssi1) : -128;
 627         rssi2 = (rssi2) ? (-12 - offset2 - rt2x00dev->lna_gain - rssi2) : -128;
 628
 629         /*
 630          * mac80211 only accepts a single RSSI value. Calculating the
 631          * average doesn't deliver a fair answer either since -60:-60 would
 632          * be considered equally good as -50:-70 while the second is the one
 633          * which gives less energy...
 634          */
 635         rssi0 = max(rssi0, rssi1);
 636         return (int)max(rssi0, rssi2);
 637 }
 638
 639 void rt2800_process_rxwi(struct queue_entry *entry,
 640                          struct rxdone_entry_desc *rxdesc)
 641 {
 642         __le32 *rxwi = (__le32 *) entry->skb->data;
 643         u32 word;
 644
 645         rt2x00_desc_read(rxwi, 0, &word);
 646
 647         rxdesc->cipher = rt2x00_get_field32(word, RXWI_W0_UDF);
 648         rxdesc->size = rt2x00_get_field32(word, RXWI_W0_MPDU_TOTAL_BYTE_COUNT);
 649
 650         rt2x00_desc_read(rxwi, 1, &word);
 651
 652         if (rt2x00_get_field32(word, RXWI_W1_SHORT_GI))
 653                 rxdesc->flags |= RX_FLAG_SHORT_GI;
 654
 655         if (rt2x00_get_field32(word, RXWI_W1_BW))
 656                 rxdesc->flags |= RX_FLAG_40MHZ;
 657
 658         /*
 659          * Detect RX rate, always use MCS as signal type.
 660          */
 661         rxdesc->dev_flags |= RXDONE_SIGNAL_MCS;
 662         rxdesc->signal = rt2x00_get_field32(word, RXWI_W1_MCS);
 663         rxdesc->rate_mode = rt2x00_get_field32(word, RXWI_W1_PHYMODE);
 664
 665         /*
 666          * Mask of 0x8 bit to remove the short preamble flag.
 667          */
 668         if (rxdesc->rate_mode == RATE_MODE_CCK)
 669                 rxdesc->signal &= ~0x8;
 670
 671         rt2x00_desc_read(rxwi, 2, &word);
 672
 673         /*
 674          * Convert descriptor AGC value to RSSI value.
 675          */
 676         rxdesc->rssi = rt2800_agc_to_rssi(entry->queue->rt2x00dev, word);
 677
 678         /*
 679          * Remove RXWI descriptor from start of buffer.
 680          */
 681         skb_pull(entry->skb, RXWI_DESC_SIZE);
 682 }
 683 EXPORT_SYMBOL_GPL(rt2800_process_rxwi);
 684
 685 void rt2800_txdone_entry(struct queue_entry *entry, u32 status, __le32 *txwi)
 686 {
 687         struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
 688         struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
 689         struct txdone_entry_desc txdesc;
 690         u32 word;
 691         u16 mcs, real_mcs;
 692         int aggr, ampdu;
 693
 694         /*
 695          * Obtain the status about this packet.
 696          */
 697         txdesc.flags = 0;
 698         rt2x00_desc_read(txwi, 0, &word);
 699
 700         mcs = rt2x00_get_field32(word, TXWI_W0_MCS);
 701         ampdu = rt2x00_get_field32(word, TXWI_W0_AMPDU);
 702
 703         real_mcs = rt2x00_get_field32(status, TX_STA_FIFO_MCS);
 704         aggr = rt2x00_get_field32(status, TX_STA_FIFO_TX_AGGRE);
 705
 706         /*
 707          * If a frame was meant to be sent as a single non-aggregated MPDU
 708          * but ended up in an aggregate the used tx rate doesn't correlate
 709          * with the one specified in the TXWI as the whole aggregate is sent
 710          * with the same rate.
 711          *
 712          * For example: two frames are sent to rt2x00, the first one sets
 713          * AMPDU=1 and requests MCS7 whereas the second frame sets AMDPU=0
 714          * and requests MCS15. If the hw aggregates both frames into one
 715          * AMDPU the tx status for both frames will contain MCS7 although
 716          * the frame was sent successfully.
 717          *
 718          * Hence, replace the requested rate with the real tx rate to not
 719          * confuse the rate control algortihm by providing clearly wrong
 720          * data.
 721          */
 722         if (unlikely(aggr == 1 && ampdu == 0 && real_mcs != mcs)) {
 723                 skbdesc->tx_rate_idx = real_mcs;
 724                 mcs = real_mcs;
 725         }
 726
 727         if (aggr == 1 || ampdu == 1)
 728                 __set_bit(TXDONE_AMPDU, &txdesc.flags);
 729
 730         /*
 731          * Ralink has a retry mechanism using a global fallback
 732          * table. We setup this fallback table to try the immediate
 733          * lower rate for all rates. In the TX_STA_FIFO, the MCS field
 734          * always contains the MCS used for the last transmission, be
 735          * it successful or not.
 736          */
 737         if (rt2x00_get_field32(status, TX_STA_FIFO_TX_SUCCESS)) {
 738                 /*
 739                  * Transmission succeeded. The number of retries is
 740                  * mcs - real_mcs
 741                  */
 742                 __set_bit(TXDONE_SUCCESS, &txdesc.flags);
 743                 txdesc.retry = ((mcs > real_mcs) ? mcs - real_mcs : 0);
 744         } else {
 745                 /*
 746                  * Transmission failed. The number of retries is
 747                  * always 7 in this case (for a total number of 8
 748                  * frames sent).
 749                  */
 750                 __set_bit(TXDONE_FAILURE, &txdesc.flags);
 751                 txdesc.retry = rt2x00dev->long_retry;
 752         }
 753
 754         /*
 755          * the frame was retried at least once
 756          * -> hw used fallback rates
 757          */
 758         if (txdesc.retry)
 759                 __set_bit(TXDONE_FALLBACK, &txdesc.flags);
 760
 761         rt2x00lib_txdone(entry, &txdesc);
 762 }
 763 EXPORT_SYMBOL_GPL(rt2800_txdone_entry);
 764
 765 void rt2800_write_beacon(struct queue_entry *entry, struct txentry_desc *txdesc)
 766 {
 767         struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
 768         struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
 769         unsigned int beacon_base;
 770         unsigned int padding_len;
 771         u32 orig_reg, reg;
 772
 773         /*
 774          * Disable beaconing while we are reloading the beacon data,
 775          * otherwise we might be sending out invalid data.
 776          */
 777         rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
 778         orig_reg = reg;
 779         rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
 780         rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
 781
 782         /*
 783          * Add space for the TXWI in front of the skb.
 784          */
 785         memset(skb_push(entry->skb, TXWI_DESC_SIZE), 0, TXWI_DESC_SIZE);
 786
 787         /*
 788          * Register descriptor details in skb frame descriptor.
 789          */
 790         skbdesc->flags |= SKBDESC_DESC_IN_SKB;
 791         skbdesc->desc = entry->skb->data;
 792         skbdesc->desc_len = TXWI_DESC_SIZE;
 793
 794         /*
 795          * Add the TXWI for the beacon to the skb.
 796          */
 797         rt2800_write_tx_data(entry, txdesc);
 798
 799         /*
 800          * Dump beacon to userspace through debugfs.
 801          */
 802         rt2x00debug_dump_frame(rt2x00dev, DUMP_FRAME_BEACON, entry->skb);
 803
 804         /*
 805          * Write entire beacon with TXWI and padding to register.
 806          */
 807         padding_len = roundup(entry->skb->len, 4) - entry->skb->len;
 808         if (padding_len && skb_pad(entry->skb, padding_len)) {
 809                 ERROR(rt2x00dev, "Failure padding beacon, aborting\n");
 810                 /* skb freed by skb_pad() on failure */
 811                 entry->skb = NULL;
 812                 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, orig_reg);
 813                 return;
 814         }
 815
 816         beacon_base = HW_BEACON_OFFSET(entry->entry_idx);
 817         rt2800_register_multiwrite(rt2x00dev, beacon_base, entry->skb->data,
 818                                    entry->skb->len + padding_len);
 819
 820         /*
 821          * Enable beaconing again.
 822          */
 823         rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 1);
 824         rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
 825
 826         /*
 827          * Clean up beacon skb.
 828          */
 829         dev_kfree_skb_any(entry->skb);
 830         entry->skb = NULL;
 831 }
 832 EXPORT_SYMBOL_GPL(rt2800_write_beacon);
 833
 834 static inline void rt2800_clear_beacon_register(struct rt2x00_dev *rt2x00dev,
 835                                                 unsigned int beacon_base)
 836 {
 837         int i;
 838
 839         /*
 840          * For the Beacon base registers we only need to clear
 841          * the whole TXWI which (when set to 0) will invalidate
 842          * the entire beacon.
 843          */
 844         for (i = 0; i < TXWI_DESC_SIZE; i += sizeof(__le32))
 845                 rt2800_register_write(rt2x00dev, beacon_base + i, 0);
 846 }
 847
 848 void rt2800_clear_beacon(struct queue_entry *entry)
 849 {
 850         struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
 851         u32 reg;
 852
 853         /*
 854          * Disable beaconing while we are reloading the beacon data,
 855          * otherwise we might be sending out invalid data.
 856          */
 857         rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
 858         rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
 859         rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
 860
 861         /*
 862          * Clear beacon.
 863          */
 864         rt2800_clear_beacon_register(rt2x00dev,
 865                                      HW_BEACON_OFFSET(entry->entry_idx));
 866
 867         /*
 868          * Enabled beaconing again.
 869          */
 870         rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 1);
 871         rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
 872 }
 873 EXPORT_SYMBOL_GPL(rt2800_clear_beacon);
 874
 875 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
 876 const struct rt2x00debug rt2800_rt2x00debug = {
 877         .owner  = THIS_MODULE,
 878         .csr    = {
 879                 .read           = rt2800_register_read,
 880                 .write          = rt2800_register_write,
 881                 .flags          = RT2X00DEBUGFS_OFFSET,
 882                 .word_base      = CSR_REG_BASE,
 883                 .word_size      = sizeof(u32),
 884                 .word_count     = CSR_REG_SIZE / sizeof(u32),
 885         },
 886         .eeprom = {
 887                 .read           = rt2x00_eeprom_read,
 888                 .write          = rt2x00_eeprom_write,
 889                 .word_base      = EEPROM_BASE,
 890                 .word_size      = sizeof(u16),
 891                 .word_count     = EEPROM_SIZE / sizeof(u16),
 892         },
 893         .bbp    = {
 894                 .read           = rt2800_bbp_read,
 895                 .write          = rt2800_bbp_write,
 896                 .word_base      = BBP_BASE,
 897                 .word_size      = sizeof(u8),
 898                 .word_count     = BBP_SIZE / sizeof(u8),
 899         },
 900         .rf     = {
 901                 .read           = rt2x00_rf_read,
 902                 .write          = rt2800_rf_write,
 903                 .word_base      = RF_BASE,
 904                 .word_size      = sizeof(u32),
 905                 .word_count     = RF_SIZE / sizeof(u32),
 906         },
 907         .rfcsr  = {
 908                 .read           = rt2800_rfcsr_read,
 909                 .write          = rt2800_rfcsr_write,
 910                 .word_base      = RFCSR_BASE,
 911                 .word_size      = sizeof(u8),
 912                 .word_count     = RFCSR_SIZE / sizeof(u8),
 913         },
 914 };
 915 EXPORT_SYMBOL_GPL(rt2800_rt2x00debug);
 916 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
 917
 918 int rt2800_rfkill_poll(struct rt2x00_dev *rt2x00dev)
 919 {
 920         u32 reg;
 921
 922         if (rt2x00_rt(rt2x00dev, RT3290)) {
 923                 rt2800_register_read(rt2x00dev, WLAN_FUN_CTRL, &reg);
 924                 return rt2x00_get_field32(reg, WLAN_GPIO_IN_BIT0);
 925         } else {
 926                 rt2800_register_read(rt2x00dev, GPIO_CTRL, &reg);
 927                 return rt2x00_get_field32(reg, GPIO_CTRL_VAL2);
 928         }
 929 }
 930 EXPORT_SYMBOL_GPL(rt2800_rfkill_poll);
 931
 932 #ifdef CONFIG_RT2X00_LIB_LEDS
 933 static void rt2800_brightness_set(struct led_classdev *led_cdev,
 934                                   enum led_brightness brightness)
 935 {
 936         struct rt2x00_led *led =
 937             container_of(led_cdev, struct rt2x00_led, led_dev);
 938         unsigned int enabled = brightness != LED_OFF;
 939         unsigned int bg_mode =
 940             (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_2GHZ);
 941         unsigned int polarity =
 942                 rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
 943                                    EEPROM_FREQ_LED_POLARITY);
 944         unsigned int ledmode =
 945                 rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
 946                                    EEPROM_FREQ_LED_MODE);
 947         u32 reg;
 948
 949         /* Check for SoC (SOC devices don't support MCU requests) */
 950         if (rt2x00_is_soc(led->rt2x00dev)) {
 951                 rt2800_register_read(led->rt2x00dev, LED_CFG, &reg);
 952
 953                 /* Set LED Polarity */
 954                 rt2x00_set_field32(&reg, LED_CFG_LED_POLAR, polarity);
 955
 956                 /* Set LED Mode */
 957                 if (led->type == LED_TYPE_RADIO) {
 958                         rt2x00_set_field32(&reg, LED_CFG_G_LED_MODE,
 959                                            enabled ? 3 : 0);
 960                 } else if (led->type == LED_TYPE_ASSOC) {
 961                         rt2x00_set_field32(&reg, LED_CFG_Y_LED_MODE,
 962                                            enabled ? 3 : 0);
 963                 } else if (led->type == LED_TYPE_QUALITY) {
 964                         rt2x00_set_field32(&reg, LED_CFG_R_LED_MODE,
 965                                            enabled ? 3 : 0);
 966                 }
 967
 968                 rt2800_register_write(led->rt2x00dev, LED_CFG, reg);
 969
 970         } else {
 971                 if (led->type == LED_TYPE_RADIO) {
 972                         rt2800_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
 973                                               enabled ? 0x20 : 0);
 974                 } else if (led->type == LED_TYPE_ASSOC) {
 975                         rt2800_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
 976                                               enabled ? (bg_mode ? 0x60 : 0xa0) : 0x20);
 977                 } else if (led->type == LED_TYPE_QUALITY) {
 978                         /*
 979                          * The brightness is divided into 6 levels (0 - 5),
 980                          * The specs tell us the following levels:
 981                          *      0, 1 ,3, 7, 15, 31
 982                          * to determine the level in a simple way we can simply
 983                          * work with bitshifting:
 984                          *      (1 << level) - 1
 985                          */
 986                         rt2800_mcu_request(led->rt2x00dev, MCU_LED_STRENGTH, 0xff,
 987                                               (1 << brightness / (LED_FULL / 6)) - 1,
 988                                               polarity);
 989                 }
 990         }
 991 }
 992
 993 static void rt2800_init_led(struct rt2x00_dev *rt2x00dev,
 994                      struct rt2x00_led *led, enum led_type type)
 995 {
 996         led->rt2x00dev = rt2x00dev;
 997         led->type = type;
 998         led->led_dev.brightness_set = rt2800_brightness_set;
 999         led->flags = LED_INITIALIZED;
1000 }
1001 #endif /* CONFIG_RT2X00_LIB_LEDS */
1002
1003 /*
1004  * Configuration handlers.
1005  */
1006 static void rt2800_config_wcid(struct rt2x00_dev *rt2x00dev,
1007                                const u8 *address,
1008                                int wcid)
1009 {
1010         struct mac_wcid_entry wcid_entry;
1011         u32 offset;
1012
1013         offset = MAC_WCID_ENTRY(wcid);
1014
1015         memset(&wcid_entry, 0xff, sizeof(wcid_entry));
1016         if (address)
1017                 memcpy(wcid_entry.mac, address, ETH_ALEN);
1018
1019         rt2800_register_multiwrite(rt2x00dev, offset,
1020                                       &wcid_entry, sizeof(wcid_entry));
1021 }
1022
1023 static void rt2800_delete_wcid_attr(struct rt2x00_dev *rt2x00dev, int wcid)
1024 {
1025         u32 offset;
1026         offset = MAC_WCID_ATTR_ENTRY(wcid);
1027         rt2800_register_write(rt2x00dev, offset, 0);
1028 }
1029
1030 static void rt2800_config_wcid_attr_bssidx(struct rt2x00_dev *rt2x00dev,
1031                                            int wcid, u32 bssidx)
1032 {
1033         u32 offset = MAC_WCID_ATTR_ENTRY(wcid);
1034         u32 reg;
1035
1036         /*
1037          * The BSS Idx numbers is split in a main value of 3 bits,
1038          * and a extended field for adding one additional bit to the value.
1039          */
1040         rt2800_register_read(rt2x00dev, offset, &reg);
1041         rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_BSS_IDX, (bssidx & 0x7));
1042         rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_BSS_IDX_EXT,
1043                            (bssidx & 0x8) >> 3);
1044         rt2800_register_write(rt2x00dev, offset, reg);
1045 }
1046
1047 static void rt2800_config_wcid_attr_cipher(struct rt2x00_dev *rt2x00dev,
1048                                            struct rt2x00lib_crypto *crypto,
1049                                            struct ieee80211_key_conf *key)
1050 {
1051         struct mac_iveiv_entry iveiv_entry;
1052         u32 offset;
1053         u32 reg;
1054
1055         offset = MAC_WCID_ATTR_ENTRY(key->hw_key_idx);
1056
1057         if (crypto->cmd == SET_KEY) {
1058                 rt2800_register_read(rt2x00dev, offset, &reg);
1059                 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_KEYTAB,
1060                                    !!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE));
1061                 /*
1062                  * Both the cipher as the BSS Idx numbers are split in a main
1063                  * value of 3 bits, and a extended field for adding one additional
1064                  * bit to the value.
1065                  */
1066                 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER,
1067                                    (crypto->cipher & 0x7));
1068                 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER_EXT,
1069                                    (crypto->cipher & 0x8) >> 3);
1070                 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_RX_WIUDF, crypto->cipher);
1071                 rt2800_register_write(rt2x00dev, offset, reg);
1072         } else {
1073                 /* Delete the cipher without touching the bssidx */
1074                 rt2800_register_read(rt2x00dev, offset, &reg);
1075                 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_KEYTAB, 0);
1076                 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER, 0);
1077                 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER_EXT, 0);
1078                 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_RX_WIUDF, 0);
1079                 rt2800_register_write(rt2x00dev, offset, reg);
1080         }
1081
1082         offset = MAC_IVEIV_ENTRY(key->hw_key_idx);
1083
1084         memset(&iveiv_entry, 0, sizeof(iveiv_entry));
1085         if ((crypto->cipher == CIPHER_TKIP) ||
1086             (crypto->cipher == CIPHER_TKIP_NO_MIC) ||
1087             (crypto->cipher == CIPHER_AES))
1088                 iveiv_entry.iv[3] |= 0x20;
1089         iveiv_entry.iv[3] |= key->keyidx << 6;
1090         rt2800_register_multiwrite(rt2x00dev, offset,
1091                                       &iveiv_entry, sizeof(iveiv_entry));
1092 }
1093
1094 int rt2800_config_shared_key(struct rt2x00_dev *rt2x00dev,
1095                              struct rt2x00lib_crypto *crypto,
1096                              struct ieee80211_key_conf *key)
1097 {
1098         struct hw_key_entry key_entry;
1099         struct rt2x00_field32 field;
1100         u32 offset;
1101         u32 reg;
1102
1103         if (crypto->cmd == SET_KEY) {
1104                 key->hw_key_idx = (4 * crypto->bssidx) + key->keyidx;
1105
1106                 memcpy(key_entry.key, crypto->key,
1107                        sizeof(key_entry.key));
1108                 memcpy(key_entry.tx_mic, crypto->tx_mic,
1109                        sizeof(key_entry.tx_mic));
1110                 memcpy(key_entry.rx_mic, crypto->rx_mic,
1111                        sizeof(key_entry.rx_mic));
1112
1113                 offset = SHARED_KEY_ENTRY(key->hw_key_idx);
1114                 rt2800_register_multiwrite(rt2x00dev, offset,
1115                                               &key_entry, sizeof(key_entry));
1116         }
1117
1118         /*
1119          * The cipher types are stored over multiple registers
1120          * starting with SHARED_KEY_MODE_BASE each word will have
1121          * 32 bits and contains the cipher types for 2 bssidx each.
1122          * Using the correct defines correctly will cause overhead,
1123          * so just calculate the correct offset.
1124          */
1125         field.bit_offset = 4 * (key->hw_key_idx % 8);
1126         field.bit_mask = 0x7 << field.bit_offset;
1127
1128         offset = SHARED_KEY_MODE_ENTRY(key->hw_key_idx / 8);
1129
1130         rt2800_register_read(rt2x00dev, offset, &reg);
1131         rt2x00_set_field32(&reg, field,
1132                            (crypto->cmd == SET_KEY) * crypto->cipher);
1133         rt2800_register_write(rt2x00dev, offset, reg);
1134
1135         /*
1136          * Update WCID information
1137          */
1138         rt2800_config_wcid(rt2x00dev, crypto->address, key->hw_key_idx);
1139         rt2800_config_wcid_attr_bssidx(rt2x00dev, key->hw_key_idx,
1140                                        crypto->bssidx);
1141         rt2800_config_wcid_attr_cipher(rt2x00dev, crypto, key);
1142
1143         return 0;
1144 }
1145 EXPORT_SYMBOL_GPL(rt2800_config_shared_key);
1146
1147 static inline int rt2800_find_wcid(struct rt2x00_dev *rt2x00dev)
1148 {
1149         struct mac_wcid_entry wcid_entry;
1150         int idx;
1151         u32 offset;
1152
1153         /*
1154          * Search for the first free WCID entry and return the corresponding
1155          * index.
1156          *
1157          * Make sure the WCID starts _after_ the last possible shared key
1158          * entry (>32).
1159          *
1160          * Since parts of the pairwise key table might be shared with
1161          * the beacon frame buffers 6 & 7 we should only write into the
1162          * first 222 entries.
1163          */
1164         for (idx = 33; idx <= 222; idx++) {
1165                 offset = MAC_WCID_ENTRY(idx);
1166                 rt2800_register_multiread(rt2x00dev, offset, &wcid_entry,
1167                                           sizeof(wcid_entry));
1168                 if (is_broadcast_ether_addr(wcid_entry.mac))
1169                         return idx;
1170         }
1171
1172         /*
1173          * Use -1 to indicate that we don't have any more space in the WCID
1174          * table.
1175          */
1176         return -1;
1177 }
1178
1179 int rt2800_config_pairwise_key(struct rt2x00_dev *rt2x00dev,
1180                                struct rt2x00lib_crypto *crypto,
1181                                struct ieee80211_key_conf *key)
1182 {
1183         struct hw_key_entry key_entry;
1184         u32 offset;
1185
1186         if (crypto->cmd == SET_KEY) {
1187                 /*
1188                  * Allow key configuration only for STAs that are
1189                  * known by the hw.
1190                  */
1191                 if (crypto->wcid < 0)
1192                         return -ENOSPC;
1193                 key->hw_key_idx = crypto->wcid;
1194
1195                 memcpy(key_entry.key, crypto->key,
1196                        sizeof(key_entry.key));
1197                 memcpy(key_entry.tx_mic, crypto->tx_mic,
1198                        sizeof(key_entry.tx_mic));
1199                 memcpy(key_entry.rx_mic, crypto->rx_mic,
1200                        sizeof(key_entry.rx_mic));
1201
1202                 offset = PAIRWISE_KEY_ENTRY(key->hw_key_idx);
1203                 rt2800_register_multiwrite(rt2x00dev, offset,
1204                                               &key_entry, sizeof(key_entry));
1205         }
1206
1207         /*
1208          * Update WCID information
1209          */
1210         rt2800_config_wcid_attr_cipher(rt2x00dev, crypto, key);
1211
1212         return 0;
1213 }
1214 EXPORT_SYMBOL_GPL(rt2800_config_pairwise_key);
1215
1216 int rt2800_sta_add(struct rt2x00_dev *rt2x00dev, struct ieee80211_vif *vif,
1217                    struct ieee80211_sta *sta)
1218 {
1219         int wcid;
1220         struct rt2x00_sta *sta_priv = sta_to_rt2x00_sta(sta);
1221
1222         /*
1223          * Find next free WCID.
1224          */
1225         wcid = rt2800_find_wcid(rt2x00dev);
1226
1227         /*
1228          * Store selected wcid even if it is invalid so that we can
1229          * later decide if the STA is uploaded into the hw.
1230          */
1231         sta_priv->wcid = wcid;
1232
1233         /*
1234          * No space left in the device, however, we can still communicate
1235          * with the STA -> No error.
1236          */
1237         if (wcid < 0)
1238                 return 0;
1239
1240         /*
1241          * Clean up WCID attributes and write STA address to the device.
1242          */
1243         rt2800_delete_wcid_attr(rt2x00dev, wcid);
1244         rt2800_config_wcid(rt2x00dev, sta->addr, wcid);
1245         rt2800_config_wcid_attr_bssidx(rt2x00dev, wcid,
1246                                        rt2x00lib_get_bssidx(rt2x00dev, vif));
1247         return 0;
1248 }
1249 EXPORT_SYMBOL_GPL(rt2800_sta_add);
1250
1251 int rt2800_sta_remove(struct rt2x00_dev *rt2x00dev, int wcid)
1252 {
1253         /*
1254          * Remove WCID entry, no need to clean the attributes as they will
1255          * get renewed when the WCID is reused.
1256          */
1257         rt2800_config_wcid(rt2x00dev, NULL, wcid);
1258
1259         return 0;
1260 }
1261 EXPORT_SYMBOL_GPL(rt2800_sta_remove);
1262
1263 void rt2800_config_filter(struct rt2x00_dev *rt2x00dev,
1264                           const unsigned int filter_flags)
1265 {
1266         u32 reg;
1267
1268         /*
1269          * Start configuration steps.
1270          * Note that the version error will always be dropped
1271          * and broadcast frames will always be accepted since
1272          * there is no filter for it at this time.
1273          */
1274         rt2800_register_read(rt2x00dev, RX_FILTER_CFG, &reg);
1275         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CRC_ERROR,
1276                            !(filter_flags & FIF_FCSFAIL));
1277         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_PHY_ERROR,
1278                            !(filter_flags & FIF_PLCPFAIL));
1279         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_NOT_TO_ME,
1280                            !(filter_flags & FIF_PROMISC_IN_BSS));
1281         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_NOT_MY_BSSD, 0);
1282         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_VER_ERROR, 1);
1283         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_MULTICAST,
1284                            !(filter_flags & FIF_ALLMULTI));
1285         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BROADCAST, 0);
1286         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_DUPLICATE, 1);
1287         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CF_END_ACK,
1288                            !(filter_flags & FIF_CONTROL));
1289         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CF_END,
1290                            !(filter_flags & FIF_CONTROL));
1291         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_ACK,
1292                            !(filter_flags & FIF_CONTROL));
1293         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CTS,
1294                            !(filter_flags & FIF_CONTROL));
1295         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_RTS,
1296                            !(filter_flags & FIF_CONTROL));
1297         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_PSPOLL,
1298                            !(filter_flags & FIF_PSPOLL));
1299         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BA, 0);
1300         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BAR,
1301                            !(filter_flags & FIF_CONTROL));
1302         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CNTL,
1303                            !(filter_flags & FIF_CONTROL));
1304         rt2800_register_write(rt2x00dev, RX_FILTER_CFG, reg);
1305 }
1306 EXPORT_SYMBOL_GPL(rt2800_config_filter);
1307
1308 void rt2800_config_intf(struct rt2x00_dev *rt2x00dev, struct rt2x00_intf *intf,
1309                         struct rt2x00intf_conf *conf, const unsigned int flags)
1310 {
1311         u32 reg;
1312         bool update_bssid = false;
1313
1314         if (flags & CONFIG_UPDATE_TYPE) {
1315                 /*
1316                  * Enable synchronisation.
1317                  */
1318                 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
1319                 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, conf->sync);
1320                 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1321
1322                 if (conf->sync == TSF_SYNC_AP_NONE) {
1323                         /*
1324                          * Tune beacon queue transmit parameters for AP mode
1325                          */
1326                         rt2800_register_read(rt2x00dev, TBTT_SYNC_CFG, &reg);
1327                         rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_CWMIN, 0);
1328                         rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_AIFSN, 1);
1329                         rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_EXP_WIN, 32);
1330                         rt2x00_set_field32(&reg, TBTT_SYNC_CFG_TBTT_ADJUST, 0);
1331                         rt2800_register_write(rt2x00dev, TBTT_SYNC_CFG, reg);
1332                 } else {
1333                         rt2800_register_read(rt2x00dev, TBTT_SYNC_CFG, &reg);
1334                         rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_CWMIN, 4);
1335                         rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_AIFSN, 2);
1336                         rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_EXP_WIN, 32);
1337                         rt2x00_set_field32(&reg, TBTT_SYNC_CFG_TBTT_ADJUST, 16);
1338                         rt2800_register_write(rt2x00dev, TBTT_SYNC_CFG, reg);
1339                 }
1340         }
1341
1342         if (flags & CONFIG_UPDATE_MAC) {
1343                 if (flags & CONFIG_UPDATE_TYPE &&
1344                     conf->sync == TSF_SYNC_AP_NONE) {
1345                         /*
1346                          * The BSSID register has to be set to our own mac
1347                          * address in AP mode.
1348                          */
1349                         memcpy(conf->bssid, conf->mac, sizeof(conf->mac));
1350                         update_bssid = true;
1351                 }
1352
1353                 if (!is_zero_ether_addr((const u8 *)conf->mac)) {
1354                         reg = le32_to_cpu(conf->mac[1]);
1355                         rt2x00_set_field32(&reg, MAC_ADDR_DW1_UNICAST_TO_ME_MASK, 0xff);
1356                         conf->mac[1] = cpu_to_le32(reg);
1357                 }
1358
1359                 rt2800_register_multiwrite(rt2x00dev, MAC_ADDR_DW0,
1360                                               conf->mac, sizeof(conf->mac));
1361         }
1362
1363         if ((flags & CONFIG_UPDATE_BSSID) || update_bssid) {
1364                 if (!is_zero_ether_addr((const u8 *)conf->bssid)) {
1365                         reg = le32_to_cpu(conf->bssid[1]);
1366                         rt2x00_set_field32(&reg, MAC_BSSID_DW1_BSS_ID_MASK, 3);
1367                         rt2x00_set_field32(&reg, MAC_BSSID_DW1_BSS_BCN_NUM, 7);
1368                         conf->bssid[1] = cpu_to_le32(reg);
1369                 }
1370
1371                 rt2800_register_multiwrite(rt2x00dev, MAC_BSSID_DW0,
1372                                               conf->bssid, sizeof(conf->bssid));
1373         }
1374 }
1375 EXPORT_SYMBOL_GPL(rt2800_config_intf);
1376
1377 static void rt2800_config_ht_opmode(struct rt2x00_dev *rt2x00dev,
1378                                     struct rt2x00lib_erp *erp)
1379 {
1380         bool any_sta_nongf = !!(erp->ht_opmode &
1381                                 IEEE80211_HT_OP_MODE_NON_GF_STA_PRSNT);
1382         u8 protection = erp->ht_opmode & IEEE80211_HT_OP_MODE_PROTECTION;
1383         u8 mm20_mode, mm40_mode, gf20_mode, gf40_mode;
1384         u16 mm20_rate, mm40_rate, gf20_rate, gf40_rate;
1385         u32 reg;
1386
1387         /* default protection rate for HT20: OFDM 24M */
1388         mm20_rate = gf20_rate = 0x4004;
1389
1390         /* default protection rate for HT40: duplicate OFDM 24M */
1391         mm40_rate = gf40_rate = 0x4084;
1392
1393         switch (protection) {
1394         case IEEE80211_HT_OP_MODE_PROTECTION_NONE:
1395                 /*
1396                  * All STAs in this BSS are HT20/40 but there might be
1397                  * STAs not supporting greenfield mode.
1398                  * => Disable protection for HT transmissions.
1399                  */
1400                 mm20_mode = mm40_mode = gf20_mode = gf40_mode = 0;
1401
1402                 break;
1403         case IEEE80211_HT_OP_MODE_PROTECTION_20MHZ:
1404                 /*
1405                  * All STAs in this BSS are HT20 or HT20/40 but there
1406                  * might be STAs not supporting greenfield mode.
1407                  * => Protect all HT40 transmissions.
1408                  */
1409                 mm20_mode = gf20_mode = 0;
1410                 mm40_mode = gf40_mode = 2;
1411
1412                 break;
1413         case IEEE80211_HT_OP_MODE_PROTECTION_NONMEMBER:
1414                 /*
1415                  * Nonmember protection:
1416                  * According to 802.11n we _should_ protect all
1417                  * HT transmissions (but we don't have to).
1418                  *
1419                  * But if cts_protection is enabled we _shall_ protect
1420                  * all HT transmissions using a CCK rate.
1421                  *
1422                  * And if any station is non GF we _shall_ protect
1423                  * GF transmissions.
1424                  *
1425                  * We decide to protect everything
1426                  * -> fall through to mixed mode.
1427                  */
1428         case IEEE80211_HT_OP_MODE_PROTECTION_NONHT_MIXED:
1429                 /*
1430                  * Legacy STAs are present
1431                  * => Protect all HT transmissions.
1432                  */
1433                 mm20_mode = mm40_mode = gf20_mode = gf40_mode = 2;
1434
1435                 /*
1436                  * If erp protection is needed we have to protect HT
1437                  * transmissions with CCK 11M long preamble.
1438                  */
1439                 if (erp->cts_protection) {
1440                         /* don't duplicate RTS/CTS in CCK mode */
1441                         mm20_rate = mm40_rate = 0x0003;
1442                         gf20_rate = gf40_rate = 0x0003;
1443                 }
1444                 break;
1445         }
1446
1447         /* check for STAs not supporting greenfield mode */
1448         if (any_sta_nongf)
1449                 gf20_mode = gf40_mode = 2;
1450
1451         /* Update HT protection config */
1452         rt2800_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
1453         rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_RATE, mm20_rate);
1454         rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_CTRL, mm20_mode);
1455         rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
1456
1457         rt2800_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
1458         rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_RATE, mm40_rate);
1459         rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_CTRL, mm40_mode);
1460         rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
1461
1462         rt2800_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
1463         rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_RATE, gf20_rate);
1464         rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_CTRL, gf20_mode);
1465         rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
1466
1467         rt2800_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
1468         rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_RATE, gf40_rate);
1469         rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_CTRL, gf40_mode);
1470         rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
1471 }
1472
1473 void rt2800_config_erp(struct rt2x00_dev *rt2x00dev, struct rt2x00lib_erp *erp,
1474                        u32 changed)
1475 {
1476         u32 reg;
1477
1478         if (changed & BSS_CHANGED_ERP_PREAMBLE) {
1479                 rt2800_register_read(rt2x00dev, AUTO_RSP_CFG, &reg);
1480                 rt2x00_set_field32(&reg, AUTO_RSP_CFG_BAC_ACK_POLICY,
1481                                    !!erp->short_preamble);
1482                 rt2x00_set_field32(&reg, AUTO_RSP_CFG_AR_PREAMBLE,
1483                                    !!erp->short_preamble);
1484                 rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
1485         }
1486
1487         if (changed & BSS_CHANGED_ERP_CTS_PROT) {
1488                 rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
1489                 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL,
1490                                    erp->cts_protection ? 2 : 0);
1491                 rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
1492         }
1493
1494         if (changed & BSS_CHANGED_BASIC_RATES) {
1495                 rt2800_register_write(rt2x00dev, LEGACY_BASIC_RATE,
1496                                          erp->basic_rates);
1497                 rt2800_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
1498         }
1499
1500         if (changed & BSS_CHANGED_ERP_SLOT) {
1501                 rt2800_register_read(rt2x00dev, BKOFF_SLOT_CFG, &reg);
1502                 rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_SLOT_TIME,
1503                                    erp->slot_time);
1504                 rt2800_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg);
1505
1506                 rt2800_register_read(rt2x00dev, XIFS_TIME_CFG, &reg);
1507                 rt2x00_set_field32(&reg, XIFS_TIME_CFG_EIFS, erp->eifs);
1508                 rt2800_register_write(rt2x00dev, XIFS_TIME_CFG, reg);
1509         }
1510
1511         if (changed & BSS_CHANGED_BEACON_INT) {
1512                 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
1513                 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL,
1514                                    erp->beacon_int * 16);
1515                 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1516         }
1517
1518         if (changed & BSS_CHANGED_HT)
1519                 rt2800_config_ht_opmode(rt2x00dev, erp);
1520 }
1521 EXPORT_SYMBOL_GPL(rt2800_config_erp);
1522
1523 static void rt2800_config_3572bt_ant(struct rt2x00_dev *rt2x00dev)
1524 {
1525         u32 reg;
1526         u16 eeprom;
1527         u8 led_ctrl, led_g_mode, led_r_mode;
1528
1529         rt2800_register_read(rt2x00dev, GPIO_SWITCH, &reg);
1530         if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ) {
1531                 rt2x00_set_field32(&reg, GPIO_SWITCH_0, 1);
1532                 rt2x00_set_field32(&reg, GPIO_SWITCH_1, 1);
1533         } else {
1534                 rt2x00_set_field32(&reg, GPIO_SWITCH_0, 0);
1535                 rt2x00_set_field32(&reg, GPIO_SWITCH_1, 0);
1536         }
1537         rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg);
1538
1539         rt2800_register_read(rt2x00dev, LED_CFG, &reg);
1540         led_g_mode = rt2x00_get_field32(reg, LED_CFG_LED_POLAR) ? 3 : 0;
1541         led_r_mode = rt2x00_get_field32(reg, LED_CFG_LED_POLAR) ? 0 : 3;
1542         if (led_g_mode != rt2x00_get_field32(reg, LED_CFG_G_LED_MODE) ||
1543             led_r_mode != rt2x00_get_field32(reg, LED_CFG_R_LED_MODE)) {
1544                 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom);
1545                 led_ctrl = rt2x00_get_field16(eeprom, EEPROM_FREQ_LED_MODE);
1546                 if (led_ctrl == 0 || led_ctrl > 0x40) {
1547                         rt2x00_set_field32(&reg, LED_CFG_G_LED_MODE, led_g_mode);
1548                         rt2x00_set_field32(&reg, LED_CFG_R_LED_MODE, led_r_mode);
1549                         rt2800_register_write(rt2x00dev, LED_CFG, reg);
1550                 } else {
1551                         rt2800_mcu_request(rt2x00dev, MCU_BAND_SELECT, 0xff,
1552                                            (led_g_mode << 2) | led_r_mode, 1);
1553                 }
1554         }
1555 }
1556
1557 static void rt2800_set_ant_diversity(struct rt2x00_dev *rt2x00dev,
1558                                      enum antenna ant)
1559 {
1560         u32 reg;
1561         u8 eesk_pin = (ant == ANTENNA_A) ? 1 : 0;
1562         u8 gpio_bit3 = (ant == ANTENNA_A) ? 0 : 1;
1563
1564         if (rt2x00_is_pci(rt2x00dev)) {
1565                 rt2800_register_read(rt2x00dev, E2PROM_CSR, &reg);
1566                 rt2x00_set_field32(&reg, E2PROM_CSR_DATA_CLOCK, eesk_pin);
1567                 rt2800_register_write(rt2x00dev, E2PROM_CSR, reg);
1568         } else if (rt2x00_is_usb(rt2x00dev))
1569                 rt2800_mcu_request(rt2x00dev, MCU_ANT_SELECT, 0xff,
1570                                    eesk_pin, 0);
1571
1572         rt2800_register_read(rt2x00dev, GPIO_CTRL, &reg);
1573         rt2x00_set_field32(&reg, GPIO_CTRL_DIR3, 0);
1574         rt2x00_set_field32(&reg, GPIO_CTRL_VAL3, gpio_bit3);
1575         rt2800_register_write(rt2x00dev, GPIO_CTRL, reg);
1576 }
1577
1578 void rt2800_config_ant(struct rt2x00_dev *rt2x00dev, struct antenna_setup *ant)
1579 {
1580         u8 r1;
1581         u8 r3;
1582         u16 eeprom;
1583
1584         rt2800_bbp_read(rt2x00dev, 1, &r1);
1585         rt2800_bbp_read(rt2x00dev, 3, &r3);
1586
1587         if (rt2x00_rt(rt2x00dev, RT3572) &&
1588             test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags))
1589                 rt2800_config_3572bt_ant(rt2x00dev);
1590
1591         /*
1592          * Configure the TX antenna.
1593          */
1594         switch (ant->tx_chain_num) {
1595         case 1:
1596                 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 0);
1597                 break;
1598         case 2:
1599                 if (rt2x00_rt(rt2x00dev, RT3572) &&
1600                     test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags))
1601                         rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 1);
1602                 else
1603                         rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 2);
1604                 break;
1605         case 3:
1606                 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 0);
1607                 break;
1608         }
1609
1610         /*
1611          * Configure the RX antenna.
1612          */
1613         switch (ant->rx_chain_num) {
1614         case 1:
1615                 if (rt2x00_rt(rt2x00dev, RT3070) ||
1616                     rt2x00_rt(rt2x00dev, RT3090) ||
1617                     rt2x00_rt(rt2x00dev, RT3352) ||
1618                     rt2x00_rt(rt2x00dev, RT3390)) {
1619                         rt2x00_eeprom_read(rt2x00dev,
1620                                            EEPROM_NIC_CONF1, &eeprom);
1621                         if (rt2x00_get_field16(eeprom,
1622                                                 EEPROM_NIC_CONF1_ANT_DIVERSITY))
1623                                 rt2800_set_ant_diversity(rt2x00dev,
1624                                                 rt2x00dev->default_ant.rx);
1625                 }
1626                 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 0);
1627                 break;
1628         case 2:
1629                 if (rt2x00_rt(rt2x00dev, RT3572) &&
1630                     test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags)) {
1631                         rt2x00_set_field8(&r3, BBP3_RX_ADC, 1);
1632                         rt2x00_set_field8(&r3, BBP3_RX_ANTENNA,
1633                                 rt2x00dev->curr_band == IEEE80211_BAND_5GHZ);
1634                         rt2800_set_ant_diversity(rt2x00dev, ANTENNA_B);
1635                 } else {
1636                         rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 1);
1637                 }
1638                 break;
1639         case 3:
1640                 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 2);
1641                 break;
1642         }
1643
1644         rt2800_bbp_write(rt2x00dev, 3, r3);
1645         rt2800_bbp_write(rt2x00dev, 1, r1);
1646 }
1647 EXPORT_SYMBOL_GPL(rt2800_config_ant);
1648
1649 static void rt2800_config_lna_gain(struct rt2x00_dev *rt2x00dev,
1650                                    struct rt2x00lib_conf *libconf)
1651 {
1652         u16 eeprom;
1653         short lna_gain;
1654
1655         if (libconf->rf.channel <= 14) {
1656                 rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom);
1657                 lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_BG);
1658         } else if (libconf->rf.channel <= 64) {
1659                 rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom);
1660                 lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_A0);
1661         } else if (libconf->rf.channel <= 128) {
1662                 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &eeprom);
1663                 lna_gain = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG2_LNA_A1);
1664         } else {
1665                 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &eeprom);
1666                 lna_gain = rt2x00_get_field16(eeprom, EEPROM_RSSI_A2_LNA_A2);
1667         }
1668
1669         rt2x00dev->lna_gain = lna_gain;
1670 }
1671
1672 static void rt2800_config_channel_rf2xxx(struct rt2x00_dev *rt2x00dev,
1673                                          struct ieee80211_conf *conf,
1674                                          struct rf_channel *rf,
1675                                          struct channel_info *info)
1676 {
1677         rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset);
1678
1679         if (rt2x00dev->default_ant.tx_chain_num == 1)
1680                 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_TX1, 1);
1681
1682         if (rt2x00dev->default_ant.rx_chain_num == 1) {
1683                 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX1, 1);
1684                 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
1685         } else if (rt2x00dev->default_ant.rx_chain_num == 2)
1686                 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
1687
1688         if (rf->channel > 14) {
1689                 /*
1690                  * When TX power is below 0, we should increase it by 7 to
1691                  * make it a positive value (Minimum value is -7).
1692                  * However this means that values between 0 and 7 have
1693                  * double meaning, and we should set a 7DBm boost flag.
1694                  */
1695                 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A_7DBM_BOOST,
1696                                    (info->default_power1 >= 0));
1697
1698                 if (info->default_power1 < 0)
1699                         info->default_power1 += 7;
1700
1701                 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A, info->default_power1);
1702
1703                 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A_7DBM_BOOST,
1704                                    (info->default_power2 >= 0));
1705
1706                 if (info->default_power2 < 0)
1707                         info->default_power2 += 7;
1708
1709                 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A, info->default_power2);
1710         } else {
1711                 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_G, info->default_power1);
1712                 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_G, info->default_power2);
1713         }
1714
1715         rt2x00_set_field32(&rf->rf4, RF4_HT40, conf_is_ht40(conf));
1716
1717         rt2800_rf_write(rt2x00dev, 1, rf->rf1);
1718         rt2800_rf_write(rt2x00dev, 2, rf->rf2);
1719         rt2800_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
1720         rt2800_rf_write(rt2x00dev, 4, rf->rf4);
1721
1722         udelay(200);
1723
1724         rt2800_rf_write(rt2x00dev, 1, rf->rf1);
1725         rt2800_rf_write(rt2x00dev, 2, rf->rf2);
1726         rt2800_rf_write(rt2x00dev, 3, rf->rf3 | 0x00000004);
1727         rt2800_rf_write(rt2x00dev, 4, rf->rf4);
1728
1729         udelay(200);
1730
1731         rt2800_rf_write(rt2x00dev, 1, rf->rf1);
1732         rt2800_rf_write(rt2x00dev, 2, rf->rf2);
1733         rt2800_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
1734         rt2800_rf_write(rt2x00dev, 4, rf->rf4);
1735 }
1736
1737 static void rt2800_config_channel_rf3xxx(struct rt2x00_dev *rt2x00dev,
1738                                          struct ieee80211_conf *conf,
1739                                          struct rf_channel *rf,
1740                                          struct channel_info *info)
1741 {
1742         struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
1743         u8 rfcsr, calib_tx, calib_rx;
1744
1745         rt2800_rfcsr_write(rt2x00dev, 2, rf->rf1);
1746
1747         rt2800_rfcsr_read(rt2x00dev, 3, &rfcsr);
1748         rt2x00_set_field8(&rfcsr, RFCSR3_K, rf->rf3);
1749         rt2800_rfcsr_write(rt2x00dev, 3, rfcsr);
1750
1751         rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
1752         rt2x00_set_field8(&rfcsr, RFCSR6_R1, rf->rf2);
1753         rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
1754
1755         rt2800_rfcsr_read(rt2x00dev, 12, &rfcsr);
1756         rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER, info->default_power1);
1757         rt2800_rfcsr_write(rt2x00dev, 12, rfcsr);
1758
1759         rt2800_rfcsr_read(rt2x00dev, 13, &rfcsr);
1760         rt2x00_set_field8(&rfcsr, RFCSR13_TX_POWER, info->default_power2);
1761         rt2800_rfcsr_write(rt2x00dev, 13, rfcsr);
1762
1763         rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
1764         rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0);
1765         rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD,
1766                           rt2x00dev->default_ant.rx_chain_num <= 1);
1767         rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD,
1768                           rt2x00dev->default_ant.rx_chain_num <= 2);
1769         rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0);
1770         rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD,
1771                           rt2x00dev->default_ant.tx_chain_num <= 1);
1772         rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD,
1773                           rt2x00dev->default_ant.tx_chain_num <= 2);
1774         rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
1775
1776         rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
1777         rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 1);
1778         rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
1779         msleep(1);
1780         rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 0);
1781         rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
1782
1783         rt2800_rfcsr_read(rt2x00dev, 23, &rfcsr);
1784         rt2x00_set_field8(&rfcsr, RFCSR23_FREQ_OFFSET, rt2x00dev->freq_offset);
1785         rt2800_rfcsr_write(rt2x00dev, 23, rfcsr);
1786
1787         if (rt2x00_rt(rt2x00dev, RT3390)) {
1788                 calib_tx = conf_is_ht40(conf) ? 0x68 : 0x4f;
1789                 calib_rx = conf_is_ht40(conf) ? 0x6f : 0x4f;
1790         } else {
1791                 if (conf_is_ht40(conf)) {
1792                         calib_tx = drv_data->calibration_bw40;
1793                         calib_rx = drv_data->calibration_bw40;
1794                 } else {
1795                         calib_tx = drv_data->calibration_bw20;
1796                         calib_rx = drv_data->calibration_bw20;
1797                 }
1798         }
1799
1800         rt2800_rfcsr_read(rt2x00dev, 24, &rfcsr);
1801         rt2x00_set_field8(&rfcsr, RFCSR24_TX_CALIB, calib_tx);
1802         rt2800_rfcsr_write(rt2x00dev, 24, rfcsr);
1803
1804         rt2800_rfcsr_read(rt2x00dev, 31, &rfcsr);
1805         rt2x00_set_field8(&rfcsr, RFCSR31_RX_CALIB, calib_rx);
1806         rt2800_rfcsr_write(rt2x00dev, 31, rfcsr);
1807
1808         rt2800_rfcsr_read(rt2x00dev, 7, &rfcsr);
1809         rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1);
1810         rt2800_rfcsr_write(rt2x00dev, 7, rfcsr);
1811
1812         rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
1813         rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 1);
1814         rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
1815         msleep(1);
1816         rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 0);
1817         rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
1818 }
1819
1820 static void rt2800_config_channel_rf3052(struct rt2x00_dev *rt2x00dev,
1821                                          struct ieee80211_conf *conf,
1822                                          struct rf_channel *rf,
1823                                          struct channel_info *info)
1824 {
1825         struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
1826         u8 rfcsr;
1827         u32 reg;
1828
1829         if (rf->channel <= 14) {
1830                 rt2800_bbp_write(rt2x00dev, 25, drv_data->bbp25);
1831                 rt2800_bbp_write(rt2x00dev, 26, drv_data->bbp26);
1832         } else {
1833                 rt2800_bbp_write(rt2x00dev, 25, 0x09);
1834                 rt2800_bbp_write(rt2x00dev, 26, 0xff);
1835         }
1836
1837         rt2800_rfcsr_write(rt2x00dev, 2, rf->rf1);
1838         rt2800_rfcsr_write(rt2x00dev, 3, rf->rf3);
1839
1840         rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
1841         rt2x00_set_field8(&rfcsr, RFCSR6_R1, rf->rf2);
1842         if (rf->channel <= 14)
1843                 rt2x00_set_field8(&rfcsr, RFCSR6_TXDIV, 2);
1844         else
1845                 rt2x00_set_field8(&rfcsr, RFCSR6_TXDIV, 1);
1846         rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
1847
1848         rt2800_rfcsr_read(rt2x00dev, 5, &rfcsr);
1849         if (rf->channel <= 14)
1850                 rt2x00_set_field8(&rfcsr, RFCSR5_R1, 1);
1851         else
1852                 rt2x00_set_field8(&rfcsr, RFCSR5_R1, 2);
1853         rt2800_rfcsr_write(rt2x00dev, 5, rfcsr);
1854
1855         rt2800_rfcsr_read(rt2x00dev, 12, &rfcsr);
1856         if (rf->channel <= 14) {
1857                 rt2x00_set_field8(&rfcsr, RFCSR12_DR0, 3);
1858                 rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER,
1859                                   info->default_power1);
1860         } else {
1861                 rt2x00_set_field8(&rfcsr, RFCSR12_DR0, 7);
1862                 rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER,
1863                                 (info->default_power1 & 0x3) |
1864                                 ((info->default_power1 & 0xC) << 1));
1865         }
1866         rt2800_rfcsr_write(rt2x00dev, 12, rfcsr);
1867
1868         rt2800_rfcsr_read(rt2x00dev, 13, &rfcsr);
1869         if (rf->channel <= 14) {
1870                 rt2x00_set_field8(&rfcsr, RFCSR13_DR0, 3);
1871                 rt2x00_set_field8(&rfcsr, RFCSR13_TX_POWER,
1872                                   info->default_power2);
1873         } else {
1874                 rt2x00_set_field8(&rfcsr, RFCSR13_DR0, 7);
1875                 rt2x00_set_field8(&rfcsr, RFCSR13_TX_POWER,
1876                                 (info->default_power2 & 0x3) |
1877                                 ((info->default_power2 & 0xC) << 1));
1878         }
1879         rt2800_rfcsr_write(rt2x00dev, 13, rfcsr);
1880
1881         rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
1882         rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0);
1883         rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0);
1884         rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 0);
1885         rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 0);
1886         rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 0);
1887         rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 0);
1888         if (test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags)) {
1889                 if (rf->channel <= 14) {
1890                         rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 1);
1891                         rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 1);
1892                 }
1893                 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 1);
1894                 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 1);
1895         } else {
1896                 switch (rt2x00dev->default_ant.tx_chain_num) {
1897                 case 1:
1898                         rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
1899                 case 2:
1900                         rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 1);
1901                         break;
1902                 }
1903
1904                 switch (rt2x00dev->default_ant.rx_chain_num) {
1905                 case 1:
1906                         rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
1907                 case 2:
1908                         rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 1);
1909                         break;
1910                 }
1911         }
1912         rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
1913
1914         rt2800_rfcsr_read(rt2x00dev, 23, &rfcsr);
1915         rt2x00_set_field8(&rfcsr, RFCSR23_FREQ_OFFSET, rt2x00dev->freq_offset);
1916         rt2800_rfcsr_write(rt2x00dev, 23, rfcsr);
1917
1918         if (conf_is_ht40(conf)) {
1919                 rt2800_rfcsr_write(rt2x00dev, 24, drv_data->calibration_bw40);
1920                 rt2800_rfcsr_write(rt2x00dev, 31, drv_data->calibration_bw40);
1921         } else {
1922                 rt2800_rfcsr_write(rt2x00dev, 24, drv_data->calibration_bw20);
1923                 rt2800_rfcsr_write(rt2x00dev, 31, drv_data->calibration_bw20);
1924         }
1925
1926         if (rf->channel <= 14) {
1927                 rt2800_rfcsr_write(rt2x00dev, 7, 0xd8);
1928                 rt2800_rfcsr_write(rt2x00dev, 9, 0xc3);
1929                 rt2800_rfcsr_write(rt2x00dev, 10, 0xf1);
1930                 rt2800_rfcsr_write(rt2x00dev, 11, 0xb9);
1931                 rt2800_rfcsr_write(rt2x00dev, 15, 0x53);
1932                 rfcsr = 0x4c;
1933                 rt2x00_set_field8(&rfcsr, RFCSR16_TXMIXER_GAIN,
1934                                   drv_data->txmixer_gain_24g);
1935                 rt2800_rfcsr_write(rt2x00dev, 16, rfcsr);
1936                 rt2800_rfcsr_write(rt2x00dev, 17, 0x23);
1937                 rt2800_rfcsr_write(rt2x00dev, 19, 0x93);
1938                 rt2800_rfcsr_write(rt2x00dev, 20, 0xb3);
1939                 rt2800_rfcsr_write(rt2x00dev, 25, 0x15);
1940                 rt2800_rfcsr_write(rt2x00dev, 26, 0x85);
1941                 rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
1942                 rt2800_rfcsr_write(rt2x00dev, 29, 0x9b);
1943         } else {
1944                 rt2800_rfcsr_read(rt2x00dev, 7, &rfcsr);
1945                 rt2x00_set_field8(&rfcsr, RFCSR7_BIT2, 1);
1946                 rt2x00_set_field8(&rfcsr, RFCSR7_BIT3, 0);
1947                 rt2x00_set_field8(&rfcsr, RFCSR7_BIT4, 1);
1948                 rt2x00_set_field8(&rfcsr, RFCSR7_BITS67, 0);
1949                 rt2800_rfcsr_write(rt2x00dev, 7, rfcsr);
1950                 rt2800_rfcsr_write(rt2x00dev, 9, 0xc0);
1951                 rt2800_rfcsr_write(rt2x00dev, 10, 0xf1);
1952                 rt2800_rfcsr_write(rt2x00dev, 11, 0x00);
1953                 rt2800_rfcsr_write(rt2x00dev, 15, 0x43);
1954                 rfcsr = 0x7a;
1955                 rt2x00_set_field8(&rfcsr, RFCSR16_TXMIXER_GAIN,
1956                                   drv_data->txmixer_gain_5g);
1957                 rt2800_rfcsr_write(rt2x00dev, 16, rfcsr);
1958                 rt2800_rfcsr_write(rt2x00dev, 17, 0x23);
1959                 if (rf->channel <= 64) {
1960                         rt2800_rfcsr_write(rt2x00dev, 19, 0xb7);
1961                         rt2800_rfcsr_write(rt2x00dev, 20, 0xf6);
1962                         rt2800_rfcsr_write(rt2x00dev, 25, 0x3d);
1963                 } else if (rf->channel <= 128) {
1964                         rt2800_rfcsr_write(rt2x00dev, 19, 0x74);
1965                         rt2800_rfcsr_write(rt2x00dev, 20, 0xf4);
1966                         rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
1967                 } else {
1968                         rt2800_rfcsr_write(rt2x00dev, 19, 0x72);
1969                         rt2800_rfcsr_write(rt2x00dev, 20, 0xf3);
1970                         rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
1971                 }
1972                 rt2800_rfcsr_write(rt2x00dev, 26, 0x87);
1973                 rt2800_rfcsr_write(rt2x00dev, 27, 0x01);
1974                 rt2800_rfcsr_write(rt2x00dev, 29, 0x9f);
1975         }
1976
1977         rt2800_register_read(rt2x00dev, GPIO_CTRL, &reg);
1978         rt2x00_set_field32(&reg, GPIO_CTRL_DIR7, 0);
1979         if (rf->channel <= 14)
1980                 rt2x00_set_field32(&reg, GPIO_CTRL_VAL7, 1);
1981         else
1982                 rt2x00_set_field32(&reg, GPIO_CTRL_VAL7, 0);
1983         rt2800_register_write(rt2x00dev, GPIO_CTRL, reg);
1984
1985         rt2800_rfcsr_read(rt2x00dev, 7, &rfcsr);
1986         rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1);
1987         rt2800_rfcsr_write(rt2x00dev, 7, rfcsr);
1988 }
1989
1990 #define POWER_BOUND             0x27
1991 #define POWER_BOUND_5G          0x2b
1992 #define FREQ_OFFSET_BOUND       0x5f
1993
1994 static void rt2800_config_channel_rf3290(struct rt2x00_dev *rt2x00dev,
1995                                          struct ieee80211_conf *conf,
1996                                          struct rf_channel *rf,
1997                                          struct channel_info *info)
1998 {
1999         u8 rfcsr;
2000
2001         rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1);
2002         rt2800_rfcsr_write(rt2x00dev, 9, rf->rf3);
2003         rt2800_rfcsr_read(rt2x00dev, 11, &rfcsr);
2004         rt2x00_set_field8(&rfcsr, RFCSR11_R, rf->rf2);
2005         rt2800_rfcsr_write(rt2x00dev, 11, rfcsr);
2006
2007         rt2800_rfcsr_read(rt2x00dev, 49, &rfcsr);
2008         if (info->default_power1 > POWER_BOUND)
2009                 rt2x00_set_field8(&rfcsr, RFCSR49_TX, POWER_BOUND);
2010         else
2011                 rt2x00_set_field8(&rfcsr, RFCSR49_TX, info->default_power1);
2012         rt2800_rfcsr_write(rt2x00dev, 49, rfcsr);
2013
2014         rt2800_rfcsr_read(rt2x00dev, 17, &rfcsr);
2015         if (rt2x00dev->freq_offset > FREQ_OFFSET_BOUND)
2016                 rt2x00_set_field8(&rfcsr, RFCSR17_CODE, FREQ_OFFSET_BOUND);
2017         else
2018                 rt2x00_set_field8(&rfcsr, RFCSR17_CODE, rt2x00dev->freq_offset);
2019         rt2800_rfcsr_write(rt2x00dev, 17, rfcsr);
2020
2021         if (rf->channel <= 14) {
2022                 if (rf->channel == 6)
2023                         rt2800_bbp_write(rt2x00dev, 68, 0x0c);
2024                 else
2025                         rt2800_bbp_write(rt2x00dev, 68, 0x0b);
2026
2027                 if (rf->channel >= 1 && rf->channel <= 6)
2028                         rt2800_bbp_write(rt2x00dev, 59, 0x0f);
2029                 else if (rf->channel >= 7 && rf->channel <= 11)
2030                         rt2800_bbp_write(rt2x00dev, 59, 0x0e);
2031                 else if (rf->channel >= 12 && rf->channel <= 14)
2032                         rt2800_bbp_write(rt2x00dev, 59, 0x0d);
2033         }
2034 }
2035
2036 static void rt2800_config_channel_rf3322(struct rt2x00_dev *rt2x00dev,
2037                                          struct ieee80211_conf *conf,
2038                                          struct rf_channel *rf,
2039                                          struct channel_info *info)
2040 {
2041         u8 rfcsr;
2042
2043         rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1);
2044         rt2800_rfcsr_write(rt2x00dev, 9, rf->rf3);
2045
2046         rt2800_rfcsr_write(rt2x00dev, 11, 0x42);
2047         rt2800_rfcsr_write(rt2x00dev, 12, 0x1c);
2048         rt2800_rfcsr_write(rt2x00dev, 13, 0x00);
2049
2050         if (info->default_power1 > POWER_BOUND)
2051                 rt2800_rfcsr_write(rt2x00dev, 47, POWER_BOUND);
2052         else
2053                 rt2800_rfcsr_write(rt2x00dev, 47, info->default_power1);
2054
2055         if (info->default_power2 > POWER_BOUND)
2056                 rt2800_rfcsr_write(rt2x00dev, 48, POWER_BOUND);
2057         else
2058                 rt2800_rfcsr_write(rt2x00dev, 48, info->default_power2);
2059
2060         rt2800_rfcsr_read(rt2x00dev, 17, &rfcsr);
2061         if (rt2x00dev->freq_offset > FREQ_OFFSET_BOUND)
2062                 rt2x00_set_field8(&rfcsr, RFCSR17_CODE, FREQ_OFFSET_BOUND);
2063         else
2064                 rt2x00_set_field8(&rfcsr, RFCSR17_CODE, rt2x00dev->freq_offset);
2065
2066         rt2800_rfcsr_write(rt2x00dev, 17, rfcsr);
2067
2068         rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
2069         rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 1);
2070         rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 1);
2071
2072         if ( rt2x00dev->default_ant.tx_chain_num == 2 )
2073                 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
2074         else
2075                 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 0);
2076
2077         if ( rt2x00dev->default_ant.rx_chain_num == 2 )
2078                 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
2079         else
2080                 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 0);
2081
2082         rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 0);
2083         rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 0);
2084
2085         rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
2086
2087         rt2800_rfcsr_write(rt2x00dev, 31, 80);
2088 }
2089
2090 static void rt2800_config_channel_rf53xx(struct rt2x00_dev *rt2x00dev,
2091                                          struct ieee80211_conf *conf,
2092                                          struct rf_channel *rf,
2093                                          struct channel_info *info)
2094 {
2095         u8 rfcsr;
2096
2097         rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1);
2098         rt2800_rfcsr_write(rt2x00dev, 9, rf->rf3);
2099         rt2800_rfcsr_read(rt2x00dev, 11, &rfcsr);
2100         rt2x00_set_field8(&rfcsr, RFCSR11_R, rf->rf2);
2101         rt2800_rfcsr_write(rt2x00dev, 11, rfcsr);
2102
2103         rt2800_rfcsr_read(rt2x00dev, 49, &rfcsr);
2104         if (info->default_power1 > POWER_BOUND)
2105                 rt2x00_set_field8(&rfcsr, RFCSR49_TX, POWER_BOUND);
2106         else
2107                 rt2x00_set_field8(&rfcsr, RFCSR49_TX, info->default_power1);
2108         rt2800_rfcsr_write(rt2x00dev, 49, rfcsr);
2109
2110         if (rt2x00_rt(rt2x00dev, RT5392)) {
2111                 rt2800_rfcsr_read(rt2x00dev, 50, &rfcsr);
2112                 if (info->default_power1 > POWER_BOUND)
2113                         rt2x00_set_field8(&rfcsr, RFCSR50_TX, POWER_BOUND);
2114                 else
2115                         rt2x00_set_field8(&rfcsr, RFCSR50_TX,
2116                                           info->default_power2);
2117                 rt2800_rfcsr_write(rt2x00dev, 50, rfcsr);
2118         }
2119
2120         rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
2121         if (rt2x00_rt(rt2x00dev, RT5392)) {
2122                 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
2123                 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
2124         }
2125         rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
2126         rt2x00_set_field8(&rfcsr, RFCSR1_PLL_PD, 1);
2127         rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 1);
2128         rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 1);
2129         rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
2130
2131         rt2800_rfcsr_read(rt2x00dev, 17, &rfcsr);
2132         if (rt2x00dev->freq_offset > FREQ_OFFSET_BOUND)
2133                 rt2x00_set_field8(&rfcsr, RFCSR17_CODE, FREQ_OFFSET_BOUND);
2134         else
2135                 rt2x00_set_field8(&rfcsr, RFCSR17_CODE, rt2x00dev->freq_offset);
2136         rt2800_rfcsr_write(rt2x00dev, 17, rfcsr);
2137
2138         if (rf->channel <= 14) {
2139                 int idx = rf->channel-1;
2140
2141                 if (test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags)) {
2142                         if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) {
2143                                 /* r55/r59 value array of channel 1~14 */
2144                                 static const char r55_bt_rev[] = {0x83, 0x83,
2145                                         0x83, 0x73, 0x73, 0x63, 0x53, 0x53,
2146                                         0x53, 0x43, 0x43, 0x43, 0x43, 0x43};
2147                                 static const char r59_bt_rev[] = {0x0e, 0x0e,
2148                                         0x0e, 0x0e, 0x0e, 0x0b, 0x0a, 0x09,
2149                                         0x07, 0x07, 0x07, 0x07, 0x07, 0x07};
2150
2151                                 rt2800_rfcsr_write(rt2x00dev, 55,
2152                                                    r55_bt_rev[idx]);
2153                                 rt2800_rfcsr_write(rt2x00dev, 59,
2154                                                    r59_bt_rev[idx]);
2155                         } else {
2156                                 static const char r59_bt[] = {0x8b, 0x8b, 0x8b,
2157                                         0x8b, 0x8b, 0x8b, 0x8b, 0x8a, 0x89,
2158                                         0x88, 0x88, 0x86, 0x85, 0x84};
2159
2160                                 rt2800_rfcsr_write(rt2x00dev, 59, r59_bt[idx]);
2161                         }
2162                 } else {
2163                         if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) {
2164                                 static const char r55_nonbt_rev[] = {0x23, 0x23,
2165                                         0x23, 0x23, 0x13, 0x13, 0x03, 0x03,
2166                                         0x03, 0x03, 0x03, 0x03, 0x03, 0x03};
2167                                 static const char r59_nonbt_rev[] = {0x07, 0x07,
2168                                         0x07, 0x07, 0x07, 0x07, 0x07, 0x07,
2169                                         0x07, 0x07, 0x06, 0x05, 0x04, 0x04};
2170
2171                                 rt2800_rfcsr_write(rt2x00dev, 55,
2172                                                    r55_nonbt_rev[idx]);
2173                                 rt2800_rfcsr_write(rt2x00dev, 59,
2174                                                    r59_nonbt_rev[idx]);
2175                         } else if (rt2x00_rt(rt2x00dev, RT5390) ||
2176                                    rt2x00_rt(rt2x00dev, RT5392)) {
2177                                 static const char r59_non_bt[] = {0x8f, 0x8f,
2178                                         0x8f, 0x8f, 0x8f, 0x8f, 0x8f, 0x8d,
2179                                         0x8a, 0x88, 0x88, 0x87, 0x87, 0x86};
2180
2181                                 rt2800_rfcsr_write(rt2x00dev, 59,
2182                                                    r59_non_bt[idx]);
2183                         }
2184                 }
2185         }
2186 }
2187
2188 static void rt2800_config_channel_rf55xx(struct rt2x00_dev *rt2x00dev,
2189                                          struct ieee80211_conf *conf,
2190                                          struct rf_channel *rf,
2191                                          struct channel_info *info)
2192 {
2193         u8 rfcsr, ep_reg;
2194         int power_bound;
2195
2196         /* TODO */
2197         const bool is_11b = false;
2198         const bool is_type_ep = false;
2199
2200
2201         /* Order of values on rf_channel entry: N, K, mod, R */
2202         rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1 & 0xff);
2203
2204         rt2800_rfcsr_read(rt2x00dev,  9, &rfcsr);
2205         rt2x00_set_field8(&rfcsr, RFCSR9_K, rf->rf2 & 0xf);
2206         rt2x00_set_field8(&rfcsr, RFCSR9_N, (rf->rf1 & 0x100) >> 8);
2207         rt2x00_set_field8(&rfcsr, RFCSR9_MOD, ((rf->rf3 - 8) & 0x4) >> 2);
2208         rt2800_rfcsr_write(rt2x00dev, 9, rfcsr);
2209
2210         rt2800_rfcsr_read(rt2x00dev, 11, &rfcsr);
2211         rt2x00_set_field8(&rfcsr, RFCSR11_R, rf->rf4 - 1);
2212         rt2x00_set_field8(&rfcsr, RFCSR11_MOD, (rf->rf3 - 8) & 0x3);
2213         rt2800_rfcsr_write(rt2x00dev, 11, rfcsr);
2214
2215         if (rf->channel <= 14) {
2216                 rt2800_rfcsr_write(rt2x00dev, 10, 0x90);
2217                 /* FIXME: RF11 owerwrite ? */
2218                 rt2800_rfcsr_write(rt2x00dev, 11, 0x4A);
2219                 rt2800_rfcsr_write(rt2x00dev, 12, 0x52);
2220                 rt2800_rfcsr_write(rt2x00dev, 13, 0x42);
2221                 rt2800_rfcsr_write(rt2x00dev, 22, 0x40);
2222                 rt2800_rfcsr_write(rt2x00dev, 24, 0x4A);
2223                 rt2800_rfcsr_write(rt2x00dev, 25, 0x80);
2224                 rt2800_rfcsr_write(rt2x00dev, 27, 0x42);
2225                 rt2800_rfcsr_write(rt2x00dev, 36, 0x80);
2226                 rt2800_rfcsr_write(rt2x00dev, 37, 0x08);
2227                 rt2800_rfcsr_write(rt2x00dev, 38, 0x89);
2228                 rt2800_rfcsr_write(rt2x00dev, 39, 0x1B);
2229                 rt2800_rfcsr_write(rt2x00dev, 40, 0x0D);
2230                 rt2800_rfcsr_write(rt2x00dev, 41, 0x9B);
2231                 rt2800_rfcsr_write(rt2x00dev, 42, 0xD5);
2232                 rt2800_rfcsr_write(rt2x00dev, 43, 0x72);
2233                 rt2800_rfcsr_write(rt2x00dev, 44, 0x0E);
2234                 rt2800_rfcsr_write(rt2x00dev, 45, 0xA2);
2235                 rt2800_rfcsr_write(rt2x00dev, 46, 0x6B);
2236                 rt2800_rfcsr_write(rt2x00dev, 48, 0x10);
2237                 rt2800_rfcsr_write(rt2x00dev, 51, 0x3E);
2238                 rt2800_rfcsr_write(rt2x00dev, 52, 0x48);
2239                 rt2800_rfcsr_write(rt2x00dev, 54, 0x38);
2240                 rt2800_rfcsr_write(rt2x00dev, 56, 0xA1);
2241                 rt2800_rfcsr_write(rt2x00dev, 57, 0x00);
2242                 rt2800_rfcsr_write(rt2x00dev, 58, 0x39);
2243                 rt2800_rfcsr_write(rt2x00dev, 60, 0x45);
2244                 rt2800_rfcsr_write(rt2x00dev, 61, 0x91);
2245                 rt2800_rfcsr_write(rt2x00dev, 62, 0x39);
2246
2247                 /* TODO RF27 <- tssi */
2248
2249                 rfcsr = rf->channel <= 10 ? 0x07 : 0x06;
2250                 rt2800_rfcsr_write(rt2x00dev, 23, rfcsr);
2251                 rt2800_rfcsr_write(rt2x00dev, 59, rfcsr);
2252
2253                 if (is_11b) {
2254                         /* CCK */
2255                         rt2800_rfcsr_write(rt2x00dev, 31, 0xF8);
2256                         rt2800_rfcsr_write(rt2x00dev, 32, 0xC0);
2257                         if (is_type_ep)
2258                                 rt2800_rfcsr_write(rt2x00dev, 55, 0x06);
2259                         else
2260                                 rt2800_rfcsr_write(rt2x00dev, 55, 0x47);
2261                 } else {
2262                         /* OFDM */
2263                         if (is_type_ep)
2264                                 rt2800_rfcsr_write(rt2x00dev, 55, 0x03);
2265                         else
2266                                 rt2800_rfcsr_write(rt2x00dev, 55, 0x43);
2267                 }
2268
2269                 power_bound = POWER_BOUND;
2270                 ep_reg = 0x2;
2271         } else {
2272                 rt2800_rfcsr_write(rt2x00dev, 10, 0x97);
2273                 /* FIMXE: RF11 overwrite */
2274                 rt2800_rfcsr_write(rt2x00dev, 11, 0x40);
2275                 rt2800_rfcsr_write(rt2x00dev, 25, 0xBF);
2276                 rt2800_rfcsr_write(rt2x00dev, 27, 0x42);
2277                 rt2800_rfcsr_write(rt2x00dev, 36, 0x00);
2278                 rt2800_rfcsr_write(rt2x00dev, 37, 0x04);
2279                 rt2800_rfcsr_write(rt2x00dev, 38, 0x85);
2280                 rt2800_rfcsr_write(rt2x00dev, 40, 0x42);
2281                 rt2800_rfcsr_write(rt2x00dev, 41, 0xBB);
2282                 rt2800_rfcsr_write(rt2x00dev, 42, 0xD7);
2283                 rt2800_rfcsr_write(rt2x00dev, 45, 0x41);
2284                 rt2800_rfcsr_write(rt2x00dev, 48, 0x00);
2285                 rt2800_rfcsr_write(rt2x00dev, 57, 0x77);
2286                 rt2800_rfcsr_write(rt2x00dev, 60, 0x05);
2287                 rt2800_rfcsr_write(rt2x00dev, 61, 0x01);
2288
2289                 /* TODO RF27 <- tssi */
2290
2291                 if (rf->channel >= 36 && rf->channel <= 64) {
2292
2293                         rt2800_rfcsr_write(rt2x00dev, 12, 0x2E);
2294                         rt2800_rfcsr_write(rt2x00dev, 13, 0x22);
2295                         rt2800_rfcsr_write(rt2x00dev, 22, 0x60);
2296                         rt2800_rfcsr_write(rt2x00dev, 23, 0x7F);
2297                         if (rf->channel <= 50)
2298                                 rt2800_rfcsr_write(rt2x00dev, 24, 0x09);
2299                         else if (rf->channel >= 52)
2300                                 rt2800_rfcsr_write(rt2x00dev, 24, 0x07);
2301                         rt2800_rfcsr_write(rt2x00dev, 39, 0x1C);
2302                         rt2800_rfcsr_write(rt2x00dev, 43, 0x5B);
2303                         rt2800_rfcsr_write(rt2x00dev, 44, 0X40);
2304                         rt2800_rfcsr_write(rt2x00dev, 46, 0X00);
2305                         rt2800_rfcsr_write(rt2x00dev, 51, 0xFE);
2306                         rt2800_rfcsr_write(rt2x00dev, 52, 0x0C);
2307                         rt2800_rfcsr_write(rt2x00dev, 54, 0xF8);
2308                         if (rf->channel <= 50) {
2309                                 rt2800_rfcsr_write(rt2x00dev, 55, 0x06),
2310                                 rt2800_rfcsr_write(rt2x00dev, 56, 0xD3);
2311                         } else if (rf->channel >= 52) {
2312                                 rt2800_rfcsr_write(rt2x00dev, 55, 0x04);
2313                                 rt2800_rfcsr_write(rt2x00dev, 56, 0xBB);
2314                         }
2315
2316                         rt2800_rfcsr_write(rt2x00dev, 58, 0x15);
2317                         rt2800_rfcsr_write(rt2x00dev, 59, 0x7F);
2318                         rt2800_rfcsr_write(rt2x00dev, 62, 0x15);
2319
2320                 } else if (rf->channel >= 100 && rf->channel <= 165) {
2321
2322                         rt2800_rfcsr_write(rt2x00dev, 12, 0x0E);
2323                         rt2800_rfcsr_write(rt2x00dev, 13, 0x42);
2324                         rt2800_rfcsr_write(rt2x00dev, 22, 0x40);
2325                         if (rf->channel <= 153) {
2326                                 rt2800_rfcsr_write(rt2x00dev, 23, 0x3C);
2327                                 rt2800_rfcsr_write(rt2x00dev, 24, 0x06);
2328                         } else if (rf->channel >= 155) {
2329                                 rt2800_rfcsr_write(rt2x00dev, 23, 0x38);
2330                                 rt2800_rfcsr_write(rt2x00dev, 24, 0x05);
2331                         }
2332                         if (rf->channel <= 138) {
2333                                 rt2800_rfcsr_write(rt2x00dev, 39, 0x1A);
2334                                 rt2800_rfcsr_write(rt2x00dev, 43, 0x3B);
2335                                 rt2800_rfcsr_write(rt2x00dev, 44, 0x20);
2336                                 rt2800_rfcsr_write(rt2x00dev, 46, 0x18);
2337                         } else if (rf->channel >= 140) {
2338                                 rt2800_rfcsr_write(rt2x00dev, 39, 0x18);
2339                                 rt2800_rfcsr_write(rt2x00dev, 43, 0x1B);
2340                                 rt2800_rfcsr_write(rt2x00dev, 44, 0x10);
2341                                 rt2800_rfcsr_write(rt2x00dev, 46, 0X08);
2342                         }
2343                         if (rf->channel <= 124)
2344                                 rt2800_rfcsr_write(rt2x00dev, 51, 0xFC);
2345                         else if (rf->channel >= 126)
2346                                 rt2800_rfcsr_write(rt2x00dev, 51, 0xEC);
2347                         if (rf->channel <= 138)
2348                                 rt2800_rfcsr_write(rt2x00dev, 52, 0x06);
2349                         else if (rf->channel >= 140)
2350                                 rt2800_rfcsr_write(rt2x00dev, 52, 0x06);
2351                         rt2800_rfcsr_write(rt2x00dev, 54, 0xEB);
2352                         if (rf->channel <= 138)
2353                                 rt2800_rfcsr_write(rt2x00dev, 55, 0x01);
2354                         else if (rf->channel >= 140)
2355                                 rt2800_rfcsr_write(rt2x00dev, 55, 0x00);
2356                         if (rf->channel <= 128)
2357                                 rt2800_rfcsr_write(rt2x00dev, 56, 0xBB);
2358                         else if (rf->channel >= 130)
2359                                 rt2800_rfcsr_write(rt2x00dev, 56, 0xAB);
2360                         if (rf->channel <= 116)
2361                                 rt2800_rfcsr_write(rt2x00dev, 58, 0x1D);
2362                         else if (rf->channel >= 118)
2363                                 rt2800_rfcsr_write(rt2x00dev, 58, 0x15);
2364                         if (rf->channel <= 138)
2365                                 rt2800_rfcsr_write(rt2x00dev, 59, 0x3F);
2366                         else if (rf->channel >= 140)
2367                                 rt2800_rfcsr_write(rt2x00dev, 59, 0x7C);
2368                         if (rf->channel <= 116)
2369                                 rt2800_rfcsr_write(rt2x00dev, 62, 0x1D);
2370                         else if (rf->channel >= 118)
2371                                 rt2800_rfcsr_write(rt2x00dev, 62, 0x15);
2372                 }
2373
2374                 power_bound = POWER_BOUND_5G;
2375                 ep_reg = 0x3;
2376         }
2377
2378         rt2800_rfcsr_read(rt2x00dev, 49, &rfcsr);
2379         if (info->default_power1 > power_bound)
2380                 rt2x00_set_field8(&rfcsr, RFCSR49_TX, power_bound);
2381         else
2382                 rt2x00_set_field8(&rfcsr, RFCSR49_TX, info->default_power1);
2383         if (is_type_ep)
2384                 rt2x00_set_field8(&rfcsr, RFCSR49_EP, ep_reg);
2385         rt2800_rfcsr_write(rt2x00dev, 49, rfcsr);
2386
2387         rt2800_rfcsr_read(rt2x00dev, 50, &rfcsr);
2388         if (info->default_power1 > power_bound)
2389                 rt2x00_set_field8(&rfcsr, RFCSR50_TX, power_bound);
2390         else
2391                 rt2x00_set_field8(&rfcsr, RFCSR50_TX, info->default_power2);
2392         if (is_type_ep)
2393                 rt2x00_set_field8(&rfcsr, RFCSR50_EP, ep_reg);
2394         rt2800_rfcsr_write(rt2x00dev, 50, rfcsr);
2395
2396         rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
2397         rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
2398         rt2x00_set_field8(&rfcsr, RFCSR1_PLL_PD, 1);
2399
2400         rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD,
2401                           rt2x00dev->default_ant.tx_chain_num >= 1);
2402         rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD,
2403                           rt2x00dev->default_ant.tx_chain_num == 2);
2404         rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 0);
2405
2406         rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD,
2407                           rt2x00dev->default_ant.rx_chain_num >= 1);
2408         rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD,
2409                           rt2x00dev->default_ant.rx_chain_num == 2);
2410         rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 0);
2411
2412         rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
2413         rt2800_rfcsr_write(rt2x00dev, 6, 0xe4);
2414
2415         if (conf_is_ht40(conf))
2416                 rt2800_rfcsr_write(rt2x00dev, 30, 0x16);
2417         else
2418                 rt2800_rfcsr_write(rt2x00dev, 30, 0x10);
2419
2420         if (!is_11b) {
2421                 rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
2422                 rt2800_rfcsr_write(rt2x00dev, 32, 0x80);
2423         }
2424
2425         /* TODO proper frequency adjustment */
2426         rt2800_rfcsr_read(rt2x00dev, 17, &rfcsr);
2427         if (rt2x00dev->freq_offset > FREQ_OFFSET_BOUND)
2428                 rt2x00_set_field8(&rfcsr, RFCSR17_CODE, FREQ_OFFSET_BOUND);
2429         else
2430                 rt2x00_set_field8(&rfcsr, RFCSR17_CODE, rt2x00dev->freq_offset);
2431         rt2800_rfcsr_write(rt2x00dev, 17, rfcsr);
2432
2433         /* TODO merge with others */
2434         rt2800_rfcsr_read(rt2x00dev, 3, &rfcsr);
2435         rt2x00_set_field8(&rfcsr, RFCSR3_VCOCAL_EN, 1);
2436         rt2800_rfcsr_write(rt2x00dev, 3, rfcsr);
2437 }
2438
2439 static void rt2800_config_channel(struct rt2x00_dev *rt2x00dev,
2440                                   struct ieee80211_conf *conf,
2441                                   struct rf_channel *rf,
2442                                   struct channel_info *info)
2443 {
2444         u32 reg;
2445         unsigned int tx_pin;
2446         u8 bbp, rfcsr;
2447
2448         if (rf->channel <= 14) {
2449                 info->default_power1 = TXPOWER_G_TO_DEV(info->default_power1);
2450                 info->default_power2 = TXPOWER_G_TO_DEV(info->default_power2);
2451         } else {
2452                 info->default_power1 = TXPOWER_A_TO_DEV(info->default_power1);
2453                 info->default_power2 = TXPOWER_A_TO_DEV(info->default_power2);
2454         }
2455
2456         switch (rt2x00dev->chip.rf) {
2457         case RF2020:
2458         case RF3020:
2459         case RF3021:
2460         case RF3022:
2461         case RF3320:
2462                 rt2800_config_channel_rf3xxx(rt2x00dev, conf, rf, info);
2463                 break;
2464         case RF3052:
2465                 rt2800_config_channel_rf3052(rt2x00dev, conf, rf, info);
2466                 break;
2467         case RF3290:
2468                 rt2800_config_channel_rf3290(rt2x00dev, conf, rf, info);
2469                 break;
2470         case RF3322:
2471                 rt2800_config_channel_rf3322(rt2x00dev, conf, rf, info);
2472                 break;
2473         case RF5360:
2474         case RF5370:
2475         case RF5372:
2476         case RF5390:
2477         case RF5392:
2478                 rt2800_config_channel_rf53xx(rt2x00dev, conf, rf, info);
2479                 break;
2480         case RF5592:
2481                 rt2800_config_channel_rf55xx(rt2x00dev, conf, rf, info);
2482                 break;
2483         default:
2484                 rt2800_config_channel_rf2xxx(rt2x00dev, conf, rf, info);
2485         }
2486
2487         if (rt2x00_rf(rt2x00dev, RF3290) ||
2488             rt2x00_rf(rt2x00dev, RF3322) ||
2489             rt2x00_rf(rt2x00dev, RF5360) ||
2490             rt2x00_rf(rt2x00dev, RF5370) ||
2491             rt2x00_rf(rt2x00dev, RF5372) ||
2492             rt2x00_rf(rt2x00dev, RF5390) ||
2493             rt2x00_rf(rt2x00dev, RF5392)) {
2494                 rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
2495                 rt2x00_set_field8(&rfcsr, RFCSR30_TX_H20M, 0);
2496                 rt2x00_set_field8(&rfcsr, RFCSR30_RX_H20M, 0);
2497                 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
2498
2499                 rt2800_rfcsr_read(rt2x00dev, 3, &rfcsr);
2500                 rt2x00_set_field8(&rfcsr, RFCSR3_VCOCAL_EN, 1);
2501                 rt2800_rfcsr_write(rt2x00dev, 3, rfcsr);
2502         }
2503
2504         /*
2505          * Change BBP settings
2506          */
2507         if (rt2x00_rt(rt2x00dev, RT3352)) {
2508                 rt2800_bbp_write(rt2x00dev, 27, 0x0);
2509                 rt2800_bbp_write(rt2x00dev, 66, 0x26 + rt2x00dev->lna_gain);
2510                 rt2800_bbp_write(rt2x00dev, 27, 0x20);
2511                 rt2800_bbp_write(rt2x00dev, 66, 0x26 + rt2x00dev->lna_gain);
2512         } else {
2513                 rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain);
2514                 rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain);
2515                 rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain);
2516                 rt2800_bbp_write(rt2x00dev, 86, 0);
2517         }
2518
2519         if (rf->channel <= 14) {
2520                 if (!rt2x00_rt(rt2x00dev, RT5390) &&
2521                     !rt2x00_rt(rt2x00dev, RT5392)) {
2522                         if (test_bit(CAPABILITY_EXTERNAL_LNA_BG,
2523                                      &rt2x00dev->cap_flags)) {
2524                                 rt2800_bbp_write(rt2x00dev, 82, 0x62);
2525                                 rt2800_bbp_write(rt2x00dev, 75, 0x46);
2526                         } else {
2527                                 rt2800_bbp_write(rt2x00dev, 82, 0x84);
2528                                 rt2800_bbp_write(rt2x00dev, 75, 0x50);
2529                         }
2530                 }
2531         } else {
2532                 if (rt2x00_rt(rt2x00dev, RT3572))
2533                         rt2800_bbp_write(rt2x00dev, 82, 0x94);
2534                 else
2535                         rt2800_bbp_write(rt2x00dev, 82, 0xf2);
2536
2537                 if (test_bit(CAPABILITY_EXTERNAL_LNA_A, &rt2x00dev->cap_flags))
2538                         rt2800_bbp_write(rt2x00dev, 75, 0x46);
2539                 else
2540                         rt2800_bbp_write(rt2x00dev, 75, 0x50);
2541         }
2542
2543         rt2800_register_read(rt2x00dev, TX_BAND_CFG, &reg);
2544         rt2x00_set_field32(&reg, TX_BAND_CFG_HT40_MINUS, conf_is_ht40_minus(conf));
2545         rt2x00_set_field32(&reg, TX_BAND_CFG_A, rf->channel > 14);
2546         rt2x00_set_field32(&reg, TX_BAND_CFG_BG, rf->channel <= 14);
2547         rt2800_register_write(rt2x00dev, TX_BAND_CFG, reg);
2548
2549         if (rt2x00_rt(rt2x00dev, RT3572))
2550                 rt2800_rfcsr_write(rt2x00dev, 8, 0);
2551
2552         tx_pin = 0;
2553
2554         /* Turn on unused PA or LNA when not using 1T or 1R */
2555         if (rt2x00dev->default_ant.tx_chain_num == 2) {
2556                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A1_EN,
2557                                    rf->channel > 14);
2558                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G1_EN,
2559                                    rf->channel <= 14);
2560         }
2561
2562         /* Turn on unused PA or LNA when not using 1T or 1R */
2563         if (rt2x00dev->default_ant.rx_chain_num == 2) {
2564                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A1_EN, 1);
2565                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G1_EN, 1);
2566         }
2567
2568         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A0_EN, 1);
2569         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G0_EN, 1);
2570         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_RFTR_EN, 1);
2571         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_TRSW_EN, 1);
2572         if (test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags))
2573                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN, 1);
2574         else
2575                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN,
2576                                    rf->channel <= 14);
2577         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A0_EN, rf->channel > 14);
2578
2579         rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin);
2580
2581         if (rt2x00_rt(rt2x00dev, RT3572))
2582                 rt2800_rfcsr_write(rt2x00dev, 8, 0x80);
2583
2584         rt2800_bbp_read(rt2x00dev, 4, &bbp);
2585         rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * conf_is_ht40(conf));
2586         rt2800_bbp_write(rt2x00dev, 4, bbp);
2587
2588         rt2800_bbp_read(rt2x00dev, 3, &bbp);
2589         rt2x00_set_field8(&bbp, BBP3_HT40_MINUS, conf_is_ht40_minus(conf));
2590         rt2800_bbp_write(rt2x00dev, 3, bbp);
2591
2592         if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C)) {
2593                 if (conf_is_ht40(conf)) {
2594                         rt2800_bbp_write(rt2x00dev, 69, 0x1a);
2595                         rt2800_bbp_write(rt2x00dev, 70, 0x0a);
2596                         rt2800_bbp_write(rt2x00dev, 73, 0x16);
2597                 } else {
2598                         rt2800_bbp_write(rt2x00dev, 69, 0x16);
2599                         rt2800_bbp_write(rt2x00dev, 70, 0x08);
2600                         rt2800_bbp_write(rt2x00dev, 73, 0x11);
2601                 }
2602         }
2603
2604         msleep(1);
2605
2606         /*
2607          * Clear channel statistic counters
2608          */
2609         rt2800_register_read(rt2x00dev, CH_IDLE_STA, &reg);
2610         rt2800_register_read(rt2x00dev, CH_BUSY_STA, &reg);
2611         rt2800_register_read(rt2x00dev, CH_BUSY_STA_SEC, &reg);
2612
2613         /*
2614          * Clear update flag
2615          */
2616         if (rt2x00_rt(rt2x00dev, RT3352)) {
2617                 rt2800_bbp_read(rt2x00dev, 49, &bbp);
2618                 rt2x00_set_field8(&bbp, BBP49_UPDATE_FLAG, 0);
2619                 rt2800_bbp_write(rt2x00dev, 49, bbp);
2620         }
2621 }
2622
2623 static int rt2800_get_gain_calibration_delta(struct rt2x00_dev *rt2x00dev)
2624 {
2625         u8 tssi_bounds[9];
2626         u8 current_tssi;
2627         u16 eeprom;
2628         u8 step;
2629         int i;
2630
2631         /*
2632          * Read TSSI boundaries for temperature compensation from
2633          * the EEPROM.
2634          *
2635          * Array idx               0    1    2    3    4    5    6    7    8
2636          * Matching Delta value   -4   -3   -2   -1    0   +1   +2   +3   +4
2637          * Example TSSI bounds  0xF0 0xD0 0xB5 0xA0 0x88 0x45 0x25 0x15 0x00
2638          */
2639         if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ) {
2640                 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG1, &eeprom);
2641                 tssi_bounds[0] = rt2x00_get_field16(eeprom,
2642                                         EEPROM_TSSI_BOUND_BG1_MINUS4);
2643                 tssi_bounds[1] = rt2x00_get_field16(eeprom,
2644                                         EEPROM_TSSI_BOUND_BG1_MINUS3);
2645
2646                 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG2, &eeprom);
2647                 tssi_bounds[2] = rt2x00_get_field16(eeprom,
2648                                         EEPROM_TSSI_BOUND_BG2_MINUS2);
2649                 tssi_bounds[3] = rt2x00_get_field16(eeprom,
2650                                         EEPROM_TSSI_BOUND_BG2_MINUS1);
2651
2652                 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG3, &eeprom);
2653                 tssi_bounds[4] = rt2x00_get_field16(eeprom,
2654                                         EEPROM_TSSI_BOUND_BG3_REF);
2655                 tssi_bounds[5] = rt2x00_get_field16(eeprom,
2656                                         EEPROM_TSSI_BOUND_BG3_PLUS1);
2657
2658                 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG4, &eeprom);
2659                 tssi_bounds[6] = rt2x00_get_field16(eeprom,
2660                                         EEPROM_TSSI_BOUND_BG4_PLUS2);
2661                 tssi_bounds[7] = rt2x00_get_field16(eeprom,
2662                                         EEPROM_TSSI_BOUND_BG4_PLUS3);
2663
2664                 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG5, &eeprom);
2665                 tssi_bounds[8] = rt2x00_get_field16(eeprom,
2666                                         EEPROM_TSSI_BOUND_BG5_PLUS4);
2667
2668                 step = rt2x00_get_field16(eeprom,
2669                                           EEPROM_TSSI_BOUND_BG5_AGC_STEP);
2670         } else {
2671                 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A1, &eeprom);
2672                 tssi_bounds[0] = rt2x00_get_field16(eeprom,
2673                                         EEPROM_TSSI_BOUND_A1_MINUS4);
2674                 tssi_bounds[1] = rt2x00_get_field16(eeprom,
2675                                         EEPROM_TSSI_BOUND_A1_MINUS3);
2676
2677                 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A2, &eeprom);
2678                 tssi_bounds[2] = rt2x00_get_field16(eeprom,
2679                                         EEPROM_TSSI_BOUND_A2_MINUS2);
2680                 tssi_bounds[3] = rt2x00_get_field16(eeprom,
2681                                         EEPROM_TSSI_BOUND_A2_MINUS1);
2682
2683                 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A3, &eeprom);
2684                 tssi_bounds[4] = rt2x00_get_field16(eeprom,
2685                                         EEPROM_TSSI_BOUND_A3_REF);
2686                 tssi_bounds[5] = rt2x00_get_field16(eeprom,
2687                                         EEPROM_TSSI_BOUND_A3_PLUS1);
2688
2689                 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A4, &eeprom);
2690                 tssi_bounds[6] = rt2x00_get_field16(eeprom,
2691                                         EEPROM_TSSI_BOUND_A4_PLUS2);
2692                 tssi_bounds[7] = rt2x00_get_field16(eeprom,
2693                                         EEPROM_TSSI_BOUND_A4_PLUS3);
2694
2695                 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A5, &eeprom);
2696                 tssi_bounds[8] = rt2x00_get_field16(eeprom,
2697                                         EEPROM_TSSI_BOUND_A5_PLUS4);
2698
2699                 step = rt2x00_get_field16(eeprom,
2700                                           EEPROM_TSSI_BOUND_A5_AGC_STEP);
2701         }
2702
2703         /*
2704          * Check if temperature compensation is supported.
2705          */
2706         if (tssi_bounds[4] == 0xff || step == 0xff)
2707                 return 0;
2708
2709         /*
2710          * Read current TSSI (BBP 49).
2711          */
2712         rt2800_bbp_read(rt2x00dev, 49, &current_tssi);
2713
2714         /*
2715          * Compare TSSI value (BBP49) with the compensation boundaries
2716          * from the EEPROM and increase or decrease tx power.
2717          */
2718         for (i = 0; i <= 3; i++) {
2719                 if (current_tssi > tssi_bounds[i])
2720                         break;
2721         }
2722
2723         if (i == 4) {
2724                 for (i = 8; i >= 5; i--) {
2725                         if (current_tssi < tssi_bounds[i])
2726                                 break;
2727                 }
2728         }
2729
2730         return (i - 4) * step;
2731 }
2732
2733 static int rt2800_get_txpower_bw_comp(struct rt2x00_dev *rt2x00dev,
2734                                       enum ieee80211_band band)
2735 {
2736         u16 eeprom;
2737         u8 comp_en;
2738         u8 comp_type;
2739         int comp_value = 0;
2740
2741         rt2x00_eeprom_read(rt2x00dev, EEPROM_TXPOWER_DELTA, &eeprom);
2742
2743         /*
2744          * HT40 compensation not required.
2745          */
2746         if (eeprom == 0xffff ||
2747             !test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags))
2748                 return 0;
2749
2750         if (band == IEEE80211_BAND_2GHZ) {
2751                 comp_en = rt2x00_get_field16(eeprom,
2752                                  EEPROM_TXPOWER_DELTA_ENABLE_2G);
2753                 if (comp_en) {
2754                         comp_type = rt2x00_get_field16(eeprom,
2755                                            EEPROM_TXPOWER_DELTA_TYPE_2G);
2756                         comp_value = rt2x00_get_field16(eeprom,
2757                                             EEPROM_TXPOWER_DELTA_VALUE_2G);
2758                         if (!comp_type)
2759                                 comp_value = -comp_value;
2760                 }
2761         } else {
2762                 comp_en = rt2x00_get_field16(eeprom,
2763                                  EEPROM_TXPOWER_DELTA_ENABLE_5G);
2764                 if (comp_en) {
2765                         comp_type = rt2x00_get_field16(eeprom,
2766                                            EEPROM_TXPOWER_DELTA_TYPE_5G);
2767                         comp_value = rt2x00_get_field16(eeprom,
2768                                             EEPROM_TXPOWER_DELTA_VALUE_5G);
2769                         if (!comp_type)
2770                                 comp_value = -comp_value;
2771                 }
2772         }
2773
2774         return comp_value;
2775 }
2776
2777 static int rt2800_get_txpower_reg_delta(struct rt2x00_dev *rt2x00dev,
2778                                         int power_level, int max_power)
2779 {
2780         int delta;
2781
2782         if (test_bit(CAPABILITY_POWER_LIMIT, &rt2x00dev->cap_flags))
2783                 return 0;
2784
2785         /*
2786          * XXX: We don't know the maximum transmit power of our hardware since
2787          * the EEPROM doesn't expose it. We only know that we are calibrated
2788          * to 100% tx power.
2789          *
2790          * Hence, we assume the regulatory limit that cfg80211 calulated for
2791          * the current channel is our maximum and if we are requested to lower
2792          * the value we just reduce our tx power accordingly.
2793          */
2794         delta = power_level - max_power;
2795         return min(delta, 0);
2796 }
2797
2798 static u8 rt2800_compensate_txpower(struct rt2x00_dev *rt2x00dev, int is_rate_b,
2799                                    enum ieee80211_band band, int power_level,
2800                                    u8 txpower, int delta)
2801 {
2802         u16 eeprom;
2803         u8 criterion;
2804         u8 eirp_txpower;
2805         u8 eirp_txpower_criterion;
2806         u8 reg_limit;
2807
2808         if (test_bit(CAPABILITY_POWER_LIMIT, &rt2x00dev->cap_flags)) {
2809                 /*
2810                  * Check if eirp txpower exceed txpower_limit.
2811                  * We use OFDM 6M as criterion and its eirp txpower
2812                  * is stored at EEPROM_EIRP_MAX_TX_POWER.
2813                  * .11b data rate need add additional 4dbm
2814                  * when calculating eirp txpower.
2815                  */
2816                 rt2x00_eeprom_read(rt2x00dev, EEPROM_TXPOWER_BYRATE + 1,
2817                                    &eeprom);
2818                 criterion = rt2x00_get_field16(eeprom,
2819                                                EEPROM_TXPOWER_BYRATE_RATE0);
2820
2821                 rt2x00_eeprom_read(rt2x00dev, EEPROM_EIRP_MAX_TX_POWER,
2822                                    &eeprom);
2823
2824                 if (band == IEEE80211_BAND_2GHZ)
2825                         eirp_txpower_criterion = rt2x00_get_field16(eeprom,
2826                                                  EEPROM_EIRP_MAX_TX_POWER_2GHZ);
2827                 else
2828                         eirp_txpower_criterion = rt2x00_get_field16(eeprom,
2829                                                  EEPROM_EIRP_MAX_TX_POWER_5GHZ);
2830
2831                 eirp_txpower = eirp_txpower_criterion + (txpower - criterion) +
2832                                (is_rate_b ? 4 : 0) + delta;
2833
2834                 reg_limit = (eirp_txpower > power_level) ?
2835                                         (eirp_txpower - power_level) : 0;
2836         } else
2837                 reg_limit = 0;
2838
2839         txpower = max(0, txpower + delta - reg_limit);
2840         return min_t(u8, txpower, 0xc);
2841 }
2842
2843 /*
2844  * We configure transmit power using MAC TX_PWR_CFG_{0,...,N} registers and
2845  * BBP R1 register. TX_PWR_CFG_X allow to configure per rate TX power values,
2846  * 4 bits for each rate (tune from 0 to 15 dBm). BBP_R1 controls transmit power
2847  * for all rates, but allow to set only 4 discrete values: -12, -6, 0 and 6 dBm.
2848  * Reference per rate transmit power values are located in the EEPROM at
2849  * EEPROM_TXPOWER_BYRATE offset. We adjust them and BBP R1 settings according to
2850  * current conditions (i.e. band, bandwidth, temperature, user settings).
2851  */
2852 static void rt2800_config_txpower(struct rt2x00_dev *rt2x00dev,
2853                                   struct ieee80211_channel *chan,
2854                                   int power_level)
2855 {
2856         u8 txpower, r1;
2857         u16 eeprom;
2858         u32 reg, offset;
2859         int i, is_rate_b, delta, power_ctrl;
2860         enum ieee80211_band band = chan->band;
2861
2862         /*
2863          * Calculate HT40 compensation. For 40MHz we need to add or subtract
2864          * value read from EEPROM (different for 2GHz and for 5GHz).
2865          */
2866         delta = rt2800_get_txpower_bw_comp(rt2x00dev, band);
2867
2868         /*
2869          * Calculate temperature compensation. Depends on measurement of current
2870          * TSSI (Transmitter Signal Strength Indication) we know TX power (due
2871          * to temperature or maybe other factors) is smaller or bigger than
2872          * expected. We adjust it, based on TSSI reference and boundaries values
2873          * provided in EEPROM.
2874          */
2875         delta += rt2800_get_gain_calibration_delta(rt2x00dev);
2876
2877         /*
2878          * Decrease power according to user settings, on devices with unknown
2879          * maximum tx power. For other devices we take user power_level into
2880          * consideration on rt2800_compensate_txpower().
2881          */
2882         delta += rt2800_get_txpower_reg_delta(rt2x00dev, power_level,
2883                                               chan->max_power);
2884
2885         /*
2886          * BBP_R1 controls TX power for all rates, it allow to set the following
2887          * gains -12, -6, 0, +6 dBm by setting values 2, 1, 0, 3 respectively.
2888          *
2889          * TODO: we do not use +6 dBm option to do not increase power beyond
2890          * regulatory limit, however this could be utilized for devices with
2891          * CAPABILITY_POWER_LIMIT.
2892          */
2893         rt2800_bbp_read(rt2x00dev, 1, &r1);
2894         if (delta <= -12) {
2895                 power_ctrl = 2;
2896                 delta += 12;
2897         } else if (delta <= -6) {
2898                 power_ctrl = 1;
2899                 delta += 6;
2900         } else {
2901                 power_ctrl = 0;
2902         }
2903         rt2x00_set_field8(&r1, BBP1_TX_POWER_CTRL, power_ctrl);
2904         rt2800_bbp_write(rt2x00dev, 1, r1);
2905         offset = TX_PWR_CFG_0;
2906
2907         for (i = 0; i < EEPROM_TXPOWER_BYRATE_SIZE; i += 2) {
2908                 /* just to be safe */
2909                 if (offset > TX_PWR_CFG_4)
2910                         break;
2911
2912                 rt2800_register_read(rt2x00dev, offset, &reg);
2913
2914                 /* read the next four txpower values */
2915                 rt2x00_eeprom_read(rt2x00dev, EEPROM_TXPOWER_BYRATE + i,
2916                                    &eeprom);
2917
2918                 is_rate_b = i ? 0 : 1;
2919                 /*
2920                  * TX_PWR_CFG_0: 1MBS, TX_PWR_CFG_1: 24MBS,
2921                  * TX_PWR_CFG_2: MCS4, TX_PWR_CFG_3: MCS12,
2922                  * TX_PWR_CFG_4: unknown
2923                  */
2924                 txpower = rt2x00_get_field16(eeprom,
2925                                              EEPROM_TXPOWER_BYRATE_RATE0);
2926                 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
2927                                              power_level, txpower, delta);
2928                 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE0, txpower);
2929
2930                 /*
2931                  * TX_PWR_CFG_0: 2MBS, TX_PWR_CFG_1: 36MBS,
2932                  * TX_PWR_CFG_2: MCS5, TX_PWR_CFG_3: MCS13,
2933                  * TX_PWR_CFG_4: unknown
2934                  */
2935                 txpower = rt2x00_get_field16(eeprom,
2936                                              EEPROM_TXPOWER_BYRATE_RATE1);
2937                 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
2938                                              power_level, txpower, delta);
2939                 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE1, txpower);
2940
2941                 /*
2942                  * TX_PWR_CFG_0: 5.5MBS, TX_PWR_CFG_1: 48MBS,
2943                  * TX_PWR_CFG_2: MCS6,  TX_PWR_CFG_3: MCS14,
2944                  * TX_PWR_CFG_4: unknown
2945                  */
2946                 txpower = rt2x00_get_field16(eeprom,
2947                                              EEPROM_TXPOWER_BYRATE_RATE2);
2948                 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
2949                                              power_level, txpower, delta);
2950                 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE2, txpower);
2951
2952                 /*
2953                  * TX_PWR_CFG_0: 11MBS, TX_PWR_CFG_1: 54MBS,
2954                  * TX_PWR_CFG_2: MCS7,  TX_PWR_CFG_3: MCS15,
2955                  * TX_PWR_CFG_4: unknown
2956                  */
2957                 txpower = rt2x00_get_field16(eeprom,
2958                                              EEPROM_TXPOWER_BYRATE_RATE3);
2959                 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
2960                                              power_level, txpower, delta);
2961                 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE3, txpower);
2962
2963                 /* read the next four txpower values */
2964                 rt2x00_eeprom_read(rt2x00dev, EEPROM_TXPOWER_BYRATE + i + 1,
2965                                    &eeprom);
2966
2967                 is_rate_b = 0;
2968                 /*
2969                  * TX_PWR_CFG_0: 6MBS, TX_PWR_CFG_1: MCS0,
2970                  * TX_PWR_CFG_2: MCS8, TX_PWR_CFG_3: unknown,
2971                  * TX_PWR_CFG_4: unknown
2972                  */
2973                 txpower = rt2x00_get_field16(eeprom,
2974                                              EEPROM_TXPOWER_BYRATE_RATE0);
2975                 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
2976                                              power_level, txpower, delta);
2977                 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE4, txpower);
2978
2979                 /*
2980                  * TX_PWR_CFG_0: 9MBS, TX_PWR_CFG_1: MCS1,
2981                  * TX_PWR_CFG_2: MCS9, TX_PWR_CFG_3: unknown,
2982                  * TX_PWR_CFG_4: unknown
2983                  */
2984                 txpower = rt2x00_get_field16(eeprom,
2985                                              EEPROM_TXPOWER_BYRATE_RATE1);
2986                 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
2987                                              power_level, txpower, delta);
2988                 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE5, txpower);
2989
2990                 /*
2991                  * TX_PWR_CFG_0: 12MBS, TX_PWR_CFG_1: MCS2,
2992                  * TX_PWR_CFG_2: MCS10, TX_PWR_CFG_3: unknown,
2993                  * TX_PWR_CFG_4: unknown
2994                  */
2995                 txpower = rt2x00_get_field16(eeprom,
2996                                              EEPROM_TXPOWER_BYRATE_RATE2);
2997                 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
2998                                              power_level, txpower, delta);
2999                 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE6, txpower);
3000
3001                 /*
3002                  * TX_PWR_CFG_0: 18MBS, TX_PWR_CFG_1: MCS3,
3003                  * TX_PWR_CFG_2: MCS11, TX_PWR_CFG_3: unknown,
3004                  * TX_PWR_CFG_4: unknown
3005                  */
3006                 txpower = rt2x00_get_field16(eeprom,
3007                                              EEPROM_TXPOWER_BYRATE_RATE3);
3008                 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
3009                                              power_level, txpower, delta);
3010                 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE7, txpower);
3011
3012                 rt2800_register_write(rt2x00dev, offset, reg);
3013
3014                 /* next TX_PWR_CFG register */
3015                 offset += 4;
3016         }
3017 }
3018
3019 void rt2800_gain_calibration(struct rt2x00_dev *rt2x00dev)
3020 {
3021         rt2800_config_txpower(rt2x00dev, rt2x00dev->hw->conf.channel,
3022                               rt2x00dev->tx_power);
3023 }
3024 EXPORT_SYMBOL_GPL(rt2800_gain_calibration);
3025
3026 void rt2800_vco_calibration(struct rt2x00_dev *rt2x00dev)
3027 {
3028         u32     tx_pin;
3029         u8      rfcsr;
3030
3031         /*
3032          * A voltage-controlled oscillator(VCO) is an electronic oscillator
3033          * designed to be controlled in oscillation frequency by a voltage
3034          * input. Maybe the temperature will affect the frequency of
3035          * oscillation to be shifted. The VCO calibration will be called
3036          * periodically to adjust the frequency to be precision.
3037         */
3038
3039         rt2800_register_read(rt2x00dev, TX_PIN_CFG, &tx_pin);
3040         tx_pin &= TX_PIN_CFG_PA_PE_DISABLE;
3041         rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin);
3042
3043         switch (rt2x00dev->chip.rf) {
3044         case RF2020:
3045         case RF3020:
3046         case RF3021:
3047         case RF3022:
3048         case RF3320:
3049         case RF3052:
3050                 rt2800_rfcsr_read(rt2x00dev, 7, &rfcsr);
3051                 rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1);
3052                 rt2800_rfcsr_write(rt2x00dev, 7, rfcsr);
3053                 break;
3054         case RF3290:
3055         case RF5360:
3056         case RF5370:
3057         case RF5372:
3058         case RF5390:
3059         case RF5392:
3060                 rt2800_rfcsr_read(rt2x00dev, 3, &rfcsr);
3061                 rt2x00_set_field8(&rfcsr, RFCSR3_VCOCAL_EN, 1);
3062                 rt2800_rfcsr_write(rt2x00dev, 3, rfcsr);
3063                 break;
3064         default:
3065                 return;
3066         }
3067
3068         mdelay(1);
3069
3070         rt2800_register_read(rt2x00dev, TX_PIN_CFG, &tx_pin);
3071         if (rt2x00dev->rf_channel <= 14) {
3072                 switch (rt2x00dev->default_ant.tx_chain_num) {
3073                 case 3:
3074                         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G2_EN, 1);
3075                         /* fall through */
3076                 case 2:
3077                         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G1_EN, 1);
3078                         /* fall through */
3079                 case 1:
3080                 default:
3081                         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN, 1);
3082                         break;
3083                 }
3084         } else {
3085                 switch (rt2x00dev->default_ant.tx_chain_num) {
3086                 case 3:
3087                         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A2_EN, 1);
3088                         /* fall through */
3089                 case 2:
3090                         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A1_EN, 1);
3091                         /* fall through */
3092                 case 1:
3093                 default:
3094                         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A0_EN, 1);
3095                         break;
3096                 }
3097         }
3098         rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin);
3099
3100 }
3101 EXPORT_SYMBOL_GPL(rt2800_vco_calibration);
3102
3103 static void rt2800_config_retry_limit(struct rt2x00_dev *rt2x00dev,
3104                                       struct rt2x00lib_conf *libconf)
3105 {
3106         u32 reg;
3107
3108         rt2800_register_read(rt2x00dev, TX_RTY_CFG, &reg);
3109         rt2x00_set_field32(&reg, TX_RTY_CFG_SHORT_RTY_LIMIT,
3110                            libconf->conf->short_frame_max_tx_count);
3111         rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_LIMIT,
3112                            libconf->conf->long_frame_max_tx_count);
3113         rt2800_register_write(rt2x00dev, TX_RTY_CFG, reg);
3114 }
3115
3116 static void rt2800_config_ps(struct rt2x00_dev *rt2x00dev,
3117                              struct rt2x00lib_conf *libconf)
3118 {
3119         enum dev_state state =
3120             (libconf->conf->flags & IEEE80211_CONF_PS) ?
3121                 STATE_SLEEP : STATE_AWAKE;
3122         u32 reg;
3123
3124         if (state == STATE_SLEEP) {
3125                 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0);
3126
3127                 rt2800_register_read(rt2x00dev, AUTOWAKEUP_CFG, &reg);
3128                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 5);
3129                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE,
3130                                    libconf->conf->listen_interval - 1);
3131                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTOWAKE, 1);
3132                 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg);
3133
3134                 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
3135         } else {
3136                 rt2800_register_read(rt2x00dev, AUTOWAKEUP_CFG, &reg);
3137                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 0);
3138                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE, 0);
3139                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTOWAKE, 0);
3140                 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg);
3141
3142                 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
3143         }
3144 }
3145
3146 void rt2800_config(struct rt2x00_dev *rt2x00dev,
3147                    struct rt2x00lib_conf *libconf,
3148                    const unsigned int flags)
3149 {
3150         /* Always recalculate LNA gain before changing configuration */
3151         rt2800_config_lna_gain(rt2x00dev, libconf);
3152
3153         if (flags & IEEE80211_CONF_CHANGE_CHANNEL) {
3154                 rt2800_config_channel(rt2x00dev, libconf->conf,
3155                                       &libconf->rf, &libconf->channel);
3156                 rt2800_config_txpower(rt2x00dev, libconf->conf->channel,
3157                                       libconf->conf->power_level);
3158         }
3159         if (flags & IEEE80211_CONF_CHANGE_POWER)
3160                 rt2800_config_txpower(rt2x00dev, libconf->conf->channel,
3161                                       libconf->conf->power_level);
3162         if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
3163                 rt2800_config_retry_limit(rt2x00dev, libconf);
3164         if (flags & IEEE80211_CONF_CHANGE_PS)
3165                 rt2800_config_ps(rt2x00dev, libconf);
3166 }
3167 EXPORT_SYMBOL_GPL(rt2800_config);
3168
3169 /*
3170  * Link tuning
3171  */
3172 void rt2800_link_stats(struct rt2x00_dev *rt2x00dev, struct link_qual *qual)
3173 {
3174         u32 reg;
3175
3176         /*
3177          * Update FCS error count from register.
3178          */
3179         rt2800_register_read(rt2x00dev, RX_STA_CNT0, &reg);
3180         qual->rx_failed = rt2x00_get_field32(reg, RX_STA_CNT0_CRC_ERR);
3181 }
3182 EXPORT_SYMBOL_GPL(rt2800_link_stats);
3183
3184 static u8 rt2800_get_default_vgc(struct rt2x00_dev *rt2x00dev)
3185 {
3186         u8 vgc;
3187
3188         if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ) {
3189                 if (rt2x00_rt(rt2x00dev, RT3070) ||
3190                     rt2x00_rt(rt2x00dev, RT3071) ||
3191                     rt2x00_rt(rt2x00dev, RT3090) ||
3192                     rt2x00_rt(rt2x00dev, RT3290) ||
3193                     rt2x00_rt(rt2x00dev, RT3390) ||
3194                     rt2x00_rt(rt2x00dev, RT3572) ||
3195                     rt2x00_rt(rt2x00dev, RT5390) ||
3196                     rt2x00_rt(rt2x00dev, RT5392))
3197                         vgc = 0x1c + (2 * rt2x00dev->lna_gain);
3198                 else
3199                         vgc = 0x2e + rt2x00dev->lna_gain;
3200         } else { /* 5GHZ band */
3201                 if (rt2x00_rt(rt2x00dev, RT3572))
3202                         vgc = 0x22 + (rt2x00dev->lna_gain * 5) / 3;
3203                 else {
3204                         if (!test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags))
3205                                 vgc = 0x32 + (rt2x00dev->lna_gain * 5) / 3;
3206                         else
3207                                 vgc = 0x3a + (rt2x00dev->lna_gain * 5) / 3;
3208                 }
3209         }
3210
3211         return vgc;
3212 }
3213
3214 static inline void rt2800_set_vgc(struct rt2x00_dev *rt2x00dev,
3215                                   struct link_qual *qual, u8 vgc_level)
3216 {
3217         if (qual->vgc_level != vgc_level) {
3218                 rt2800_bbp_write(rt2x00dev, 66, vgc_level);
3219                 qual->vgc_level = vgc_level;
3220                 qual->vgc_level_reg = vgc_level;
3221         }
3222 }
3223
3224 void rt2800_reset_tuner(struct rt2x00_dev *rt2x00dev, struct link_qual *qual)
3225 {
3226         rt2800_set_vgc(rt2x00dev, qual, rt2800_get_default_vgc(rt2x00dev));
3227 }
3228 EXPORT_SYMBOL_GPL(rt2800_reset_tuner);
3229
3230 void rt2800_link_tuner(struct rt2x00_dev *rt2x00dev, struct link_qual *qual,
3231                        const u32 count)
3232 {
3233         if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C))
3234                 return;
3235
3236         /*
3237          * When RSSI is better then -80 increase VGC level with 0x10
3238          */
3239         rt2800_set_vgc(rt2x00dev, qual,
3240                        rt2800_get_default_vgc(rt2x00dev) +
3241                        ((qual->rssi > -80) * 0x10));
3242 }
3243 EXPORT_SYMBOL_GPL(rt2800_link_tuner);
3244
3245 /*
3246  * Initialization functions.
3247  */
3248 static int rt2800_init_registers(struct rt2x00_dev *rt2x00dev)
3249 {
3250         u32 reg;
3251         u16 eeprom;
3252         unsigned int i;
3253         int ret;
3254
3255         rt2800_disable_wpdma(rt2x00dev);
3256
3257         ret = rt2800_drv_init_registers(rt2x00dev);
3258         if (ret)
3259                 return ret;
3260
3261         rt2800_register_read(rt2x00dev, BCN_OFFSET0, &reg);
3262         rt2x00_set_field32(&reg, BCN_OFFSET0_BCN0, 0xe0); /* 0x3800 */
3263         rt2x00_set_field32(&reg, BCN_OFFSET0_BCN1, 0xe8); /* 0x3a00 */
3264         rt2x00_set_field32(&reg, BCN_OFFSET0_BCN2, 0xf0); /* 0x3c00 */
3265         rt2x00_set_field32(&reg, BCN_OFFSET0_BCN3, 0xf8); /* 0x3e00 */
3266         rt2800_register_write(rt2x00dev, BCN_OFFSET0, reg);
3267
3268         rt2800_register_read(rt2x00dev, BCN_OFFSET1, &reg);
3269         rt2x00_set_field32(&reg, BCN_OFFSET1_BCN4, 0xc8); /* 0x3200 */
3270         rt2x00_set_field32(&reg, BCN_OFFSET1_BCN5, 0xd0); /* 0x3400 */
3271         rt2x00_set_field32(&reg, BCN_OFFSET1_BCN6, 0x77); /* 0x1dc0 */
3272         rt2x00_set_field32(&reg, BCN_OFFSET1_BCN7, 0x6f); /* 0x1bc0 */
3273         rt2800_register_write(rt2x00dev, BCN_OFFSET1, reg);
3274
3275         rt2800_register_write(rt2x00dev, LEGACY_BASIC_RATE, 0x0000013f);
3276         rt2800_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
3277
3278         rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000);
3279
3280         rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
3281         rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL, 1600);
3282         rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 0);
3283         rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, 0);
3284         rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 0);
3285         rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
3286         rt2x00_set_field32(&reg, BCN_TIME_CFG_TX_TIME_COMPENSATE, 0);
3287         rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
3288
3289         rt2800_config_filter(rt2x00dev, FIF_ALLMULTI);
3290
3291         rt2800_register_read(rt2x00dev, BKOFF_SLOT_CFG, &reg);
3292         rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_SLOT_TIME, 9);
3293         rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_CC_DELAY_TIME, 2);
3294         rt2800_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg);
3295
3296         if (rt2x00_rt(rt2x00dev, RT3290)) {
3297                 rt2800_register_read(rt2x00dev, WLAN_FUN_CTRL, &reg);
3298                 if (rt2x00_get_field32(reg, WLAN_EN) == 1) {
3299                         rt2x00_set_field32(&reg, PCIE_APP0_CLK_REQ, 1);
3300                         rt2800_register_write(rt2x00dev, WLAN_FUN_CTRL, reg);
3301                 }
3302
3303                 rt2800_register_read(rt2x00dev, CMB_CTRL, &reg);
3304                 if (!(rt2x00_get_field32(reg, LDO0_EN) == 1)) {
3305                         rt2x00_set_field32(&reg, LDO0_EN, 1);
3306                         rt2x00_set_field32(&reg, LDO_BGSEL, 3);
3307                         rt2800_register_write(rt2x00dev, CMB_CTRL, reg);
3308                 }
3309
3310                 rt2800_register_read(rt2x00dev, OSC_CTRL, &reg);
3311                 rt2x00_set_field32(&reg, OSC_ROSC_EN, 1);
3312                 rt2x00_set_field32(&reg, OSC_CAL_REQ, 1);
3313                 rt2x00_set_field32(&reg, OSC_REF_CYCLE, 0x27);
3314                 rt2800_register_write(rt2x00dev, OSC_CTRL, reg);
3315
3316                 rt2800_register_read(rt2x00dev, COEX_CFG0, &reg);
3317                 rt2x00_set_field32(&reg, COEX_CFG_ANT, 0x5e);
3318                 rt2800_register_write(rt2x00dev, COEX_CFG0, reg);
3319
3320                 rt2800_register_read(rt2x00dev, COEX_CFG2, &reg);
3321                 rt2x00_set_field32(&reg, BT_COEX_CFG1, 0x00);
3322                 rt2x00_set_field32(&reg, BT_COEX_CFG0, 0x17);
3323                 rt2x00_set_field32(&reg, WL_COEX_CFG1, 0x93);
3324                 rt2x00_set_field32(&reg, WL_COEX_CFG0, 0x7f);
3325                 rt2800_register_write(rt2x00dev, COEX_CFG2, reg);
3326
3327                 rt2800_register_read(rt2x00dev, PLL_CTRL, &reg);
3328                 rt2x00_set_field32(&reg, PLL_CONTROL, 1);
3329                 rt2800_register_write(rt2x00dev, PLL_CTRL, reg);
3330         }
3331
3332         if (rt2x00_rt(rt2x00dev, RT3071) ||
3333             rt2x00_rt(rt2x00dev, RT3090) ||
3334             rt2x00_rt(rt2x00dev, RT3290) ||
3335             rt2x00_rt(rt2x00dev, RT3390)) {
3336
3337                 if (rt2x00_rt(rt2x00dev, RT3290))
3338                         rt2800_register_write(rt2x00dev, TX_SW_CFG0,
3339                                               0x00000404);
3340                 else
3341                         rt2800_register_write(rt2x00dev, TX_SW_CFG0,
3342                                               0x00000400);
3343
3344                 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
3345                 if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
3346                     rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) ||
3347                     rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E)) {
3348                         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
3349                         if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_DAC_TEST))
3350                                 rt2800_register_write(rt2x00dev, TX_SW_CFG2,
3351                                                       0x0000002c);
3352                         else
3353                                 rt2800_register_write(rt2x00dev, TX_SW_CFG2,
3354                                                       0x0000000f);
3355                 } else {
3356                         rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
3357                 }
3358         } else if (rt2x00_rt(rt2x00dev, RT3070)) {
3359                 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
3360
3361                 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F)) {
3362                         rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
3363                         rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x0000002c);
3364                 } else {
3365                         rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
3366                         rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
3367                 }
3368         } else if (rt2800_is_305x_soc(rt2x00dev)) {
3369                 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
3370                 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
3371                 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000030);
3372         } else if (rt2x00_rt(rt2x00dev, RT3352)) {
3373                 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000402);
3374                 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
3375                 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
3376         } else if (rt2x00_rt(rt2x00dev, RT3572)) {
3377                 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
3378                 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
3379         } else if (rt2x00_rt(rt2x00dev, RT5390) ||
3380                    rt2x00_rt(rt2x00dev, RT5392) ||
3381                    rt2x00_rt(rt2x00dev, RT5592)) {
3382                 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000404);
3383                 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
3384                 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
3385         } else {
3386                 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000000);
3387                 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
3388         }
3389
3390         rt2800_register_read(rt2x00dev, TX_LINK_CFG, &reg);
3391         rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB_LIFETIME, 32);
3392         rt2x00_set_field32(&reg, TX_LINK_CFG_MFB_ENABLE, 0);
3393         rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_UMFS_ENABLE, 0);
3394         rt2x00_set_field32(&reg, TX_LINK_CFG_TX_MRQ_EN, 0);
3395         rt2x00_set_field32(&reg, TX_LINK_CFG_TX_RDG_EN, 0);
3396         rt2x00_set_field32(&reg, TX_LINK_CFG_TX_CF_ACK_EN, 1);
3397         rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB, 0);
3398         rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFS, 0);
3399         rt2800_register_write(rt2x00dev, TX_LINK_CFG, reg);
3400
3401         rt2800_register_read(rt2x00dev, TX_TIMEOUT_CFG, &reg);
3402         rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_MPDU_LIFETIME, 9);
3403         rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_RX_ACK_TIMEOUT, 32);
3404         rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_TX_OP_TIMEOUT, 10);
3405         rt2800_register_write(rt2x00dev, TX_TIMEOUT_CFG, reg);
3406
3407         rt2800_register_read(rt2x00dev, MAX_LEN_CFG, &reg);
3408         rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_MPDU, AGGREGATION_SIZE);
3409         if (rt2x00_rt_rev_gte(rt2x00dev, RT2872, REV_RT2872E) ||
3410             rt2x00_rt(rt2x00dev, RT2883) ||
3411             rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070E))
3412                 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, 2);
3413         else
3414                 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, 1);
3415         rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_PSDU, 0);
3416         rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_MPDU, 0);
3417         rt2800_register_write(rt2x00dev, MAX_LEN_CFG, reg);
3418
3419         rt2800_register_read(rt2x00dev, LED_CFG, &reg);
3420         rt2x00_set_field32(&reg, LED_CFG_ON_PERIOD, 70);
3421         rt2x00_set_field32(&reg, LED_CFG_OFF_PERIOD, 30);
3422         rt2x00_set_field32(&reg, LED_CFG_SLOW_BLINK_PERIOD, 3);
3423         rt2x00_set_field32(&reg, LED_CFG_R_LED_MODE, 3);
3424         rt2x00_set_field32(&reg, LED_CFG_G_LED_MODE, 3);
3425         rt2x00_set_field32(&reg, LED_CFG_Y_LED_MODE, 3);
3426         rt2x00_set_field32(&reg, LED_CFG_LED_POLAR, 1);
3427         rt2800_register_write(rt2x00dev, LED_CFG, reg);
3428
3429         rt2800_register_write(rt2x00dev, PBF_MAX_PCNT, 0x1f3fbf9f);
3430
3431         rt2800_register_read(rt2x00dev, TX_RTY_CFG, &reg);
3432         rt2x00_set_field32(&reg, TX_RTY_CFG_SHORT_RTY_LIMIT, 15);
3433         rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_LIMIT, 31);
3434         rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_THRE, 2000);
3435         rt2x00_set_field32(&reg, TX_RTY_CFG_NON_AGG_RTY_MODE, 0);
3436         rt2x00_set_field32(&reg, TX_RTY_CFG_AGG_RTY_MODE, 0);
3437         rt2x00_set_field32(&reg, TX_RTY_CFG_TX_AUTO_FB_ENABLE, 1);
3438         rt2800_register_write(rt2x00dev, TX_RTY_CFG, reg);
3439
3440         rt2800_register_read(rt2x00dev, AUTO_RSP_CFG, &reg);
3441         rt2x00_set_field32(&reg, AUTO_RSP_CFG_AUTORESPONDER, 1);
3442         rt2x00_set_field32(&reg, AUTO_RSP_CFG_BAC_ACK_POLICY, 1);
3443         rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MMODE, 0);
3444         rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MREF, 0);
3445         rt2x00_set_field32(&reg, AUTO_RSP_CFG_AR_PREAMBLE, 1);
3446         rt2x00_set_field32(&reg, AUTO_RSP_CFG_DUAL_CTS_EN, 0);
3447         rt2x00_set_field32(&reg, AUTO_RSP_CFG_ACK_CTS_PSM_BIT, 0);
3448         rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
3449
3450         rt2800_register_read(rt2x00dev, CCK_PROT_CFG, &reg);
3451         rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_RATE, 3);
3452         rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_CTRL, 0);
3453         rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_NAV_SHORT, 1);
3454         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_CCK, 1);
3455         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
3456         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM20, 1);
3457         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM40, 0);
3458         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF20, 1);
3459         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF40, 0);
3460         rt2x00_set_field32(&reg, CCK_PROT_CFG_RTS_TH_EN, 1);
3461         rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg);
3462
3463         rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
3464         rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_RATE, 3);
3465         rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL, 0);
3466         rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_NAV_SHORT, 1);
3467         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_CCK, 1);
3468         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
3469         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM20, 1);
3470         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM40, 0);
3471         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF20, 1);
3472         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF40, 0);
3473         rt2x00_set_field32(&reg, OFDM_PROT_CFG_RTS_TH_EN, 1);
3474         rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
3475
3476         rt2800_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
3477         rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_RATE, 0x4004);
3478         rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_CTRL, 0);
3479         rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_NAV_SHORT, 1);
3480         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_CCK, 1);
3481         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
3482         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
3483         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
3484         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
3485         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
3486         rt2x00_set_field32(&reg, MM20_PROT_CFG_RTS_TH_EN, 0);
3487         rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
3488
3489         rt2800_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
3490         rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_RATE, 0x4084);
3491         rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_CTRL, 0);
3492         rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_NAV_SHORT, 1);
3493         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_CCK, 1);
3494         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
3495         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
3496         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
3497         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
3498         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
3499         rt2x00_set_field32(&reg, MM40_PROT_CFG_RTS_TH_EN, 0);
3500         rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
3501
3502         rt2800_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
3503         rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_RATE, 0x4004);
3504         rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_CTRL, 0);
3505         rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_NAV_SHORT, 1);
3506         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_CCK, 1);
3507         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
3508         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
3509         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
3510         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
3511         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
3512         rt2x00_set_field32(&reg, GF20_PROT_CFG_RTS_TH_EN, 0);
3513         rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
3514
3515         rt2800_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
3516         rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_RATE, 0x4084);
3517         rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_CTRL, 0);
3518         rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_NAV_SHORT, 1);
3519         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_CCK, 1);
3520         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
3521         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
3522         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
3523         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
3524         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
3525         rt2x00_set_field32(&reg, GF40_PROT_CFG_RTS_TH_EN, 0);
3526         rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
3527
3528         if (rt2x00_is_usb(rt2x00dev)) {
3529                 rt2800_register_write(rt2x00dev, PBF_CFG, 0xf40006);
3530
3531                 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
3532                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
3533                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
3534                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
3535                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
3536                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE, 3);
3537                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 0);
3538                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_BIG_ENDIAN, 0);
3539                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_HDR_SCATTER, 0);
3540                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_HDR_SEG_LEN, 0);
3541                 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
3542         }
3543
3544         /*
3545          * The legacy driver also sets TXOP_CTRL_CFG_RESERVED_TRUN_EN to 1
3546          * although it is reserved.
3547          */
3548         rt2800_register_read(rt2x00dev, TXOP_CTRL_CFG, &reg);
3549         rt2x00_set_field32(&reg, TXOP_CTRL_CFG_TIMEOUT_TRUN_EN, 1);
3550         rt2x00_set_field32(&reg, TXOP_CTRL_CFG_AC_TRUN_EN, 1);
3551         rt2x00_set_field32(&reg, TXOP_CTRL_CFG_TXRATEGRP_TRUN_EN, 1);
3552         rt2x00_set_field32(&reg, TXOP_CTRL_CFG_USER_MODE_TRUN_EN, 1);
3553         rt2x00_set_field32(&reg, TXOP_CTRL_CFG_MIMO_PS_TRUN_EN, 1);
3554         rt2x00_set_field32(&reg, TXOP_CTRL_CFG_RESERVED_TRUN_EN, 1);
3555         rt2x00_set_field32(&reg, TXOP_CTRL_CFG_LSIG_TXOP_EN, 0);
3556         rt2x00_set_field32(&reg, TXOP_CTRL_CFG_EXT_CCA_EN, 0);
3557         rt2x00_set_field32(&reg, TXOP_CTRL_CFG_EXT_CCA_DLY, 88);
3558         rt2x00_set_field32(&reg, TXOP_CTRL_CFG_EXT_CWMIN, 0);
3559         rt2800_register_write(rt2x00dev, TXOP_CTRL_CFG, reg);
3560
3561         reg = rt2x00_rt(rt2x00dev, RT5592) ? 0x00000082 : 0x00000002;
3562         rt2800_register_write(rt2x00dev, TXOP_HLDR_ET, reg);
3563
3564         rt2800_register_read(rt2x00dev, TX_RTS_CFG, &reg);
3565         rt2x00_set_field32(&reg, TX_RTS_CFG_AUTO_RTS_RETRY_LIMIT, 32);
3566         rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_THRES,
3567                            IEEE80211_MAX_RTS_THRESHOLD);
3568         rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_FBK_EN, 0);
3569         rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg);
3570
3571         rt2800_register_write(rt2x00dev, EXP_ACK_TIME, 0x002400ca);
3572
3573         /*
3574          * Usually the CCK SIFS time should be set to 10 and the OFDM SIFS
3575          * time should be set to 16. However, the original Ralink driver uses
3576          * 16 for both and indeed using a value of 10 for CCK SIFS results in
3577          * connection problems with 11g + CTS protection. Hence, use the same
3578          * defaults as the Ralink driver: 16 for both, CCK and OFDM SIFS.
3579          */
3580         rt2800_register_read(rt2x00dev, XIFS_TIME_CFG, &reg);
3581         rt2x00_set_field32(&reg, XIFS_TIME_CFG_CCKM_SIFS_TIME, 16);
3582         rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_SIFS_TIME, 16);
3583         rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_XIFS_TIME, 4);
3584         rt2x00_set_field32(&reg, XIFS_TIME_CFG_EIFS, 314);
3585         rt2x00_set_field32(&reg, XIFS_TIME_CFG_BB_RXEND_ENABLE, 1);
3586         rt2800_register_write(rt2x00dev, XIFS_TIME_CFG, reg);
3587
3588         rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000003);
3589
3590         /*
3591          * ASIC will keep garbage value after boot, clear encryption keys.
3592          */
3593         for (i = 0; i < 4; i++)
3594                 rt2800_register_write(rt2x00dev,
3595                                          SHARED_KEY_MODE_ENTRY(i), 0);
3596
3597         for (i = 0; i < 256; i++) {
3598                 rt2800_config_wcid(rt2x00dev, NULL, i);
3599                 rt2800_delete_wcid_attr(rt2x00dev, i);
3600                 rt2800_register_write(rt2x00dev, MAC_IVEIV_ENTRY(i), 0);
3601         }
3602
3603         /*
3604          * Clear all beacons
3605          */
3606         rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE0);
3607         rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE1);
3608         rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE2);
3609         rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE3);
3610         rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE4);
3611         rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE5);
3612         rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE6);
3613         rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE7);
3614
3615         if (rt2x00_is_usb(rt2x00dev)) {
3616                 rt2800_register_read(rt2x00dev, US_CYC_CNT, &reg);
3617                 rt2x00_set_field32(&reg, US_CYC_CNT_CLOCK_CYCLE, 30);
3618                 rt2800_register_write(rt2x00dev, US_CYC_CNT, reg);
3619         } else if (rt2x00_is_pcie(rt2x00dev)) {
3620                 rt2800_register_read(rt2x00dev, US_CYC_CNT, &reg);
3621                 rt2x00_set_field32(&reg, US_CYC_CNT_CLOCK_CYCLE, 125);
3622                 rt2800_register_write(rt2x00dev, US_CYC_CNT, reg);
3623         }
3624
3625         rt2800_register_read(rt2x00dev, HT_FBK_CFG0, &reg);
3626         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS0FBK, 0);
3627         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS1FBK, 0);
3628         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS2FBK, 1);
3629         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS3FBK, 2);
3630         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS4FBK, 3);
3631         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS5FBK, 4);
3632         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS6FBK, 5);
3633         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS7FBK, 6);
3634         rt2800_register_write(rt2x00dev, HT_FBK_CFG0, reg);
3635
3636         rt2800_register_read(rt2x00dev, HT_FBK_CFG1, &reg);
3637         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS8FBK, 8);
3638         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS9FBK, 8);
3639         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS10FBK, 9);
3640         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS11FBK, 10);
3641         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS12FBK, 11);
3642         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS13FBK, 12);
3643         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS14FBK, 13);
3644         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS15FBK, 14);
3645         rt2800_register_write(rt2x00dev, HT_FBK_CFG1, reg);
3646
3647         rt2800_register_read(rt2x00dev, LG_FBK_CFG0, &reg);
3648         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS0FBK, 8);
3649         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS1FBK, 8);
3650         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS2FBK, 9);
3651         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS3FBK, 10);
3652         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS4FBK, 11);
3653         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS5FBK, 12);
3654         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS6FBK, 13);
3655         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS7FBK, 14);
3656         rt2800_register_write(rt2x00dev, LG_FBK_CFG0, reg);
3657
3658         rt2800_register_read(rt2x00dev, LG_FBK_CFG1, &reg);
3659         rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS0FBK, 0);
3660         rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS1FBK, 0);
3661         rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS2FBK, 1);
3662         rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS3FBK, 2);
3663         rt2800_register_write(rt2x00dev, LG_FBK_CFG1, reg);
3664
3665         /*
3666          * Do not force the BA window size, we use the TXWI to set it
3667          */
3668         rt2800_register_read(rt2x00dev, AMPDU_BA_WINSIZE, &reg);
3669         rt2x00_set_field32(&reg, AMPDU_BA_WINSIZE_FORCE_WINSIZE_ENABLE, 0);
3670         rt2x00_set_field32(&reg, AMPDU_BA_WINSIZE_FORCE_WINSIZE, 0);
3671         rt2800_register_write(rt2x00dev, AMPDU_BA_WINSIZE, reg);
3672
3673         /*
3674          * We must clear the error counters.
3675          * These registers are cleared on read,
3676          * so we may pass a useless variable to store the value.
3677          */
3678         rt2800_register_read(rt2x00dev, RX_STA_CNT0, &reg);
3679         rt2800_register_read(rt2x00dev, RX_STA_CNT1, &reg);
3680         rt2800_register_read(rt2x00dev, RX_STA_CNT2, &reg);
3681         rt2800_register_read(rt2x00dev, TX_STA_CNT0, &reg);
3682         rt2800_register_read(rt2x00dev, TX_STA_CNT1, &reg);
3683         rt2800_register_read(rt2x00dev, TX_STA_CNT2, &reg);
3684
3685         /*
3686          * Setup leadtime for pre tbtt interrupt to 6ms
3687          */
3688         rt2800_register_read(rt2x00dev, INT_TIMER_CFG, &reg);
3689         rt2x00_set_field32(&reg, INT_TIMER_CFG_PRE_TBTT_TIMER, 6 << 4);
3690         rt2800_register_write(rt2x00dev, INT_TIMER_CFG, reg);
3691
3692         /*
3693          * Set up channel statistics timer
3694          */
3695         rt2800_register_read(rt2x00dev, CH_TIME_CFG, &reg);
3696         rt2x00_set_field32(&reg, CH_TIME_CFG_EIFS_BUSY, 1);
3697         rt2x00_set_field32(&reg, CH_TIME_CFG_NAV_BUSY, 1);
3698         rt2x00_set_field32(&reg, CH_TIME_CFG_RX_BUSY, 1);
3699         rt2x00_set_field32(&reg, CH_TIME_CFG_TX_BUSY, 1);
3700         rt2x00_set_field32(&reg, CH_TIME_CFG_TMR_EN, 1);
3701         rt2800_register_write(rt2x00dev, CH_TIME_CFG, reg);
3702
3703         return 0;
3704 }
3705
3706 static int rt2800_wait_bbp_rf_ready(struct rt2x00_dev *rt2x00dev)
3707 {
3708         unsigned int i;
3709         u32 reg;
3710
3711         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
3712                 rt2800_register_read(rt2x00dev, MAC_STATUS_CFG, &reg);
3713                 if (!rt2x00_get_field32(reg, MAC_STATUS_CFG_BBP_RF_BUSY))
3714                         return 0;
3715
3716                 udelay(REGISTER_BUSY_DELAY);
3717         }
3718
3719         ERROR(rt2x00dev, "BBP/RF register access failed, aborting.\n");
3720         return -EACCES;
3721 }
3722
3723 static int rt2800_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)
3724 {
3725         unsigned int i;
3726         u8 value;
3727
3728         /*
3729          * BBP was enabled after firmware was loaded,
3730          * but we need to reactivate it now.
3731          */
3732         rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
3733         rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
3734         msleep(1);
3735
3736         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
3737                 rt2800_bbp_read(rt2x00dev, 0, &value);
3738                 if ((value != 0xff) && (value != 0x00))
3739                         return 0;
3740                 udelay(REGISTER_BUSY_DELAY);
3741         }
3742
3743         ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
3744         return -EACCES;
3745 }
3746
3747 static void rt2800_bbp4_mac_if_ctrl(struct rt2x00_dev *rt2x00dev)
3748 {
3749         u8 value;
3750
3751         rt2800_bbp_read(rt2x00dev, 4, &value);
3752         rt2x00_set_field8(&value, BBP4_MAC_IF_CTRL, 1);
3753         rt2800_bbp_write(rt2x00dev, 4, value);
3754 }
3755
3756 static void rt2800_init_bbp_5592_glrt(struct rt2x00_dev *rt2x00dev)
3757 {
3758         const u8 glrt_table[] = {
3759                 0xE0, 0x1F, 0X38, 0x32, 0x08, 0x28, 0x19, 0x0A, 0xFF, 0x00, /* 128 ~ 137 */
3760                 0x16, 0x10, 0x10, 0x0B, 0x36, 0x2C, 0x26, 0x24, 0x42, 0x36, /* 138 ~ 147 */
3761                 0x30, 0x2D, 0x4C, 0x46, 0x3D, 0x40, 0x3E, 0x42, 0x3D, 0x40, /* 148 ~ 157 */
3762                 0X3C, 0x34, 0x2C, 0x2F, 0x3C, 0x35, 0x2E, 0x2A, 0x49, 0x41, /* 158 ~ 167 */
3763                 0x36, 0x31, 0x30, 0x30, 0x0E, 0x0D, 0x28, 0x21, 0x1C, 0x16, /* 168 ~ 177 */
3764                 0x50, 0x4A, 0x43, 0x40, 0x10, 0x10, 0x10, 0x10, 0x00, 0x00, /* 178 ~ 187 */
3765                 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 188 ~ 197 */
3766                 0x00, 0x00, 0x7D, 0x14, 0x32, 0x2C, 0x36, 0x4C, 0x43, 0x2C, /* 198 ~ 207 */
3767                 0x2E, 0x36, 0x30, 0x6E,                                     /* 208 ~ 211 */
3768         };
3769         int i;
3770
3771         for (i = 0; i < ARRAY_SIZE(glrt_table); i++) {
3772                 rt2800_bbp_write(rt2x00dev, 195, 128 + i);
3773                 rt2800_bbp_write(rt2x00dev, 196, glrt_table[i]);
3774         }
3775 };
3776
3777 static void rt2800_init_bbp_5592(struct rt2x00_dev *rt2x00dev)
3778 {
3779         int ant, div_mode;
3780         u16 eeprom;
3781         u8 value;
3782
3783         rt2800_bbp_read(rt2x00dev, 105, &value);
3784         rt2x00_set_field8(&value, BBP105_MLD,
3785                           rt2x00dev->default_ant.rx_chain_num == 2);
3786         rt2800_bbp_write(rt2x00dev, 105, value);
3787
3788         rt2800_bbp4_mac_if_ctrl(rt2x00dev);
3789
3790         rt2800_bbp_write(rt2x00dev, 20, 0x06);
3791         rt2800_bbp_write(rt2x00dev, 31, 0x08);
3792         rt2800_bbp_write(rt2x00dev, 65, 0x2C);
3793         rt2800_bbp_write(rt2x00dev, 68, 0xDD);
3794         rt2800_bbp_write(rt2x00dev, 69, 0x1A);
3795         rt2800_bbp_write(rt2x00dev, 70, 0x05);
3796         rt2800_bbp_write(rt2x00dev, 73, 0x13);
3797         rt2800_bbp_write(rt2x00dev, 74, 0x0F);
3798         rt2800_bbp_write(rt2x00dev, 75, 0x4F);
3799         rt2800_bbp_write(rt2x00dev, 76, 0x28);
3800         rt2800_bbp_write(rt2x00dev, 77, 0x59);
3801         rt2800_bbp_write(rt2x00dev, 84, 0x9A);
3802         rt2800_bbp_write(rt2x00dev, 86, 0x38);
3803         rt2800_bbp_write(rt2x00dev, 88, 0x90);
3804         rt2800_bbp_write(rt2x00dev, 91, 0x04);
3805         rt2800_bbp_write(rt2x00dev, 92, 0x02);
3806         rt2800_bbp_write(rt2x00dev, 95, 0x9a);
3807         rt2800_bbp_write(rt2x00dev, 98, 0x12);
3808         rt2800_bbp_write(rt2x00dev, 103, 0xC0);
3809         rt2800_bbp_write(rt2x00dev, 104, 0x92);
3810         /* FIXME BBP105 owerwrite */
3811         rt2800_bbp_write(rt2x00dev, 105, 0x3C);
3812         rt2800_bbp_write(rt2x00dev, 106, 0x35);
3813         rt2800_bbp_write(rt2x00dev, 128, 0x12);
3814         rt2800_bbp_write(rt2x00dev, 134, 0xD0);
3815         rt2800_bbp_write(rt2x00dev, 135, 0xF6);
3816         rt2800_bbp_write(rt2x00dev, 137, 0x0F);
3817
3818         /* Initialize GLRT (Generalized Likehood Radio Test) */
3819         rt2800_init_bbp_5592_glrt(rt2x00dev);
3820
3821         rt2800_bbp4_mac_if_ctrl(rt2x00dev);
3822
3823         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
3824         div_mode = rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_ANT_DIVERSITY);
3825         ant = (div_mode == 3) ? 1 : 0;
3826         rt2800_bbp_read(rt2x00dev, 152, &value);
3827         if (ant == 0) {
3828                 /* Main antenna */
3829                 rt2x00_set_field8(&value, BBP152_RX_DEFAULT_ANT, 1);
3830         } else {
3831                 /* Auxiliary antenna */
3832                 rt2x00_set_field8(&value, BBP152_RX_DEFAULT_ANT, 0);
3833         }
3834         rt2800_bbp_write(rt2x00dev, 152, value);
3835
3836         if (rt2x00_rt_rev_gte(rt2x00dev, RT5592, REV_RT5592C)) {
3837                 rt2800_bbp_read(rt2x00dev, 254, &value);
3838                 rt2x00_set_field8(&value, BBP254_BIT7, 1);
3839                 rt2800_bbp_write(rt2x00dev, 254, value);
3840         }
3841
3842         rt2800_bbp_write(rt2x00dev, 84, 0x19);
3843 }
3844
3845 static int rt2800_init_bbp(struct rt2x00_dev *rt2x00dev)
3846 {
3847         unsigned int i;
3848         u16 eeprom;
3849         u8 reg_id;
3850         u8 value;
3851
3852         if (unlikely(rt2800_wait_bbp_rf_ready(rt2x00dev) ||
3853                      rt2800_wait_bbp_ready(rt2x00dev)))
3854                 return -EACCES;
3855
3856         if (rt2x00_rt(rt2x00dev, RT5592)) {
3857                 rt2800_init_bbp_5592(rt2x00dev);
3858                 return 0;
3859         }
3860
3861         if (rt2x00_rt(rt2x00dev, RT3352)) {
3862                 rt2800_bbp_write(rt2x00dev, 3, 0x00);
3863                 rt2800_bbp_write(rt2x00dev, 4, 0x50);
3864         }
3865
3866         if (rt2x00_rt(rt2x00dev, RT3290) ||
3867             rt2x00_rt(rt2x00dev, RT5390) ||
3868             rt2x00_rt(rt2x00dev, RT5392))
3869                 rt2800_bbp4_mac_if_ctrl(rt2x00dev);
3870
3871         if (rt2800_is_305x_soc(rt2x00dev) ||
3872             rt2x00_rt(rt2x00dev, RT3290) ||
3873             rt2x00_rt(rt2x00dev, RT3352) ||
3874             rt2x00_rt(rt2x00dev, RT3572) ||
3875             rt2x00_rt(rt2x00dev, RT5390) ||
3876             rt2x00_rt(rt2x00dev, RT5392))
3877                 rt2800_bbp_write(rt2x00dev, 31, 0x08);
3878
3879         if (rt2x00_rt(rt2x00dev, RT3352))
3880                 rt2800_bbp_write(rt2x00dev, 47, 0x48);
3881
3882         rt2800_bbp_write(rt2x00dev, 65, 0x2c);
3883         rt2800_bbp_write(rt2x00dev, 66, 0x38);
3884
3885         if (rt2x00_rt(rt2x00dev, RT3290) ||
3886             rt2x00_rt(rt2x00dev, RT3352) ||
3887             rt2x00_rt(rt2x00dev, RT5390) ||
3888             rt2x00_rt(rt2x00dev, RT5392))
3889                 rt2800_bbp_write(rt2x00dev, 68, 0x0b);
3890
3891         if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C)) {
3892                 rt2800_bbp_write(rt2x00dev, 69, 0x16);
3893                 rt2800_bbp_write(rt2x00dev, 73, 0x12);
3894         } else if (rt2x00_rt(rt2x00dev, RT3290) ||
3895                    rt2x00_rt(rt2x00dev, RT3352) ||
3896                    rt2x00_rt(rt2x00dev, RT5390) ||
3897                    rt2x00_rt(rt2x00dev, RT5392)) {
3898                 rt2800_bbp_write(rt2x00dev, 69, 0x12);
3899                 rt2800_bbp_write(rt2x00dev, 73, 0x13);
3900                 rt2800_bbp_write(rt2x00dev, 75, 0x46);
3901                 rt2800_bbp_write(rt2x00dev, 76, 0x28);
3902
3903                 if (rt2x00_rt(rt2x00dev, RT3290))
3904                         rt2800_bbp_write(rt2x00dev, 77, 0x58);
3905                 else
3906                         rt2800_bbp_write(rt2x00dev, 77, 0x59);
3907         } else {
3908                 rt2800_bbp_write(rt2x00dev, 69, 0x12);
3909                 rt2800_bbp_write(rt2x00dev, 73, 0x10);
3910         }
3911
3912         rt2800_bbp_write(rt2x00dev, 70, 0x0a);
3913
3914         if (rt2x00_rt(rt2x00dev, RT3070) ||
3915             rt2x00_rt(rt2x00dev, RT3071) ||
3916             rt2x00_rt(rt2x00dev, RT3090) ||
3917             rt2x00_rt(rt2x00dev, RT3390) ||
3918             rt2x00_rt(rt2x00dev, RT3572) ||
3919             rt2x00_rt(rt2x00dev, RT5390) ||
3920             rt2x00_rt(rt2x00dev, RT5392)) {
3921                 rt2800_bbp_write(rt2x00dev, 79, 0x13);
3922                 rt2800_bbp_write(rt2x00dev, 80, 0x05);
3923                 rt2800_bbp_write(rt2x00dev, 81, 0x33);
3924         } else if (rt2800_is_305x_soc(rt2x00dev)) {
3925                 rt2800_bbp_write(rt2x00dev, 78, 0x0e);
3926                 rt2800_bbp_write(rt2x00dev, 80, 0x08);
3927         } else if (rt2x00_rt(rt2x00dev, RT3290)) {
3928                 rt2800_bbp_write(rt2x00dev, 74, 0x0b);
3929                 rt2800_bbp_write(rt2x00dev, 79, 0x18);
3930                 rt2800_bbp_write(rt2x00dev, 80, 0x09);
3931                 rt2800_bbp_write(rt2x00dev, 81, 0x33);
3932         } else if (rt2x00_rt(rt2x00dev, RT3352)) {
3933                 rt2800_bbp_write(rt2x00dev, 78, 0x0e);
3934                 rt2800_bbp_write(rt2x00dev, 80, 0x08);
3935                 rt2800_bbp_write(rt2x00dev, 81, 0x37);
3936         } else {
3937                 rt2800_bbp_write(rt2x00dev, 81, 0x37);
3938         }
3939
3940         rt2800_bbp_write(rt2x00dev, 82, 0x62);
3941         if (rt2x00_rt(rt2x00dev, RT3290) ||
3942             rt2x00_rt(rt2x00dev, RT5390) ||
3943             rt2x00_rt(rt2x00dev, RT5392))
3944                 rt2800_bbp_write(rt2x00dev, 83, 0x7a);
3945         else
3946                 rt2800_bbp_write(rt2x00dev, 83, 0x6a);
3947
3948         if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860D))
3949                 rt2800_bbp_write(rt2x00dev, 84, 0x19);
3950         else if (rt2x00_rt(rt2x00dev, RT3290) ||
3951                  rt2x00_rt(rt2x00dev, RT5390) ||
3952                  rt2x00_rt(rt2x00dev, RT5392))
3953                 rt2800_bbp_write(rt2x00dev, 84, 0x9a);
3954         else
3955                 rt2800_bbp_write(rt2x00dev, 84, 0x99);
3956
3957         if (rt2x00_rt(rt2x00dev, RT3290) ||
3958             rt2x00_rt(rt2x00dev, RT3352) ||
3959             rt2x00_rt(rt2x00dev, RT5390) ||
3960             rt2x00_rt(rt2x00dev, RT5392))
3961                 rt2800_bbp_write(rt2x00dev, 86, 0x38);
3962         else
3963                 rt2800_bbp_write(rt2x00dev, 86, 0x00);
3964
3965         if (rt2x00_rt(rt2x00dev, RT3352) ||
3966             rt2x00_rt(rt2x00dev, RT5392))
3967                 rt2800_bbp_write(rt2x00dev, 88, 0x90);
3968
3969         rt2800_bbp_write(rt2x00dev, 91, 0x04);
3970
3971         if (rt2x00_rt(rt2x00dev, RT3290) ||
3972             rt2x00_rt(rt2x00dev, RT3352) ||
3973             rt2x00_rt(rt2x00dev, RT5390) ||
3974             rt2x00_rt(rt2x00dev, RT5392))
3975                 rt2800_bbp_write(rt2x00dev, 92, 0x02);
3976         else
3977                 rt2800_bbp_write(rt2x00dev, 92, 0x00);
3978
3979         if (rt2x00_rt(rt2x00dev, RT5392)) {
3980                 rt2800_bbp_write(rt2x00dev, 95, 0x9a);
3981                 rt2800_bbp_write(rt2x00dev, 98, 0x12);
3982         }
3983
3984         if (rt2x00_rt_rev_gte(rt2x00dev, RT3070, REV_RT3070F) ||
3985             rt2x00_rt_rev_gte(rt2x00dev, RT3071, REV_RT3071E) ||
3986             rt2x00_rt_rev_gte(rt2x00dev, RT3090, REV_RT3090E) ||
3987             rt2x00_rt_rev_gte(rt2x00dev, RT3390, REV_RT3390E) ||
3988             rt2x00_rt(rt2x00dev, RT3290) ||
3989             rt2x00_rt(rt2x00dev, RT3352) ||
3990             rt2x00_rt(rt2x00dev, RT3572) ||
3991             rt2x00_rt(rt2x00dev, RT5390) ||
3992             rt2x00_rt(rt2x00dev, RT5392) ||
3993             rt2800_is_305x_soc(rt2x00dev))
3994                 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
3995         else
3996                 rt2800_bbp_write(rt2x00dev, 103, 0x00);
3997
3998         if (rt2x00_rt(rt2x00dev, RT3290) ||
3999             rt2x00_rt(rt2x00dev, RT3352) ||
4000             rt2x00_rt(rt2x00dev, RT5390) ||
4001             rt2x00_rt(rt2x00dev, RT5392))
4002                 rt2800_bbp_write(rt2x00dev, 104, 0x92);
4003
4004         if (rt2800_is_305x_soc(rt2x00dev))
4005                 rt2800_bbp_write(rt2x00dev, 105, 0x01);
4006         else if (rt2x00_rt(rt2x00dev, RT3290))
4007                 rt2800_bbp_write(rt2x00dev, 105, 0x1c);
4008         else if (rt2x00_rt(rt2x00dev, RT3352))
4009                 rt2800_bbp_write(rt2x00dev, 105, 0x34);
4010         else if (rt2x00_rt(rt2x00dev, RT5390) ||
4011                  rt2x00_rt(rt2x00dev, RT5392))
4012                 rt2800_bbp_write(rt2x00dev, 105, 0x3c);
4013         else
4014                 rt2800_bbp_write(rt2x00dev, 105, 0x05);
4015
4016         if (rt2x00_rt(rt2x00dev, RT3290) ||
4017             rt2x00_rt(rt2x00dev, RT5390))
4018                 rt2800_bbp_write(rt2x00dev, 106, 0x03);
4019         else if (rt2x00_rt(rt2x00dev, RT3352))
4020                 rt2800_bbp_write(rt2x00dev, 106, 0x05);
4021         else if (rt2x00_rt(rt2x00dev, RT5392))
4022                 rt2800_bbp_write(rt2x00dev, 106, 0x12);
4023         else
4024                 rt2800_bbp_write(rt2x00dev, 106, 0x35);
4025
4026         if (rt2x00_rt(rt2x00dev, RT3352))
4027                 rt2800_bbp_write(rt2x00dev, 120, 0x50);
4028
4029         if (rt2x00_rt(rt2x00dev, RT3290) ||
4030             rt2x00_rt(rt2x00dev, RT5390) ||
4031             rt2x00_rt(rt2x00dev, RT5392))
4032                 rt2800_bbp_write(rt2x00dev, 128, 0x12);
4033
4034         if (rt2x00_rt(rt2x00dev, RT5392)) {
4035                 rt2800_bbp_write(rt2x00dev, 134, 0xd0);
4036                 rt2800_bbp_write(rt2x00dev, 135, 0xf6);
4037         }
4038
4039         if (rt2x00_rt(rt2x00dev, RT3352))
4040                 rt2800_bbp_write(rt2x00dev, 137, 0x0f);
4041
4042         if (rt2x00_rt(rt2x00dev, RT3071) ||
4043             rt2x00_rt(rt2x00dev, RT3090) ||
4044             rt2x00_rt(rt2x00dev, RT3390) ||
4045             rt2x00_rt(rt2x00dev, RT3572) ||
4046             rt2x00_rt(rt2x00dev, RT5390) ||
4047             rt2x00_rt(rt2x00dev, RT5392)) {
4048                 rt2800_bbp_read(rt2x00dev, 138, &value);
4049
4050                 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom);
4051                 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) == 1)
4052                         value |= 0x20;
4053                 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) == 1)
4054                         value &= ~0x02;
4055
4056                 rt2800_bbp_write(rt2x00dev, 138, value);
4057         }
4058
4059         if (rt2x00_rt(rt2x00dev, RT3290)) {
4060                 rt2800_bbp_write(rt2x00dev, 67, 0x24);
4061                 rt2800_bbp_write(rt2x00dev, 143, 0x04);
4062                 rt2800_bbp_write(rt2x00dev, 142, 0x99);
4063                 rt2800_bbp_write(rt2x00dev, 150, 0x30);
4064                 rt2800_bbp_write(rt2x00dev, 151, 0x2e);
4065                 rt2800_bbp_write(rt2x00dev, 152, 0x20);
4066                 rt2800_bbp_write(rt2x00dev, 153, 0x34);
4067                 rt2800_bbp_write(rt2x00dev, 154, 0x40);
4068                 rt2800_bbp_write(rt2x00dev, 155, 0x3b);
4069                 rt2800_bbp_write(rt2x00dev, 253, 0x04);
4070
4071                 rt2800_bbp_read(rt2x00dev, 47, &value);
4072                 rt2x00_set_field8(&value, BBP47_TSSI_ADC6, 1);
4073                 rt2800_bbp_write(rt2x00dev, 47, value);
4074
4075                 /* Use 5-bit ADC for Acquisition and 8-bit ADC for data */
4076                 rt2800_bbp_read(rt2x00dev, 3, &value);
4077                 rt2x00_set_field8(&value, BBP3_ADC_MODE_SWITCH, 1);
4078                 rt2x00_set_field8(&value, BBP3_ADC_INIT_MODE, 1);
4079                 rt2800_bbp_write(rt2x00dev, 3, value);
4080         }
4081
4082         if (rt2x00_rt(rt2x00dev, RT3352)) {
4083                 rt2800_bbp_write(rt2x00dev, 163, 0xbd);
4084                 /* Set ITxBF timeout to 0x9c40=1000msec */
4085                 rt2800_bbp_write(rt2x00dev, 179, 0x02);
4086                 rt2800_bbp_write(rt2x00dev, 180, 0x00);
4087                 rt2800_bbp_write(rt2x00dev, 182, 0x40);
4088                 rt2800_bbp_write(rt2x00dev, 180, 0x01);
4089                 rt2800_bbp_write(rt2x00dev, 182, 0x9c);
4090                 rt2800_bbp_write(rt2x00dev, 179, 0x00);
4091                 /* Reprogram the inband interface to put right values in RXWI */
4092                 rt2800_bbp_write(rt2x00dev, 142, 0x04);
4093                 rt2800_bbp_write(rt2x00dev, 143, 0x3b);
4094                 rt2800_bbp_write(rt2x00dev, 142, 0x06);
4095                 rt2800_bbp_write(rt2x00dev, 143, 0xa0);
4096                 rt2800_bbp_write(rt2x00dev, 142, 0x07);
4097                 rt2800_bbp_write(rt2x00dev, 143, 0xa1);
4098                 rt2800_bbp_write(rt2x00dev, 142, 0x08);
4099                 rt2800_bbp_write(rt2x00dev, 143, 0xa2);
4100
4101                 rt2800_bbp_write(rt2x00dev, 148, 0xc8);
4102         }
4103
4104         if (rt2x00_rt(rt2x00dev, RT5390) ||
4105             rt2x00_rt(rt2x00dev, RT5392)) {
4106                 int ant, div_mode;
4107
4108                 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
4109                 div_mode = rt2x00_get_field16(eeprom,
4110                                               EEPROM_NIC_CONF1_ANT_DIVERSITY);
4111                 ant = (div_mode == 3) ? 1 : 0;
4112
4113                 /* check if this is a Bluetooth combo card */
4114                 if (test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags)) {
4115                         u32 reg;
4116
4117                         rt2800_register_read(rt2x00dev, GPIO_CTRL, &reg);
4118                         rt2x00_set_field32(&reg, GPIO_CTRL_DIR3, 0);
4119                         rt2x00_set_field32(&reg, GPIO_CTRL_DIR6, 0);
4120                         rt2x00_set_field32(&reg, GPIO_CTRL_VAL3, 0);
4121                         rt2x00_set_field32(&reg, GPIO_CTRL_VAL6, 0);
4122                         if (ant == 0)
4123                                 rt2x00_set_field32(&reg, GPIO_CTRL_VAL3, 1);
4124                         else if (ant == 1)
4125                                 rt2x00_set_field32(&reg, GPIO_CTRL_VAL6, 1);
4126                         rt2800_register_write(rt2x00dev, GPIO_CTRL, reg);
4127                 }
4128
4129                 /* This chip has hardware antenna diversity*/
4130                 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390R)) {
4131                         rt2800_bbp_write(rt2x00dev, 150, 0); /* Disable Antenna Software OFDM */
4132                         rt2800_bbp_write(rt2x00dev, 151, 0); /* Disable Antenna Software CCK */
4133                         rt2800_bbp_write(rt2x00dev, 154, 0); /* Clear previously selected antenna */
4134                 }
4135
4136                 rt2800_bbp_read(rt2x00dev, 152, &value);
4137                 if (ant == 0)
4138                         rt2x00_set_field8(&value, BBP152_RX_DEFAULT_ANT, 1);
4139                 else
4140                         rt2x00_set_field8(&value, BBP152_RX_DEFAULT_ANT, 0);
4141                 rt2800_bbp_write(rt2x00dev, 152, value);
4142
4143                 /* Init frequency calibration */
4144                 rt2800_bbp_write(rt2x00dev, 142, 1);
4145                 rt2800_bbp_write(rt2x00dev, 143, 57);
4146         }
4147
4148         for (i = 0; i < EEPROM_BBP_SIZE; i++) {
4149                 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
4150
4151                 if (eeprom != 0xffff && eeprom != 0x0000) {
4152                         reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
4153                         value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
4154                         rt2800_bbp_write(rt2x00dev, reg_id, value);
4155                 }
4156         }
4157
4158         return 0;
4159 }
4160
4161 static u8 rt2800_init_rx_filter(struct rt2x00_dev *rt2x00dev,
4162                                 bool bw40, u8 rfcsr24, u8 filter_target)
4163 {
4164         unsigned int i;
4165         u8 bbp;
4166         u8 rfcsr;
4167         u8 passband;
4168         u8 stopband;
4169         u8 overtuned = 0;
4170
4171         rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
4172
4173         rt2800_bbp_read(rt2x00dev, 4, &bbp);
4174         rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * bw40);
4175         rt2800_bbp_write(rt2x00dev, 4, bbp);
4176
4177         rt2800_rfcsr_read(rt2x00dev, 31, &rfcsr);
4178         rt2x00_set_field8(&rfcsr, RFCSR31_RX_H20M, bw40);
4179         rt2800_rfcsr_write(rt2x00dev, 31, rfcsr);
4180
4181         rt2800_rfcsr_read(rt2x00dev, 22, &rfcsr);
4182         rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 1);
4183         rt2800_rfcsr_write(rt2x00dev, 22, rfcsr);
4184
4185         /*
4186          * Set power & frequency of passband test tone
4187          */
4188         rt2800_bbp_write(rt2x00dev, 24, 0);
4189
4190         for (i = 0; i < 100; i++) {
4191                 rt2800_bbp_write(rt2x00dev, 25, 0x90);
4192                 msleep(1);
4193
4194                 rt2800_bbp_read(rt2x00dev, 55, &passband);
4195                 if (passband)
4196                         break;
4197         }
4198
4199         /*
4200          * Set power & frequency of stopband test tone
4201          */
4202         rt2800_bbp_write(rt2x00dev, 24, 0x06);
4203
4204         for (i = 0; i < 100; i++) {
4205                 rt2800_bbp_write(rt2x00dev, 25, 0x90);
4206                 msleep(1);
4207
4208                 rt2800_bbp_read(rt2x00dev, 55, &stopband);
4209
4210                 if ((passband - stopband) <= filter_target) {
4211                         rfcsr24++;
4212                         overtuned += ((passband - stopband) == filter_target);
4213                 } else
4214                         break;
4215
4216                 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
4217         }
4218
4219         rfcsr24 -= !!overtuned;
4220
4221         rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
4222         return rfcsr24;
4223 }
4224
4225 static void rt2800_init_rfcsr_305x_soc(struct rt2x00_dev *rt2x00dev)
4226 {
4227         rt2800_rfcsr_write(rt2x00dev, 0, 0x50);
4228         rt2800_rfcsr_write(rt2x00dev, 1, 0x01);
4229         rt2800_rfcsr_write(rt2x00dev, 2, 0xf7);
4230         rt2800_rfcsr_write(rt2x00dev, 3, 0x75);
4231         rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
4232         rt2800_rfcsr_write(rt2x00dev, 5, 0x03);
4233         rt2800_rfcsr_write(rt2x00dev, 6, 0x02);
4234         rt2800_rfcsr_write(rt2x00dev, 7, 0x50);
4235         rt2800_rfcsr_write(rt2x00dev, 8, 0x39);
4236         rt2800_rfcsr_write(rt2x00dev, 9, 0x0f);
4237         rt2800_rfcsr_write(rt2x00dev, 10, 0x60);
4238         rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
4239         rt2800_rfcsr_write(rt2x00dev, 12, 0x75);
4240         rt2800_rfcsr_write(rt2x00dev, 13, 0x75);
4241         rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
4242         rt2800_rfcsr_write(rt2x00dev, 15, 0x58);
4243         rt2800_rfcsr_write(rt2x00dev, 16, 0xb3);
4244         rt2800_rfcsr_write(rt2x00dev, 17, 0x92);
4245         rt2800_rfcsr_write(rt2x00dev, 18, 0x2c);
4246         rt2800_rfcsr_write(rt2x00dev, 19, 0x02);
4247         rt2800_rfcsr_write(rt2x00dev, 20, 0xba);
4248         rt2800_rfcsr_write(rt2x00dev, 21, 0xdb);
4249         rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
4250         rt2800_rfcsr_write(rt2x00dev, 23, 0x31);
4251         rt2800_rfcsr_write(rt2x00dev, 24, 0x08);
4252         rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
4253         rt2800_rfcsr_write(rt2x00dev, 26, 0x25);
4254         rt2800_rfcsr_write(rt2x00dev, 27, 0x23);
4255         rt2800_rfcsr_write(rt2x00dev, 28, 0x13);
4256         rt2800_rfcsr_write(rt2x00dev, 29, 0x83);
4257         rt2800_rfcsr_write(rt2x00dev, 30, 0x00);
4258         rt2800_rfcsr_write(rt2x00dev, 31, 0x00);
4259 }
4260
4261 static void rt2800_init_rfcsr_30xx(struct rt2x00_dev *rt2x00dev)
4262 {
4263         rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
4264         rt2800_rfcsr_write(rt2x00dev, 5, 0x03);
4265         rt2800_rfcsr_write(rt2x00dev, 6, 0x02);
4266         rt2800_rfcsr_write(rt2x00dev, 7, 0x60);
4267         rt2800_rfcsr_write(rt2x00dev, 9, 0x0f);
4268         rt2800_rfcsr_write(rt2x00dev, 10, 0x41);
4269         rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
4270         rt2800_rfcsr_write(rt2x00dev, 12, 0x7b);
4271         rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
4272         rt2800_rfcsr_write(rt2x00dev, 15, 0x58);
4273         rt2800_rfcsr_write(rt2x00dev, 16, 0xb3);
4274         rt2800_rfcsr_write(rt2x00dev, 17, 0x92);
4275         rt2800_rfcsr_write(rt2x00dev, 18, 0x2c);
4276         rt2800_rfcsr_write(rt2x00dev, 19, 0x02);
4277         rt2800_rfcsr_write(rt2x00dev, 20, 0xba);
4278         rt2800_rfcsr_write(rt2x00dev, 21, 0xdb);
4279         rt2800_rfcsr_write(rt2x00dev, 24, 0x16);
4280         rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
4281         rt2800_rfcsr_write(rt2x00dev, 29, 0x1f);
4282 }
4283
4284 static void rt2800_init_rfcsr_3290(struct rt2x00_dev *rt2x00dev)
4285 {
4286         rt2800_rfcsr_write(rt2x00dev, 1, 0x0f);
4287         rt2800_rfcsr_write(rt2x00dev, 2, 0x80);
4288         rt2800_rfcsr_write(rt2x00dev, 3, 0x08);
4289         rt2800_rfcsr_write(rt2x00dev, 4, 0x00);
4290         rt2800_rfcsr_write(rt2x00dev, 6, 0xa0);
4291         rt2800_rfcsr_write(rt2x00dev, 8, 0xf3);
4292         rt2800_rfcsr_write(rt2x00dev, 9, 0x02);
4293         rt2800_rfcsr_write(rt2x00dev, 10, 0x53);
4294         rt2800_rfcsr_write(rt2x00dev, 11, 0x4a);
4295         rt2800_rfcsr_write(rt2x00dev, 12, 0x46);
4296         rt2800_rfcsr_write(rt2x00dev, 13, 0x9f);
4297         rt2800_rfcsr_write(rt2x00dev, 18, 0x02);
4298         rt2800_rfcsr_write(rt2x00dev, 22, 0x20);
4299         rt2800_rfcsr_write(rt2x00dev, 25, 0x83);
4300         rt2800_rfcsr_write(rt2x00dev, 26, 0x82);
4301         rt2800_rfcsr_write(rt2x00dev, 27, 0x09);
4302         rt2800_rfcsr_write(rt2x00dev, 29, 0x10);
4303         rt2800_rfcsr_write(rt2x00dev, 30, 0x10);
4304         rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
4305         rt2800_rfcsr_write(rt2x00dev, 32, 0x80);
4306         rt2800_rfcsr_write(rt2x00dev, 33, 0x00);
4307         rt2800_rfcsr_write(rt2x00dev, 34, 0x05);
4308         rt2800_rfcsr_write(rt2x00dev, 35, 0x12);
4309         rt2800_rfcsr_write(rt2x00dev, 36, 0x00);
4310         rt2800_rfcsr_write(rt2x00dev, 38, 0x85);
4311         rt2800_rfcsr_write(rt2x00dev, 39, 0x1b);
4312         rt2800_rfcsr_write(rt2x00dev, 40, 0x0b);
4313         rt2800_rfcsr_write(rt2x00dev, 41, 0xbb);
4314         rt2800_rfcsr_write(rt2x00dev, 42, 0xd5);
4315         rt2800_rfcsr_write(rt2x00dev, 43, 0x7b);
4316         rt2800_rfcsr_write(rt2x00dev, 44, 0x0e);
4317         rt2800_rfcsr_write(rt2x00dev, 45, 0xa2);
4318         rt2800_rfcsr_write(rt2x00dev, 46, 0x73);
4319         rt2800_rfcsr_write(rt2x00dev, 47, 0x00);
4320         rt2800_rfcsr_write(rt2x00dev, 48, 0x10);
4321         rt2800_rfcsr_write(rt2x00dev, 49, 0x98);
4322         rt2800_rfcsr_write(rt2x00dev, 52, 0x38);
4323         rt2800_rfcsr_write(rt2x00dev, 53, 0x00);
4324         rt2800_rfcsr_write(rt2x00dev, 54, 0x78);
4325         rt2800_rfcsr_write(rt2x00dev, 55, 0x43);
4326         rt2800_rfcsr_write(rt2x00dev, 56, 0x02);
4327         rt2800_rfcsr_write(rt2x00dev, 57, 0x80);
4328         rt2800_rfcsr_write(rt2x00dev, 58, 0x7f);
4329         rt2800_rfcsr_write(rt2x00dev, 59, 0x09);
4330         rt2800_rfcsr_write(rt2x00dev, 60, 0x45);
4331         rt2800_rfcsr_write(rt2x00dev, 61, 0xc1);
4332 }
4333
4334 static void rt2800_init_rfcsr_3352(struct rt2x00_dev *rt2x00dev)
4335 {
4336         rt2800_rfcsr_write(rt2x00dev, 0, 0xf0);
4337         rt2800_rfcsr_write(rt2x00dev, 1, 0x23);
4338         rt2800_rfcsr_write(rt2x00dev, 2, 0x50);
4339         rt2800_rfcsr_write(rt2x00dev, 3, 0x18);
4340         rt2800_rfcsr_write(rt2x00dev, 4, 0x00);
4341         rt2800_rfcsr_write(rt2x00dev, 5, 0x00);
4342         rt2800_rfcsr_write(rt2x00dev, 6, 0x33);
4343         rt2800_rfcsr_write(rt2x00dev, 7, 0x00);
4344         rt2800_rfcsr_write(rt2x00dev, 8, 0xf1);
4345         rt2800_rfcsr_write(rt2x00dev, 9, 0x02);
4346         rt2800_rfcsr_write(rt2x00dev, 10, 0xd2);
4347         rt2800_rfcsr_write(rt2x00dev, 11, 0x42);
4348         rt2800_rfcsr_write(rt2x00dev, 12, 0x1c);
4349         rt2800_rfcsr_write(rt2x00dev, 13, 0x00);
4350         rt2800_rfcsr_write(rt2x00dev, 14, 0x5a);
4351         rt2800_rfcsr_write(rt2x00dev, 15, 0x00);
4352         rt2800_rfcsr_write(rt2x00dev, 16, 0x01);
4353         rt2800_rfcsr_write(rt2x00dev, 18, 0x45);
4354         rt2800_rfcsr_write(rt2x00dev, 19, 0x02);
4355         rt2800_rfcsr_write(rt2x00dev, 20, 0x00);
4356         rt2800_rfcsr_write(rt2x00dev, 21, 0x00);
4357         rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
4358         rt2800_rfcsr_write(rt2x00dev, 23, 0x00);
4359         rt2800_rfcsr_write(rt2x00dev, 24, 0x00);
4360         rt2800_rfcsr_write(rt2x00dev, 25, 0x80);
4361         rt2800_rfcsr_write(rt2x00dev, 26, 0x00);
4362         rt2800_rfcsr_write(rt2x00dev, 27, 0x03);
4363         rt2800_rfcsr_write(rt2x00dev, 28, 0x03);
4364         rt2800_rfcsr_write(rt2x00dev, 29, 0x00);
4365         rt2800_rfcsr_write(rt2x00dev, 30, 0x10);
4366         rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
4367         rt2800_rfcsr_write(rt2x00dev, 32, 0x80);
4368         rt2800_rfcsr_write(rt2x00dev, 33, 0x00);
4369         rt2800_rfcsr_write(rt2x00dev, 34, 0x01);
4370         rt2800_rfcsr_write(rt2x00dev, 35, 0x03);
4371         rt2800_rfcsr_write(rt2x00dev, 36, 0xbd);
4372         rt2800_rfcsr_write(rt2x00dev, 37, 0x3c);
4373         rt2800_rfcsr_write(rt2x00dev, 38, 0x5f);
4374         rt2800_rfcsr_write(rt2x00dev, 39, 0xc5);
4375         rt2800_rfcsr_write(rt2x00dev, 40, 0x33);
4376         rt2800_rfcsr_write(rt2x00dev, 41, 0x5b);
4377         rt2800_rfcsr_write(rt2x00dev, 42, 0x5b);
4378         rt2800_rfcsr_write(rt2x00dev, 43, 0xdb);
4379         rt2800_rfcsr_write(rt2x00dev, 44, 0xdb);
4380         rt2800_rfcsr_write(rt2x00dev, 45, 0xdb);
4381         rt2800_rfcsr_write(rt2x00dev, 46, 0xdd);
4382         rt2800_rfcsr_write(rt2x00dev, 47, 0x0d);
4383         rt2800_rfcsr_write(rt2x00dev, 48, 0x14);
4384         rt2800_rfcsr_write(rt2x00dev, 49, 0x00);
4385         rt2800_rfcsr_write(rt2x00dev, 50, 0x2d);
4386         rt2800_rfcsr_write(rt2x00dev, 51, 0x7f);
4387         rt2800_rfcsr_write(rt2x00dev, 52, 0x00);
4388         rt2800_rfcsr_write(rt2x00dev, 53, 0x52);
4389         rt2800_rfcsr_write(rt2x00dev, 54, 0x1b);
4390         rt2800_rfcsr_write(rt2x00dev, 55, 0x7f);
4391         rt2800_rfcsr_write(rt2x00dev, 56, 0x00);
4392         rt2800_rfcsr_write(rt2x00dev, 57, 0x52);
4393         rt2800_rfcsr_write(rt2x00dev, 58, 0x1b);
4394         rt2800_rfcsr_write(rt2x00dev, 59, 0x00);
4395         rt2800_rfcsr_write(rt2x00dev, 60, 0x00);
4396         rt2800_rfcsr_write(rt2x00dev, 61, 0x00);
4397         rt2800_rfcsr_write(rt2x00dev, 62, 0x00);
4398         rt2800_rfcsr_write(rt2x00dev, 63, 0x00);
4399 }
4400
4401 static void rt2800_init_rfcsr_3390(struct rt2x00_dev *rt2x00dev)
4402 {
4403         rt2800_rfcsr_write(rt2x00dev, 0, 0xa0);
4404         rt2800_rfcsr_write(rt2x00dev, 1, 0xe1);
4405         rt2800_rfcsr_write(rt2x00dev, 2, 0xf1);
4406         rt2800_rfcsr_write(rt2x00dev, 3, 0x62);
4407         rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
4408         rt2800_rfcsr_write(rt2x00dev, 5, 0x8b);
4409         rt2800_rfcsr_write(rt2x00dev, 6, 0x42);
4410         rt2800_rfcsr_write(rt2x00dev, 7, 0x34);
4411         rt2800_rfcsr_write(rt2x00dev, 8, 0x00);
4412         rt2800_rfcsr_write(rt2x00dev, 9, 0xc0);
4413         rt2800_rfcsr_write(rt2x00dev, 10, 0x61);
4414         rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
4415         rt2800_rfcsr_write(rt2x00dev, 12, 0x3b);
4416         rt2800_rfcsr_write(rt2x00dev, 13, 0xe0);
4417         rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
4418         rt2800_rfcsr_write(rt2x00dev, 15, 0x53);
4419         rt2800_rfcsr_write(rt2x00dev, 16, 0xe0);
4420         rt2800_rfcsr_write(rt2x00dev, 17, 0x94);
4421         rt2800_rfcsr_write(rt2x00dev, 18, 0x5c);
4422         rt2800_rfcsr_write(rt2x00dev, 19, 0x4a);
4423         rt2800_rfcsr_write(rt2x00dev, 20, 0xb2);
4424         rt2800_rfcsr_write(rt2x00dev, 21, 0xf6);
4425         rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
4426         rt2800_rfcsr_write(rt2x00dev, 23, 0x14);
4427         rt2800_rfcsr_write(rt2x00dev, 24, 0x08);
4428         rt2800_rfcsr_write(rt2x00dev, 25, 0x3d);
4429         rt2800_rfcsr_write(rt2x00dev, 26, 0x85);
4430         rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
4431         rt2800_rfcsr_write(rt2x00dev, 28, 0x41);
4432         rt2800_rfcsr_write(rt2x00dev, 29, 0x8f);
4433         rt2800_rfcsr_write(rt2x00dev, 30, 0x20);
4434         rt2800_rfcsr_write(rt2x00dev, 31, 0x0f);
4435 }
4436
4437 static void rt2800_init_rfcsr_3572(struct rt2x00_dev *rt2x00dev)
4438 {
4439         rt2800_rfcsr_write(rt2x00dev, 0, 0x70);
4440         rt2800_rfcsr_write(rt2x00dev, 1, 0x81);
4441         rt2800_rfcsr_write(rt2x00dev, 2, 0xf1);
4442         rt2800_rfcsr_write(rt2x00dev, 3, 0x02);
4443         rt2800_rfcsr_write(rt2x00dev, 4, 0x4c);
4444         rt2800_rfcsr_write(rt2x00dev, 5, 0x05);
4445         rt2800_rfcsr_write(rt2x00dev, 6, 0x4a);
4446         rt2800_rfcsr_write(rt2x00dev, 7, 0xd8);
4447         rt2800_rfcsr_write(rt2x00dev, 9, 0xc3);
4448         rt2800_rfcsr_write(rt2x00dev, 10, 0xf1);
4449         rt2800_rfcsr_write(rt2x00dev, 11, 0xb9);
4450         rt2800_rfcsr_write(rt2x00dev, 12, 0x70);
4451         rt2800_rfcsr_write(rt2x00dev, 13, 0x65);
4452         rt2800_rfcsr_write(rt2x00dev, 14, 0xa0);
4453         rt2800_rfcsr_write(rt2x00dev, 15, 0x53);
4454         rt2800_rfcsr_write(rt2x00dev, 16, 0x4c);
4455         rt2800_rfcsr_write(rt2x00dev, 17, 0x23);
4456         rt2800_rfcsr_write(rt2x00dev, 18, 0xac);
4457         rt2800_rfcsr_write(rt2x00dev, 19, 0x93);
4458         rt2800_rfcsr_write(rt2x00dev, 20, 0xb3);
4459         rt2800_rfcsr_write(rt2x00dev, 21, 0xd0);
4460         rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
4461         rt2800_rfcsr_write(rt2x00dev, 23, 0x3c);
4462         rt2800_rfcsr_write(rt2x00dev, 24, 0x16);
4463         rt2800_rfcsr_write(rt2x00dev, 25, 0x15);
4464         rt2800_rfcsr_write(rt2x00dev, 26, 0x85);
4465         rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
4466         rt2800_rfcsr_write(rt2x00dev, 28, 0x00);
4467         rt2800_rfcsr_write(rt2x00dev, 29, 0x9b);
4468         rt2800_rfcsr_write(rt2x00dev, 30, 0x09);
4469         rt2800_rfcsr_write(rt2x00dev, 31, 0x10);
4470 }
4471
4472 static void rt2800_init_rfcsr_5390(struct rt2x00_dev *rt2x00dev)
4473 {
4474         rt2800_rfcsr_write(rt2x00dev, 1, 0x0f);
4475         rt2800_rfcsr_write(rt2x00dev, 2, 0x80);
4476         rt2800_rfcsr_write(rt2x00dev, 3, 0x88);
4477         rt2800_rfcsr_write(rt2x00dev, 5, 0x10);
4478         if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
4479                 rt2800_rfcsr_write(rt2x00dev, 6, 0xe0);
4480         else
4481                 rt2800_rfcsr_write(rt2x00dev, 6, 0xa0);
4482         rt2800_rfcsr_write(rt2x00dev, 7, 0x00);
4483         rt2800_rfcsr_write(rt2x00dev, 10, 0x53);
4484         rt2800_rfcsr_write(rt2x00dev, 11, 0x4a);
4485         rt2800_rfcsr_write(rt2x00dev, 12, 0xc6);
4486         rt2800_rfcsr_write(rt2x00dev, 13, 0x9f);
4487         rt2800_rfcsr_write(rt2x00dev, 14, 0x00);
4488         rt2800_rfcsr_write(rt2x00dev, 15, 0x00);
4489         rt2800_rfcsr_write(rt2x00dev, 16, 0x00);
4490         rt2800_rfcsr_write(rt2x00dev, 18, 0x03);
4491         rt2800_rfcsr_write(rt2x00dev, 19, 0x00);
4492
4493         rt2800_rfcsr_write(rt2x00dev, 20, 0x00);
4494         rt2800_rfcsr_write(rt2x00dev, 21, 0x00);
4495         rt2800_rfcsr_write(rt2x00dev, 22, 0x20);
4496         rt2800_rfcsr_write(rt2x00dev, 23, 0x00);
4497         rt2800_rfcsr_write(rt2x00dev, 24, 0x00);
4498         if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
4499                 rt2800_rfcsr_write(rt2x00dev, 25, 0x80);
4500         else
4501                 rt2800_rfcsr_write(rt2x00dev, 25, 0xc0);
4502         rt2800_rfcsr_write(rt2x00dev, 26, 0x00);
4503         rt2800_rfcsr_write(rt2x00dev, 27, 0x09);
4504         rt2800_rfcsr_write(rt2x00dev, 28, 0x00);
4505         rt2800_rfcsr_write(rt2x00dev, 29, 0x10);
4506
4507         rt2800_rfcsr_write(rt2x00dev, 30, 0x00);
4508         rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
4509         rt2800_rfcsr_write(rt2x00dev, 32, 0x80);
4510         rt2800_rfcsr_write(rt2x00dev, 33, 0x00);
4511         rt2800_rfcsr_write(rt2x00dev, 34, 0x07);
4512         rt2800_rfcsr_write(rt2x00dev, 35, 0x12);
4513         rt2800_rfcsr_write(rt2x00dev, 36, 0x00);
4514         rt2800_rfcsr_write(rt2x00dev, 37, 0x08);
4515         rt2800_rfcsr_write(rt2x00dev, 38, 0x85);
4516         rt2800_rfcsr_write(rt2x00dev, 39, 0x1b);
4517
4518         if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
4519                 rt2800_rfcsr_write(rt2x00dev, 40, 0x0b);
4520         else
4521                 rt2800_rfcsr_write(rt2x00dev, 40, 0x4b);
4522         rt2800_rfcsr_write(rt2x00dev, 41, 0xbb);
4523         rt2800_rfcsr_write(rt2x00dev, 42, 0xd2);
4524         rt2800_rfcsr_write(rt2x00dev, 43, 0x9a);
4525         rt2800_rfcsr_write(rt2x00dev, 44, 0x0e);
4526         rt2800_rfcsr_write(rt2x00dev, 45, 0xa2);
4527         if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
4528                 rt2800_rfcsr_write(rt2x00dev, 46, 0x73);
4529         else
4530                 rt2800_rfcsr_write(rt2x00dev, 46, 0x7b);
4531         rt2800_rfcsr_write(rt2x00dev, 47, 0x00);
4532         rt2800_rfcsr_write(rt2x00dev, 48, 0x10);
4533         rt2800_rfcsr_write(rt2x00dev, 49, 0x94);
4534
4535         rt2800_rfcsr_write(rt2x00dev, 52, 0x38);
4536         if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
4537                 rt2800_rfcsr_write(rt2x00dev, 53, 0x00);
4538         else
4539                 rt2800_rfcsr_write(rt2x00dev, 53, 0x84);
4540         rt2800_rfcsr_write(rt2x00dev, 54, 0x78);
4541         rt2800_rfcsr_write(rt2x00dev, 55, 0x44);
4542         rt2800_rfcsr_write(rt2x00dev, 56, 0x22);
4543         rt2800_rfcsr_write(rt2x00dev, 57, 0x80);
4544         rt2800_rfcsr_write(rt2x00dev, 58, 0x7f);
4545         rt2800_rfcsr_write(rt2x00dev, 59, 0x63);
4546
4547         rt2800_rfcsr_write(rt2x00dev, 60, 0x45);
4548         if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
4549                 rt2800_rfcsr_write(rt2x00dev, 61, 0xd1);
4550         else
4551                 rt2800_rfcsr_write(rt2x00dev, 61, 0xdd);
4552         rt2800_rfcsr_write(rt2x00dev, 62, 0x00);
4553         rt2800_rfcsr_write(rt2x00dev, 63, 0x00);
4554 }
4555
4556 static void rt2800_init_rfcsr_5392(struct rt2x00_dev *rt2x00dev)
4557 {
4558         rt2800_rfcsr_write(rt2x00dev, 1, 0x17);
4559         rt2800_rfcsr_write(rt2x00dev, 2, 0x80);
4560         rt2800_rfcsr_write(rt2x00dev, 3, 0x88);
4561         rt2800_rfcsr_write(rt2x00dev, 5, 0x10);
4562         rt2800_rfcsr_write(rt2x00dev, 6, 0xe0);
4563         rt2800_rfcsr_write(rt2x00dev, 7, 0x00);
4564         rt2800_rfcsr_write(rt2x00dev, 10, 0x53);
4565         rt2800_rfcsr_write(rt2x00dev, 11, 0x4a);
4566         rt2800_rfcsr_write(rt2x00dev, 12, 0x46);
4567         rt2800_rfcsr_write(rt2x00dev, 13, 0x9f);
4568         rt2800_rfcsr_write(rt2x00dev, 14, 0x00);
4569         rt2800_rfcsr_write(rt2x00dev, 15, 0x00);
4570         rt2800_rfcsr_write(rt2x00dev, 16, 0x00);
4571         rt2800_rfcsr_write(rt2x00dev, 18, 0x03);
4572         rt2800_rfcsr_write(rt2x00dev, 19, 0x4d);
4573         rt2800_rfcsr_write(rt2x00dev, 20, 0x00);
4574         rt2800_rfcsr_write(rt2x00dev, 21, 0x8d);
4575         rt2800_rfcsr_write(rt2x00dev, 22, 0x20);
4576         rt2800_rfcsr_write(rt2x00dev, 23, 0x0b);
4577         rt2800_rfcsr_write(rt2x00dev, 24, 0x44);
4578         rt2800_rfcsr_write(rt2x00dev, 25, 0x80);
4579         rt2800_rfcsr_write(rt2x00dev, 26, 0x82);
4580         rt2800_rfcsr_write(rt2x00dev, 27, 0x09);
4581         rt2800_rfcsr_write(rt2x00dev, 28, 0x00);
4582         rt2800_rfcsr_write(rt2x00dev, 29, 0x10);
4583         rt2800_rfcsr_write(rt2x00dev, 30, 0x10);
4584         rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
4585         rt2800_rfcsr_write(rt2x00dev, 32, 0x20);
4586         rt2800_rfcsr_write(rt2x00dev, 33, 0xC0);
4587         rt2800_rfcsr_write(rt2x00dev, 34, 0x07);
4588         rt2800_rfcsr_write(rt2x00dev, 35, 0x12);
4589         rt2800_rfcsr_write(rt2x00dev, 36, 0x00);
4590         rt2800_rfcsr_write(rt2x00dev, 37, 0x08);
4591         rt2800_rfcsr_write(rt2x00dev, 38, 0x89);
4592         rt2800_rfcsr_write(rt2x00dev, 39, 0x1b);
4593         rt2800_rfcsr_write(rt2x00dev, 40, 0x0f);
4594         rt2800_rfcsr_write(rt2x00dev, 41, 0xbb);
4595         rt2800_rfcsr_write(rt2x00dev, 42, 0xd5);
4596         rt2800_rfcsr_write(rt2x00dev, 43, 0x9b);
4597         rt2800_rfcsr_write(rt2x00dev, 44, 0x0e);
4598         rt2800_rfcsr_write(rt2x00dev, 45, 0xa2);
4599         rt2800_rfcsr_write(rt2x00dev, 46, 0x73);
4600         rt2800_rfcsr_write(rt2x00dev, 47, 0x0c);
4601         rt2800_rfcsr_write(rt2x00dev, 48, 0x10);
4602         rt2800_rfcsr_write(rt2x00dev, 49, 0x94);
4603         rt2800_rfcsr_write(rt2x00dev, 50, 0x94);
4604         rt2800_rfcsr_write(rt2x00dev, 51, 0x3a);
4605         rt2800_rfcsr_write(rt2x00dev, 52, 0x48);
4606         rt2800_rfcsr_write(rt2x00dev, 53, 0x44);
4607         rt2800_rfcsr_write(rt2x00dev, 54, 0x38);
4608         rt2800_rfcsr_write(rt2x00dev, 55, 0x43);
4609         rt2800_rfcsr_write(rt2x00dev, 56, 0xa1);
4610         rt2800_rfcsr_write(rt2x00dev, 57, 0x00);
4611         rt2800_rfcsr_write(rt2x00dev, 58, 0x39);
4612         rt2800_rfcsr_write(rt2x00dev, 59, 0x07);
4613         rt2800_rfcsr_write(rt2x00dev, 60, 0x45);
4614         rt2800_rfcsr_write(rt2x00dev, 61, 0x91);
4615         rt2800_rfcsr_write(rt2x00dev, 62, 0x39);
4616         rt2800_rfcsr_write(rt2x00dev, 63, 0x07);
4617 }
4618
4619 static int rt2800_init_rfcsr(struct rt2x00_dev *rt2x00dev)
4620 {
4621         struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
4622         u8 rfcsr;
4623         u8 bbp;
4624         u32 reg;
4625         u16 eeprom;
4626
4627         if (!rt2x00_rt(rt2x00dev, RT3070) &&
4628             !rt2x00_rt(rt2x00dev, RT3071) &&
4629             !rt2x00_rt(rt2x00dev, RT3090) &&
4630             !rt2x00_rt(rt2x00dev, RT3290) &&
4631             !rt2x00_rt(rt2x00dev, RT3352) &&
4632             !rt2x00_rt(rt2x00dev, RT3390) &&
4633             !rt2x00_rt(rt2x00dev, RT3572) &&
4634             !rt2x00_rt(rt2x00dev, RT5390) &&
4635             !rt2x00_rt(rt2x00dev, RT5392) &&
4636             !rt2800_is_305x_soc(rt2x00dev))
4637                 return 0;
4638
4639         /*
4640          * Init RF calibration.
4641          */
4642
4643         if (rt2x00_rt(rt2x00dev, RT3290) ||
4644             rt2x00_rt(rt2x00dev, RT5390) ||
4645             rt2x00_rt(rt2x00dev, RT5392)) {
4646                 rt2800_rfcsr_read(rt2x00dev, 2, &rfcsr);
4647                 rt2x00_set_field8(&rfcsr, RFCSR2_RESCAL_EN, 1);
4648                 rt2800_rfcsr_write(rt2x00dev, 2, rfcsr);
4649                 msleep(1);
4650                 rt2x00_set_field8(&rfcsr, RFCSR2_RESCAL_EN, 0);
4651                 rt2800_rfcsr_write(rt2x00dev, 2, rfcsr);
4652         } else {
4653                 rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
4654                 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 1);
4655                 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
4656                 msleep(1);
4657                 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 0);
4658                 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
4659         }
4660
4661         if (rt2800_is_305x_soc(rt2x00dev)) {
4662                 rt2800_init_rfcsr_305x_soc(rt2x00dev);
4663                 return 0;
4664         }
4665
4666         switch (rt2x00dev->chip.rt) {
4667         case RT3070:
4668         case RT3071:
4669         case RT3090:
4670                 rt2800_init_rfcsr_30xx(rt2x00dev);
4671                 break;
4672         case RT3290:
4673                 rt2800_init_rfcsr_3290(rt2x00dev);
4674                 break;
4675         case RT3352:
4676                 rt2800_init_rfcsr_3352(rt2x00dev);
4677                 break;
4678         case RT3390:
4679                 rt2800_init_rfcsr_3390(rt2x00dev);
4680                 break;
4681         case RT3572:
4682                 rt2800_init_rfcsr_3572(rt2x00dev);
4683                 break;
4684         case RT5390:
4685                 rt2800_init_rfcsr_5390(rt2x00dev);
4686                 break;
4687         case RT5392:
4688                 rt2800_init_rfcsr_5392(rt2x00dev);
4689                 break;
4690         }
4691
4692         if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F)) {
4693                 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
4694                 rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
4695                 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 3);
4696                 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
4697         } else if (rt2x00_rt(rt2x00dev, RT3071) ||
4698                    rt2x00_rt(rt2x00dev, RT3090)) {
4699                 rt2800_rfcsr_write(rt2x00dev, 31, 0x14);
4700
4701                 rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
4702                 rt2x00_set_field8(&rfcsr, RFCSR6_R2, 1);
4703                 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
4704
4705                 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
4706                 rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
4707                 if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
4708                     rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E)) {
4709                         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
4710                         if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_DAC_TEST))
4711                                 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 3);
4712                         else
4713                                 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 0);
4714                 }
4715                 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
4716
4717                 rt2800_register_read(rt2x00dev, GPIO_SWITCH, &reg);
4718                 rt2x00_set_field32(&reg, GPIO_SWITCH_5, 0);
4719                 rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg);
4720         } else if (rt2x00_rt(rt2x00dev, RT3390)) {
4721                 rt2800_register_read(rt2x00dev, GPIO_SWITCH, &reg);
4722                 rt2x00_set_field32(&reg, GPIO_SWITCH_5, 0);
4723                 rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg);
4724         } else if (rt2x00_rt(rt2x00dev, RT3572)) {
4725                 rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
4726                 rt2x00_set_field8(&rfcsr, RFCSR6_R2, 1);
4727                 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
4728
4729                 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
4730                 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 3);
4731                 rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
4732                 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
4733                 msleep(1);
4734                 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
4735                 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 0);
4736                 rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
4737                 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
4738         }
4739
4740         /*
4741          * Set RX Filter calibration for 20MHz and 40MHz
4742          */
4743         if (rt2x00_rt(rt2x00dev, RT3070)) {
4744                 drv_data->calibration_bw20 =
4745                         rt2800_init_rx_filter(rt2x00dev, false, 0x07, 0x16);
4746                 drv_data->calibration_bw40 =
4747                         rt2800_init_rx_filter(rt2x00dev, true, 0x27, 0x19);
4748         } else if (rt2x00_rt(rt2x00dev, RT3071) ||
4749                    rt2x00_rt(rt2x00dev, RT3090) ||
4750                    rt2x00_rt(rt2x00dev, RT3352) ||
4751                    rt2x00_rt(rt2x00dev, RT3390) ||
4752                    rt2x00_rt(rt2x00dev, RT3572)) {
4753                 drv_data->calibration_bw20 =
4754                         rt2800_init_rx_filter(rt2x00dev, false, 0x07, 0x13);
4755                 drv_data->calibration_bw40 =
4756                         rt2800_init_rx_filter(rt2x00dev, true, 0x27, 0x15);
4757         }
4758
4759         /*
4760          * Save BBP 25 & 26 values for later use in channel switching
4761          */
4762         rt2800_bbp_read(rt2x00dev, 25, &drv_data->bbp25);
4763         rt2800_bbp_read(rt2x00dev, 26, &drv_data->bbp26);
4764
4765         if (!rt2x00_rt(rt2x00dev, RT5390) &&
4766             !rt2x00_rt(rt2x00dev, RT5392)) {
4767                 /*
4768                  * Set back to initial state
4769                  */
4770                 rt2800_bbp_write(rt2x00dev, 24, 0);
4771
4772                 rt2800_rfcsr_read(rt2x00dev, 22, &rfcsr);
4773                 rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 0);
4774                 rt2800_rfcsr_write(rt2x00dev, 22, rfcsr);
4775
4776                 /*
4777                  * Set BBP back to BW20
4778                  */
4779                 rt2800_bbp_read(rt2x00dev, 4, &bbp);
4780                 rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 0);
4781                 rt2800_bbp_write(rt2x00dev, 4, bbp);
4782         }
4783
4784         if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F) ||
4785             rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
4786             rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) ||
4787             rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E))
4788                 rt2800_rfcsr_write(rt2x00dev, 27, 0x03);
4789
4790         rt2800_register_read(rt2x00dev, OPT_14_CSR, &reg);
4791         rt2x00_set_field32(&reg, OPT_14_CSR_BIT0, 1);
4792         rt2800_register_write(rt2x00dev, OPT_14_CSR, reg);
4793
4794         if (!rt2x00_rt(rt2x00dev, RT5390) &&
4795             !rt2x00_rt(rt2x00dev, RT5392)) {
4796                 rt2800_rfcsr_read(rt2x00dev, 17, &rfcsr);
4797                 rt2x00_set_field8(&rfcsr, RFCSR17_TX_LO1_EN, 0);
4798                 if (rt2x00_rt(rt2x00dev, RT3070) ||
4799                     rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
4800                     rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) ||
4801                     rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E)) {
4802                         if (!test_bit(CAPABILITY_EXTERNAL_LNA_BG,
4803                                       &rt2x00dev->cap_flags))
4804                                 rt2x00_set_field8(&rfcsr, RFCSR17_R, 1);
4805                 }
4806                 rt2x00_set_field8(&rfcsr, RFCSR17_TXMIXER_GAIN,
4807                                   drv_data->txmixer_gain_24g);
4808                 rt2800_rfcsr_write(rt2x00dev, 17, rfcsr);
4809         }
4810
4811         if (rt2x00_rt(rt2x00dev, RT3090)) {
4812                 rt2800_bbp_read(rt2x00dev, 138, &bbp);
4813
4814                 /*  Turn off unused DAC1 and ADC1 to reduce power consumption */
4815                 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom);
4816                 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) == 1)
4817                         rt2x00_set_field8(&bbp, BBP138_RX_ADC1, 0);
4818                 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) == 1)
4819                         rt2x00_set_field8(&bbp, BBP138_TX_DAC1, 1);
4820
4821                 rt2800_bbp_write(rt2x00dev, 138, bbp);
4822         }
4823
4824         if (rt2x00_rt(rt2x00dev, RT3071) ||
4825             rt2x00_rt(rt2x00dev, RT3090) ||
4826             rt2x00_rt(rt2x00dev, RT3390)) {
4827                 rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
4828                 rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
4829                 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0);
4830                 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0);
4831                 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
4832                 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
4833                 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
4834
4835                 rt2800_rfcsr_read(rt2x00dev, 15, &rfcsr);
4836                 rt2x00_set_field8(&rfcsr, RFCSR15_TX_LO2_EN, 0);
4837                 rt2800_rfcsr_write(rt2x00dev, 15, rfcsr);
4838
4839                 rt2800_rfcsr_read(rt2x00dev, 20, &rfcsr);
4840                 rt2x00_set_field8(&rfcsr, RFCSR20_RX_LO1_EN, 0);
4841                 rt2800_rfcsr_write(rt2x00dev, 20, rfcsr);
4842
4843                 rt2800_rfcsr_read(rt2x00dev, 21, &rfcsr);
4844                 rt2x00_set_field8(&rfcsr, RFCSR21_RX_LO2_EN, 0);
4845                 rt2800_rfcsr_write(rt2x00dev, 21, rfcsr);
4846         }
4847
4848         if (rt2x00_rt(rt2x00dev, RT3070)) {
4849                 rt2800_rfcsr_read(rt2x00dev, 27, &rfcsr);
4850                 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F))
4851                         rt2x00_set_field8(&rfcsr, RFCSR27_R1, 3);
4852                 else
4853                         rt2x00_set_field8(&rfcsr, RFCSR27_R1, 0);
4854                 rt2x00_set_field8(&rfcsr, RFCSR27_R2, 0);
4855                 rt2x00_set_field8(&rfcsr, RFCSR27_R3, 0);
4856                 rt2x00_set_field8(&rfcsr, RFCSR27_R4, 0);
4857                 rt2800_rfcsr_write(rt2x00dev, 27, rfcsr);
4858         }
4859
4860         if (rt2x00_rt(rt2x00dev, RT3290)) {
4861                 rt2800_rfcsr_read(rt2x00dev, 29, &rfcsr);
4862                 rt2x00_set_field8(&rfcsr, RFCSR29_RSSI_GAIN, 3);
4863                 rt2800_rfcsr_write(rt2x00dev, 29, rfcsr);
4864         }
4865
4866         if (rt2x00_rt(rt2x00dev, RT5390) ||
4867             rt2x00_rt(rt2x00dev, RT5392)) {
4868                 rt2800_rfcsr_read(rt2x00dev, 38, &rfcsr);
4869                 rt2x00_set_field8(&rfcsr, RFCSR38_RX_LO1_EN, 0);
4870                 rt2800_rfcsr_write(rt2x00dev, 38, rfcsr);
4871
4872                 rt2800_rfcsr_read(rt2x00dev, 39, &rfcsr);
4873                 rt2x00_set_field8(&rfcsr, RFCSR39_RX_LO2_EN, 0);
4874                 rt2800_rfcsr_write(rt2x00dev, 39, rfcsr);
4875
4876                 rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
4877                 rt2x00_set_field8(&rfcsr, RFCSR30_RX_VCM, 2);
4878                 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
4879         }
4880
4881         return 0;
4882 }
4883
4884 int rt2800_enable_radio(struct rt2x00_dev *rt2x00dev)
4885 {
4886         u32 reg;
4887         u16 word;
4888
4889         /*
4890          * Initialize all registers.
4891          */
4892         if (unlikely(rt2800_wait_wpdma_ready(rt2x00dev) ||
4893                      rt2800_init_registers(rt2x00dev) ||
4894                      rt2800_init_bbp(rt2x00dev) ||
4895                      rt2800_init_rfcsr(rt2x00dev)))
4896                 return -EIO;
4897
4898         /*
4899          * Send signal to firmware during boot time.
4900          */
4901         rt2800_mcu_request(rt2x00dev, MCU_BOOT_SIGNAL, 0, 0, 0);
4902
4903         if (rt2x00_is_usb(rt2x00dev) &&
4904             (rt2x00_rt(rt2x00dev, RT3070) ||
4905              rt2x00_rt(rt2x00dev, RT3071) ||
4906              rt2x00_rt(rt2x00dev, RT3572))) {
4907                 udelay(200);
4908                 rt2800_mcu_request(rt2x00dev, MCU_CURRENT, 0, 0, 0);
4909                 udelay(10);
4910         }
4911
4912         /*
4913          * Enable RX.
4914          */
4915         rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
4916         rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 1);
4917         rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 0);
4918         rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
4919
4920         udelay(50);
4921
4922         rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
4923         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 1);
4924         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 1);
4925         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE, 2);
4926         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
4927         rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
4928
4929         rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
4930         rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 1);
4931         rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 1);
4932         rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
4933
4934         /*
4935          * Initialize LED control
4936          */
4937         rt2x00_eeprom_read(rt2x00dev, EEPROM_LED_AG_CONF, &word);
4938         rt2800_mcu_request(rt2x00dev, MCU_LED_AG_CONF, 0xff,
4939                            word & 0xff, (word >> 8) & 0xff);
4940
4941         rt2x00_eeprom_read(rt2x00dev, EEPROM_LED_ACT_CONF, &word);
4942         rt2800_mcu_request(rt2x00dev, MCU_LED_ACT_CONF, 0xff,
4943                            word & 0xff, (word >> 8) & 0xff);
4944
4945         rt2x00_eeprom_read(rt2x00dev, EEPROM_LED_POLARITY, &word);
4946         rt2800_mcu_request(rt2x00dev, MCU_LED_LED_POLARITY, 0xff,
4947                            word & 0xff, (word >> 8) & 0xff);
4948
4949         return 0;
4950 }
4951 EXPORT_SYMBOL_GPL(rt2800_enable_radio);
4952
4953 void rt2800_disable_radio(struct rt2x00_dev *rt2x00dev)
4954 {
4955         u32 reg;
4956
4957         rt2800_disable_wpdma(rt2x00dev);
4958
4959         /* Wait for DMA, ignore error */
4960         rt2800_wait_wpdma_ready(rt2x00dev);
4961
4962         rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
4963         rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 0);
4964         rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 0);
4965         rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
4966 }
4967 EXPORT_SYMBOL_GPL(rt2800_disable_radio);
4968
4969 int rt2800_efuse_detect(struct rt2x00_dev *rt2x00dev)
4970 {
4971         u32 reg;
4972         u16 efuse_ctrl_reg;
4973
4974         if (rt2x00_rt(rt2x00dev, RT3290))
4975                 efuse_ctrl_reg = EFUSE_CTRL_3290;
4976         else
4977                 efuse_ctrl_reg = EFUSE_CTRL;
4978
4979         rt2800_register_read(rt2x00dev, efuse_ctrl_reg, &reg);
4980         return rt2x00_get_field32(reg, EFUSE_CTRL_PRESENT);
4981 }
4982 EXPORT_SYMBOL_GPL(rt2800_efuse_detect);
4983
4984 static void rt2800_efuse_read(struct rt2x00_dev *rt2x00dev, unsigned int i)
4985 {
4986         u32 reg;
4987         u16 efuse_ctrl_reg;
4988         u16 efuse_data0_reg;
4989         u16 efuse_data1_reg;
4990         u16 efuse_data2_reg;
4991         u16 efuse_data3_reg;
4992
4993         if (rt2x00_rt(rt2x00dev, RT3290)) {
4994                 efuse_ctrl_reg = EFUSE_CTRL_3290;
4995                 efuse_data0_reg = EFUSE_DATA0_3290;
4996                 efuse_data1_reg = EFUSE_DATA1_3290;
4997                 efuse_data2_reg = EFUSE_DATA2_3290;
4998                 efuse_data3_reg = EFUSE_DATA3_3290;
4999         } else {
5000                 efuse_ctrl_reg = EFUSE_CTRL;
5001                 efuse_data0_reg = EFUSE_DATA0;
5002                 efuse_data1_reg = EFUSE_DATA1;
5003                 efuse_data2_reg = EFUSE_DATA2;
5004                 efuse_data3_reg = EFUSE_DATA3;
5005         }
5006         mutex_lock(&rt2x00dev->csr_mutex);
5007
5008         rt2800_register_read_lock(rt2x00dev, efuse_ctrl_reg, &reg);
5009         rt2x00_set_field32(&reg, EFUSE_CTRL_ADDRESS_IN, i);
5010         rt2x00_set_field32(&reg, EFUSE_CTRL_MODE, 0);
5011         rt2x00_set_field32(&reg, EFUSE_CTRL_KICK, 1);
5012         rt2800_register_write_lock(rt2x00dev, efuse_ctrl_reg, reg);
5013
5014         /* Wait until the EEPROM has been loaded */
5015         rt2800_regbusy_read(rt2x00dev, efuse_ctrl_reg, EFUSE_CTRL_KICK, &reg);
5016         /* Apparently the data is read from end to start */
5017         rt2800_register_read_lock(rt2x00dev, efuse_data3_reg, &reg);
5018         /* The returned value is in CPU order, but eeprom is le */
5019         *(u32 *)&rt2x00dev->eeprom[i] = cpu_to_le32(reg);
5020         rt2800_register_read_lock(rt2x00dev, efuse_data2_reg, &reg);
5021         *(u32 *)&rt2x00dev->eeprom[i + 2] = cpu_to_le32(reg);
5022         rt2800_register_read_lock(rt2x00dev, efuse_data1_reg, &reg);
5023         *(u32 *)&rt2x00dev->eeprom[i + 4] = cpu_to_le32(reg);
5024         rt2800_register_read_lock(rt2x00dev, efuse_data0_reg, &reg);
5025         *(u32 *)&rt2x00dev->eeprom[i + 6] = cpu_to_le32(reg);
5026
5027         mutex_unlock(&rt2x00dev->csr_mutex);
5028 }
5029
5030 int rt2800_read_eeprom_efuse(struct rt2x00_dev *rt2x00dev)
5031 {
5032         unsigned int i;
5033
5034         for (i = 0; i < EEPROM_SIZE / sizeof(u16); i += 8)
5035                 rt2800_efuse_read(rt2x00dev, i);
5036
5037         return 0;
5038 }
5039 EXPORT_SYMBOL_GPL(rt2800_read_eeprom_efuse);
5040
5041 static int rt2800_validate_eeprom(struct rt2x00_dev *rt2x00dev)
5042 {
5043         struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
5044         u16 word;
5045         u8 *mac;
5046         u8 default_lna_gain;
5047         int retval;
5048
5049         /*
5050          * Read the EEPROM.
5051          */
5052         retval = rt2800_read_eeprom(rt2x00dev);
5053         if (retval)
5054                 return retval;
5055
5056         /*
5057          * Start validation of the data that has been read.
5058          */
5059         mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
5060         if (!is_valid_ether_addr(mac)) {
5061                 eth_random_addr(mac);
5062                 EEPROM(rt2x00dev, "MAC: %pM\n", mac);
5063         }
5064
5065         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &word);
5066         if (word == 0xffff) {
5067                 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_RXPATH, 2);
5068                 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_TXPATH, 1);
5069                 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_RF_TYPE, RF2820);
5070                 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC_CONF0, word);
5071                 EEPROM(rt2x00dev, "Antenna: 0x%04x\n", word);
5072         } else if (rt2x00_rt(rt2x00dev, RT2860) ||
5073                    rt2x00_rt(rt2x00dev, RT2872)) {
5074                 /*
5075                  * There is a max of 2 RX streams for RT28x0 series
5076                  */
5077                 if (rt2x00_get_field16(word, EEPROM_NIC_CONF0_RXPATH) > 2)
5078                         rt2x00_set_field16(&word, EEPROM_NIC_CONF0_RXPATH, 2);
5079                 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC_CONF0, word);
5080         }
5081
5082         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &word);
5083         if (word == 0xffff) {
5084                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_HW_RADIO, 0);
5085                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_EXTERNAL_TX_ALC, 0);
5086                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_EXTERNAL_LNA_2G, 0);
5087                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_EXTERNAL_LNA_5G, 0);
5088                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_CARDBUS_ACCEL, 0);
5089                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_SB_2G, 0);
5090                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_SB_5G, 0);
5091                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_WPS_PBC, 0);
5092                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_2G, 0);
5093                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_5G, 0);
5094                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BROADBAND_EXT_LNA, 0);
5095                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_ANT_DIVERSITY, 0);
5096                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_INTERNAL_TX_ALC, 0);
5097                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BT_COEXIST, 0);
5098                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_DAC_TEST, 0);
5099                 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC_CONF1, word);
5100                 EEPROM(rt2x00dev, "NIC: 0x%04x\n", word);
5101         }
5102
5103         rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &word);
5104         if ((word & 0x00ff) == 0x00ff) {
5105                 rt2x00_set_field16(&word, EEPROM_FREQ_OFFSET, 0);
5106                 rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
5107                 EEPROM(rt2x00dev, "Freq: 0x%04x\n", word);
5108         }
5109         if ((word & 0xff00) == 0xff00) {
5110                 rt2x00_set_field16(&word, EEPROM_FREQ_LED_MODE,
5111                                    LED_MODE_TXRX_ACTIVITY);
5112                 rt2x00_set_field16(&word, EEPROM_FREQ_LED_POLARITY, 0);
5113                 rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
5114                 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED_AG_CONF, 0x5555);
5115                 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED_ACT_CONF, 0x2221);
5116                 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED_POLARITY, 0xa9f8);
5117                 EEPROM(rt2x00dev, "Led Mode: 0x%04x\n", word);
5118         }
5119
5120         /*
5121          * During the LNA validation we are going to use
5122          * lna0 as correct value. Note that EEPROM_LNA
5123          * is never validated.
5124          */
5125         rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &word);
5126         default_lna_gain = rt2x00_get_field16(word, EEPROM_LNA_A0);
5127
5128         rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG, &word);
5129         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET0)) > 10)
5130                 rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET0, 0);
5131         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET1)) > 10)
5132                 rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET1, 0);
5133         rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_BG, word);
5134
5135         rt2x00_eeprom_read(rt2x00dev, EEPROM_TXMIXER_GAIN_BG, &word);
5136         if ((word & 0x00ff) != 0x00ff) {
5137                 drv_data->txmixer_gain_24g =
5138                         rt2x00_get_field16(word, EEPROM_TXMIXER_GAIN_BG_VAL);
5139         } else {
5140                 drv_data->txmixer_gain_24g = 0;
5141         }
5142
5143         rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &word);
5144         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG2_OFFSET2)) > 10)
5145                 rt2x00_set_field16(&word, EEPROM_RSSI_BG2_OFFSET2, 0);
5146         if (rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0x00 ||
5147             rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0xff)
5148                 rt2x00_set_field16(&word, EEPROM_RSSI_BG2_LNA_A1,
5149                                    default_lna_gain);
5150         rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_BG2, word);
5151
5152         rt2x00_eeprom_read(rt2x00dev, EEPROM_TXMIXER_GAIN_A, &word);
5153         if ((word & 0x00ff) != 0x00ff) {
5154                 drv_data->txmixer_gain_5g =
5155                         rt2x00_get_field16(word, EEPROM_TXMIXER_GAIN_A_VAL);
5156         } else {
5157                 drv_data->txmixer_gain_5g = 0;
5158         }
5159
5160         rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A, &word);
5161         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET0)) > 10)
5162                 rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET0, 0);
5163         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET1)) > 10)
5164                 rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET1, 0);
5165         rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_A, word);
5166
5167         rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &word);
5168         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A2_OFFSET2)) > 10)
5169                 rt2x00_set_field16(&word, EEPROM_RSSI_A2_OFFSET2, 0);
5170         if (rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0x00 ||
5171             rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0xff)
5172                 rt2x00_set_field16(&word, EEPROM_RSSI_A2_LNA_A2,
5173                                    default_lna_gain);
5174         rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_A2, word);
5175
5176         return 0;
5177 }
5178
5179 static int rt2800_init_eeprom(struct rt2x00_dev *rt2x00dev)
5180 {
5181         u32 reg;
5182         u16 value;
5183         u16 eeprom;
5184
5185         /*
5186          * Read EEPROM word for configuration.
5187          */
5188         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom);
5189
5190         /*
5191          * Identify RF chipset by EEPROM value
5192          * RT28xx/RT30xx: defined in "EEPROM_NIC_CONF0_RF_TYPE" field
5193          * RT53xx: defined in "EEPROM_CHIP_ID" field
5194          */
5195         if (rt2x00_rt(rt2x00dev, RT3290))
5196                 rt2800_register_read(rt2x00dev, MAC_CSR0_3290, &reg);
5197         else
5198                 rt2800_register_read(rt2x00dev, MAC_CSR0, &reg);
5199
5200         if (rt2x00_get_field32(reg, MAC_CSR0_CHIPSET) == RT3290 ||
5201             rt2x00_get_field32(reg, MAC_CSR0_CHIPSET) == RT5390 ||
5202             rt2x00_get_field32(reg, MAC_CSR0_CHIPSET) == RT5392)
5203                 rt2x00_eeprom_read(rt2x00dev, EEPROM_CHIP_ID, &value);
5204         else
5205                 value = rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RF_TYPE);
5206
5207         rt2x00_set_chip(rt2x00dev, rt2x00_get_field32(reg, MAC_CSR0_CHIPSET),
5208                         value, rt2x00_get_field32(reg, MAC_CSR0_REVISION));
5209
5210         switch (rt2x00dev->chip.rt) {
5211         case RT2860:
5212         case RT2872:
5213         case RT2883:
5214         case RT3070:
5215         case RT3071:
5216         case RT3090:
5217         case RT3290:
5218         case RT3352:
5219         case RT3390:
5220         case RT3572:
5221         case RT5390:
5222         case RT5392:
5223         case RT5592:
5224                 break;
5225         default:
5226                 ERROR(rt2x00dev, "Invalid RT chipset 0x%04x detected.\n", rt2x00dev->chip.rt);
5227                 return -ENODEV;
5228         }
5229
5230         switch (rt2x00dev->chip.rf) {
5231         case RF2820:
5232         case RF2850:
5233         case RF2720:
5234         case RF2750:
5235         case RF3020:
5236         case RF2020:
5237         case RF3021:
5238         case RF3022:
5239         case RF3052:
5240         case RF3290:
5241         case RF3320:
5242         case RF3322:
5243         case RF5360:
5244         case RF5370:
5245         case RF5372:
5246         case RF5390:
5247         case RF5392:
5248         case RF5592:
5249                 break;
5250         default:
5251                 ERROR(rt2x00dev, "Invalid RF chipset 0x%04x detected.\n",
5252                       rt2x00dev->chip.rf);
5253                 return -ENODEV;
5254         }
5255
5256         /*
5257          * Identify default antenna configuration.
5258          */
5259         rt2x00dev->default_ant.tx_chain_num =
5260             rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH);
5261         rt2x00dev->default_ant.rx_chain_num =
5262             rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH);
5263
5264         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
5265
5266         if (rt2x00_rt(rt2x00dev, RT3070) ||
5267             rt2x00_rt(rt2x00dev, RT3090) ||
5268             rt2x00_rt(rt2x00dev, RT3352) ||
5269             rt2x00_rt(rt2x00dev, RT3390)) {
5270                 value = rt2x00_get_field16(eeprom,
5271                                 EEPROM_NIC_CONF1_ANT_DIVERSITY);
5272                 switch (value) {
5273                 case 0:
5274                 case 1:
5275                 case 2:
5276                         rt2x00dev->default_ant.tx = ANTENNA_A;
5277                         rt2x00dev->default_ant.rx = ANTENNA_A;
5278                         break;
5279                 case 3:
5280                         rt2x00dev->default_ant.tx = ANTENNA_A;
5281                         rt2x00dev->default_ant.rx = ANTENNA_B;
5282                         break;
5283                 }
5284         } else {
5285                 rt2x00dev->default_ant.tx = ANTENNA_A;
5286                 rt2x00dev->default_ant.rx = ANTENNA_A;
5287         }
5288
5289         if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390R)) {
5290                 rt2x00dev->default_ant.tx = ANTENNA_HW_DIVERSITY; /* Unused */
5291                 rt2x00dev->default_ant.rx = ANTENNA_HW_DIVERSITY; /* Unused */
5292         }
5293
5294         /*
5295          * Determine external LNA informations.
5296          */
5297         if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_EXTERNAL_LNA_5G))
5298                 __set_bit(CAPABILITY_EXTERNAL_LNA_A, &rt2x00dev->cap_flags);
5299         if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_EXTERNAL_LNA_2G))
5300                 __set_bit(CAPABILITY_EXTERNAL_LNA_BG, &rt2x00dev->cap_flags);
5301
5302         /*
5303          * Detect if this device has an hardware controlled radio.
5304          */
5305         if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_HW_RADIO))
5306                 __set_bit(CAPABILITY_HW_BUTTON, &rt2x00dev->cap_flags);
5307
5308         /*
5309          * Detect if this device has Bluetooth co-existence.
5310          */
5311         if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_BT_COEXIST))
5312                 __set_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags);
5313
5314         /*
5315          * Read frequency offset and RF programming sequence.
5316          */
5317         rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom);
5318         rt2x00dev->freq_offset = rt2x00_get_field16(eeprom, EEPROM_FREQ_OFFSET);
5319
5320         /*
5321          * Store led settings, for correct led behaviour.
5322          */
5323 #ifdef CONFIG_RT2X00_LIB_LEDS
5324         rt2800_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO);
5325         rt2800_init_led(rt2x00dev, &rt2x00dev->led_assoc, LED_TYPE_ASSOC);
5326         rt2800_init_led(rt2x00dev, &rt2x00dev->led_qual, LED_TYPE_QUALITY);
5327
5328         rt2x00dev->led_mcu_reg = eeprom;
5329 #endif /* CONFIG_RT2X00_LIB_LEDS */
5330
5331         /*
5332          * Check if support EIRP tx power limit feature.
5333          */
5334         rt2x00_eeprom_read(rt2x00dev, EEPROM_EIRP_MAX_TX_POWER, &eeprom);
5335
5336         if (rt2x00_get_field16(eeprom, EEPROM_EIRP_MAX_TX_POWER_2GHZ) <
5337                                         EIRP_MAX_TX_POWER_LIMIT)
5338                 __set_bit(CAPABILITY_POWER_LIMIT, &rt2x00dev->cap_flags);
5339
5340         return 0;
5341 }
5342
5343 /*
5344  * RF value list for rt28xx
5345  * Supports: 2.4 GHz (all) & 5.2 GHz (RF2850 & RF2750)
5346  */
5347 static const struct rf_channel rf_vals[] = {
5348         { 1,  0x18402ecc, 0x184c0786, 0x1816b455, 0x1800510b },
5349         { 2,  0x18402ecc, 0x184c0786, 0x18168a55, 0x1800519f },
5350         { 3,  0x18402ecc, 0x184c078a, 0x18168a55, 0x1800518b },
5351         { 4,  0x18402ecc, 0x184c078a, 0x18168a55, 0x1800519f },
5352         { 5,  0x18402ecc, 0x184c078e, 0x18168a55, 0x1800518b },
5353         { 6,  0x18402ecc, 0x184c078e, 0x18168a55, 0x1800519f },
5354         { 7,  0x18402ecc, 0x184c0792, 0x18168a55, 0x1800518b },
5355         { 8,  0x18402ecc, 0x184c0792, 0x18168a55, 0x1800519f },
5356         { 9,  0x18402ecc, 0x184c0796, 0x18168a55, 0x1800518b },
5357         { 10, 0x18402ecc, 0x184c0796, 0x18168a55, 0x1800519f },
5358         { 11, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800518b },
5359         { 12, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800519f },
5360         { 13, 0x18402ecc, 0x184c079e, 0x18168a55, 0x1800518b },
5361         { 14, 0x18402ecc, 0x184c07a2, 0x18168a55, 0x18005193 },
5362
5363         /* 802.11 UNI / HyperLan 2 */
5364         { 36, 0x18402ecc, 0x184c099a, 0x18158a55, 0x180ed1a3 },
5365         { 38, 0x18402ecc, 0x184c099e, 0x18158a55, 0x180ed193 },
5366         { 40, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed183 },
5367         { 44, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed1a3 },
5368         { 46, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed18b },
5369         { 48, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed19b },
5370         { 52, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed193 },
5371         { 54, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed1a3 },
5372         { 56, 0x18402ec8, 0x184c068e, 0x18158a55, 0x180ed18b },
5373         { 60, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed183 },
5374         { 62, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed193 },
5375         { 64, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed1a3 },
5376
5377         /* 802.11 HyperLan 2 */
5378         { 100, 0x18402ec8, 0x184c06b2, 0x18178a55, 0x180ed783 },
5379         { 102, 0x18402ec8, 0x184c06b2, 0x18578a55, 0x180ed793 },
5380         { 104, 0x18402ec8, 0x185c06b2, 0x18578a55, 0x180ed1a3 },
5381         { 108, 0x18402ecc, 0x185c0a32, 0x18578a55, 0x180ed193 },
5382         { 110, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed183 },
5383         { 112, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed19b },
5384         { 116, 0x18402ecc, 0x184c0a3a, 0x18178a55, 0x180ed1a3 },
5385         { 118, 0x18402ecc, 0x184c0a3e, 0x18178a55, 0x180ed193 },
5386         { 120, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed183 },
5387         { 124, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed193 },
5388         { 126, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed15b },
5389         { 128, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed1a3 },
5390         { 132, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed18b },
5391         { 134, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed193 },
5392         { 136, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed19b },
5393         { 140, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed183 },
5394
5395         /* 802.11 UNII */
5396         { 149, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed1a7 },
5397         { 151, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed187 },
5398         { 153, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed18f },
5399         { 157, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed19f },
5400         { 159, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed1a7 },
5401         { 161, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed187 },
5402         { 165, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed197 },
5403         { 167, 0x18402ec4, 0x184c03d2, 0x18179855, 0x1815531f },
5404         { 169, 0x18402ec4, 0x184c03d2, 0x18179855, 0x18155327 },
5405         { 171, 0x18402ec4, 0x184c03d6, 0x18179855, 0x18155307 },
5406         { 173, 0x18402ec4, 0x184c03d6, 0x18179855, 0x1815530f },
5407
5408         /* 802.11 Japan */
5409         { 184, 0x15002ccc, 0x1500491e, 0x1509be55, 0x150c0a0b },
5410         { 188, 0x15002ccc, 0x15004922, 0x1509be55, 0x150c0a13 },
5411         { 192, 0x15002ccc, 0x15004926, 0x1509be55, 0x150c0a1b },
5412         { 196, 0x15002ccc, 0x1500492a, 0x1509be55, 0x150c0a23 },
5413         { 208, 0x15002ccc, 0x1500493a, 0x1509be55, 0x150c0a13 },
5414         { 212, 0x15002ccc, 0x1500493e, 0x1509be55, 0x150c0a1b },
5415         { 216, 0x15002ccc, 0x15004982, 0x1509be55, 0x150c0a23 },
5416 };
5417
5418 /*
5419  * RF value list for rt3xxx
5420  * Supports: 2.4 GHz (all) & 5.2 GHz (RF3052)
5421  */
5422 static const struct rf_channel rf_vals_3x[] = {
5423         {1,  241, 2, 2 },
5424         {2,  241, 2, 7 },
5425         {3,  242, 2, 2 },
5426         {4,  242, 2, 7 },
5427         {5,  243, 2, 2 },
5428         {6,  243, 2, 7 },
5429         {7,  244, 2, 2 },
5430         {8,  244, 2, 7 },
5431         {9,  245, 2, 2 },
5432         {10, 245, 2, 7 },
5433         {11, 246, 2, 2 },
5434         {12, 246, 2, 7 },
5435         {13, 247, 2, 2 },
5436         {14, 248, 2, 4 },
5437
5438         /* 802.11 UNI / HyperLan 2 */
5439         {36, 0x56, 0, 4},
5440         {38, 0x56, 0, 6},
5441         {40, 0x56, 0, 8},
5442         {44, 0x57, 0, 0},
5443         {46, 0x57, 0, 2},
5444         {48, 0x57, 0, 4},
5445         {52, 0x57, 0, 8},
5446         {54, 0x57, 0, 10},
5447         {56, 0x58, 0, 0},
5448         {60, 0x58, 0, 4},
5449         {62, 0x58, 0, 6},
5450         {64, 0x58, 0, 8},
5451
5452         /* 802.11 HyperLan 2 */
5453         {100, 0x5b, 0, 8},
5454         {102, 0x5b, 0, 10},
5455         {104, 0x5c, 0, 0},
5456         {108, 0x5c, 0, 4},
5457         {110, 0x5c, 0, 6},
5458         {112, 0x5c, 0, 8},
5459         {116, 0x5d, 0, 0},
5460         {118, 0x5d, 0, 2},
5461         {120, 0x5d, 0, 4},
5462         {124, 0x5d, 0, 8},
5463         {126, 0x5d, 0, 10},
5464         {128, 0x5e, 0, 0},
5465         {132, 0x5e, 0, 4},
5466         {134, 0x5e, 0, 6},
5467         {136, 0x5e, 0, 8},
5468         {140, 0x5f, 0, 0},
5469
5470         /* 802.11 UNII */
5471         {149, 0x5f, 0, 9},
5472         {151, 0x5f, 0, 11},
5473         {153, 0x60, 0, 1},
5474         {157, 0x60, 0, 5},
5475         {159, 0x60, 0, 7},
5476         {161, 0x60, 0, 9},
5477         {165, 0x61, 0, 1},
5478         {167, 0x61, 0, 3},
5479         {169, 0x61, 0, 5},
5480         {171, 0x61, 0, 7},
5481         {173, 0x61, 0, 9},
5482 };
5483
5484 static const struct rf_channel rf_vals_5592_xtal20[] = {
5485         /* Channel, N, K, mod, R */
5486         {1, 482, 4, 10, 3},
5487         {2, 483, 4, 10, 3},
5488         {3, 484, 4, 10, 3},
5489         {4, 485, 4, 10, 3},
5490         {5, 486, 4, 10, 3},
5491         {6, 487, 4, 10, 3},
5492         {7, 488, 4, 10, 3},
5493         {8, 489, 4, 10, 3},
5494         {9, 490, 4, 10, 3},
5495         {10, 491, 4, 10, 3},
5496         {11, 492, 4, 10, 3},
5497         {12, 493, 4, 10, 3},
5498         {13, 494, 4, 10, 3},
5499         {14, 496, 8, 10, 3},
5500         {36, 172, 8, 12, 1},
5501         {38, 173, 0, 12, 1},
5502         {40, 173, 4, 12, 1},
5503         {42, 173, 8, 12, 1},
5504         {44, 174, 0, 12, 1},
5505         {46, 174, 4, 12, 1},
5506         {48, 174, 8, 12, 1},
5507         {50, 175, 0, 12, 1},
5508         {52, 175, 4, 12, 1},
5509         {54, 175, 8, 12, 1},
5510         {56, 176, 0, 12, 1},
5511         {58, 176, 4, 12, 1},
5512         {60, 176, 8, 12, 1},
5513         {62, 177, 0, 12, 1},
5514         {64, 177, 4, 12, 1},
5515         {100, 183, 4, 12, 1},
5516         {102, 183, 8, 12, 1},
5517         {104, 184, 0, 12, 1},
5518         {106, 184, 4, 12, 1},
5519         {108, 184, 8, 12, 1},
5520         {110, 185, 0, 12, 1},
5521         {112, 185, 4, 12, 1},
5522         {114, 185, 8, 12, 1},
5523         {116, 186, 0, 12, 1},
5524         {118, 186, 4, 12, 1},
5525         {120, 186, 8, 12, 1},
5526         {122, 187, 0, 12, 1},
5527         {124, 187, 4, 12, 1},
5528         {126, 187, 8, 12, 1},
5529         {128, 188, 0, 12, 1},
5530         {130, 188, 4, 12, 1},
5531         {132, 188, 8, 12, 1},
5532         {134, 189, 0, 12, 1},
5533         {136, 189, 4, 12, 1},
5534         {138, 189, 8, 12, 1},
5535         {140, 190, 0, 12, 1},
5536         {149, 191, 6, 12, 1},
5537         {151, 191, 10, 12, 1},
5538         {153, 192, 2, 12, 1},
5539         {155, 192, 6, 12, 1},
5540         {157, 192, 10, 12, 1},
5541         {159, 193, 2, 12, 1},
5542         {161, 193, 6, 12, 1},
5543         {165, 194, 2, 12, 1},
5544         {184, 164, 0, 12, 1},
5545         {188, 164, 4, 12, 1},
5546         {192, 165, 8, 12, 1},
5547         {196, 166, 0, 12, 1},
5548 };
5549
5550 static const struct rf_channel rf_vals_5592_xtal40[] = {
5551         /* Channel, N, K, mod, R */
5552         {1, 241, 2, 10, 3},
5553         {2, 241, 7, 10, 3},
5554         {3, 242, 2, 10, 3},
5555         {4, 242, 7, 10, 3},
5556         {5, 243, 2, 10, 3},
5557         {6, 243, 7, 10, 3},
5558         {7, 244, 2, 10, 3},
5559         {8, 244, 7, 10, 3},
5560         {9, 245, 2, 10, 3},
5561         {10, 245, 7, 10, 3},
5562         {11, 246, 2, 10, 3},
5563         {12, 246, 7, 10, 3},
5564         {13, 247, 2, 10, 3},
5565         {14, 248, 4, 10, 3},
5566         {36, 86, 4, 12, 1},
5567         {38, 86, 6, 12, 1},
5568         {40, 86, 8, 12, 1},
5569         {42, 86, 10, 12, 1},
5570         {44, 87, 0, 12, 1},
5571         {46, 87, 2, 12, 1},
5572         {48, 87, 4, 12, 1},
5573         {50, 87, 6, 12, 1},
5574         {52, 87, 8, 12, 1},
5575         {54, 87, 10, 12, 1},
5576         {56, 88, 0, 12, 1},
5577         {58, 88, 2, 12, 1},
5578         {60, 88, 4, 12, 1},
5579         {62, 88, 6, 12, 1},
5580         {64, 88, 8, 12, 1},
5581         {100, 91, 8, 12, 1},
5582         {102, 91, 10, 12, 1},
5583         {104, 92, 0, 12, 1},
5584         {106, 92, 2, 12, 1},
5585         {108, 92, 4, 12, 1},
5586         {110, 92, 6, 12, 1},
5587         {112, 92, 8, 12, 1},
5588         {114, 92, 10, 12, 1},
5589         {116, 93, 0, 12, 1},
5590         {118, 93, 2, 12, 1},
5591         {120, 93, 4, 12, 1},
5592         {122, 93, 6, 12, 1},
5593         {124, 93, 8, 12, 1},
5594         {126, 93, 10, 12, 1},
5595         {128, 94, 0, 12, 1},
5596         {130, 94, 2, 12, 1},
5597         {132, 94, 4, 12, 1},
5598         {134, 94, 6, 12, 1},
5599         {136, 94, 8, 12, 1},
5600         {138, 94, 10, 12, 1},
5601         {140, 95, 0, 12, 1},
5602         {149, 95, 9, 12, 1},
5603         {151, 95, 11, 12, 1},
5604         {153, 96, 1, 12, 1},
5605         {155, 96, 3, 12, 1},
5606         {157, 96, 5, 12, 1},
5607         {159, 96, 7, 12, 1},
5608         {161, 96, 9, 12, 1},
5609         {165, 97, 1, 12, 1},
5610         {184, 82, 0, 12, 1},
5611         {188, 82, 4, 12, 1},
5612         {192, 82, 8, 12, 1},
5613         {196, 83, 0, 12, 1},
5614 };
5615
5616 static int rt2800_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
5617 {
5618         struct hw_mode_spec *spec = &rt2x00dev->spec;
5619         struct channel_info *info;
5620         char *default_power1;
5621         char *default_power2;
5622         unsigned int i;
5623         u16 eeprom;
5624         u32 reg;
5625
5626         /*
5627          * Disable powersaving as default on PCI devices.
5628          */
5629         if (rt2x00_is_pci(rt2x00dev) || rt2x00_is_soc(rt2x00dev))
5630                 rt2x00dev->hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
5631
5632         /*
5633          * Initialize all hw fields.
5634          */
5635         rt2x00dev->hw->flags =
5636             IEEE80211_HW_SIGNAL_DBM |
5637             IEEE80211_HW_SUPPORTS_PS |
5638             IEEE80211_HW_PS_NULLFUNC_STACK |
5639             IEEE80211_HW_AMPDU_AGGREGATION |
5640             IEEE80211_HW_REPORTS_TX_ACK_STATUS;
5641
5642         /*
5643          * Don't set IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING for USB devices
5644          * unless we are capable of sending the buffered frames out after the
5645          * DTIM transmission using rt2x00lib_beacondone. This will send out
5646          * multicast and broadcast traffic immediately instead of buffering it
5647          * infinitly and thus dropping it after some time.
5648          */
5649         if (!rt2x00_is_usb(rt2x00dev))
5650                 rt2x00dev->hw->flags |=
5651                         IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING;
5652
5653         SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev);
5654         SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
5655                                 rt2x00_eeprom_addr(rt2x00dev,
5656                                                    EEPROM_MAC_ADDR_0));
5657
5658         /*
5659          * As rt2800 has a global fallback table we cannot specify
5660          * more then one tx rate per frame but since the hw will
5661          * try several rates (based on the fallback table) we should
5662          * initialize max_report_rates to the maximum number of rates
5663          * we are going to try. Otherwise mac80211 will truncate our
5664          * reported tx rates and the rc algortihm will end up with
5665          * incorrect data.
5666          */
5667         rt2x00dev->hw->max_rates = 1;
5668         rt2x00dev->hw->max_report_rates = 7;
5669         rt2x00dev->hw->max_rate_tries = 1;
5670
5671         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom);
5672
5673         /*
5674          * Initialize hw_mode information.
5675          */
5676         spec->supported_bands = SUPPORT_BAND_2GHZ;
5677         spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM;
5678
5679         if (rt2x00_rf(rt2x00dev, RF2820) ||
5680             rt2x00_rf(rt2x00dev, RF2720)) {
5681                 spec->num_channels = 14;
5682                 spec->channels = rf_vals;
5683         } else if (rt2x00_rf(rt2x00dev, RF2850) ||
5684                    rt2x00_rf(rt2x00dev, RF2750)) {
5685                 spec->supported_bands |= SUPPORT_BAND_5GHZ;
5686                 spec->num_channels = ARRAY_SIZE(rf_vals);
5687                 spec->channels = rf_vals;
5688         } else if (rt2x00_rf(rt2x00dev, RF3020) ||
5689                    rt2x00_rf(rt2x00dev, RF2020) ||
5690                    rt2x00_rf(rt2x00dev, RF3021) ||
5691                    rt2x00_rf(rt2x00dev, RF3022) ||
5692                    rt2x00_rf(rt2x00dev, RF3290) ||
5693                    rt2x00_rf(rt2x00dev, RF3320) ||
5694                    rt2x00_rf(rt2x00dev, RF3322) ||
5695                    rt2x00_rf(rt2x00dev, RF5360) ||
5696                    rt2x00_rf(rt2x00dev, RF5370) ||
5697                    rt2x00_rf(rt2x00dev, RF5372) ||
5698                    rt2x00_rf(rt2x00dev, RF5390) ||
5699                    rt2x00_rf(rt2x00dev, RF5392)) {
5700                 spec->num_channels = 14;
5701                 spec->channels = rf_vals_3x;
5702         } else if (rt2x00_rf(rt2x00dev, RF3052)) {
5703                 spec->supported_bands |= SUPPORT_BAND_5GHZ;
5704                 spec->num_channels = ARRAY_SIZE(rf_vals_3x);
5705                 spec->channels = rf_vals_3x;
5706         } else if (rt2x00_rf(rt2x00dev, RF5592)) {
5707                 spec->supported_bands |= SUPPORT_BAND_5GHZ;
5708
5709                 rt2800_register_read(rt2x00dev, MAC_DEBUG_INDEX, &reg);
5710                 if (rt2x00_get_field32(reg, MAC_DEBUG_INDEX_XTAL)) {
5711                         spec->num_channels = ARRAY_SIZE(rf_vals_5592_xtal40);
5712                         spec->channels = rf_vals_5592_xtal40;
5713                 } else {
5714                         spec->num_channels = ARRAY_SIZE(rf_vals_5592_xtal20);
5715                         spec->channels = rf_vals_5592_xtal20;
5716                 }
5717         }
5718
5719         if (WARN_ON_ONCE(!spec->channels))
5720                 return -ENODEV;
5721
5722         /*
5723          * Initialize HT information.
5724          */
5725         if (!rt2x00_rf(rt2x00dev, RF2020))
5726                 spec->ht.ht_supported = true;
5727         else
5728                 spec->ht.ht_supported = false;
5729
5730         spec->ht.cap =
5731             IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
5732             IEEE80211_HT_CAP_GRN_FLD |
5733             IEEE80211_HT_CAP_SGI_20 |
5734             IEEE80211_HT_CAP_SGI_40;
5735
5736         if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) >= 2)
5737                 spec->ht.cap |= IEEE80211_HT_CAP_TX_STBC;
5738
5739         spec->ht.cap |=
5740             rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) <<
5741                 IEEE80211_HT_CAP_RX_STBC_SHIFT;
5742
5743         spec->ht.ampdu_factor = 3;
5744         spec->ht.ampdu_density = 4;
5745         spec->ht.mcs.tx_params =
5746             IEEE80211_HT_MCS_TX_DEFINED |
5747             IEEE80211_HT_MCS_TX_RX_DIFF |
5748             ((rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) - 1) <<
5749                 IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT);
5750
5751         switch (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH)) {
5752         case 3:
5753                 spec->ht.mcs.rx_mask[2] = 0xff;
5754         case 2:
5755                 spec->ht.mcs.rx_mask[1] = 0xff;
5756         case 1:
5757                 spec->ht.mcs.rx_mask[0] = 0xff;
5758                 spec->ht.mcs.rx_mask[4] = 0x1; /* MCS32 */
5759                 break;
5760         }
5761
5762         /*
5763          * Create channel information array
5764          */
5765         info = kcalloc(spec->num_channels, sizeof(*info), GFP_KERNEL);
5766         if (!info)
5767                 return -ENOMEM;
5768
5769         spec->channels_info = info;
5770
5771         default_power1 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG1);
5772         default_power2 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG2);
5773
5774         for (i = 0; i < 14; i++) {
5775                 info[i].default_power1 = default_power1[i];
5776                 info[i].default_power2 = default_power2[i];
5777         }
5778
5779         if (spec->num_channels > 14) {
5780                 default_power1 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A1);
5781                 default_power2 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A2);
5782
5783                 for (i = 14; i < spec->num_channels; i++) {
5784                         info[i].default_power1 = default_power1[i];
5785                         info[i].default_power2 = default_power2[i];
5786                 }
5787         }
5788
5789         switch (rt2x00dev->chip.rf) {
5790         case RF2020:
5791         case RF3020:
5792         case RF3021:
5793         case RF3022:
5794         case RF3320:
5795         case RF3052:
5796         case RF3290:
5797         case RF5360:
5798         case RF5370:
5799         case RF5372:
5800         case RF5390:
5801         case RF5392:
5802                 __set_bit(CAPABILITY_VCO_RECALIBRATION, &rt2x00dev->cap_flags);
5803                 break;
5804         }
5805
5806         return 0;
5807 }
5808
5809 int rt2800_probe_hw(struct rt2x00_dev *rt2x00dev)
5810 {
5811         int retval;
5812         u32 reg;
5813
5814         /*
5815          * Allocate eeprom data.
5816          */
5817         retval = rt2800_validate_eeprom(rt2x00dev);
5818         if (retval)
5819                 return retval;
5820
5821         retval = rt2800_init_eeprom(rt2x00dev);
5822         if (retval)
5823                 return retval;
5824
5825         /*
5826          * Enable rfkill polling by setting GPIO direction of the
5827          * rfkill switch GPIO pin correctly.
5828          */
5829         rt2800_register_read(rt2x00dev, GPIO_CTRL, &reg);
5830         rt2x00_set_field32(&reg, GPIO_CTRL_DIR2, 1);
5831         rt2800_register_write(rt2x00dev, GPIO_CTRL, reg);
5832
5833         /*
5834          * Initialize hw specifications.
5835          */
5836         retval = rt2800_probe_hw_mode(rt2x00dev);
5837         if (retval)
5838                 return retval;
5839
5840         /*
5841          * Set device capabilities.
5842          */
5843         __set_bit(CAPABILITY_CONTROL_FILTERS, &rt2x00dev->cap_flags);
5844         __set_bit(CAPABILITY_CONTROL_FILTER_PSPOLL, &rt2x00dev->cap_flags);
5845         if (!rt2x00_is_usb(rt2x00dev))
5846                 __set_bit(CAPABILITY_PRE_TBTT_INTERRUPT, &rt2x00dev->cap_flags);
5847
5848         /*
5849          * Set device requirements.
5850          */
5851         if (!rt2x00_is_soc(rt2x00dev))
5852                 __set_bit(REQUIRE_FIRMWARE, &rt2x00dev->cap_flags);
5853         __set_bit(REQUIRE_L2PAD, &rt2x00dev->cap_flags);
5854         __set_bit(REQUIRE_TXSTATUS_FIFO, &rt2x00dev->cap_flags);
5855         if (!rt2800_hwcrypt_disabled(rt2x00dev))
5856                 __set_bit(CAPABILITY_HW_CRYPTO, &rt2x00dev->cap_flags);
5857         __set_bit(CAPABILITY_LINK_TUNING, &rt2x00dev->cap_flags);
5858         __set_bit(REQUIRE_HT_TX_DESC, &rt2x00dev->cap_flags);
5859         if (rt2x00_is_usb(rt2x00dev))
5860                 __set_bit(REQUIRE_PS_AUTOWAKE, &rt2x00dev->cap_flags);
5861         else {
5862                 __set_bit(REQUIRE_DMA, &rt2x00dev->cap_flags);
5863                 __set_bit(REQUIRE_TASKLET_CONTEXT, &rt2x00dev->cap_flags);
5864         }
5865
5866         /*
5867          * Set the rssi offset.
5868          */
5869         rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
5870
5871         return 0;
5872 }
5873 EXPORT_SYMBOL_GPL(rt2800_probe_hw);
5874
5875 /*
5876  * IEEE80211 stack callback functions.
5877  */
5878 void rt2800_get_tkip_seq(struct ieee80211_hw *hw, u8 hw_key_idx, u32 *iv32,
5879                          u16 *iv16)
5880 {
5881         struct rt2x00_dev *rt2x00dev = hw->priv;
5882         struct mac_iveiv_entry iveiv_entry;
5883         u32 offset;
5884
5885         offset = MAC_IVEIV_ENTRY(hw_key_idx);
5886         rt2800_register_multiread(rt2x00dev, offset,
5887                                       &iveiv_entry, sizeof(iveiv_entry));
5888
5889         memcpy(iv16, &iveiv_entry.iv[0], sizeof(*iv16));
5890         memcpy(iv32, &iveiv_entry.iv[4], sizeof(*iv32));
5891 }
5892 EXPORT_SYMBOL_GPL(rt2800_get_tkip_seq);
5893
5894 int rt2800_set_rts_threshold(struct ieee80211_hw *hw, u32 value)
5895 {
5896         struct rt2x00_dev *rt2x00dev = hw->priv;
5897         u32 reg;
5898         bool enabled = (value < IEEE80211_MAX_RTS_THRESHOLD);
5899
5900         rt2800_register_read(rt2x00dev, TX_RTS_CFG, &reg);
5901         rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_THRES, value);
5902         rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg);
5903
5904         rt2800_register_read(rt2x00dev, CCK_PROT_CFG, &reg);
5905         rt2x00_set_field32(&reg, CCK_PROT_CFG_RTS_TH_EN, enabled);
5906         rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg);
5907
5908         rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
5909         rt2x00_set_field32(&reg, OFDM_PROT_CFG_RTS_TH_EN, enabled);
5910         rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
5911
5912         rt2800_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
5913         rt2x00_set_field32(&reg, MM20_PROT_CFG_RTS_TH_EN, enabled);
5914         rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
5915
5916         rt2800_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
5917         rt2x00_set_field32(&reg, MM40_PROT_CFG_RTS_TH_EN, enabled);
5918         rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
5919
5920         rt2800_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
5921         rt2x00_set_field32(&reg, GF20_PROT_CFG_RTS_TH_EN, enabled);
5922         rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
5923
5924         rt2800_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
5925         rt2x00_set_field32(&reg, GF40_PROT_CFG_RTS_TH_EN, enabled);
5926         rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
5927
5928         return 0;
5929 }
5930 EXPORT_SYMBOL_GPL(rt2800_set_rts_threshold);
5931
5932 int rt2800_conf_tx(struct ieee80211_hw *hw,
5933                    struct ieee80211_vif *vif, u16 queue_idx,
5934                    const struct ieee80211_tx_queue_params *params)
5935 {
5936         struct rt2x00_dev *rt2x00dev = hw->priv;
5937         struct data_queue *queue;
5938         struct rt2x00_field32 field;
5939         int retval;
5940         u32 reg;
5941         u32 offset;
5942
5943         /*
5944          * First pass the configuration through rt2x00lib, that will
5945          * update the queue settings and validate the input. After that
5946          * we are free to update the registers based on the value
5947          * in the queue parameter.
5948          */
5949         retval = rt2x00mac_conf_tx(hw, vif, queue_idx, params);
5950         if (retval)
5951                 return retval;
5952
5953         /*
5954          * We only need to perform additional register initialization
5955          * for WMM queues/
5956          */
5957         if (queue_idx >= 4)
5958                 return 0;
5959
5960         queue = rt2x00queue_get_tx_queue(rt2x00dev, queue_idx);
5961
5962         /* Update WMM TXOP register */
5963         offset = WMM_TXOP0_CFG + (sizeof(u32) * (!!(queue_idx & 2)));
5964         field.bit_offset = (queue_idx & 1) * 16;
5965         field.bit_mask = 0xffff << field.bit_offset;
5966
5967         rt2800_register_read(rt2x00dev, offset, &reg);
5968         rt2x00_set_field32(&reg, field, queue->txop);
5969         rt2800_register_write(rt2x00dev, offset, reg);
5970
5971         /* Update WMM registers */
5972         field.bit_offset = queue_idx * 4;
5973         field.bit_mask = 0xf << field.bit_offset;
5974
5975         rt2800_register_read(rt2x00dev, WMM_AIFSN_CFG, &reg);
5976         rt2x00_set_field32(&reg, field, queue->aifs);
5977         rt2800_register_write(rt2x00dev, WMM_AIFSN_CFG, reg);
5978
5979         rt2800_register_read(rt2x00dev, WMM_CWMIN_CFG, &reg);
5980         rt2x00_set_field32(&reg, field, queue->cw_min);
5981         rt2800_register_write(rt2x00dev, WMM_CWMIN_CFG, reg);
5982
5983         rt2800_register_read(rt2x00dev, WMM_CWMAX_CFG, &reg);
5984         rt2x00_set_field32(&reg, field, queue->cw_max);
5985         rt2800_register_write(rt2x00dev, WMM_CWMAX_CFG, reg);
5986
5987         /* Update EDCA registers */
5988         offset = EDCA_AC0_CFG + (sizeof(u32) * queue_idx);
5989
5990         rt2800_register_read(rt2x00dev, offset, &reg);
5991         rt2x00_set_field32(&reg, EDCA_AC0_CFG_TX_OP, queue->txop);
5992         rt2x00_set_field32(&reg, EDCA_AC0_CFG_AIFSN, queue->aifs);
5993         rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMIN, queue->cw_min);
5994         rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMAX, queue->cw_max);
5995         rt2800_register_write(rt2x00dev, offset, reg);
5996
5997         return 0;
5998 }
5999 EXPORT_SYMBOL_GPL(rt2800_conf_tx);
6000
6001 u64 rt2800_get_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
6002 {
6003         struct rt2x00_dev *rt2x00dev = hw->priv;
6004         u64 tsf;
6005         u32 reg;
6006
6007         rt2800_register_read(rt2x00dev, TSF_TIMER_DW1, &reg);
6008         tsf = (u64) rt2x00_get_field32(reg, TSF_TIMER_DW1_HIGH_WORD) << 32;
6009         rt2800_register_read(rt2x00dev, TSF_TIMER_DW0, &reg);
6010         tsf |= rt2x00_get_field32(reg, TSF_TIMER_DW0_LOW_WORD);
6011
6012         return tsf;
6013 }
6014 EXPORT_SYMBOL_GPL(rt2800_get_tsf);
6015
6016 int rt2800_ampdu_action(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
6017                         enum ieee80211_ampdu_mlme_action action,
6018                         struct ieee80211_sta *sta, u16 tid, u16 *ssn,
6019                         u8 buf_size)
6020 {
6021         struct rt2x00_sta *sta_priv = (struct rt2x00_sta *)sta->drv_priv;
6022         int ret = 0;
6023
6024         /*
6025          * Don't allow aggregation for stations the hardware isn't aware
6026          * of because tx status reports for frames to an unknown station
6027          * always contain wcid=255 and thus we can't distinguish between
6028          * multiple stations which leads to unwanted situations when the
6029          * hw reorders frames due to aggregation.
6030          */
6031         if (sta_priv->wcid < 0)
6032                 return 1;
6033
6034         switch (action) {
6035         case IEEE80211_AMPDU_RX_START:
6036         case IEEE80211_AMPDU_RX_STOP:
6037                 /*
6038                  * The hw itself takes care of setting up BlockAck mechanisms.
6039                  * So, we only have to allow mac80211 to nagotiate a BlockAck
6040                  * agreement. Once that is done, the hw will BlockAck incoming
6041                  * AMPDUs without further setup.
6042                  */
6043                 break;
6044         case IEEE80211_AMPDU_TX_START:
6045                 ieee80211_start_tx_ba_cb_irqsafe(vif, sta->addr, tid);
6046                 break;
6047         case IEEE80211_AMPDU_TX_STOP_CONT:
6048         case IEEE80211_AMPDU_TX_STOP_FLUSH:
6049         case IEEE80211_AMPDU_TX_STOP_FLUSH_CONT:
6050                 ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid);
6051                 break;
6052         case IEEE80211_AMPDU_TX_OPERATIONAL:
6053                 break;
6054         default:
6055                 WARNING((struct rt2x00_dev *)hw->priv, "Unknown AMPDU action\n");
6056         }
6057
6058         return ret;
6059 }
6060 EXPORT_SYMBOL_GPL(rt2800_ampdu_action);
6061
6062 int rt2800_get_survey(struct ieee80211_hw *hw, int idx,
6063                       struct survey_info *survey)
6064 {
6065         struct rt2x00_dev *rt2x00dev = hw->priv;
6066         struct ieee80211_conf *conf = &hw->conf;
6067         u32 idle, busy, busy_ext;
6068
6069         if (idx != 0)
6070                 return -ENOENT;
6071
6072         survey->channel = conf->channel;
6073
6074         rt2800_register_read(rt2x00dev, CH_IDLE_STA, &idle);
6075         rt2800_register_read(rt2x00dev, CH_BUSY_STA, &busy);
6076         rt2800_register_read(rt2x00dev, CH_BUSY_STA_SEC, &busy_ext);
6077
6078         if (idle || busy) {
6079                 survey->filled = SURVEY_INFO_CHANNEL_TIME |
6080                                  SURVEY_INFO_CHANNEL_TIME_BUSY |
6081                                  SURVEY_INFO_CHANNEL_TIME_EXT_BUSY;
6082
6083                 survey->channel_time = (idle + busy) / 1000;
6084                 survey->channel_time_busy = busy / 1000;
6085                 survey->channel_time_ext_busy = busy_ext / 1000;
6086         }
6087
6088         if (!(hw->conf.flags & IEEE80211_CONF_OFFCHANNEL))
6089                 survey->filled |= SURVEY_INFO_IN_USE;
6090
6091         return 0;
6092
6093 }
6094 EXPORT_SYMBOL_GPL(rt2800_get_survey);
6095
6096 MODULE_AUTHOR(DRV_PROJECT ", Bartlomiej Zolnierkiewicz");
6097 MODULE_VERSION(DRV_VERSION);
6098 MODULE_DESCRIPTION("Ralink RT2800 library");
6099 MODULE_LICENSE("GPL");