drivers/net/wireless/rt2x00/rt2800lib.c

   1 /*
   2         Copyright (C) 2010 Willow Garage <http://www.willowgarage.com>
   3         Copyright (C) 2010 Ivo van Doorn <IvDoorn@gmail.com>
   4         Copyright (C) 2009 Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>
   5         Copyright (C) 2009 Gertjan van Wingerde <gwingerde@gmail.com>
   6
   7         Based on the original rt2800pci.c and rt2800usb.c.
   8           Copyright (C) 2009 Alban Browaeys <prahal@yahoo.com>
   9           Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org>
  10           Copyright (C) 2009 Luis Correia <luis.f.correia@gmail.com>
  11           Copyright (C) 2009 Mattias Nissler <mattias.nissler@gmx.de>
  12           Copyright (C) 2009 Mark Asselstine <asselsm@gmail.com>
  13           Copyright (C) 2009 Xose Vazquez Perez <xose.vazquez@gmail.com>
  14           <http://rt2x00.serialmonkey.com>
  15
  16         This program is free software; you can redistribute it and/or modify
  17         it under the terms of the GNU General Public License as published by
  18         the Free Software Foundation; either version 2 of the License, or
  19         (at your option) any later version.
  20
  21         This program is distributed in the hope that it will be useful,
  22         but WITHOUT ANY WARRANTY; without even the implied warranty of
  23         MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  24         GNU General Public License for more details.
  25
  26         You should have received a copy of the GNU General Public License
  27         along with this program; if not, write to the
  28         Free Software Foundation, Inc.,
  29         59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  30  */
  31
  32 /*
  33         Module: rt2800lib
  34         Abstract: rt2800 generic device routines.
  35  */
  36
  37 #include <linux/crc-ccitt.h>
  38 #include <linux/kernel.h>
  39 #include <linux/module.h>
  40 #include <linux/slab.h>
  41
  42 #include "rt2x00.h"
  43 #include "rt2800lib.h"
  44 #include "rt2800.h"
  45
  46 /*
  47  * Register access.
  48  * All access to the CSR registers will go through the methods
  49  * rt2800_register_read and rt2800_register_write.
  50  * BBP and RF register require indirect register access,
  51  * and use the CSR registers BBPCSR and RFCSR to achieve this.
  52  * These indirect registers work with busy bits,
  53  * and we will try maximal REGISTER_BUSY_COUNT times to access
  54  * the register while taking a REGISTER_BUSY_DELAY us delay
  55  * between each attampt. When the busy bit is still set at that time,
  56  * the access attempt is considered to have failed,
  57  * and we will print an error.
  58  * The _lock versions must be used if you already hold the csr_mutex
  59  */
  60 #define WAIT_FOR_BBP(__dev, __reg) \
  61         rt2800_regbusy_read((__dev), BBP_CSR_CFG, BBP_CSR_CFG_BUSY, (__reg))
  62 #define WAIT_FOR_RFCSR(__dev, __reg) \
  63         rt2800_regbusy_read((__dev), RF_CSR_CFG, RF_CSR_CFG_BUSY, (__reg))
  64 #define WAIT_FOR_RF(__dev, __reg) \
  65         rt2800_regbusy_read((__dev), RF_CSR_CFG0, RF_CSR_CFG0_BUSY, (__reg))
  66 #define WAIT_FOR_MCU(__dev, __reg) \
  67         rt2800_regbusy_read((__dev), H2M_MAILBOX_CSR, \
  68                             H2M_MAILBOX_CSR_OWNER, (__reg))
  69
  70 static inline bool rt2800_is_305x_soc(struct rt2x00_dev *rt2x00dev)
  71 {
  72         /* check for rt2872 on SoC */
  73         if (!rt2x00_is_soc(rt2x00dev) ||
  74             !rt2x00_rt(rt2x00dev, RT2872))
  75                 return false;
  76
  77         /* we know for sure that these rf chipsets are used on rt305x boards */
  78         if (rt2x00_rf(rt2x00dev, RF3020) ||
  79             rt2x00_rf(rt2x00dev, RF3021) ||
  80             rt2x00_rf(rt2x00dev, RF3022))
  81                 return true;
  82
  83         rt2x00_warn(rt2x00dev, "Unknown RF chipset on rt305x\n");
  84         return false;
  85 }
  86
  87 static void rt2800_bbp_write(struct rt2x00_dev *rt2x00dev,
  88                              const unsigned int word, const u8 value)
  89 {
  90         u32 reg;
  91
  92         mutex_lock(&rt2x00dev->csr_mutex);
  93
  94         /*
  95          * Wait until the BBP becomes available, afterwards we
  96          * can safely write the new data into the register.
  97          */
  98         if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
  99                 reg = 0;
 100                 rt2x00_set_field32(&reg, BBP_CSR_CFG_VALUE, value);
 101                 rt2x00_set_field32(&reg, BBP_CSR_CFG_REGNUM, word);
 102                 rt2x00_set_field32(&reg, BBP_CSR_CFG_BUSY, 1);
 103                 rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 0);
 104                 rt2x00_set_field32(&reg, BBP_CSR_CFG_BBP_RW_MODE, 1);
 105
 106                 rt2800_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg);
 107         }
 108
 109         mutex_unlock(&rt2x00dev->csr_mutex);
 110 }
 111
 112 static void rt2800_bbp_read(struct rt2x00_dev *rt2x00dev,
 113                             const unsigned int word, u8 *value)
 114 {
 115         u32 reg;
 116
 117         mutex_lock(&rt2x00dev->csr_mutex);
 118
 119         /*
 120          * Wait until the BBP becomes available, afterwards we
 121          * can safely write the read request into the register.
 122          * After the data has been written, we wait until hardware
 123          * returns the correct value, if at any time the register
 124          * doesn't become available in time, reg will be 0xffffffff
 125          * which means we return 0xff to the caller.
 126          */
 127         if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
 128                 reg = 0;
 129                 rt2x00_set_field32(&reg, BBP_CSR_CFG_REGNUM, word);
 130                 rt2x00_set_field32(&reg, BBP_CSR_CFG_BUSY, 1);
 131                 rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 1);
 132                 rt2x00_set_field32(&reg, BBP_CSR_CFG_BBP_RW_MODE, 1);
 133
 134                 rt2800_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg);
 135
 136                 WAIT_FOR_BBP(rt2x00dev, &reg);
 137         }
 138
 139         *value = rt2x00_get_field32(reg, BBP_CSR_CFG_VALUE);
 140
 141         mutex_unlock(&rt2x00dev->csr_mutex);
 142 }
 143
 144 static void rt2800_rfcsr_write(struct rt2x00_dev *rt2x00dev,
 145                                const unsigned int word, const u8 value)
 146 {
 147         u32 reg;
 148
 149         mutex_lock(&rt2x00dev->csr_mutex);
 150
 151         /*
 152          * Wait until the RFCSR becomes available, afterwards we
 153          * can safely write the new data into the register.
 154          */
 155         if (WAIT_FOR_RFCSR(rt2x00dev, &reg)) {
 156                 reg = 0;
 157                 rt2x00_set_field32(&reg, RF_CSR_CFG_DATA, value);
 158                 rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM, word);
 159                 rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE, 1);
 160                 rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY, 1);
 161
 162                 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
 163         }
 164
 165         mutex_unlock(&rt2x00dev->csr_mutex);
 166 }
 167
 168 static void rt2800_rfcsr_read(struct rt2x00_dev *rt2x00dev,
 169                               const unsigned int word, u8 *value)
 170 {
 171         u32 reg;
 172
 173         mutex_lock(&rt2x00dev->csr_mutex);
 174
 175         /*
 176          * Wait until the RFCSR becomes available, afterwards we
 177          * can safely write the read request into the register.
 178          * After the data has been written, we wait until hardware
 179          * returns the correct value, if at any time the register
 180          * doesn't become available in time, reg will be 0xffffffff
 181          * which means we return 0xff to the caller.
 182          */
 183         if (WAIT_FOR_RFCSR(rt2x00dev, &reg)) {
 184                 reg = 0;
 185                 rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM, word);
 186                 rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE, 0);
 187                 rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY, 1);
 188
 189                 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
 190
 191                 WAIT_FOR_RFCSR(rt2x00dev, &reg);
 192         }
 193
 194         *value = rt2x00_get_field32(reg, RF_CSR_CFG_DATA);
 195
 196         mutex_unlock(&rt2x00dev->csr_mutex);
 197 }
 198
 199 static void rt2800_rf_write(struct rt2x00_dev *rt2x00dev,
 200                             const unsigned int word, const u32 value)
 201 {
 202         u32 reg;
 203
 204         mutex_lock(&rt2x00dev->csr_mutex);
 205
 206         /*
 207          * Wait until the RF becomes available, afterwards we
 208          * can safely write the new data into the register.
 209          */
 210         if (WAIT_FOR_RF(rt2x00dev, &reg)) {
 211                 reg = 0;
 212                 rt2x00_set_field32(&reg, RF_CSR_CFG0_REG_VALUE_BW, value);
 213                 rt2x00_set_field32(&reg, RF_CSR_CFG0_STANDBYMODE, 0);
 214                 rt2x00_set_field32(&reg, RF_CSR_CFG0_SEL, 0);
 215                 rt2x00_set_field32(&reg, RF_CSR_CFG0_BUSY, 1);
 216
 217                 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG0, reg);
 218                 rt2x00_rf_write(rt2x00dev, word, value);
 219         }
 220
 221         mutex_unlock(&rt2x00dev->csr_mutex);
 222 }
 223
 224 static const unsigned int rt2800_eeprom_map[EEPROM_WORD_COUNT] = {
 225         [EEPROM_CHIP_ID]                = 0x0000,
 226         [EEPROM_VERSION]                = 0x0001,
 227         [EEPROM_MAC_ADDR_0]             = 0x0002,
 228         [EEPROM_MAC_ADDR_1]             = 0x0003,
 229         [EEPROM_MAC_ADDR_2]             = 0x0004,
 230         [EEPROM_NIC_CONF0]              = 0x001a,
 231         [EEPROM_NIC_CONF1]              = 0x001b,
 232         [EEPROM_FREQ]                   = 0x001d,
 233         [EEPROM_LED_AG_CONF]            = 0x001e,
 234         [EEPROM_LED_ACT_CONF]           = 0x001f,
 235         [EEPROM_LED_POLARITY]           = 0x0020,
 236         [EEPROM_NIC_CONF2]              = 0x0021,
 237         [EEPROM_LNA]                    = 0x0022,
 238         [EEPROM_RSSI_BG]                = 0x0023,
 239         [EEPROM_RSSI_BG2]               = 0x0024,
 240         [EEPROM_TXMIXER_GAIN_BG]        = 0x0024, /* overlaps with RSSI_BG2 */
 241         [EEPROM_RSSI_A]                 = 0x0025,
 242         [EEPROM_RSSI_A2]                = 0x0026,
 243         [EEPROM_TXMIXER_GAIN_A]         = 0x0026, /* overlaps with RSSI_A2 */
 244         [EEPROM_EIRP_MAX_TX_POWER]      = 0x0027,
 245         [EEPROM_TXPOWER_DELTA]          = 0x0028,
 246         [EEPROM_TXPOWER_BG1]            = 0x0029,
 247         [EEPROM_TXPOWER_BG2]            = 0x0030,
 248         [EEPROM_TSSI_BOUND_BG1]         = 0x0037,
 249         [EEPROM_TSSI_BOUND_BG2]         = 0x0038,
 250         [EEPROM_TSSI_BOUND_BG3]         = 0x0039,
 251         [EEPROM_TSSI_BOUND_BG4]         = 0x003a,
 252         [EEPROM_TSSI_BOUND_BG5]         = 0x003b,
 253         [EEPROM_TXPOWER_A1]             = 0x003c,
 254         [EEPROM_TXPOWER_A2]             = 0x0053,
 255         [EEPROM_TSSI_BOUND_A1]          = 0x006a,
 256         [EEPROM_TSSI_BOUND_A2]          = 0x006b,
 257         [EEPROM_TSSI_BOUND_A3]          = 0x006c,
 258         [EEPROM_TSSI_BOUND_A4]          = 0x006d,
 259         [EEPROM_TSSI_BOUND_A5]          = 0x006e,
 260         [EEPROM_TXPOWER_BYRATE]         = 0x006f,
 261         [EEPROM_BBP_START]              = 0x0078,
 262 };
 263
 264 static const unsigned int rt2800_eeprom_map_ext[EEPROM_WORD_COUNT] = {
 265         [EEPROM_CHIP_ID]                = 0x0000,
 266         [EEPROM_VERSION]                = 0x0001,
 267         [EEPROM_MAC_ADDR_0]             = 0x0002,
 268         [EEPROM_MAC_ADDR_1]             = 0x0003,
 269         [EEPROM_MAC_ADDR_2]             = 0x0004,
 270         [EEPROM_NIC_CONF0]              = 0x001a,
 271         [EEPROM_NIC_CONF1]              = 0x001b,
 272         [EEPROM_NIC_CONF2]              = 0x001c,
 273         [EEPROM_EIRP_MAX_TX_POWER]      = 0x0020,
 274         [EEPROM_FREQ]                   = 0x0022,
 275         [EEPROM_LED_AG_CONF]            = 0x0023,
 276         [EEPROM_LED_ACT_CONF]           = 0x0024,
 277         [EEPROM_LED_POLARITY]           = 0x0025,
 278         [EEPROM_LNA]                    = 0x0026,
 279         [EEPROM_EXT_LNA2]               = 0x0027,
 280         [EEPROM_RSSI_BG]                = 0x0028,
 281         [EEPROM_RSSI_BG2]               = 0x0029,
 282         [EEPROM_RSSI_A]                 = 0x002a,
 283         [EEPROM_RSSI_A2]                = 0x002b,
 284         [EEPROM_TXPOWER_BG1]            = 0x0030,
 285         [EEPROM_TXPOWER_BG2]            = 0x0037,
 286         [EEPROM_EXT_TXPOWER_BG3]        = 0x003e,
 287         [EEPROM_TSSI_BOUND_BG1]         = 0x0045,
 288         [EEPROM_TSSI_BOUND_BG2]         = 0x0046,
 289         [EEPROM_TSSI_BOUND_BG3]         = 0x0047,
 290         [EEPROM_TSSI_BOUND_BG4]         = 0x0048,
 291         [EEPROM_TSSI_BOUND_BG5]         = 0x0049,
 292         [EEPROM_TXPOWER_A1]             = 0x004b,
 293         [EEPROM_TXPOWER_A2]             = 0x0065,
 294         [EEPROM_EXT_TXPOWER_A3]         = 0x007f,
 295         [EEPROM_TSSI_BOUND_A1]          = 0x009a,
 296         [EEPROM_TSSI_BOUND_A2]          = 0x009b,
 297         [EEPROM_TSSI_BOUND_A3]          = 0x009c,
 298         [EEPROM_TSSI_BOUND_A4]          = 0x009d,
 299         [EEPROM_TSSI_BOUND_A5]          = 0x009e,
 300         [EEPROM_TXPOWER_BYRATE]         = 0x00a0,
 301 };
 302
 303 static unsigned int rt2800_eeprom_word_index(struct rt2x00_dev *rt2x00dev,
 304                                              const enum rt2800_eeprom_word word)
 305 {
 306         const unsigned int *map;
 307         unsigned int index;
 308
 309         if (WARN_ONCE(word >= EEPROM_WORD_COUNT,
 310                       "%s: invalid EEPROM word %d\n",
 311                       wiphy_name(rt2x00dev->hw->wiphy), word))
 312                 return 0;
 313
 314         if (rt2x00_rt(rt2x00dev, RT3593))
 315                 map = rt2800_eeprom_map_ext;
 316         else
 317                 map = rt2800_eeprom_map;
 318
 319         index = map[word];
 320
 321         /* Index 0 is valid only for EEPROM_CHIP_ID.
 322          * Otherwise it means that the offset of the
 323          * given word is not initialized in the map,
 324          * or that the field is not usable on the
 325          * actual chipset.
 326          */
 327         WARN_ONCE(word != EEPROM_CHIP_ID && index == 0,
 328                   "%s: invalid access of EEPROM word %d\n",
 329                   wiphy_name(rt2x00dev->hw->wiphy), word);
 330
 331         return index;
 332 }
 333
 334 static void *rt2800_eeprom_addr(struct rt2x00_dev *rt2x00dev,
 335                                 const enum rt2800_eeprom_word word)
 336 {
 337         unsigned int index;
 338
 339         index = rt2800_eeprom_word_index(rt2x00dev, word);
 340         return rt2x00_eeprom_addr(rt2x00dev, index);
 341 }
 342
 343 static void rt2800_eeprom_read(struct rt2x00_dev *rt2x00dev,
 344                                const enum rt2800_eeprom_word word, u16 *data)
 345 {
 346         unsigned int index;
 347
 348         index = rt2800_eeprom_word_index(rt2x00dev, word);
 349         rt2x00_eeprom_read(rt2x00dev, index, data);
 350 }
 351
 352 static void rt2800_eeprom_write(struct rt2x00_dev *rt2x00dev,
 353                                 const enum rt2800_eeprom_word word, u16 data)
 354 {
 355         unsigned int index;
 356
 357         index = rt2800_eeprom_word_index(rt2x00dev, word);
 358         rt2x00_eeprom_write(rt2x00dev, index, data);
 359 }
 360
 361 static void rt2800_eeprom_read_from_array(struct rt2x00_dev *rt2x00dev,
 362                                           const enum rt2800_eeprom_word array,
 363                                           unsigned int offset,
 364                                           u16 *data)
 365 {
 366         unsigned int index;
 367
 368         index = rt2800_eeprom_word_index(rt2x00dev, array);
 369         rt2x00_eeprom_read(rt2x00dev, index + offset, data);
 370 }
 371
 372 static int rt2800_enable_wlan_rt3290(struct rt2x00_dev *rt2x00dev)
 373 {
 374         u32 reg;
 375         int i, count;
 376
 377         rt2800_register_read(rt2x00dev, WLAN_FUN_CTRL, &reg);
 378         if (rt2x00_get_field32(reg, WLAN_EN))
 379                 return 0;
 380
 381         rt2x00_set_field32(&reg, WLAN_GPIO_OUT_OE_BIT_ALL, 0xff);
 382         rt2x00_set_field32(&reg, FRC_WL_ANT_SET, 1);
 383         rt2x00_set_field32(&reg, WLAN_CLK_EN, 0);
 384         rt2x00_set_field32(&reg, WLAN_EN, 1);
 385         rt2800_register_write(rt2x00dev, WLAN_FUN_CTRL, reg);
 386
 387         udelay(REGISTER_BUSY_DELAY);
 388
 389         count = 0;
 390         do {
 391                 /*
 392                  * Check PLL_LD & XTAL_RDY.
 393                  */
 394                 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
 395                         rt2800_register_read(rt2x00dev, CMB_CTRL, &reg);
 396                         if (rt2x00_get_field32(reg, PLL_LD) &&
 397                             rt2x00_get_field32(reg, XTAL_RDY))
 398                                 break;
 399                         udelay(REGISTER_BUSY_DELAY);
 400                 }
 401
 402                 if (i >= REGISTER_BUSY_COUNT) {
 403
 404                         if (count >= 10)
 405                                 return -EIO;
 406
 407                         rt2800_register_write(rt2x00dev, 0x58, 0x018);
 408                         udelay(REGISTER_BUSY_DELAY);
 409                         rt2800_register_write(rt2x00dev, 0x58, 0x418);
 410                         udelay(REGISTER_BUSY_DELAY);
 411                         rt2800_register_write(rt2x00dev, 0x58, 0x618);
 412                         udelay(REGISTER_BUSY_DELAY);
 413                         count++;
 414                 } else {
 415                         count = 0;
 416                 }
 417
 418                 rt2800_register_read(rt2x00dev, WLAN_FUN_CTRL, &reg);
 419                 rt2x00_set_field32(&reg, PCIE_APP0_CLK_REQ, 0);
 420                 rt2x00_set_field32(&reg, WLAN_CLK_EN, 1);
 421                 rt2x00_set_field32(&reg, WLAN_RESET, 1);
 422                 rt2800_register_write(rt2x00dev, WLAN_FUN_CTRL, reg);
 423                 udelay(10);
 424                 rt2x00_set_field32(&reg, WLAN_RESET, 0);
 425                 rt2800_register_write(rt2x00dev, WLAN_FUN_CTRL, reg);
 426                 udelay(10);
 427                 rt2800_register_write(rt2x00dev, INT_SOURCE_CSR, 0x7fffffff);
 428         } while (count != 0);
 429
 430         return 0;
 431 }
 432
 433 void rt2800_mcu_request(struct rt2x00_dev *rt2x00dev,
 434                         const u8 command, const u8 token,
 435                         const u8 arg0, const u8 arg1)
 436 {
 437         u32 reg;
 438
 439         /*
 440          * SOC devices don't support MCU requests.
 441          */
 442         if (rt2x00_is_soc(rt2x00dev))
 443                 return;
 444
 445         mutex_lock(&rt2x00dev->csr_mutex);
 446
 447         /*
 448          * Wait until the MCU becomes available, afterwards we
 449          * can safely write the new data into the register.
 450          */
 451         if (WAIT_FOR_MCU(rt2x00dev, &reg)) {
 452                 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_OWNER, 1);
 453                 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_CMD_TOKEN, token);
 454                 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG0, arg0);
 455                 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG1, arg1);
 456                 rt2800_register_write_lock(rt2x00dev, H2M_MAILBOX_CSR, reg);
 457
 458                 reg = 0;
 459                 rt2x00_set_field32(&reg, HOST_CMD_CSR_HOST_COMMAND, command);
 460                 rt2800_register_write_lock(rt2x00dev, HOST_CMD_CSR, reg);
 461         }
 462
 463         mutex_unlock(&rt2x00dev->csr_mutex);
 464 }
 465 EXPORT_SYMBOL_GPL(rt2800_mcu_request);
 466
 467 int rt2800_wait_csr_ready(struct rt2x00_dev *rt2x00dev)
 468 {
 469         unsigned int i = 0;
 470         u32 reg;
 471
 472         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
 473                 rt2800_register_read(rt2x00dev, MAC_CSR0, &reg);
 474                 if (reg && reg != ~0)
 475                         return 0;
 476                 msleep(1);
 477         }
 478
 479         rt2x00_err(rt2x00dev, "Unstable hardware\n");
 480         return -EBUSY;
 481 }
 482 EXPORT_SYMBOL_GPL(rt2800_wait_csr_ready);
 483
 484 int rt2800_wait_wpdma_ready(struct rt2x00_dev *rt2x00dev)
 485 {
 486         unsigned int i;
 487         u32 reg;
 488
 489         /*
 490          * Some devices are really slow to respond here. Wait a whole second
 491          * before timing out.
 492          */
 493         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
 494                 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
 495                 if (!rt2x00_get_field32(reg, WPDMA_GLO_CFG_TX_DMA_BUSY) &&
 496                     !rt2x00_get_field32(reg, WPDMA_GLO_CFG_RX_DMA_BUSY))
 497                         return 0;
 498
 499                 msleep(10);
 500         }
 501
 502         rt2x00_err(rt2x00dev, "WPDMA TX/RX busy [0x%08x]\n", reg);
 503         return -EACCES;
 504 }
 505 EXPORT_SYMBOL_GPL(rt2800_wait_wpdma_ready);
 506
 507 void rt2800_disable_wpdma(struct rt2x00_dev *rt2x00dev)
 508 {
 509         u32 reg;
 510
 511         rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
 512         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
 513         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
 514         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
 515         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
 516         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
 517         rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
 518 }
 519 EXPORT_SYMBOL_GPL(rt2800_disable_wpdma);
 520
 521 void rt2800_get_txwi_rxwi_size(struct rt2x00_dev *rt2x00dev,
 522                                unsigned short *txwi_size,
 523                                unsigned short *rxwi_size)
 524 {
 525         switch (rt2x00dev->chip.rt) {
 526         case RT3593:
 527                 *txwi_size = TXWI_DESC_SIZE_4WORDS;
 528                 *rxwi_size = RXWI_DESC_SIZE_5WORDS;
 529                 break;
 530
 531         case RT5592:
 532                 *txwi_size = TXWI_DESC_SIZE_5WORDS;
 533                 *rxwi_size = RXWI_DESC_SIZE_6WORDS;
 534                 break;
 535
 536         default:
 537                 *txwi_size = TXWI_DESC_SIZE_4WORDS;
 538                 *rxwi_size = RXWI_DESC_SIZE_4WORDS;
 539                 break;
 540         }
 541 }
 542 EXPORT_SYMBOL_GPL(rt2800_get_txwi_rxwi_size);
 543
 544 static bool rt2800_check_firmware_crc(const u8 *data, const size_t len)
 545 {
 546         u16 fw_crc;
 547         u16 crc;
 548
 549         /*
 550          * The last 2 bytes in the firmware array are the crc checksum itself,
 551          * this means that we should never pass those 2 bytes to the crc
 552          * algorithm.
 553          */
 554         fw_crc = (data[len - 2] << 8 | data[len - 1]);
 555
 556         /*
 557          * Use the crc ccitt algorithm.
 558          * This will return the same value as the legacy driver which
 559          * used bit ordering reversion on the both the firmware bytes
 560          * before input input as well as on the final output.
 561          * Obviously using crc ccitt directly is much more efficient.
 562          */
 563         crc = crc_ccitt(~0, data, len - 2);
 564
 565         /*
 566          * There is a small difference between the crc-itu-t + bitrev and
 567          * the crc-ccitt crc calculation. In the latter method the 2 bytes
 568          * will be swapped, use swab16 to convert the crc to the correct
 569          * value.
 570          */
 571         crc = swab16(crc);
 572
 573         return fw_crc == crc;
 574 }
 575
 576 int rt2800_check_firmware(struct rt2x00_dev *rt2x00dev,
 577                           const u8 *data, const size_t len)
 578 {
 579         size_t offset = 0;
 580         size_t fw_len;
 581         bool multiple;
 582
 583         /*
 584          * PCI(e) & SOC devices require firmware with a length
 585          * of 8kb. USB devices require firmware files with a length
 586          * of 4kb. Certain USB chipsets however require different firmware,
 587          * which Ralink only provides attached to the original firmware
 588          * file. Thus for USB devices, firmware files have a length
 589          * which is a multiple of 4kb. The firmware for rt3290 chip also
 590          * have a length which is a multiple of 4kb.
 591          */
 592         if (rt2x00_is_usb(rt2x00dev) || rt2x00_rt(rt2x00dev, RT3290))
 593                 fw_len = 4096;
 594         else
 595                 fw_len = 8192;
 596
 597         multiple = true;
 598         /*
 599          * Validate the firmware length
 600          */
 601         if (len != fw_len && (!multiple || (len % fw_len) != 0))
 602                 return FW_BAD_LENGTH;
 603
 604         /*
 605          * Check if the chipset requires one of the upper parts
 606          * of the firmware.
 607          */
 608         if (rt2x00_is_usb(rt2x00dev) &&
 609             !rt2x00_rt(rt2x00dev, RT2860) &&
 610             !rt2x00_rt(rt2x00dev, RT2872) &&
 611             !rt2x00_rt(rt2x00dev, RT3070) &&
 612             ((len / fw_len) == 1))
 613                 return FW_BAD_VERSION;
 614
 615         /*
 616          * 8kb firmware files must be checked as if it were
 617          * 2 separate firmware files.
 618          */
 619         while (offset < len) {
 620                 if (!rt2800_check_firmware_crc(data + offset, fw_len))
 621                         return FW_BAD_CRC;
 622
 623                 offset += fw_len;
 624         }
 625
 626         return FW_OK;
 627 }
 628 EXPORT_SYMBOL_GPL(rt2800_check_firmware);
 629
 630 int rt2800_load_firmware(struct rt2x00_dev *rt2x00dev,
 631                          const u8 *data, const size_t len)
 632 {
 633         unsigned int i;
 634         u32 reg;
 635         int retval;
 636
 637         if (rt2x00_rt(rt2x00dev, RT3290)) {
 638                 retval = rt2800_enable_wlan_rt3290(rt2x00dev);
 639                 if (retval)
 640                         return -EBUSY;
 641         }
 642
 643         /*
 644          * If driver doesn't wake up firmware here,
 645          * rt2800_load_firmware will hang forever when interface is up again.
 646          */
 647         rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0x00000000);
 648
 649         /*
 650          * Wait for stable hardware.
 651          */
 652         if (rt2800_wait_csr_ready(rt2x00dev))
 653                 return -EBUSY;
 654
 655         if (rt2x00_is_pci(rt2x00dev)) {
 656                 if (rt2x00_rt(rt2x00dev, RT3290) ||
 657                     rt2x00_rt(rt2x00dev, RT3572) ||
 658                     rt2x00_rt(rt2x00dev, RT5390) ||
 659                     rt2x00_rt(rt2x00dev, RT5392)) {
 660                         rt2800_register_read(rt2x00dev, AUX_CTRL, &reg);
 661                         rt2x00_set_field32(&reg, AUX_CTRL_FORCE_PCIE_CLK, 1);
 662                         rt2x00_set_field32(&reg, AUX_CTRL_WAKE_PCIE_EN, 1);
 663                         rt2800_register_write(rt2x00dev, AUX_CTRL, reg);
 664                 }
 665                 rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000002);
 666         }
 667
 668         rt2800_disable_wpdma(rt2x00dev);
 669
 670         /*
 671          * Write firmware to the device.
 672          */
 673         rt2800_drv_write_firmware(rt2x00dev, data, len);
 674
 675         /*
 676          * Wait for device to stabilize.
 677          */
 678         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
 679                 rt2800_register_read(rt2x00dev, PBF_SYS_CTRL, &reg);
 680                 if (rt2x00_get_field32(reg, PBF_SYS_CTRL_READY))
 681                         break;
 682                 msleep(1);
 683         }
 684
 685         if (i == REGISTER_BUSY_COUNT) {
 686                 rt2x00_err(rt2x00dev, "PBF system register not ready\n");
 687                 return -EBUSY;
 688         }
 689
 690         /*
 691          * Disable DMA, will be reenabled later when enabling
 692          * the radio.
 693          */
 694         rt2800_disable_wpdma(rt2x00dev);
 695
 696         /*
 697          * Initialize firmware.
 698          */
 699         rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
 700         rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
 701         if (rt2x00_is_usb(rt2x00dev)) {
 702                 rt2800_register_write(rt2x00dev, H2M_INT_SRC, 0);
 703                 rt2800_mcu_request(rt2x00dev, MCU_BOOT_SIGNAL, 0, 0, 0);
 704         }
 705         msleep(1);
 706
 707         return 0;
 708 }
 709 EXPORT_SYMBOL_GPL(rt2800_load_firmware);
 710
 711 void rt2800_write_tx_data(struct queue_entry *entry,
 712                           struct txentry_desc *txdesc)
 713 {
 714         __le32 *txwi = rt2800_drv_get_txwi(entry);
 715         u32 word;
 716         int i;
 717
 718         /*
 719          * Initialize TX Info descriptor
 720          */
 721         rt2x00_desc_read(txwi, 0, &word);
 722         rt2x00_set_field32(&word, TXWI_W0_FRAG,
 723                            test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
 724         rt2x00_set_field32(&word, TXWI_W0_MIMO_PS,
 725                            test_bit(ENTRY_TXD_HT_MIMO_PS, &txdesc->flags));
 726         rt2x00_set_field32(&word, TXWI_W0_CF_ACK, 0);
 727         rt2x00_set_field32(&word, TXWI_W0_TS,
 728                            test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
 729         rt2x00_set_field32(&word, TXWI_W0_AMPDU,
 730                            test_bit(ENTRY_TXD_HT_AMPDU, &txdesc->flags));
 731         rt2x00_set_field32(&word, TXWI_W0_MPDU_DENSITY,
 732                            txdesc->u.ht.mpdu_density);
 733         rt2x00_set_field32(&word, TXWI_W0_TX_OP, txdesc->u.ht.txop);
 734         rt2x00_set_field32(&word, TXWI_W0_MCS, txdesc->u.ht.mcs);
 735         rt2x00_set_field32(&word, TXWI_W0_BW,
 736                            test_bit(ENTRY_TXD_HT_BW_40, &txdesc->flags));
 737         rt2x00_set_field32(&word, TXWI_W0_SHORT_GI,
 738                            test_bit(ENTRY_TXD_HT_SHORT_GI, &txdesc->flags));
 739         rt2x00_set_field32(&word, TXWI_W0_STBC, txdesc->u.ht.stbc);
 740         rt2x00_set_field32(&word, TXWI_W0_PHYMODE, txdesc->rate_mode);
 741         rt2x00_desc_write(txwi, 0, word);
 742
 743         rt2x00_desc_read(txwi, 1, &word);
 744         rt2x00_set_field32(&word, TXWI_W1_ACK,
 745                            test_bit(ENTRY_TXD_ACK, &txdesc->flags));
 746         rt2x00_set_field32(&word, TXWI_W1_NSEQ,
 747                            test_bit(ENTRY_TXD_GENERATE_SEQ, &txdesc->flags));
 748         rt2x00_set_field32(&word, TXWI_W1_BW_WIN_SIZE, txdesc->u.ht.ba_size);
 749         rt2x00_set_field32(&word, TXWI_W1_WIRELESS_CLI_ID,
 750                            test_bit(ENTRY_TXD_ENCRYPT, &txdesc->flags) ?
 751                            txdesc->key_idx : txdesc->u.ht.wcid);
 752         rt2x00_set_field32(&word, TXWI_W1_MPDU_TOTAL_BYTE_COUNT,
 753                            txdesc->length);
 754         rt2x00_set_field32(&word, TXWI_W1_PACKETID_QUEUE, entry->queue->qid);
 755         rt2x00_set_field32(&word, TXWI_W1_PACKETID_ENTRY, (entry->entry_idx % 3) + 1);
 756         rt2x00_desc_write(txwi, 1, word);
 757
 758         /*
 759          * Always write 0 to IV/EIV fields (word 2 and 3), hardware will insert
 760          * the IV from the IVEIV register when TXD_W3_WIV is set to 0.
 761          * When TXD_W3_WIV is set to 1 it will use the IV data
 762          * from the descriptor. The TXWI_W1_WIRELESS_CLI_ID indicates which
 763          * crypto entry in the registers should be used to encrypt the frame.
 764          *
 765          * Nulify all remaining words as well, we don't know how to program them.
 766          */
 767         for (i = 2; i < entry->queue->winfo_size / sizeof(__le32); i++)
 768                 _rt2x00_desc_write(txwi, i, 0);
 769 }
 770 EXPORT_SYMBOL_GPL(rt2800_write_tx_data);
 771
 772 static int rt2800_agc_to_rssi(struct rt2x00_dev *rt2x00dev, u32 rxwi_w2)
 773 {
 774         s8 rssi0 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI0);
 775         s8 rssi1 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI1);
 776         s8 rssi2 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI2);
 777         u16 eeprom;
 778         u8 offset0;
 779         u8 offset1;
 780         u8 offset2;
 781
 782         if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ) {
 783                 rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_BG, &eeprom);
 784                 offset0 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG_OFFSET0);
 785                 offset1 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG_OFFSET1);
 786                 rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &eeprom);
 787                 offset2 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG2_OFFSET2);
 788         } else {
 789                 rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_A, &eeprom);
 790                 offset0 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A_OFFSET0);
 791                 offset1 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A_OFFSET1);
 792                 rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &eeprom);
 793                 offset2 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A2_OFFSET2);
 794         }
 795
 796         /*
 797          * Convert the value from the descriptor into the RSSI value
 798          * If the value in the descriptor is 0, it is considered invalid
 799          * and the default (extremely low) rssi value is assumed
 800          */
 801         rssi0 = (rssi0) ? (-12 - offset0 - rt2x00dev->lna_gain - rssi0) : -128;
 802         rssi1 = (rssi1) ? (-12 - offset1 - rt2x00dev->lna_gain - rssi1) : -128;
 803         rssi2 = (rssi2) ? (-12 - offset2 - rt2x00dev->lna_gain - rssi2) : -128;
 804
 805         /*
 806          * mac80211 only accepts a single RSSI value. Calculating the
 807          * average doesn't deliver a fair answer either since -60:-60 would
 808          * be considered equally good as -50:-70 while the second is the one
 809          * which gives less energy...
 810          */
 811         rssi0 = max(rssi0, rssi1);
 812         return (int)max(rssi0, rssi2);
 813 }
 814
 815 void rt2800_process_rxwi(struct queue_entry *entry,
 816                          struct rxdone_entry_desc *rxdesc)
 817 {
 818         __le32 *rxwi = (__le32 *) entry->skb->data;
 819         u32 word;
 820
 821         rt2x00_desc_read(rxwi, 0, &word);
 822
 823         rxdesc->cipher = rt2x00_get_field32(word, RXWI_W0_UDF);
 824         rxdesc->size = rt2x00_get_field32(word, RXWI_W0_MPDU_TOTAL_BYTE_COUNT);
 825
 826         rt2x00_desc_read(rxwi, 1, &word);
 827
 828         if (rt2x00_get_field32(word, RXWI_W1_SHORT_GI))
 829                 rxdesc->flags |= RX_FLAG_SHORT_GI;
 830
 831         if (rt2x00_get_field32(word, RXWI_W1_BW))
 832                 rxdesc->flags |= RX_FLAG_40MHZ;
 833
 834         /*
 835          * Detect RX rate, always use MCS as signal type.
 836          */
 837         rxdesc->dev_flags |= RXDONE_SIGNAL_MCS;
 838         rxdesc->signal = rt2x00_get_field32(word, RXWI_W1_MCS);
 839         rxdesc->rate_mode = rt2x00_get_field32(word, RXWI_W1_PHYMODE);
 840
 841         /*
 842          * Mask of 0x8 bit to remove the short preamble flag.
 843          */
 844         if (rxdesc->rate_mode == RATE_MODE_CCK)
 845                 rxdesc->signal &= ~0x8;
 846
 847         rt2x00_desc_read(rxwi, 2, &word);
 848
 849         /*
 850          * Convert descriptor AGC value to RSSI value.
 851          */
 852         rxdesc->rssi = rt2800_agc_to_rssi(entry->queue->rt2x00dev, word);
 853         /*
 854          * Remove RXWI descriptor from start of the buffer.
 855          */
 856         skb_pull(entry->skb, entry->queue->winfo_size);
 857 }
 858 EXPORT_SYMBOL_GPL(rt2800_process_rxwi);
 859
 860 void rt2800_txdone_entry(struct queue_entry *entry, u32 status, __le32 *txwi)
 861 {
 862         struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
 863         struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
 864         struct txdone_entry_desc txdesc;
 865         u32 word;
 866         u16 mcs, real_mcs;
 867         int aggr, ampdu;
 868
 869         /*
 870          * Obtain the status about this packet.
 871          */
 872         txdesc.flags = 0;
 873         rt2x00_desc_read(txwi, 0, &word);
 874
 875         mcs = rt2x00_get_field32(word, TXWI_W0_MCS);
 876         ampdu = rt2x00_get_field32(word, TXWI_W0_AMPDU);
 877
 878         real_mcs = rt2x00_get_field32(status, TX_STA_FIFO_MCS);
 879         aggr = rt2x00_get_field32(status, TX_STA_FIFO_TX_AGGRE);
 880
 881         /*
 882          * If a frame was meant to be sent as a single non-aggregated MPDU
 883          * but ended up in an aggregate the used tx rate doesn't correlate
 884          * with the one specified in the TXWI as the whole aggregate is sent
 885          * with the same rate.
 886          *
 887          * For example: two frames are sent to rt2x00, the first one sets
 888          * AMPDU=1 and requests MCS7 whereas the second frame sets AMDPU=0
 889          * and requests MCS15. If the hw aggregates both frames into one
 890          * AMDPU the tx status for both frames will contain MCS7 although
 891          * the frame was sent successfully.
 892          *
 893          * Hence, replace the requested rate with the real tx rate to not
 894          * confuse the rate control algortihm by providing clearly wrong
 895          * data.
 896          */
 897         if (unlikely(aggr == 1 && ampdu == 0 && real_mcs != mcs)) {
 898                 skbdesc->tx_rate_idx = real_mcs;
 899                 mcs = real_mcs;
 900         }
 901
 902         if (aggr == 1 || ampdu == 1)
 903                 __set_bit(TXDONE_AMPDU, &txdesc.flags);
 904
 905         /*
 906          * Ralink has a retry mechanism using a global fallback
 907          * table. We setup this fallback table to try the immediate
 908          * lower rate for all rates. In the TX_STA_FIFO, the MCS field
 909          * always contains the MCS used for the last transmission, be
 910          * it successful or not.
 911          */
 912         if (rt2x00_get_field32(status, TX_STA_FIFO_TX_SUCCESS)) {
 913                 /*
 914                  * Transmission succeeded. The number of retries is
 915                  * mcs - real_mcs
 916                  */
 917                 __set_bit(TXDONE_SUCCESS, &txdesc.flags);
 918                 txdesc.retry = ((mcs > real_mcs) ? mcs - real_mcs : 0);
 919         } else {
 920                 /*
 921                  * Transmission failed. The number of retries is
 922                  * always 7 in this case (for a total number of 8
 923                  * frames sent).
 924                  */
 925                 __set_bit(TXDONE_FAILURE, &txdesc.flags);
 926                 txdesc.retry = rt2x00dev->long_retry;
 927         }
 928
 929         /*
 930          * the frame was retried at least once
 931          * -> hw used fallback rates
 932          */
 933         if (txdesc.retry)
 934                 __set_bit(TXDONE_FALLBACK, &txdesc.flags);
 935
 936         rt2x00lib_txdone(entry, &txdesc);
 937 }
 938 EXPORT_SYMBOL_GPL(rt2800_txdone_entry);
 939
 940 static unsigned int rt2800_hw_beacon_base(struct rt2x00_dev *rt2x00dev,
 941                                           unsigned int index)
 942 {
 943         return HW_BEACON_BASE(index);
 944 }
 945
 946 static inline u8 rt2800_get_beacon_offset(struct rt2x00_dev *rt2x00dev,
 947                                           unsigned int index)
 948 {
 949         return BEACON_BASE_TO_OFFSET(rt2800_hw_beacon_base(rt2x00dev, index));
 950 }
 951
 952 void rt2800_write_beacon(struct queue_entry *entry, struct txentry_desc *txdesc)
 953 {
 954         struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
 955         struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
 956         unsigned int beacon_base;
 957         unsigned int padding_len;
 958         u32 orig_reg, reg;
 959         const int txwi_desc_size = entry->queue->winfo_size;
 960
 961         /*
 962          * Disable beaconing while we are reloading the beacon data,
 963          * otherwise we might be sending out invalid data.
 964          */
 965         rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
 966         orig_reg = reg;
 967         rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
 968         rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
 969
 970         /*
 971          * Add space for the TXWI in front of the skb.
 972          */
 973         memset(skb_push(entry->skb, txwi_desc_size), 0, txwi_desc_size);
 974
 975         /*
 976          * Register descriptor details in skb frame descriptor.
 977          */
 978         skbdesc->flags |= SKBDESC_DESC_IN_SKB;
 979         skbdesc->desc = entry->skb->data;
 980         skbdesc->desc_len = txwi_desc_size;
 981
 982         /*
 983          * Add the TXWI for the beacon to the skb.
 984          */
 985         rt2800_write_tx_data(entry, txdesc);
 986
 987         /*
 988          * Dump beacon to userspace through debugfs.
 989          */
 990         rt2x00debug_dump_frame(rt2x00dev, DUMP_FRAME_BEACON, entry->skb);
 991
 992         /*
 993          * Write entire beacon with TXWI and padding to register.
 994          */
 995         padding_len = roundup(entry->skb->len, 4) - entry->skb->len;
 996         if (padding_len && skb_pad(entry->skb, padding_len)) {
 997                 rt2x00_err(rt2x00dev, "Failure padding beacon, aborting\n");
 998                 /* skb freed by skb_pad() on failure */
 999                 entry->skb = NULL;
1000                 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, orig_reg);
1001                 return;
1002         }
1003
1004         beacon_base = rt2800_hw_beacon_base(rt2x00dev, entry->entry_idx);
1005
1006         rt2800_register_multiwrite(rt2x00dev, beacon_base, entry->skb->data,
1007                                    entry->skb->len + padding_len);
1008
1009         /*
1010          * Enable beaconing again.
1011          */
1012         rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 1);
1013         rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1014
1015         /*
1016          * Clean up beacon skb.
1017          */
1018         dev_kfree_skb_any(entry->skb);
1019         entry->skb = NULL;
1020 }
1021 EXPORT_SYMBOL_GPL(rt2800_write_beacon);
1022
1023 static inline void rt2800_clear_beacon_register(struct rt2x00_dev *rt2x00dev,
1024                                                 unsigned int index)
1025 {
1026         int i;
1027         const int txwi_desc_size = rt2x00dev->bcn->winfo_size;
1028         unsigned int beacon_base;
1029
1030         beacon_base = rt2800_hw_beacon_base(rt2x00dev, index);
1031
1032         /*
1033          * For the Beacon base registers we only need to clear
1034          * the whole TXWI which (when set to 0) will invalidate
1035          * the entire beacon.
1036          */
1037         for (i = 0; i < txwi_desc_size; i += sizeof(__le32))
1038                 rt2800_register_write(rt2x00dev, beacon_base + i, 0);
1039 }
1040
1041 void rt2800_clear_beacon(struct queue_entry *entry)
1042 {
1043         struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
1044         u32 reg;
1045
1046         /*
1047          * Disable beaconing while we are reloading the beacon data,
1048          * otherwise we might be sending out invalid data.
1049          */
1050         rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
1051         rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
1052         rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1053
1054         /*
1055          * Clear beacon.
1056          */
1057         rt2800_clear_beacon_register(rt2x00dev, entry->entry_idx);
1058
1059         /*
1060          * Enabled beaconing again.
1061          */
1062         rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 1);
1063         rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1064 }
1065 EXPORT_SYMBOL_GPL(rt2800_clear_beacon);
1066
1067 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
1068 const struct rt2x00debug rt2800_rt2x00debug = {
1069         .owner  = THIS_MODULE,
1070         .csr    = {
1071                 .read           = rt2800_register_read,
1072                 .write          = rt2800_register_write,
1073                 .flags          = RT2X00DEBUGFS_OFFSET,
1074                 .word_base      = CSR_REG_BASE,
1075                 .word_size      = sizeof(u32),
1076                 .word_count     = CSR_REG_SIZE / sizeof(u32),
1077         },
1078         .eeprom = {
1079                 /* NOTE: The local EEPROM access functions can't
1080                  * be used here, use the generic versions instead.
1081                  */
1082                 .read           = rt2x00_eeprom_read,
1083                 .write          = rt2x00_eeprom_write,
1084                 .word_base      = EEPROM_BASE,
1085                 .word_size      = sizeof(u16),
1086                 .word_count     = EEPROM_SIZE / sizeof(u16),
1087         },
1088         .bbp    = {
1089                 .read           = rt2800_bbp_read,
1090                 .write          = rt2800_bbp_write,
1091                 .word_base      = BBP_BASE,
1092                 .word_size      = sizeof(u8),
1093                 .word_count     = BBP_SIZE / sizeof(u8),
1094         },
1095         .rf     = {
1096                 .read           = rt2x00_rf_read,
1097                 .write          = rt2800_rf_write,
1098                 .word_base      = RF_BASE,
1099                 .word_size      = sizeof(u32),
1100                 .word_count     = RF_SIZE / sizeof(u32),
1101         },
1102         .rfcsr  = {
1103                 .read           = rt2800_rfcsr_read,
1104                 .write          = rt2800_rfcsr_write,
1105                 .word_base      = RFCSR_BASE,
1106                 .word_size      = sizeof(u8),
1107                 .word_count     = RFCSR_SIZE / sizeof(u8),
1108         },
1109 };
1110 EXPORT_SYMBOL_GPL(rt2800_rt2x00debug);
1111 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
1112
1113 int rt2800_rfkill_poll(struct rt2x00_dev *rt2x00dev)
1114 {
1115         u32 reg;
1116
1117         if (rt2x00_rt(rt2x00dev, RT3290)) {
1118                 rt2800_register_read(rt2x00dev, WLAN_FUN_CTRL, &reg);
1119                 return rt2x00_get_field32(reg, WLAN_GPIO_IN_BIT0);
1120         } else {
1121                 rt2800_register_read(rt2x00dev, GPIO_CTRL, &reg);
1122                 return rt2x00_get_field32(reg, GPIO_CTRL_VAL2);
1123         }
1124 }
1125 EXPORT_SYMBOL_GPL(rt2800_rfkill_poll);
1126
1127 #ifdef CONFIG_RT2X00_LIB_LEDS
1128 static void rt2800_brightness_set(struct led_classdev *led_cdev,
1129                                   enum led_brightness brightness)
1130 {
1131         struct rt2x00_led *led =
1132             container_of(led_cdev, struct rt2x00_led, led_dev);
1133         unsigned int enabled = brightness != LED_OFF;
1134         unsigned int bg_mode =
1135             (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_2GHZ);
1136         unsigned int polarity =
1137                 rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
1138                                    EEPROM_FREQ_LED_POLARITY);
1139         unsigned int ledmode =
1140                 rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
1141                                    EEPROM_FREQ_LED_MODE);
1142         u32 reg;
1143
1144         /* Check for SoC (SOC devices don't support MCU requests) */
1145         if (rt2x00_is_soc(led->rt2x00dev)) {
1146                 rt2800_register_read(led->rt2x00dev, LED_CFG, &reg);
1147
1148                 /* Set LED Polarity */
1149                 rt2x00_set_field32(&reg, LED_CFG_LED_POLAR, polarity);
1150
1151                 /* Set LED Mode */
1152                 if (led->type == LED_TYPE_RADIO) {
1153                         rt2x00_set_field32(&reg, LED_CFG_G_LED_MODE,
1154                                            enabled ? 3 : 0);
1155                 } else if (led->type == LED_TYPE_ASSOC) {
1156                         rt2x00_set_field32(&reg, LED_CFG_Y_LED_MODE,
1157                                            enabled ? 3 : 0);
1158                 } else if (led->type == LED_TYPE_QUALITY) {
1159                         rt2x00_set_field32(&reg, LED_CFG_R_LED_MODE,
1160                                            enabled ? 3 : 0);
1161                 }
1162
1163                 rt2800_register_write(led->rt2x00dev, LED_CFG, reg);
1164
1165         } else {
1166                 if (led->type == LED_TYPE_RADIO) {
1167                         rt2800_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
1168                                               enabled ? 0x20 : 0);
1169                 } else if (led->type == LED_TYPE_ASSOC) {
1170                         rt2800_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
1171                                               enabled ? (bg_mode ? 0x60 : 0xa0) : 0x20);
1172                 } else if (led->type == LED_TYPE_QUALITY) {
1173                         /*
1174                          * The brightness is divided into 6 levels (0 - 5),
1175                          * The specs tell us the following levels:
1176                          *      0, 1 ,3, 7, 15, 31
1177                          * to determine the level in a simple way we can simply
1178                          * work with bitshifting:
1179                          *      (1 << level) - 1
1180                          */
1181                         rt2800_mcu_request(led->rt2x00dev, MCU_LED_STRENGTH, 0xff,
1182                                               (1 << brightness / (LED_FULL / 6)) - 1,
1183                                               polarity);
1184                 }
1185         }
1186 }
1187
1188 static void rt2800_init_led(struct rt2x00_dev *rt2x00dev,
1189                      struct rt2x00_led *led, enum led_type type)
1190 {
1191         led->rt2x00dev = rt2x00dev;
1192         led->type = type;
1193         led->led_dev.brightness_set = rt2800_brightness_set;
1194         led->flags = LED_INITIALIZED;
1195 }
1196 #endif /* CONFIG_RT2X00_LIB_LEDS */
1197
1198 /*
1199  * Configuration handlers.
1200  */
1201 static void rt2800_config_wcid(struct rt2x00_dev *rt2x00dev,
1202                                const u8 *address,
1203                                int wcid)
1204 {
1205         struct mac_wcid_entry wcid_entry;
1206         u32 offset;
1207
1208         offset = MAC_WCID_ENTRY(wcid);
1209
1210         memset(&wcid_entry, 0xff, sizeof(wcid_entry));
1211         if (address)
1212                 memcpy(wcid_entry.mac, address, ETH_ALEN);
1213
1214         rt2800_register_multiwrite(rt2x00dev, offset,
1215                                       &wcid_entry, sizeof(wcid_entry));
1216 }
1217
1218 static void rt2800_delete_wcid_attr(struct rt2x00_dev *rt2x00dev, int wcid)
1219 {
1220         u32 offset;
1221         offset = MAC_WCID_ATTR_ENTRY(wcid);
1222         rt2800_register_write(rt2x00dev, offset, 0);
1223 }
1224
1225 static void rt2800_config_wcid_attr_bssidx(struct rt2x00_dev *rt2x00dev,
1226                                            int wcid, u32 bssidx)
1227 {
1228         u32 offset = MAC_WCID_ATTR_ENTRY(wcid);
1229         u32 reg;
1230
1231         /*
1232          * The BSS Idx numbers is split in a main value of 3 bits,
1233          * and a extended field for adding one additional bit to the value.
1234          */
1235         rt2800_register_read(rt2x00dev, offset, &reg);
1236         rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_BSS_IDX, (bssidx & 0x7));
1237         rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_BSS_IDX_EXT,
1238                            (bssidx & 0x8) >> 3);
1239         rt2800_register_write(rt2x00dev, offset, reg);
1240 }
1241
1242 static void rt2800_config_wcid_attr_cipher(struct rt2x00_dev *rt2x00dev,
1243                                            struct rt2x00lib_crypto *crypto,
1244                                            struct ieee80211_key_conf *key)
1245 {
1246         struct mac_iveiv_entry iveiv_entry;
1247         u32 offset;
1248         u32 reg;
1249
1250         offset = MAC_WCID_ATTR_ENTRY(key->hw_key_idx);
1251
1252         if (crypto->cmd == SET_KEY) {
1253                 rt2800_register_read(rt2x00dev, offset, &reg);
1254                 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_KEYTAB,
1255                                    !!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE));
1256                 /*
1257                  * Both the cipher as the BSS Idx numbers are split in a main
1258                  * value of 3 bits, and a extended field for adding one additional
1259                  * bit to the value.
1260                  */
1261                 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER,
1262                                    (crypto->cipher & 0x7));
1263                 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER_EXT,
1264                                    (crypto->cipher & 0x8) >> 3);
1265                 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_RX_WIUDF, crypto->cipher);
1266                 rt2800_register_write(rt2x00dev, offset, reg);
1267         } else {
1268                 /* Delete the cipher without touching the bssidx */
1269                 rt2800_register_read(rt2x00dev, offset, &reg);
1270                 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_KEYTAB, 0);
1271                 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER, 0);
1272                 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER_EXT, 0);
1273                 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_RX_WIUDF, 0);
1274                 rt2800_register_write(rt2x00dev, offset, reg);
1275         }
1276
1277         offset = MAC_IVEIV_ENTRY(key->hw_key_idx);
1278
1279         memset(&iveiv_entry, 0, sizeof(iveiv_entry));
1280         if ((crypto->cipher == CIPHER_TKIP) ||
1281             (crypto->cipher == CIPHER_TKIP_NO_MIC) ||
1282             (crypto->cipher == CIPHER_AES))
1283                 iveiv_entry.iv[3] |= 0x20;
1284         iveiv_entry.iv[3] |= key->keyidx << 6;
1285         rt2800_register_multiwrite(rt2x00dev, offset,
1286                                       &iveiv_entry, sizeof(iveiv_entry));
1287 }
1288
1289 int rt2800_config_shared_key(struct rt2x00_dev *rt2x00dev,
1290                              struct rt2x00lib_crypto *crypto,
1291                              struct ieee80211_key_conf *key)
1292 {
1293         struct hw_key_entry key_entry;
1294         struct rt2x00_field32 field;
1295         u32 offset;
1296         u32 reg;
1297
1298         if (crypto->cmd == SET_KEY) {
1299                 key->hw_key_idx = (4 * crypto->bssidx) + key->keyidx;
1300
1301                 memcpy(key_entry.key, crypto->key,
1302                        sizeof(key_entry.key));
1303                 memcpy(key_entry.tx_mic, crypto->tx_mic,
1304                        sizeof(key_entry.tx_mic));
1305                 memcpy(key_entry.rx_mic, crypto->rx_mic,
1306                        sizeof(key_entry.rx_mic));
1307
1308                 offset = SHARED_KEY_ENTRY(key->hw_key_idx);
1309                 rt2800_register_multiwrite(rt2x00dev, offset,
1310                                               &key_entry, sizeof(key_entry));
1311         }
1312
1313         /*
1314          * The cipher types are stored over multiple registers
1315          * starting with SHARED_KEY_MODE_BASE each word will have
1316          * 32 bits and contains the cipher types for 2 bssidx each.
1317          * Using the correct defines correctly will cause overhead,
1318          * so just calculate the correct offset.
1319          */
1320         field.bit_offset = 4 * (key->hw_key_idx % 8);
1321         field.bit_mask = 0x7 << field.bit_offset;
1322
1323         offset = SHARED_KEY_MODE_ENTRY(key->hw_key_idx / 8);
1324
1325         rt2800_register_read(rt2x00dev, offset, &reg);
1326         rt2x00_set_field32(&reg, field,
1327                            (crypto->cmd == SET_KEY) * crypto->cipher);
1328         rt2800_register_write(rt2x00dev, offset, reg);
1329
1330         /*
1331          * Update WCID information
1332          */
1333         rt2800_config_wcid(rt2x00dev, crypto->address, key->hw_key_idx);
1334         rt2800_config_wcid_attr_bssidx(rt2x00dev, key->hw_key_idx,
1335                                        crypto->bssidx);
1336         rt2800_config_wcid_attr_cipher(rt2x00dev, crypto, key);
1337
1338         return 0;
1339 }
1340 EXPORT_SYMBOL_GPL(rt2800_config_shared_key);
1341
1342 static inline int rt2800_find_wcid(struct rt2x00_dev *rt2x00dev)
1343 {
1344         struct mac_wcid_entry wcid_entry;
1345         int idx;
1346         u32 offset;
1347
1348         /*
1349          * Search for the first free WCID entry and return the corresponding
1350          * index.
1351          *
1352          * Make sure the WCID starts _after_ the last possible shared key
1353          * entry (>32).
1354          *
1355          * Since parts of the pairwise key table might be shared with
1356          * the beacon frame buffers 6 & 7 we should only write into the
1357          * first 222 entries.
1358          */
1359         for (idx = 33; idx <= 222; idx++) {
1360                 offset = MAC_WCID_ENTRY(idx);
1361                 rt2800_register_multiread(rt2x00dev, offset, &wcid_entry,
1362                                           sizeof(wcid_entry));
1363                 if (is_broadcast_ether_addr(wcid_entry.mac))
1364                         return idx;
1365         }
1366
1367         /*
1368          * Use -1 to indicate that we don't have any more space in the WCID
1369          * table.
1370          */
1371         return -1;
1372 }
1373
1374 int rt2800_config_pairwise_key(struct rt2x00_dev *rt2x00dev,
1375                                struct rt2x00lib_crypto *crypto,
1376                                struct ieee80211_key_conf *key)
1377 {
1378         struct hw_key_entry key_entry;
1379         u32 offset;
1380
1381         if (crypto->cmd == SET_KEY) {
1382                 /*
1383                  * Allow key configuration only for STAs that are
1384                  * known by the hw.
1385                  */
1386                 if (crypto->wcid < 0)
1387                         return -ENOSPC;
1388                 key->hw_key_idx = crypto->wcid;
1389
1390                 memcpy(key_entry.key, crypto->key,
1391                        sizeof(key_entry.key));
1392                 memcpy(key_entry.tx_mic, crypto->tx_mic,
1393                        sizeof(key_entry.tx_mic));
1394                 memcpy(key_entry.rx_mic, crypto->rx_mic,
1395                        sizeof(key_entry.rx_mic));
1396
1397                 offset = PAIRWISE_KEY_ENTRY(key->hw_key_idx);
1398                 rt2800_register_multiwrite(rt2x00dev, offset,
1399                                               &key_entry, sizeof(key_entry));
1400         }
1401
1402         /*
1403          * Update WCID information
1404          */
1405         rt2800_config_wcid_attr_cipher(rt2x00dev, crypto, key);
1406
1407         return 0;
1408 }
1409 EXPORT_SYMBOL_GPL(rt2800_config_pairwise_key);
1410
1411 int rt2800_sta_add(struct rt2x00_dev *rt2x00dev, struct ieee80211_vif *vif,
1412                    struct ieee80211_sta *sta)
1413 {
1414         int wcid;
1415         struct rt2x00_sta *sta_priv = sta_to_rt2x00_sta(sta);
1416
1417         /*
1418          * Find next free WCID.
1419          */
1420         wcid = rt2800_find_wcid(rt2x00dev);
1421
1422         /*
1423          * Store selected wcid even if it is invalid so that we can
1424          * later decide if the STA is uploaded into the hw.
1425          */
1426         sta_priv->wcid = wcid;
1427
1428         /*
1429          * No space left in the device, however, we can still communicate
1430          * with the STA -> No error.
1431          */
1432         if (wcid < 0)
1433                 return 0;
1434
1435         /*
1436          * Clean up WCID attributes and write STA address to the device.
1437          */
1438         rt2800_delete_wcid_attr(rt2x00dev, wcid);
1439         rt2800_config_wcid(rt2x00dev, sta->addr, wcid);
1440         rt2800_config_wcid_attr_bssidx(rt2x00dev, wcid,
1441                                        rt2x00lib_get_bssidx(rt2x00dev, vif));
1442         return 0;
1443 }
1444 EXPORT_SYMBOL_GPL(rt2800_sta_add);
1445
1446 int rt2800_sta_remove(struct rt2x00_dev *rt2x00dev, int wcid)
1447 {
1448         /*
1449          * Remove WCID entry, no need to clean the attributes as they will
1450          * get renewed when the WCID is reused.
1451          */
1452         rt2800_config_wcid(rt2x00dev, NULL, wcid);
1453
1454         return 0;
1455 }
1456 EXPORT_SYMBOL_GPL(rt2800_sta_remove);
1457
1458 void rt2800_config_filter(struct rt2x00_dev *rt2x00dev,
1459                           const unsigned int filter_flags)
1460 {
1461         u32 reg;
1462
1463         /*
1464          * Start configuration steps.
1465          * Note that the version error will always be dropped
1466          * and broadcast frames will always be accepted since
1467          * there is no filter for it at this time.
1468          */
1469         rt2800_register_read(rt2x00dev, RX_FILTER_CFG, &reg);
1470         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CRC_ERROR,
1471                            !(filter_flags & FIF_FCSFAIL));
1472         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_PHY_ERROR,
1473                            !(filter_flags & FIF_PLCPFAIL));
1474         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_NOT_TO_ME,
1475                            !(filter_flags & FIF_PROMISC_IN_BSS));
1476         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_NOT_MY_BSSD, 0);
1477         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_VER_ERROR, 1);
1478         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_MULTICAST,
1479                            !(filter_flags & FIF_ALLMULTI));
1480         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BROADCAST, 0);
1481         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_DUPLICATE, 1);
1482         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CF_END_ACK,
1483                            !(filter_flags & FIF_CONTROL));
1484         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CF_END,
1485                            !(filter_flags & FIF_CONTROL));
1486         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_ACK,
1487                            !(filter_flags & FIF_CONTROL));
1488         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CTS,
1489                            !(filter_flags & FIF_CONTROL));
1490         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_RTS,
1491                            !(filter_flags & FIF_CONTROL));
1492         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_PSPOLL,
1493                            !(filter_flags & FIF_PSPOLL));
1494         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BA, 0);
1495         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BAR,
1496                            !(filter_flags & FIF_CONTROL));
1497         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CNTL,
1498                            !(filter_flags & FIF_CONTROL));
1499         rt2800_register_write(rt2x00dev, RX_FILTER_CFG, reg);
1500 }
1501 EXPORT_SYMBOL_GPL(rt2800_config_filter);
1502
1503 void rt2800_config_intf(struct rt2x00_dev *rt2x00dev, struct rt2x00_intf *intf,
1504                         struct rt2x00intf_conf *conf, const unsigned int flags)
1505 {
1506         u32 reg;
1507         bool update_bssid = false;
1508
1509         if (flags & CONFIG_UPDATE_TYPE) {
1510                 /*
1511                  * Enable synchronisation.
1512                  */
1513                 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
1514                 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, conf->sync);
1515                 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1516
1517                 if (conf->sync == TSF_SYNC_AP_NONE) {
1518                         /*
1519                          * Tune beacon queue transmit parameters for AP mode
1520                          */
1521                         rt2800_register_read(rt2x00dev, TBTT_SYNC_CFG, &reg);
1522                         rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_CWMIN, 0);
1523                         rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_AIFSN, 1);
1524                         rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_EXP_WIN, 32);
1525                         rt2x00_set_field32(&reg, TBTT_SYNC_CFG_TBTT_ADJUST, 0);
1526                         rt2800_register_write(rt2x00dev, TBTT_SYNC_CFG, reg);
1527                 } else {
1528                         rt2800_register_read(rt2x00dev, TBTT_SYNC_CFG, &reg);
1529                         rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_CWMIN, 4);
1530                         rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_AIFSN, 2);
1531                         rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_EXP_WIN, 32);
1532                         rt2x00_set_field32(&reg, TBTT_SYNC_CFG_TBTT_ADJUST, 16);
1533                         rt2800_register_write(rt2x00dev, TBTT_SYNC_CFG, reg);
1534                 }
1535         }
1536
1537         if (flags & CONFIG_UPDATE_MAC) {
1538                 if (flags & CONFIG_UPDATE_TYPE &&
1539                     conf->sync == TSF_SYNC_AP_NONE) {
1540                         /*
1541                          * The BSSID register has to be set to our own mac
1542                          * address in AP mode.
1543                          */
1544                         memcpy(conf->bssid, conf->mac, sizeof(conf->mac));
1545                         update_bssid = true;
1546                 }
1547
1548                 if (!is_zero_ether_addr((const u8 *)conf->mac)) {
1549                         reg = le32_to_cpu(conf->mac[1]);
1550                         rt2x00_set_field32(&reg, MAC_ADDR_DW1_UNICAST_TO_ME_MASK, 0xff);
1551                         conf->mac[1] = cpu_to_le32(reg);
1552                 }
1553
1554                 rt2800_register_multiwrite(rt2x00dev, MAC_ADDR_DW0,
1555                                               conf->mac, sizeof(conf->mac));
1556         }
1557
1558         if ((flags & CONFIG_UPDATE_BSSID) || update_bssid) {
1559                 if (!is_zero_ether_addr((const u8 *)conf->bssid)) {
1560                         reg = le32_to_cpu(conf->bssid[1]);
1561                         rt2x00_set_field32(&reg, MAC_BSSID_DW1_BSS_ID_MASK, 3);
1562                         rt2x00_set_field32(&reg, MAC_BSSID_DW1_BSS_BCN_NUM, 7);
1563                         conf->bssid[1] = cpu_to_le32(reg);
1564                 }
1565
1566                 rt2800_register_multiwrite(rt2x00dev, MAC_BSSID_DW0,
1567                                               conf->bssid, sizeof(conf->bssid));
1568         }
1569 }
1570 EXPORT_SYMBOL_GPL(rt2800_config_intf);
1571
1572 static void rt2800_config_ht_opmode(struct rt2x00_dev *rt2x00dev,
1573                                     struct rt2x00lib_erp *erp)
1574 {
1575         bool any_sta_nongf = !!(erp->ht_opmode &
1576                                 IEEE80211_HT_OP_MODE_NON_GF_STA_PRSNT);
1577         u8 protection = erp->ht_opmode & IEEE80211_HT_OP_MODE_PROTECTION;
1578         u8 mm20_mode, mm40_mode, gf20_mode, gf40_mode;
1579         u16 mm20_rate, mm40_rate, gf20_rate, gf40_rate;
1580         u32 reg;
1581
1582         /* default protection rate for HT20: OFDM 24M */
1583         mm20_rate = gf20_rate = 0x4004;
1584
1585         /* default protection rate for HT40: duplicate OFDM 24M */
1586         mm40_rate = gf40_rate = 0x4084;
1587
1588         switch (protection) {
1589         case IEEE80211_HT_OP_MODE_PROTECTION_NONE:
1590                 /*
1591                  * All STAs in this BSS are HT20/40 but there might be
1592                  * STAs not supporting greenfield mode.
1593                  * => Disable protection for HT transmissions.
1594                  */
1595                 mm20_mode = mm40_mode = gf20_mode = gf40_mode = 0;
1596
1597                 break;
1598         case IEEE80211_HT_OP_MODE_PROTECTION_20MHZ:
1599                 /*
1600                  * All STAs in this BSS are HT20 or HT20/40 but there
1601                  * might be STAs not supporting greenfield mode.
1602                  * => Protect all HT40 transmissions.
1603                  */
1604                 mm20_mode = gf20_mode = 0;
1605                 mm40_mode = gf40_mode = 2;
1606
1607                 break;
1608         case IEEE80211_HT_OP_MODE_PROTECTION_NONMEMBER:
1609                 /*
1610                  * Nonmember protection:
1611                  * According to 802.11n we _should_ protect all
1612                  * HT transmissions (but we don't have to).
1613                  *
1614                  * But if cts_protection is enabled we _shall_ protect
1615                  * all HT transmissions using a CCK rate.
1616                  *
1617                  * And if any station is non GF we _shall_ protect
1618                  * GF transmissions.
1619                  *
1620                  * We decide to protect everything
1621                  * -> fall through to mixed mode.
1622                  */
1623         case IEEE80211_HT_OP_MODE_PROTECTION_NONHT_MIXED:
1624                 /*
1625                  * Legacy STAs are present
1626                  * => Protect all HT transmissions.
1627                  */
1628                 mm20_mode = mm40_mode = gf20_mode = gf40_mode = 2;
1629
1630                 /*
1631                  * If erp protection is needed we have to protect HT
1632                  * transmissions with CCK 11M long preamble.
1633                  */
1634                 if (erp->cts_protection) {
1635                         /* don't duplicate RTS/CTS in CCK mode */
1636                         mm20_rate = mm40_rate = 0x0003;
1637                         gf20_rate = gf40_rate = 0x0003;
1638                 }
1639                 break;
1640         }
1641
1642         /* check for STAs not supporting greenfield mode */
1643         if (any_sta_nongf)
1644                 gf20_mode = gf40_mode = 2;
1645
1646         /* Update HT protection config */
1647         rt2800_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
1648         rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_RATE, mm20_rate);
1649         rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_CTRL, mm20_mode);
1650         rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
1651
1652         rt2800_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
1653         rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_RATE, mm40_rate);
1654         rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_CTRL, mm40_mode);
1655         rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
1656
1657         rt2800_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
1658         rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_RATE, gf20_rate);
1659         rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_CTRL, gf20_mode);
1660         rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
1661
1662         rt2800_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
1663         rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_RATE, gf40_rate);
1664         rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_CTRL, gf40_mode);
1665         rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
1666 }
1667
1668 void rt2800_config_erp(struct rt2x00_dev *rt2x00dev, struct rt2x00lib_erp *erp,
1669                        u32 changed)
1670 {
1671         u32 reg;
1672
1673         if (changed & BSS_CHANGED_ERP_PREAMBLE) {
1674                 rt2800_register_read(rt2x00dev, AUTO_RSP_CFG, &reg);
1675                 rt2x00_set_field32(&reg, AUTO_RSP_CFG_BAC_ACK_POLICY,
1676                                    !!erp->short_preamble);
1677                 rt2x00_set_field32(&reg, AUTO_RSP_CFG_AR_PREAMBLE,
1678                                    !!erp->short_preamble);
1679                 rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
1680         }
1681
1682         if (changed & BSS_CHANGED_ERP_CTS_PROT) {
1683                 rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
1684                 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL,
1685                                    erp->cts_protection ? 2 : 0);
1686                 rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
1687         }
1688
1689         if (changed & BSS_CHANGED_BASIC_RATES) {
1690                 rt2800_register_write(rt2x00dev, LEGACY_BASIC_RATE,
1691                                          erp->basic_rates);
1692                 rt2800_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
1693         }
1694
1695         if (changed & BSS_CHANGED_ERP_SLOT) {
1696                 rt2800_register_read(rt2x00dev, BKOFF_SLOT_CFG, &reg);
1697                 rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_SLOT_TIME,
1698                                    erp->slot_time);
1699                 rt2800_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg);
1700
1701                 rt2800_register_read(rt2x00dev, XIFS_TIME_CFG, &reg);
1702                 rt2x00_set_field32(&reg, XIFS_TIME_CFG_EIFS, erp->eifs);
1703                 rt2800_register_write(rt2x00dev, XIFS_TIME_CFG, reg);
1704         }
1705
1706         if (changed & BSS_CHANGED_BEACON_INT) {
1707                 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
1708                 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL,
1709                                    erp->beacon_int * 16);
1710                 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1711         }
1712
1713         if (changed & BSS_CHANGED_HT)
1714                 rt2800_config_ht_opmode(rt2x00dev, erp);
1715 }
1716 EXPORT_SYMBOL_GPL(rt2800_config_erp);
1717
1718 static void rt2800_config_3572bt_ant(struct rt2x00_dev *rt2x00dev)
1719 {
1720         u32 reg;
1721         u16 eeprom;
1722         u8 led_ctrl, led_g_mode, led_r_mode;
1723
1724         rt2800_register_read(rt2x00dev, GPIO_SWITCH, &reg);
1725         if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ) {
1726                 rt2x00_set_field32(&reg, GPIO_SWITCH_0, 1);
1727                 rt2x00_set_field32(&reg, GPIO_SWITCH_1, 1);
1728         } else {
1729                 rt2x00_set_field32(&reg, GPIO_SWITCH_0, 0);
1730                 rt2x00_set_field32(&reg, GPIO_SWITCH_1, 0);
1731         }
1732         rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg);
1733
1734         rt2800_register_read(rt2x00dev, LED_CFG, &reg);
1735         led_g_mode = rt2x00_get_field32(reg, LED_CFG_LED_POLAR) ? 3 : 0;
1736         led_r_mode = rt2x00_get_field32(reg, LED_CFG_LED_POLAR) ? 0 : 3;
1737         if (led_g_mode != rt2x00_get_field32(reg, LED_CFG_G_LED_MODE) ||
1738             led_r_mode != rt2x00_get_field32(reg, LED_CFG_R_LED_MODE)) {
1739                 rt2800_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom);
1740                 led_ctrl = rt2x00_get_field16(eeprom, EEPROM_FREQ_LED_MODE);
1741                 if (led_ctrl == 0 || led_ctrl > 0x40) {
1742                         rt2x00_set_field32(&reg, LED_CFG_G_LED_MODE, led_g_mode);
1743                         rt2x00_set_field32(&reg, LED_CFG_R_LED_MODE, led_r_mode);
1744                         rt2800_register_write(rt2x00dev, LED_CFG, reg);
1745                 } else {
1746                         rt2800_mcu_request(rt2x00dev, MCU_BAND_SELECT, 0xff,
1747                                            (led_g_mode << 2) | led_r_mode, 1);
1748                 }
1749         }
1750 }
1751
1752 static void rt2800_set_ant_diversity(struct rt2x00_dev *rt2x00dev,
1753                                      enum antenna ant)
1754 {
1755         u32 reg;
1756         u8 eesk_pin = (ant == ANTENNA_A) ? 1 : 0;
1757         u8 gpio_bit3 = (ant == ANTENNA_A) ? 0 : 1;
1758
1759         if (rt2x00_is_pci(rt2x00dev)) {
1760                 rt2800_register_read(rt2x00dev, E2PROM_CSR, &reg);
1761                 rt2x00_set_field32(&reg, E2PROM_CSR_DATA_CLOCK, eesk_pin);
1762                 rt2800_register_write(rt2x00dev, E2PROM_CSR, reg);
1763         } else if (rt2x00_is_usb(rt2x00dev))
1764                 rt2800_mcu_request(rt2x00dev, MCU_ANT_SELECT, 0xff,
1765                                    eesk_pin, 0);
1766
1767         rt2800_register_read(rt2x00dev, GPIO_CTRL, &reg);
1768         rt2x00_set_field32(&reg, GPIO_CTRL_DIR3, 0);
1769         rt2x00_set_field32(&reg, GPIO_CTRL_VAL3, gpio_bit3);
1770         rt2800_register_write(rt2x00dev, GPIO_CTRL, reg);
1771 }
1772
1773 void rt2800_config_ant(struct rt2x00_dev *rt2x00dev, struct antenna_setup *ant)
1774 {
1775         u8 r1;
1776         u8 r3;
1777         u16 eeprom;
1778
1779         rt2800_bbp_read(rt2x00dev, 1, &r1);
1780         rt2800_bbp_read(rt2x00dev, 3, &r3);
1781
1782         if (rt2x00_rt(rt2x00dev, RT3572) &&
1783             test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags))
1784                 rt2800_config_3572bt_ant(rt2x00dev);
1785
1786         /*
1787          * Configure the TX antenna.
1788          */
1789         switch (ant->tx_chain_num) {
1790         case 1:
1791                 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 0);
1792                 break;
1793         case 2:
1794                 if (rt2x00_rt(rt2x00dev, RT3572) &&
1795                     test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags))
1796                         rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 1);
1797                 else
1798                         rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 2);
1799                 break;
1800         case 3:
1801                 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 2);
1802                 break;
1803         }
1804
1805         /*
1806          * Configure the RX antenna.
1807          */
1808         switch (ant->rx_chain_num) {
1809         case 1:
1810                 if (rt2x00_rt(rt2x00dev, RT3070) ||
1811                     rt2x00_rt(rt2x00dev, RT3090) ||
1812                     rt2x00_rt(rt2x00dev, RT3352) ||
1813                     rt2x00_rt(rt2x00dev, RT3390)) {
1814                         rt2800_eeprom_read(rt2x00dev,
1815                                            EEPROM_NIC_CONF1, &eeprom);
1816                         if (rt2x00_get_field16(eeprom,
1817                                                 EEPROM_NIC_CONF1_ANT_DIVERSITY))
1818                                 rt2800_set_ant_diversity(rt2x00dev,
1819                                                 rt2x00dev->default_ant.rx);
1820                 }
1821                 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 0);
1822                 break;
1823         case 2:
1824                 if (rt2x00_rt(rt2x00dev, RT3572) &&
1825                     test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags)) {
1826                         rt2x00_set_field8(&r3, BBP3_RX_ADC, 1);
1827                         rt2x00_set_field8(&r3, BBP3_RX_ANTENNA,
1828                                 rt2x00dev->curr_band == IEEE80211_BAND_5GHZ);
1829                         rt2800_set_ant_diversity(rt2x00dev, ANTENNA_B);
1830                 } else {
1831                         rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 1);
1832                 }
1833                 break;
1834         case 3:
1835                 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 2);
1836                 break;
1837         }
1838
1839         rt2800_bbp_write(rt2x00dev, 3, r3);
1840         rt2800_bbp_write(rt2x00dev, 1, r1);
1841
1842         if (rt2x00_rt(rt2x00dev, RT3593)) {
1843                 if (ant->rx_chain_num == 1)
1844                         rt2800_bbp_write(rt2x00dev, 86, 0x00);
1845                 else
1846                         rt2800_bbp_write(rt2x00dev, 86, 0x46);
1847         }
1848 }
1849 EXPORT_SYMBOL_GPL(rt2800_config_ant);
1850
1851 static void rt2800_config_lna_gain(struct rt2x00_dev *rt2x00dev,
1852                                    struct rt2x00lib_conf *libconf)
1853 {
1854         u16 eeprom;
1855         short lna_gain;
1856
1857         if (libconf->rf.channel <= 14) {
1858                 rt2800_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom);
1859                 lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_BG);
1860         } else if (libconf->rf.channel <= 64) {
1861                 rt2800_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom);
1862                 lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_A0);
1863         } else if (libconf->rf.channel <= 128) {
1864                 if (rt2x00_rt(rt2x00dev, RT3593)) {
1865                         rt2800_eeprom_read(rt2x00dev, EEPROM_EXT_LNA2, &eeprom);
1866                         lna_gain = rt2x00_get_field16(eeprom,
1867                                                       EEPROM_EXT_LNA2_A1);
1868                 } else {
1869                         rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &eeprom);
1870                         lna_gain = rt2x00_get_field16(eeprom,
1871                                                       EEPROM_RSSI_BG2_LNA_A1);
1872                 }
1873         } else {
1874                 if (rt2x00_rt(rt2x00dev, RT3593)) {
1875                         rt2800_eeprom_read(rt2x00dev, EEPROM_EXT_LNA2, &eeprom);
1876                         lna_gain = rt2x00_get_field16(eeprom,
1877                                                       EEPROM_EXT_LNA2_A2);
1878                 } else {
1879                         rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &eeprom);
1880                         lna_gain = rt2x00_get_field16(eeprom,
1881                                                       EEPROM_RSSI_A2_LNA_A2);
1882                 }
1883         }
1884
1885         rt2x00dev->lna_gain = lna_gain;
1886 }
1887
1888 #define FREQ_OFFSET_BOUND       0x5f
1889
1890 static void rt2800_adjust_freq_offset(struct rt2x00_dev *rt2x00dev)
1891 {
1892         u8 freq_offset, prev_freq_offset;
1893         u8 rfcsr, prev_rfcsr;
1894
1895         freq_offset = rt2x00_get_field8(rt2x00dev->freq_offset, RFCSR17_CODE);
1896         freq_offset = min_t(u8, freq_offset, FREQ_OFFSET_BOUND);
1897
1898         rt2800_rfcsr_read(rt2x00dev, 17, &rfcsr);
1899         prev_rfcsr = rfcsr;
1900
1901         rt2x00_set_field8(&rfcsr, RFCSR17_CODE, freq_offset);
1902         if (rfcsr == prev_rfcsr)
1903                 return;
1904
1905         if (rt2x00_is_usb(rt2x00dev)) {
1906                 rt2800_mcu_request(rt2x00dev, MCU_FREQ_OFFSET, 0xff,
1907                                    freq_offset, prev_rfcsr);
1908                 return;
1909         }
1910
1911         prev_freq_offset = rt2x00_get_field8(prev_rfcsr, RFCSR17_CODE);
1912         while (prev_freq_offset != freq_offset) {
1913                 if (prev_freq_offset < freq_offset)
1914                         prev_freq_offset++;
1915                 else
1916                         prev_freq_offset--;
1917
1918                 rt2x00_set_field8(&rfcsr, RFCSR17_CODE, prev_freq_offset);
1919                 rt2800_rfcsr_write(rt2x00dev, 17, rfcsr);
1920
1921                 usleep_range(1000, 1500);
1922         }
1923 }
1924
1925 static void rt2800_config_channel_rf2xxx(struct rt2x00_dev *rt2x00dev,
1926                                          struct ieee80211_conf *conf,
1927                                          struct rf_channel *rf,
1928                                          struct channel_info *info)
1929 {
1930         rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset);
1931
1932         if (rt2x00dev->default_ant.tx_chain_num == 1)
1933                 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_TX1, 1);
1934
1935         if (rt2x00dev->default_ant.rx_chain_num == 1) {
1936                 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX1, 1);
1937                 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
1938         } else if (rt2x00dev->default_ant.rx_chain_num == 2)
1939                 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
1940
1941         if (rf->channel > 14) {
1942                 /*
1943                  * When TX power is below 0, we should increase it by 7 to
1944                  * make it a positive value (Minimum value is -7).
1945                  * However this means that values between 0 and 7 have
1946                  * double meaning, and we should set a 7DBm boost flag.
1947                  */
1948                 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A_7DBM_BOOST,
1949                                    (info->default_power1 >= 0));
1950
1951                 if (info->default_power1 < 0)
1952                         info->default_power1 += 7;
1953
1954                 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A, info->default_power1);
1955
1956                 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A_7DBM_BOOST,
1957                                    (info->default_power2 >= 0));
1958
1959                 if (info->default_power2 < 0)
1960                         info->default_power2 += 7;
1961
1962                 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A, info->default_power2);
1963         } else {
1964                 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_G, info->default_power1);
1965                 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_G, info->default_power2);
1966         }
1967
1968         rt2x00_set_field32(&rf->rf4, RF4_HT40, conf_is_ht40(conf));
1969
1970         rt2800_rf_write(rt2x00dev, 1, rf->rf1);
1971         rt2800_rf_write(rt2x00dev, 2, rf->rf2);
1972         rt2800_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
1973         rt2800_rf_write(rt2x00dev, 4, rf->rf4);
1974
1975         udelay(200);
1976
1977         rt2800_rf_write(rt2x00dev, 1, rf->rf1);
1978         rt2800_rf_write(rt2x00dev, 2, rf->rf2);
1979         rt2800_rf_write(rt2x00dev, 3, rf->rf3 | 0x00000004);
1980         rt2800_rf_write(rt2x00dev, 4, rf->rf4);
1981
1982         udelay(200);
1983
1984         rt2800_rf_write(rt2x00dev, 1, rf->rf1);
1985         rt2800_rf_write(rt2x00dev, 2, rf->rf2);
1986         rt2800_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
1987         rt2800_rf_write(rt2x00dev, 4, rf->rf4);
1988 }
1989
1990 static void rt2800_config_channel_rf3xxx(struct rt2x00_dev *rt2x00dev,
1991                                          struct ieee80211_conf *conf,
1992                                          struct rf_channel *rf,
1993                                          struct channel_info *info)
1994 {
1995         struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
1996         u8 rfcsr, calib_tx, calib_rx;
1997
1998         rt2800_rfcsr_write(rt2x00dev, 2, rf->rf1);
1999
2000         rt2800_rfcsr_read(rt2x00dev, 3, &rfcsr);
2001         rt2x00_set_field8(&rfcsr, RFCSR3_K, rf->rf3);
2002         rt2800_rfcsr_write(rt2x00dev, 3, rfcsr);
2003
2004         rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
2005         rt2x00_set_field8(&rfcsr, RFCSR6_R1, rf->rf2);
2006         rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
2007
2008         rt2800_rfcsr_read(rt2x00dev, 12, &rfcsr);
2009         rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER, info->default_power1);
2010         rt2800_rfcsr_write(rt2x00dev, 12, rfcsr);
2011
2012         rt2800_rfcsr_read(rt2x00dev, 13, &rfcsr);
2013         rt2x00_set_field8(&rfcsr, RFCSR13_TX_POWER, info->default_power2);
2014         rt2800_rfcsr_write(rt2x00dev, 13, rfcsr);
2015
2016         rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
2017         rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0);
2018         rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD,
2019                           rt2x00dev->default_ant.rx_chain_num <= 1);
2020         rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD,
2021                           rt2x00dev->default_ant.rx_chain_num <= 2);
2022         rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0);
2023         rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD,
2024                           rt2x00dev->default_ant.tx_chain_num <= 1);
2025         rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD,
2026                           rt2x00dev->default_ant.tx_chain_num <= 2);
2027         rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
2028
2029         rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
2030         rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 1);
2031         rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
2032         msleep(1);
2033         rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 0);
2034         rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
2035
2036         rt2800_rfcsr_read(rt2x00dev, 23, &rfcsr);
2037         rt2x00_set_field8(&rfcsr, RFCSR23_FREQ_OFFSET, rt2x00dev->freq_offset);
2038         rt2800_rfcsr_write(rt2x00dev, 23, rfcsr);
2039
2040         if (rt2x00_rt(rt2x00dev, RT3390)) {
2041                 calib_tx = conf_is_ht40(conf) ? 0x68 : 0x4f;
2042                 calib_rx = conf_is_ht40(conf) ? 0x6f : 0x4f;
2043         } else {
2044                 if (conf_is_ht40(conf)) {
2045                         calib_tx = drv_data->calibration_bw40;
2046                         calib_rx = drv_data->calibration_bw40;
2047                 } else {
2048                         calib_tx = drv_data->calibration_bw20;
2049                         calib_rx = drv_data->calibration_bw20;
2050                 }
2051         }
2052
2053         rt2800_rfcsr_read(rt2x00dev, 24, &rfcsr);
2054         rt2x00_set_field8(&rfcsr, RFCSR24_TX_CALIB, calib_tx);
2055         rt2800_rfcsr_write(rt2x00dev, 24, rfcsr);
2056
2057         rt2800_rfcsr_read(rt2x00dev, 31, &rfcsr);
2058         rt2x00_set_field8(&rfcsr, RFCSR31_RX_CALIB, calib_rx);
2059         rt2800_rfcsr_write(rt2x00dev, 31, rfcsr);
2060
2061         rt2800_rfcsr_read(rt2x00dev, 7, &rfcsr);
2062         rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1);
2063         rt2800_rfcsr_write(rt2x00dev, 7, rfcsr);
2064
2065         rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
2066         rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 1);
2067         rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
2068         msleep(1);
2069         rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 0);
2070         rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
2071 }
2072
2073 static void rt2800_config_channel_rf3052(struct rt2x00_dev *rt2x00dev,
2074                                          struct ieee80211_conf *conf,
2075                                          struct rf_channel *rf,
2076                                          struct channel_info *info)
2077 {
2078         struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
2079         u8 rfcsr;
2080         u32 reg;
2081
2082         if (rf->channel <= 14) {
2083                 rt2800_bbp_write(rt2x00dev, 25, drv_data->bbp25);
2084                 rt2800_bbp_write(rt2x00dev, 26, drv_data->bbp26);
2085         } else {
2086                 rt2800_bbp_write(rt2x00dev, 25, 0x09);
2087                 rt2800_bbp_write(rt2x00dev, 26, 0xff);
2088         }
2089
2090         rt2800_rfcsr_write(rt2x00dev, 2, rf->rf1);
2091         rt2800_rfcsr_write(rt2x00dev, 3, rf->rf3);
2092
2093         rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
2094         rt2x00_set_field8(&rfcsr, RFCSR6_R1, rf->rf2);
2095         if (rf->channel <= 14)
2096                 rt2x00_set_field8(&rfcsr, RFCSR6_TXDIV, 2);
2097         else
2098                 rt2x00_set_field8(&rfcsr, RFCSR6_TXDIV, 1);
2099         rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
2100
2101         rt2800_rfcsr_read(rt2x00dev, 5, &rfcsr);
2102         if (rf->channel <= 14)
2103                 rt2x00_set_field8(&rfcsr, RFCSR5_R1, 1);
2104         else
2105                 rt2x00_set_field8(&rfcsr, RFCSR5_R1, 2);
2106         rt2800_rfcsr_write(rt2x00dev, 5, rfcsr);
2107
2108         rt2800_rfcsr_read(rt2x00dev, 12, &rfcsr);
2109         if (rf->channel <= 14) {
2110                 rt2x00_set_field8(&rfcsr, RFCSR12_DR0, 3);
2111                 rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER,
2112                                   info->default_power1);
2113         } else {
2114                 rt2x00_set_field8(&rfcsr, RFCSR12_DR0, 7);
2115                 rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER,
2116                                 (info->default_power1 & 0x3) |
2117                                 ((info->default_power1 & 0xC) << 1));
2118         }
2119         rt2800_rfcsr_write(rt2x00dev, 12, rfcsr);
2120
2121         rt2800_rfcsr_read(rt2x00dev, 13, &rfcsr);
2122         if (rf->channel <= 14) {
2123                 rt2x00_set_field8(&rfcsr, RFCSR13_DR0, 3);
2124                 rt2x00_set_field8(&rfcsr, RFCSR13_TX_POWER,
2125                                   info->default_power2);
2126         } else {
2127                 rt2x00_set_field8(&rfcsr, RFCSR13_DR0, 7);
2128                 rt2x00_set_field8(&rfcsr, RFCSR13_TX_POWER,
2129                                 (info->default_power2 & 0x3) |
2130                                 ((info->default_power2 & 0xC) << 1));
2131         }
2132         rt2800_rfcsr_write(rt2x00dev, 13, rfcsr);
2133
2134         rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
2135         rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0);
2136         rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0);
2137         rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 0);
2138         rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 0);
2139         rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 0);
2140         rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 0);
2141         if (test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags)) {
2142                 if (rf->channel <= 14) {
2143                         rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 1);
2144                         rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 1);
2145                 }
2146                 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 1);
2147                 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 1);
2148         } else {
2149                 switch (rt2x00dev->default_ant.tx_chain_num) {
2150                 case 1:
2151                         rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
2152                 case 2:
2153                         rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 1);
2154                         break;
2155                 }
2156
2157                 switch (rt2x00dev->default_ant.rx_chain_num) {
2158                 case 1:
2159                         rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
2160                 case 2:
2161                         rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 1);
2162                         break;
2163                 }
2164         }
2165         rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
2166
2167         rt2800_rfcsr_read(rt2x00dev, 23, &rfcsr);
2168         rt2x00_set_field8(&rfcsr, RFCSR23_FREQ_OFFSET, rt2x00dev->freq_offset);
2169         rt2800_rfcsr_write(rt2x00dev, 23, rfcsr);
2170
2171         if (conf_is_ht40(conf)) {
2172                 rt2800_rfcsr_write(rt2x00dev, 24, drv_data->calibration_bw40);
2173                 rt2800_rfcsr_write(rt2x00dev, 31, drv_data->calibration_bw40);
2174         } else {
2175                 rt2800_rfcsr_write(rt2x00dev, 24, drv_data->calibration_bw20);
2176                 rt2800_rfcsr_write(rt2x00dev, 31, drv_data->calibration_bw20);
2177         }
2178
2179         if (rf->channel <= 14) {
2180                 rt2800_rfcsr_write(rt2x00dev, 7, 0xd8);
2181                 rt2800_rfcsr_write(rt2x00dev, 9, 0xc3);
2182                 rt2800_rfcsr_write(rt2x00dev, 10, 0xf1);
2183                 rt2800_rfcsr_write(rt2x00dev, 11, 0xb9);
2184                 rt2800_rfcsr_write(rt2x00dev, 15, 0x53);
2185                 rfcsr = 0x4c;
2186                 rt2x00_set_field8(&rfcsr, RFCSR16_TXMIXER_GAIN,
2187                                   drv_data->txmixer_gain_24g);
2188                 rt2800_rfcsr_write(rt2x00dev, 16, rfcsr);
2189                 rt2800_rfcsr_write(rt2x00dev, 17, 0x23);
2190                 rt2800_rfcsr_write(rt2x00dev, 19, 0x93);
2191                 rt2800_rfcsr_write(rt2x00dev, 20, 0xb3);
2192                 rt2800_rfcsr_write(rt2x00dev, 25, 0x15);
2193                 rt2800_rfcsr_write(rt2x00dev, 26, 0x85);
2194                 rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
2195                 rt2800_rfcsr_write(rt2x00dev, 29, 0x9b);
2196         } else {
2197                 rt2800_rfcsr_read(rt2x00dev, 7, &rfcsr);
2198                 rt2x00_set_field8(&rfcsr, RFCSR7_BIT2, 1);
2199                 rt2x00_set_field8(&rfcsr, RFCSR7_BIT3, 0);
2200                 rt2x00_set_field8(&rfcsr, RFCSR7_BIT4, 1);
2201                 rt2x00_set_field8(&rfcsr, RFCSR7_BITS67, 0);
2202                 rt2800_rfcsr_write(rt2x00dev, 7, rfcsr);
2203                 rt2800_rfcsr_write(rt2x00dev, 9, 0xc0);
2204                 rt2800_rfcsr_write(rt2x00dev, 10, 0xf1);
2205                 rt2800_rfcsr_write(rt2x00dev, 11, 0x00);
2206                 rt2800_rfcsr_write(rt2x00dev, 15, 0x43);
2207                 rfcsr = 0x7a;
2208                 rt2x00_set_field8(&rfcsr, RFCSR16_TXMIXER_GAIN,
2209                                   drv_data->txmixer_gain_5g);
2210                 rt2800_rfcsr_write(rt2x00dev, 16, rfcsr);
2211                 rt2800_rfcsr_write(rt2x00dev, 17, 0x23);
2212                 if (rf->channel <= 64) {
2213                         rt2800_rfcsr_write(rt2x00dev, 19, 0xb7);
2214                         rt2800_rfcsr_write(rt2x00dev, 20, 0xf6);
2215                         rt2800_rfcsr_write(rt2x00dev, 25, 0x3d);
2216                 } else if (rf->channel <= 128) {
2217                         rt2800_rfcsr_write(rt2x00dev, 19, 0x74);
2218                         rt2800_rfcsr_write(rt2x00dev, 20, 0xf4);
2219                         rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
2220                 } else {
2221                         rt2800_rfcsr_write(rt2x00dev, 19, 0x72);
2222                         rt2800_rfcsr_write(rt2x00dev, 20, 0xf3);
2223                         rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
2224                 }
2225                 rt2800_rfcsr_write(rt2x00dev, 26, 0x87);
2226                 rt2800_rfcsr_write(rt2x00dev, 27, 0x01);
2227                 rt2800_rfcsr_write(rt2x00dev, 29, 0x9f);
2228         }
2229
2230         rt2800_register_read(rt2x00dev, GPIO_CTRL, &reg);
2231         rt2x00_set_field32(&reg, GPIO_CTRL_DIR7, 0);
2232         if (rf->channel <= 14)
2233                 rt2x00_set_field32(&reg, GPIO_CTRL_VAL7, 1);
2234         else
2235                 rt2x00_set_field32(&reg, GPIO_CTRL_VAL7, 0);
2236         rt2800_register_write(rt2x00dev, GPIO_CTRL, reg);
2237
2238         rt2800_rfcsr_read(rt2x00dev, 7, &rfcsr);
2239         rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1);
2240         rt2800_rfcsr_write(rt2x00dev, 7, rfcsr);
2241 }
2242
2243 static void rt2800_config_channel_rf3053(struct rt2x00_dev *rt2x00dev,
2244                                          struct ieee80211_conf *conf,
2245                                          struct rf_channel *rf,
2246                                          struct channel_info *info)
2247 {
2248         struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
2249         u8 txrx_agc_fc;
2250         u8 txrx_h20m;
2251         u8 rfcsr;
2252         u8 bbp;
2253         const bool txbf_enabled = false; /* TODO */
2254
2255         /* TODO: use TX{0,1,2}FinePowerControl values from EEPROM */
2256         rt2800_bbp_read(rt2x00dev, 109, &bbp);
2257         rt2x00_set_field8(&bbp, BBP109_TX0_POWER, 0);
2258         rt2x00_set_field8(&bbp, BBP109_TX1_POWER, 0);
2259         rt2800_bbp_write(rt2x00dev, 109, bbp);
2260
2261         rt2800_bbp_read(rt2x00dev, 110, &bbp);
2262         rt2x00_set_field8(&bbp, BBP110_TX2_POWER, 0);
2263         rt2800_bbp_write(rt2x00dev, 110, bbp);
2264
2265         if (rf->channel <= 14) {
2266                 /* Restore BBP 25 & 26 for 2.4 GHz */
2267                 rt2800_bbp_write(rt2x00dev, 25, drv_data->bbp25);
2268                 rt2800_bbp_write(rt2x00dev, 26, drv_data->bbp26);
2269         } else {
2270                 /* Hard code BBP 25 & 26 for 5GHz */
2271
2272                 /* Enable IQ Phase correction */
2273                 rt2800_bbp_write(rt2x00dev, 25, 0x09);
2274                 /* Setup IQ Phase correction value */
2275                 rt2800_bbp_write(rt2x00dev, 26, 0xff);
2276         }
2277
2278         rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1);
2279         rt2800_rfcsr_write(rt2x00dev, 9, rf->rf3 & 0xf);
2280
2281         rt2800_rfcsr_read(rt2x00dev, 11, &rfcsr);
2282         rt2x00_set_field8(&rfcsr, RFCSR11_R, (rf->rf2 & 0x3));
2283         rt2800_rfcsr_write(rt2x00dev, 11, rfcsr);
2284
2285         rt2800_rfcsr_read(rt2x00dev, 11, &rfcsr);
2286         rt2x00_set_field8(&rfcsr, RFCSR11_PLL_IDOH, 1);
2287         if (rf->channel <= 14)
2288                 rt2x00_set_field8(&rfcsr, RFCSR11_PLL_MOD, 1);
2289         else
2290                 rt2x00_set_field8(&rfcsr, RFCSR11_PLL_MOD, 2);
2291         rt2800_rfcsr_write(rt2x00dev, 11, rfcsr);
2292
2293         rt2800_rfcsr_read(rt2x00dev, 53, &rfcsr);
2294         if (rf->channel <= 14) {
2295                 rfcsr = 0;
2296                 rt2x00_set_field8(&rfcsr, RFCSR53_TX_POWER,
2297                                   info->default_power1 & 0x1f);
2298         } else {
2299                 if (rt2x00_is_usb(rt2x00dev))
2300                         rfcsr = 0x40;
2301
2302                 rt2x00_set_field8(&rfcsr, RFCSR53_TX_POWER,
2303                                   ((info->default_power1 & 0x18) << 1) |
2304                                   (info->default_power1 & 7));
2305         }
2306         rt2800_rfcsr_write(rt2x00dev, 53, rfcsr);
2307
2308         rt2800_rfcsr_read(rt2x00dev, 55, &rfcsr);
2309         if (rf->channel <= 14) {
2310                 rfcsr = 0;
2311                 rt2x00_set_field8(&rfcsr, RFCSR55_TX_POWER,
2312                                   info->default_power2 & 0x1f);
2313         } else {
2314                 if (rt2x00_is_usb(rt2x00dev))
2315                         rfcsr = 0x40;
2316
2317                 rt2x00_set_field8(&rfcsr, RFCSR55_TX_POWER,
2318                                   ((info->default_power2 & 0x18) << 1) |
2319                                   (info->default_power2 & 7));
2320         }
2321         rt2800_rfcsr_write(rt2x00dev, 55, rfcsr);
2322
2323         rt2800_rfcsr_read(rt2x00dev, 54, &rfcsr);
2324         if (rf->channel <= 14) {
2325                 rfcsr = 0;
2326                 rt2x00_set_field8(&rfcsr, RFCSR54_TX_POWER,
2327                                   info->default_power3 & 0x1f);
2328         } else {
2329                 if (rt2x00_is_usb(rt2x00dev))
2330                         rfcsr = 0x40;
2331
2332                 rt2x00_set_field8(&rfcsr, RFCSR54_TX_POWER,
2333                                   ((info->default_power3 & 0x18) << 1) |
2334                                   (info->default_power3 & 7));
2335         }
2336         rt2800_rfcsr_write(rt2x00dev, 54, rfcsr);
2337
2338         rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
2339         rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0);
2340         rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0);
2341         rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 0);
2342         rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 0);
2343         rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 0);
2344         rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 0);
2345         rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
2346         rt2x00_set_field8(&rfcsr, RFCSR1_PLL_PD, 1);
2347
2348         switch (rt2x00dev->default_ant.tx_chain_num) {
2349         case 3:
2350                 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 1);
2351                 /* fallthrough */
2352         case 2:
2353                 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
2354                 /* fallthrough */
2355         case 1:
2356                 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 1);
2357                 break;
2358         }
2359
2360         switch (rt2x00dev->default_ant.rx_chain_num) {
2361         case 3:
2362                 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 1);
2363                 /* fallthrough */
2364         case 2:
2365                 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
2366                 /* fallthrough */
2367         case 1:
2368                 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 1);
2369                 break;
2370         }
2371         rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
2372
2373         rt2800_adjust_freq_offset(rt2x00dev);
2374
2375         if (conf_is_ht40(conf)) {
2376                 txrx_agc_fc = rt2x00_get_field8(drv_data->calibration_bw40,
2377                                                 RFCSR24_TX_AGC_FC);
2378                 txrx_h20m = rt2x00_get_field8(drv_data->calibration_bw40,
2379                                               RFCSR24_TX_H20M);
2380         } else {
2381                 txrx_agc_fc = rt2x00_get_field8(drv_data->calibration_bw20,
2382                                                 RFCSR24_TX_AGC_FC);
2383                 txrx_h20m = rt2x00_get_field8(drv_data->calibration_bw20,
2384                                               RFCSR24_TX_H20M);
2385         }
2386
2387         /* NOTE: the reference driver does not writes the new value
2388          * back to RFCSR 32
2389          */
2390         rt2800_rfcsr_read(rt2x00dev, 32, &rfcsr);
2391         rt2x00_set_field8(&rfcsr, RFCSR32_TX_AGC_FC, txrx_agc_fc);
2392
2393         if (rf->channel <= 14)
2394                 rfcsr = 0xa0;
2395         else
2396                 rfcsr = 0x80;
2397         rt2800_rfcsr_write(rt2x00dev, 31, rfcsr);
2398
2399         rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
2400         rt2x00_set_field8(&rfcsr, RFCSR30_TX_H20M, txrx_h20m);
2401         rt2x00_set_field8(&rfcsr, RFCSR30_RX_H20M, txrx_h20m);
2402         rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
2403
2404         /* Band selection */
2405         rt2800_rfcsr_read(rt2x00dev, 36, &rfcsr);
2406         if (rf->channel <= 14)
2407                 rt2x00_set_field8(&rfcsr, RFCSR36_RF_BS, 1);
2408         else
2409                 rt2x00_set_field8(&rfcsr, RFCSR36_RF_BS, 0);
2410         rt2800_rfcsr_write(rt2x00dev, 36, rfcsr);
2411
2412         rt2800_rfcsr_read(rt2x00dev, 34, &rfcsr);
2413         if (rf->channel <= 14)
2414                 rfcsr = 0x3c;
2415         else
2416                 rfcsr = 0x20;
2417         rt2800_rfcsr_write(rt2x00dev, 34, rfcsr);
2418
2419         rt2800_rfcsr_read(rt2x00dev, 12, &rfcsr);
2420         if (rf->channel <= 14)
2421                 rfcsr = 0x1a;
2422         else
2423                 rfcsr = 0x12;
2424         rt2800_rfcsr_write(rt2x00dev, 12, rfcsr);
2425
2426         rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
2427         if (rf->channel >= 1 && rf->channel <= 14)
2428                 rt2x00_set_field8(&rfcsr, RFCSR6_VCO_IC, 1);
2429         else if (rf->channel >= 36 && rf->channel <= 64)
2430                 rt2x00_set_field8(&rfcsr, RFCSR6_VCO_IC, 2);
2431         else if (rf->channel >= 100 && rf->channel <= 128)
2432                 rt2x00_set_field8(&rfcsr, RFCSR6_VCO_IC, 2);
2433         else
2434                 rt2x00_set_field8(&rfcsr, RFCSR6_VCO_IC, 1);
2435         rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
2436
2437         rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
2438         rt2x00_set_field8(&rfcsr, RFCSR30_RX_VCM, 2);
2439         rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
2440
2441         rt2800_rfcsr_write(rt2x00dev, 46, 0x60);
2442
2443         if (rf->channel <= 14) {
2444                 rt2800_rfcsr_write(rt2x00dev, 10, 0xd3);
2445                 rt2800_rfcsr_write(rt2x00dev, 13, 0x12);
2446         } else {
2447                 rt2800_rfcsr_write(rt2x00dev, 10, 0xd8);
2448                 rt2800_rfcsr_write(rt2x00dev, 13, 0x23);
2449         }
2450
2451         rt2800_rfcsr_read(rt2x00dev, 51, &rfcsr);
2452         rt2x00_set_field8(&rfcsr, RFCSR51_BITS01, 1);
2453         rt2800_rfcsr_write(rt2x00dev, 51, rfcsr);
2454
2455         rt2800_rfcsr_read(rt2x00dev, 51, &rfcsr);
2456         if (rf->channel <= 14) {
2457                 rt2x00_set_field8(&rfcsr, RFCSR51_BITS24, 5);
2458                 rt2x00_set_field8(&rfcsr, RFCSR51_BITS57, 3);
2459         } else {
2460                 rt2x00_set_field8(&rfcsr, RFCSR51_BITS24, 4);
2461                 rt2x00_set_field8(&rfcsr, RFCSR51_BITS57, 2);
2462         }
2463         rt2800_rfcsr_write(rt2x00dev, 51, rfcsr);
2464
2465         rt2800_rfcsr_read(rt2x00dev, 49, &rfcsr);
2466         if (rf->channel <= 14)
2467                 rt2x00_set_field8(&rfcsr, RFCSR49_TX_LO1_IC, 3);
2468         else
2469                 rt2x00_set_field8(&rfcsr, RFCSR49_TX_LO1_IC, 2);
2470
2471         if (txbf_enabled)
2472                 rt2x00_set_field8(&rfcsr, RFCSR49_TX_DIV, 1);
2473
2474         rt2800_rfcsr_write(rt2x00dev, 49, rfcsr);
2475
2476         rt2800_rfcsr_read(rt2x00dev, 50, &rfcsr);
2477         rt2x00_set_field8(&rfcsr, RFCSR50_TX_LO1_EN, 0);
2478         rt2800_rfcsr_write(rt2x00dev, 50, rfcsr);
2479
2480         rt2800_rfcsr_read(rt2x00dev, 57, &rfcsr);
2481         if (rf->channel <= 14)
2482                 rt2x00_set_field8(&rfcsr, RFCSR57_DRV_CC, 0x1b);
2483         else
2484                 rt2x00_set_field8(&rfcsr, RFCSR57_DRV_CC, 0x0f);
2485         rt2800_rfcsr_write(rt2x00dev, 57, rfcsr);
2486
2487         if (rf->channel <= 14) {
2488                 rt2800_rfcsr_write(rt2x00dev, 44, 0x93);
2489                 rt2800_rfcsr_write(rt2x00dev, 52, 0x45);
2490         } else {
2491                 rt2800_rfcsr_write(rt2x00dev, 44, 0x9b);
2492                 rt2800_rfcsr_write(rt2x00dev, 52, 0x05);
2493         }
2494
2495         /* Initiate VCO calibration */
2496         rt2800_rfcsr_read(rt2x00dev, 3, &rfcsr);
2497         if (rf->channel <= 14) {
2498                 rt2x00_set_field8(&rfcsr, RFCSR3_VCOCAL_EN, 1);
2499         } else {
2500                 rt2x00_set_field8(&rfcsr, RFCSR3_BIT1, 1);
2501                 rt2x00_set_field8(&rfcsr, RFCSR3_BIT2, 1);
2502                 rt2x00_set_field8(&rfcsr, RFCSR3_BIT3, 1);
2503                 rt2x00_set_field8(&rfcsr, RFCSR3_BIT4, 1);
2504                 rt2x00_set_field8(&rfcsr, RFCSR3_BIT5, 1);
2505                 rt2x00_set_field8(&rfcsr, RFCSR3_VCOCAL_EN, 1);
2506         }
2507         rt2800_rfcsr_write(rt2x00dev, 3, rfcsr);
2508
2509         if (rf->channel >= 1 && rf->channel <= 14) {
2510                 rfcsr = 0x23;
2511                 if (txbf_enabled)
2512                         rt2x00_set_field8(&rfcsr, RFCSR39_RX_DIV, 1);
2513                 rt2800_rfcsr_write(rt2x00dev, 39, rfcsr);
2514
2515                 rt2800_rfcsr_write(rt2x00dev, 45, 0xbb);
2516         } else if (rf->channel >= 36 && rf->channel <= 64) {
2517                 rfcsr = 0x36;
2518                 if (txbf_enabled)
2519                         rt2x00_set_field8(&rfcsr, RFCSR39_RX_DIV, 1);
2520                 rt2800_rfcsr_write(rt2x00dev, 39, 0x36);
2521
2522                 rt2800_rfcsr_write(rt2x00dev, 45, 0xeb);
2523         } else if (rf->channel >= 100 && rf->channel <= 128) {
2524                 rfcsr = 0x32;
2525                 if (txbf_enabled)
2526                         rt2x00_set_field8(&rfcsr, RFCSR39_RX_DIV, 1);
2527                 rt2800_rfcsr_write(rt2x00dev, 39, rfcsr);
2528
2529                 rt2800_rfcsr_write(rt2x00dev, 45, 0xb3);
2530         } else {
2531                 rfcsr = 0x30;
2532                 if (txbf_enabled)
2533                         rt2x00_set_field8(&rfcsr, RFCSR39_RX_DIV, 1);
2534                 rt2800_rfcsr_write(rt2x00dev, 39, rfcsr);
2535
2536                 rt2800_rfcsr_write(rt2x00dev, 45, 0x9b);
2537         }
2538 }
2539
2540 #define POWER_BOUND             0x27
2541 #define POWER_BOUND_5G          0x2b
2542
2543 static void rt2800_config_channel_rf3290(struct rt2x00_dev *rt2x00dev,
2544                                          struct ieee80211_conf *conf,
2545                                          struct rf_channel *rf,
2546                                          struct channel_info *info)
2547 {
2548         u8 rfcsr;
2549
2550         rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1);
2551         rt2800_rfcsr_write(rt2x00dev, 9, rf->rf3);
2552         rt2800_rfcsr_read(rt2x00dev, 11, &rfcsr);
2553         rt2x00_set_field8(&rfcsr, RFCSR11_R, rf->rf2);
2554         rt2800_rfcsr_write(rt2x00dev, 11, rfcsr);
2555
2556         rt2800_rfcsr_read(rt2x00dev, 49, &rfcsr);
2557         if (info->default_power1 > POWER_BOUND)
2558                 rt2x00_set_field8(&rfcsr, RFCSR49_TX, POWER_BOUND);
2559         else
2560                 rt2x00_set_field8(&rfcsr, RFCSR49_TX, info->default_power1);
2561         rt2800_rfcsr_write(rt2x00dev, 49, rfcsr);
2562
2563         rt2800_adjust_freq_offset(rt2x00dev);
2564
2565         if (rf->channel <= 14) {
2566                 if (rf->channel == 6)
2567                         rt2800_bbp_write(rt2x00dev, 68, 0x0c);
2568                 else
2569                         rt2800_bbp_write(rt2x00dev, 68, 0x0b);
2570
2571                 if (rf->channel >= 1 && rf->channel <= 6)
2572                         rt2800_bbp_write(rt2x00dev, 59, 0x0f);
2573                 else if (rf->channel >= 7 && rf->channel <= 11)
2574                         rt2800_bbp_write(rt2x00dev, 59, 0x0e);
2575                 else if (rf->channel >= 12 && rf->channel <= 14)
2576                         rt2800_bbp_write(rt2x00dev, 59, 0x0d);
2577         }
2578 }
2579
2580 static void rt2800_config_channel_rf3322(struct rt2x00_dev *rt2x00dev,
2581                                          struct ieee80211_conf *conf,
2582                                          struct rf_channel *rf,
2583                                          struct channel_info *info)
2584 {
2585         u8 rfcsr;
2586
2587         rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1);
2588         rt2800_rfcsr_write(rt2x00dev, 9, rf->rf3);
2589
2590         rt2800_rfcsr_write(rt2x00dev, 11, 0x42);
2591         rt2800_rfcsr_write(rt2x00dev, 12, 0x1c);
2592         rt2800_rfcsr_write(rt2x00dev, 13, 0x00);
2593
2594         if (info->default_power1 > POWER_BOUND)
2595                 rt2800_rfcsr_write(rt2x00dev, 47, POWER_BOUND);
2596         else
2597                 rt2800_rfcsr_write(rt2x00dev, 47, info->default_power1);
2598
2599         if (info->default_power2 > POWER_BOUND)
2600                 rt2800_rfcsr_write(rt2x00dev, 48, POWER_BOUND);
2601         else
2602                 rt2800_rfcsr_write(rt2x00dev, 48, info->default_power2);
2603
2604         rt2800_adjust_freq_offset(rt2x00dev);
2605
2606         rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
2607         rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 1);
2608         rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 1);
2609
2610         if ( rt2x00dev->default_ant.tx_chain_num == 2 )
2611                 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
2612         else
2613                 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 0);
2614
2615         if ( rt2x00dev->default_ant.rx_chain_num == 2 )
2616                 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
2617         else
2618                 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 0);
2619
2620         rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 0);
2621         rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 0);
2622
2623         rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
2624
2625         rt2800_rfcsr_write(rt2x00dev, 31, 80);
2626 }
2627
2628 static void rt2800_config_channel_rf53xx(struct rt2x00_dev *rt2x00dev,
2629                                          struct ieee80211_conf *conf,
2630                                          struct rf_channel *rf,
2631                                          struct channel_info *info)
2632 {
2633         u8 rfcsr;
2634
2635         rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1);
2636         rt2800_rfcsr_write(rt2x00dev, 9, rf->rf3);
2637         rt2800_rfcsr_read(rt2x00dev, 11, &rfcsr);
2638         rt2x00_set_field8(&rfcsr, RFCSR11_R, rf->rf2);
2639         rt2800_rfcsr_write(rt2x00dev, 11, rfcsr);
2640
2641         rt2800_rfcsr_read(rt2x00dev, 49, &rfcsr);
2642         if (info->default_power1 > POWER_BOUND)
2643                 rt2x00_set_field8(&rfcsr, RFCSR49_TX, POWER_BOUND);
2644         else
2645                 rt2x00_set_field8(&rfcsr, RFCSR49_TX, info->default_power1);
2646         rt2800_rfcsr_write(rt2x00dev, 49, rfcsr);
2647
2648         if (rt2x00_rt(rt2x00dev, RT5392)) {
2649                 rt2800_rfcsr_read(rt2x00dev, 50, &rfcsr);
2650                 if (info->default_power1 > POWER_BOUND)
2651                         rt2x00_set_field8(&rfcsr, RFCSR50_TX, POWER_BOUND);
2652                 else
2653                         rt2x00_set_field8(&rfcsr, RFCSR50_TX,
2654                                           info->default_power2);
2655                 rt2800_rfcsr_write(rt2x00dev, 50, rfcsr);
2656         }
2657
2658         rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
2659         if (rt2x00_rt(rt2x00dev, RT5392)) {
2660                 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
2661                 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
2662         }
2663         rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
2664         rt2x00_set_field8(&rfcsr, RFCSR1_PLL_PD, 1);
2665         rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 1);
2666         rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 1);
2667         rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
2668
2669         rt2800_adjust_freq_offset(rt2x00dev);
2670
2671         if (rf->channel <= 14) {
2672                 int idx = rf->channel-1;
2673
2674                 if (test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags)) {
2675                         if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) {
2676                                 /* r55/r59 value array of channel 1~14 */
2677                                 static const char r55_bt_rev[] = {0x83, 0x83,
2678                                         0x83, 0x73, 0x73, 0x63, 0x53, 0x53,
2679                                         0x53, 0x43, 0x43, 0x43, 0x43, 0x43};
2680                                 static const char r59_bt_rev[] = {0x0e, 0x0e,
2681                                         0x0e, 0x0e, 0x0e, 0x0b, 0x0a, 0x09,
2682                                         0x07, 0x07, 0x07, 0x07, 0x07, 0x07};
2683
2684                                 rt2800_rfcsr_write(rt2x00dev, 55,
2685                                                    r55_bt_rev[idx]);
2686                                 rt2800_rfcsr_write(rt2x00dev, 59,
2687                                                    r59_bt_rev[idx]);
2688                         } else {
2689                                 static const char r59_bt[] = {0x8b, 0x8b, 0x8b,
2690                                         0x8b, 0x8b, 0x8b, 0x8b, 0x8a, 0x89,
2691                                         0x88, 0x88, 0x86, 0x85, 0x84};
2692
2693                                 rt2800_rfcsr_write(rt2x00dev, 59, r59_bt[idx]);
2694                         }
2695                 } else {
2696                         if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) {
2697                                 static const char r55_nonbt_rev[] = {0x23, 0x23,
2698                                         0x23, 0x23, 0x13, 0x13, 0x03, 0x03,
2699                                         0x03, 0x03, 0x03, 0x03, 0x03, 0x03};
2700                                 static const char r59_nonbt_rev[] = {0x07, 0x07,
2701                                         0x07, 0x07, 0x07, 0x07, 0x07, 0x07,
2702                                         0x07, 0x07, 0x06, 0x05, 0x04, 0x04};
2703
2704                                 rt2800_rfcsr_write(rt2x00dev, 55,
2705                                                    r55_nonbt_rev[idx]);
2706                                 rt2800_rfcsr_write(rt2x00dev, 59,
2707                                                    r59_nonbt_rev[idx]);
2708                         } else if (rt2x00_rt(rt2x00dev, RT5390) ||
2709                                    rt2x00_rt(rt2x00dev, RT5392)) {
2710                                 static const char r59_non_bt[] = {0x8f, 0x8f,
2711                                         0x8f, 0x8f, 0x8f, 0x8f, 0x8f, 0x8d,
2712                                         0x8a, 0x88, 0x88, 0x87, 0x87, 0x86};
2713
2714                                 rt2800_rfcsr_write(rt2x00dev, 59,
2715                                                    r59_non_bt[idx]);
2716                         }
2717                 }
2718         }
2719 }
2720
2721 static void rt2800_config_channel_rf55xx(struct rt2x00_dev *rt2x00dev,
2722                                          struct ieee80211_conf *conf,
2723                                          struct rf_channel *rf,
2724                                          struct channel_info *info)
2725 {
2726         u8 rfcsr, ep_reg;
2727         u32 reg;
2728         int power_bound;
2729
2730         /* TODO */
2731         const bool is_11b = false;
2732         const bool is_type_ep = false;
2733
2734         rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
2735         rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL,
2736                            (rf->channel > 14 || conf_is_ht40(conf)) ? 5 : 0);
2737         rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
2738
2739         /* Order of values on rf_channel entry: N, K, mod, R */
2740         rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1 & 0xff);
2741
2742         rt2800_rfcsr_read(rt2x00dev,  9, &rfcsr);
2743         rt2x00_set_field8(&rfcsr, RFCSR9_K, rf->rf2 & 0xf);
2744         rt2x00_set_field8(&rfcsr, RFCSR9_N, (rf->rf1 & 0x100) >> 8);
2745         rt2x00_set_field8(&rfcsr, RFCSR9_MOD, ((rf->rf3 - 8) & 0x4) >> 2);
2746         rt2800_rfcsr_write(rt2x00dev, 9, rfcsr);
2747
2748         rt2800_rfcsr_read(rt2x00dev, 11, &rfcsr);
2749         rt2x00_set_field8(&rfcsr, RFCSR11_R, rf->rf4 - 1);
2750         rt2x00_set_field8(&rfcsr, RFCSR11_MOD, (rf->rf3 - 8) & 0x3);
2751         rt2800_rfcsr_write(rt2x00dev, 11, rfcsr);
2752
2753         if (rf->channel <= 14) {
2754                 rt2800_rfcsr_write(rt2x00dev, 10, 0x90);
2755                 /* FIXME: RF11 owerwrite ? */
2756                 rt2800_rfcsr_write(rt2x00dev, 11, 0x4A);
2757                 rt2800_rfcsr_write(rt2x00dev, 12, 0x52);
2758                 rt2800_rfcsr_write(rt2x00dev, 13, 0x42);
2759                 rt2800_rfcsr_write(rt2x00dev, 22, 0x40);
2760                 rt2800_rfcsr_write(rt2x00dev, 24, 0x4A);
2761                 rt2800_rfcsr_write(rt2x00dev, 25, 0x80);
2762                 rt2800_rfcsr_write(rt2x00dev, 27, 0x42);
2763                 rt2800_rfcsr_write(rt2x00dev, 36, 0x80);
2764                 rt2800_rfcsr_write(rt2x00dev, 37, 0x08);
2765                 rt2800_rfcsr_write(rt2x00dev, 38, 0x89);
2766                 rt2800_rfcsr_write(rt2x00dev, 39, 0x1B);
2767                 rt2800_rfcsr_write(rt2x00dev, 40, 0x0D);
2768                 rt2800_rfcsr_write(rt2x00dev, 41, 0x9B);
2769                 rt2800_rfcsr_write(rt2x00dev, 42, 0xD5);
2770                 rt2800_rfcsr_write(rt2x00dev, 43, 0x72);
2771                 rt2800_rfcsr_write(rt2x00dev, 44, 0x0E);
2772                 rt2800_rfcsr_write(rt2x00dev, 45, 0xA2);
2773                 rt2800_rfcsr_write(rt2x00dev, 46, 0x6B);
2774                 rt2800_rfcsr_write(rt2x00dev, 48, 0x10);
2775                 rt2800_rfcsr_write(rt2x00dev, 51, 0x3E);
2776                 rt2800_rfcsr_write(rt2x00dev, 52, 0x48);
2777                 rt2800_rfcsr_write(rt2x00dev, 54, 0x38);
2778                 rt2800_rfcsr_write(rt2x00dev, 56, 0xA1);
2779                 rt2800_rfcsr_write(rt2x00dev, 57, 0x00);
2780                 rt2800_rfcsr_write(rt2x00dev, 58, 0x39);
2781                 rt2800_rfcsr_write(rt2x00dev, 60, 0x45);
2782                 rt2800_rfcsr_write(rt2x00dev, 61, 0x91);
2783                 rt2800_rfcsr_write(rt2x00dev, 62, 0x39);
2784
2785                 /* TODO RF27 <- tssi */
2786
2787                 rfcsr = rf->channel <= 10 ? 0x07 : 0x06;
2788                 rt2800_rfcsr_write(rt2x00dev, 23, rfcsr);
2789                 rt2800_rfcsr_write(rt2x00dev, 59, rfcsr);
2790
2791                 if (is_11b) {
2792                         /* CCK */
2793                         rt2800_rfcsr_write(rt2x00dev, 31, 0xF8);
2794                         rt2800_rfcsr_write(rt2x00dev, 32, 0xC0);
2795                         if (is_type_ep)
2796                                 rt2800_rfcsr_write(rt2x00dev, 55, 0x06);
2797                         else
2798                                 rt2800_rfcsr_write(rt2x00dev, 55, 0x47);
2799                 } else {
2800                         /* OFDM */
2801                         if (is_type_ep)
2802                                 rt2800_rfcsr_write(rt2x00dev, 55, 0x03);
2803                         else
2804                                 rt2800_rfcsr_write(rt2x00dev, 55, 0x43);
2805                 }
2806
2807                 power_bound = POWER_BOUND;
2808                 ep_reg = 0x2;
2809         } else {
2810                 rt2800_rfcsr_write(rt2x00dev, 10, 0x97);
2811                 /* FIMXE: RF11 overwrite */
2812                 rt2800_rfcsr_write(rt2x00dev, 11, 0x40);
2813                 rt2800_rfcsr_write(rt2x00dev, 25, 0xBF);
2814                 rt2800_rfcsr_write(rt2x00dev, 27, 0x42);
2815                 rt2800_rfcsr_write(rt2x00dev, 36, 0x00);
2816                 rt2800_rfcsr_write(rt2x00dev, 37, 0x04);
2817                 rt2800_rfcsr_write(rt2x00dev, 38, 0x85);
2818                 rt2800_rfcsr_write(rt2x00dev, 40, 0x42);
2819                 rt2800_rfcsr_write(rt2x00dev, 41, 0xBB);
2820                 rt2800_rfcsr_write(rt2x00dev, 42, 0xD7);
2821                 rt2800_rfcsr_write(rt2x00dev, 45, 0x41);
2822                 rt2800_rfcsr_write(rt2x00dev, 48, 0x00);
2823                 rt2800_rfcsr_write(rt2x00dev, 57, 0x77);
2824                 rt2800_rfcsr_write(rt2x00dev, 60, 0x05);
2825                 rt2800_rfcsr_write(rt2x00dev, 61, 0x01);
2826
2827                 /* TODO RF27 <- tssi */
2828
2829                 if (rf->channel >= 36 && rf->channel <= 64) {
2830
2831                         rt2800_rfcsr_write(rt2x00dev, 12, 0x2E);
2832                         rt2800_rfcsr_write(rt2x00dev, 13, 0x22);
2833                         rt2800_rfcsr_write(rt2x00dev, 22, 0x60);
2834                         rt2800_rfcsr_write(rt2x00dev, 23, 0x7F);
2835                         if (rf->channel <= 50)
2836                                 rt2800_rfcsr_write(rt2x00dev, 24, 0x09);
2837                         else if (rf->channel >= 52)
2838                                 rt2800_rfcsr_write(rt2x00dev, 24, 0x07);
2839                         rt2800_rfcsr_write(rt2x00dev, 39, 0x1C);
2840                         rt2800_rfcsr_write(rt2x00dev, 43, 0x5B);
2841                         rt2800_rfcsr_write(rt2x00dev, 44, 0X40);
2842                         rt2800_rfcsr_write(rt2x00dev, 46, 0X00);
2843                         rt2800_rfcsr_write(rt2x00dev, 51, 0xFE);
2844                         rt2800_rfcsr_write(rt2x00dev, 52, 0x0C);
2845                         rt2800_rfcsr_write(rt2x00dev, 54, 0xF8);
2846                         if (rf->channel <= 50) {
2847                                 rt2800_rfcsr_write(rt2x00dev, 55, 0x06),
2848                                 rt2800_rfcsr_write(rt2x00dev, 56, 0xD3);
2849                         } else if (rf->channel >= 52) {
2850                                 rt2800_rfcsr_write(rt2x00dev, 55, 0x04);
2851                                 rt2800_rfcsr_write(rt2x00dev, 56, 0xBB);
2852                         }
2853
2854                         rt2800_rfcsr_write(rt2x00dev, 58, 0x15);
2855                         rt2800_rfcsr_write(rt2x00dev, 59, 0x7F);
2856                         rt2800_rfcsr_write(rt2x00dev, 62, 0x15);
2857
2858                 } else if (rf->channel >= 100 && rf->channel <= 165) {
2859
2860                         rt2800_rfcsr_write(rt2x00dev, 12, 0x0E);
2861                         rt2800_rfcsr_write(rt2x00dev, 13, 0x42);
2862                         rt2800_rfcsr_write(rt2x00dev, 22, 0x40);
2863                         if (rf->channel <= 153) {
2864                                 rt2800_rfcsr_write(rt2x00dev, 23, 0x3C);
2865                                 rt2800_rfcsr_write(rt2x00dev, 24, 0x06);
2866                         } else if (rf->channel >= 155) {
2867                                 rt2800_rfcsr_write(rt2x00dev, 23, 0x38);
2868                                 rt2800_rfcsr_write(rt2x00dev, 24, 0x05);
2869                         }
2870                         if (rf->channel <= 138) {
2871                                 rt2800_rfcsr_write(rt2x00dev, 39, 0x1A);
2872                                 rt2800_rfcsr_write(rt2x00dev, 43, 0x3B);
2873                                 rt2800_rfcsr_write(rt2x00dev, 44, 0x20);
2874                                 rt2800_rfcsr_write(rt2x00dev, 46, 0x18);
2875                         } else if (rf->channel >= 140) {
2876                                 rt2800_rfcsr_write(rt2x00dev, 39, 0x18);
2877                                 rt2800_rfcsr_write(rt2x00dev, 43, 0x1B);
2878                                 rt2800_rfcsr_write(rt2x00dev, 44, 0x10);
2879                                 rt2800_rfcsr_write(rt2x00dev, 46, 0X08);
2880                         }
2881                         if (rf->channel <= 124)
2882                                 rt2800_rfcsr_write(rt2x00dev, 51, 0xFC);
2883                         else if (rf->channel >= 126)
2884                                 rt2800_rfcsr_write(rt2x00dev, 51, 0xEC);
2885                         if (rf->channel <= 138)
2886                                 rt2800_rfcsr_write(rt2x00dev, 52, 0x06);
2887                         else if (rf->channel >= 140)
2888                                 rt2800_rfcsr_write(rt2x00dev, 52, 0x06);
2889                         rt2800_rfcsr_write(rt2x00dev, 54, 0xEB);
2890                         if (rf->channel <= 138)
2891                                 rt2800_rfcsr_write(rt2x00dev, 55, 0x01);
2892                         else if (rf->channel >= 140)
2893                                 rt2800_rfcsr_write(rt2x00dev, 55, 0x00);
2894                         if (rf->channel <= 128)
2895                                 rt2800_rfcsr_write(rt2x00dev, 56, 0xBB);
2896                         else if (rf->channel >= 130)
2897                                 rt2800_rfcsr_write(rt2x00dev, 56, 0xAB);
2898                         if (rf->channel <= 116)
2899                                 rt2800_rfcsr_write(rt2x00dev, 58, 0x1D);
2900                         else if (rf->channel >= 118)
2901                                 rt2800_rfcsr_write(rt2x00dev, 58, 0x15);
2902                         if (rf->channel <= 138)
2903                                 rt2800_rfcsr_write(rt2x00dev, 59, 0x3F);
2904                         else if (rf->channel >= 140)
2905                                 rt2800_rfcsr_write(rt2x00dev, 59, 0x7C);
2906                         if (rf->channel <= 116)
2907                                 rt2800_rfcsr_write(rt2x00dev, 62, 0x1D);
2908                         else if (rf->channel >= 118)
2909                                 rt2800_rfcsr_write(rt2x00dev, 62, 0x15);
2910                 }
2911
2912                 power_bound = POWER_BOUND_5G;
2913                 ep_reg = 0x3;
2914         }
2915
2916         rt2800_rfcsr_read(rt2x00dev, 49, &rfcsr);
2917         if (info->default_power1 > power_bound)
2918                 rt2x00_set_field8(&rfcsr, RFCSR49_TX, power_bound);
2919         else
2920                 rt2x00_set_field8(&rfcsr, RFCSR49_TX, info->default_power1);
2921         if (is_type_ep)
2922                 rt2x00_set_field8(&rfcsr, RFCSR49_EP, ep_reg);
2923         rt2800_rfcsr_write(rt2x00dev, 49, rfcsr);
2924
2925         rt2800_rfcsr_read(rt2x00dev, 50, &rfcsr);
2926         if (info->default_power2 > power_bound)
2927                 rt2x00_set_field8(&rfcsr, RFCSR50_TX, power_bound);
2928         else
2929                 rt2x00_set_field8(&rfcsr, RFCSR50_TX, info->default_power2);
2930         if (is_type_ep)
2931                 rt2x00_set_field8(&rfcsr, RFCSR50_EP, ep_reg);
2932         rt2800_rfcsr_write(rt2x00dev, 50, rfcsr);
2933
2934         rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
2935         rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
2936         rt2x00_set_field8(&rfcsr, RFCSR1_PLL_PD, 1);
2937
2938         rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD,
2939                           rt2x00dev->default_ant.tx_chain_num >= 1);
2940         rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD,
2941                           rt2x00dev->default_ant.tx_chain_num == 2);
2942         rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 0);
2943
2944         rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD,
2945                           rt2x00dev->default_ant.rx_chain_num >= 1);
2946         rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD,
2947                           rt2x00dev->default_ant.rx_chain_num == 2);
2948         rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 0);
2949
2950         rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
2951         rt2800_rfcsr_write(rt2x00dev, 6, 0xe4);
2952
2953         if (conf_is_ht40(conf))
2954                 rt2800_rfcsr_write(rt2x00dev, 30, 0x16);
2955         else
2956                 rt2800_rfcsr_write(rt2x00dev, 30, 0x10);
2957
2958         if (!is_11b) {
2959                 rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
2960                 rt2800_rfcsr_write(rt2x00dev, 32, 0x80);
2961         }
2962
2963         /* TODO proper frequency adjustment */
2964         rt2800_adjust_freq_offset(rt2x00dev);
2965
2966         /* TODO merge with others */
2967         rt2800_rfcsr_read(rt2x00dev, 3, &rfcsr);
2968         rt2x00_set_field8(&rfcsr, RFCSR3_VCOCAL_EN, 1);
2969         rt2800_rfcsr_write(rt2x00dev, 3, rfcsr);
2970
2971         /* BBP settings */
2972         rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain);
2973         rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain);
2974         rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain);
2975
2976         rt2800_bbp_write(rt2x00dev, 79, (rf->channel <= 14) ? 0x1C : 0x18);
2977         rt2800_bbp_write(rt2x00dev, 80, (rf->channel <= 14) ? 0x0E : 0x08);
2978         rt2800_bbp_write(rt2x00dev, 81, (rf->channel <= 14) ? 0x3A : 0x38);
2979         rt2800_bbp_write(rt2x00dev, 82, (rf->channel <= 14) ? 0x62 : 0x92);
2980
2981         /* GLRT band configuration */
2982         rt2800_bbp_write(rt2x00dev, 195, 128);
2983         rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0xE0 : 0xF0);
2984         rt2800_bbp_write(rt2x00dev, 195, 129);
2985         rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0x1F : 0x1E);
2986         rt2800_bbp_write(rt2x00dev, 195, 130);
2987         rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0x38 : 0x28);
2988         rt2800_bbp_write(rt2x00dev, 195, 131);
2989         rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0x32 : 0x20);
2990         rt2800_bbp_write(rt2x00dev, 195, 133);
2991         rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0x28 : 0x7F);
2992         rt2800_bbp_write(rt2x00dev, 195, 124);
2993         rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0x19 : 0x7F);
2994 }
2995
2996 static void rt2800_bbp_write_with_rx_chain(struct rt2x00_dev *rt2x00dev,
2997                                            const unsigned int word,
2998                                            const u8 value)
2999 {
3000         u8 chain, reg;
3001
3002         for (chain = 0; chain < rt2x00dev->default_ant.rx_chain_num; chain++) {
3003                 rt2800_bbp_read(rt2x00dev, 27, &reg);
3004                 rt2x00_set_field8(&reg,  BBP27_RX_CHAIN_SEL, chain);
3005                 rt2800_bbp_write(rt2x00dev, 27, reg);
3006
3007                 rt2800_bbp_write(rt2x00dev, word, value);
3008         }
3009 }
3010
3011 static void rt2800_iq_calibrate(struct rt2x00_dev *rt2x00dev, int channel)
3012 {
3013         u8 cal;
3014
3015         /* TX0 IQ Gain */
3016         rt2800_bbp_write(rt2x00dev, 158, 0x2c);
3017         if (channel <= 14)
3018                 cal = rt2x00_eeprom_byte(rt2x00dev, EEPROM_IQ_GAIN_CAL_TX0_2G);
3019         else if (channel >= 36 && channel <= 64)
3020                 cal = rt2x00_eeprom_byte(rt2x00dev,
3021                                          EEPROM_IQ_GAIN_CAL_TX0_CH36_TO_CH64_5G);
3022         else if (channel >= 100 && channel <= 138)
3023                 cal = rt2x00_eeprom_byte(rt2x00dev,
3024                                          EEPROM_IQ_GAIN_CAL_TX0_CH100_TO_CH138_5G);
3025         else if (channel >= 140 && channel <= 165)
3026                 cal = rt2x00_eeprom_byte(rt2x00dev,
3027                                          EEPROM_IQ_GAIN_CAL_TX0_CH140_TO_CH165_5G);
3028         else
3029                 cal = 0;
3030         rt2800_bbp_write(rt2x00dev, 159, cal);
3031
3032         /* TX0 IQ Phase */
3033         rt2800_bbp_write(rt2x00dev, 158, 0x2d);
3034         if (channel <= 14)
3035                 cal = rt2x00_eeprom_byte(rt2x00dev, EEPROM_IQ_PHASE_CAL_TX0_2G);
3036         else if (channel >= 36 && channel <= 64)
3037                 cal = rt2x00_eeprom_byte(rt2x00dev,
3038                                          EEPROM_IQ_PHASE_CAL_TX0_CH36_TO_CH64_5G);
3039         else if (channel >= 100 && channel <= 138)
3040                 cal = rt2x00_eeprom_byte(rt2x00dev,
3041                                          EEPROM_IQ_PHASE_CAL_TX0_CH100_TO_CH138_5G);
3042         else if (channel >= 140 && channel <= 165)
3043                 cal = rt2x00_eeprom_byte(rt2x00dev,
3044                                          EEPROM_IQ_PHASE_CAL_TX0_CH140_TO_CH165_5G);
3045         else
3046                 cal = 0;
3047         rt2800_bbp_write(rt2x00dev, 159, cal);
3048
3049         /* TX1 IQ Gain */
3050         rt2800_bbp_write(rt2x00dev, 158, 0x4a);
3051         if (channel <= 14)
3052                 cal = rt2x00_eeprom_byte(rt2x00dev, EEPROM_IQ_GAIN_CAL_TX1_2G);
3053         else if (channel >= 36 && channel <= 64)
3054                 cal = rt2x00_eeprom_byte(rt2x00dev,
3055                                          EEPROM_IQ_GAIN_CAL_TX1_CH36_TO_CH64_5G);
3056         else if (channel >= 100 && channel <= 138)
3057                 cal = rt2x00_eeprom_byte(rt2x00dev,
3058                                          EEPROM_IQ_GAIN_CAL_TX1_CH100_TO_CH138_5G);
3059         else if (channel >= 140 && channel <= 165)
3060                 cal = rt2x00_eeprom_byte(rt2x00dev,
3061                                          EEPROM_IQ_GAIN_CAL_TX1_CH140_TO_CH165_5G);
3062         else
3063                 cal = 0;
3064         rt2800_bbp_write(rt2x00dev, 159, cal);
3065
3066         /* TX1 IQ Phase */
3067         rt2800_bbp_write(rt2x00dev, 158, 0x4b);
3068         if (channel <= 14)
3069                 cal = rt2x00_eeprom_byte(rt2x00dev, EEPROM_IQ_PHASE_CAL_TX1_2G);
3070         else if (channel >= 36 && channel <= 64)
3071                 cal = rt2x00_eeprom_byte(rt2x00dev,
3072                                          EEPROM_IQ_PHASE_CAL_TX1_CH36_TO_CH64_5G);
3073         else if (channel >= 100 && channel <= 138)
3074                 cal = rt2x00_eeprom_byte(rt2x00dev,
3075                                          EEPROM_IQ_PHASE_CAL_TX1_CH100_TO_CH138_5G);
3076         else if (channel >= 140 && channel <= 165)
3077                 cal = rt2x00_eeprom_byte(rt2x00dev,
3078                                          EEPROM_IQ_PHASE_CAL_TX1_CH140_TO_CH165_5G);
3079         else
3080                 cal = 0;
3081         rt2800_bbp_write(rt2x00dev, 159, cal);
3082
3083         /* FIXME: possible RX0, RX1 callibration ? */
3084
3085         /* RF IQ compensation control */
3086         rt2800_bbp_write(rt2x00dev, 158, 0x04);
3087         cal = rt2x00_eeprom_byte(rt2x00dev, EEPROM_RF_IQ_COMPENSATION_CONTROL);
3088         rt2800_bbp_write(rt2x00dev, 159, cal != 0xff ? cal : 0);
3089
3090         /* RF IQ imbalance compensation control */
3091         rt2800_bbp_write(rt2x00dev, 158, 0x03);
3092         cal = rt2x00_eeprom_byte(rt2x00dev,
3093                                  EEPROM_RF_IQ_IMBALANCE_COMPENSATION_CONTROL);
3094         rt2800_bbp_write(rt2x00dev, 159, cal != 0xff ? cal : 0);
3095 }
3096
3097 static char rt2800_txpower_to_dev(struct rt2x00_dev *rt2x00dev,
3098                                   unsigned int channel,
3099                                   char txpower)
3100 {
3101         if (rt2x00_rt(rt2x00dev, RT3593))
3102                 txpower = rt2x00_get_field8(txpower, EEPROM_TXPOWER_ALC);
3103
3104         if (channel <= 14)
3105                 return clamp_t(char, txpower, MIN_G_TXPOWER, MAX_G_TXPOWER);
3106
3107         if (rt2x00_rt(rt2x00dev, RT3593))
3108                 return clamp_t(char, txpower, MIN_A_TXPOWER_3593,
3109                                MAX_A_TXPOWER_3593);
3110         else
3111                 return clamp_t(char, txpower, MIN_A_TXPOWER, MAX_A_TXPOWER);
3112 }
3113
3114 static void rt2800_config_channel(struct rt2x00_dev *rt2x00dev,
3115                                   struct ieee80211_conf *conf,
3116                                   struct rf_channel *rf,
3117                                   struct channel_info *info)
3118 {
3119         u32 reg;
3120         unsigned int tx_pin;
3121         u8 bbp, rfcsr;
3122
3123         info->default_power1 = rt2800_txpower_to_dev(rt2x00dev, rf->channel,
3124                                                      info->default_power1);
3125         info->default_power2 = rt2800_txpower_to_dev(rt2x00dev, rf->channel,
3126                                                      info->default_power2);
3127         if (rt2x00dev->default_ant.tx_chain_num > 2)
3128                 info->default_power3 =
3129                         rt2800_txpower_to_dev(rt2x00dev, rf->channel,
3130                                               info->default_power3);
3131
3132         switch (rt2x00dev->chip.rf) {
3133         case RF2020:
3134         case RF3020:
3135         case RF3021:
3136         case RF3022:
3137         case RF3320:
3138                 rt2800_config_channel_rf3xxx(rt2x00dev, conf, rf, info);
3139                 break;
3140         case RF3052:
3141                 rt2800_config_channel_rf3052(rt2x00dev, conf, rf, info);
3142                 break;
3143         case RF3053:
3144                 rt2800_config_channel_rf3053(rt2x00dev, conf, rf, info);
3145                 break;
3146         case RF3290:
3147                 rt2800_config_channel_rf3290(rt2x00dev, conf, rf, info);
3148                 break;
3149         case RF3322:
3150                 rt2800_config_channel_rf3322(rt2x00dev, conf, rf, info);
3151                 break;
3152         case RF3070:
3153         case RF5360:
3154         case RF5370:
3155         case RF5372:
3156         case RF5390:
3157         case RF5392:
3158                 rt2800_config_channel_rf53xx(rt2x00dev, conf, rf, info);
3159                 break;
3160         case RF5592:
3161                 rt2800_config_channel_rf55xx(rt2x00dev, conf, rf, info);
3162                 break;
3163         default:
3164                 rt2800_config_channel_rf2xxx(rt2x00dev, conf, rf, info);
3165         }
3166
3167         if (rt2x00_rf(rt2x00dev, RF3070) ||
3168             rt2x00_rf(rt2x00dev, RF3290) ||
3169             rt2x00_rf(rt2x00dev, RF3322) ||
3170             rt2x00_rf(rt2x00dev, RF5360) ||
3171             rt2x00_rf(rt2x00dev, RF5370) ||
3172             rt2x00_rf(rt2x00dev, RF5372) ||
3173             rt2x00_rf(rt2x00dev, RF5390) ||
3174             rt2x00_rf(rt2x00dev, RF5392)) {
3175                 rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
3176                 rt2x00_set_field8(&rfcsr, RFCSR30_TX_H20M, 0);
3177                 rt2x00_set_field8(&rfcsr, RFCSR30_RX_H20M, 0);
3178                 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
3179
3180                 rt2800_rfcsr_read(rt2x00dev, 3, &rfcsr);
3181                 rt2x00_set_field8(&rfcsr, RFCSR3_VCOCAL_EN, 1);
3182                 rt2800_rfcsr_write(rt2x00dev, 3, rfcsr);
3183         }
3184
3185         /*
3186          * Change BBP settings
3187          */
3188         if (rt2x00_rt(rt2x00dev, RT3352)) {
3189                 rt2800_bbp_write(rt2x00dev, 27, 0x0);
3190                 rt2800_bbp_write(rt2x00dev, 66, 0x26 + rt2x00dev->lna_gain);
3191                 rt2800_bbp_write(rt2x00dev, 27, 0x20);
3192                 rt2800_bbp_write(rt2x00dev, 66, 0x26 + rt2x00dev->lna_gain);
3193         } else if (rt2x00_rt(rt2x00dev, RT3593)) {
3194                 if (rf->channel > 14) {
3195                         /* Disable CCK Packet detection on 5GHz */
3196                         rt2800_bbp_write(rt2x00dev, 70, 0x00);
3197                 } else {
3198                         rt2800_bbp_write(rt2x00dev, 70, 0x0a);
3199                 }
3200
3201                 if (conf_is_ht40(conf))
3202                         rt2800_bbp_write(rt2x00dev, 105, 0x04);
3203                 else
3204                         rt2800_bbp_write(rt2x00dev, 105, 0x34);
3205
3206                 rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain);
3207                 rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain);
3208                 rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain);
3209                 rt2800_bbp_write(rt2x00dev, 77, 0x98);
3210         } else {
3211                 rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain);
3212                 rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain);
3213                 rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain);
3214                 rt2800_bbp_write(rt2x00dev, 86, 0);
3215         }
3216
3217         if (rf->channel <= 14) {
3218                 if (!rt2x00_rt(rt2x00dev, RT5390) &&
3219                     !rt2x00_rt(rt2x00dev, RT5392)) {
3220                         if (test_bit(CAPABILITY_EXTERNAL_LNA_BG,
3221                                      &rt2x00dev->cap_flags)) {
3222                                 rt2800_bbp_write(rt2x00dev, 82, 0x62);
3223                                 rt2800_bbp_write(rt2x00dev, 75, 0x46);
3224                         } else {
3225                                 if (rt2x00_rt(rt2x00dev, RT3593))
3226                                         rt2800_bbp_write(rt2x00dev, 82, 0x62);
3227                                 else
3228                                         rt2800_bbp_write(rt2x00dev, 82, 0x84);
3229                                 rt2800_bbp_write(rt2x00dev, 75, 0x50);
3230                         }
3231                         if (rt2x00_rt(rt2x00dev, RT3593))
3232                                 rt2800_bbp_write(rt2x00dev, 83, 0x8a);
3233                 }
3234
3235         } else {
3236                 if (rt2x00_rt(rt2x00dev, RT3572))
3237                         rt2800_bbp_write(rt2x00dev, 82, 0x94);
3238                 else if (rt2x00_rt(rt2x00dev, RT3593))
3239                         rt2800_bbp_write(rt2x00dev, 82, 0x82);
3240                 else
3241                         rt2800_bbp_write(rt2x00dev, 82, 0xf2);
3242
3243                 if (rt2x00_rt(rt2x00dev, RT3593))
3244                         rt2800_bbp_write(rt2x00dev, 83, 0x9a);
3245
3246                 if (test_bit(CAPABILITY_EXTERNAL_LNA_A, &rt2x00dev->cap_flags))
3247                         rt2800_bbp_write(rt2x00dev, 75, 0x46);
3248                 else
3249                         rt2800_bbp_write(rt2x00dev, 75, 0x50);
3250         }
3251
3252         rt2800_register_read(rt2x00dev, TX_BAND_CFG, &reg);
3253         rt2x00_set_field32(&reg, TX_BAND_CFG_HT40_MINUS, conf_is_ht40_minus(conf));
3254         rt2x00_set_field32(&reg, TX_BAND_CFG_A, rf->channel > 14);
3255         rt2x00_set_field32(&reg, TX_BAND_CFG_BG, rf->channel <= 14);
3256         rt2800_register_write(rt2x00dev, TX_BAND_CFG, reg);
3257
3258         if (rt2x00_rt(rt2x00dev, RT3572))
3259                 rt2800_rfcsr_write(rt2x00dev, 8, 0);
3260
3261         tx_pin = 0;
3262
3263         switch (rt2x00dev->default_ant.tx_chain_num) {
3264         case 3:
3265                 /* Turn on tertiary PAs */
3266                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A2_EN,
3267                                    rf->channel > 14);
3268                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G2_EN,
3269                                    rf->channel <= 14);
3270                 /* fall-through */
3271         case 2:
3272                 /* Turn on secondary PAs */
3273                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A1_EN,
3274                                    rf->channel > 14);
3275                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G1_EN,
3276                                    rf->channel <= 14);
3277                 /* fall-through */
3278         case 1:
3279                 /* Turn on primary PAs */
3280                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A0_EN,
3281                                    rf->channel > 14);
3282                 if (test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags))
3283                         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN, 1);
3284                 else
3285                         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN,
3286                                            rf->channel <= 14);
3287                 break;
3288         }
3289
3290         switch (rt2x00dev->default_ant.rx_chain_num) {
3291         case 3:
3292                 /* Turn on tertiary LNAs */
3293                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A2_EN, 1);
3294                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G2_EN, 1);
3295                 /* fall-through */
3296         case 2:
3297                 /* Turn on secondary LNAs */
3298                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A1_EN, 1);
3299                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G1_EN, 1);
3300                 /* fall-through */
3301         case 1:
3302                 /* Turn on primary LNAs */
3303                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A0_EN, 1);
3304                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G0_EN, 1);
3305                 break;
3306         }
3307
3308         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_RFTR_EN, 1);
3309         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_TRSW_EN, 1);
3310
3311         rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin);
3312
3313         if (rt2x00_rt(rt2x00dev, RT3572))
3314                 rt2800_rfcsr_write(rt2x00dev, 8, 0x80);
3315
3316         if (rt2x00_rt(rt2x00dev, RT3593)) {
3317                 rt2800_register_read(rt2x00dev, GPIO_CTRL, &reg);
3318
3319                 /* Band selection */
3320                 if (rt2x00_is_usb(rt2x00dev) ||
3321                     rt2x00_is_pcie(rt2x00dev)) {
3322                         /* GPIO #8 controls all paths */
3323                         rt2x00_set_field32(&reg, GPIO_CTRL_DIR8, 0);
3324                         if (rf->channel <= 14)
3325                                 rt2x00_set_field32(&reg, GPIO_CTRL_VAL8, 1);
3326                         else
3327                                 rt2x00_set_field32(&reg, GPIO_CTRL_VAL8, 0);
3328                 }
3329
3330                 /* LNA PE control. */
3331                 if (rt2x00_is_usb(rt2x00dev)) {
3332                         /* GPIO #4 controls PE0 and PE1,
3333                          * GPIO #7 controls PE2
3334                          */
3335                         rt2x00_set_field32(&reg, GPIO_CTRL_DIR4, 0);
3336                         rt2x00_set_field32(&reg, GPIO_CTRL_DIR7, 0);
3337
3338                         rt2x00_set_field32(&reg, GPIO_CTRL_VAL4, 1);
3339                         rt2x00_set_field32(&reg, GPIO_CTRL_VAL7, 1);
3340                 } else if (rt2x00_is_pcie(rt2x00dev)) {
3341                         /* GPIO #4 controls PE0, PE1 and PE2 */
3342                         rt2x00_set_field32(&reg, GPIO_CTRL_DIR4, 0);
3343                         rt2x00_set_field32(&reg, GPIO_CTRL_VAL4, 1);
3344                 }
3345
3346                 rt2800_register_write(rt2x00dev, GPIO_CTRL, reg);
3347
3348                 /* AGC init */
3349                 if (rf->channel <= 14)
3350                         reg = 0x1c + 2 * rt2x00dev->lna_gain;
3351                 else
3352                         reg = 0x22 + ((rt2x00dev->lna_gain * 5) / 3);
3353
3354                 rt2800_bbp_write_with_rx_chain(rt2x00dev, 66, reg);
3355
3356                 usleep_range(1000, 1500);
3357         }
3358
3359         if (rt2x00_rt(rt2x00dev, RT5592)) {
3360                 rt2800_bbp_write(rt2x00dev, 195, 141);
3361                 rt2800_bbp_write(rt2x00dev, 196, conf_is_ht40(conf) ? 0x10 : 0x1a);
3362
3363                 /* AGC init */
3364                 reg = (rf->channel <= 14 ? 0x1c : 0x24) + 2 * rt2x00dev->lna_gain;
3365                 rt2800_bbp_write_with_rx_chain(rt2x00dev, 66, reg);
3366
3367                 rt2800_iq_calibrate(rt2x00dev, rf->channel);
3368         }
3369
3370         rt2800_bbp_read(rt2x00dev, 4, &bbp);
3371         rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * conf_is_ht40(conf));
3372         rt2800_bbp_write(rt2x00dev, 4, bbp);
3373
3374         rt2800_bbp_read(rt2x00dev, 3, &bbp);
3375         rt2x00_set_field8(&bbp, BBP3_HT40_MINUS, conf_is_ht40_minus(conf));
3376         rt2800_bbp_write(rt2x00dev, 3, bbp);
3377
3378         if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C)) {
3379                 if (conf_is_ht40(conf)) {
3380                         rt2800_bbp_write(rt2x00dev, 69, 0x1a);
3381                         rt2800_bbp_write(rt2x00dev, 70, 0x0a);
3382                         rt2800_bbp_write(rt2x00dev, 73, 0x16);
3383                 } else {
3384                         rt2800_bbp_write(rt2x00dev, 69, 0x16);
3385                         rt2800_bbp_write(rt2x00dev, 70, 0x08);
3386                         rt2800_bbp_write(rt2x00dev, 73, 0x11);
3387                 }
3388         }
3389
3390         msleep(1);
3391
3392         /*
3393          * Clear channel statistic counters
3394          */
3395         rt2800_register_read(rt2x00dev, CH_IDLE_STA, &reg);
3396         rt2800_register_read(rt2x00dev, CH_BUSY_STA, &reg);
3397         rt2800_register_read(rt2x00dev, CH_BUSY_STA_SEC, &reg);
3398
3399         /*
3400          * Clear update flag
3401          */
3402         if (rt2x00_rt(rt2x00dev, RT3352)) {
3403                 rt2800_bbp_read(rt2x00dev, 49, &bbp);
3404                 rt2x00_set_field8(&bbp, BBP49_UPDATE_FLAG, 0);
3405                 rt2800_bbp_write(rt2x00dev, 49, bbp);
3406         }
3407 }
3408
3409 static int rt2800_get_gain_calibration_delta(struct rt2x00_dev *rt2x00dev)
3410 {
3411         u8 tssi_bounds[9];
3412         u8 current_tssi;
3413         u16 eeprom;
3414         u8 step;
3415         int i;
3416
3417         /*
3418          * First check if temperature compensation is supported.
3419          */
3420         rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
3421         if (!rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_EXTERNAL_TX_ALC))
3422                 return 0;
3423
3424         /*
3425          * Read TSSI boundaries for temperature compensation from
3426          * the EEPROM.
3427          *
3428          * Array idx               0    1    2    3    4    5    6    7    8
3429          * Matching Delta value   -4   -3   -2   -1    0   +1   +2   +3   +4
3430          * Example TSSI bounds  0xF0 0xD0 0xB5 0xA0 0x88 0x45 0x25 0x15 0x00
3431          */
3432         if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ) {
3433                 rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG1, &eeprom);
3434                 tssi_bounds[0] = rt2x00_get_field16(eeprom,
3435                                         EEPROM_TSSI_BOUND_BG1_MINUS4);
3436                 tssi_bounds[1] = rt2x00_get_field16(eeprom,
3437                                         EEPROM_TSSI_BOUND_BG1_MINUS3);
3438
3439                 rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG2, &eeprom);
3440                 tssi_bounds[2] = rt2x00_get_field16(eeprom,
3441                                         EEPROM_TSSI_BOUND_BG2_MINUS2);
3442                 tssi_bounds[3] = rt2x00_get_field16(eeprom,
3443                                         EEPROM_TSSI_BOUND_BG2_MINUS1);
3444
3445                 rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG3, &eeprom);
3446                 tssi_bounds[4] = rt2x00_get_field16(eeprom,
3447                                         EEPROM_TSSI_BOUND_BG3_REF);
3448                 tssi_bounds[5] = rt2x00_get_field16(eeprom,
3449                                         EEPROM_TSSI_BOUND_BG3_PLUS1);
3450
3451                 rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG4, &eeprom);
3452                 tssi_bounds[6] = rt2x00_get_field16(eeprom,
3453                                         EEPROM_TSSI_BOUND_BG4_PLUS2);
3454                 tssi_bounds[7] = rt2x00_get_field16(eeprom,
3455                                         EEPROM_TSSI_BOUND_BG4_PLUS3);
3456
3457                 rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG5, &eeprom);
3458                 tssi_bounds[8] = rt2x00_get_field16(eeprom,
3459                                         EEPROM_TSSI_BOUND_BG5_PLUS4);
3460
3461                 step = rt2x00_get_field16(eeprom,
3462                                           EEPROM_TSSI_BOUND_BG5_AGC_STEP);
3463         } else {
3464                 rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A1, &eeprom);
3465                 tssi_bounds[0] = rt2x00_get_field16(eeprom,
3466                                         EEPROM_TSSI_BOUND_A1_MINUS4);
3467                 tssi_bounds[1] = rt2x00_get_field16(eeprom,
3468                                         EEPROM_TSSI_BOUND_A1_MINUS3);
3469
3470                 rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A2, &eeprom);
3471                 tssi_bounds[2] = rt2x00_get_field16(eeprom,
3472                                         EEPROM_TSSI_BOUND_A2_MINUS2);
3473                 tssi_bounds[3] = rt2x00_get_field16(eeprom,
3474                                         EEPROM_TSSI_BOUND_A2_MINUS1);
3475
3476                 rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A3, &eeprom);
3477                 tssi_bounds[4] = rt2x00_get_field16(eeprom,
3478                                         EEPROM_TSSI_BOUND_A3_REF);
3479                 tssi_bounds[5] = rt2x00_get_field16(eeprom,
3480                                         EEPROM_TSSI_BOUND_A3_PLUS1);
3481
3482                 rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A4, &eeprom);
3483                 tssi_bounds[6] = rt2x00_get_field16(eeprom,
3484                                         EEPROM_TSSI_BOUND_A4_PLUS2);
3485                 tssi_bounds[7] = rt2x00_get_field16(eeprom,
3486                                         EEPROM_TSSI_BOUND_A4_PLUS3);
3487
3488                 rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A5, &eeprom);
3489                 tssi_bounds[8] = rt2x00_get_field16(eeprom,
3490                                         EEPROM_TSSI_BOUND_A5_PLUS4);
3491
3492                 step = rt2x00_get_field16(eeprom,
3493                                           EEPROM_TSSI_BOUND_A5_AGC_STEP);
3494         }
3495
3496         /*
3497          * Check if temperature compensation is supported.
3498          */
3499         if (tssi_bounds[4] == 0xff || step == 0xff)
3500                 return 0;
3501
3502         /*
3503          * Read current TSSI (BBP 49).
3504          */
3505         rt2800_bbp_read(rt2x00dev, 49, &current_tssi);
3506
3507         /*
3508          * Compare TSSI value (BBP49) with the compensation boundaries
3509          * from the EEPROM and increase or decrease tx power.
3510          */
3511         for (i = 0; i <= 3; i++) {
3512                 if (current_tssi > tssi_bounds[i])
3513                         break;
3514         }
3515
3516         if (i == 4) {
3517                 for (i = 8; i >= 5; i--) {
3518                         if (current_tssi < tssi_bounds[i])
3519                                 break;
3520                 }
3521         }
3522
3523         return (i - 4) * step;
3524 }
3525
3526 static int rt2800_get_txpower_bw_comp(struct rt2x00_dev *rt2x00dev,
3527                                       enum ieee80211_band band)
3528 {
3529         u16 eeprom;
3530         u8 comp_en;
3531         u8 comp_type;
3532         int comp_value = 0;
3533
3534         rt2800_eeprom_read(rt2x00dev, EEPROM_TXPOWER_DELTA, &eeprom);
3535
3536         /*
3537          * HT40 compensation not required.
3538          */
3539         if (eeprom == 0xffff ||
3540             !test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags))
3541                 return 0;
3542
3543         if (band == IEEE80211_BAND_2GHZ) {
3544                 comp_en = rt2x00_get_field16(eeprom,
3545                                  EEPROM_TXPOWER_DELTA_ENABLE_2G);
3546                 if (comp_en) {
3547                         comp_type = rt2x00_get_field16(eeprom,
3548                                            EEPROM_TXPOWER_DELTA_TYPE_2G);
3549                         comp_value = rt2x00_get_field16(eeprom,
3550                                             EEPROM_TXPOWER_DELTA_VALUE_2G);
3551                         if (!comp_type)
3552                                 comp_value = -comp_value;
3553                 }
3554         } else {
3555                 comp_en = rt2x00_get_field16(eeprom,
3556                                  EEPROM_TXPOWER_DELTA_ENABLE_5G);
3557                 if (comp_en) {
3558                         comp_type = rt2x00_get_field16(eeprom,
3559                                            EEPROM_TXPOWER_DELTA_TYPE_5G);
3560                         comp_value = rt2x00_get_field16(eeprom,
3561                                             EEPROM_TXPOWER_DELTA_VALUE_5G);
3562                         if (!comp_type)
3563                                 comp_value = -comp_value;
3564                 }
3565         }
3566
3567         return comp_value;
3568 }
3569
3570 static int rt2800_get_txpower_reg_delta(struct rt2x00_dev *rt2x00dev,
3571                                         int power_level, int max_power)
3572 {
3573         int delta;
3574
3575         if (test_bit(CAPABILITY_POWER_LIMIT, &rt2x00dev->cap_flags))
3576                 return 0;
3577
3578         /*
3579          * XXX: We don't know the maximum transmit power of our hardware since
3580          * the EEPROM doesn't expose it. We only know that we are calibrated
3581          * to 100% tx power.
3582          *
3583          * Hence, we assume the regulatory limit that cfg80211 calulated for
3584          * the current channel is our maximum and if we are requested to lower
3585          * the value we just reduce our tx power accordingly.
3586          */
3587         delta = power_level - max_power;
3588         return min(delta, 0);
3589 }
3590
3591 static u8 rt2800_compensate_txpower(struct rt2x00_dev *rt2x00dev, int is_rate_b,
3592                                    enum ieee80211_band band, int power_level,
3593                                    u8 txpower, int delta)
3594 {
3595         u16 eeprom;
3596         u8 criterion;
3597         u8 eirp_txpower;
3598         u8 eirp_txpower_criterion;
3599         u8 reg_limit;
3600
3601         if (rt2x00_rt(rt2x00dev, RT3593))
3602                 return min_t(u8, txpower, 0xc);
3603
3604         if (test_bit(CAPABILITY_POWER_LIMIT, &rt2x00dev->cap_flags)) {
3605                 /*
3606                  * Check if eirp txpower exceed txpower_limit.
3607                  * We use OFDM 6M as criterion and its eirp txpower
3608                  * is stored at EEPROM_EIRP_MAX_TX_POWER.
3609                  * .11b data rate need add additional 4dbm
3610                  * when calculating eirp txpower.
3611                  */
3612                 rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
3613                                               1, &eeprom);
3614                 criterion = rt2x00_get_field16(eeprom,
3615                                                EEPROM_TXPOWER_BYRATE_RATE0);
3616
3617                 rt2800_eeprom_read(rt2x00dev, EEPROM_EIRP_MAX_TX_POWER,
3618                                    &eeprom);
3619
3620                 if (band == IEEE80211_BAND_2GHZ)
3621                         eirp_txpower_criterion = rt2x00_get_field16(eeprom,
3622                                                  EEPROM_EIRP_MAX_TX_POWER_2GHZ);
3623                 else
3624                         eirp_txpower_criterion = rt2x00_get_field16(eeprom,
3625                                                  EEPROM_EIRP_MAX_TX_POWER_5GHZ);
3626
3627                 eirp_txpower = eirp_txpower_criterion + (txpower - criterion) +
3628                                (is_rate_b ? 4 : 0) + delta;
3629
3630                 reg_limit = (eirp_txpower > power_level) ?
3631                                         (eirp_txpower - power_level) : 0;
3632         } else
3633                 reg_limit = 0;
3634
3635         txpower = max(0, txpower + delta - reg_limit);
3636         return min_t(u8, txpower, 0xc);
3637 }
3638
3639
3640 enum {
3641         TX_PWR_CFG_0_IDX,
3642         TX_PWR_CFG_1_IDX,
3643         TX_PWR_CFG_2_IDX,
3644         TX_PWR_CFG_3_IDX,
3645         TX_PWR_CFG_4_IDX,
3646         TX_PWR_CFG_5_IDX,
3647         TX_PWR_CFG_6_IDX,
3648         TX_PWR_CFG_7_IDX,
3649         TX_PWR_CFG_8_IDX,
3650         TX_PWR_CFG_9_IDX,
3651         TX_PWR_CFG_0_EXT_IDX,
3652         TX_PWR_CFG_1_EXT_IDX,
3653         TX_PWR_CFG_2_EXT_IDX,
3654         TX_PWR_CFG_3_EXT_IDX,
3655         TX_PWR_CFG_4_EXT_IDX,
3656         TX_PWR_CFG_IDX_COUNT,
3657 };
3658
3659 static void rt2800_config_txpower_rt3593(struct rt2x00_dev *rt2x00dev,
3660                                          struct ieee80211_channel *chan,
3661                                          int power_level)
3662 {
3663         u8 txpower;
3664         u16 eeprom;
3665         u32 regs[TX_PWR_CFG_IDX_COUNT];
3666         unsigned int offset;
3667         enum ieee80211_band band = chan->band;
3668         int delta;
3669         int i;
3670
3671         memset(regs, '\0', sizeof(regs));
3672
3673         /* TODO: adapt TX power reduction from the rt28xx code */
3674
3675         /* calculate temperature compensation delta */
3676         delta = rt2800_get_gain_calibration_delta(rt2x00dev);
3677
3678         if (band == IEEE80211_BAND_5GHZ)
3679                 offset = 16;
3680         else
3681                 offset = 0;
3682
3683         if (test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags))
3684                 offset += 8;
3685
3686         /* read the next four txpower values */
3687         rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
3688                                       offset, &eeprom);
3689
3690         /* CCK 1MBS,2MBS */
3691         txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0);
3692         txpower = rt2800_compensate_txpower(rt2x00dev, 1, band, power_level,
3693                                             txpower, delta);
3694         rt2x00_set_field32(&regs[TX_PWR_CFG_0_IDX],
3695                            TX_PWR_CFG_0_CCK1_CH0, txpower);
3696         rt2x00_set_field32(&regs[TX_PWR_CFG_0_IDX],
3697                            TX_PWR_CFG_0_CCK1_CH1, txpower);
3698         rt2x00_set_field32(&regs[TX_PWR_CFG_0_EXT_IDX],
3699                            TX_PWR_CFG_0_EXT_CCK1_CH2, txpower);
3700
3701         /* CCK 5.5MBS,11MBS */
3702         txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1);
3703         txpower = rt2800_compensate_txpower(rt2x00dev, 1, band, power_level,
3704                                             txpower, delta);
3705         rt2x00_set_field32(&regs[TX_PWR_CFG_0_IDX],
3706                            TX_PWR_CFG_0_CCK5_CH0, txpower);
3707         rt2x00_set_field32(&regs[TX_PWR_CFG_0_IDX],
3708                            TX_PWR_CFG_0_CCK5_CH1, txpower);
3709         rt2x00_set_field32(&regs[TX_PWR_CFG_0_EXT_IDX],
3710                            TX_PWR_CFG_0_EXT_CCK5_CH2, txpower);
3711
3712         /* OFDM 6MBS,9MBS */
3713         txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2);
3714         txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3715                                             txpower, delta);
3716         rt2x00_set_field32(&regs[TX_PWR_CFG_0_IDX],
3717                            TX_PWR_CFG_0_OFDM6_CH0, txpower);
3718         rt2x00_set_field32(&regs[TX_PWR_CFG_0_IDX],
3719                            TX_PWR_CFG_0_OFDM6_CH1, txpower);
3720         rt2x00_set_field32(&regs[TX_PWR_CFG_0_EXT_IDX],
3721                            TX_PWR_CFG_0_EXT_OFDM6_CH2, txpower);
3722
3723         /* OFDM 12MBS,18MBS */
3724         txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE3);
3725         txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3726                                             txpower, delta);
3727         rt2x00_set_field32(&regs[TX_PWR_CFG_0_IDX],
3728                            TX_PWR_CFG_0_OFDM12_CH0, txpower);
3729         rt2x00_set_field32(&regs[TX_PWR_CFG_0_IDX],
3730                            TX_PWR_CFG_0_OFDM12_CH1, txpower);
3731         rt2x00_set_field32(&regs[TX_PWR_CFG_0_EXT_IDX],
3732                            TX_PWR_CFG_0_EXT_OFDM12_CH2, txpower);
3733
3734         /* read the next four txpower values */
3735         rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
3736                                       offset + 1, &eeprom);
3737
3738         /* OFDM 24MBS,36MBS */
3739         txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0);
3740         txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3741                                             txpower, delta);
3742         rt2x00_set_field32(&regs[TX_PWR_CFG_1_IDX],
3743                            TX_PWR_CFG_1_OFDM24_CH0, txpower);
3744         rt2x00_set_field32(&regs[TX_PWR_CFG_1_IDX],
3745                            TX_PWR_CFG_1_OFDM24_CH1, txpower);
3746         rt2x00_set_field32(&regs[TX_PWR_CFG_1_EXT_IDX],
3747                            TX_PWR_CFG_1_EXT_OFDM24_CH2, txpower);
3748
3749         /* OFDM 48MBS */
3750         txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1);
3751         txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3752                                             txpower, delta);
3753         rt2x00_set_field32(&regs[TX_PWR_CFG_1_IDX],
3754                            TX_PWR_CFG_1_OFDM48_CH0, txpower);
3755         rt2x00_set_field32(&regs[TX_PWR_CFG_1_IDX],
3756                            TX_PWR_CFG_1_OFDM48_CH1, txpower);
3757         rt2x00_set_field32(&regs[TX_PWR_CFG_1_EXT_IDX],
3758                            TX_PWR_CFG_1_EXT_OFDM48_CH2, txpower);
3759
3760         /* OFDM 54MBS */
3761         txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2);
3762         txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3763                                             txpower, delta);
3764         rt2x00_set_field32(&regs[TX_PWR_CFG_7_IDX],
3765                            TX_PWR_CFG_7_OFDM54_CH0, txpower);
3766         rt2x00_set_field32(&regs[TX_PWR_CFG_7_IDX],
3767                            TX_PWR_CFG_7_OFDM54_CH1, txpower);
3768         rt2x00_set_field32(&regs[TX_PWR_CFG_7_IDX],
3769                            TX_PWR_CFG_7_OFDM54_CH2, txpower);
3770
3771         /* read the next four txpower values */
3772         rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
3773                                       offset + 2, &eeprom);
3774
3775         /* MCS 0,1 */
3776         txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0);
3777         txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3778                                             txpower, delta);
3779         rt2x00_set_field32(&regs[TX_PWR_CFG_1_IDX],
3780                            TX_PWR_CFG_1_MCS0_CH0, txpower);
3781         rt2x00_set_field32(&regs[TX_PWR_CFG_1_IDX],
3782                            TX_PWR_CFG_1_MCS0_CH1, txpower);
3783         rt2x00_set_field32(&regs[TX_PWR_CFG_1_EXT_IDX],
3784                            TX_PWR_CFG_1_EXT_MCS0_CH2, txpower);
3785
3786         /* MCS 2,3 */
3787         txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1);
3788         txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3789                                             txpower, delta);
3790         rt2x00_set_field32(&regs[TX_PWR_CFG_1_IDX],
3791                            TX_PWR_CFG_1_MCS2_CH0, txpower);
3792         rt2x00_set_field32(&regs[TX_PWR_CFG_1_IDX],
3793                            TX_PWR_CFG_1_MCS2_CH1, txpower);
3794         rt2x00_set_field32(&regs[TX_PWR_CFG_1_EXT_IDX],
3795                            TX_PWR_CFG_1_EXT_MCS2_CH2, txpower);
3796
3797         /* MCS 4,5 */
3798         txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2);
3799         txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3800                                             txpower, delta);
3801         rt2x00_set_field32(&regs[TX_PWR_CFG_2_IDX],
3802                            TX_PWR_CFG_2_MCS4_CH0, txpower);
3803         rt2x00_set_field32(&regs[TX_PWR_CFG_2_IDX],
3804                            TX_PWR_CFG_2_MCS4_CH1, txpower);
3805         rt2x00_set_field32(&regs[TX_PWR_CFG_2_EXT_IDX],
3806                            TX_PWR_CFG_2_EXT_MCS4_CH2, txpower);
3807
3808         /* MCS 6 */
3809         txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE3);
3810         txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3811                                             txpower, delta);
3812         rt2x00_set_field32(&regs[TX_PWR_CFG_2_IDX],
3813                            TX_PWR_CFG_2_MCS6_CH0, txpower);
3814         rt2x00_set_field32(&regs[TX_PWR_CFG_2_IDX],
3815                            TX_PWR_CFG_2_MCS6_CH1, txpower);
3816         rt2x00_set_field32(&regs[TX_PWR_CFG_2_EXT_IDX],
3817                            TX_PWR_CFG_2_EXT_MCS6_CH2, txpower);
3818
3819         /* read the next four txpower values */
3820         rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
3821                                       offset + 3, &eeprom);
3822
3823         /* MCS 7 */
3824         txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0);
3825         txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3826                                             txpower, delta);
3827         rt2x00_set_field32(&regs[TX_PWR_CFG_7_IDX],
3828                            TX_PWR_CFG_7_MCS7_CH0, txpower);
3829         rt2x00_set_field32(&regs[TX_PWR_CFG_7_IDX],
3830                            TX_PWR_CFG_7_MCS7_CH1, txpower);
3831         rt2x00_set_field32(&regs[TX_PWR_CFG_7_IDX],
3832                            TX_PWR_CFG_7_MCS7_CH2, txpower);
3833
3834         /* MCS 8,9 */
3835         txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1);
3836         txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3837                                             txpower, delta);
3838         rt2x00_set_field32(&regs[TX_PWR_CFG_2_IDX],
3839                            TX_PWR_CFG_2_MCS8_CH0, txpower);
3840         rt2x00_set_field32(&regs[TX_PWR_CFG_2_IDX],
3841                            TX_PWR_CFG_2_MCS8_CH1, txpower);
3842         rt2x00_set_field32(&regs[TX_PWR_CFG_2_EXT_IDX],
3843                            TX_PWR_CFG_2_EXT_MCS8_CH2, txpower);
3844
3845         /* MCS 10,11 */
3846         txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2);
3847         txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3848                                             txpower, delta);
3849         rt2x00_set_field32(&regs[TX_PWR_CFG_2_IDX],
3850                            TX_PWR_CFG_2_MCS10_CH0, txpower);
3851         rt2x00_set_field32(&regs[TX_PWR_CFG_2_IDX],
3852                            TX_PWR_CFG_2_MCS10_CH1, txpower);
3853         rt2x00_set_field32(&regs[TX_PWR_CFG_2_EXT_IDX],
3854                            TX_PWR_CFG_2_EXT_MCS10_CH2, txpower);
3855
3856         /* MCS 12,13 */
3857         txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE3);
3858         txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3859                                             txpower, delta);
3860         rt2x00_set_field32(&regs[TX_PWR_CFG_3_IDX],
3861                            TX_PWR_CFG_3_MCS12_CH0, txpower);
3862         rt2x00_set_field32(&regs[TX_PWR_CFG_3_IDX],
3863                            TX_PWR_CFG_3_MCS12_CH1, txpower);
3864         rt2x00_set_field32(&regs[TX_PWR_CFG_3_EXT_IDX],
3865                            TX_PWR_CFG_3_EXT_MCS12_CH2, txpower);
3866
3867         /* read the next four txpower values */
3868         rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
3869                                       offset + 4, &eeprom);
3870
3871         /* MCS 14 */
3872         txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0);
3873         txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3874                                             txpower, delta);
3875         rt2x00_set_field32(&regs[TX_PWR_CFG_3_IDX],
3876                            TX_PWR_CFG_3_MCS14_CH0, txpower);
3877         rt2x00_set_field32(&regs[TX_PWR_CFG_3_IDX],
3878                            TX_PWR_CFG_3_MCS14_CH1, txpower);
3879         rt2x00_set_field32(&regs[TX_PWR_CFG_3_EXT_IDX],
3880                            TX_PWR_CFG_3_EXT_MCS14_CH2, txpower);
3881
3882         /* MCS 15 */
3883         txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1);
3884         txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3885                                             txpower, delta);
3886         rt2x00_set_field32(&regs[TX_PWR_CFG_8_IDX],
3887                            TX_PWR_CFG_8_MCS15_CH0, txpower);
3888         rt2x00_set_field32(&regs[TX_PWR_CFG_8_IDX],
3889                            TX_PWR_CFG_8_MCS15_CH1, txpower);
3890         rt2x00_set_field32(&regs[TX_PWR_CFG_8_IDX],
3891                            TX_PWR_CFG_8_MCS15_CH2, txpower);
3892
3893         /* MCS 16,17 */
3894         txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2);
3895         txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3896                                             txpower, delta);
3897         rt2x00_set_field32(&regs[TX_PWR_CFG_5_IDX],
3898                            TX_PWR_CFG_5_MCS16_CH0, txpower);
3899         rt2x00_set_field32(&regs[TX_PWR_CFG_5_IDX],
3900                            TX_PWR_CFG_5_MCS16_CH1, txpower);
3901         rt2x00_set_field32(&regs[TX_PWR_CFG_5_IDX],
3902                            TX_PWR_CFG_5_MCS16_CH2, txpower);
3903
3904         /* MCS 18,19 */
3905         txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE3);
3906         txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3907                                             txpower, delta);
3908         rt2x00_set_field32(&regs[TX_PWR_CFG_5_IDX],
3909                            TX_PWR_CFG_5_MCS18_CH0, txpower);
3910         rt2x00_set_field32(&regs[TX_PWR_CFG_5_IDX],
3911                            TX_PWR_CFG_5_MCS18_CH1, txpower);
3912         rt2x00_set_field32(&regs[TX_PWR_CFG_5_IDX],
3913                            TX_PWR_CFG_5_MCS18_CH2, txpower);
3914
3915         /* read the next four txpower values */
3916         rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
3917                                       offset + 5, &eeprom);
3918
3919         /* MCS 20,21 */
3920         txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0);
3921         txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3922                                             txpower, delta);
3923         rt2x00_set_field32(&regs[TX_PWR_CFG_6_IDX],
3924                            TX_PWR_CFG_6_MCS20_CH0, txpower);
3925         rt2x00_set_field32(&regs[TX_PWR_CFG_6_IDX],
3926                            TX_PWR_CFG_6_MCS20_CH1, txpower);
3927         rt2x00_set_field32(&regs[TX_PWR_CFG_6_IDX],
3928                            TX_PWR_CFG_6_MCS20_CH2, txpower);
3929
3930         /* MCS 22 */
3931         txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1);
3932         txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3933                                             txpower, delta);
3934         rt2x00_set_field32(&regs[TX_PWR_CFG_6_IDX],
3935                            TX_PWR_CFG_6_MCS22_CH0, txpower);
3936         rt2x00_set_field32(&regs[TX_PWR_CFG_6_IDX],
3937                            TX_PWR_CFG_6_MCS22_CH1, txpower);
3938         rt2x00_set_field32(&regs[TX_PWR_CFG_6_IDX],
3939                            TX_PWR_CFG_6_MCS22_CH2, txpower);
3940
3941         /* MCS 23 */
3942         txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2);
3943         txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3944                                             txpower, delta);
3945         rt2x00_set_field32(&regs[TX_PWR_CFG_8_IDX],
3946                            TX_PWR_CFG_8_MCS23_CH0, txpower);
3947         rt2x00_set_field32(&regs[TX_PWR_CFG_8_IDX],
3948                            TX_PWR_CFG_8_MCS23_CH1, txpower);
3949         rt2x00_set_field32(&regs[TX_PWR_CFG_8_IDX],
3950                            TX_PWR_CFG_8_MCS23_CH2, txpower);
3951
3952         /* read the next four txpower values */
3953         rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
3954                                       offset + 6, &eeprom);
3955
3956         /* STBC, MCS 0,1 */
3957         txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0);
3958         txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3959                                             txpower, delta);
3960         rt2x00_set_field32(&regs[TX_PWR_CFG_3_IDX],
3961                            TX_PWR_CFG_3_STBC0_CH0, txpower);
3962         rt2x00_set_field32(&regs[TX_PWR_CFG_3_IDX],
3963                            TX_PWR_CFG_3_STBC0_CH1, txpower);
3964         rt2x00_set_field32(&regs[TX_PWR_CFG_3_EXT_IDX],
3965                            TX_PWR_CFG_3_EXT_STBC0_CH2, txpower);
3966
3967         /* STBC, MCS 2,3 */
3968         txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1);
3969         txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3970                                             txpower, delta);
3971         rt2x00_set_field32(&regs[TX_PWR_CFG_3_IDX],
3972                            TX_PWR_CFG_3_STBC2_CH0, txpower);
3973         rt2x00_set_field32(&regs[TX_PWR_CFG_3_IDX],
3974                            TX_PWR_CFG_3_STBC2_CH1, txpower);
3975         rt2x00_set_field32(&regs[TX_PWR_CFG_3_EXT_IDX],
3976                            TX_PWR_CFG_3_EXT_STBC2_CH2, txpower);
3977
3978         /* STBC, MCS 4,5 */
3979         txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2);
3980         txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3981                                             txpower, delta);
3982         rt2x00_set_field32(&regs[TX_PWR_CFG_4_IDX], TX_PWR_CFG_RATE0, txpower);
3983         rt2x00_set_field32(&regs[TX_PWR_CFG_4_IDX], TX_PWR_CFG_RATE1, txpower);
3984         rt2x00_set_field32(&regs[TX_PWR_CFG_4_EXT_IDX], TX_PWR_CFG_RATE0,
3985                            txpower);
3986
3987         /* STBC, MCS 6 */
3988         txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE3);
3989         txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3990                                             txpower, delta);
3991         rt2x00_set_field32(&regs[TX_PWR_CFG_4_IDX], TX_PWR_CFG_RATE2, txpower);
3992         rt2x00_set_field32(&regs[TX_PWR_CFG_4_IDX], TX_PWR_CFG_RATE3, txpower);
3993         rt2x00_set_field32(&regs[TX_PWR_CFG_4_EXT_IDX], TX_PWR_CFG_RATE2,
3994                            txpower);
3995
3996         /* read the next four txpower values */
3997         rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
3998                                       offset + 7, &eeprom);
3999
4000         /* STBC, MCS 7 */
4001         txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0);
4002         txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4003                                             txpower, delta);
4004         rt2x00_set_field32(&regs[TX_PWR_CFG_9_IDX],
4005                            TX_PWR_CFG_9_STBC7_CH0, txpower);
4006         rt2x00_set_field32(&regs[TX_PWR_CFG_9_IDX],
4007                            TX_PWR_CFG_9_STBC7_CH1, txpower);
4008         rt2x00_set_field32(&regs[TX_PWR_CFG_9_IDX],
4009                            TX_PWR_CFG_9_STBC7_CH2, txpower);
4010
4011         rt2800_register_write(rt2x00dev, TX_PWR_CFG_0, regs[TX_PWR_CFG_0_IDX]);
4012         rt2800_register_write(rt2x00dev, TX_PWR_CFG_1, regs[TX_PWR_CFG_1_IDX]);
4013         rt2800_register_write(rt2x00dev, TX_PWR_CFG_2, regs[TX_PWR_CFG_2_IDX]);
4014         rt2800_register_write(rt2x00dev, TX_PWR_CFG_3, regs[TX_PWR_CFG_3_IDX]);
4015         rt2800_register_write(rt2x00dev, TX_PWR_CFG_4, regs[TX_PWR_CFG_4_IDX]);
4016         rt2800_register_write(rt2x00dev, TX_PWR_CFG_5, regs[TX_PWR_CFG_5_IDX]);
4017         rt2800_register_write(rt2x00dev, TX_PWR_CFG_6, regs[TX_PWR_CFG_6_IDX]);
4018         rt2800_register_write(rt2x00dev, TX_PWR_CFG_7, regs[TX_PWR_CFG_7_IDX]);
4019         rt2800_register_write(rt2x00dev, TX_PWR_CFG_8, regs[TX_PWR_CFG_8_IDX]);
4020         rt2800_register_write(rt2x00dev, TX_PWR_CFG_9, regs[TX_PWR_CFG_9_IDX]);
4021
4022         rt2800_register_write(rt2x00dev, TX_PWR_CFG_0_EXT,
4023                               regs[TX_PWR_CFG_0_EXT_IDX]);
4024         rt2800_register_write(rt2x00dev, TX_PWR_CFG_1_EXT,
4025                               regs[TX_PWR_CFG_1_EXT_IDX]);
4026         rt2800_register_write(rt2x00dev, TX_PWR_CFG_2_EXT,
4027                               regs[TX_PWR_CFG_2_EXT_IDX]);
4028         rt2800_register_write(rt2x00dev, TX_PWR_CFG_3_EXT,
4029                               regs[TX_PWR_CFG_3_EXT_IDX]);
4030         rt2800_register_write(rt2x00dev, TX_PWR_CFG_4_EXT,
4031                               regs[TX_PWR_CFG_4_EXT_IDX]);
4032
4033         for (i = 0; i < TX_PWR_CFG_IDX_COUNT; i++)
4034                 rt2x00_dbg(rt2x00dev,
4035                            "band:%cGHz, BW:%c0MHz, TX_PWR_CFG_%d%s = %08lx\n",
4036                            (band == IEEE80211_BAND_5GHZ) ? '5' : '2',
4037                            (test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags)) ?
4038                                                                 '4' : '2',
4039                            (i > TX_PWR_CFG_9_IDX) ?
4040                                         (i - TX_PWR_CFG_9_IDX - 1) : i,
4041                            (i > TX_PWR_CFG_9_IDX) ? "_EXT" : "",
4042                            (unsigned long) regs[i]);
4043 }
4044
4045 /*
4046  * We configure transmit power using MAC TX_PWR_CFG_{0,...,N} registers and
4047  * BBP R1 register. TX_PWR_CFG_X allow to configure per rate TX power values,
4048  * 4 bits for each rate (tune from 0 to 15 dBm). BBP_R1 controls transmit power
4049  * for all rates, but allow to set only 4 discrete values: -12, -6, 0 and 6 dBm.
4050  * Reference per rate transmit power values are located in the EEPROM at
4051  * EEPROM_TXPOWER_BYRATE offset. We adjust them and BBP R1 settings according to
4052  * current conditions (i.e. band, bandwidth, temperature, user settings).
4053  */
4054 static void rt2800_config_txpower_rt28xx(struct rt2x00_dev *rt2x00dev,
4055                                          struct ieee80211_channel *chan,
4056                                          int power_level)
4057 {
4058         u8 txpower, r1;
4059         u16 eeprom;
4060         u32 reg, offset;
4061         int i, is_rate_b, delta, power_ctrl;
4062         enum ieee80211_band band = chan->band;
4063
4064         /*
4065          * Calculate HT40 compensation. For 40MHz we need to add or subtract
4066          * value read from EEPROM (different for 2GHz and for 5GHz).
4067          */
4068         delta = rt2800_get_txpower_bw_comp(rt2x00dev, band);
4069
4070         /*
4071          * Calculate temperature compensation. Depends on measurement of current
4072          * TSSI (Transmitter Signal Strength Indication) we know TX power (due
4073          * to temperature or maybe other factors) is smaller or bigger than
4074          * expected. We adjust it, based on TSSI reference and boundaries values
4075          * provided in EEPROM.
4076          */
4077         delta += rt2800_get_gain_calibration_delta(rt2x00dev);
4078
4079         /*
4080          * Decrease power according to user settings, on devices with unknown
4081          * maximum tx power. For other devices we take user power_level into
4082          * consideration on rt2800_compensate_txpower().
4083          */
4084         delta += rt2800_get_txpower_reg_delta(rt2x00dev, power_level,
4085                                               chan->max_power);
4086
4087         /*
4088          * BBP_R1 controls TX power for all rates, it allow to set the following
4089          * gains -12, -6, 0, +6 dBm by setting values 2, 1, 0, 3 respectively.
4090          *
4091          * TODO: we do not use +6 dBm option to do not increase power beyond
4092          * regulatory limit, however this could be utilized for devices with
4093          * CAPABILITY_POWER_LIMIT.
4094          *
4095          * TODO: add different temperature compensation code for RT3290 & RT5390
4096          * to allow to use BBP_R1 for those chips.
4097          */
4098         if (!rt2x00_rt(rt2x00dev, RT3290) &&
4099             !rt2x00_rt(rt2x00dev, RT5390)) {
4100                 rt2800_bbp_read(rt2x00dev, 1, &r1);
4101                 if (delta <= -12) {
4102                         power_ctrl = 2;
4103                         delta += 12;
4104                 } else if (delta <= -6) {
4105                         power_ctrl = 1;
4106                         delta += 6;
4107                 } else {
4108                         power_ctrl = 0;
4109                 }
4110                 rt2x00_set_field8(&r1, BBP1_TX_POWER_CTRL, power_ctrl);
4111                 rt2800_bbp_write(rt2x00dev, 1, r1);
4112         }
4113
4114         offset = TX_PWR_CFG_0;
4115
4116         for (i = 0; i < EEPROM_TXPOWER_BYRATE_SIZE; i += 2) {
4117                 /* just to be safe */
4118                 if (offset > TX_PWR_CFG_4)
4119                         break;
4120
4121                 rt2800_register_read(rt2x00dev, offset, &reg);
4122
4123                 /* read the next four txpower values */
4124                 rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
4125                                               i, &eeprom);
4126
4127                 is_rate_b = i ? 0 : 1;
4128                 /*
4129                  * TX_PWR_CFG_0: 1MBS, TX_PWR_CFG_1: 24MBS,
4130                  * TX_PWR_CFG_2: MCS4, TX_PWR_CFG_3: MCS12,
4131                  * TX_PWR_CFG_4: unknown
4132                  */
4133                 txpower = rt2x00_get_field16(eeprom,
4134                                              EEPROM_TXPOWER_BYRATE_RATE0);
4135                 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
4136                                              power_level, txpower, delta);
4137                 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE0, txpower);
4138
4139                 /*
4140                  * TX_PWR_CFG_0: 2MBS, TX_PWR_CFG_1: 36MBS,
4141                  * TX_PWR_CFG_2: MCS5, TX_PWR_CFG_3: MCS13,
4142                  * TX_PWR_CFG_4: unknown
4143                  */
4144                 txpower = rt2x00_get_field16(eeprom,
4145                                              EEPROM_TXPOWER_BYRATE_RATE1);
4146                 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
4147                                              power_level, txpower, delta);
4148                 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE1, txpower);
4149
4150                 /*
4151                  * TX_PWR_CFG_0: 5.5MBS, TX_PWR_CFG_1: 48MBS,
4152                  * TX_PWR_CFG_2: MCS6,  TX_PWR_CFG_3: MCS14,
4153                  * TX_PWR_CFG_4: unknown
4154                  */
4155                 txpower = rt2x00_get_field16(eeprom,
4156                                              EEPROM_TXPOWER_BYRATE_RATE2);
4157                 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
4158                                              power_level, txpower, delta);
4159                 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE2, txpower);
4160
4161                 /*
4162                  * TX_PWR_CFG_0: 11MBS, TX_PWR_CFG_1: 54MBS,
4163                  * TX_PWR_CFG_2: MCS7,  TX_PWR_CFG_3: MCS15,
4164                  * TX_PWR_CFG_4: unknown
4165                  */
4166                 txpower = rt2x00_get_field16(eeprom,
4167                                              EEPROM_TXPOWER_BYRATE_RATE3);
4168                 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
4169                                              power_level, txpower, delta);
4170                 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE3, txpower);
4171
4172                 /* read the next four txpower values */
4173                 rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
4174                                               i + 1, &eeprom);
4175
4176                 is_rate_b = 0;
4177                 /*
4178                  * TX_PWR_CFG_0: 6MBS, TX_PWR_CFG_1: MCS0,
4179                  * TX_PWR_CFG_2: MCS8, TX_PWR_CFG_3: unknown,
4180                  * TX_PWR_CFG_4: unknown
4181                  */
4182                 txpower = rt2x00_get_field16(eeprom,
4183                                              EEPROM_TXPOWER_BYRATE_RATE0);
4184                 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
4185                                              power_level, txpower, delta);
4186                 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE4, txpower);
4187
4188                 /*
4189                  * TX_PWR_CFG_0: 9MBS, TX_PWR_CFG_1: MCS1,
4190                  * TX_PWR_CFG_2: MCS9, TX_PWR_CFG_3: unknown,
4191                  * TX_PWR_CFG_4: unknown
4192                  */
4193                 txpower = rt2x00_get_field16(eeprom,
4194                                              EEPROM_TXPOWER_BYRATE_RATE1);
4195                 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
4196                                              power_level, txpower, delta);
4197                 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE5, txpower);
4198
4199                 /*
4200                  * TX_PWR_CFG_0: 12MBS, TX_PWR_CFG_1: MCS2,
4201                  * TX_PWR_CFG_2: MCS10, TX_PWR_CFG_3: unknown,
4202                  * TX_PWR_CFG_4: unknown
4203                  */
4204                 txpower = rt2x00_get_field16(eeprom,
4205                                              EEPROM_TXPOWER_BYRATE_RATE2);
4206                 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
4207                                              power_level, txpower, delta);
4208                 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE6, txpower);
4209
4210                 /*
4211                  * TX_PWR_CFG_0: 18MBS, TX_PWR_CFG_1: MCS3,
4212                  * TX_PWR_CFG_2: MCS11, TX_PWR_CFG_3: unknown,
4213                  * TX_PWR_CFG_4: unknown
4214                  */
4215                 txpower = rt2x00_get_field16(eeprom,
4216                                              EEPROM_TXPOWER_BYRATE_RATE3);
4217                 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
4218                                              power_level, txpower, delta);
4219                 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE7, txpower);
4220
4221                 rt2800_register_write(rt2x00dev, offset, reg);
4222
4223                 /* next TX_PWR_CFG register */
4224                 offset += 4;
4225         }
4226 }
4227
4228 static void rt2800_config_txpower(struct rt2x00_dev *rt2x00dev,
4229                                   struct ieee80211_channel *chan,
4230                                   int power_level)
4231 {
4232         if (rt2x00_rt(rt2x00dev, RT3593))
4233                 rt2800_config_txpower_rt3593(rt2x00dev, chan, power_level);
4234         else
4235                 rt2800_config_txpower_rt28xx(rt2x00dev, chan, power_level);
4236 }
4237
4238 void rt2800_gain_calibration(struct rt2x00_dev *rt2x00dev)
4239 {
4240         rt2800_config_txpower(rt2x00dev, rt2x00dev->hw->conf.chandef.chan,
4241                               rt2x00dev->tx_power);
4242 }
4243 EXPORT_SYMBOL_GPL(rt2800_gain_calibration);
4244
4245 void rt2800_vco_calibration(struct rt2x00_dev *rt2x00dev)
4246 {
4247         u32     tx_pin;
4248         u8      rfcsr;
4249
4250         /*
4251          * A voltage-controlled oscillator(VCO) is an electronic oscillator
4252          * designed to be controlled in oscillation frequency by a voltage
4253          * input. Maybe the temperature will affect the frequency of
4254          * oscillation to be shifted. The VCO calibration will be called
4255          * periodically to adjust the frequency to be precision.
4256         */
4257
4258         rt2800_register_read(rt2x00dev, TX_PIN_CFG, &tx_pin);
4259         tx_pin &= TX_PIN_CFG_PA_PE_DISABLE;
4260         rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin);
4261
4262         switch (rt2x00dev->chip.rf) {
4263         case RF2020:
4264         case RF3020:
4265         case RF3021:
4266         case RF3022:
4267         case RF3320:
4268         case RF3052:
4269                 rt2800_rfcsr_read(rt2x00dev, 7, &rfcsr);
4270                 rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1);
4271                 rt2800_rfcsr_write(rt2x00dev, 7, rfcsr);
4272                 break;
4273         case RF3053:
4274         case RF3070:
4275         case RF3290:
4276         case RF5360:
4277         case RF5370:
4278         case RF5372:
4279         case RF5390:
4280         case RF5392:
4281                 rt2800_rfcsr_read(rt2x00dev, 3, &rfcsr);
4282                 rt2x00_set_field8(&rfcsr, RFCSR3_VCOCAL_EN, 1);
4283                 rt2800_rfcsr_write(rt2x00dev, 3, rfcsr);
4284                 break;
4285         default:
4286                 return;
4287         }
4288
4289         mdelay(1);
4290
4291         rt2800_register_read(rt2x00dev, TX_PIN_CFG, &tx_pin);
4292         if (rt2x00dev->rf_channel <= 14) {
4293                 switch (rt2x00dev->default_ant.tx_chain_num) {
4294                 case 3:
4295                         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G2_EN, 1);
4296                         /* fall through */
4297                 case 2:
4298                         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G1_EN, 1);
4299                         /* fall through */
4300                 case 1:
4301                 default:
4302                         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN, 1);
4303                         break;
4304                 }
4305         } else {
4306                 switch (rt2x00dev->default_ant.tx_chain_num) {
4307                 case 3:
4308                         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A2_EN, 1);
4309                         /* fall through */
4310                 case 2:
4311                         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A1_EN, 1);
4312                         /* fall through */
4313                 case 1:
4314                 default:
4315                         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A0_EN, 1);
4316                         break;
4317                 }
4318         }
4319         rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin);
4320
4321 }
4322 EXPORT_SYMBOL_GPL(rt2800_vco_calibration);
4323
4324 static void rt2800_config_retry_limit(struct rt2x00_dev *rt2x00dev,
4325                                       struct rt2x00lib_conf *libconf)
4326 {
4327         u32 reg;
4328
4329         rt2800_register_read(rt2x00dev, TX_RTY_CFG, &reg);
4330         rt2x00_set_field32(&reg, TX_RTY_CFG_SHORT_RTY_LIMIT,
4331                            libconf->conf->short_frame_max_tx_count);
4332         rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_LIMIT,
4333                            libconf->conf->long_frame_max_tx_count);
4334         rt2800_register_write(rt2x00dev, TX_RTY_CFG, reg);
4335 }
4336
4337 static void rt2800_config_ps(struct rt2x00_dev *rt2x00dev,
4338                              struct rt2x00lib_conf *libconf)
4339 {
4340         enum dev_state state =
4341             (libconf->conf->flags & IEEE80211_CONF_PS) ?
4342                 STATE_SLEEP : STATE_AWAKE;
4343         u32 reg;
4344
4345         if (state == STATE_SLEEP) {
4346                 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0);
4347
4348                 rt2800_register_read(rt2x00dev, AUTOWAKEUP_CFG, &reg);
4349                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 5);
4350                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE,
4351                                    libconf->conf->listen_interval - 1);
4352                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTOWAKE, 1);
4353                 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg);
4354
4355                 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
4356         } else {
4357                 rt2800_register_read(rt2x00dev, AUTOWAKEUP_CFG, &reg);
4358                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 0);
4359                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE, 0);
4360                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTOWAKE, 0);
4361                 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg);
4362
4363                 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
4364         }
4365 }
4366
4367 void rt2800_config(struct rt2x00_dev *rt2x00dev,
4368                    struct rt2x00lib_conf *libconf,
4369                    const unsigned int flags)
4370 {
4371         /* Always recalculate LNA gain before changing configuration */
4372         rt2800_config_lna_gain(rt2x00dev, libconf);
4373
4374         if (flags & IEEE80211_CONF_CHANGE_CHANNEL) {
4375                 rt2800_config_channel(rt2x00dev, libconf->conf,
4376                                       &libconf->rf, &libconf->channel);
4377                 rt2800_config_txpower(rt2x00dev, libconf->conf->chandef.chan,
4378                                       libconf->conf->power_level);
4379         }
4380         if (flags & IEEE80211_CONF_CHANGE_POWER)
4381                 rt2800_config_txpower(rt2x00dev, libconf->conf->chandef.chan,
4382                                       libconf->conf->power_level);
4383         if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
4384                 rt2800_config_retry_limit(rt2x00dev, libconf);
4385         if (flags & IEEE80211_CONF_CHANGE_PS)
4386                 rt2800_config_ps(rt2x00dev, libconf);
4387 }
4388 EXPORT_SYMBOL_GPL(rt2800_config);
4389
4390 /*
4391  * Link tuning
4392  */
4393 void rt2800_link_stats(struct rt2x00_dev *rt2x00dev, struct link_qual *qual)
4394 {
4395         u32 reg;
4396
4397         /*
4398          * Update FCS error count from register.
4399          */
4400         rt2800_register_read(rt2x00dev, RX_STA_CNT0, &reg);
4401         qual->rx_failed = rt2x00_get_field32(reg, RX_STA_CNT0_CRC_ERR);
4402 }
4403 EXPORT_SYMBOL_GPL(rt2800_link_stats);
4404
4405 static u8 rt2800_get_default_vgc(struct rt2x00_dev *rt2x00dev)
4406 {
4407         u8 vgc;
4408
4409         if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ) {
4410                 if (rt2x00_rt(rt2x00dev, RT3070) ||
4411                     rt2x00_rt(rt2x00dev, RT3071) ||
4412                     rt2x00_rt(rt2x00dev, RT3090) ||
4413                     rt2x00_rt(rt2x00dev, RT3290) ||
4414                     rt2x00_rt(rt2x00dev, RT3390) ||
4415                     rt2x00_rt(rt2x00dev, RT3572) ||
4416                     rt2x00_rt(rt2x00dev, RT3593) ||
4417                     rt2x00_rt(rt2x00dev, RT5390) ||
4418                     rt2x00_rt(rt2x00dev, RT5392) ||
4419                     rt2x00_rt(rt2x00dev, RT5592))
4420                         vgc = 0x1c + (2 * rt2x00dev->lna_gain);
4421                 else
4422                         vgc = 0x2e + rt2x00dev->lna_gain;
4423         } else { /* 5GHZ band */
4424                 if (rt2x00_rt(rt2x00dev, RT3572))
4425                         vgc = 0x22 + (rt2x00dev->lna_gain * 5) / 3;
4426                 else if (rt2x00_rt(rt2x00dev, RT3593))
4427                         vgc = 0x20 + (rt2x00dev->lna_gain * 5) / 3;
4428                 else if (rt2x00_rt(rt2x00dev, RT5592))
4429                         vgc = 0x24 + (2 * rt2x00dev->lna_gain);
4430                 else {
4431                         if (!test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags))
4432                                 vgc = 0x32 + (rt2x00dev->lna_gain * 5) / 3;
4433                         else
4434                                 vgc = 0x3a + (rt2x00dev->lna_gain * 5) / 3;
4435                 }
4436         }
4437
4438         return vgc;
4439 }
4440
4441 static inline void rt2800_set_vgc(struct rt2x00_dev *rt2x00dev,
4442                                   struct link_qual *qual, u8 vgc_level)
4443 {
4444         if (qual->vgc_level != vgc_level) {
4445                 if (rt2x00_rt(rt2x00dev, RT3572) ||
4446                     rt2x00_rt(rt2x00dev, RT3593)) {
4447                         rt2800_bbp_write_with_rx_chain(rt2x00dev, 66,
4448                                                        vgc_level);
4449                 } else if (rt2x00_rt(rt2x00dev, RT5592)) {
4450                         rt2800_bbp_write(rt2x00dev, 83, qual->rssi > -65 ? 0x4a : 0x7a);
4451                         rt2800_bbp_write_with_rx_chain(rt2x00dev, 66, vgc_level);
4452                 } else {
4453                         rt2800_bbp_write(rt2x00dev, 66, vgc_level);
4454                 }
4455
4456                 qual->vgc_level = vgc_level;
4457                 qual->vgc_level_reg = vgc_level;
4458         }
4459 }
4460
4461 void rt2800_reset_tuner(struct rt2x00_dev *rt2x00dev, struct link_qual *qual)
4462 {
4463         rt2800_set_vgc(rt2x00dev, qual, rt2800_get_default_vgc(rt2x00dev));
4464 }
4465 EXPORT_SYMBOL_GPL(rt2800_reset_tuner);
4466
4467 void rt2800_link_tuner(struct rt2x00_dev *rt2x00dev, struct link_qual *qual,
4468                        const u32 count)
4469 {
4470         u8 vgc;
4471
4472         if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C))
4473                 return;
4474         /*
4475          * When RSSI is better then -80 increase VGC level with 0x10, except
4476          * for rt5592 chip.
4477          */
4478
4479         vgc = rt2800_get_default_vgc(rt2x00dev);
4480
4481         if (rt2x00_rt(rt2x00dev, RT5592) && qual->rssi > -65)
4482                 vgc += 0x20;
4483         else if (qual->rssi > -80)
4484                 vgc += 0x10;
4485
4486         rt2800_set_vgc(rt2x00dev, qual, vgc);
4487 }
4488 EXPORT_SYMBOL_GPL(rt2800_link_tuner);
4489
4490 /*
4491  * Initialization functions.
4492  */
4493 static int rt2800_init_registers(struct rt2x00_dev *rt2x00dev)
4494 {
4495         u32 reg;
4496         u16 eeprom;
4497         unsigned int i;
4498         int ret;
4499
4500         rt2800_disable_wpdma(rt2x00dev);
4501
4502         ret = rt2800_drv_init_registers(rt2x00dev);
4503         if (ret)
4504                 return ret;
4505
4506         rt2800_register_read(rt2x00dev, BCN_OFFSET0, &reg);
4507         rt2x00_set_field32(&reg, BCN_OFFSET0_BCN0,
4508                            rt2800_get_beacon_offset(rt2x00dev, 0));
4509         rt2x00_set_field32(&reg, BCN_OFFSET0_BCN1,
4510                            rt2800_get_beacon_offset(rt2x00dev, 1));
4511         rt2x00_set_field32(&reg, BCN_OFFSET0_BCN2,
4512                            rt2800_get_beacon_offset(rt2x00dev, 2));
4513         rt2x00_set_field32(&reg, BCN_OFFSET0_BCN3,
4514                            rt2800_get_beacon_offset(rt2x00dev, 3));
4515         rt2800_register_write(rt2x00dev, BCN_OFFSET0, reg);
4516
4517         rt2800_register_read(rt2x00dev, BCN_OFFSET1, &reg);
4518         rt2x00_set_field32(&reg, BCN_OFFSET1_BCN4,
4519                            rt2800_get_beacon_offset(rt2x00dev, 4));
4520         rt2x00_set_field32(&reg, BCN_OFFSET1_BCN5,
4521                            rt2800_get_beacon_offset(rt2x00dev, 5));
4522         rt2x00_set_field32(&reg, BCN_OFFSET1_BCN6,
4523                            rt2800_get_beacon_offset(rt2x00dev, 6));
4524         rt2x00_set_field32(&reg, BCN_OFFSET1_BCN7,
4525                            rt2800_get_beacon_offset(rt2x00dev, 7));
4526         rt2800_register_write(rt2x00dev, BCN_OFFSET1, reg);
4527
4528         rt2800_register_write(rt2x00dev, LEGACY_BASIC_RATE, 0x0000013f);
4529         rt2800_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
4530
4531         rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000);
4532
4533         rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
4534         rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL, 1600);
4535         rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 0);
4536         rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, 0);
4537         rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 0);
4538         rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
4539         rt2x00_set_field32(&reg, BCN_TIME_CFG_TX_TIME_COMPENSATE, 0);
4540         rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
4541
4542         rt2800_config_filter(rt2x00dev, FIF_ALLMULTI);
4543
4544         rt2800_register_read(rt2x00dev, BKOFF_SLOT_CFG, &reg);
4545         rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_SLOT_TIME, 9);
4546         rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_CC_DELAY_TIME, 2);
4547         rt2800_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg);
4548
4549         if (rt2x00_rt(rt2x00dev, RT3290)) {
4550                 rt2800_register_read(rt2x00dev, WLAN_FUN_CTRL, &reg);
4551                 if (rt2x00_get_field32(reg, WLAN_EN) == 1) {
4552                         rt2x00_set_field32(&reg, PCIE_APP0_CLK_REQ, 1);
4553                         rt2800_register_write(rt2x00dev, WLAN_FUN_CTRL, reg);
4554                 }
4555
4556                 rt2800_register_read(rt2x00dev, CMB_CTRL, &reg);
4557                 if (!(rt2x00_get_field32(reg, LDO0_EN) == 1)) {
4558                         rt2x00_set_field32(&reg, LDO0_EN, 1);
4559                         rt2x00_set_field32(&reg, LDO_BGSEL, 3);
4560                         rt2800_register_write(rt2x00dev, CMB_CTRL, reg);
4561                 }
4562
4563                 rt2800_register_read(rt2x00dev, OSC_CTRL, &reg);
4564                 rt2x00_set_field32(&reg, OSC_ROSC_EN, 1);
4565                 rt2x00_set_field32(&reg, OSC_CAL_REQ, 1);
4566                 rt2x00_set_field32(&reg, OSC_REF_CYCLE, 0x27);
4567                 rt2800_register_write(rt2x00dev, OSC_CTRL, reg);
4568
4569                 rt2800_register_read(rt2x00dev, COEX_CFG0, &reg);
4570                 rt2x00_set_field32(&reg, COEX_CFG_ANT, 0x5e);
4571                 rt2800_register_write(rt2x00dev, COEX_CFG0, reg);
4572
4573                 rt2800_register_read(rt2x00dev, COEX_CFG2, &reg);
4574                 rt2x00_set_field32(&reg, BT_COEX_CFG1, 0x00);
4575                 rt2x00_set_field32(&reg, BT_COEX_CFG0, 0x17);
4576                 rt2x00_set_field32(&reg, WL_COEX_CFG1, 0x93);
4577                 rt2x00_set_field32(&reg, WL_COEX_CFG0, 0x7f);
4578                 rt2800_register_write(rt2x00dev, COEX_CFG2, reg);
4579
4580                 rt2800_register_read(rt2x00dev, PLL_CTRL, &reg);
4581                 rt2x00_set_field32(&reg, PLL_CONTROL, 1);
4582                 rt2800_register_write(rt2x00dev, PLL_CTRL, reg);
4583         }
4584
4585         if (rt2x00_rt(rt2x00dev, RT3071) ||
4586             rt2x00_rt(rt2x00dev, RT3090) ||
4587             rt2x00_rt(rt2x00dev, RT3290) ||
4588             rt2x00_rt(rt2x00dev, RT3390)) {
4589
4590                 if (rt2x00_rt(rt2x00dev, RT3290))
4591                         rt2800_register_write(rt2x00dev, TX_SW_CFG0,
4592                                               0x00000404);
4593                 else
4594                         rt2800_register_write(rt2x00dev, TX_SW_CFG0,
4595                                               0x00000400);
4596
4597                 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
4598                 if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
4599                     rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) ||
4600                     rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E)) {
4601                         rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1,
4602                                            &eeprom);
4603                         if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_DAC_TEST))
4604                                 rt2800_register_write(rt2x00dev, TX_SW_CFG2,
4605                                                       0x0000002c);
4606                         else
4607                                 rt2800_register_write(rt2x00dev, TX_SW_CFG2,
4608                                                       0x0000000f);
4609                 } else {
4610                         rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
4611                 }
4612         } else if (rt2x00_rt(rt2x00dev, RT3070)) {
4613                 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
4614
4615                 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F)) {
4616                         rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
4617                         rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x0000002c);
4618                 } else {
4619                         rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
4620                         rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
4621                 }
4622         } else if (rt2800_is_305x_soc(rt2x00dev)) {
4623                 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
4624                 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
4625                 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000030);
4626         } else if (rt2x00_rt(rt2x00dev, RT3352)) {
4627                 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000402);
4628                 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
4629                 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
4630         } else if (rt2x00_rt(rt2x00dev, RT3572)) {
4631                 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
4632                 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
4633         } else if (rt2x00_rt(rt2x00dev, RT3593)) {
4634                 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000402);
4635                 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
4636                 if (rt2x00_rt_rev_lt(rt2x00dev, RT3593, REV_RT3593E)) {
4637                         rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1,
4638                                            &eeprom);
4639                         if (rt2x00_get_field16(eeprom,
4640                                                EEPROM_NIC_CONF1_DAC_TEST))
4641                                 rt2800_register_write(rt2x00dev, TX_SW_CFG2,
4642                                                       0x0000001f);
4643                         else
4644                                 rt2800_register_write(rt2x00dev, TX_SW_CFG2,
4645                                                       0x0000000f);
4646                 } else {
4647                         rt2800_register_write(rt2x00dev, TX_SW_CFG2,
4648                                               0x00000000);
4649                 }
4650         } else if (rt2x00_rt(rt2x00dev, RT5390) ||
4651                    rt2x00_rt(rt2x00dev, RT5392) ||
4652                    rt2x00_rt(rt2x00dev, RT5592)) {
4653                 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000404);
4654                 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
4655                 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
4656         } else {
4657                 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000000);
4658                 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
4659         }
4660
4661         rt2800_register_read(rt2x00dev, TX_LINK_CFG, &reg);
4662         rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB_LIFETIME, 32);
4663         rt2x00_set_field32(&reg, TX_LINK_CFG_MFB_ENABLE, 0);
4664         rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_UMFS_ENABLE, 0);
4665         rt2x00_set_field32(&reg, TX_LINK_CFG_TX_MRQ_EN, 0);
4666         rt2x00_set_field32(&reg, TX_LINK_CFG_TX_RDG_EN, 0);
4667         rt2x00_set_field32(&reg, TX_LINK_CFG_TX_CF_ACK_EN, 1);
4668         rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB, 0);
4669         rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFS, 0);
4670         rt2800_register_write(rt2x00dev, TX_LINK_CFG, reg);
4671
4672         rt2800_register_read(rt2x00dev, TX_TIMEOUT_CFG, &reg);
4673         rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_MPDU_LIFETIME, 9);
4674         rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_RX_ACK_TIMEOUT, 32);
4675         rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_TX_OP_TIMEOUT, 10);
4676         rt2800_register_write(rt2x00dev, TX_TIMEOUT_CFG, reg);
4677
4678         rt2800_register_read(rt2x00dev, MAX_LEN_CFG, &reg);
4679         rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_MPDU, AGGREGATION_SIZE);
4680         if (rt2x00_rt_rev_gte(rt2x00dev, RT2872, REV_RT2872E) ||
4681             rt2x00_rt(rt2x00dev, RT2883) ||
4682             rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070E))
4683                 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, 2);
4684         else
4685                 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, 1);
4686         rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_PSDU, 0);
4687         rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_MPDU, 0);
4688         rt2800_register_write(rt2x00dev, MAX_LEN_CFG, reg);
4689
4690         rt2800_register_read(rt2x00dev, LED_CFG, &reg);
4691         rt2x00_set_field32(&reg, LED_CFG_ON_PERIOD, 70);
4692         rt2x00_set_field32(&reg, LED_CFG_OFF_PERIOD, 30);
4693         rt2x00_set_field32(&reg, LED_CFG_SLOW_BLINK_PERIOD, 3);
4694         rt2x00_set_field32(&reg, LED_CFG_R_LED_MODE, 3);
4695         rt2x00_set_field32(&reg, LED_CFG_G_LED_MODE, 3);
4696         rt2x00_set_field32(&reg, LED_CFG_Y_LED_MODE, 3);
4697         rt2x00_set_field32(&reg, LED_CFG_LED_POLAR, 1);
4698         rt2800_register_write(rt2x00dev, LED_CFG, reg);
4699
4700         rt2800_register_write(rt2x00dev, PBF_MAX_PCNT, 0x1f3fbf9f);
4701
4702         rt2800_register_read(rt2x00dev, TX_RTY_CFG, &reg);
4703         rt2x00_set_field32(&reg, TX_RTY_CFG_SHORT_RTY_LIMIT, 15);
4704         rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_LIMIT, 31);
4705         rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_THRE, 2000);
4706         rt2x00_set_field32(&reg, TX_RTY_CFG_NON_AGG_RTY_MODE, 0);
4707         rt2x00_set_field32(&reg, TX_RTY_CFG_AGG_RTY_MODE, 0);
4708         rt2x00_set_field32(&reg, TX_RTY_CFG_TX_AUTO_FB_ENABLE, 1);
4709         rt2800_register_write(rt2x00dev, TX_RTY_CFG, reg);
4710
4711         rt2800_register_read(rt2x00dev, AUTO_RSP_CFG, &reg);
4712         rt2x00_set_field32(&reg, AUTO_RSP_CFG_AUTORESPONDER, 1);
4713         rt2x00_set_field32(&reg, AUTO_RSP_CFG_BAC_ACK_POLICY, 1);
4714         rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MMODE, 0);
4715         rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MREF, 0);
4716         rt2x00_set_field32(&reg, AUTO_RSP_CFG_AR_PREAMBLE, 1);
4717         rt2x00_set_field32(&reg, AUTO_RSP_CFG_DUAL_CTS_EN, 0);
4718         rt2x00_set_field32(&reg, AUTO_RSP_CFG_ACK_CTS_PSM_BIT, 0);
4719         rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
4720
4721         rt2800_register_read(rt2x00dev, CCK_PROT_CFG, &reg);
4722         rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_RATE, 3);
4723         rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_CTRL, 0);
4724         rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_NAV_SHORT, 1);
4725         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_CCK, 1);
4726         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
4727         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM20, 1);
4728         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM40, 0);
4729         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF20, 1);
4730         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF40, 0);
4731         rt2x00_set_field32(&reg, CCK_PROT_CFG_RTS_TH_EN, 1);
4732         rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg);
4733
4734         rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
4735         rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_RATE, 3);
4736         rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL, 0);
4737         rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_NAV_SHORT, 1);
4738         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_CCK, 1);
4739         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
4740         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM20, 1);
4741         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM40, 0);
4742         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF20, 1);
4743         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF40, 0);
4744         rt2x00_set_field32(&reg, OFDM_PROT_CFG_RTS_TH_EN, 1);
4745         rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
4746
4747         rt2800_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
4748         rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_RATE, 0x4004);
4749         rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_CTRL, 0);
4750         rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_NAV_SHORT, 1);
4751         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_CCK, 1);
4752         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
4753         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
4754         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
4755         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
4756         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
4757         rt2x00_set_field32(&reg, MM20_PROT_CFG_RTS_TH_EN, 0);
4758         rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
4759
4760         rt2800_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
4761         rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_RATE, 0x4084);
4762         rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_CTRL, 0);
4763         rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_NAV_SHORT, 1);
4764         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_CCK, 1);
4765         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
4766         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
4767         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
4768         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
4769         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
4770         rt2x00_set_field32(&reg, MM40_PROT_CFG_RTS_TH_EN, 0);
4771         rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
4772
4773         rt2800_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
4774         rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_RATE, 0x4004);
4775         rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_CTRL, 0);
4776         rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_NAV_SHORT, 1);
4777         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_CCK, 1);
4778         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
4779         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
4780         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
4781         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
4782         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
4783         rt2x00_set_field32(&reg, GF20_PROT_CFG_RTS_TH_EN, 0);
4784         rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
4785
4786         rt2800_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
4787         rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_RATE, 0x4084);
4788         rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_CTRL, 0);
4789         rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_NAV_SHORT, 1);
4790         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_CCK, 1);
4791         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
4792         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
4793         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
4794         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
4795         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
4796         rt2x00_set_field32(&reg, GF40_PROT_CFG_RTS_TH_EN, 0);
4797         rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
4798
4799         if (rt2x00_is_usb(rt2x00dev)) {
4800                 rt2800_register_write(rt2x00dev, PBF_CFG, 0xf40006);
4801
4802                 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
4803                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
4804                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
4805                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
4806                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
4807                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE, 3);
4808                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 0);
4809                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_BIG_ENDIAN, 0);
4810                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_HDR_SCATTER, 0);
4811                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_HDR_SEG_LEN, 0);
4812                 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
4813         }
4814
4815         /*
4816          * The legacy driver also sets TXOP_CTRL_CFG_RESERVED_TRUN_EN to 1
4817          * although it is reserved.
4818          */
4819         rt2800_register_read(rt2x00dev, TXOP_CTRL_CFG, &reg);
4820         rt2x00_set_field32(&reg, TXOP_CTRL_CFG_TIMEOUT_TRUN_EN, 1);
4821         rt2x00_set_field32(&reg, TXOP_CTRL_CFG_AC_TRUN_EN, 1);
4822         rt2x00_set_field32(&reg, TXOP_CTRL_CFG_TXRATEGRP_TRUN_EN, 1);
4823         rt2x00_set_field32(&reg, TXOP_CTRL_CFG_USER_MODE_TRUN_EN, 1);
4824         rt2x00_set_field32(&reg, TXOP_CTRL_CFG_MIMO_PS_TRUN_EN, 1);
4825         rt2x00_set_field32(&reg, TXOP_CTRL_CFG_RESERVED_TRUN_EN, 1);
4826         rt2x00_set_field32(&reg, TXOP_CTRL_CFG_LSIG_TXOP_EN, 0);
4827         rt2x00_set_field32(&reg, TXOP_CTRL_CFG_EXT_CCA_EN, 0);
4828         rt2x00_set_field32(&reg, TXOP_CTRL_CFG_EXT_CCA_DLY, 88);
4829         rt2x00_set_field32(&reg, TXOP_CTRL_CFG_EXT_CWMIN, 0);
4830         rt2800_register_write(rt2x00dev, TXOP_CTRL_CFG, reg);
4831
4832         reg = rt2x00_rt(rt2x00dev, RT5592) ? 0x00000082 : 0x00000002;
4833         rt2800_register_write(rt2x00dev, TXOP_HLDR_ET, reg);
4834
4835         rt2800_register_read(rt2x00dev, TX_RTS_CFG, &reg);
4836         rt2x00_set_field32(&reg, TX_RTS_CFG_AUTO_RTS_RETRY_LIMIT, 32);
4837         rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_THRES,
4838                            IEEE80211_MAX_RTS_THRESHOLD);
4839         rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_FBK_EN, 0);
4840         rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg);
4841
4842         rt2800_register_write(rt2x00dev, EXP_ACK_TIME, 0x002400ca);
4843
4844         /*
4845          * Usually the CCK SIFS time should be set to 10 and the OFDM SIFS
4846          * time should be set to 16. However, the original Ralink driver uses
4847          * 16 for both and indeed using a value of 10 for CCK SIFS results in
4848          * connection problems with 11g + CTS protection. Hence, use the same
4849          * defaults as the Ralink driver: 16 for both, CCK and OFDM SIFS.
4850          */
4851         rt2800_register_read(rt2x00dev, XIFS_TIME_CFG, &reg);
4852         rt2x00_set_field32(&reg, XIFS_TIME_CFG_CCKM_SIFS_TIME, 16);
4853         rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_SIFS_TIME, 16);
4854         rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_XIFS_TIME, 4);
4855         rt2x00_set_field32(&reg, XIFS_TIME_CFG_EIFS, 314);
4856         rt2x00_set_field32(&reg, XIFS_TIME_CFG_BB_RXEND_ENABLE, 1);
4857         rt2800_register_write(rt2x00dev, XIFS_TIME_CFG, reg);
4858
4859         rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000003);
4860
4861         /*
4862          * ASIC will keep garbage value after boot, clear encryption keys.
4863          */
4864         for (i = 0; i < 4; i++)
4865                 rt2800_register_write(rt2x00dev,
4866                                          SHARED_KEY_MODE_ENTRY(i), 0);
4867
4868         for (i = 0; i < 256; i++) {
4869                 rt2800_config_wcid(rt2x00dev, NULL, i);
4870                 rt2800_delete_wcid_attr(rt2x00dev, i);
4871                 rt2800_register_write(rt2x00dev, MAC_IVEIV_ENTRY(i), 0);
4872         }
4873
4874         /*
4875          * Clear all beacons
4876          */
4877         for (i = 0; i < 8; i++)
4878                 rt2800_clear_beacon_register(rt2x00dev, i);
4879
4880         if (rt2x00_is_usb(rt2x00dev)) {
4881                 rt2800_register_read(rt2x00dev, US_CYC_CNT, &reg);
4882                 rt2x00_set_field32(&reg, US_CYC_CNT_CLOCK_CYCLE, 30);
4883                 rt2800_register_write(rt2x00dev, US_CYC_CNT, reg);
4884         } else if (rt2x00_is_pcie(rt2x00dev)) {
4885                 rt2800_register_read(rt2x00dev, US_CYC_CNT, &reg);
4886                 rt2x00_set_field32(&reg, US_CYC_CNT_CLOCK_CYCLE, 125);
4887                 rt2800_register_write(rt2x00dev, US_CYC_CNT, reg);
4888         }
4889
4890         rt2800_register_read(rt2x00dev, HT_FBK_CFG0, &reg);
4891         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS0FBK, 0);
4892         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS1FBK, 0);
4893         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS2FBK, 1);
4894         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS3FBK, 2);
4895         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS4FBK, 3);
4896         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS5FBK, 4);
4897         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS6FBK, 5);
4898         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS7FBK, 6);
4899         rt2800_register_write(rt2x00dev, HT_FBK_CFG0, reg);
4900
4901         rt2800_register_read(rt2x00dev, HT_FBK_CFG1, &reg);
4902         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS8FBK, 8);
4903         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS9FBK, 8);
4904         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS10FBK, 9);
4905         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS11FBK, 10);
4906         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS12FBK, 11);
4907         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS13FBK, 12);
4908         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS14FBK, 13);
4909         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS15FBK, 14);
4910         rt2800_register_write(rt2x00dev, HT_FBK_CFG1, reg);
4911
4912         rt2800_register_read(rt2x00dev, LG_FBK_CFG0, &reg);
4913         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS0FBK, 8);
4914         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS1FBK, 8);
4915         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS2FBK, 9);
4916         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS3FBK, 10);
4917         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS4FBK, 11);
4918         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS5FBK, 12);
4919         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS6FBK, 13);
4920         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS7FBK, 14);
4921         rt2800_register_write(rt2x00dev, LG_FBK_CFG0, reg);
4922
4923         rt2800_register_read(rt2x00dev, LG_FBK_CFG1, &reg);
4924         rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS0FBK, 0);
4925         rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS1FBK, 0);
4926         rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS2FBK, 1);
4927         rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS3FBK, 2);
4928         rt2800_register_write(rt2x00dev, LG_FBK_CFG1, reg);
4929
4930         /*
4931          * Do not force the BA window size, we use the TXWI to set it
4932          */
4933         rt2800_register_read(rt2x00dev, AMPDU_BA_WINSIZE, &reg);
4934         rt2x00_set_field32(&reg, AMPDU_BA_WINSIZE_FORCE_WINSIZE_ENABLE, 0);
4935         rt2x00_set_field32(&reg, AMPDU_BA_WINSIZE_FORCE_WINSIZE, 0);
4936         rt2800_register_write(rt2x00dev, AMPDU_BA_WINSIZE, reg);
4937
4938         /*
4939          * We must clear the error counters.
4940          * These registers are cleared on read,
4941          * so we may pass a useless variable to store the value.
4942          */
4943         rt2800_register_read(rt2x00dev, RX_STA_CNT0, &reg);
4944         rt2800_register_read(rt2x00dev, RX_STA_CNT1, &reg);
4945         rt2800_register_read(rt2x00dev, RX_STA_CNT2, &reg);
4946         rt2800_register_read(rt2x00dev, TX_STA_CNT0, &reg);
4947         rt2800_register_read(rt2x00dev, TX_STA_CNT1, &reg);
4948         rt2800_register_read(rt2x00dev, TX_STA_CNT2, &reg);
4949
4950         /*
4951          * Setup leadtime for pre tbtt interrupt to 6ms
4952          */
4953         rt2800_register_read(rt2x00dev, INT_TIMER_CFG, &reg);
4954         rt2x00_set_field32(&reg, INT_TIMER_CFG_PRE_TBTT_TIMER, 6 << 4);
4955         rt2800_register_write(rt2x00dev, INT_TIMER_CFG, reg);
4956
4957         /*
4958          * Set up channel statistics timer
4959          */
4960         rt2800_register_read(rt2x00dev, CH_TIME_CFG, &reg);
4961         rt2x00_set_field32(&reg, CH_TIME_CFG_EIFS_BUSY, 1);
4962         rt2x00_set_field32(&reg, CH_TIME_CFG_NAV_BUSY, 1);
4963         rt2x00_set_field32(&reg, CH_TIME_CFG_RX_BUSY, 1);
4964         rt2x00_set_field32(&reg, CH_TIME_CFG_TX_BUSY, 1);
4965         rt2x00_set_field32(&reg, CH_TIME_CFG_TMR_EN, 1);
4966         rt2800_register_write(rt2x00dev, CH_TIME_CFG, reg);
4967
4968         return 0;
4969 }
4970
4971 static int rt2800_wait_bbp_rf_ready(struct rt2x00_dev *rt2x00dev)
4972 {
4973         unsigned int i;
4974         u32 reg;
4975
4976         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
4977                 rt2800_register_read(rt2x00dev, MAC_STATUS_CFG, &reg);
4978                 if (!rt2x00_get_field32(reg, MAC_STATUS_CFG_BBP_RF_BUSY))
4979                         return 0;
4980
4981                 udelay(REGISTER_BUSY_DELAY);
4982         }
4983
4984         rt2x00_err(rt2x00dev, "BBP/RF register access failed, aborting\n");
4985         return -EACCES;
4986 }
4987
4988 static int rt2800_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)
4989 {
4990         unsigned int i;
4991         u8 value;
4992
4993         /*
4994          * BBP was enabled after firmware was loaded,
4995          * but we need to reactivate it now.
4996          */
4997         rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
4998         rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
4999         msleep(1);
5000
5001         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
5002                 rt2800_bbp_read(rt2x00dev, 0, &value);
5003                 if ((value != 0xff) && (value != 0x00))
5004                         return 0;
5005                 udelay(REGISTER_BUSY_DELAY);
5006         }
5007
5008         rt2x00_err(rt2x00dev, "BBP register access failed, aborting\n");
5009         return -EACCES;
5010 }
5011
5012 static void rt2800_bbp4_mac_if_ctrl(struct rt2x00_dev *rt2x00dev)
5013 {
5014         u8 value;
5015
5016         rt2800_bbp_read(rt2x00dev, 4, &value);
5017         rt2x00_set_field8(&value, BBP4_MAC_IF_CTRL, 1);
5018         rt2800_bbp_write(rt2x00dev, 4, value);
5019 }
5020
5021 static void rt2800_init_freq_calibration(struct rt2x00_dev *rt2x00dev)
5022 {
5023         rt2800_bbp_write(rt2x00dev, 142, 1);
5024         rt2800_bbp_write(rt2x00dev, 143, 57);
5025 }
5026
5027 static void rt2800_init_bbp_5592_glrt(struct rt2x00_dev *rt2x00dev)
5028 {
5029         const u8 glrt_table[] = {
5030                 0xE0, 0x1F, 0X38, 0x32, 0x08, 0x28, 0x19, 0x0A, 0xFF, 0x00, /* 128 ~ 137 */
5031                 0x16, 0x10, 0x10, 0x0B, 0x36, 0x2C, 0x26, 0x24, 0x42, 0x36, /* 138 ~ 147 */
5032                 0x30, 0x2D, 0x4C, 0x46, 0x3D, 0x40, 0x3E, 0x42, 0x3D, 0x40, /* 148 ~ 157 */
5033                 0X3C, 0x34, 0x2C, 0x2F, 0x3C, 0x35, 0x2E, 0x2A, 0x49, 0x41, /* 158 ~ 167 */
5034                 0x36, 0x31, 0x30, 0x30, 0x0E, 0x0D, 0x28, 0x21, 0x1C, 0x16, /* 168 ~ 177 */
5035                 0x50, 0x4A, 0x43, 0x40, 0x10, 0x10, 0x10, 0x10, 0x00, 0x00, /* 178 ~ 187 */
5036                 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 188 ~ 197 */
5037                 0x00, 0x00, 0x7D, 0x14, 0x32, 0x2C, 0x36, 0x4C, 0x43, 0x2C, /* 198 ~ 207 */
5038                 0x2E, 0x36, 0x30, 0x6E,                                     /* 208 ~ 211 */
5039         };
5040         int i;
5041
5042         for (i = 0; i < ARRAY_SIZE(glrt_table); i++) {
5043                 rt2800_bbp_write(rt2x00dev, 195, 128 + i);
5044                 rt2800_bbp_write(rt2x00dev, 196, glrt_table[i]);
5045         }
5046 };
5047
5048 static void rt2800_init_bbp_early(struct rt2x00_dev *rt2x00dev)
5049 {
5050         rt2800_bbp_write(rt2x00dev, 65, 0x2C);
5051         rt2800_bbp_write(rt2x00dev, 66, 0x38);
5052         rt2800_bbp_write(rt2x00dev, 68, 0x0B);
5053         rt2800_bbp_write(rt2x00dev, 69, 0x12);
5054         rt2800_bbp_write(rt2x00dev, 70, 0x0a);
5055         rt2800_bbp_write(rt2x00dev, 73, 0x10);
5056         rt2800_bbp_write(rt2x00dev, 81, 0x37);
5057         rt2800_bbp_write(rt2x00dev, 82, 0x62);
5058         rt2800_bbp_write(rt2x00dev, 83, 0x6A);
5059         rt2800_bbp_write(rt2x00dev, 84, 0x99);
5060         rt2800_bbp_write(rt2x00dev, 86, 0x00);
5061         rt2800_bbp_write(rt2x00dev, 91, 0x04);
5062         rt2800_bbp_write(rt2x00dev, 92, 0x00);
5063         rt2800_bbp_write(rt2x00dev, 103, 0x00);
5064         rt2800_bbp_write(rt2x00dev, 105, 0x05);
5065         rt2800_bbp_write(rt2x00dev, 106, 0x35);
5066 }
5067
5068 static void rt2800_disable_unused_dac_adc(struct rt2x00_dev *rt2x00dev)
5069 {
5070         u16 eeprom;
5071         u8 value;
5072
5073         rt2800_bbp_read(rt2x00dev, 138, &value);
5074         rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom);
5075         if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) == 1)
5076                 value |= 0x20;
5077         if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) == 1)
5078                 value &= ~0x02;
5079         rt2800_bbp_write(rt2x00dev, 138, value);
5080 }
5081
5082 static void rt2800_init_bbp_305x_soc(struct rt2x00_dev *rt2x00dev)
5083 {
5084         rt2800_bbp_write(rt2x00dev, 31, 0x08);
5085
5086         rt2800_bbp_write(rt2x00dev, 65, 0x2c);
5087         rt2800_bbp_write(rt2x00dev, 66, 0x38);
5088
5089         rt2800_bbp_write(rt2x00dev, 69, 0x12);
5090         rt2800_bbp_write(rt2x00dev, 73, 0x10);
5091
5092         rt2800_bbp_write(rt2x00dev, 70, 0x0a);
5093
5094         rt2800_bbp_write(rt2x00dev, 78, 0x0e);
5095         rt2800_bbp_write(rt2x00dev, 80, 0x08);
5096
5097         rt2800_bbp_write(rt2x00dev, 82, 0x62);
5098
5099         rt2800_bbp_write(rt2x00dev, 83, 0x6a);
5100
5101         rt2800_bbp_write(rt2x00dev, 84, 0x99);
5102
5103         rt2800_bbp_write(rt2x00dev, 86, 0x00);
5104
5105         rt2800_bbp_write(rt2x00dev, 91, 0x04);
5106
5107         rt2800_bbp_write(rt2x00dev, 92, 0x00);
5108
5109         rt2800_bbp_write(rt2x00dev, 103, 0xc0);
5110
5111         rt2800_bbp_write(rt2x00dev, 105, 0x01);
5112
5113         rt2800_bbp_write(rt2x00dev, 106, 0x35);
5114 }
5115
5116 static void rt2800_init_bbp_28xx(struct rt2x00_dev *rt2x00dev)
5117 {
5118         rt2800_bbp_write(rt2x00dev, 65, 0x2c);
5119         rt2800_bbp_write(rt2x00dev, 66, 0x38);
5120
5121         if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C)) {
5122                 rt2800_bbp_write(rt2x00dev, 69, 0x16);
5123                 rt2800_bbp_write(rt2x00dev, 73, 0x12);
5124         } else {
5125                 rt2800_bbp_write(rt2x00dev, 69, 0x12);
5126                 rt2800_bbp_write(rt2x00dev, 73, 0x10);
5127         }
5128
5129         rt2800_bbp_write(rt2x00dev, 70, 0x0a);
5130
5131         rt2800_bbp_write(rt2x00dev, 81, 0x37);
5132
5133         rt2800_bbp_write(rt2x00dev, 82, 0x62);
5134
5135         rt2800_bbp_write(rt2x00dev, 83, 0x6a);
5136
5137         if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860D))
5138                 rt2800_bbp_write(rt2x00dev, 84, 0x19);
5139         else
5140                 rt2800_bbp_write(rt2x00dev, 84, 0x99);
5141
5142         rt2800_bbp_write(rt2x00dev, 86, 0x00);
5143
5144         rt2800_bbp_write(rt2x00dev, 91, 0x04);
5145
5146         rt2800_bbp_write(rt2x00dev, 92, 0x00);
5147
5148         rt2800_bbp_write(rt2x00dev, 103, 0x00);
5149
5150         rt2800_bbp_write(rt2x00dev, 105, 0x05);
5151
5152         rt2800_bbp_write(rt2x00dev, 106, 0x35);
5153 }
5154
5155 static void rt2800_init_bbp_30xx(struct rt2x00_dev *rt2x00dev)
5156 {
5157         rt2800_bbp_write(rt2x00dev, 65, 0x2c);
5158         rt2800_bbp_write(rt2x00dev, 66, 0x38);
5159
5160         rt2800_bbp_write(rt2x00dev, 69, 0x12);
5161         rt2800_bbp_write(rt2x00dev, 73, 0x10);
5162
5163         rt2800_bbp_write(rt2x00dev, 70, 0x0a);
5164
5165         rt2800_bbp_write(rt2x00dev, 79, 0x13);
5166         rt2800_bbp_write(rt2x00dev, 80, 0x05);
5167         rt2800_bbp_write(rt2x00dev, 81, 0x33);
5168
5169         rt2800_bbp_write(rt2x00dev, 82, 0x62);
5170
5171         rt2800_bbp_write(rt2x00dev, 83, 0x6a);
5172
5173         rt2800_bbp_write(rt2x00dev, 84, 0x99);
5174
5175         rt2800_bbp_write(rt2x00dev, 86, 0x00);
5176
5177         rt2800_bbp_write(rt2x00dev, 91, 0x04);
5178
5179         rt2800_bbp_write(rt2x00dev, 92, 0x00);
5180
5181         if (rt2x00_rt_rev_gte(rt2x00dev, RT3070, REV_RT3070F) ||
5182             rt2x00_rt_rev_gte(rt2x00dev, RT3071, REV_RT3071E) ||
5183             rt2x00_rt_rev_gte(rt2x00dev, RT3090, REV_RT3090E))
5184                 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
5185         else
5186                 rt2800_bbp_write(rt2x00dev, 103, 0x00);
5187
5188         rt2800_bbp_write(rt2x00dev, 105, 0x05);
5189
5190         rt2800_bbp_write(rt2x00dev, 106, 0x35);
5191
5192         if (rt2x00_rt(rt2x00dev, RT3071) ||
5193             rt2x00_rt(rt2x00dev, RT3090))
5194                 rt2800_disable_unused_dac_adc(rt2x00dev);
5195 }
5196
5197 static void rt2800_init_bbp_3290(struct rt2x00_dev *rt2x00dev)
5198 {
5199         u8 value;
5200
5201         rt2800_bbp4_mac_if_ctrl(rt2x00dev);
5202
5203         rt2800_bbp_write(rt2x00dev, 31, 0x08);
5204
5205         rt2800_bbp_write(rt2x00dev, 65, 0x2c);
5206         rt2800_bbp_write(rt2x00dev, 66, 0x38);
5207
5208         rt2800_bbp_write(rt2x00dev, 68, 0x0b);
5209
5210         rt2800_bbp_write(rt2x00dev, 69, 0x12);
5211         rt2800_bbp_write(rt2x00dev, 73, 0x13);
5212         rt2800_bbp_write(rt2x00dev, 75, 0x46);
5213         rt2800_bbp_write(rt2x00dev, 76, 0x28);
5214
5215         rt2800_bbp_write(rt2x00dev, 77, 0x58);
5216
5217         rt2800_bbp_write(rt2x00dev, 70, 0x0a);
5218
5219         rt2800_bbp_write(rt2x00dev, 74, 0x0b);
5220         rt2800_bbp_write(rt2x00dev, 79, 0x18);
5221         rt2800_bbp_write(rt2x00dev, 80, 0x09);
5222         rt2800_bbp_write(rt2x00dev, 81, 0x33);
5223
5224         rt2800_bbp_write(rt2x00dev, 82, 0x62);
5225
5226         rt2800_bbp_write(rt2x00dev, 83, 0x7a);
5227
5228         rt2800_bbp_write(rt2x00dev, 84, 0x9a);
5229
5230         rt2800_bbp_write(rt2x00dev, 86, 0x38);
5231
5232         rt2800_bbp_write(rt2x00dev, 91, 0x04);
5233
5234         rt2800_bbp_write(rt2x00dev, 92, 0x02);
5235
5236         rt2800_bbp_write(rt2x00dev, 103, 0xc0);
5237
5238         rt2800_bbp_write(rt2x00dev, 104, 0x92);
5239
5240         rt2800_bbp_write(rt2x00dev, 105, 0x1c);
5241
5242         rt2800_bbp_write(rt2x00dev, 106, 0x03);
5243
5244         rt2800_bbp_write(rt2x00dev, 128, 0x12);
5245
5246         rt2800_bbp_write(rt2x00dev, 67, 0x24);
5247         rt2800_bbp_write(rt2x00dev, 143, 0x04);
5248         rt2800_bbp_write(rt2x00dev, 142, 0x99);
5249         rt2800_bbp_write(rt2x00dev, 150, 0x30);
5250         rt2800_bbp_write(rt2x00dev, 151, 0x2e);
5251         rt2800_bbp_write(rt2x00dev, 152, 0x20);
5252         rt2800_bbp_write(rt2x00dev, 153, 0x34);
5253         rt2800_bbp_write(rt2x00dev, 154, 0x40);
5254         rt2800_bbp_write(rt2x00dev, 155, 0x3b);
5255         rt2800_bbp_write(rt2x00dev, 253, 0x04);
5256
5257         rt2800_bbp_read(rt2x00dev, 47, &value);
5258         rt2x00_set_field8(&value, BBP47_TSSI_ADC6, 1);
5259         rt2800_bbp_write(rt2x00dev, 47, value);
5260
5261         /* Use 5-bit ADC for Acquisition and 8-bit ADC for data */
5262         rt2800_bbp_read(rt2x00dev, 3, &value);
5263         rt2x00_set_field8(&value, BBP3_ADC_MODE_SWITCH, 1);
5264         rt2x00_set_field8(&value, BBP3_ADC_INIT_MODE, 1);
5265         rt2800_bbp_write(rt2x00dev, 3, value);
5266 }
5267
5268 static void rt2800_init_bbp_3352(struct rt2x00_dev *rt2x00dev)
5269 {
5270         rt2800_bbp_write(rt2x00dev, 3, 0x00);
5271         rt2800_bbp_write(rt2x00dev, 4, 0x50);
5272
5273         rt2800_bbp_write(rt2x00dev, 31, 0x08);
5274
5275         rt2800_bbp_write(rt2x00dev, 47, 0x48);
5276
5277         rt2800_bbp_write(rt2x00dev, 65, 0x2c);
5278         rt2800_bbp_write(rt2x00dev, 66, 0x38);
5279
5280         rt2800_bbp_write(rt2x00dev, 68, 0x0b);
5281
5282         rt2800_bbp_write(rt2x00dev, 69, 0x12);
5283         rt2800_bbp_write(rt2x00dev, 73, 0x13);
5284         rt2800_bbp_write(rt2x00dev, 75, 0x46);
5285         rt2800_bbp_write(rt2x00dev, 76, 0x28);
5286
5287         rt2800_bbp_write(rt2x00dev, 77, 0x59);
5288
5289         rt2800_bbp_write(rt2x00dev, 70, 0x0a);
5290
5291         rt2800_bbp_write(rt2x00dev, 78, 0x0e);
5292         rt2800_bbp_write(rt2x00dev, 80, 0x08);
5293         rt2800_bbp_write(rt2x00dev, 81, 0x37);
5294
5295         rt2800_bbp_write(rt2x00dev, 82, 0x62);
5296
5297         rt2800_bbp_write(rt2x00dev, 83, 0x6a);
5298
5299         rt2800_bbp_write(rt2x00dev, 84, 0x99);
5300
5301         rt2800_bbp_write(rt2x00dev, 86, 0x38);
5302
5303         rt2800_bbp_write(rt2x00dev, 88, 0x90);
5304
5305         rt2800_bbp_write(rt2x00dev, 91, 0x04);
5306
5307         rt2800_bbp_write(rt2x00dev, 92, 0x02);
5308
5309         rt2800_bbp_write(rt2x00dev, 103, 0xc0);
5310
5311         rt2800_bbp_write(rt2x00dev, 104, 0x92);
5312
5313         rt2800_bbp_write(rt2x00dev, 105, 0x34);
5314
5315         rt2800_bbp_write(rt2x00dev, 106, 0x05);
5316
5317         rt2800_bbp_write(rt2x00dev, 120, 0x50);
5318
5319         rt2800_bbp_write(rt2x00dev, 137, 0x0f);
5320
5321         rt2800_bbp_write(rt2x00dev, 163, 0xbd);
5322         /* Set ITxBF timeout to 0x9c40=1000msec */
5323         rt2800_bbp_write(rt2x00dev, 179, 0x02);
5324         rt2800_bbp_write(rt2x00dev, 180, 0x00);
5325         rt2800_bbp_write(rt2x00dev, 182, 0x40);
5326         rt2800_bbp_write(rt2x00dev, 180, 0x01);
5327         rt2800_bbp_write(rt2x00dev, 182, 0x9c);
5328         rt2800_bbp_write(rt2x00dev, 179, 0x00);
5329         /* Reprogram the inband interface to put right values in RXWI */
5330         rt2800_bbp_write(rt2x00dev, 142, 0x04);
5331         rt2800_bbp_write(rt2x00dev, 143, 0x3b);
5332         rt2800_bbp_write(rt2x00dev, 142, 0x06);
5333         rt2800_bbp_write(rt2x00dev, 143, 0xa0);
5334         rt2800_bbp_write(rt2x00dev, 142, 0x07);
5335         rt2800_bbp_write(rt2x00dev, 143, 0xa1);
5336         rt2800_bbp_write(rt2x00dev, 142, 0x08);
5337         rt2800_bbp_write(rt2x00dev, 143, 0xa2);
5338
5339         rt2800_bbp_write(rt2x00dev, 148, 0xc8);
5340 }
5341
5342 static void rt2800_init_bbp_3390(struct rt2x00_dev *rt2x00dev)
5343 {
5344         rt2800_bbp_write(rt2x00dev, 65, 0x2c);
5345         rt2800_bbp_write(rt2x00dev, 66, 0x38);
5346
5347         rt2800_bbp_write(rt2x00dev, 69, 0x12);
5348         rt2800_bbp_write(rt2x00dev, 73, 0x10);
5349
5350         rt2800_bbp_write(rt2x00dev, 70, 0x0a);
5351
5352         rt2800_bbp_write(rt2x00dev, 79, 0x13);
5353         rt2800_bbp_write(rt2x00dev, 80, 0x05);
5354         rt2800_bbp_write(rt2x00dev, 81, 0x33);
5355
5356         rt2800_bbp_write(rt2x00dev, 82, 0x62);
5357
5358         rt2800_bbp_write(rt2x00dev, 83, 0x6a);
5359
5360         rt2800_bbp_write(rt2x00dev, 84, 0x99);
5361
5362         rt2800_bbp_write(rt2x00dev, 86, 0x00);
5363
5364         rt2800_bbp_write(rt2x00dev, 91, 0x04);
5365
5366         rt2800_bbp_write(rt2x00dev, 92, 0x00);
5367
5368         if (rt2x00_rt_rev_gte(rt2x00dev, RT3390, REV_RT3390E))
5369                 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
5370         else
5371                 rt2800_bbp_write(rt2x00dev, 103, 0x00);
5372
5373         rt2800_bbp_write(rt2x00dev, 105, 0x05);
5374
5375         rt2800_bbp_write(rt2x00dev, 106, 0x35);
5376
5377         rt2800_disable_unused_dac_adc(rt2x00dev);
5378 }
5379
5380 static void rt2800_init_bbp_3572(struct rt2x00_dev *rt2x00dev)
5381 {
5382         rt2800_bbp_write(rt2x00dev, 31, 0x08);
5383
5384         rt2800_bbp_write(rt2x00dev, 65, 0x2c);
5385         rt2800_bbp_write(rt2x00dev, 66, 0x38);
5386
5387         rt2800_bbp_write(rt2x00dev, 69, 0x12);
5388         rt2800_bbp_write(rt2x00dev, 73, 0x10);
5389
5390         rt2800_bbp_write(rt2x00dev, 70, 0x0a);
5391
5392         rt2800_bbp_write(rt2x00dev, 79, 0x13);
5393         rt2800_bbp_write(rt2x00dev, 80, 0x05);
5394         rt2800_bbp_write(rt2x00dev, 81, 0x33);
5395
5396         rt2800_bbp_write(rt2x00dev, 82, 0x62);
5397
5398         rt2800_bbp_write(rt2x00dev, 83, 0x6a);
5399
5400         rt2800_bbp_write(rt2x00dev, 84, 0x99);
5401
5402         rt2800_bbp_write(rt2x00dev, 86, 0x00);
5403
5404         rt2800_bbp_write(rt2x00dev, 91, 0x04);
5405
5406         rt2800_bbp_write(rt2x00dev, 92, 0x00);
5407
5408         rt2800_bbp_write(rt2x00dev, 103, 0xc0);
5409
5410         rt2800_bbp_write(rt2x00dev, 105, 0x05);
5411
5412         rt2800_bbp_write(rt2x00dev, 106, 0x35);
5413
5414         rt2800_disable_unused_dac_adc(rt2x00dev);
5415 }
5416
5417 static void rt2800_init_bbp_3593(struct rt2x00_dev *rt2x00dev)
5418 {
5419         rt2800_init_bbp_early(rt2x00dev);
5420
5421         rt2800_bbp_write(rt2x00dev, 79, 0x13);
5422         rt2800_bbp_write(rt2x00dev, 80, 0x05);
5423         rt2800_bbp_write(rt2x00dev, 81, 0x33);
5424         rt2800_bbp_write(rt2x00dev, 137, 0x0f);
5425
5426         rt2800_bbp_write(rt2x00dev, 84, 0x19);
5427
5428         /* Enable DC filter */
5429         if (rt2x00_rt_rev_gte(rt2x00dev, RT3593, REV_RT3593E))
5430                 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
5431 }
5432
5433 static void rt2800_init_bbp_53xx(struct rt2x00_dev *rt2x00dev)
5434 {
5435         int ant, div_mode;
5436         u16 eeprom;
5437         u8 value;
5438
5439         rt2800_bbp4_mac_if_ctrl(rt2x00dev);
5440
5441         rt2800_bbp_write(rt2x00dev, 31, 0x08);
5442
5443         rt2800_bbp_write(rt2x00dev, 65, 0x2c);
5444         rt2800_bbp_write(rt2x00dev, 66, 0x38);
5445
5446         rt2800_bbp_write(rt2x00dev, 68, 0x0b);
5447
5448         rt2800_bbp_write(rt2x00dev, 69, 0x12);
5449         rt2800_bbp_write(rt2x00dev, 73, 0x13);
5450         rt2800_bbp_write(rt2x00dev, 75, 0x46);
5451         rt2800_bbp_write(rt2x00dev, 76, 0x28);
5452
5453         rt2800_bbp_write(rt2x00dev, 77, 0x59);
5454
5455         rt2800_bbp_write(rt2x00dev, 70, 0x0a);
5456
5457         rt2800_bbp_write(rt2x00dev, 79, 0x13);
5458         rt2800_bbp_write(rt2x00dev, 80, 0x05);
5459         rt2800_bbp_write(rt2x00dev, 81, 0x33);
5460
5461         rt2800_bbp_write(rt2x00dev, 82, 0x62);
5462
5463         rt2800_bbp_write(rt2x00dev, 83, 0x7a);
5464
5465         rt2800_bbp_write(rt2x00dev, 84, 0x9a);
5466
5467         rt2800_bbp_write(rt2x00dev, 86, 0x38);
5468
5469         if (rt2x00_rt(rt2x00dev, RT5392))
5470                 rt2800_bbp_write(rt2x00dev, 88, 0x90);
5471
5472         rt2800_bbp_write(rt2x00dev, 91, 0x04);
5473
5474         rt2800_bbp_write(rt2x00dev, 92, 0x02);
5475
5476         if (rt2x00_rt(rt2x00dev, RT5392)) {
5477                 rt2800_bbp_write(rt2x00dev, 95, 0x9a);
5478                 rt2800_bbp_write(rt2x00dev, 98, 0x12);
5479         }
5480
5481         rt2800_bbp_write(rt2x00dev, 103, 0xc0);
5482
5483         rt2800_bbp_write(rt2x00dev, 104, 0x92);
5484
5485         rt2800_bbp_write(rt2x00dev, 105, 0x3c);
5486
5487         if (rt2x00_rt(rt2x00dev, RT5390))
5488                 rt2800_bbp_write(rt2x00dev, 106, 0x03);
5489         else if (rt2x00_rt(rt2x00dev, RT5392))
5490                 rt2800_bbp_write(rt2x00dev, 106, 0x12);
5491         else
5492                 WARN_ON(1);
5493
5494         rt2800_bbp_write(rt2x00dev, 128, 0x12);
5495
5496         if (rt2x00_rt(rt2x00dev, RT5392)) {
5497                 rt2800_bbp_write(rt2x00dev, 134, 0xd0);
5498                 rt2800_bbp_write(rt2x00dev, 135, 0xf6);
5499         }
5500
5501         rt2800_disable_unused_dac_adc(rt2x00dev);
5502
5503         rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
5504         div_mode = rt2x00_get_field16(eeprom,
5505                                       EEPROM_NIC_CONF1_ANT_DIVERSITY);
5506         ant = (div_mode == 3) ? 1 : 0;
5507
5508         /* check if this is a Bluetooth combo card */
5509         if (test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags)) {
5510                 u32 reg;
5511
5512                 rt2800_register_read(rt2x00dev, GPIO_CTRL, &reg);
5513                 rt2x00_set_field32(&reg, GPIO_CTRL_DIR3, 0);
5514                 rt2x00_set_field32(&reg, GPIO_CTRL_DIR6, 0);
5515                 rt2x00_set_field32(&reg, GPIO_CTRL_VAL3, 0);
5516                 rt2x00_set_field32(&reg, GPIO_CTRL_VAL6, 0);
5517                 if (ant == 0)
5518                         rt2x00_set_field32(&reg, GPIO_CTRL_VAL3, 1);
5519                 else if (ant == 1)
5520                         rt2x00_set_field32(&reg, GPIO_CTRL_VAL6, 1);
5521                 rt2800_register_write(rt2x00dev, GPIO_CTRL, reg);
5522         }
5523
5524         /* This chip has hardware antenna diversity*/
5525         if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390R)) {
5526                 rt2800_bbp_write(rt2x00dev, 150, 0); /* Disable Antenna Software OFDM */
5527                 rt2800_bbp_write(rt2x00dev, 151, 0); /* Disable Antenna Software CCK */
5528                 rt2800_bbp_write(rt2x00dev, 154, 0); /* Clear previously selected antenna */
5529         }
5530
5531         rt2800_bbp_read(rt2x00dev, 152, &value);
5532         if (ant == 0)
5533                 rt2x00_set_field8(&value, BBP152_RX_DEFAULT_ANT, 1);
5534         else
5535                 rt2x00_set_field8(&value, BBP152_RX_DEFAULT_ANT, 0);
5536         rt2800_bbp_write(rt2x00dev, 152, value);
5537
5538         rt2800_init_freq_calibration(rt2x00dev);
5539 }
5540
5541 static void rt2800_init_bbp_5592(struct rt2x00_dev *rt2x00dev)
5542 {
5543         int ant, div_mode;
5544         u16 eeprom;
5545         u8 value;
5546
5547         rt2800_init_bbp_early(rt2x00dev);
5548
5549         rt2800_bbp_read(rt2x00dev, 105, &value);
5550         rt2x00_set_field8(&value, BBP105_MLD,
5551                           rt2x00dev->default_ant.rx_chain_num == 2);
5552         rt2800_bbp_write(rt2x00dev, 105, value);
5553
5554         rt2800_bbp4_mac_if_ctrl(rt2x00dev);
5555
5556         rt2800_bbp_write(rt2x00dev, 20, 0x06);
5557         rt2800_bbp_write(rt2x00dev, 31, 0x08);
5558         rt2800_bbp_write(rt2x00dev, 65, 0x2C);
5559         rt2800_bbp_write(rt2x00dev, 68, 0xDD);
5560         rt2800_bbp_write(rt2x00dev, 69, 0x1A);
5561         rt2800_bbp_write(rt2x00dev, 70, 0x05);
5562         rt2800_bbp_write(rt2x00dev, 73, 0x13);
5563         rt2800_bbp_write(rt2x00dev, 74, 0x0F);
5564         rt2800_bbp_write(rt2x00dev, 75, 0x4F);
5565         rt2800_bbp_write(rt2x00dev, 76, 0x28);
5566         rt2800_bbp_write(rt2x00dev, 77, 0x59);
5567         rt2800_bbp_write(rt2x00dev, 84, 0x9A);
5568         rt2800_bbp_write(rt2x00dev, 86, 0x38);
5569         rt2800_bbp_write(rt2x00dev, 88, 0x90);
5570         rt2800_bbp_write(rt2x00dev, 91, 0x04);
5571         rt2800_bbp_write(rt2x00dev, 92, 0x02);
5572         rt2800_bbp_write(rt2x00dev, 95, 0x9a);
5573         rt2800_bbp_write(rt2x00dev, 98, 0x12);
5574         rt2800_bbp_write(rt2x00dev, 103, 0xC0);
5575         rt2800_bbp_write(rt2x00dev, 104, 0x92);
5576         /* FIXME BBP105 owerwrite */
5577         rt2800_bbp_write(rt2x00dev, 105, 0x3C);
5578         rt2800_bbp_write(rt2x00dev, 106, 0x35);
5579         rt2800_bbp_write(rt2x00dev, 128, 0x12);
5580         rt2800_bbp_write(rt2x00dev, 134, 0xD0);
5581         rt2800_bbp_write(rt2x00dev, 135, 0xF6);
5582         rt2800_bbp_write(rt2x00dev, 137, 0x0F);
5583
5584         /* Initialize GLRT (Generalized Likehood Radio Test) */
5585         rt2800_init_bbp_5592_glrt(rt2x00dev);
5586
5587         rt2800_bbp4_mac_if_ctrl(rt2x00dev);
5588
5589         rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
5590         div_mode = rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_ANT_DIVERSITY);
5591         ant = (div_mode == 3) ? 1 : 0;
5592         rt2800_bbp_read(rt2x00dev, 152, &value);
5593         if (ant == 0) {
5594                 /* Main antenna */
5595                 rt2x00_set_field8(&value, BBP152_RX_DEFAULT_ANT, 1);
5596         } else {
5597                 /* Auxiliary antenna */
5598                 rt2x00_set_field8(&value, BBP152_RX_DEFAULT_ANT, 0);
5599         }
5600         rt2800_bbp_write(rt2x00dev, 152, value);
5601
5602         if (rt2x00_rt_rev_gte(rt2x00dev, RT5592, REV_RT5592C)) {
5603                 rt2800_bbp_read(rt2x00dev, 254, &value);
5604                 rt2x00_set_field8(&value, BBP254_BIT7, 1);
5605                 rt2800_bbp_write(rt2x00dev, 254, value);
5606         }
5607
5608         rt2800_init_freq_calibration(rt2x00dev);
5609
5610         rt2800_bbp_write(rt2x00dev, 84, 0x19);
5611         if (rt2x00_rt_rev_gte(rt2x00dev, RT5592, REV_RT5592C))
5612                 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
5613 }
5614
5615 static void rt2800_init_bbp(struct rt2x00_dev *rt2x00dev)
5616 {
5617         unsigned int i;
5618         u16 eeprom;
5619         u8 reg_id;
5620         u8 value;
5621
5622         if (rt2800_is_305x_soc(rt2x00dev))
5623                 rt2800_init_bbp_305x_soc(rt2x00dev);
5624
5625         switch (rt2x00dev->chip.rt) {
5626         case RT2860:
5627         case RT2872:
5628         case RT2883:
5629                 rt2800_init_bbp_28xx(rt2x00dev);
5630                 break;
5631         case RT3070:
5632         case RT3071:
5633         case RT3090:
5634                 rt2800_init_bbp_30xx(rt2x00dev);
5635                 break;
5636         case RT3290:
5637                 rt2800_init_bbp_3290(rt2x00dev);
5638                 break;
5639         case RT3352:
5640                 rt2800_init_bbp_3352(rt2x00dev);
5641                 break;
5642         case RT3390:
5643                 rt2800_init_bbp_3390(rt2x00dev);
5644                 break;
5645         case RT3572:
5646                 rt2800_init_bbp_3572(rt2x00dev);
5647                 break;
5648         case RT3593:
5649                 rt2800_init_bbp_3593(rt2x00dev);
5650                 return;
5651         case RT5390:
5652         case RT5392:
5653                 rt2800_init_bbp_53xx(rt2x00dev);
5654                 break;
5655         case RT5592:
5656                 rt2800_init_bbp_5592(rt2x00dev);
5657                 return;
5658         }
5659
5660         for (i = 0; i < EEPROM_BBP_SIZE; i++) {
5661                 rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_BBP_START, i,
5662                                               &eeprom);
5663
5664                 if (eeprom != 0xffff && eeprom != 0x0000) {
5665                         reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
5666                         value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
5667                         rt2800_bbp_write(rt2x00dev, reg_id, value);
5668                 }
5669         }
5670 }
5671
5672 static void rt2800_led_open_drain_enable(struct rt2x00_dev *rt2x00dev)
5673 {
5674         u32 reg;
5675
5676         rt2800_register_read(rt2x00dev, OPT_14_CSR, &reg);
5677         rt2x00_set_field32(&reg, OPT_14_CSR_BIT0, 1);
5678         rt2800_register_write(rt2x00dev, OPT_14_CSR, reg);
5679 }
5680
5681 static u8 rt2800_init_rx_filter(struct rt2x00_dev *rt2x00dev, bool bw40,
5682                                 u8 filter_target)
5683 {
5684         unsigned int i;
5685         u8 bbp;
5686         u8 rfcsr;
5687         u8 passband;
5688         u8 stopband;
5689         u8 overtuned = 0;
5690         u8 rfcsr24 = (bw40) ? 0x27 : 0x07;
5691
5692         rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
5693
5694         rt2800_bbp_read(rt2x00dev, 4, &bbp);
5695         rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * bw40);
5696         rt2800_bbp_write(rt2x00dev, 4, bbp);
5697
5698         rt2800_rfcsr_read(rt2x00dev, 31, &rfcsr);
5699         rt2x00_set_field8(&rfcsr, RFCSR31_RX_H20M, bw40);
5700         rt2800_rfcsr_write(rt2x00dev, 31, rfcsr);
5701
5702         rt2800_rfcsr_read(rt2x00dev, 22, &rfcsr);
5703         rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 1);
5704         rt2800_rfcsr_write(rt2x00dev, 22, rfcsr);
5705
5706         /*
5707          * Set power & frequency of passband test tone
5708          */
5709         rt2800_bbp_write(rt2x00dev, 24, 0);
5710
5711         for (i = 0; i < 100; i++) {
5712                 rt2800_bbp_write(rt2x00dev, 25, 0x90);
5713                 msleep(1);
5714
5715                 rt2800_bbp_read(rt2x00dev, 55, &passband);
5716                 if (passband)
5717                         break;
5718         }
5719
5720         /*
5721          * Set power & frequency of stopband test tone
5722          */
5723         rt2800_bbp_write(rt2x00dev, 24, 0x06);
5724
5725         for (i = 0; i < 100; i++) {
5726                 rt2800_bbp_write(rt2x00dev, 25, 0x90);
5727                 msleep(1);
5728
5729                 rt2800_bbp_read(rt2x00dev, 55, &stopband);
5730
5731                 if ((passband - stopband) <= filter_target) {
5732                         rfcsr24++;
5733                         overtuned += ((passband - stopband) == filter_target);
5734                 } else
5735                         break;
5736
5737                 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
5738         }
5739
5740         rfcsr24 -= !!overtuned;
5741
5742         rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
5743         return rfcsr24;
5744 }
5745
5746 static void rt2800_rf_init_calibration(struct rt2x00_dev *rt2x00dev,
5747                                        const unsigned int rf_reg)
5748 {
5749         u8 rfcsr;
5750
5751         rt2800_rfcsr_read(rt2x00dev, rf_reg, &rfcsr);
5752         rt2x00_set_field8(&rfcsr, FIELD8(0x80), 1);
5753         rt2800_rfcsr_write(rt2x00dev, rf_reg, rfcsr);
5754         msleep(1);
5755         rt2x00_set_field8(&rfcsr, FIELD8(0x80), 0);
5756         rt2800_rfcsr_write(rt2x00dev, rf_reg, rfcsr);
5757 }
5758
5759 static void rt2800_rx_filter_calibration(struct rt2x00_dev *rt2x00dev)
5760 {
5761         struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
5762         u8 filter_tgt_bw20;
5763         u8 filter_tgt_bw40;
5764         u8 rfcsr, bbp;
5765
5766         /*
5767          * TODO: sync filter_tgt values with vendor driver
5768          */
5769         if (rt2x00_rt(rt2x00dev, RT3070)) {
5770                 filter_tgt_bw20 = 0x16;
5771                 filter_tgt_bw40 = 0x19;
5772         } else {
5773                 filter_tgt_bw20 = 0x13;
5774                 filter_tgt_bw40 = 0x15;
5775         }
5776
5777         drv_data->calibration_bw20 =
5778                 rt2800_init_rx_filter(rt2x00dev, false, filter_tgt_bw20);
5779         drv_data->calibration_bw40 =
5780                 rt2800_init_rx_filter(rt2x00dev, true, filter_tgt_bw40);
5781
5782         /*
5783          * Save BBP 25 & 26 values for later use in channel switching (for 3052)
5784          */
5785         rt2800_bbp_read(rt2x00dev, 25, &drv_data->bbp25);
5786         rt2800_bbp_read(rt2x00dev, 26, &drv_data->bbp26);
5787
5788         /*
5789          * Set back to initial state
5790          */
5791         rt2800_bbp_write(rt2x00dev, 24, 0);
5792
5793         rt2800_rfcsr_read(rt2x00dev, 22, &rfcsr);
5794         rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 0);
5795         rt2800_rfcsr_write(rt2x00dev, 22, rfcsr);
5796
5797         /*
5798          * Set BBP back to BW20
5799          */
5800         rt2800_bbp_read(rt2x00dev, 4, &bbp);
5801         rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 0);
5802         rt2800_bbp_write(rt2x00dev, 4, bbp);
5803 }
5804
5805 static void rt2800_normal_mode_setup_3xxx(struct rt2x00_dev *rt2x00dev)
5806 {
5807         struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
5808         u8 min_gain, rfcsr, bbp;
5809         u16 eeprom;
5810
5811         rt2800_rfcsr_read(rt2x00dev, 17, &rfcsr);
5812
5813         rt2x00_set_field8(&rfcsr, RFCSR17_TX_LO1_EN, 0);
5814         if (rt2x00_rt(rt2x00dev, RT3070) ||
5815             rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
5816             rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) ||
5817             rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E)) {
5818                 if (!test_bit(CAPABILITY_EXTERNAL_LNA_BG, &rt2x00dev->cap_flags))
5819                         rt2x00_set_field8(&rfcsr, RFCSR17_R, 1);
5820         }
5821
5822         min_gain = rt2x00_rt(rt2x00dev, RT3070) ? 1 : 2;
5823         if (drv_data->txmixer_gain_24g >= min_gain) {
5824                 rt2x00_set_field8(&rfcsr, RFCSR17_TXMIXER_GAIN,
5825                                   drv_data->txmixer_gain_24g);
5826         }
5827
5828         rt2800_rfcsr_write(rt2x00dev, 17, rfcsr);
5829
5830         if (rt2x00_rt(rt2x00dev, RT3090)) {
5831                 /*  Turn off unused DAC1 and ADC1 to reduce power consumption */
5832                 rt2800_bbp_read(rt2x00dev, 138, &bbp);
5833                 rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom);
5834                 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) == 1)
5835                         rt2x00_set_field8(&bbp, BBP138_RX_ADC1, 0);
5836                 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) == 1)
5837                         rt2x00_set_field8(&bbp, BBP138_TX_DAC1, 1);
5838                 rt2800_bbp_write(rt2x00dev, 138, bbp);
5839         }
5840
5841         if (rt2x00_rt(rt2x00dev, RT3070)) {
5842                 rt2800_rfcsr_read(rt2x00dev, 27, &rfcsr);
5843                 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F))
5844                         rt2x00_set_field8(&rfcsr, RFCSR27_R1, 3);
5845                 else
5846                         rt2x00_set_field8(&rfcsr, RFCSR27_R1, 0);
5847                 rt2x00_set_field8(&rfcsr, RFCSR27_R2, 0);
5848                 rt2x00_set_field8(&rfcsr, RFCSR27_R3, 0);
5849                 rt2x00_set_field8(&rfcsr, RFCSR27_R4, 0);
5850                 rt2800_rfcsr_write(rt2x00dev, 27, rfcsr);
5851         } else if (rt2x00_rt(rt2x00dev, RT3071) ||
5852                    rt2x00_rt(rt2x00dev, RT3090) ||
5853                    rt2x00_rt(rt2x00dev, RT3390)) {
5854                 rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
5855                 rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
5856                 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0);
5857                 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0);
5858                 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
5859                 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
5860                 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
5861
5862                 rt2800_rfcsr_read(rt2x00dev, 15, &rfcsr);
5863                 rt2x00_set_field8(&rfcsr, RFCSR15_TX_LO2_EN, 0);
5864                 rt2800_rfcsr_write(rt2x00dev, 15, rfcsr);
5865
5866                 rt2800_rfcsr_read(rt2x00dev, 20, &rfcsr);
5867                 rt2x00_set_field8(&rfcsr, RFCSR20_RX_LO1_EN, 0);
5868                 rt2800_rfcsr_write(rt2x00dev, 20, rfcsr);
5869
5870                 rt2800_rfcsr_read(rt2x00dev, 21, &rfcsr);
5871                 rt2x00_set_field8(&rfcsr, RFCSR21_RX_LO2_EN, 0);
5872                 rt2800_rfcsr_write(rt2x00dev, 21, rfcsr);
5873         }
5874 }
5875
5876 static void rt2800_normal_mode_setup_3593(struct rt2x00_dev *rt2x00dev)
5877 {
5878         struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
5879         u8 rfcsr;
5880         u8 tx_gain;
5881
5882         rt2800_rfcsr_read(rt2x00dev, 50, &rfcsr);
5883         rt2x00_set_field8(&rfcsr, RFCSR50_TX_LO2_EN, 0);
5884         rt2800_rfcsr_write(rt2x00dev, 50, rfcsr);
5885
5886         rt2800_rfcsr_read(rt2x00dev, 51, &rfcsr);
5887         tx_gain = rt2x00_get_field8(drv_data->txmixer_gain_24g,
5888                                     RFCSR17_TXMIXER_GAIN);
5889         rt2x00_set_field8(&rfcsr, RFCSR51_BITS24, tx_gain);
5890         rt2800_rfcsr_write(rt2x00dev, 51, rfcsr);
5891
5892         rt2800_rfcsr_read(rt2x00dev, 38, &rfcsr);
5893         rt2x00_set_field8(&rfcsr, RFCSR38_RX_LO1_EN, 0);
5894         rt2800_rfcsr_write(rt2x00dev, 38, rfcsr);
5895
5896         rt2800_rfcsr_read(rt2x00dev, 39, &rfcsr);
5897         rt2x00_set_field8(&rfcsr, RFCSR39_RX_LO2_EN, 0);
5898         rt2800_rfcsr_write(rt2x00dev, 39, rfcsr);
5899
5900         rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
5901         rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
5902         rt2x00_set_field8(&rfcsr, RFCSR1_PLL_PD, 1);
5903         rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
5904
5905         rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
5906         rt2x00_set_field8(&rfcsr, RFCSR30_RX_VCM, 2);
5907         rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
5908
5909         /* TODO: enable stream mode */
5910 }
5911
5912 static void rt2800_normal_mode_setup_5xxx(struct rt2x00_dev *rt2x00dev)
5913 {
5914         u8 reg;
5915         u16 eeprom;
5916
5917         /*  Turn off unused DAC1 and ADC1 to reduce power consumption */
5918         rt2800_bbp_read(rt2x00dev, 138, &reg);
5919         rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom);
5920         if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) == 1)
5921                 rt2x00_set_field8(&reg, BBP138_RX_ADC1, 0);
5922         if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) == 1)
5923                 rt2x00_set_field8(&reg, BBP138_TX_DAC1, 1);
5924         rt2800_bbp_write(rt2x00dev, 138, reg);
5925
5926         rt2800_rfcsr_read(rt2x00dev, 38, &reg);
5927         rt2x00_set_field8(&reg, RFCSR38_RX_LO1_EN, 0);
5928         rt2800_rfcsr_write(rt2x00dev, 38, reg);
5929
5930         rt2800_rfcsr_read(rt2x00dev, 39, &reg);
5931         rt2x00_set_field8(&reg, RFCSR39_RX_LO2_EN, 0);
5932         rt2800_rfcsr_write(rt2x00dev, 39, reg);
5933
5934         rt2800_bbp4_mac_if_ctrl(rt2x00dev);
5935
5936         rt2800_rfcsr_read(rt2x00dev, 30, &reg);
5937         rt2x00_set_field8(&reg, RFCSR30_RX_VCM, 2);
5938         rt2800_rfcsr_write(rt2x00dev, 30, reg);
5939 }
5940
5941 static void rt2800_init_rfcsr_305x_soc(struct rt2x00_dev *rt2x00dev)
5942 {
5943         rt2800_rf_init_calibration(rt2x00dev, 30);
5944
5945         rt2800_rfcsr_write(rt2x00dev, 0, 0x50);
5946         rt2800_rfcsr_write(rt2x00dev, 1, 0x01);
5947         rt2800_rfcsr_write(rt2x00dev, 2, 0xf7);
5948         rt2800_rfcsr_write(rt2x00dev, 3, 0x75);
5949         rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
5950         rt2800_rfcsr_write(rt2x00dev, 5, 0x03);
5951         rt2800_rfcsr_write(rt2x00dev, 6, 0x02);
5952         rt2800_rfcsr_write(rt2x00dev, 7, 0x50);
5953         rt2800_rfcsr_write(rt2x00dev, 8, 0x39);
5954         rt2800_rfcsr_write(rt2x00dev, 9, 0x0f);
5955         rt2800_rfcsr_write(rt2x00dev, 10, 0x60);
5956         rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
5957         rt2800_rfcsr_write(rt2x00dev, 12, 0x75);
5958         rt2800_rfcsr_write(rt2x00dev, 13, 0x75);
5959         rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
5960         rt2800_rfcsr_write(rt2x00dev, 15, 0x58);
5961         rt2800_rfcsr_write(rt2x00dev, 16, 0xb3);
5962         rt2800_rfcsr_write(rt2x00dev, 17, 0x92);
5963         rt2800_rfcsr_write(rt2x00dev, 18, 0x2c);
5964         rt2800_rfcsr_write(rt2x00dev, 19, 0x02);
5965         rt2800_rfcsr_write(rt2x00dev, 20, 0xba);
5966         rt2800_rfcsr_write(rt2x00dev, 21, 0xdb);
5967         rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
5968         rt2800_rfcsr_write(rt2x00dev, 23, 0x31);
5969         rt2800_rfcsr_write(rt2x00dev, 24, 0x08);
5970         rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
5971         rt2800_rfcsr_write(rt2x00dev, 26, 0x25);
5972         rt2800_rfcsr_write(rt2x00dev, 27, 0x23);
5973         rt2800_rfcsr_write(rt2x00dev, 28, 0x13);
5974         rt2800_rfcsr_write(rt2x00dev, 29, 0x83);
5975         rt2800_rfcsr_write(rt2x00dev, 30, 0x00);
5976         rt2800_rfcsr_write(rt2x00dev, 31, 0x00);
5977 }
5978
5979 static void rt2800_init_rfcsr_30xx(struct rt2x00_dev *rt2x00dev)
5980 {
5981         u8 rfcsr;
5982         u16 eeprom;
5983         u32 reg;
5984
5985         /* XXX vendor driver do this only for 3070 */
5986         rt2800_rf_init_calibration(rt2x00dev, 30);
5987
5988         rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
5989         rt2800_rfcsr_write(rt2x00dev, 5, 0x03);
5990         rt2800_rfcsr_write(rt2x00dev, 6, 0x02);
5991         rt2800_rfcsr_write(rt2x00dev, 7, 0x60);
5992         rt2800_rfcsr_write(rt2x00dev, 9, 0x0f);
5993         rt2800_rfcsr_write(rt2x00dev, 10, 0x41);
5994         rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
5995         rt2800_rfcsr_write(rt2x00dev, 12, 0x7b);
5996         rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
5997         rt2800_rfcsr_write(rt2x00dev, 15, 0x58);
5998         rt2800_rfcsr_write(rt2x00dev, 16, 0xb3);
5999         rt2800_rfcsr_write(rt2x00dev, 17, 0x92);
6000         rt2800_rfcsr_write(rt2x00dev, 18, 0x2c);
6001         rt2800_rfcsr_write(rt2x00dev, 19, 0x02);
6002         rt2800_rfcsr_write(rt2x00dev, 20, 0xba);
6003         rt2800_rfcsr_write(rt2x00dev, 21, 0xdb);
6004         rt2800_rfcsr_write(rt2x00dev, 24, 0x16);
6005         rt2800_rfcsr_write(rt2x00dev, 25, 0x03);
6006         rt2800_rfcsr_write(rt2x00dev, 29, 0x1f);
6007
6008         if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F)) {
6009                 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
6010                 rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
6011                 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 3);
6012                 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
6013         } else if (rt2x00_rt(rt2x00dev, RT3071) ||
6014                    rt2x00_rt(rt2x00dev, RT3090)) {
6015                 rt2800_rfcsr_write(rt2x00dev, 31, 0x14);
6016
6017                 rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
6018                 rt2x00_set_field8(&rfcsr, RFCSR6_R2, 1);
6019                 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
6020
6021                 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
6022                 rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
6023                 if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
6024                     rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E)) {
6025                         rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1,
6026                                            &eeprom);
6027                         if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_DAC_TEST))
6028                                 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 3);
6029                         else
6030                                 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 0);
6031                 }
6032                 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
6033
6034                 rt2800_register_read(rt2x00dev, GPIO_SWITCH, &reg);
6035                 rt2x00_set_field32(&reg, GPIO_SWITCH_5, 0);
6036                 rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg);
6037         }
6038
6039         rt2800_rx_filter_calibration(rt2x00dev);
6040
6041         if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F) ||
6042             rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
6043             rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E))
6044                 rt2800_rfcsr_write(rt2x00dev, 27, 0x03);
6045
6046         rt2800_led_open_drain_enable(rt2x00dev);
6047         rt2800_normal_mode_setup_3xxx(rt2x00dev);
6048 }
6049
6050 static void rt2800_init_rfcsr_3290(struct rt2x00_dev *rt2x00dev)
6051 {
6052         u8 rfcsr;
6053
6054         rt2800_rf_init_calibration(rt2x00dev, 2);
6055
6056         rt2800_rfcsr_write(rt2x00dev, 1, 0x0f);
6057         rt2800_rfcsr_write(rt2x00dev, 2, 0x80);
6058         rt2800_rfcsr_write(rt2x00dev, 3, 0x08);
6059         rt2800_rfcsr_write(rt2x00dev, 4, 0x00);
6060         rt2800_rfcsr_write(rt2x00dev, 6, 0xa0);
6061         rt2800_rfcsr_write(rt2x00dev, 8, 0xf3);
6062         rt2800_rfcsr_write(rt2x00dev, 9, 0x02);
6063         rt2800_rfcsr_write(rt2x00dev, 10, 0x53);
6064         rt2800_rfcsr_write(rt2x00dev, 11, 0x4a);
6065         rt2800_rfcsr_write(rt2x00dev, 12, 0x46);
6066         rt2800_rfcsr_write(rt2x00dev, 13, 0x9f);
6067         rt2800_rfcsr_write(rt2x00dev, 18, 0x02);
6068         rt2800_rfcsr_write(rt2x00dev, 22, 0x20);
6069         rt2800_rfcsr_write(rt2x00dev, 25, 0x83);
6070         rt2800_rfcsr_write(rt2x00dev, 26, 0x82);
6071         rt2800_rfcsr_write(rt2x00dev, 27, 0x09);
6072         rt2800_rfcsr_write(rt2x00dev, 29, 0x10);
6073         rt2800_rfcsr_write(rt2x00dev, 30, 0x10);
6074         rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
6075         rt2800_rfcsr_write(rt2x00dev, 32, 0x80);
6076         rt2800_rfcsr_write(rt2x00dev, 33, 0x00);
6077         rt2800_rfcsr_write(rt2x00dev, 34, 0x05);
6078         rt2800_rfcsr_write(rt2x00dev, 35, 0x12);
6079         rt2800_rfcsr_write(rt2x00dev, 36, 0x00);
6080         rt2800_rfcsr_write(rt2x00dev, 38, 0x85);
6081         rt2800_rfcsr_write(rt2x00dev, 39, 0x1b);
6082         rt2800_rfcsr_write(rt2x00dev, 40, 0x0b);
6083         rt2800_rfcsr_write(rt2x00dev, 41, 0xbb);
6084         rt2800_rfcsr_write(rt2x00dev, 42, 0xd5);
6085         rt2800_rfcsr_write(rt2x00dev, 43, 0x7b);
6086         rt2800_rfcsr_write(rt2x00dev, 44, 0x0e);
6087         rt2800_rfcsr_write(rt2x00dev, 45, 0xa2);
6088         rt2800_rfcsr_write(rt2x00dev, 46, 0x73);
6089         rt2800_rfcsr_write(rt2x00dev, 47, 0x00);
6090         rt2800_rfcsr_write(rt2x00dev, 48, 0x10);
6091         rt2800_rfcsr_write(rt2x00dev, 49, 0x98);
6092         rt2800_rfcsr_write(rt2x00dev, 52, 0x38);
6093         rt2800_rfcsr_write(rt2x00dev, 53, 0x00);
6094         rt2800_rfcsr_write(rt2x00dev, 54, 0x78);
6095         rt2800_rfcsr_write(rt2x00dev, 55, 0x43);
6096         rt2800_rfcsr_write(rt2x00dev, 56, 0x02);
6097         rt2800_rfcsr_write(rt2x00dev, 57, 0x80);
6098         rt2800_rfcsr_write(rt2x00dev, 58, 0x7f);
6099         rt2800_rfcsr_write(rt2x00dev, 59, 0x09);
6100         rt2800_rfcsr_write(rt2x00dev, 60, 0x45);
6101         rt2800_rfcsr_write(rt2x00dev, 61, 0xc1);
6102
6103         rt2800_rfcsr_read(rt2x00dev, 29, &rfcsr);
6104         rt2x00_set_field8(&rfcsr, RFCSR29_RSSI_GAIN, 3);
6105         rt2800_rfcsr_write(rt2x00dev, 29, rfcsr);
6106
6107         rt2800_led_open_drain_enable(rt2x00dev);
6108         rt2800_normal_mode_setup_3xxx(rt2x00dev);
6109 }
6110
6111 static void rt2800_init_rfcsr_3352(struct rt2x00_dev *rt2x00dev)
6112 {
6113         rt2800_rf_init_calibration(rt2x00dev, 30);
6114
6115         rt2800_rfcsr_write(rt2x00dev, 0, 0xf0);
6116         rt2800_rfcsr_write(rt2x00dev, 1, 0x23);
6117         rt2800_rfcsr_write(rt2x00dev, 2, 0x50);
6118         rt2800_rfcsr_write(rt2x00dev, 3, 0x18);
6119         rt2800_rfcsr_write(rt2x00dev, 4, 0x00);
6120         rt2800_rfcsr_write(rt2x00dev, 5, 0x00);
6121         rt2800_rfcsr_write(rt2x00dev, 6, 0x33);
6122         rt2800_rfcsr_write(rt2x00dev, 7, 0x00);
6123         rt2800_rfcsr_write(rt2x00dev, 8, 0xf1);
6124         rt2800_rfcsr_write(rt2x00dev, 9, 0x02);
6125         rt2800_rfcsr_write(rt2x00dev, 10, 0xd2);
6126         rt2800_rfcsr_write(rt2x00dev, 11, 0x42);
6127         rt2800_rfcsr_write(rt2x00dev, 12, 0x1c);
6128         rt2800_rfcsr_write(rt2x00dev, 13, 0x00);
6129         rt2800_rfcsr_write(rt2x00dev, 14, 0x5a);
6130         rt2800_rfcsr_write(rt2x00dev, 15, 0x00);
6131         rt2800_rfcsr_write(rt2x00dev, 16, 0x01);
6132         rt2800_rfcsr_write(rt2x00dev, 18, 0x45);
6133         rt2800_rfcsr_write(rt2x00dev, 19, 0x02);
6134         rt2800_rfcsr_write(rt2x00dev, 20, 0x00);
6135         rt2800_rfcsr_write(rt2x00dev, 21, 0x00);
6136         rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
6137         rt2800_rfcsr_write(rt2x00dev, 23, 0x00);
6138         rt2800_rfcsr_write(rt2x00dev, 24, 0x00);
6139         rt2800_rfcsr_write(rt2x00dev, 25, 0x80);
6140         rt2800_rfcsr_write(rt2x00dev, 26, 0x00);
6141         rt2800_rfcsr_write(rt2x00dev, 27, 0x03);
6142         rt2800_rfcsr_write(rt2x00dev, 28, 0x03);
6143         rt2800_rfcsr_write(rt2x00dev, 29, 0x00);
6144         rt2800_rfcsr_write(rt2x00dev, 30, 0x10);
6145         rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
6146         rt2800_rfcsr_write(rt2x00dev, 32, 0x80);
6147         rt2800_rfcsr_write(rt2x00dev, 33, 0x00);
6148         rt2800_rfcsr_write(rt2x00dev, 34, 0x01);
6149         rt2800_rfcsr_write(rt2x00dev, 35, 0x03);
6150         rt2800_rfcsr_write(rt2x00dev, 36, 0xbd);
6151         rt2800_rfcsr_write(rt2x00dev, 37, 0x3c);
6152         rt2800_rfcsr_write(rt2x00dev, 38, 0x5f);
6153         rt2800_rfcsr_write(rt2x00dev, 39, 0xc5);
6154         rt2800_rfcsr_write(rt2x00dev, 40, 0x33);
6155         rt2800_rfcsr_write(rt2x00dev, 41, 0x5b);
6156         rt2800_rfcsr_write(rt2x00dev, 42, 0x5b);
6157         rt2800_rfcsr_write(rt2x00dev, 43, 0xdb);
6158         rt2800_rfcsr_write(rt2x00dev, 44, 0xdb);
6159         rt2800_rfcsr_write(rt2x00dev, 45, 0xdb);
6160         rt2800_rfcsr_write(rt2x00dev, 46, 0xdd);
6161         rt2800_rfcsr_write(rt2x00dev, 47, 0x0d);
6162         rt2800_rfcsr_write(rt2x00dev, 48, 0x14);
6163         rt2800_rfcsr_write(rt2x00dev, 49, 0x00);
6164         rt2800_rfcsr_write(rt2x00dev, 50, 0x2d);
6165         rt2800_rfcsr_write(rt2x00dev, 51, 0x7f);
6166         rt2800_rfcsr_write(rt2x00dev, 52, 0x00);
6167         rt2800_rfcsr_write(rt2x00dev, 53, 0x52);
6168         rt2800_rfcsr_write(rt2x00dev, 54, 0x1b);
6169         rt2800_rfcsr_write(rt2x00dev, 55, 0x7f);
6170         rt2800_rfcsr_write(rt2x00dev, 56, 0x00);
6171         rt2800_rfcsr_write(rt2x00dev, 57, 0x52);
6172         rt2800_rfcsr_write(rt2x00dev, 58, 0x1b);
6173         rt2800_rfcsr_write(rt2x00dev, 59, 0x00);
6174         rt2800_rfcsr_write(rt2x00dev, 60, 0x00);
6175         rt2800_rfcsr_write(rt2x00dev, 61, 0x00);
6176         rt2800_rfcsr_write(rt2x00dev, 62, 0x00);
6177         rt2800_rfcsr_write(rt2x00dev, 63, 0x00);
6178
6179         rt2800_rx_filter_calibration(rt2x00dev);
6180         rt2800_led_open_drain_enable(rt2x00dev);
6181         rt2800_normal_mode_setup_3xxx(rt2x00dev);
6182 }
6183
6184 static void rt2800_init_rfcsr_3390(struct rt2x00_dev *rt2x00dev)
6185 {
6186         u32 reg;
6187
6188         rt2800_rf_init_calibration(rt2x00dev, 30);
6189
6190         rt2800_rfcsr_write(rt2x00dev, 0, 0xa0);
6191         rt2800_rfcsr_write(rt2x00dev, 1, 0xe1);
6192         rt2800_rfcsr_write(rt2x00dev, 2, 0xf1);
6193         rt2800_rfcsr_write(rt2x00dev, 3, 0x62);
6194         rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
6195         rt2800_rfcsr_write(rt2x00dev, 5, 0x8b);
6196         rt2800_rfcsr_write(rt2x00dev, 6, 0x42);
6197         rt2800_rfcsr_write(rt2x00dev, 7, 0x34);
6198         rt2800_rfcsr_write(rt2x00dev, 8, 0x00);
6199         rt2800_rfcsr_write(rt2x00dev, 9, 0xc0);
6200         rt2800_rfcsr_write(rt2x00dev, 10, 0x61);
6201         rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
6202         rt2800_rfcsr_write(rt2x00dev, 12, 0x3b);
6203         rt2800_rfcsr_write(rt2x00dev, 13, 0xe0);
6204         rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
6205         rt2800_rfcsr_write(rt2x00dev, 15, 0x53);
6206         rt2800_rfcsr_write(rt2x00dev, 16, 0xe0);
6207         rt2800_rfcsr_write(rt2x00dev, 17, 0x94);
6208         rt2800_rfcsr_write(rt2x00dev, 18, 0x5c);
6209         rt2800_rfcsr_write(rt2x00dev, 19, 0x4a);
6210         rt2800_rfcsr_write(rt2x00dev, 20, 0xb2);
6211         rt2800_rfcsr_write(rt2x00dev, 21, 0xf6);
6212         rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
6213         rt2800_rfcsr_write(rt2x00dev, 23, 0x14);
6214         rt2800_rfcsr_write(rt2x00dev, 24, 0x08);
6215         rt2800_rfcsr_write(rt2x00dev, 25, 0x3d);
6216         rt2800_rfcsr_write(rt2x00dev, 26, 0x85);
6217         rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
6218         rt2800_rfcsr_write(rt2x00dev, 28, 0x41);
6219         rt2800_rfcsr_write(rt2x00dev, 29, 0x8f);
6220         rt2800_rfcsr_write(rt2x00dev, 30, 0x20);
6221         rt2800_rfcsr_write(rt2x00dev, 31, 0x0f);
6222
6223         rt2800_register_read(rt2x00dev, GPIO_SWITCH, &reg);
6224         rt2x00_set_field32(&reg, GPIO_SWITCH_5, 0);
6225         rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg);
6226
6227         rt2800_rx_filter_calibration(rt2x00dev);
6228
6229         if (rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E))
6230                 rt2800_rfcsr_write(rt2x00dev, 27, 0x03);
6231
6232         rt2800_led_open_drain_enable(rt2x00dev);
6233         rt2800_normal_mode_setup_3xxx(rt2x00dev);
6234 }
6235
6236 static void rt2800_init_rfcsr_3572(struct rt2x00_dev *rt2x00dev)
6237 {
6238         u8 rfcsr;
6239         u32 reg;
6240
6241         rt2800_rf_init_calibration(rt2x00dev, 30);
6242
6243         rt2800_rfcsr_write(rt2x00dev, 0, 0x70);
6244         rt2800_rfcsr_write(rt2x00dev, 1, 0x81);
6245         rt2800_rfcsr_write(rt2x00dev, 2, 0xf1);
6246         rt2800_rfcsr_write(rt2x00dev, 3, 0x02);
6247         rt2800_rfcsr_write(rt2x00dev, 4, 0x4c);
6248         rt2800_rfcsr_write(rt2x00dev, 5, 0x05);
6249         rt2800_rfcsr_write(rt2x00dev, 6, 0x4a);
6250         rt2800_rfcsr_write(rt2x00dev, 7, 0xd8);
6251         rt2800_rfcsr_write(rt2x00dev, 9, 0xc3);
6252         rt2800_rfcsr_write(rt2x00dev, 10, 0xf1);
6253         rt2800_rfcsr_write(rt2x00dev, 11, 0xb9);
6254         rt2800_rfcsr_write(rt2x00dev, 12, 0x70);
6255         rt2800_rfcsr_write(rt2x00dev, 13, 0x65);
6256         rt2800_rfcsr_write(rt2x00dev, 14, 0xa0);
6257         rt2800_rfcsr_write(rt2x00dev, 15, 0x53);
6258         rt2800_rfcsr_write(rt2x00dev, 16, 0x4c);
6259         rt2800_rfcsr_write(rt2x00dev, 17, 0x23);
6260         rt2800_rfcsr_write(rt2x00dev, 18, 0xac);
6261         rt2800_rfcsr_write(rt2x00dev, 19, 0x93);
6262         rt2800_rfcsr_write(rt2x00dev, 20, 0xb3);
6263         rt2800_rfcsr_write(rt2x00dev, 21, 0xd0);
6264         rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
6265         rt2800_rfcsr_write(rt2x00dev, 23, 0x3c);
6266         rt2800_rfcsr_write(rt2x00dev, 24, 0x16);
6267         rt2800_rfcsr_write(rt2x00dev, 25, 0x15);
6268         rt2800_rfcsr_write(rt2x00dev, 26, 0x85);
6269         rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
6270         rt2800_rfcsr_write(rt2x00dev, 28, 0x00);
6271         rt2800_rfcsr_write(rt2x00dev, 29, 0x9b);
6272         rt2800_rfcsr_write(rt2x00dev, 30, 0x09);
6273         rt2800_rfcsr_write(rt2x00dev, 31, 0x10);
6274
6275         rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
6276         rt2x00_set_field8(&rfcsr, RFCSR6_R2, 1);
6277         rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
6278
6279         rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
6280         rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 3);
6281         rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
6282         rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
6283         msleep(1);
6284         rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
6285         rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 0);
6286         rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
6287         rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
6288
6289         rt2800_rx_filter_calibration(rt2x00dev);
6290         rt2800_led_open_drain_enable(rt2x00dev);
6291         rt2800_normal_mode_setup_3xxx(rt2x00dev);
6292 }
6293
6294 static void rt3593_post_bbp_init(struct rt2x00_dev *rt2x00dev)
6295 {
6296         u8 bbp;
6297         bool txbf_enabled = false; /* FIXME */
6298
6299         rt2800_bbp_read(rt2x00dev, 105, &bbp);
6300         if (rt2x00dev->default_ant.rx_chain_num == 1)
6301                 rt2x00_set_field8(&bbp, BBP105_MLD, 0);
6302         else
6303                 rt2x00_set_field8(&bbp, BBP105_MLD, 1);
6304         rt2800_bbp_write(rt2x00dev, 105, bbp);
6305
6306         rt2800_bbp4_mac_if_ctrl(rt2x00dev);
6307
6308         rt2800_bbp_write(rt2x00dev, 92, 0x02);
6309         rt2800_bbp_write(rt2x00dev, 82, 0x82);
6310         rt2800_bbp_write(rt2x00dev, 106, 0x05);
6311         rt2800_bbp_write(rt2x00dev, 104, 0x92);
6312         rt2800_bbp_write(rt2x00dev, 88, 0x90);
6313         rt2800_bbp_write(rt2x00dev, 148, 0xc8);
6314         rt2800_bbp_write(rt2x00dev, 47, 0x48);
6315         rt2800_bbp_write(rt2x00dev, 120, 0x50);
6316
6317         if (txbf_enabled)
6318                 rt2800_bbp_write(rt2x00dev, 163, 0xbd);
6319         else
6320                 rt2800_bbp_write(rt2x00dev, 163, 0x9d);
6321
6322         /* SNR mapping */
6323         rt2800_bbp_write(rt2x00dev, 142, 6);
6324         rt2800_bbp_write(rt2x00dev, 143, 160);
6325         rt2800_bbp_write(rt2x00dev, 142, 7);
6326         rt2800_bbp_write(rt2x00dev, 143, 161);
6327         rt2800_bbp_write(rt2x00dev, 142, 8);
6328         rt2800_bbp_write(rt2x00dev, 143, 162);
6329
6330         /* ADC/DAC control */
6331         rt2800_bbp_write(rt2x00dev, 31, 0x08);
6332
6333         /* RX AGC energy lower bound in log2 */
6334         rt2800_bbp_write(rt2x00dev, 68, 0x0b);
6335
6336         /* FIXME: BBP 105 owerwrite? */
6337         rt2800_bbp_write(rt2x00dev, 105, 0x04);
6338
6339 }
6340
6341 static void rt2800_init_rfcsr_3593(struct rt2x00_dev *rt2x00dev)
6342 {
6343         struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
6344         u32 reg;
6345         u8 rfcsr;
6346
6347         /* Disable GPIO #4 and #7 function for LAN PE control */
6348         rt2800_register_read(rt2x00dev, GPIO_SWITCH, &reg);
6349         rt2x00_set_field32(&reg, GPIO_SWITCH_4, 0);
6350         rt2x00_set_field32(&reg, GPIO_SWITCH_7, 0);
6351         rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg);
6352
6353         /* Initialize default register values */
6354         rt2800_rfcsr_write(rt2x00dev, 1, 0x03);
6355         rt2800_rfcsr_write(rt2x00dev, 3, 0x80);
6356         rt2800_rfcsr_write(rt2x00dev, 5, 0x00);
6357         rt2800_rfcsr_write(rt2x00dev, 6, 0x40);
6358         rt2800_rfcsr_write(rt2x00dev, 8, 0xf1);
6359         rt2800_rfcsr_write(rt2x00dev, 9, 0x02);
6360         rt2800_rfcsr_write(rt2x00dev, 10, 0xd3);
6361         rt2800_rfcsr_write(rt2x00dev, 11, 0x40);
6362         rt2800_rfcsr_write(rt2x00dev, 12, 0x4e);
6363         rt2800_rfcsr_write(rt2x00dev, 13, 0x12);
6364         rt2800_rfcsr_write(rt2x00dev, 18, 0x40);
6365         rt2800_rfcsr_write(rt2x00dev, 22, 0x20);
6366         rt2800_rfcsr_write(rt2x00dev, 30, 0x10);
6367         rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
6368         rt2800_rfcsr_write(rt2x00dev, 32, 0x78);
6369         rt2800_rfcsr_write(rt2x00dev, 33, 0x3b);
6370         rt2800_rfcsr_write(rt2x00dev, 34, 0x3c);
6371         rt2800_rfcsr_write(rt2x00dev, 35, 0xe0);
6372         rt2800_rfcsr_write(rt2x00dev, 38, 0x86);
6373         rt2800_rfcsr_write(rt2x00dev, 39, 0x23);
6374         rt2800_rfcsr_write(rt2x00dev, 44, 0xd3);
6375         rt2800_rfcsr_write(rt2x00dev, 45, 0xbb);
6376         rt2800_rfcsr_write(rt2x00dev, 46, 0x60);
6377         rt2800_rfcsr_write(rt2x00dev, 49, 0x8e);
6378         rt2800_rfcsr_write(rt2x00dev, 50, 0x86);
6379         rt2800_rfcsr_write(rt2x00dev, 51, 0x75);
6380         rt2800_rfcsr_write(rt2x00dev, 52, 0x45);
6381         rt2800_rfcsr_write(rt2x00dev, 53, 0x18);
6382         rt2800_rfcsr_write(rt2x00dev, 54, 0x18);
6383         rt2800_rfcsr_write(rt2x00dev, 55, 0x18);
6384         rt2800_rfcsr_write(rt2x00dev, 56, 0xdb);
6385         rt2800_rfcsr_write(rt2x00dev, 57, 0x6e);
6386
6387         /* Initiate calibration */
6388         /* TODO: use rt2800_rf_init_calibration ? */
6389         rt2800_rfcsr_read(rt2x00dev, 2, &rfcsr);
6390         rt2x00_set_field8(&rfcsr, RFCSR2_RESCAL_EN, 1);
6391         rt2800_rfcsr_write(rt2x00dev, 2, rfcsr);
6392
6393         rt2800_adjust_freq_offset(rt2x00dev);
6394
6395         rt2800_rfcsr_read(rt2x00dev, 18, &rfcsr);
6396         rt2x00_set_field8(&rfcsr, RFCSR18_XO_TUNE_BYPASS, 1);
6397         rt2800_rfcsr_write(rt2x00dev, 18, rfcsr);
6398
6399         rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
6400         rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 3);
6401         rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
6402         rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
6403         usleep_range(1000, 1500);
6404         rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
6405         rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 0);
6406         rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
6407
6408         /* Set initial values for RX filter calibration */
6409         drv_data->calibration_bw20 = 0x1f;
6410         drv_data->calibration_bw40 = 0x2f;
6411
6412         /* Save BBP 25 & 26 values for later use in channel switching */
6413         rt2800_bbp_read(rt2x00dev, 25, &drv_data->bbp25);
6414         rt2800_bbp_read(rt2x00dev, 26, &drv_data->bbp26);
6415
6416         rt2800_led_open_drain_enable(rt2x00dev);
6417         rt2800_normal_mode_setup_3593(rt2x00dev);
6418
6419         rt3593_post_bbp_init(rt2x00dev);
6420
6421         /* TODO: enable stream mode support */
6422 }
6423
6424 static void rt2800_init_rfcsr_5390(struct rt2x00_dev *rt2x00dev)
6425 {
6426         rt2800_rf_init_calibration(rt2x00dev, 2);
6427
6428         rt2800_rfcsr_write(rt2x00dev, 1, 0x0f);
6429         rt2800_rfcsr_write(rt2x00dev, 2, 0x80);
6430         rt2800_rfcsr_write(rt2x00dev, 3, 0x88);
6431         rt2800_rfcsr_write(rt2x00dev, 5, 0x10);
6432         if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
6433                 rt2800_rfcsr_write(rt2x00dev, 6, 0xe0);
6434         else
6435                 rt2800_rfcsr_write(rt2x00dev, 6, 0xa0);
6436         rt2800_rfcsr_write(rt2x00dev, 7, 0x00);
6437         rt2800_rfcsr_write(rt2x00dev, 10, 0x53);
6438         rt2800_rfcsr_write(rt2x00dev, 11, 0x4a);
6439         rt2800_rfcsr_write(rt2x00dev, 12, 0xc6);
6440         rt2800_rfcsr_write(rt2x00dev, 13, 0x9f);
6441         rt2800_rfcsr_write(rt2x00dev, 14, 0x00);
6442         rt2800_rfcsr_write(rt2x00dev, 15, 0x00);
6443         rt2800_rfcsr_write(rt2x00dev, 16, 0x00);
6444         rt2800_rfcsr_write(rt2x00dev, 18, 0x03);
6445         rt2800_rfcsr_write(rt2x00dev, 19, 0x00);
6446
6447         rt2800_rfcsr_write(rt2x00dev, 20, 0x00);
6448         rt2800_rfcsr_write(rt2x00dev, 21, 0x00);
6449         rt2800_rfcsr_write(rt2x00dev, 22, 0x20);
6450         rt2800_rfcsr_write(rt2x00dev, 23, 0x00);
6451         rt2800_rfcsr_write(rt2x00dev, 24, 0x00);
6452         if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
6453                 rt2800_rfcsr_write(rt2x00dev, 25, 0x80);
6454         else
6455                 rt2800_rfcsr_write(rt2x00dev, 25, 0xc0);
6456         rt2800_rfcsr_write(rt2x00dev, 26, 0x00);
6457         rt2800_rfcsr_write(rt2x00dev, 27, 0x09);
6458         rt2800_rfcsr_write(rt2x00dev, 28, 0x00);
6459         rt2800_rfcsr_write(rt2x00dev, 29, 0x10);
6460
6461         rt2800_rfcsr_write(rt2x00dev, 30, 0x00);
6462         rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
6463         rt2800_rfcsr_write(rt2x00dev, 32, 0x80);
6464         rt2800_rfcsr_write(rt2x00dev, 33, 0x00);
6465         rt2800_rfcsr_write(rt2x00dev, 34, 0x07);
6466         rt2800_rfcsr_write(rt2x00dev, 35, 0x12);
6467         rt2800_rfcsr_write(rt2x00dev, 36, 0x00);
6468         rt2800_rfcsr_write(rt2x00dev, 37, 0x08);
6469         rt2800_rfcsr_write(rt2x00dev, 38, 0x85);
6470         rt2800_rfcsr_write(rt2x00dev, 39, 0x1b);
6471
6472         if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
6473                 rt2800_rfcsr_write(rt2x00dev, 40, 0x0b);
6474         else
6475                 rt2800_rfcsr_write(rt2x00dev, 40, 0x4b);
6476         rt2800_rfcsr_write(rt2x00dev, 41, 0xbb);
6477         rt2800_rfcsr_write(rt2x00dev, 42, 0xd2);
6478         rt2800_rfcsr_write(rt2x00dev, 43, 0x9a);
6479         rt2800_rfcsr_write(rt2x00dev, 44, 0x0e);
6480         rt2800_rfcsr_write(rt2x00dev, 45, 0xa2);
6481         if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
6482                 rt2800_rfcsr_write(rt2x00dev, 46, 0x73);
6483         else
6484                 rt2800_rfcsr_write(rt2x00dev, 46, 0x7b);
6485         rt2800_rfcsr_write(rt2x00dev, 47, 0x00);
6486         rt2800_rfcsr_write(rt2x00dev, 48, 0x10);
6487         rt2800_rfcsr_write(rt2x00dev, 49, 0x94);
6488
6489         rt2800_rfcsr_write(rt2x00dev, 52, 0x38);
6490         if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
6491                 rt2800_rfcsr_write(rt2x00dev, 53, 0x00);
6492         else
6493                 rt2800_rfcsr_write(rt2x00dev, 53, 0x84);
6494         rt2800_rfcsr_write(rt2x00dev, 54, 0x78);
6495         rt2800_rfcsr_write(rt2x00dev, 55, 0x44);
6496         rt2800_rfcsr_write(rt2x00dev, 56, 0x22);
6497         rt2800_rfcsr_write(rt2x00dev, 57, 0x80);
6498         rt2800_rfcsr_write(rt2x00dev, 58, 0x7f);
6499         rt2800_rfcsr_write(rt2x00dev, 59, 0x63);
6500
6501         rt2800_rfcsr_write(rt2x00dev, 60, 0x45);
6502         if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
6503                 rt2800_rfcsr_write(rt2x00dev, 61, 0xd1);
6504         else
6505                 rt2800_rfcsr_write(rt2x00dev, 61, 0xdd);
6506         rt2800_rfcsr_write(rt2x00dev, 62, 0x00);
6507         rt2800_rfcsr_write(rt2x00dev, 63, 0x00);
6508
6509         rt2800_normal_mode_setup_5xxx(rt2x00dev);
6510
6511         rt2800_led_open_drain_enable(rt2x00dev);
6512 }
6513
6514 static void rt2800_init_rfcsr_5392(struct rt2x00_dev *rt2x00dev)
6515 {
6516         rt2800_rf_init_calibration(rt2x00dev, 2);
6517
6518         rt2800_rfcsr_write(rt2x00dev, 1, 0x17);
6519         rt2800_rfcsr_write(rt2x00dev, 2, 0x80);
6520         rt2800_rfcsr_write(rt2x00dev, 3, 0x88);
6521         rt2800_rfcsr_write(rt2x00dev, 5, 0x10);
6522         rt2800_rfcsr_write(rt2x00dev, 6, 0xe0);
6523         rt2800_rfcsr_write(rt2x00dev, 7, 0x00);
6524         rt2800_rfcsr_write(rt2x00dev, 10, 0x53);
6525         rt2800_rfcsr_write(rt2x00dev, 11, 0x4a);
6526         rt2800_rfcsr_write(rt2x00dev, 12, 0x46);
6527         rt2800_rfcsr_write(rt2x00dev, 13, 0x9f);
6528         rt2800_rfcsr_write(rt2x00dev, 14, 0x00);
6529         rt2800_rfcsr_write(rt2x00dev, 15, 0x00);
6530         rt2800_rfcsr_write(rt2x00dev, 16, 0x00);
6531         rt2800_rfcsr_write(rt2x00dev, 18, 0x03);
6532         rt2800_rfcsr_write(rt2x00dev, 19, 0x4d);
6533         rt2800_rfcsr_write(rt2x00dev, 20, 0x00);
6534         rt2800_rfcsr_write(rt2x00dev, 21, 0x8d);
6535         rt2800_rfcsr_write(rt2x00dev, 22, 0x20);
6536         rt2800_rfcsr_write(rt2x00dev, 23, 0x0b);
6537         rt2800_rfcsr_write(rt2x00dev, 24, 0x44);
6538         rt2800_rfcsr_write(rt2x00dev, 25, 0x80);
6539         rt2800_rfcsr_write(rt2x00dev, 26, 0x82);
6540         rt2800_rfcsr_write(rt2x00dev, 27, 0x09);
6541         rt2800_rfcsr_write(rt2x00dev, 28, 0x00);
6542         rt2800_rfcsr_write(rt2x00dev, 29, 0x10);
6543         rt2800_rfcsr_write(rt2x00dev, 30, 0x10);
6544         rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
6545         rt2800_rfcsr_write(rt2x00dev, 32, 0x20);
6546         rt2800_rfcsr_write(rt2x00dev, 33, 0xC0);
6547         rt2800_rfcsr_write(rt2x00dev, 34, 0x07);
6548         rt2800_rfcsr_write(rt2x00dev, 35, 0x12);
6549         rt2800_rfcsr_write(rt2x00dev, 36, 0x00);
6550         rt2800_rfcsr_write(rt2x00dev, 37, 0x08);
6551         rt2800_rfcsr_write(rt2x00dev, 38, 0x89);
6552         rt2800_rfcsr_write(rt2x00dev, 39, 0x1b);
6553         rt2800_rfcsr_write(rt2x00dev, 40, 0x0f);
6554         rt2800_rfcsr_write(rt2x00dev, 41, 0xbb);
6555         rt2800_rfcsr_write(rt2x00dev, 42, 0xd5);
6556         rt2800_rfcsr_write(rt2x00dev, 43, 0x9b);
6557         rt2800_rfcsr_write(rt2x00dev, 44, 0x0e);
6558         rt2800_rfcsr_write(rt2x00dev, 45, 0xa2);
6559         rt2800_rfcsr_write(rt2x00dev, 46, 0x73);
6560         rt2800_rfcsr_write(rt2x00dev, 47, 0x0c);
6561         rt2800_rfcsr_write(rt2x00dev, 48, 0x10);
6562         rt2800_rfcsr_write(rt2x00dev, 49, 0x94);
6563         rt2800_rfcsr_write(rt2x00dev, 50, 0x94);
6564         rt2800_rfcsr_write(rt2x00dev, 51, 0x3a);
6565         rt2800_rfcsr_write(rt2x00dev, 52, 0x48);
6566         rt2800_rfcsr_write(rt2x00dev, 53, 0x44);
6567         rt2800_rfcsr_write(rt2x00dev, 54, 0x38);
6568         rt2800_rfcsr_write(rt2x00dev, 55, 0x43);
6569         rt2800_rfcsr_write(rt2x00dev, 56, 0xa1);
6570         rt2800_rfcsr_write(rt2x00dev, 57, 0x00);
6571         rt2800_rfcsr_write(rt2x00dev, 58, 0x39);
6572         rt2800_rfcsr_write(rt2x00dev, 59, 0x07);
6573         rt2800_rfcsr_write(rt2x00dev, 60, 0x45);
6574         rt2800_rfcsr_write(rt2x00dev, 61, 0x91);
6575         rt2800_rfcsr_write(rt2x00dev, 62, 0x39);
6576         rt2800_rfcsr_write(rt2x00dev, 63, 0x07);
6577
6578         rt2800_normal_mode_setup_5xxx(rt2x00dev);
6579
6580         rt2800_led_open_drain_enable(rt2x00dev);
6581 }
6582
6583 static void rt2800_init_rfcsr_5592(struct rt2x00_dev *rt2x00dev)
6584 {
6585         rt2800_rf_init_calibration(rt2x00dev, 30);
6586
6587         rt2800_rfcsr_write(rt2x00dev, 1, 0x3F);
6588         rt2800_rfcsr_write(rt2x00dev, 3, 0x08);
6589         rt2800_rfcsr_write(rt2x00dev, 3, 0x08);
6590         rt2800_rfcsr_write(rt2x00dev, 5, 0x10);
6591         rt2800_rfcsr_write(rt2x00dev, 6, 0xE4);
6592         rt2800_rfcsr_write(rt2x00dev, 7, 0x00);
6593         rt2800_rfcsr_write(rt2x00dev, 14, 0x00);
6594         rt2800_rfcsr_write(rt2x00dev, 15, 0x00);
6595         rt2800_rfcsr_write(rt2x00dev, 16, 0x00);
6596         rt2800_rfcsr_write(rt2x00dev, 18, 0x03);
6597         rt2800_rfcsr_write(rt2x00dev, 19, 0x4D);
6598         rt2800_rfcsr_write(rt2x00dev, 20, 0x10);
6599         rt2800_rfcsr_write(rt2x00dev, 21, 0x8D);
6600         rt2800_rfcsr_write(rt2x00dev, 26, 0x82);
6601         rt2800_rfcsr_write(rt2x00dev, 28, 0x00);
6602         rt2800_rfcsr_write(rt2x00dev, 29, 0x10);
6603         rt2800_rfcsr_write(rt2x00dev, 33, 0xC0);
6604         rt2800_rfcsr_write(rt2x00dev, 34, 0x07);
6605         rt2800_rfcsr_write(rt2x00dev, 35, 0x12);
6606         rt2800_rfcsr_write(rt2x00dev, 47, 0x0C);
6607         rt2800_rfcsr_write(rt2x00dev, 53, 0x22);
6608         rt2800_rfcsr_write(rt2x00dev, 63, 0x07);
6609
6610         rt2800_rfcsr_write(rt2x00dev, 2, 0x80);
6611         msleep(1);
6612
6613         rt2800_adjust_freq_offset(rt2x00dev);
6614
6615         /* Enable DC filter */
6616         if (rt2x00_rt_rev_gte(rt2x00dev, RT5592, REV_RT5592C))
6617                 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
6618
6619         rt2800_normal_mode_setup_5xxx(rt2x00dev);
6620
6621         if (rt2x00_rt_rev_lt(rt2x00dev, RT5592, REV_RT5592C))
6622                 rt2800_rfcsr_write(rt2x00dev, 27, 0x03);
6623
6624         rt2800_led_open_drain_enable(rt2x00dev);
6625 }
6626
6627 static void rt2800_init_rfcsr(struct rt2x00_dev *rt2x00dev)
6628 {
6629         if (rt2800_is_305x_soc(rt2x00dev)) {
6630                 rt2800_init_rfcsr_305x_soc(rt2x00dev);
6631                 return;
6632         }
6633
6634         switch (rt2x00dev->chip.rt) {
6635         case RT3070:
6636         case RT3071:
6637         case RT3090:
6638                 rt2800_init_rfcsr_30xx(rt2x00dev);
6639                 break;
6640         case RT3290:
6641                 rt2800_init_rfcsr_3290(rt2x00dev);
6642                 break;
6643         case RT3352:
6644                 rt2800_init_rfcsr_3352(rt2x00dev);
6645                 break;
6646         case RT3390:
6647                 rt2800_init_rfcsr_3390(rt2x00dev);
6648                 break;
6649         case RT3572:
6650                 rt2800_init_rfcsr_3572(rt2x00dev);
6651                 break;
6652         case RT3593:
6653                 rt2800_init_rfcsr_3593(rt2x00dev);
6654                 break;
6655         case RT5390:
6656                 rt2800_init_rfcsr_5390(rt2x00dev);
6657                 break;
6658         case RT5392:
6659                 rt2800_init_rfcsr_5392(rt2x00dev);
6660                 break;
6661         case RT5592:
6662                 rt2800_init_rfcsr_5592(rt2x00dev);
6663                 break;
6664         }
6665 }
6666
6667 int rt2800_enable_radio(struct rt2x00_dev *rt2x00dev)
6668 {
6669         u32 reg;
6670         u16 word;
6671
6672         /*
6673          * Initialize MAC registers.
6674          */
6675         if (unlikely(rt2800_wait_wpdma_ready(rt2x00dev) ||
6676                      rt2800_init_registers(rt2x00dev)))
6677                 return -EIO;
6678
6679         /*
6680          * Wait BBP/RF to wake up.
6681          */
6682         if (unlikely(rt2800_wait_bbp_rf_ready(rt2x00dev)))
6683                 return -EIO;
6684
6685         /*
6686          * Send signal during boot time to initialize firmware.
6687          */
6688         rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
6689         rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
6690         if (rt2x00_is_usb(rt2x00dev))
6691                 rt2800_register_write(rt2x00dev, H2M_INT_SRC, 0);
6692         rt2800_mcu_request(rt2x00dev, MCU_BOOT_SIGNAL, 0, 0, 0);
6693         msleep(1);
6694
6695         /*
6696          * Make sure BBP is up and running.
6697          */
6698         if (unlikely(rt2800_wait_bbp_ready(rt2x00dev)))
6699                 return -EIO;
6700
6701         /*
6702          * Initialize BBP/RF registers.
6703          */
6704         rt2800_init_bbp(rt2x00dev);
6705         rt2800_init_rfcsr(rt2x00dev);
6706
6707         if (rt2x00_is_usb(rt2x00dev) &&
6708             (rt2x00_rt(rt2x00dev, RT3070) ||
6709              rt2x00_rt(rt2x00dev, RT3071) ||
6710              rt2x00_rt(rt2x00dev, RT3572))) {
6711                 udelay(200);
6712                 rt2800_mcu_request(rt2x00dev, MCU_CURRENT, 0, 0, 0);
6713                 udelay(10);
6714         }
6715
6716         /*
6717          * Enable RX.
6718          */
6719         rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
6720         rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 1);
6721         rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 0);
6722         rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
6723
6724         udelay(50);
6725
6726         rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
6727         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 1);
6728         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 1);
6729         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE, 2);
6730         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
6731         rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
6732
6733         rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
6734         rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 1);
6735         rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 1);
6736         rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
6737
6738         /*
6739          * Initialize LED control
6740          */
6741         rt2800_eeprom_read(rt2x00dev, EEPROM_LED_AG_CONF, &word);
6742         rt2800_mcu_request(rt2x00dev, MCU_LED_AG_CONF, 0xff,
6743                            word & 0xff, (word >> 8) & 0xff);
6744
6745         rt2800_eeprom_read(rt2x00dev, EEPROM_LED_ACT_CONF, &word);
6746         rt2800_mcu_request(rt2x00dev, MCU_LED_ACT_CONF, 0xff,
6747                            word & 0xff, (word >> 8) & 0xff);
6748
6749         rt2800_eeprom_read(rt2x00dev, EEPROM_LED_POLARITY, &word);
6750         rt2800_mcu_request(rt2x00dev, MCU_LED_LED_POLARITY, 0xff,
6751                            word & 0xff, (word >> 8) & 0xff);
6752
6753         return 0;
6754 }
6755 EXPORT_SYMBOL_GPL(rt2800_enable_radio);
6756
6757 void rt2800_disable_radio(struct rt2x00_dev *rt2x00dev)
6758 {
6759         u32 reg;
6760
6761         rt2800_disable_wpdma(rt2x00dev);
6762
6763         /* Wait for DMA, ignore error */
6764         rt2800_wait_wpdma_ready(rt2x00dev);
6765
6766         rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
6767         rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 0);
6768         rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 0);
6769         rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
6770 }
6771 EXPORT_SYMBOL_GPL(rt2800_disable_radio);
6772
6773 int rt2800_efuse_detect(struct rt2x00_dev *rt2x00dev)
6774 {
6775         u32 reg;
6776         u16 efuse_ctrl_reg;
6777
6778         if (rt2x00_rt(rt2x00dev, RT3290))
6779                 efuse_ctrl_reg = EFUSE_CTRL_3290;
6780         else
6781                 efuse_ctrl_reg = EFUSE_CTRL;
6782
6783         rt2800_register_read(rt2x00dev, efuse_ctrl_reg, &reg);
6784         return rt2x00_get_field32(reg, EFUSE_CTRL_PRESENT);
6785 }
6786 EXPORT_SYMBOL_GPL(rt2800_efuse_detect);
6787
6788 static void rt2800_efuse_read(struct rt2x00_dev *rt2x00dev, unsigned int i)
6789 {
6790         u32 reg;
6791         u16 efuse_ctrl_reg;
6792         u16 efuse_data0_reg;
6793         u16 efuse_data1_reg;
6794         u16 efuse_data2_reg;
6795         u16 efuse_data3_reg;
6796
6797         if (rt2x00_rt(rt2x00dev, RT3290)) {
6798                 efuse_ctrl_reg = EFUSE_CTRL_3290;
6799                 efuse_data0_reg = EFUSE_DATA0_3290;
6800                 efuse_data1_reg = EFUSE_DATA1_3290;
6801                 efuse_data2_reg = EFUSE_DATA2_3290;
6802                 efuse_data3_reg = EFUSE_DATA3_3290;
6803         } else {
6804                 efuse_ctrl_reg = EFUSE_CTRL;
6805                 efuse_data0_reg = EFUSE_DATA0;
6806                 efuse_data1_reg = EFUSE_DATA1;
6807                 efuse_data2_reg = EFUSE_DATA2;
6808                 efuse_data3_reg = EFUSE_DATA3;
6809         }
6810         mutex_lock(&rt2x00dev->csr_mutex);
6811
6812         rt2800_register_read_lock(rt2x00dev, efuse_ctrl_reg, &reg);
6813         rt2x00_set_field32(&reg, EFUSE_CTRL_ADDRESS_IN, i);
6814         rt2x00_set_field32(&reg, EFUSE_CTRL_MODE, 0);
6815         rt2x00_set_field32(&reg, EFUSE_CTRL_KICK, 1);
6816         rt2800_register_write_lock(rt2x00dev, efuse_ctrl_reg, reg);
6817
6818         /* Wait until the EEPROM has been loaded */
6819         rt2800_regbusy_read(rt2x00dev, efuse_ctrl_reg, EFUSE_CTRL_KICK, &reg);
6820         /* Apparently the data is read from end to start */
6821         rt2800_register_read_lock(rt2x00dev, efuse_data3_reg, &reg);
6822         /* The returned value is in CPU order, but eeprom is le */
6823         *(u32 *)&rt2x00dev->eeprom[i] = cpu_to_le32(reg);
6824         rt2800_register_read_lock(rt2x00dev, efuse_data2_reg, &reg);
6825         *(u32 *)&rt2x00dev->eeprom[i + 2] = cpu_to_le32(reg);
6826         rt2800_register_read_lock(rt2x00dev, efuse_data1_reg, &reg);
6827         *(u32 *)&rt2x00dev->eeprom[i + 4] = cpu_to_le32(reg);
6828         rt2800_register_read_lock(rt2x00dev, efuse_data0_reg, &reg);
6829         *(u32 *)&rt2x00dev->eeprom[i + 6] = cpu_to_le32(reg);
6830
6831         mutex_unlock(&rt2x00dev->csr_mutex);
6832 }
6833
6834 int rt2800_read_eeprom_efuse(struct rt2x00_dev *rt2x00dev)
6835 {
6836         unsigned int i;
6837
6838         for (i = 0; i < EEPROM_SIZE / sizeof(u16); i += 8)
6839                 rt2800_efuse_read(rt2x00dev, i);
6840
6841         return 0;
6842 }
6843 EXPORT_SYMBOL_GPL(rt2800_read_eeprom_efuse);
6844
6845 static u8 rt2800_get_txmixer_gain_24g(struct rt2x00_dev *rt2x00dev)
6846 {
6847         u16 word;
6848
6849         if (rt2x00_rt(rt2x00dev, RT3593))
6850                 return 0;
6851
6852         rt2800_eeprom_read(rt2x00dev, EEPROM_TXMIXER_GAIN_BG, &word);
6853         if ((word & 0x00ff) != 0x00ff)
6854                 return rt2x00_get_field16(word, EEPROM_TXMIXER_GAIN_BG_VAL);
6855
6856         return 0;
6857 }
6858
6859 static u8 rt2800_get_txmixer_gain_5g(struct rt2x00_dev *rt2x00dev)
6860 {
6861         u16 word;
6862
6863         if (rt2x00_rt(rt2x00dev, RT3593))
6864                 return 0;
6865
6866         rt2800_eeprom_read(rt2x00dev, EEPROM_TXMIXER_GAIN_A, &word);
6867         if ((word & 0x00ff) != 0x00ff)
6868                 return rt2x00_get_field16(word, EEPROM_TXMIXER_GAIN_A_VAL);
6869
6870         return 0;
6871 }
6872
6873 static int rt2800_validate_eeprom(struct rt2x00_dev *rt2x00dev)
6874 {
6875         struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
6876         u16 word;
6877         u8 *mac;
6878         u8 default_lna_gain;
6879         int retval;
6880
6881         /*
6882          * Read the EEPROM.
6883          */
6884         retval = rt2800_read_eeprom(rt2x00dev);
6885         if (retval)
6886                 return retval;
6887
6888         /*
6889          * Start validation of the data that has been read.
6890          */
6891         mac = rt2800_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
6892         if (!is_valid_ether_addr(mac)) {
6893                 eth_random_addr(mac);
6894                 rt2x00_eeprom_dbg(rt2x00dev, "MAC: %pM\n", mac);
6895         }
6896
6897         rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &word);
6898         if (word == 0xffff) {
6899                 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_RXPATH, 2);
6900                 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_TXPATH, 1);
6901                 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_RF_TYPE, RF2820);
6902                 rt2800_eeprom_write(rt2x00dev, EEPROM_NIC_CONF0, word);
6903                 rt2x00_eeprom_dbg(rt2x00dev, "Antenna: 0x%04x\n", word);
6904         } else if (rt2x00_rt(rt2x00dev, RT2860) ||
6905                    rt2x00_rt(rt2x00dev, RT2872)) {
6906                 /*
6907                  * There is a max of 2 RX streams for RT28x0 series
6908                  */
6909                 if (rt2x00_get_field16(word, EEPROM_NIC_CONF0_RXPATH) > 2)
6910                         rt2x00_set_field16(&word, EEPROM_NIC_CONF0_RXPATH, 2);
6911                 rt2800_eeprom_write(rt2x00dev, EEPROM_NIC_CONF0, word);
6912         }
6913
6914         rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &word);
6915         if (word == 0xffff) {
6916                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_HW_RADIO, 0);
6917                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_EXTERNAL_TX_ALC, 0);
6918                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_EXTERNAL_LNA_2G, 0);
6919                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_EXTERNAL_LNA_5G, 0);
6920                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_CARDBUS_ACCEL, 0);
6921                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_SB_2G, 0);
6922                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_SB_5G, 0);
6923                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_WPS_PBC, 0);
6924                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_2G, 0);
6925                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_5G, 0);
6926                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BROADBAND_EXT_LNA, 0);
6927                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_ANT_DIVERSITY, 0);
6928                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_INTERNAL_TX_ALC, 0);
6929                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BT_COEXIST, 0);
6930                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_DAC_TEST, 0);
6931                 rt2800_eeprom_write(rt2x00dev, EEPROM_NIC_CONF1, word);
6932                 rt2x00_eeprom_dbg(rt2x00dev, "NIC: 0x%04x\n", word);
6933         }
6934
6935         rt2800_eeprom_read(rt2x00dev, EEPROM_FREQ, &word);
6936         if ((word & 0x00ff) == 0x00ff) {
6937                 rt2x00_set_field16(&word, EEPROM_FREQ_OFFSET, 0);
6938                 rt2800_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
6939                 rt2x00_eeprom_dbg(rt2x00dev, "Freq: 0x%04x\n", word);
6940         }
6941         if ((word & 0xff00) == 0xff00) {
6942                 rt2x00_set_field16(&word, EEPROM_FREQ_LED_MODE,
6943                                    LED_MODE_TXRX_ACTIVITY);
6944                 rt2x00_set_field16(&word, EEPROM_FREQ_LED_POLARITY, 0);
6945                 rt2800_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
6946                 rt2800_eeprom_write(rt2x00dev, EEPROM_LED_AG_CONF, 0x5555);
6947                 rt2800_eeprom_write(rt2x00dev, EEPROM_LED_ACT_CONF, 0x2221);
6948                 rt2800_eeprom_write(rt2x00dev, EEPROM_LED_POLARITY, 0xa9f8);
6949                 rt2x00_eeprom_dbg(rt2x00dev, "Led Mode: 0x%04x\n", word);
6950         }
6951
6952         /*
6953          * During the LNA validation we are going to use
6954          * lna0 as correct value. Note that EEPROM_LNA
6955          * is never validated.
6956          */
6957         rt2800_eeprom_read(rt2x00dev, EEPROM_LNA, &word);
6958         default_lna_gain = rt2x00_get_field16(word, EEPROM_LNA_A0);
6959
6960         rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_BG, &word);
6961         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET0)) > 10)
6962                 rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET0, 0);
6963         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET1)) > 10)
6964                 rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET1, 0);
6965         rt2800_eeprom_write(rt2x00dev, EEPROM_RSSI_BG, word);
6966
6967         drv_data->txmixer_gain_24g = rt2800_get_txmixer_gain_24g(rt2x00dev);
6968
6969         rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &word);
6970         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG2_OFFSET2)) > 10)
6971                 rt2x00_set_field16(&word, EEPROM_RSSI_BG2_OFFSET2, 0);
6972         if (!rt2x00_rt(rt2x00dev, RT3593)) {
6973                 if (rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0x00 ||
6974                     rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0xff)
6975                         rt2x00_set_field16(&word, EEPROM_RSSI_BG2_LNA_A1,
6976                                            default_lna_gain);
6977         }
6978         rt2800_eeprom_write(rt2x00dev, EEPROM_RSSI_BG2, word);
6979
6980         drv_data->txmixer_gain_5g = rt2800_get_txmixer_gain_5g(rt2x00dev);
6981
6982         rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_A, &word);
6983         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET0)) > 10)
6984                 rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET0, 0);
6985         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET1)) > 10)
6986                 rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET1, 0);
6987         rt2800_eeprom_write(rt2x00dev, EEPROM_RSSI_A, word);
6988
6989         rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &word);
6990         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A2_OFFSET2)) > 10)
6991                 rt2x00_set_field16(&word, EEPROM_RSSI_A2_OFFSET2, 0);
6992         if (!rt2x00_rt(rt2x00dev, RT3593)) {
6993                 if (rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0x00 ||
6994                     rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0xff)
6995                         rt2x00_set_field16(&word, EEPROM_RSSI_A2_LNA_A2,
6996                                            default_lna_gain);
6997         }
6998         rt2800_eeprom_write(rt2x00dev, EEPROM_RSSI_A2, word);
6999
7000         if (rt2x00_rt(rt2x00dev, RT3593)) {
7001                 rt2800_eeprom_read(rt2x00dev, EEPROM_EXT_LNA2, &word);
7002                 if (rt2x00_get_field16(word, EEPROM_EXT_LNA2_A1) == 0x00 ||
7003                     rt2x00_get_field16(word, EEPROM_EXT_LNA2_A1) == 0xff)
7004                         rt2x00_set_field16(&word, EEPROM_EXT_LNA2_A1,
7005                                            default_lna_gain);
7006                 if (rt2x00_get_field16(word, EEPROM_EXT_LNA2_A2) == 0x00 ||
7007                     rt2x00_get_field16(word, EEPROM_EXT_LNA2_A2) == 0xff)
7008                         rt2x00_set_field16(&word, EEPROM_EXT_LNA2_A1,
7009                                            default_lna_gain);
7010                 rt2800_eeprom_write(rt2x00dev, EEPROM_EXT_LNA2, word);
7011         }
7012
7013         return 0;
7014 }
7015
7016 static int rt2800_init_eeprom(struct rt2x00_dev *rt2x00dev)
7017 {
7018         u16 value;
7019         u16 eeprom;
7020         u16 rf;
7021
7022         /*
7023          * Read EEPROM word for configuration.
7024          */
7025         rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom);
7026
7027         /*
7028          * Identify RF chipset by EEPROM value
7029          * RT28xx/RT30xx: defined in "EEPROM_NIC_CONF0_RF_TYPE" field
7030          * RT53xx: defined in "EEPROM_CHIP_ID" field
7031          */
7032         if (rt2x00_rt(rt2x00dev, RT3290) ||
7033             rt2x00_rt(rt2x00dev, RT5390) ||
7034             rt2x00_rt(rt2x00dev, RT5392))
7035                 rt2800_eeprom_read(rt2x00dev, EEPROM_CHIP_ID, &rf);
7036         else
7037                 rf = rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RF_TYPE);
7038
7039         switch (rf) {
7040         case RF2820:
7041         case RF2850:
7042         case RF2720:
7043         case RF2750:
7044         case RF3020:
7045         case RF2020:
7046         case RF3021:
7047         case RF3022:
7048         case RF3052:
7049         case RF3053:
7050         case RF3070:
7051         case RF3290:
7052         case RF3320:
7053         case RF3322:
7054         case RF5360:
7055         case RF5370:
7056         case RF5372:
7057         case RF5390:
7058         case RF5392:
7059         case RF5592:
7060                 break;
7061         default:
7062                 rt2x00_err(rt2x00dev, "Invalid RF chipset 0x%04x detected\n",
7063                            rf);
7064                 return -ENODEV;
7065         }
7066
7067         rt2x00_set_rf(rt2x00dev, rf);
7068
7069         /*
7070          * Identify default antenna configuration.
7071          */
7072         rt2x00dev->default_ant.tx_chain_num =
7073             rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH);
7074         rt2x00dev->default_ant.rx_chain_num =
7075             rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH);
7076
7077         rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
7078
7079         if (rt2x00_rt(rt2x00dev, RT3070) ||
7080             rt2x00_rt(rt2x00dev, RT3090) ||
7081             rt2x00_rt(rt2x00dev, RT3352) ||
7082             rt2x00_rt(rt2x00dev, RT3390)) {
7083                 value = rt2x00_get_field16(eeprom,
7084                                 EEPROM_NIC_CONF1_ANT_DIVERSITY);
7085                 switch (value) {
7086                 case 0:
7087                 case 1:
7088                 case 2:
7089                         rt2x00dev->default_ant.tx = ANTENNA_A;
7090                         rt2x00dev->default_ant.rx = ANTENNA_A;
7091                         break;
7092                 case 3:
7093                         rt2x00dev->default_ant.tx = ANTENNA_A;
7094                         rt2x00dev->default_ant.rx = ANTENNA_B;
7095                         break;
7096                 }
7097         } else {
7098                 rt2x00dev->default_ant.tx = ANTENNA_A;
7099                 rt2x00dev->default_ant.rx = ANTENNA_A;
7100         }
7101
7102         if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390R)) {
7103                 rt2x00dev->default_ant.tx = ANTENNA_HW_DIVERSITY; /* Unused */
7104                 rt2x00dev->default_ant.rx = ANTENNA_HW_DIVERSITY; /* Unused */
7105         }
7106
7107         /*
7108          * Determine external LNA informations.
7109          */
7110         if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_EXTERNAL_LNA_5G))
7111                 __set_bit(CAPABILITY_EXTERNAL_LNA_A, &rt2x00dev->cap_flags);
7112         if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_EXTERNAL_LNA_2G))
7113                 __set_bit(CAPABILITY_EXTERNAL_LNA_BG, &rt2x00dev->cap_flags);
7114
7115         /*
7116          * Detect if this device has an hardware controlled radio.
7117          */
7118         if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_HW_RADIO))
7119                 __set_bit(CAPABILITY_HW_BUTTON, &rt2x00dev->cap_flags);
7120
7121         /*
7122          * Detect if this device has Bluetooth co-existence.
7123          */
7124         if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_BT_COEXIST))
7125                 __set_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags);
7126
7127         /*
7128          * Read frequency offset and RF programming sequence.
7129          */
7130         rt2800_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom);
7131         rt2x00dev->freq_offset = rt2x00_get_field16(eeprom, EEPROM_FREQ_OFFSET);
7132
7133         /*
7134          * Store led settings, for correct led behaviour.
7135          */
7136 #ifdef CONFIG_RT2X00_LIB_LEDS
7137         rt2800_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO);
7138         rt2800_init_led(rt2x00dev, &rt2x00dev->led_assoc, LED_TYPE_ASSOC);
7139         rt2800_init_led(rt2x00dev, &rt2x00dev->led_qual, LED_TYPE_QUALITY);
7140
7141         rt2x00dev->led_mcu_reg = eeprom;
7142 #endif /* CONFIG_RT2X00_LIB_LEDS */
7143
7144         /*
7145          * Check if support EIRP tx power limit feature.
7146          */
7147         rt2800_eeprom_read(rt2x00dev, EEPROM_EIRP_MAX_TX_POWER, &eeprom);
7148
7149         if (rt2x00_get_field16(eeprom, EEPROM_EIRP_MAX_TX_POWER_2GHZ) <
7150                                         EIRP_MAX_TX_POWER_LIMIT)
7151                 __set_bit(CAPABILITY_POWER_LIMIT, &rt2x00dev->cap_flags);
7152
7153         return 0;
7154 }
7155
7156 /*
7157  * RF value list for rt28xx
7158  * Supports: 2.4 GHz (all) & 5.2 GHz (RF2850 & RF2750)
7159  */
7160 static const struct rf_channel rf_vals[] = {
7161         { 1,  0x18402ecc, 0x184c0786, 0x1816b455, 0x1800510b },
7162         { 2,  0x18402ecc, 0x184c0786, 0x18168a55, 0x1800519f },
7163         { 3,  0x18402ecc, 0x184c078a, 0x18168a55, 0x1800518b },
7164         { 4,  0x18402ecc, 0x184c078a, 0x18168a55, 0x1800519f },
7165         { 5,  0x18402ecc, 0x184c078e, 0x18168a55, 0x1800518b },
7166         { 6,  0x18402ecc, 0x184c078e, 0x18168a55, 0x1800519f },
7167         { 7,  0x18402ecc, 0x184c0792, 0x18168a55, 0x1800518b },
7168         { 8,  0x18402ecc, 0x184c0792, 0x18168a55, 0x1800519f },
7169         { 9,  0x18402ecc, 0x184c0796, 0x18168a55, 0x1800518b },
7170         { 10, 0x18402ecc, 0x184c0796, 0x18168a55, 0x1800519f },
7171         { 11, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800518b },
7172         { 12, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800519f },
7173         { 13, 0x18402ecc, 0x184c079e, 0x18168a55, 0x1800518b },
7174         { 14, 0x18402ecc, 0x184c07a2, 0x18168a55, 0x18005193 },
7175
7176         /* 802.11 UNI / HyperLan 2 */
7177         { 36, 0x18402ecc, 0x184c099a, 0x18158a55, 0x180ed1a3 },
7178         { 38, 0x18402ecc, 0x184c099e, 0x18158a55, 0x180ed193 },
7179         { 40, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed183 },
7180         { 44, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed1a3 },
7181         { 46, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed18b },
7182         { 48, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed19b },
7183         { 52, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed193 },
7184         { 54, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed1a3 },
7185         { 56, 0x18402ec8, 0x184c068e, 0x18158a55, 0x180ed18b },
7186         { 60, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed183 },
7187         { 62, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed193 },
7188         { 64, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed1a3 },
7189
7190         /* 802.11 HyperLan 2 */
7191         { 100, 0x18402ec8, 0x184c06b2, 0x18178a55, 0x180ed783 },
7192         { 102, 0x18402ec8, 0x184c06b2, 0x18578a55, 0x180ed793 },
7193         { 104, 0x18402ec8, 0x185c06b2, 0x18578a55, 0x180ed1a3 },
7194         { 108, 0x18402ecc, 0x185c0a32, 0x18578a55, 0x180ed193 },
7195         { 110, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed183 },
7196         { 112, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed19b },
7197         { 116, 0x18402ecc, 0x184c0a3a, 0x18178a55, 0x180ed1a3 },
7198         { 118, 0x18402ecc, 0x184c0a3e, 0x18178a55, 0x180ed193 },
7199         { 120, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed183 },
7200         { 124, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed193 },
7201         { 126, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed15b },
7202         { 128, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed1a3 },
7203         { 132, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed18b },
7204         { 134, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed193 },
7205         { 136, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed19b },
7206         { 140, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed183 },
7207
7208         /* 802.11 UNII */
7209         { 149, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed1a7 },
7210         { 151, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed187 },
7211         { 153, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed18f },
7212         { 157, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed19f },
7213         { 159, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed1a7 },
7214         { 161, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed187 },
7215         { 165, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed197 },
7216         { 167, 0x18402ec4, 0x184c03d2, 0x18179855, 0x1815531f },
7217         { 169, 0x18402ec4, 0x184c03d2, 0x18179855, 0x18155327 },
7218         { 171, 0x18402ec4, 0x184c03d6, 0x18179855, 0x18155307 },
7219         { 173, 0x18402ec4, 0x184c03d6, 0x18179855, 0x1815530f },
7220
7221         /* 802.11 Japan */
7222         { 184, 0x15002ccc, 0x1500491e, 0x1509be55, 0x150c0a0b },
7223         { 188, 0x15002ccc, 0x15004922, 0x1509be55, 0x150c0a13 },
7224         { 192, 0x15002ccc, 0x15004926, 0x1509be55, 0x150c0a1b },
7225         { 196, 0x15002ccc, 0x1500492a, 0x1509be55, 0x150c0a23 },
7226         { 208, 0x15002ccc, 0x1500493a, 0x1509be55, 0x150c0a13 },
7227         { 212, 0x15002ccc, 0x1500493e, 0x1509be55, 0x150c0a1b },
7228         { 216, 0x15002ccc, 0x15004982, 0x1509be55, 0x150c0a23 },
7229 };
7230
7231 /*
7232  * RF value list for rt3xxx
7233  * Supports: 2.4 GHz (all) & 5.2 GHz (RF3052)
7234  */
7235 static const struct rf_channel rf_vals_3x[] = {
7236         {1,  241, 2, 2 },
7237         {2,  241, 2, 7 },
7238         {3,  242, 2, 2 },
7239         {4,  242, 2, 7 },
7240         {5,  243, 2, 2 },
7241         {6,  243, 2, 7 },
7242         {7,  244, 2, 2 },
7243         {8,  244, 2, 7 },
7244         {9,  245, 2, 2 },
7245         {10, 245, 2, 7 },
7246         {11, 246, 2, 2 },
7247         {12, 246, 2, 7 },
7248         {13, 247, 2, 2 },
7249         {14, 248, 2, 4 },
7250
7251         /* 802.11 UNI / HyperLan 2 */
7252         {36, 0x56, 0, 4},
7253         {38, 0x56, 0, 6},
7254         {40, 0x56, 0, 8},
7255         {44, 0x57, 0, 0},
7256         {46, 0x57, 0, 2},
7257         {48, 0x57, 0, 4},
7258         {52, 0x57, 0, 8},
7259         {54, 0x57, 0, 10},
7260         {56, 0x58, 0, 0},
7261         {60, 0x58, 0, 4},
7262         {62, 0x58, 0, 6},
7263         {64, 0x58, 0, 8},
7264
7265         /* 802.11 HyperLan 2 */
7266         {100, 0x5b, 0, 8},
7267         {102, 0x5b, 0, 10},
7268         {104, 0x5c, 0, 0},
7269         {108, 0x5c, 0, 4},
7270         {110, 0x5c, 0, 6},
7271         {112, 0x5c, 0, 8},
7272         {116, 0x5d, 0, 0},
7273         {118, 0x5d, 0, 2},
7274         {120, 0x5d, 0, 4},
7275         {124, 0x5d, 0, 8},
7276         {126, 0x5d, 0, 10},
7277         {128, 0x5e, 0, 0},
7278         {132, 0x5e, 0, 4},
7279         {134, 0x5e, 0, 6},
7280         {136, 0x5e, 0, 8},
7281         {140, 0x5f, 0, 0},
7282
7283         /* 802.11 UNII */
7284         {149, 0x5f, 0, 9},
7285         {151, 0x5f, 0, 11},
7286         {153, 0x60, 0, 1},
7287         {157, 0x60, 0, 5},
7288         {159, 0x60, 0, 7},
7289         {161, 0x60, 0, 9},
7290         {165, 0x61, 0, 1},
7291         {167, 0x61, 0, 3},
7292         {169, 0x61, 0, 5},
7293         {171, 0x61, 0, 7},
7294         {173, 0x61, 0, 9},
7295 };
7296
7297 static const struct rf_channel rf_vals_5592_xtal20[] = {
7298         /* Channel, N, K, mod, R */
7299         {1, 482, 4, 10, 3},
7300         {2, 483, 4, 10, 3},
7301         {3, 484, 4, 10, 3},
7302         {4, 485, 4, 10, 3},
7303         {5, 486, 4, 10, 3},
7304         {6, 487, 4, 10, 3},
7305         {7, 488, 4, 10, 3},
7306         {8, 489, 4, 10, 3},
7307         {9, 490, 4, 10, 3},
7308         {10, 491, 4, 10, 3},
7309         {11, 492, 4, 10, 3},
7310         {12, 493, 4, 10, 3},
7311         {13, 494, 4, 10, 3},
7312         {14, 496, 8, 10, 3},
7313         {36, 172, 8, 12, 1},
7314         {38, 173, 0, 12, 1},
7315         {40, 173, 4, 12, 1},
7316         {42, 173, 8, 12, 1},
7317         {44, 174, 0, 12, 1},
7318         {46, 174, 4, 12, 1},
7319         {48, 174, 8, 12, 1},
7320         {50, 175, 0, 12, 1},
7321         {52, 175, 4, 12, 1},
7322         {54, 175, 8, 12, 1},
7323         {56, 176, 0, 12, 1},
7324         {58, 176, 4, 12, 1},
7325         {60, 176, 8, 12, 1},
7326         {62, 177, 0, 12, 1},
7327         {64, 177, 4, 12, 1},
7328         {100, 183, 4, 12, 1},
7329         {102, 183, 8, 12, 1},
7330         {104, 184, 0, 12, 1},
7331         {106, 184, 4, 12, 1},
7332         {108, 184, 8, 12, 1},
7333         {110, 185, 0, 12, 1},
7334         {112, 185, 4, 12, 1},
7335         {114, 185, 8, 12, 1},
7336         {116, 186, 0, 12, 1},
7337         {118, 186, 4, 12, 1},
7338         {120, 186, 8, 12, 1},
7339         {122, 187, 0, 12, 1},
7340         {124, 187, 4, 12, 1},
7341         {126, 187, 8, 12, 1},
7342         {128, 188, 0, 12, 1},
7343         {130, 188, 4, 12, 1},
7344         {132, 188, 8, 12, 1},
7345         {134, 189, 0, 12, 1},
7346         {136, 189, 4, 12, 1},
7347         {138, 189, 8, 12, 1},
7348         {140, 190, 0, 12, 1},
7349         {149, 191, 6, 12, 1},
7350         {151, 191, 10, 12, 1},
7351         {153, 192, 2, 12, 1},
7352         {155, 192, 6, 12, 1},
7353         {157, 192, 10, 12, 1},
7354         {159, 193, 2, 12, 1},
7355         {161, 193, 6, 12, 1},
7356         {165, 194, 2, 12, 1},
7357         {184, 164, 0, 12, 1},
7358         {188, 164, 4, 12, 1},
7359         {192, 165, 8, 12, 1},
7360         {196, 166, 0, 12, 1},
7361 };
7362
7363 static const struct rf_channel rf_vals_5592_xtal40[] = {
7364         /* Channel, N, K, mod, R */
7365         {1, 241, 2, 10, 3},
7366         {2, 241, 7, 10, 3},
7367         {3, 242, 2, 10, 3},
7368         {4, 242, 7, 10, 3},
7369         {5, 243, 2, 10, 3},
7370         {6, 243, 7, 10, 3},
7371         {7, 244, 2, 10, 3},
7372         {8, 244, 7, 10, 3},
7373         {9, 245, 2, 10, 3},
7374         {10, 245, 7, 10, 3},
7375         {11, 246, 2, 10, 3},
7376         {12, 246, 7, 10, 3},
7377         {13, 247, 2, 10, 3},
7378         {14, 248, 4, 10, 3},
7379         {36, 86, 4, 12, 1},
7380         {38, 86, 6, 12, 1},
7381         {40, 86, 8, 12, 1},
7382         {42, 86, 10, 12, 1},
7383         {44, 87, 0, 12, 1},
7384         {46, 87, 2, 12, 1},
7385         {48, 87, 4, 12, 1},
7386         {50, 87, 6, 12, 1},
7387         {52, 87, 8, 12, 1},
7388         {54, 87, 10, 12, 1},
7389         {56, 88, 0, 12, 1},
7390         {58, 88, 2, 12, 1},
7391         {60, 88, 4, 12, 1},
7392         {62, 88, 6, 12, 1},
7393         {64, 88, 8, 12, 1},
7394         {100, 91, 8, 12, 1},
7395         {102, 91, 10, 12, 1},
7396         {104, 92, 0, 12, 1},
7397         {106, 92, 2, 12, 1},
7398         {108, 92, 4, 12, 1},
7399         {110, 92, 6, 12, 1},
7400         {112, 92, 8, 12, 1},
7401         {114, 92, 10, 12, 1},
7402         {116, 93, 0, 12, 1},
7403         {118, 93, 2, 12, 1},
7404         {120, 93, 4, 12, 1},
7405         {122, 93, 6, 12, 1},
7406         {124, 93, 8, 12, 1},
7407         {126, 93, 10, 12, 1},
7408         {128, 94, 0, 12, 1},
7409         {130, 94, 2, 12, 1},
7410         {132, 94, 4, 12, 1},
7411         {134, 94, 6, 12, 1},
7412         {136, 94, 8, 12, 1},
7413         {138, 94, 10, 12, 1},
7414         {140, 95, 0, 12, 1},
7415         {149, 95, 9, 12, 1},
7416         {151, 95, 11, 12, 1},
7417         {153, 96, 1, 12, 1},
7418         {155, 96, 3, 12, 1},
7419         {157, 96, 5, 12, 1},
7420         {159, 96, 7, 12, 1},
7421         {161, 96, 9, 12, 1},
7422         {165, 97, 1, 12, 1},
7423         {184, 82, 0, 12, 1},
7424         {188, 82, 4, 12, 1},
7425         {192, 82, 8, 12, 1},
7426         {196, 83, 0, 12, 1},
7427 };
7428
7429 static const struct rf_channel rf_vals_3053[] = {
7430         /* Channel, N, R, K */
7431         {1, 241, 2, 2},
7432         {2, 241, 2, 7},
7433         {3, 242, 2, 2},
7434         {4, 242, 2, 7},
7435         {5, 243, 2, 2},
7436         {6, 243, 2, 7},
7437         {7, 244, 2, 2},
7438         {8, 244, 2, 7},
7439         {9, 245, 2, 2},
7440         {10, 245, 2, 7},
7441         {11, 246, 2, 2},
7442         {12, 246, 2, 7},
7443         {13, 247, 2, 2},
7444         {14, 248, 2, 4},
7445
7446         {36, 0x56, 0, 4},
7447         {38, 0x56, 0, 6},
7448         {40, 0x56, 0, 8},
7449         {44, 0x57, 0, 0},
7450         {46, 0x57, 0, 2},
7451         {48, 0x57, 0, 4},
7452         {52, 0x57, 0, 8},
7453         {54, 0x57, 0, 10},
7454         {56, 0x58, 0, 0},
7455         {60, 0x58, 0, 4},
7456         {62, 0x58, 0, 6},
7457         {64, 0x58, 0, 8},
7458
7459         {100, 0x5B, 0, 8},
7460         {102, 0x5B, 0, 10},
7461         {104, 0x5C, 0, 0},
7462         {108, 0x5C, 0, 4},
7463         {110, 0x5C, 0, 6},
7464         {112, 0x5C, 0, 8},
7465
7466         /* NOTE: Channel 114 has been removed intentionally.
7467          * The EEPROM contains no TX power values for that,
7468          * and it is disabled in the vendor driver as well.
7469          */
7470
7471         {116, 0x5D, 0, 0},
7472         {118, 0x5D, 0, 2},
7473         {120, 0x5D, 0, 4},
7474         {124, 0x5D, 0, 8},
7475         {126, 0x5D, 0, 10},
7476         {128, 0x5E, 0, 0},
7477         {132, 0x5E, 0, 4},
7478         {134, 0x5E, 0, 6},
7479         {136, 0x5E, 0, 8},
7480         {140, 0x5F, 0, 0},
7481
7482         {149, 0x5F, 0, 9},
7483         {151, 0x5F, 0, 11},
7484         {153, 0x60, 0, 1},
7485         {157, 0x60, 0, 5},
7486         {159, 0x60, 0, 7},
7487         {161, 0x60, 0, 9},
7488         {165, 0x61, 0, 1},
7489         {167, 0x61, 0, 3},
7490         {169, 0x61, 0, 5},
7491         {171, 0x61, 0, 7},
7492         {173, 0x61, 0, 9},
7493 };
7494
7495 static int rt2800_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
7496 {
7497         struct hw_mode_spec *spec = &rt2x00dev->spec;
7498         struct channel_info *info;
7499         char *default_power1;
7500         char *default_power2;
7501         char *default_power3;
7502         unsigned int i;
7503         u16 eeprom;
7504         u32 reg;
7505
7506         /*
7507          * Disable powersaving as default on PCI devices.
7508          */
7509         if (rt2x00_is_pci(rt2x00dev) || rt2x00_is_soc(rt2x00dev))
7510                 rt2x00dev->hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
7511
7512         /*
7513          * Initialize all hw fields.
7514          */
7515         rt2x00dev->hw->flags =
7516             IEEE80211_HW_SIGNAL_DBM |
7517             IEEE80211_HW_SUPPORTS_PS |
7518             IEEE80211_HW_PS_NULLFUNC_STACK |
7519             IEEE80211_HW_AMPDU_AGGREGATION |
7520             IEEE80211_HW_REPORTS_TX_ACK_STATUS |
7521             IEEE80211_HW_SUPPORTS_HT_CCK_RATES;
7522
7523         /*
7524          * Don't set IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING for USB devices
7525          * unless we are capable of sending the buffered frames out after the
7526          * DTIM transmission using rt2x00lib_beacondone. This will send out
7527          * multicast and broadcast traffic immediately instead of buffering it
7528          * infinitly and thus dropping it after some time.
7529          */
7530         if (!rt2x00_is_usb(rt2x00dev))
7531                 rt2x00dev->hw->flags |=
7532                         IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING;
7533
7534         SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev);
7535         SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
7536                                 rt2800_eeprom_addr(rt2x00dev,
7537                                                    EEPROM_MAC_ADDR_0));
7538
7539         /*
7540          * As rt2800 has a global fallback table we cannot specify
7541          * more then one tx rate per frame but since the hw will
7542          * try several rates (based on the fallback table) we should
7543          * initialize max_report_rates to the maximum number of rates
7544          * we are going to try. Otherwise mac80211 will truncate our
7545          * reported tx rates and the rc algortihm will end up with
7546          * incorrect data.
7547          */
7548         rt2x00dev->hw->max_rates = 1;
7549         rt2x00dev->hw->max_report_rates = 7;
7550         rt2x00dev->hw->max_rate_tries = 1;
7551
7552         rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom);
7553
7554         /*
7555          * Initialize hw_mode information.
7556          */
7557         spec->supported_bands = SUPPORT_BAND_2GHZ;
7558         spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM;
7559
7560         if (rt2x00_rf(rt2x00dev, RF2820) ||
7561             rt2x00_rf(rt2x00dev, RF2720)) {
7562                 spec->num_channels = 14;
7563                 spec->channels = rf_vals;
7564         } else if (rt2x00_rf(rt2x00dev, RF2850) ||
7565                    rt2x00_rf(rt2x00dev, RF2750)) {
7566                 spec->supported_bands |= SUPPORT_BAND_5GHZ;
7567                 spec->num_channels = ARRAY_SIZE(rf_vals);
7568                 spec->channels = rf_vals;
7569         } else if (rt2x00_rf(rt2x00dev, RF3020) ||
7570                    rt2x00_rf(rt2x00dev, RF2020) ||
7571                    rt2x00_rf(rt2x00dev, RF3021) ||
7572                    rt2x00_rf(rt2x00dev, RF3022) ||
7573                    rt2x00_rf(rt2x00dev, RF3070) ||
7574                    rt2x00_rf(rt2x00dev, RF3290) ||
7575                    rt2x00_rf(rt2x00dev, RF3320) ||
7576                    rt2x00_rf(rt2x00dev, RF3322) ||
7577                    rt2x00_rf(rt2x00dev, RF5360) ||
7578                    rt2x00_rf(rt2x00dev, RF5370) ||
7579                    rt2x00_rf(rt2x00dev, RF5372) ||
7580                    rt2x00_rf(rt2x00dev, RF5390) ||
7581                    rt2x00_rf(rt2x00dev, RF5392)) {
7582                 spec->num_channels = 14;
7583                 spec->channels = rf_vals_3x;
7584         } else if (rt2x00_rf(rt2x00dev, RF3052)) {
7585                 spec->supported_bands |= SUPPORT_BAND_5GHZ;
7586                 spec->num_channels = ARRAY_SIZE(rf_vals_3x);
7587                 spec->channels = rf_vals_3x;
7588         } else if (rt2x00_rf(rt2x00dev, RF3053)) {
7589                 spec->supported_bands |= SUPPORT_BAND_5GHZ;
7590                 spec->num_channels = ARRAY_SIZE(rf_vals_3053);
7591                 spec->channels = rf_vals_3053;
7592         } else if (rt2x00_rf(rt2x00dev, RF5592)) {
7593                 spec->supported_bands |= SUPPORT_BAND_5GHZ;
7594
7595                 rt2800_register_read(rt2x00dev, MAC_DEBUG_INDEX, &reg);
7596                 if (rt2x00_get_field32(reg, MAC_DEBUG_INDEX_XTAL)) {
7597                         spec->num_channels = ARRAY_SIZE(rf_vals_5592_xtal40);
7598                         spec->channels = rf_vals_5592_xtal40;
7599                 } else {
7600                         spec->num_channels = ARRAY_SIZE(rf_vals_5592_xtal20);
7601                         spec->channels = rf_vals_5592_xtal20;
7602                 }
7603         }
7604
7605         if (WARN_ON_ONCE(!spec->channels))
7606                 return -ENODEV;
7607
7608         /*
7609          * Initialize HT information.
7610          */
7611         if (!rt2x00_rf(rt2x00dev, RF2020))
7612                 spec->ht.ht_supported = true;
7613         else
7614                 spec->ht.ht_supported = false;
7615
7616         spec->ht.cap =
7617             IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
7618             IEEE80211_HT_CAP_GRN_FLD |
7619             IEEE80211_HT_CAP_SGI_20 |
7620             IEEE80211_HT_CAP_SGI_40;
7621
7622         if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) >= 2)
7623                 spec->ht.cap |= IEEE80211_HT_CAP_TX_STBC;
7624
7625         spec->ht.cap |=
7626             rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) <<
7627                 IEEE80211_HT_CAP_RX_STBC_SHIFT;
7628
7629         spec->ht.ampdu_factor = 3;
7630         spec->ht.ampdu_density = 4;
7631         spec->ht.mcs.tx_params =
7632             IEEE80211_HT_MCS_TX_DEFINED |
7633             IEEE80211_HT_MCS_TX_RX_DIFF |
7634             ((rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) - 1) <<
7635                 IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT);
7636
7637         switch (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH)) {
7638         case 3:
7639                 spec->ht.mcs.rx_mask[2] = 0xff;
7640         case 2:
7641                 spec->ht.mcs.rx_mask[1] = 0xff;
7642         case 1:
7643                 spec->ht.mcs.rx_mask[0] = 0xff;
7644                 spec->ht.mcs.rx_mask[4] = 0x1; /* MCS32 */
7645                 break;
7646         }
7647
7648         /*
7649          * Create channel information array
7650          */
7651         info = kcalloc(spec->num_channels, sizeof(*info), GFP_KERNEL);
7652         if (!info)
7653                 return -ENOMEM;
7654
7655         spec->channels_info = info;
7656
7657         default_power1 = rt2800_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG1);
7658         default_power2 = rt2800_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG2);
7659
7660         if (rt2x00dev->default_ant.tx_chain_num > 2)
7661                 default_power3 = rt2800_eeprom_addr(rt2x00dev,
7662                                                     EEPROM_EXT_TXPOWER_BG3);
7663         else
7664                 default_power3 = NULL;
7665
7666         for (i = 0; i < 14; i++) {
7667                 info[i].default_power1 = default_power1[i];
7668                 info[i].default_power2 = default_power2[i];
7669                 if (default_power3)
7670                         info[i].default_power3 = default_power3[i];
7671         }
7672
7673         if (spec->num_channels > 14) {
7674                 default_power1 = rt2800_eeprom_addr(rt2x00dev,
7675                                                     EEPROM_TXPOWER_A1);
7676                 default_power2 = rt2800_eeprom_addr(rt2x00dev,
7677                                                     EEPROM_TXPOWER_A2);
7678
7679                 if (rt2x00dev->default_ant.tx_chain_num > 2)
7680                         default_power3 =
7681                                 rt2800_eeprom_addr(rt2x00dev,
7682                                                    EEPROM_EXT_TXPOWER_A3);
7683                 else
7684                         default_power3 = NULL;
7685
7686                 for (i = 14; i < spec->num_channels; i++) {
7687                         info[i].default_power1 = default_power1[i - 14];
7688                         info[i].default_power2 = default_power2[i - 14];
7689                         if (default_power3)
7690                                 info[i].default_power3 = default_power3[i - 14];
7691                 }
7692         }
7693
7694         switch (rt2x00dev->chip.rf) {
7695         case RF2020:
7696         case RF3020:
7697         case RF3021:
7698         case RF3022:
7699         case RF3320:
7700         case RF3052:
7701         case RF3053:
7702         case RF3070:
7703         case RF3290:
7704         case RF5360:
7705         case RF5370:
7706         case RF5372:
7707         case RF5390:
7708         case RF5392:
7709                 __set_bit(CAPABILITY_VCO_RECALIBRATION, &rt2x00dev->cap_flags);
7710                 break;
7711         }
7712
7713         return 0;
7714 }
7715
7716 static int rt2800_probe_rt(struct rt2x00_dev *rt2x00dev)
7717 {
7718         u32 reg;
7719         u32 rt;
7720         u32 rev;
7721
7722         if (rt2x00_rt(rt2x00dev, RT3290))
7723                 rt2800_register_read(rt2x00dev, MAC_CSR0_3290, &reg);
7724         else
7725                 rt2800_register_read(rt2x00dev, MAC_CSR0, &reg);
7726
7727         rt = rt2x00_get_field32(reg, MAC_CSR0_CHIPSET);
7728         rev = rt2x00_get_field32(reg, MAC_CSR0_REVISION);
7729
7730         switch (rt) {
7731         case RT2860:
7732         case RT2872:
7733         case RT2883:
7734         case RT3070:
7735         case RT3071:
7736         case RT3090:
7737         case RT3290:
7738         case RT3352:
7739         case RT3390:
7740         case RT3572:
7741         case RT3593:
7742         case RT5390:
7743         case RT5392:
7744         case RT5592:
7745                 break;
7746         default:
7747                 rt2x00_err(rt2x00dev, "Invalid RT chipset 0x%04x, rev %04x detected\n",
7748                            rt, rev);
7749                 return -ENODEV;
7750         }
7751
7752         rt2x00_set_rt(rt2x00dev, rt, rev);
7753
7754         return 0;
7755 }
7756
7757 int rt2800_probe_hw(struct rt2x00_dev *rt2x00dev)
7758 {
7759         int retval;
7760         u32 reg;
7761
7762         retval = rt2800_probe_rt(rt2x00dev);
7763         if (retval)
7764                 return retval;
7765
7766         /*
7767          * Allocate eeprom data.
7768          */
7769         retval = rt2800_validate_eeprom(rt2x00dev);
7770         if (retval)
7771                 return retval;
7772
7773         retval = rt2800_init_eeprom(rt2x00dev);
7774         if (retval)
7775                 return retval;
7776
7777         /*
7778          * Enable rfkill polling by setting GPIO direction of the
7779          * rfkill switch GPIO pin correctly.
7780          */
7781         rt2800_register_read(rt2x00dev, GPIO_CTRL, &reg);
7782         rt2x00_set_field32(&reg, GPIO_CTRL_DIR2, 1);
7783         rt2800_register_write(rt2x00dev, GPIO_CTRL, reg);
7784
7785         /*
7786          * Initialize hw specifications.
7787          */
7788         retval = rt2800_probe_hw_mode(rt2x00dev);
7789         if (retval)
7790                 return retval;
7791
7792         /*
7793          * Set device capabilities.
7794          */
7795         __set_bit(CAPABILITY_CONTROL_FILTERS, &rt2x00dev->cap_flags);
7796         __set_bit(CAPABILITY_CONTROL_FILTER_PSPOLL, &rt2x00dev->cap_flags);
7797         if (!rt2x00_is_usb(rt2x00dev))
7798                 __set_bit(CAPABILITY_PRE_TBTT_INTERRUPT, &rt2x00dev->cap_flags);
7799
7800         /*
7801          * Set device requirements.
7802          */
7803         if (!rt2x00_is_soc(rt2x00dev))
7804                 __set_bit(REQUIRE_FIRMWARE, &rt2x00dev->cap_flags);
7805         __set_bit(REQUIRE_L2PAD, &rt2x00dev->cap_flags);
7806         __set_bit(REQUIRE_TXSTATUS_FIFO, &rt2x00dev->cap_flags);
7807         if (!rt2800_hwcrypt_disabled(rt2x00dev))
7808                 __set_bit(CAPABILITY_HW_CRYPTO, &rt2x00dev->cap_flags);
7809         __set_bit(CAPABILITY_LINK_TUNING, &rt2x00dev->cap_flags);
7810         __set_bit(REQUIRE_HT_TX_DESC, &rt2x00dev->cap_flags);
7811         if (rt2x00_is_usb(rt2x00dev))
7812                 __set_bit(REQUIRE_PS_AUTOWAKE, &rt2x00dev->cap_flags);
7813         else {
7814                 __set_bit(REQUIRE_DMA, &rt2x00dev->cap_flags);
7815                 __set_bit(REQUIRE_TASKLET_CONTEXT, &rt2x00dev->cap_flags);
7816         }
7817
7818         /*
7819          * Set the rssi offset.
7820          */
7821         rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
7822
7823         return 0;
7824 }
7825 EXPORT_SYMBOL_GPL(rt2800_probe_hw);
7826
7827 /*
7828  * IEEE80211 stack callback functions.
7829  */
7830 void rt2800_get_tkip_seq(struct ieee80211_hw *hw, u8 hw_key_idx, u32 *iv32,
7831                          u16 *iv16)
7832 {
7833         struct rt2x00_dev *rt2x00dev = hw->priv;
7834         struct mac_iveiv_entry iveiv_entry;
7835         u32 offset;
7836
7837         offset = MAC_IVEIV_ENTRY(hw_key_idx);
7838         rt2800_register_multiread(rt2x00dev, offset,
7839                                       &iveiv_entry, sizeof(iveiv_entry));
7840
7841         memcpy(iv16, &iveiv_entry.iv[0], sizeof(*iv16));
7842         memcpy(iv32, &iveiv_entry.iv[4], sizeof(*iv32));
7843 }
7844 EXPORT_SYMBOL_GPL(rt2800_get_tkip_seq);
7845
7846 int rt2800_set_rts_threshold(struct ieee80211_hw *hw, u32 value)
7847 {
7848         struct rt2x00_dev *rt2x00dev = hw->priv;
7849         u32 reg;
7850         bool enabled = (value < IEEE80211_MAX_RTS_THRESHOLD);
7851
7852         rt2800_register_read(rt2x00dev, TX_RTS_CFG, &reg);
7853         rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_THRES, value);
7854         rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg);
7855
7856         rt2800_register_read(rt2x00dev, CCK_PROT_CFG, &reg);
7857         rt2x00_set_field32(&reg, CCK_PROT_CFG_RTS_TH_EN, enabled);
7858         rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg);
7859
7860         rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
7861         rt2x00_set_field32(&reg, OFDM_PROT_CFG_RTS_TH_EN, enabled);
7862         rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
7863
7864         rt2800_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
7865         rt2x00_set_field32(&reg, MM20_PROT_CFG_RTS_TH_EN, enabled);
7866         rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
7867
7868         rt2800_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
7869         rt2x00_set_field32(&reg, MM40_PROT_CFG_RTS_TH_EN, enabled);
7870         rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
7871
7872         rt2800_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
7873         rt2x00_set_field32(&reg, GF20_PROT_CFG_RTS_TH_EN, enabled);
7874         rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
7875
7876         rt2800_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
7877         rt2x00_set_field32(&reg, GF40_PROT_CFG_RTS_TH_EN, enabled);
7878         rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
7879
7880         return 0;
7881 }
7882 EXPORT_SYMBOL_GPL(rt2800_set_rts_threshold);
7883
7884 int rt2800_conf_tx(struct ieee80211_hw *hw,
7885                    struct ieee80211_vif *vif, u16 queue_idx,
7886                    const struct ieee80211_tx_queue_params *params)
7887 {
7888         struct rt2x00_dev *rt2x00dev = hw->priv;
7889         struct data_queue *queue;
7890         struct rt2x00_field32 field;
7891         int retval;
7892         u32 reg;
7893         u32 offset;
7894
7895         /*
7896          * First pass the configuration through rt2x00lib, that will
7897          * update the queue settings and validate the input. After that
7898          * we are free to update the registers based on the value
7899          * in the queue parameter.
7900          */
7901         retval = rt2x00mac_conf_tx(hw, vif, queue_idx, params);
7902         if (retval)
7903                 return retval;
7904
7905         /*
7906          * We only need to perform additional register initialization
7907          * for WMM queues/
7908          */
7909         if (queue_idx >= 4)
7910                 return 0;
7911
7912         queue = rt2x00queue_get_tx_queue(rt2x00dev, queue_idx);
7913
7914         /* Update WMM TXOP register */
7915         offset = WMM_TXOP0_CFG + (sizeof(u32) * (!!(queue_idx & 2)));
7916         field.bit_offset = (queue_idx & 1) * 16;
7917         field.bit_mask = 0xffff << field.bit_offset;
7918
7919         rt2800_register_read(rt2x00dev, offset, &reg);
7920         rt2x00_set_field32(&reg, field, queue->txop);
7921         rt2800_register_write(rt2x00dev, offset, reg);
7922
7923         /* Update WMM registers */
7924         field.bit_offset = queue_idx * 4;
7925         field.bit_mask = 0xf << field.bit_offset;
7926
7927         rt2800_register_read(rt2x00dev, WMM_AIFSN_CFG, &reg);
7928         rt2x00_set_field32(&reg, field, queue->aifs);
7929         rt2800_register_write(rt2x00dev, WMM_AIFSN_CFG, reg);
7930
7931         rt2800_register_read(rt2x00dev, WMM_CWMIN_CFG, &reg);
7932         rt2x00_set_field32(&reg, field, queue->cw_min);
7933         rt2800_register_write(rt2x00dev, WMM_CWMIN_CFG, reg);
7934
7935         rt2800_register_read(rt2x00dev, WMM_CWMAX_CFG, &reg);
7936         rt2x00_set_field32(&reg, field, queue->cw_max);
7937         rt2800_register_write(rt2x00dev, WMM_CWMAX_CFG, reg);
7938
7939         /* Update EDCA registers */
7940         offset = EDCA_AC0_CFG + (sizeof(u32) * queue_idx);
7941
7942         rt2800_register_read(rt2x00dev, offset, &reg);
7943         rt2x00_set_field32(&reg, EDCA_AC0_CFG_TX_OP, queue->txop);
7944         rt2x00_set_field32(&reg, EDCA_AC0_CFG_AIFSN, queue->aifs);
7945         rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMIN, queue->cw_min);
7946         rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMAX, queue->cw_max);
7947         rt2800_register_write(rt2x00dev, offset, reg);
7948
7949         return 0;
7950 }
7951 EXPORT_SYMBOL_GPL(rt2800_conf_tx);
7952
7953 u64 rt2800_get_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
7954 {
7955         struct rt2x00_dev *rt2x00dev = hw->priv;
7956         u64 tsf;
7957         u32 reg;
7958
7959         rt2800_register_read(rt2x00dev, TSF_TIMER_DW1, &reg);
7960         tsf = (u64) rt2x00_get_field32(reg, TSF_TIMER_DW1_HIGH_WORD) << 32;
7961         rt2800_register_read(rt2x00dev, TSF_TIMER_DW0, &reg);
7962         tsf |= rt2x00_get_field32(reg, TSF_TIMER_DW0_LOW_WORD);
7963
7964         return tsf;
7965 }
7966 EXPORT_SYMBOL_GPL(rt2800_get_tsf);
7967
7968 int rt2800_ampdu_action(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
7969                         enum ieee80211_ampdu_mlme_action action,
7970                         struct ieee80211_sta *sta, u16 tid, u16 *ssn,
7971                         u8 buf_size)
7972 {
7973         struct rt2x00_sta *sta_priv = (struct rt2x00_sta *)sta->drv_priv;
7974         int ret = 0;
7975
7976         /*
7977          * Don't allow aggregation for stations the hardware isn't aware
7978          * of because tx status reports for frames to an unknown station
7979          * always contain wcid=255 and thus we can't distinguish between
7980          * multiple stations which leads to unwanted situations when the
7981          * hw reorders frames due to aggregation.
7982          */
7983         if (sta_priv->wcid < 0)
7984                 return 1;
7985
7986         switch (action) {
7987         case IEEE80211_AMPDU_RX_START:
7988         case IEEE80211_AMPDU_RX_STOP:
7989                 /*
7990                  * The hw itself takes care of setting up BlockAck mechanisms.
7991                  * So, we only have to allow mac80211 to nagotiate a BlockAck
7992                  * agreement. Once that is done, the hw will BlockAck incoming
7993                  * AMPDUs without further setup.
7994                  */
7995                 break;
7996         case IEEE80211_AMPDU_TX_START:
7997                 ieee80211_start_tx_ba_cb_irqsafe(vif, sta->addr, tid);
7998                 break;
7999         case IEEE80211_AMPDU_TX_STOP_CONT:
8000         case IEEE80211_AMPDU_TX_STOP_FLUSH:
8001         case IEEE80211_AMPDU_TX_STOP_FLUSH_CONT:
8002                 ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid);
8003                 break;
8004         case IEEE80211_AMPDU_TX_OPERATIONAL:
8005                 break;
8006         default:
8007                 rt2x00_warn((struct rt2x00_dev *)hw->priv,
8008                             "Unknown AMPDU action\n");
8009         }
8010
8011         return ret;
8012 }
8013 EXPORT_SYMBOL_GPL(rt2800_ampdu_action);
8014
8015 int rt2800_get_survey(struct ieee80211_hw *hw, int idx,
8016                       struct survey_info *survey)
8017 {
8018         struct rt2x00_dev *rt2x00dev = hw->priv;
8019         struct ieee80211_conf *conf = &hw->conf;
8020         u32 idle, busy, busy_ext;
8021
8022         if (idx != 0)
8023                 return -ENOENT;
8024
8025         survey->channel = conf->chandef.chan;
8026
8027         rt2800_register_read(rt2x00dev, CH_IDLE_STA, &idle);
8028         rt2800_register_read(rt2x00dev, CH_BUSY_STA, &busy);
8029         rt2800_register_read(rt2x00dev, CH_BUSY_STA_SEC, &busy_ext);
8030
8031         if (idle || busy) {
8032                 survey->filled = SURVEY_INFO_CHANNEL_TIME |
8033                                  SURVEY_INFO_CHANNEL_TIME_BUSY |
8034                                  SURVEY_INFO_CHANNEL_TIME_EXT_BUSY;
8035
8036                 survey->channel_time = (idle + busy) / 1000;
8037                 survey->channel_time_busy = busy / 1000;
8038                 survey->channel_time_ext_busy = busy_ext / 1000;
8039         }
8040
8041         if (!(hw->conf.flags & IEEE80211_CONF_OFFCHANNEL))
8042                 survey->filled |= SURVEY_INFO_IN_USE;
8043
8044         return 0;
8045
8046 }
8047 EXPORT_SYMBOL_GPL(rt2800_get_survey);
8048
8049 MODULE_AUTHOR(DRV_PROJECT ", Bartlomiej Zolnierkiewicz");
8050 MODULE_VERSION(DRV_VERSION);
8051 MODULE_DESCRIPTION("Ralink RT2800 library");
8052 MODULE_LICENSE("GPL");