drivers/net/wireless/rt2x00/rt2800lib.c

   1 /*
   2         Copyright (C) 2010 Willow Garage <http://www.willowgarage.com>
   3         Copyright (C) 2010 Ivo van Doorn <IvDoorn@gmail.com>
   4         Copyright (C) 2009 Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>
   5         Copyright (C) 2009 Gertjan van Wingerde <gwingerde@gmail.com>
   6
   7         Based on the original rt2800pci.c and rt2800usb.c.
   8           Copyright (C) 2009 Alban Browaeys <prahal@yahoo.com>
   9           Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org>
  10           Copyright (C) 2009 Luis Correia <luis.f.correia@gmail.com>
  11           Copyright (C) 2009 Mattias Nissler <mattias.nissler@gmx.de>
  12           Copyright (C) 2009 Mark Asselstine <asselsm@gmail.com>
  13           Copyright (C) 2009 Xose Vazquez Perez <xose.vazquez@gmail.com>
  14           <http://rt2x00.serialmonkey.com>
  15
  16         This program is free software; you can redistribute it and/or modify
  17         it under the terms of the GNU General Public License as published by
  18         the Free Software Foundation; either version 2 of the License, or
  19         (at your option) any later version.
  20
  21         This program is distributed in the hope that it will be useful,
  22         but WITHOUT ANY WARRANTY; without even the implied warranty of
  23         MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  24         GNU General Public License for more details.
  25
  26         You should have received a copy of the GNU General Public License
  27         along with this program; if not, write to the
  28         Free Software Foundation, Inc.,
  29         59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  30  */
  31
  32 /*
  33         Module: rt2800lib
  34         Abstract: rt2800 generic device routines.
  35  */
  36
  37 #include <linux/crc-ccitt.h>
  38 #include <linux/kernel.h>
  39 #include <linux/module.h>
  40 #include <linux/slab.h>
  41
  42 #include "rt2x00.h"
  43 #include "rt2800lib.h"
  44 #include "rt2800.h"
  45
  46 /*
  47  * Register access.
  48  * All access to the CSR registers will go through the methods
  49  * rt2800_register_read and rt2800_register_write.
  50  * BBP and RF register require indirect register access,
  51  * and use the CSR registers BBPCSR and RFCSR to achieve this.
  52  * These indirect registers work with busy bits,
  53  * and we will try maximal REGISTER_BUSY_COUNT times to access
  54  * the register while taking a REGISTER_BUSY_DELAY us delay
  55  * between each attampt. When the busy bit is still set at that time,
  56  * the access attempt is considered to have failed,
  57  * and we will print an error.
  58  * The _lock versions must be used if you already hold the csr_mutex
  59  */
  60 #define WAIT_FOR_BBP(__dev, __reg) \
  61         rt2800_regbusy_read((__dev), BBP_CSR_CFG, BBP_CSR_CFG_BUSY, (__reg))
  62 #define WAIT_FOR_RFCSR(__dev, __reg) \
  63         rt2800_regbusy_read((__dev), RF_CSR_CFG, RF_CSR_CFG_BUSY, (__reg))
  64 #define WAIT_FOR_RF(__dev, __reg) \
  65         rt2800_regbusy_read((__dev), RF_CSR_CFG0, RF_CSR_CFG0_BUSY, (__reg))
  66 #define WAIT_FOR_MCU(__dev, __reg) \
  67         rt2800_regbusy_read((__dev), H2M_MAILBOX_CSR, \
  68                             H2M_MAILBOX_CSR_OWNER, (__reg))
  69
  70 static inline bool rt2800_is_305x_soc(struct rt2x00_dev *rt2x00dev)
  71 {
  72         /* check for rt2872 on SoC */
  73         if (!rt2x00_is_soc(rt2x00dev) ||
  74             !rt2x00_rt(rt2x00dev, RT2872))
  75                 return false;
  76
  77         /* we know for sure that these rf chipsets are used on rt305x boards */
  78         if (rt2x00_rf(rt2x00dev, RF3020) ||
  79             rt2x00_rf(rt2x00dev, RF3021) ||
  80             rt2x00_rf(rt2x00dev, RF3022))
  81                 return true;
  82
  83         NOTICE(rt2x00dev, "Unknown RF chipset on rt305x\n");
  84         return false;
  85 }
  86
  87 static void rt2800_bbp_write(struct rt2x00_dev *rt2x00dev,
  88                              const unsigned int word, const u8 value)
  89 {
  90         u32 reg;
  91
  92         mutex_lock(&rt2x00dev->csr_mutex);
  93
  94         /*
  95          * Wait until the BBP becomes available, afterwards we
  96          * can safely write the new data into the register.
  97          */
  98         if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
  99                 reg = 0;
 100                 rt2x00_set_field32(&reg, BBP_CSR_CFG_VALUE, value);
 101                 rt2x00_set_field32(&reg, BBP_CSR_CFG_REGNUM, word);
 102                 rt2x00_set_field32(&reg, BBP_CSR_CFG_BUSY, 1);
 103                 rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 0);
 104                 rt2x00_set_field32(&reg, BBP_CSR_CFG_BBP_RW_MODE, 1);
 105
 106                 rt2800_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg);
 107         }
 108
 109         mutex_unlock(&rt2x00dev->csr_mutex);
 110 }
 111
 112 static void rt2800_bbp_read(struct rt2x00_dev *rt2x00dev,
 113                             const unsigned int word, u8 *value)
 114 {
 115         u32 reg;
 116
 117         mutex_lock(&rt2x00dev->csr_mutex);
 118
 119         /*
 120          * Wait until the BBP becomes available, afterwards we
 121          * can safely write the read request into the register.
 122          * After the data has been written, we wait until hardware
 123          * returns the correct value, if at any time the register
 124          * doesn't become available in time, reg will be 0xffffffff
 125          * which means we return 0xff to the caller.
 126          */
 127         if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
 128                 reg = 0;
 129                 rt2x00_set_field32(&reg, BBP_CSR_CFG_REGNUM, word);
 130                 rt2x00_set_field32(&reg, BBP_CSR_CFG_BUSY, 1);
 131                 rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 1);
 132                 rt2x00_set_field32(&reg, BBP_CSR_CFG_BBP_RW_MODE, 1);
 133
 134                 rt2800_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg);
 135
 136                 WAIT_FOR_BBP(rt2x00dev, &reg);
 137         }
 138
 139         *value = rt2x00_get_field32(reg, BBP_CSR_CFG_VALUE);
 140
 141         mutex_unlock(&rt2x00dev->csr_mutex);
 142 }
 143
 144 static void rt2800_rfcsr_write(struct rt2x00_dev *rt2x00dev,
 145                                const unsigned int word, const u8 value)
 146 {
 147         u32 reg;
 148
 149         mutex_lock(&rt2x00dev->csr_mutex);
 150
 151         /*
 152          * Wait until the RFCSR becomes available, afterwards we
 153          * can safely write the new data into the register.
 154          */
 155         if (WAIT_FOR_RFCSR(rt2x00dev, &reg)) {
 156                 reg = 0;
 157                 rt2x00_set_field32(&reg, RF_CSR_CFG_DATA, value);
 158                 rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM, word);
 159                 rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE, 1);
 160                 rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY, 1);
 161
 162                 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
 163         }
 164
 165         mutex_unlock(&rt2x00dev->csr_mutex);
 166 }
 167
 168 static void rt2800_rfcsr_read(struct rt2x00_dev *rt2x00dev,
 169                               const unsigned int word, u8 *value)
 170 {
 171         u32 reg;
 172
 173         mutex_lock(&rt2x00dev->csr_mutex);
 174
 175         /*
 176          * Wait until the RFCSR becomes available, afterwards we
 177          * can safely write the read request into the register.
 178          * After the data has been written, we wait until hardware
 179          * returns the correct value, if at any time the register
 180          * doesn't become available in time, reg will be 0xffffffff
 181          * which means we return 0xff to the caller.
 182          */
 183         if (WAIT_FOR_RFCSR(rt2x00dev, &reg)) {
 184                 reg = 0;
 185                 rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM, word);
 186                 rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE, 0);
 187                 rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY, 1);
 188
 189                 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
 190
 191                 WAIT_FOR_RFCSR(rt2x00dev, &reg);
 192         }
 193
 194         *value = rt2x00_get_field32(reg, RF_CSR_CFG_DATA);
 195
 196         mutex_unlock(&rt2x00dev->csr_mutex);
 197 }
 198
 199 static void rt2800_rf_write(struct rt2x00_dev *rt2x00dev,
 200                             const unsigned int word, const u32 value)
 201 {
 202         u32 reg;
 203
 204         mutex_lock(&rt2x00dev->csr_mutex);
 205
 206         /*
 207          * Wait until the RF becomes available, afterwards we
 208          * can safely write the new data into the register.
 209          */
 210         if (WAIT_FOR_RF(rt2x00dev, &reg)) {
 211                 reg = 0;
 212                 rt2x00_set_field32(&reg, RF_CSR_CFG0_REG_VALUE_BW, value);
 213                 rt2x00_set_field32(&reg, RF_CSR_CFG0_STANDBYMODE, 0);
 214                 rt2x00_set_field32(&reg, RF_CSR_CFG0_SEL, 0);
 215                 rt2x00_set_field32(&reg, RF_CSR_CFG0_BUSY, 1);
 216
 217                 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG0, reg);
 218                 rt2x00_rf_write(rt2x00dev, word, value);
 219         }
 220
 221         mutex_unlock(&rt2x00dev->csr_mutex);
 222 }
 223
 224 void rt2800_mcu_request(struct rt2x00_dev *rt2x00dev,
 225                         const u8 command, const u8 token,
 226                         const u8 arg0, const u8 arg1)
 227 {
 228         u32 reg;
 229
 230         /*
 231          * SOC devices don't support MCU requests.
 232          */
 233         if (rt2x00_is_soc(rt2x00dev))
 234                 return;
 235
 236         mutex_lock(&rt2x00dev->csr_mutex);
 237
 238         /*
 239          * Wait until the MCU becomes available, afterwards we
 240          * can safely write the new data into the register.
 241          */
 242         if (WAIT_FOR_MCU(rt2x00dev, &reg)) {
 243                 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_OWNER, 1);
 244                 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_CMD_TOKEN, token);
 245                 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG0, arg0);
 246                 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG1, arg1);
 247                 rt2800_register_write_lock(rt2x00dev, H2M_MAILBOX_CSR, reg);
 248
 249                 reg = 0;
 250                 rt2x00_set_field32(&reg, HOST_CMD_CSR_HOST_COMMAND, command);
 251                 rt2800_register_write_lock(rt2x00dev, HOST_CMD_CSR, reg);
 252         }
 253
 254         mutex_unlock(&rt2x00dev->csr_mutex);
 255 }
 256 EXPORT_SYMBOL_GPL(rt2800_mcu_request);
 257
 258 int rt2800_wait_csr_ready(struct rt2x00_dev *rt2x00dev)
 259 {
 260         unsigned int i = 0;
 261         u32 reg;
 262
 263         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
 264                 rt2800_register_read(rt2x00dev, MAC_CSR0, &reg);
 265                 if (reg && reg != ~0)
 266                         return 0;
 267                 msleep(1);
 268         }
 269
 270         ERROR(rt2x00dev, "Unstable hardware.\n");
 271         return -EBUSY;
 272 }
 273 EXPORT_SYMBOL_GPL(rt2800_wait_csr_ready);
 274
 275 int rt2800_wait_wpdma_ready(struct rt2x00_dev *rt2x00dev)
 276 {
 277         unsigned int i;
 278         u32 reg;
 279
 280         /*
 281          * Some devices are really slow to respond here. Wait a whole second
 282          * before timing out.
 283          */
 284         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
 285                 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
 286                 if (!rt2x00_get_field32(reg, WPDMA_GLO_CFG_TX_DMA_BUSY) &&
 287                     !rt2x00_get_field32(reg, WPDMA_GLO_CFG_RX_DMA_BUSY))
 288                         return 0;
 289
 290                 msleep(10);
 291         }
 292
 293         ERROR(rt2x00dev, "WPDMA TX/RX busy, aborting.\n");
 294         return -EACCES;
 295 }
 296 EXPORT_SYMBOL_GPL(rt2800_wait_wpdma_ready);
 297
 298 static bool rt2800_check_firmware_crc(const u8 *data, const size_t len)
 299 {
 300         u16 fw_crc;
 301         u16 crc;
 302
 303         /*
 304          * The last 2 bytes in the firmware array are the crc checksum itself,
 305          * this means that we should never pass those 2 bytes to the crc
 306          * algorithm.
 307          */
 308         fw_crc = (data[len - 2] << 8 | data[len - 1]);
 309
 310         /*
 311          * Use the crc ccitt algorithm.
 312          * This will return the same value as the legacy driver which
 313          * used bit ordering reversion on the both the firmware bytes
 314          * before input input as well as on the final output.
 315          * Obviously using crc ccitt directly is much more efficient.
 316          */
 317         crc = crc_ccitt(~0, data, len - 2);
 318
 319         /*
 320          * There is a small difference between the crc-itu-t + bitrev and
 321          * the crc-ccitt crc calculation. In the latter method the 2 bytes
 322          * will be swapped, use swab16 to convert the crc to the correct
 323          * value.
 324          */
 325         crc = swab16(crc);
 326
 327         return fw_crc == crc;
 328 }
 329
 330 int rt2800_check_firmware(struct rt2x00_dev *rt2x00dev,
 331                           const u8 *data, const size_t len)
 332 {
 333         size_t offset = 0;
 334         size_t fw_len;
 335         bool multiple;
 336
 337         /*
 338          * PCI(e) & SOC devices require firmware with a length
 339          * of 8kb. USB devices require firmware files with a length
 340          * of 4kb. Certain USB chipsets however require different firmware,
 341          * which Ralink only provides attached to the original firmware
 342          * file. Thus for USB devices, firmware files have a length
 343          * which is a multiple of 4kb.
 344          */
 345         if (rt2x00_is_usb(rt2x00dev)) {
 346                 fw_len = 4096;
 347                 multiple = true;
 348         } else {
 349                 fw_len = 8192;
 350                 multiple = true;
 351         }
 352
 353         /*
 354          * Validate the firmware length
 355          */
 356         if (len != fw_len && (!multiple || (len % fw_len) != 0))
 357                 return FW_BAD_LENGTH;
 358
 359         /*
 360          * Check if the chipset requires one of the upper parts
 361          * of the firmware.
 362          */
 363         if (rt2x00_is_usb(rt2x00dev) &&
 364             !rt2x00_rt(rt2x00dev, RT2860) &&
 365             !rt2x00_rt(rt2x00dev, RT2872) &&
 366             !rt2x00_rt(rt2x00dev, RT3070) &&
 367             ((len / fw_len) == 1))
 368                 return FW_BAD_VERSION;
 369
 370         /*
 371          * 8kb firmware files must be checked as if it were
 372          * 2 separate firmware files.
 373          */
 374         while (offset < len) {
 375                 if (!rt2800_check_firmware_crc(data + offset, fw_len))
 376                         return FW_BAD_CRC;
 377
 378                 offset += fw_len;
 379         }
 380
 381         return FW_OK;
 382 }
 383 EXPORT_SYMBOL_GPL(rt2800_check_firmware);
 384
 385 int rt2800_load_firmware(struct rt2x00_dev *rt2x00dev,
 386                          const u8 *data, const size_t len)
 387 {
 388         unsigned int i;
 389         u32 reg;
 390
 391         /*
 392          * If driver doesn't wake up firmware here,
 393          * rt2800_load_firmware will hang forever when interface is up again.
 394          */
 395         rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0x00000000);
 396
 397         /*
 398          * Wait for stable hardware.
 399          */
 400         if (rt2800_wait_csr_ready(rt2x00dev))
 401                 return -EBUSY;
 402
 403         if (rt2x00_is_pci(rt2x00dev))
 404                 rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000002);
 405
 406         /*
 407          * Disable DMA, will be reenabled later when enabling
 408          * the radio.
 409          */
 410         rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
 411         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
 412         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
 413         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
 414         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
 415         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
 416         rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
 417
 418         /*
 419          * Write firmware to the device.
 420          */
 421         rt2800_drv_write_firmware(rt2x00dev, data, len);
 422
 423         /*
 424          * Wait for device to stabilize.
 425          */
 426         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
 427                 rt2800_register_read(rt2x00dev, PBF_SYS_CTRL, &reg);
 428                 if (rt2x00_get_field32(reg, PBF_SYS_CTRL_READY))
 429                         break;
 430                 msleep(1);
 431         }
 432
 433         if (i == REGISTER_BUSY_COUNT) {
 434                 ERROR(rt2x00dev, "PBF system register not ready.\n");
 435                 return -EBUSY;
 436         }
 437
 438         /*
 439          * Initialize firmware.
 440          */
 441         rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
 442         rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
 443         msleep(1);
 444
 445         return 0;
 446 }
 447 EXPORT_SYMBOL_GPL(rt2800_load_firmware);
 448
 449 void rt2800_write_tx_data(struct queue_entry *entry,
 450                           struct txentry_desc *txdesc)
 451 {
 452         __le32 *txwi = rt2800_drv_get_txwi(entry);
 453         u32 word;
 454
 455         /*
 456          * Initialize TX Info descriptor
 457          */
 458         rt2x00_desc_read(txwi, 0, &word);
 459         rt2x00_set_field32(&word, TXWI_W0_FRAG,
 460                            test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
 461         rt2x00_set_field32(&word, TXWI_W0_MIMO_PS,
 462                            test_bit(ENTRY_TXD_HT_MIMO_PS, &txdesc->flags));
 463         rt2x00_set_field32(&word, TXWI_W0_CF_ACK, 0);
 464         rt2x00_set_field32(&word, TXWI_W0_TS,
 465                            test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
 466         rt2x00_set_field32(&word, TXWI_W0_AMPDU,
 467                            test_bit(ENTRY_TXD_HT_AMPDU, &txdesc->flags));
 468         rt2x00_set_field32(&word, TXWI_W0_MPDU_DENSITY, txdesc->mpdu_density);
 469         rt2x00_set_field32(&word, TXWI_W0_TX_OP, txdesc->txop);
 470         rt2x00_set_field32(&word, TXWI_W0_MCS, txdesc->mcs);
 471         rt2x00_set_field32(&word, TXWI_W0_BW,
 472                            test_bit(ENTRY_TXD_HT_BW_40, &txdesc->flags));
 473         rt2x00_set_field32(&word, TXWI_W0_SHORT_GI,
 474                            test_bit(ENTRY_TXD_HT_SHORT_GI, &txdesc->flags));
 475         rt2x00_set_field32(&word, TXWI_W0_STBC, txdesc->stbc);
 476         rt2x00_set_field32(&word, TXWI_W0_PHYMODE, txdesc->rate_mode);
 477         rt2x00_desc_write(txwi, 0, word);
 478
 479         rt2x00_desc_read(txwi, 1, &word);
 480         rt2x00_set_field32(&word, TXWI_W1_ACK,
 481                            test_bit(ENTRY_TXD_ACK, &txdesc->flags));
 482         rt2x00_set_field32(&word, TXWI_W1_NSEQ,
 483                            test_bit(ENTRY_TXD_GENERATE_SEQ, &txdesc->flags));
 484         rt2x00_set_field32(&word, TXWI_W1_BW_WIN_SIZE, txdesc->ba_size);
 485         rt2x00_set_field32(&word, TXWI_W1_WIRELESS_CLI_ID,
 486                            test_bit(ENTRY_TXD_ENCRYPT, &txdesc->flags) ?
 487                            txdesc->key_idx : 0xff);
 488         rt2x00_set_field32(&word, TXWI_W1_MPDU_TOTAL_BYTE_COUNT,
 489                            txdesc->length);
 490         rt2x00_set_field32(&word, TXWI_W1_PACKETID_QUEUE, entry->queue->qid);
 491         rt2x00_set_field32(&word, TXWI_W1_PACKETID_ENTRY, (entry->entry_idx % 3) + 1);
 492         rt2x00_desc_write(txwi, 1, word);
 493
 494         /*
 495          * Always write 0 to IV/EIV fields, hardware will insert the IV
 496          * from the IVEIV register when TXD_W3_WIV is set to 0.
 497          * When TXD_W3_WIV is set to 1 it will use the IV data
 498          * from the descriptor. The TXWI_W1_WIRELESS_CLI_ID indicates which
 499          * crypto entry in the registers should be used to encrypt the frame.
 500          */
 501         _rt2x00_desc_write(txwi, 2, 0 /* skbdesc->iv[0] */);
 502         _rt2x00_desc_write(txwi, 3, 0 /* skbdesc->iv[1] */);
 503 }
 504 EXPORT_SYMBOL_GPL(rt2800_write_tx_data);
 505
 506 static int rt2800_agc_to_rssi(struct rt2x00_dev *rt2x00dev, u32 rxwi_w2)
 507 {
 508         int rssi0 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI0);
 509         int rssi1 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI1);
 510         int rssi2 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI2);
 511         u16 eeprom;
 512         u8 offset0;
 513         u8 offset1;
 514         u8 offset2;
 515
 516         if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ) {
 517                 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG, &eeprom);
 518                 offset0 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG_OFFSET0);
 519                 offset1 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG_OFFSET1);
 520                 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &eeprom);
 521                 offset2 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG2_OFFSET2);
 522         } else {
 523                 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A, &eeprom);
 524                 offset0 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A_OFFSET0);
 525                 offset1 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A_OFFSET1);
 526                 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &eeprom);
 527                 offset2 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A2_OFFSET2);
 528         }
 529
 530         /*
 531          * Convert the value from the descriptor into the RSSI value
 532          * If the value in the descriptor is 0, it is considered invalid
 533          * and the default (extremely low) rssi value is assumed
 534          */
 535         rssi0 = (rssi0) ? (-12 - offset0 - rt2x00dev->lna_gain - rssi0) : -128;
 536         rssi1 = (rssi1) ? (-12 - offset1 - rt2x00dev->lna_gain - rssi1) : -128;
 537         rssi2 = (rssi2) ? (-12 - offset2 - rt2x00dev->lna_gain - rssi2) : -128;
 538
 539         /*
 540          * mac80211 only accepts a single RSSI value. Calculating the
 541          * average doesn't deliver a fair answer either since -60:-60 would
 542          * be considered equally good as -50:-70 while the second is the one
 543          * which gives less energy...
 544          */
 545         rssi0 = max(rssi0, rssi1);
 546         return max(rssi0, rssi2);
 547 }
 548
 549 void rt2800_process_rxwi(struct queue_entry *entry,
 550                          struct rxdone_entry_desc *rxdesc)
 551 {
 552         __le32 *rxwi = (__le32 *) entry->skb->data;
 553         u32 word;
 554
 555         rt2x00_desc_read(rxwi, 0, &word);
 556
 557         rxdesc->cipher = rt2x00_get_field32(word, RXWI_W0_UDF);
 558         rxdesc->size = rt2x00_get_field32(word, RXWI_W0_MPDU_TOTAL_BYTE_COUNT);
 559
 560         rt2x00_desc_read(rxwi, 1, &word);
 561
 562         if (rt2x00_get_field32(word, RXWI_W1_SHORT_GI))
 563                 rxdesc->flags |= RX_FLAG_SHORT_GI;
 564
 565         if (rt2x00_get_field32(word, RXWI_W1_BW))
 566                 rxdesc->flags |= RX_FLAG_40MHZ;
 567
 568         /*
 569          * Detect RX rate, always use MCS as signal type.
 570          */
 571         rxdesc->dev_flags |= RXDONE_SIGNAL_MCS;
 572         rxdesc->signal = rt2x00_get_field32(word, RXWI_W1_MCS);
 573         rxdesc->rate_mode = rt2x00_get_field32(word, RXWI_W1_PHYMODE);
 574
 575         /*
 576          * Mask of 0x8 bit to remove the short preamble flag.
 577          */
 578         if (rxdesc->rate_mode == RATE_MODE_CCK)
 579                 rxdesc->signal &= ~0x8;
 580
 581         rt2x00_desc_read(rxwi, 2, &word);
 582
 583         /*
 584          * Convert descriptor AGC value to RSSI value.
 585          */
 586         rxdesc->rssi = rt2800_agc_to_rssi(entry->queue->rt2x00dev, word);
 587
 588         /*
 589          * Remove RXWI descriptor from start of buffer.
 590          */
 591         skb_pull(entry->skb, RXWI_DESC_SIZE);
 592 }
 593 EXPORT_SYMBOL_GPL(rt2800_process_rxwi);
 594
 595 static bool rt2800_txdone_entry_check(struct queue_entry *entry, u32 reg)
 596 {
 597         __le32 *txwi;
 598         u32 word;
 599         int wcid, ack, pid;
 600         int tx_wcid, tx_ack, tx_pid;
 601
 602         wcid    = rt2x00_get_field32(reg, TX_STA_FIFO_WCID);
 603         ack     = rt2x00_get_field32(reg, TX_STA_FIFO_TX_ACK_REQUIRED);
 604         pid     = rt2x00_get_field32(reg, TX_STA_FIFO_PID_TYPE);
 605
 606         /*
 607          * This frames has returned with an IO error,
 608          * so the status report is not intended for this
 609          * frame.
 610          */
 611         if (test_bit(ENTRY_DATA_IO_FAILED, &entry->flags)) {
 612                 rt2x00lib_txdone_noinfo(entry, TXDONE_FAILURE);
 613                 return false;
 614         }
 615
 616         /*
 617          * Validate if this TX status report is intended for
 618          * this entry by comparing the WCID/ACK/PID fields.
 619          */
 620         txwi = rt2800_drv_get_txwi(entry);
 621
 622         rt2x00_desc_read(txwi, 1, &word);
 623         tx_wcid = rt2x00_get_field32(word, TXWI_W1_WIRELESS_CLI_ID);
 624         tx_ack  = rt2x00_get_field32(word, TXWI_W1_ACK);
 625         tx_pid  = rt2x00_get_field32(word, TXWI_W1_PACKETID);
 626
 627         if ((wcid != tx_wcid) || (ack != tx_ack) || (pid != tx_pid)) {
 628                 WARNING(entry->queue->rt2x00dev,
 629                         "TX status report missed for queue %d entry %d\n",
 630                 entry->queue->qid, entry->entry_idx);
 631                 rt2x00lib_txdone_noinfo(entry, TXDONE_UNKNOWN);
 632                 return false;
 633         }
 634
 635         return true;
 636 }
 637
 638 void rt2800_txdone_entry(struct queue_entry *entry, u32 status)
 639 {
 640         struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
 641         struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
 642         struct txdone_entry_desc txdesc;
 643         u32 word;
 644         u16 mcs, real_mcs;
 645         int aggr, ampdu;
 646         __le32 *txwi;
 647
 648         /*
 649          * Obtain the status about this packet.
 650          */
 651         txdesc.flags = 0;
 652         txwi = rt2800_drv_get_txwi(entry);
 653         rt2x00_desc_read(txwi, 0, &word);
 654
 655         mcs = rt2x00_get_field32(word, TXWI_W0_MCS);
 656         ampdu = rt2x00_get_field32(word, TXWI_W0_AMPDU);
 657
 658         real_mcs = rt2x00_get_field32(status, TX_STA_FIFO_MCS);
 659         aggr = rt2x00_get_field32(status, TX_STA_FIFO_TX_AGGRE);
 660
 661         /*
 662          * If a frame was meant to be sent as a single non-aggregated MPDU
 663          * but ended up in an aggregate the used tx rate doesn't correlate
 664          * with the one specified in the TXWI as the whole aggregate is sent
 665          * with the same rate.
 666          *
 667          * For example: two frames are sent to rt2x00, the first one sets
 668          * AMPDU=1 and requests MCS7 whereas the second frame sets AMDPU=0
 669          * and requests MCS15. If the hw aggregates both frames into one
 670          * AMDPU the tx status for both frames will contain MCS7 although
 671          * the frame was sent successfully.
 672          *
 673          * Hence, replace the requested rate with the real tx rate to not
 674          * confuse the rate control algortihm by providing clearly wrong
 675          * data.
 676          */
 677         if (aggr == 1 && ampdu == 0 && real_mcs != mcs) {
 678                 skbdesc->tx_rate_idx = real_mcs;
 679                 mcs = real_mcs;
 680         }
 681
 682         /*
 683          * Ralink has a retry mechanism using a global fallback
 684          * table. We setup this fallback table to try the immediate
 685          * lower rate for all rates. In the TX_STA_FIFO, the MCS field
 686          * always contains the MCS used for the last transmission, be
 687          * it successful or not.
 688          */
 689         if (rt2x00_get_field32(status, TX_STA_FIFO_TX_SUCCESS)) {
 690                 /*
 691                  * Transmission succeeded. The number of retries is
 692                  * mcs - real_mcs
 693                  */
 694                 __set_bit(TXDONE_SUCCESS, &txdesc.flags);
 695                 txdesc.retry = ((mcs > real_mcs) ? mcs - real_mcs : 0);
 696         } else {
 697                 /*
 698                  * Transmission failed. The number of retries is
 699                  * always 7 in this case (for a total number of 8
 700                  * frames sent).
 701                  */
 702                 __set_bit(TXDONE_FAILURE, &txdesc.flags);
 703                 txdesc.retry = rt2x00dev->long_retry;
 704         }
 705
 706         /*
 707          * the frame was retried at least once
 708          * -> hw used fallback rates
 709          */
 710         if (txdesc.retry)
 711                 __set_bit(TXDONE_FALLBACK, &txdesc.flags);
 712
 713         rt2x00lib_txdone(entry, &txdesc);
 714 }
 715 EXPORT_SYMBOL_GPL(rt2800_txdone_entry);
 716
 717 void rt2800_txdone(struct rt2x00_dev *rt2x00dev)
 718 {
 719         struct data_queue *queue;
 720         struct queue_entry *entry;
 721         u32 reg;
 722         u8 pid;
 723         int i;
 724
 725         /*
 726          * TX_STA_FIFO is a stack of X entries, hence read TX_STA_FIFO
 727          * at most X times and also stop processing once the TX_STA_FIFO_VALID
 728          * flag is not set anymore.
 729          *
 730          * The legacy drivers use X=TX_RING_SIZE but state in a comment
 731          * that the TX_STA_FIFO stack has a size of 16. We stick to our
 732          * tx ring size for now.
 733          */
 734         for (i = 0; i < rt2x00dev->ops->tx->entry_num; i++) {
 735                 rt2800_register_read(rt2x00dev, TX_STA_FIFO, &reg);
 736                 if (!rt2x00_get_field32(reg, TX_STA_FIFO_VALID))
 737                         break;
 738
 739                 /*
 740                  * Skip this entry when it contains an invalid
 741                  * queue identication number.
 742                  */
 743                 pid = rt2x00_get_field32(reg, TX_STA_FIFO_PID_QUEUE);
 744                 if (pid >= QID_RX)
 745                         continue;
 746
 747                 queue = rt2x00queue_get_queue(rt2x00dev, pid);
 748                 if (unlikely(!queue))
 749                         continue;
 750
 751                 /*
 752                  * Inside each queue, we process each entry in a chronological
 753                  * order. We first check that the queue is not empty.
 754                  */
 755                 entry = NULL;
 756                 while (!rt2x00queue_empty(queue)) {
 757                         entry = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
 758                         if (rt2800_txdone_entry_check(entry, reg))
 759                                 break;
 760                 }
 761
 762                 if (!entry || rt2x00queue_empty(queue))
 763                         break;
 764
 765                 rt2800_txdone_entry(entry, reg);
 766         }
 767 }
 768 EXPORT_SYMBOL_GPL(rt2800_txdone);
 769
 770 void rt2800_write_beacon(struct queue_entry *entry, struct txentry_desc *txdesc)
 771 {
 772         struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
 773         struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
 774         unsigned int beacon_base;
 775         unsigned int padding_len;
 776         u32 reg;
 777
 778         /*
 779          * Disable beaconing while we are reloading the beacon data,
 780          * otherwise we might be sending out invalid data.
 781          */
 782         rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
 783         rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
 784         rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
 785
 786         /*
 787          * Add space for the TXWI in front of the skb.
 788          */
 789         skb_push(entry->skb, TXWI_DESC_SIZE);
 790         memset(entry->skb, 0, TXWI_DESC_SIZE);
 791
 792         /*
 793          * Register descriptor details in skb frame descriptor.
 794          */
 795         skbdesc->flags |= SKBDESC_DESC_IN_SKB;
 796         skbdesc->desc = entry->skb->data;
 797         skbdesc->desc_len = TXWI_DESC_SIZE;
 798
 799         /*
 800          * Add the TXWI for the beacon to the skb.
 801          */
 802         rt2800_write_tx_data(entry, txdesc);
 803
 804         /*
 805          * Dump beacon to userspace through debugfs.
 806          */
 807         rt2x00debug_dump_frame(rt2x00dev, DUMP_FRAME_BEACON, entry->skb);
 808
 809         /*
 810          * Write entire beacon with TXWI and padding to register.
 811          */
 812         padding_len = roundup(entry->skb->len, 4) - entry->skb->len;
 813         skb_pad(entry->skb, padding_len);
 814         beacon_base = HW_BEACON_OFFSET(entry->entry_idx);
 815         rt2800_register_multiwrite(rt2x00dev, beacon_base, entry->skb->data,
 816                                    entry->skb->len + padding_len);
 817
 818         /*
 819          * Enable beaconing again.
 820          */
 821         rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 1);
 822         rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 1);
 823         rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 1);
 824         rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
 825
 826         /*
 827          * Clean up beacon skb.
 828          */
 829         dev_kfree_skb_any(entry->skb);
 830         entry->skb = NULL;
 831 }
 832 EXPORT_SYMBOL_GPL(rt2800_write_beacon);
 833
 834 static inline void rt2800_clear_beacon(struct rt2x00_dev *rt2x00dev,
 835                                        unsigned int beacon_base)
 836 {
 837         int i;
 838
 839         /*
 840          * For the Beacon base registers we only need to clear
 841          * the whole TXWI which (when set to 0) will invalidate
 842          * the entire beacon.
 843          */
 844         for (i = 0; i < TXWI_DESC_SIZE; i += sizeof(__le32))
 845                 rt2800_register_write(rt2x00dev, beacon_base + i, 0);
 846 }
 847
 848 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
 849 const struct rt2x00debug rt2800_rt2x00debug = {
 850         .owner  = THIS_MODULE,
 851         .csr    = {
 852                 .read           = rt2800_register_read,
 853                 .write          = rt2800_register_write,
 854                 .flags          = RT2X00DEBUGFS_OFFSET,
 855                 .word_base      = CSR_REG_BASE,
 856                 .word_size      = sizeof(u32),
 857                 .word_count     = CSR_REG_SIZE / sizeof(u32),
 858         },
 859         .eeprom = {
 860                 .read           = rt2x00_eeprom_read,
 861                 .write          = rt2x00_eeprom_write,
 862                 .word_base      = EEPROM_BASE,
 863                 .word_size      = sizeof(u16),
 864                 .word_count     = EEPROM_SIZE / sizeof(u16),
 865         },
 866         .bbp    = {
 867                 .read           = rt2800_bbp_read,
 868                 .write          = rt2800_bbp_write,
 869                 .word_base      = BBP_BASE,
 870                 .word_size      = sizeof(u8),
 871                 .word_count     = BBP_SIZE / sizeof(u8),
 872         },
 873         .rf     = {
 874                 .read           = rt2x00_rf_read,
 875                 .write          = rt2800_rf_write,
 876                 .word_base      = RF_BASE,
 877                 .word_size      = sizeof(u32),
 878                 .word_count     = RF_SIZE / sizeof(u32),
 879         },
 880 };
 881 EXPORT_SYMBOL_GPL(rt2800_rt2x00debug);
 882 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
 883
 884 int rt2800_rfkill_poll(struct rt2x00_dev *rt2x00dev)
 885 {
 886         u32 reg;
 887
 888         rt2800_register_read(rt2x00dev, GPIO_CTRL_CFG, &reg);
 889         return rt2x00_get_field32(reg, GPIO_CTRL_CFG_BIT2);
 890 }
 891 EXPORT_SYMBOL_GPL(rt2800_rfkill_poll);
 892
 893 #ifdef CONFIG_RT2X00_LIB_LEDS
 894 static void rt2800_brightness_set(struct led_classdev *led_cdev,
 895                                   enum led_brightness brightness)
 896 {
 897         struct rt2x00_led *led =
 898             container_of(led_cdev, struct rt2x00_led, led_dev);
 899         unsigned int enabled = brightness != LED_OFF;
 900         unsigned int bg_mode =
 901             (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_2GHZ);
 902         unsigned int polarity =
 903                 rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
 904                                    EEPROM_FREQ_LED_POLARITY);
 905         unsigned int ledmode =
 906                 rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
 907                                    EEPROM_FREQ_LED_MODE);
 908
 909         if (led->type == LED_TYPE_RADIO) {
 910                 rt2800_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
 911                                       enabled ? 0x20 : 0);
 912         } else if (led->type == LED_TYPE_ASSOC) {
 913                 rt2800_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
 914                                       enabled ? (bg_mode ? 0x60 : 0xa0) : 0x20);
 915         } else if (led->type == LED_TYPE_QUALITY) {
 916                 /*
 917                  * The brightness is divided into 6 levels (0 - 5),
 918                  * The specs tell us the following levels:
 919                  *      0, 1 ,3, 7, 15, 31
 920                  * to determine the level in a simple way we can simply
 921                  * work with bitshifting:
 922                  *      (1 << level) - 1
 923                  */
 924                 rt2800_mcu_request(led->rt2x00dev, MCU_LED_STRENGTH, 0xff,
 925                                       (1 << brightness / (LED_FULL / 6)) - 1,
 926                                       polarity);
 927         }
 928 }
 929
 930 static int rt2800_blink_set(struct led_classdev *led_cdev,
 931                             unsigned long *delay_on, unsigned long *delay_off)
 932 {
 933         struct rt2x00_led *led =
 934             container_of(led_cdev, struct rt2x00_led, led_dev);
 935         u32 reg;
 936
 937         rt2800_register_read(led->rt2x00dev, LED_CFG, &reg);
 938         rt2x00_set_field32(&reg, LED_CFG_ON_PERIOD, *delay_on);
 939         rt2x00_set_field32(&reg, LED_CFG_OFF_PERIOD, *delay_off);
 940         rt2800_register_write(led->rt2x00dev, LED_CFG, reg);
 941
 942         return 0;
 943 }
 944
 945 static void rt2800_init_led(struct rt2x00_dev *rt2x00dev,
 946                      struct rt2x00_led *led, enum led_type type)
 947 {
 948         led->rt2x00dev = rt2x00dev;
 949         led->type = type;
 950         led->led_dev.brightness_set = rt2800_brightness_set;
 951         led->led_dev.blink_set = rt2800_blink_set;
 952         led->flags = LED_INITIALIZED;
 953 }
 954 #endif /* CONFIG_RT2X00_LIB_LEDS */
 955
 956 /*
 957  * Configuration handlers.
 958  */
 959 static void rt2800_config_wcid_attr(struct rt2x00_dev *rt2x00dev,
 960                                     struct rt2x00lib_crypto *crypto,
 961                                     struct ieee80211_key_conf *key)
 962 {
 963         struct mac_wcid_entry wcid_entry;
 964         struct mac_iveiv_entry iveiv_entry;
 965         u32 offset;
 966         u32 reg;
 967
 968         offset = MAC_WCID_ATTR_ENTRY(key->hw_key_idx);
 969
 970         if (crypto->cmd == SET_KEY) {
 971                 rt2800_register_read(rt2x00dev, offset, &reg);
 972                 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_KEYTAB,
 973                                    !!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE));
 974                 /*
 975                  * Both the cipher as the BSS Idx numbers are split in a main
 976                  * value of 3 bits, and a extended field for adding one additional
 977                  * bit to the value.
 978                  */
 979                 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER,
 980                                    (crypto->cipher & 0x7));
 981                 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER_EXT,
 982                                    (crypto->cipher & 0x8) >> 3);
 983                 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_BSS_IDX,
 984                                    (crypto->bssidx & 0x7));
 985                 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_BSS_IDX_EXT,
 986                                    (crypto->bssidx & 0x8) >> 3);
 987                 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_RX_WIUDF, crypto->cipher);
 988                 rt2800_register_write(rt2x00dev, offset, reg);
 989         } else {
 990                 rt2800_register_write(rt2x00dev, offset, 0);
 991         }
 992
 993         offset = MAC_IVEIV_ENTRY(key->hw_key_idx);
 994
 995         memset(&iveiv_entry, 0, sizeof(iveiv_entry));
 996         if ((crypto->cipher == CIPHER_TKIP) ||
 997             (crypto->cipher == CIPHER_TKIP_NO_MIC) ||
 998             (crypto->cipher == CIPHER_AES))
 999                 iveiv_entry.iv[3] |= 0x20;
1000         iveiv_entry.iv[3] |= key->keyidx << 6;
1001         rt2800_register_multiwrite(rt2x00dev, offset,
1002                                       &iveiv_entry, sizeof(iveiv_entry));
1003
1004         offset = MAC_WCID_ENTRY(key->hw_key_idx);
1005
1006         memset(&wcid_entry, 0, sizeof(wcid_entry));
1007         if (crypto->cmd == SET_KEY)
1008                 memcpy(&wcid_entry, crypto->address, ETH_ALEN);
1009         rt2800_register_multiwrite(rt2x00dev, offset,
1010                                       &wcid_entry, sizeof(wcid_entry));
1011 }
1012
1013 int rt2800_config_shared_key(struct rt2x00_dev *rt2x00dev,
1014                              struct rt2x00lib_crypto *crypto,
1015                              struct ieee80211_key_conf *key)
1016 {
1017         struct hw_key_entry key_entry;
1018         struct rt2x00_field32 field;
1019         u32 offset;
1020         u32 reg;
1021
1022         if (crypto->cmd == SET_KEY) {
1023                 key->hw_key_idx = (4 * crypto->bssidx) + key->keyidx;
1024
1025                 memcpy(key_entry.key, crypto->key,
1026                        sizeof(key_entry.key));
1027                 memcpy(key_entry.tx_mic, crypto->tx_mic,
1028                        sizeof(key_entry.tx_mic));
1029                 memcpy(key_entry.rx_mic, crypto->rx_mic,
1030                        sizeof(key_entry.rx_mic));
1031
1032                 offset = SHARED_KEY_ENTRY(key->hw_key_idx);
1033                 rt2800_register_multiwrite(rt2x00dev, offset,
1034                                               &key_entry, sizeof(key_entry));
1035         }
1036
1037         /*
1038          * The cipher types are stored over multiple registers
1039          * starting with SHARED_KEY_MODE_BASE each word will have
1040          * 32 bits and contains the cipher types for 2 bssidx each.
1041          * Using the correct defines correctly will cause overhead,
1042          * so just calculate the correct offset.
1043          */
1044         field.bit_offset = 4 * (key->hw_key_idx % 8);
1045         field.bit_mask = 0x7 << field.bit_offset;
1046
1047         offset = SHARED_KEY_MODE_ENTRY(key->hw_key_idx / 8);
1048
1049         rt2800_register_read(rt2x00dev, offset, &reg);
1050         rt2x00_set_field32(&reg, field,
1051                            (crypto->cmd == SET_KEY) * crypto->cipher);
1052         rt2800_register_write(rt2x00dev, offset, reg);
1053
1054         /*
1055          * Update WCID information
1056          */
1057         rt2800_config_wcid_attr(rt2x00dev, crypto, key);
1058
1059         return 0;
1060 }
1061 EXPORT_SYMBOL_GPL(rt2800_config_shared_key);
1062
1063 int rt2800_config_pairwise_key(struct rt2x00_dev *rt2x00dev,
1064                                struct rt2x00lib_crypto *crypto,
1065                                struct ieee80211_key_conf *key)
1066 {
1067         struct hw_key_entry key_entry;
1068         u32 offset;
1069
1070         if (crypto->cmd == SET_KEY) {
1071                 /*
1072                  * 1 pairwise key is possible per AID, this means that the AID
1073                  * equals our hw_key_idx. Make sure the WCID starts _after_ the
1074                  * last possible shared key entry.
1075                  *
1076                  * Since parts of the pairwise key table might be shared with
1077                  * the beacon frame buffers 6 & 7 we should only write into the
1078                  * first 222 entries.
1079                  */
1080                 if (crypto->aid > (222 - 32))
1081                         return -ENOSPC;
1082
1083                 key->hw_key_idx = 32 + crypto->aid;
1084
1085                 memcpy(key_entry.key, crypto->key,
1086                        sizeof(key_entry.key));
1087                 memcpy(key_entry.tx_mic, crypto->tx_mic,
1088                        sizeof(key_entry.tx_mic));
1089                 memcpy(key_entry.rx_mic, crypto->rx_mic,
1090                        sizeof(key_entry.rx_mic));
1091
1092                 offset = PAIRWISE_KEY_ENTRY(key->hw_key_idx);
1093                 rt2800_register_multiwrite(rt2x00dev, offset,
1094                                               &key_entry, sizeof(key_entry));
1095         }
1096
1097         /*
1098          * Update WCID information
1099          */
1100         rt2800_config_wcid_attr(rt2x00dev, crypto, key);
1101
1102         return 0;
1103 }
1104 EXPORT_SYMBOL_GPL(rt2800_config_pairwise_key);
1105
1106 void rt2800_config_filter(struct rt2x00_dev *rt2x00dev,
1107                           const unsigned int filter_flags)
1108 {
1109         u32 reg;
1110
1111         /*
1112          * Start configuration steps.
1113          * Note that the version error will always be dropped
1114          * and broadcast frames will always be accepted since
1115          * there is no filter for it at this time.
1116          */
1117         rt2800_register_read(rt2x00dev, RX_FILTER_CFG, &reg);
1118         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CRC_ERROR,
1119                            !(filter_flags & FIF_FCSFAIL));
1120         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_PHY_ERROR,
1121                            !(filter_flags & FIF_PLCPFAIL));
1122         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_NOT_TO_ME,
1123                            !(filter_flags & FIF_PROMISC_IN_BSS));
1124         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_NOT_MY_BSSD, 0);
1125         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_VER_ERROR, 1);
1126         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_MULTICAST,
1127                            !(filter_flags & FIF_ALLMULTI));
1128         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BROADCAST, 0);
1129         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_DUPLICATE, 1);
1130         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CF_END_ACK,
1131                            !(filter_flags & FIF_CONTROL));
1132         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CF_END,
1133                            !(filter_flags & FIF_CONTROL));
1134         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_ACK,
1135                            !(filter_flags & FIF_CONTROL));
1136         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CTS,
1137                            !(filter_flags & FIF_CONTROL));
1138         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_RTS,
1139                            !(filter_flags & FIF_CONTROL));
1140         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_PSPOLL,
1141                            !(filter_flags & FIF_PSPOLL));
1142         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BA, 1);
1143         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BAR, 0);
1144         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CNTL,
1145                            !(filter_flags & FIF_CONTROL));
1146         rt2800_register_write(rt2x00dev, RX_FILTER_CFG, reg);
1147 }
1148 EXPORT_SYMBOL_GPL(rt2800_config_filter);
1149
1150 void rt2800_config_intf(struct rt2x00_dev *rt2x00dev, struct rt2x00_intf *intf,
1151                         struct rt2x00intf_conf *conf, const unsigned int flags)
1152 {
1153         u32 reg;
1154         bool update_bssid = false;
1155
1156         if (flags & CONFIG_UPDATE_TYPE) {
1157                 /*
1158                  * Clear current synchronisation setup.
1159                  */
1160                 rt2800_clear_beacon(rt2x00dev,
1161                                     HW_BEACON_OFFSET(intf->beacon->entry_idx));
1162                 /*
1163                  * Enable synchronisation.
1164                  */
1165                 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
1166                 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 1);
1167                 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, conf->sync);
1168                 rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE,
1169                                    (conf->sync == TSF_SYNC_ADHOC ||
1170                                     conf->sync == TSF_SYNC_AP_NONE));
1171                 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1172
1173                 /*
1174                  * Enable pre tbtt interrupt for beaconing modes
1175                  */
1176                 rt2800_register_read(rt2x00dev, INT_TIMER_EN, &reg);
1177                 rt2x00_set_field32(&reg, INT_TIMER_EN_PRE_TBTT_TIMER,
1178                                    (conf->sync == TSF_SYNC_AP_NONE));
1179                 rt2800_register_write(rt2x00dev, INT_TIMER_EN, reg);
1180
1181         }
1182
1183         if (flags & CONFIG_UPDATE_MAC) {
1184                 if (flags & CONFIG_UPDATE_TYPE &&
1185                     conf->sync == TSF_SYNC_AP_NONE) {
1186                         /*
1187                          * The BSSID register has to be set to our own mac
1188                          * address in AP mode.
1189                          */
1190                         memcpy(conf->bssid, conf->mac, sizeof(conf->mac));
1191                         update_bssid = true;
1192                 }
1193
1194                 if (!is_zero_ether_addr((const u8 *)conf->mac)) {
1195                         reg = le32_to_cpu(conf->mac[1]);
1196                         rt2x00_set_field32(&reg, MAC_ADDR_DW1_UNICAST_TO_ME_MASK, 0xff);
1197                         conf->mac[1] = cpu_to_le32(reg);
1198                 }
1199
1200                 rt2800_register_multiwrite(rt2x00dev, MAC_ADDR_DW0,
1201                                               conf->mac, sizeof(conf->mac));
1202         }
1203
1204         if ((flags & CONFIG_UPDATE_BSSID) || update_bssid) {
1205                 if (!is_zero_ether_addr((const u8 *)conf->bssid)) {
1206                         reg = le32_to_cpu(conf->bssid[1]);
1207                         rt2x00_set_field32(&reg, MAC_BSSID_DW1_BSS_ID_MASK, 3);
1208                         rt2x00_set_field32(&reg, MAC_BSSID_DW1_BSS_BCN_NUM, 7);
1209                         conf->bssid[1] = cpu_to_le32(reg);
1210                 }
1211
1212                 rt2800_register_multiwrite(rt2x00dev, MAC_BSSID_DW0,
1213                                               conf->bssid, sizeof(conf->bssid));
1214         }
1215 }
1216 EXPORT_SYMBOL_GPL(rt2800_config_intf);
1217
1218 static void rt2800_config_ht_opmode(struct rt2x00_dev *rt2x00dev,
1219                                     struct rt2x00lib_erp *erp)
1220 {
1221         bool any_sta_nongf = !!(erp->ht_opmode &
1222                                 IEEE80211_HT_OP_MODE_NON_GF_STA_PRSNT);
1223         u8 protection = erp->ht_opmode & IEEE80211_HT_OP_MODE_PROTECTION;
1224         u8 mm20_mode, mm40_mode, gf20_mode, gf40_mode;
1225         u16 mm20_rate, mm40_rate, gf20_rate, gf40_rate;
1226         u32 reg;
1227
1228         /* default protection rate for HT20: OFDM 24M */
1229         mm20_rate = gf20_rate = 0x4004;
1230
1231         /* default protection rate for HT40: duplicate OFDM 24M */
1232         mm40_rate = gf40_rate = 0x4084;
1233
1234         switch (protection) {
1235         case IEEE80211_HT_OP_MODE_PROTECTION_NONE:
1236                 /*
1237                  * All STAs in this BSS are HT20/40 but there might be
1238                  * STAs not supporting greenfield mode.
1239                  * => Disable protection for HT transmissions.
1240                  */
1241                 mm20_mode = mm40_mode = gf20_mode = gf40_mode = 0;
1242
1243                 break;
1244         case IEEE80211_HT_OP_MODE_PROTECTION_20MHZ:
1245                 /*
1246                  * All STAs in this BSS are HT20 or HT20/40 but there
1247                  * might be STAs not supporting greenfield mode.
1248                  * => Protect all HT40 transmissions.
1249                  */
1250                 mm20_mode = gf20_mode = 0;
1251                 mm40_mode = gf40_mode = 2;
1252
1253                 break;
1254         case IEEE80211_HT_OP_MODE_PROTECTION_NONMEMBER:
1255                 /*
1256                  * Nonmember protection:
1257                  * According to 802.11n we _should_ protect all
1258                  * HT transmissions (but we don't have to).
1259                  *
1260                  * But if cts_protection is enabled we _shall_ protect
1261                  * all HT transmissions using a CCK rate.
1262                  *
1263                  * And if any station is non GF we _shall_ protect
1264                  * GF transmissions.
1265                  *
1266                  * We decide to protect everything
1267                  * -> fall through to mixed mode.
1268                  */
1269         case IEEE80211_HT_OP_MODE_PROTECTION_NONHT_MIXED:
1270                 /*
1271                  * Legacy STAs are present
1272                  * => Protect all HT transmissions.
1273                  */
1274                 mm20_mode = mm40_mode = gf20_mode = gf40_mode = 2;
1275
1276                 /*
1277                  * If erp protection is needed we have to protect HT
1278                  * transmissions with CCK 11M long preamble.
1279                  */
1280                 if (erp->cts_protection) {
1281                         /* don't duplicate RTS/CTS in CCK mode */
1282                         mm20_rate = mm40_rate = 0x0003;
1283                         gf20_rate = gf40_rate = 0x0003;
1284                 }
1285                 break;
1286         };
1287
1288         /* check for STAs not supporting greenfield mode */
1289         if (any_sta_nongf)
1290                 gf20_mode = gf40_mode = 2;
1291
1292         /* Update HT protection config */
1293         rt2800_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
1294         rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_RATE, mm20_rate);
1295         rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_CTRL, mm20_mode);
1296         rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
1297
1298         rt2800_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
1299         rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_RATE, mm40_rate);
1300         rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_CTRL, mm40_mode);
1301         rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
1302
1303         rt2800_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
1304         rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_RATE, gf20_rate);
1305         rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_CTRL, gf20_mode);
1306         rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
1307
1308         rt2800_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
1309         rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_RATE, gf40_rate);
1310         rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_CTRL, gf40_mode);
1311         rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
1312 }
1313
1314 void rt2800_config_erp(struct rt2x00_dev *rt2x00dev, struct rt2x00lib_erp *erp,
1315                        u32 changed)
1316 {
1317         u32 reg;
1318
1319         if (changed & BSS_CHANGED_ERP_PREAMBLE) {
1320                 rt2800_register_read(rt2x00dev, AUTO_RSP_CFG, &reg);
1321                 rt2x00_set_field32(&reg, AUTO_RSP_CFG_BAC_ACK_POLICY,
1322                                    !!erp->short_preamble);
1323                 rt2x00_set_field32(&reg, AUTO_RSP_CFG_AR_PREAMBLE,
1324                                    !!erp->short_preamble);
1325                 rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
1326         }
1327
1328         if (changed & BSS_CHANGED_ERP_CTS_PROT) {
1329                 rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
1330                 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL,
1331                                    erp->cts_protection ? 2 : 0);
1332                 rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
1333         }
1334
1335         if (changed & BSS_CHANGED_BASIC_RATES) {
1336                 rt2800_register_write(rt2x00dev, LEGACY_BASIC_RATE,
1337                                          erp->basic_rates);
1338                 rt2800_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
1339         }
1340
1341         if (changed & BSS_CHANGED_ERP_SLOT) {
1342                 rt2800_register_read(rt2x00dev, BKOFF_SLOT_CFG, &reg);
1343                 rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_SLOT_TIME,
1344                                    erp->slot_time);
1345                 rt2800_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg);
1346
1347                 rt2800_register_read(rt2x00dev, XIFS_TIME_CFG, &reg);
1348                 rt2x00_set_field32(&reg, XIFS_TIME_CFG_EIFS, erp->eifs);
1349                 rt2800_register_write(rt2x00dev, XIFS_TIME_CFG, reg);
1350         }
1351
1352         if (changed & BSS_CHANGED_BEACON_INT) {
1353                 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
1354                 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL,
1355                                    erp->beacon_int * 16);
1356                 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1357         }
1358
1359         if (changed & BSS_CHANGED_HT)
1360                 rt2800_config_ht_opmode(rt2x00dev, erp);
1361 }
1362 EXPORT_SYMBOL_GPL(rt2800_config_erp);
1363
1364 void rt2800_config_ant(struct rt2x00_dev *rt2x00dev, struct antenna_setup *ant)
1365 {
1366         u8 r1;
1367         u8 r3;
1368
1369         rt2800_bbp_read(rt2x00dev, 1, &r1);
1370         rt2800_bbp_read(rt2x00dev, 3, &r3);
1371
1372         /*
1373          * Configure the TX antenna.
1374          */
1375         switch ((int)ant->tx) {
1376         case 1:
1377                 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 0);
1378                 break;
1379         case 2:
1380                 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 2);
1381                 break;
1382         case 3:
1383                 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 0);
1384                 break;
1385         }
1386
1387         /*
1388          * Configure the RX antenna.
1389          */
1390         switch ((int)ant->rx) {
1391         case 1:
1392                 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 0);
1393                 break;
1394         case 2:
1395                 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 1);
1396                 break;
1397         case 3:
1398                 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 2);
1399                 break;
1400         }
1401
1402         rt2800_bbp_write(rt2x00dev, 3, r3);
1403         rt2800_bbp_write(rt2x00dev, 1, r1);
1404 }
1405 EXPORT_SYMBOL_GPL(rt2800_config_ant);
1406
1407 static void rt2800_config_lna_gain(struct rt2x00_dev *rt2x00dev,
1408                                    struct rt2x00lib_conf *libconf)
1409 {
1410         u16 eeprom;
1411         short lna_gain;
1412
1413         if (libconf->rf.channel <= 14) {
1414                 rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom);
1415                 lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_BG);
1416         } else if (libconf->rf.channel <= 64) {
1417                 rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom);
1418                 lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_A0);
1419         } else if (libconf->rf.channel <= 128) {
1420                 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &eeprom);
1421                 lna_gain = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG2_LNA_A1);
1422         } else {
1423                 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &eeprom);
1424                 lna_gain = rt2x00_get_field16(eeprom, EEPROM_RSSI_A2_LNA_A2);
1425         }
1426
1427         rt2x00dev->lna_gain = lna_gain;
1428 }
1429
1430 static void rt2800_config_channel_rf2xxx(struct rt2x00_dev *rt2x00dev,
1431                                          struct ieee80211_conf *conf,
1432                                          struct rf_channel *rf,
1433                                          struct channel_info *info)
1434 {
1435         rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset);
1436
1437         if (rt2x00dev->default_ant.tx == 1)
1438                 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_TX1, 1);
1439
1440         if (rt2x00dev->default_ant.rx == 1) {
1441                 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX1, 1);
1442                 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
1443         } else if (rt2x00dev->default_ant.rx == 2)
1444                 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
1445
1446         if (rf->channel > 14) {
1447                 /*
1448                  * When TX power is below 0, we should increase it by 7 to
1449                  * make it a positive value (Minumum value is -7).
1450                  * However this means that values between 0 and 7 have
1451                  * double meaning, and we should set a 7DBm boost flag.
1452                  */
1453                 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A_7DBM_BOOST,
1454                                    (info->default_power1 >= 0));
1455
1456                 if (info->default_power1 < 0)
1457                         info->default_power1 += 7;
1458
1459                 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A, info->default_power1);
1460
1461                 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A_7DBM_BOOST,
1462                                    (info->default_power2 >= 0));
1463
1464                 if (info->default_power2 < 0)
1465                         info->default_power2 += 7;
1466
1467                 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A, info->default_power2);
1468         } else {
1469                 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_G, info->default_power1);
1470                 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_G, info->default_power2);
1471         }
1472
1473         rt2x00_set_field32(&rf->rf4, RF4_HT40, conf_is_ht40(conf));
1474
1475         rt2800_rf_write(rt2x00dev, 1, rf->rf1);
1476         rt2800_rf_write(rt2x00dev, 2, rf->rf2);
1477         rt2800_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
1478         rt2800_rf_write(rt2x00dev, 4, rf->rf4);
1479
1480         udelay(200);
1481
1482         rt2800_rf_write(rt2x00dev, 1, rf->rf1);
1483         rt2800_rf_write(rt2x00dev, 2, rf->rf2);
1484         rt2800_rf_write(rt2x00dev, 3, rf->rf3 | 0x00000004);
1485         rt2800_rf_write(rt2x00dev, 4, rf->rf4);
1486
1487         udelay(200);
1488
1489         rt2800_rf_write(rt2x00dev, 1, rf->rf1);
1490         rt2800_rf_write(rt2x00dev, 2, rf->rf2);
1491         rt2800_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
1492         rt2800_rf_write(rt2x00dev, 4, rf->rf4);
1493 }
1494
1495 static void rt2800_config_channel_rf3xxx(struct rt2x00_dev *rt2x00dev,
1496                                          struct ieee80211_conf *conf,
1497                                          struct rf_channel *rf,
1498                                          struct channel_info *info)
1499 {
1500         u8 rfcsr;
1501
1502         rt2800_rfcsr_write(rt2x00dev, 2, rf->rf1);
1503         rt2800_rfcsr_write(rt2x00dev, 3, rf->rf3);
1504
1505         rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
1506         rt2x00_set_field8(&rfcsr, RFCSR6_R1, rf->rf2);
1507         rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
1508
1509         rt2800_rfcsr_read(rt2x00dev, 12, &rfcsr);
1510         rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER, info->default_power1);
1511         rt2800_rfcsr_write(rt2x00dev, 12, rfcsr);
1512
1513         rt2800_rfcsr_read(rt2x00dev, 13, &rfcsr);
1514         rt2x00_set_field8(&rfcsr, RFCSR13_TX_POWER, info->default_power2);
1515         rt2800_rfcsr_write(rt2x00dev, 13, rfcsr);
1516
1517         rt2800_rfcsr_read(rt2x00dev, 23, &rfcsr);
1518         rt2x00_set_field8(&rfcsr, RFCSR23_FREQ_OFFSET, rt2x00dev->freq_offset);
1519         rt2800_rfcsr_write(rt2x00dev, 23, rfcsr);
1520
1521         rt2800_rfcsr_write(rt2x00dev, 24,
1522                               rt2x00dev->calibration[conf_is_ht40(conf)]);
1523
1524         rt2800_rfcsr_read(rt2x00dev, 7, &rfcsr);
1525         rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1);
1526         rt2800_rfcsr_write(rt2x00dev, 7, rfcsr);
1527 }
1528
1529 static void rt2800_config_channel(struct rt2x00_dev *rt2x00dev,
1530                                   struct ieee80211_conf *conf,
1531                                   struct rf_channel *rf,
1532                                   struct channel_info *info)
1533 {
1534         u32 reg;
1535         unsigned int tx_pin;
1536         u8 bbp;
1537
1538         if (rf->channel <= 14) {
1539                 info->default_power1 = TXPOWER_G_TO_DEV(info->default_power1);
1540                 info->default_power2 = TXPOWER_G_TO_DEV(info->default_power2);
1541         } else {
1542                 info->default_power1 = TXPOWER_A_TO_DEV(info->default_power1);
1543                 info->default_power2 = TXPOWER_A_TO_DEV(info->default_power2);
1544         }
1545
1546         if (rt2x00_rf(rt2x00dev, RF2020) ||
1547             rt2x00_rf(rt2x00dev, RF3020) ||
1548             rt2x00_rf(rt2x00dev, RF3021) ||
1549             rt2x00_rf(rt2x00dev, RF3022) ||
1550             rt2x00_rf(rt2x00dev, RF3052) ||
1551             rt2x00_rf(rt2x00dev, RF3320))
1552                 rt2800_config_channel_rf3xxx(rt2x00dev, conf, rf, info);
1553         else
1554                 rt2800_config_channel_rf2xxx(rt2x00dev, conf, rf, info);
1555
1556         /*
1557          * Change BBP settings
1558          */
1559         rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain);
1560         rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain);
1561         rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain);
1562         rt2800_bbp_write(rt2x00dev, 86, 0);
1563
1564         if (rf->channel <= 14) {
1565                 if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags)) {
1566                         rt2800_bbp_write(rt2x00dev, 82, 0x62);
1567                         rt2800_bbp_write(rt2x00dev, 75, 0x46);
1568                 } else {
1569                         rt2800_bbp_write(rt2x00dev, 82, 0x84);
1570                         rt2800_bbp_write(rt2x00dev, 75, 0x50);
1571                 }
1572         } else {
1573                 rt2800_bbp_write(rt2x00dev, 82, 0xf2);
1574
1575                 if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags))
1576                         rt2800_bbp_write(rt2x00dev, 75, 0x46);
1577                 else
1578                         rt2800_bbp_write(rt2x00dev, 75, 0x50);
1579         }
1580
1581         rt2800_register_read(rt2x00dev, TX_BAND_CFG, &reg);
1582         rt2x00_set_field32(&reg, TX_BAND_CFG_HT40_MINUS, conf_is_ht40_minus(conf));
1583         rt2x00_set_field32(&reg, TX_BAND_CFG_A, rf->channel > 14);
1584         rt2x00_set_field32(&reg, TX_BAND_CFG_BG, rf->channel <= 14);
1585         rt2800_register_write(rt2x00dev, TX_BAND_CFG, reg);
1586
1587         tx_pin = 0;
1588
1589         /* Turn on unused PA or LNA when not using 1T or 1R */
1590         if (rt2x00dev->default_ant.tx != 1) {
1591                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A1_EN, 1);
1592                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G1_EN, 1);
1593         }
1594
1595         /* Turn on unused PA or LNA when not using 1T or 1R */
1596         if (rt2x00dev->default_ant.rx != 1) {
1597                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A1_EN, 1);
1598                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G1_EN, 1);
1599         }
1600
1601         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A0_EN, 1);
1602         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G0_EN, 1);
1603         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_RFTR_EN, 1);
1604         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_TRSW_EN, 1);
1605         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN, rf->channel <= 14);
1606         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A0_EN, rf->channel > 14);
1607
1608         rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin);
1609
1610         rt2800_bbp_read(rt2x00dev, 4, &bbp);
1611         rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * conf_is_ht40(conf));
1612         rt2800_bbp_write(rt2x00dev, 4, bbp);
1613
1614         rt2800_bbp_read(rt2x00dev, 3, &bbp);
1615         rt2x00_set_field8(&bbp, BBP3_HT40_MINUS, conf_is_ht40_minus(conf));
1616         rt2800_bbp_write(rt2x00dev, 3, bbp);
1617
1618         if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C)) {
1619                 if (conf_is_ht40(conf)) {
1620                         rt2800_bbp_write(rt2x00dev, 69, 0x1a);
1621                         rt2800_bbp_write(rt2x00dev, 70, 0x0a);
1622                         rt2800_bbp_write(rt2x00dev, 73, 0x16);
1623                 } else {
1624                         rt2800_bbp_write(rt2x00dev, 69, 0x16);
1625                         rt2800_bbp_write(rt2x00dev, 70, 0x08);
1626                         rt2800_bbp_write(rt2x00dev, 73, 0x11);
1627                 }
1628         }
1629
1630         msleep(1);
1631
1632         /*
1633          * Clear channel statistic counters
1634          */
1635         rt2800_register_read(rt2x00dev, CH_IDLE_STA, &reg);
1636         rt2800_register_read(rt2x00dev, CH_BUSY_STA, &reg);
1637         rt2800_register_read(rt2x00dev, CH_BUSY_STA_SEC, &reg);
1638 }
1639
1640 static void rt2800_config_txpower(struct rt2x00_dev *rt2x00dev,
1641                                   const int max_txpower)
1642 {
1643         u8 txpower;
1644         u8 max_value = (u8)max_txpower;
1645         u16 eeprom;
1646         int i;
1647         u32 reg;
1648         u8 r1;
1649         u32 offset;
1650
1651         /*
1652          * set to normal tx power mode: +/- 0dBm
1653          */
1654         rt2800_bbp_read(rt2x00dev, 1, &r1);
1655         rt2x00_set_field8(&r1, BBP1_TX_POWER, 0);
1656         rt2800_bbp_write(rt2x00dev, 1, r1);
1657
1658         /*
1659          * The eeprom contains the tx power values for each rate. These
1660          * values map to 100% tx power. Each 16bit word contains four tx
1661          * power values and the order is the same as used in the TX_PWR_CFG
1662          * registers.
1663          */
1664         offset = TX_PWR_CFG_0;
1665
1666         for (i = 0; i < EEPROM_TXPOWER_BYRATE_SIZE; i += 2) {
1667                 /* just to be safe */
1668                 if (offset > TX_PWR_CFG_4)
1669                         break;
1670
1671                 rt2800_register_read(rt2x00dev, offset, &reg);
1672
1673                 /* read the next four txpower values */
1674                 rt2x00_eeprom_read(rt2x00dev, EEPROM_TXPOWER_BYRATE + i,
1675                                    &eeprom);
1676
1677                 /* TX_PWR_CFG_0: 1MBS, TX_PWR_CFG_1: 24MBS,
1678                  * TX_PWR_CFG_2: MCS4, TX_PWR_CFG_3: MCS12,
1679                  * TX_PWR_CFG_4: unknown */
1680                 txpower = rt2x00_get_field16(eeprom,
1681                                              EEPROM_TXPOWER_BYRATE_RATE0);
1682                 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE0,
1683                                    min(txpower, max_value));
1684
1685                 /* TX_PWR_CFG_0: 2MBS, TX_PWR_CFG_1: 36MBS,
1686                  * TX_PWR_CFG_2: MCS5, TX_PWR_CFG_3: MCS13,
1687                  * TX_PWR_CFG_4: unknown */
1688                 txpower = rt2x00_get_field16(eeprom,
1689                                              EEPROM_TXPOWER_BYRATE_RATE1);
1690                 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE1,
1691                                    min(txpower, max_value));
1692
1693                 /* TX_PWR_CFG_0: 55MBS, TX_PWR_CFG_1: 48MBS,
1694                  * TX_PWR_CFG_2: MCS6,  TX_PWR_CFG_3: MCS14,
1695                  * TX_PWR_CFG_4: unknown */
1696                 txpower = rt2x00_get_field16(eeprom,
1697                                              EEPROM_TXPOWER_BYRATE_RATE2);
1698                 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE2,
1699                                    min(txpower, max_value));
1700
1701                 /* TX_PWR_CFG_0: 11MBS, TX_PWR_CFG_1: 54MBS,
1702                  * TX_PWR_CFG_2: MCS7,  TX_PWR_CFG_3: MCS15,
1703                  * TX_PWR_CFG_4: unknown */
1704                 txpower = rt2x00_get_field16(eeprom,
1705                                              EEPROM_TXPOWER_BYRATE_RATE3);
1706                 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE3,
1707                                    min(txpower, max_value));
1708
1709                 /* read the next four txpower values */
1710                 rt2x00_eeprom_read(rt2x00dev, EEPROM_TXPOWER_BYRATE + i + 1,
1711                                    &eeprom);
1712
1713                 /* TX_PWR_CFG_0: 6MBS, TX_PWR_CFG_1: MCS0,
1714                  * TX_PWR_CFG_2: MCS8, TX_PWR_CFG_3: unknown,
1715                  * TX_PWR_CFG_4: unknown */
1716                 txpower = rt2x00_get_field16(eeprom,
1717                                              EEPROM_TXPOWER_BYRATE_RATE0);
1718                 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE4,
1719                                    min(txpower, max_value));
1720
1721                 /* TX_PWR_CFG_0: 9MBS, TX_PWR_CFG_1: MCS1,
1722                  * TX_PWR_CFG_2: MCS9, TX_PWR_CFG_3: unknown,
1723                  * TX_PWR_CFG_4: unknown */
1724                 txpower = rt2x00_get_field16(eeprom,
1725                                              EEPROM_TXPOWER_BYRATE_RATE1);
1726                 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE5,
1727                                    min(txpower, max_value));
1728
1729                 /* TX_PWR_CFG_0: 12MBS, TX_PWR_CFG_1: MCS2,
1730                  * TX_PWR_CFG_2: MCS10, TX_PWR_CFG_3: unknown,
1731                  * TX_PWR_CFG_4: unknown */
1732                 txpower = rt2x00_get_field16(eeprom,
1733                                              EEPROM_TXPOWER_BYRATE_RATE2);
1734                 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE6,
1735                                    min(txpower, max_value));
1736
1737                 /* TX_PWR_CFG_0: 18MBS, TX_PWR_CFG_1: MCS3,
1738                  * TX_PWR_CFG_2: MCS11, TX_PWR_CFG_3: unknown,
1739                  * TX_PWR_CFG_4: unknown */
1740                 txpower = rt2x00_get_field16(eeprom,
1741                                              EEPROM_TXPOWER_BYRATE_RATE3);
1742                 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE7,
1743                                    min(txpower, max_value));
1744
1745                 rt2800_register_write(rt2x00dev, offset, reg);
1746
1747                 /* next TX_PWR_CFG register */
1748                 offset += 4;
1749         }
1750 }
1751
1752 static void rt2800_config_retry_limit(struct rt2x00_dev *rt2x00dev,
1753                                       struct rt2x00lib_conf *libconf)
1754 {
1755         u32 reg;
1756
1757         rt2800_register_read(rt2x00dev, TX_RTY_CFG, &reg);
1758         rt2x00_set_field32(&reg, TX_RTY_CFG_SHORT_RTY_LIMIT,
1759                            libconf->conf->short_frame_max_tx_count);
1760         rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_LIMIT,
1761                            libconf->conf->long_frame_max_tx_count);
1762         rt2800_register_write(rt2x00dev, TX_RTY_CFG, reg);
1763 }
1764
1765 static void rt2800_config_ps(struct rt2x00_dev *rt2x00dev,
1766                              struct rt2x00lib_conf *libconf)
1767 {
1768         enum dev_state state =
1769             (libconf->conf->flags & IEEE80211_CONF_PS) ?
1770                 STATE_SLEEP : STATE_AWAKE;
1771         u32 reg;
1772
1773         if (state == STATE_SLEEP) {
1774                 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0);
1775
1776                 rt2800_register_read(rt2x00dev, AUTOWAKEUP_CFG, &reg);
1777                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 5);
1778                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE,
1779                                    libconf->conf->listen_interval - 1);
1780                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTOWAKE, 1);
1781                 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg);
1782
1783                 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
1784         } else {
1785                 rt2800_register_read(rt2x00dev, AUTOWAKEUP_CFG, &reg);
1786                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 0);
1787                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE, 0);
1788                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTOWAKE, 0);
1789                 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg);
1790
1791                 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
1792         }
1793 }
1794
1795 void rt2800_config(struct rt2x00_dev *rt2x00dev,
1796                    struct rt2x00lib_conf *libconf,
1797                    const unsigned int flags)
1798 {
1799         /* Always recalculate LNA gain before changing configuration */
1800         rt2800_config_lna_gain(rt2x00dev, libconf);
1801
1802         if (flags & IEEE80211_CONF_CHANGE_CHANNEL)
1803                 rt2800_config_channel(rt2x00dev, libconf->conf,
1804                                       &libconf->rf, &libconf->channel);
1805         if (flags & IEEE80211_CONF_CHANGE_POWER)
1806                 rt2800_config_txpower(rt2x00dev, libconf->conf->power_level);
1807         if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
1808                 rt2800_config_retry_limit(rt2x00dev, libconf);
1809         if (flags & IEEE80211_CONF_CHANGE_PS)
1810                 rt2800_config_ps(rt2x00dev, libconf);
1811 }
1812 EXPORT_SYMBOL_GPL(rt2800_config);
1813
1814 /*
1815  * Link tuning
1816  */
1817 void rt2800_link_stats(struct rt2x00_dev *rt2x00dev, struct link_qual *qual)
1818 {
1819         u32 reg;
1820
1821         /*
1822          * Update FCS error count from register.
1823          */
1824         rt2800_register_read(rt2x00dev, RX_STA_CNT0, &reg);
1825         qual->rx_failed = rt2x00_get_field32(reg, RX_STA_CNT0_CRC_ERR);
1826 }
1827 EXPORT_SYMBOL_GPL(rt2800_link_stats);
1828
1829 static u8 rt2800_get_default_vgc(struct rt2x00_dev *rt2x00dev)
1830 {
1831         if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ) {
1832                 if (rt2x00_rt(rt2x00dev, RT3070) ||
1833                     rt2x00_rt(rt2x00dev, RT3071) ||
1834                     rt2x00_rt(rt2x00dev, RT3090) ||
1835                     rt2x00_rt(rt2x00dev, RT3390))
1836                         return 0x1c + (2 * rt2x00dev->lna_gain);
1837                 else
1838                         return 0x2e + rt2x00dev->lna_gain;
1839         }
1840
1841         if (!test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags))
1842                 return 0x32 + (rt2x00dev->lna_gain * 5) / 3;
1843         else
1844                 return 0x3a + (rt2x00dev->lna_gain * 5) / 3;
1845 }
1846
1847 static inline void rt2800_set_vgc(struct rt2x00_dev *rt2x00dev,
1848                                   struct link_qual *qual, u8 vgc_level)
1849 {
1850         if (qual->vgc_level != vgc_level) {
1851                 rt2800_bbp_write(rt2x00dev, 66, vgc_level);
1852                 qual->vgc_level = vgc_level;
1853                 qual->vgc_level_reg = vgc_level;
1854         }
1855 }
1856
1857 void rt2800_reset_tuner(struct rt2x00_dev *rt2x00dev, struct link_qual *qual)
1858 {
1859         rt2800_set_vgc(rt2x00dev, qual, rt2800_get_default_vgc(rt2x00dev));
1860 }
1861 EXPORT_SYMBOL_GPL(rt2800_reset_tuner);
1862
1863 void rt2800_link_tuner(struct rt2x00_dev *rt2x00dev, struct link_qual *qual,
1864                        const u32 count)
1865 {
1866         if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C))
1867                 return;
1868
1869         /*
1870          * When RSSI is better then -80 increase VGC level with 0x10
1871          */
1872         rt2800_set_vgc(rt2x00dev, qual,
1873                        rt2800_get_default_vgc(rt2x00dev) +
1874                        ((qual->rssi > -80) * 0x10));
1875 }
1876 EXPORT_SYMBOL_GPL(rt2800_link_tuner);
1877
1878 /*
1879  * Initialization functions.
1880  */
1881 static int rt2800_init_registers(struct rt2x00_dev *rt2x00dev)
1882 {
1883         u32 reg;
1884         u16 eeprom;
1885         unsigned int i;
1886         int ret;
1887
1888         rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
1889         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
1890         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
1891         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
1892         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
1893         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
1894         rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
1895
1896         ret = rt2800_drv_init_registers(rt2x00dev);
1897         if (ret)
1898                 return ret;
1899
1900         rt2800_register_read(rt2x00dev, BCN_OFFSET0, &reg);
1901         rt2x00_set_field32(&reg, BCN_OFFSET0_BCN0, 0xe0); /* 0x3800 */
1902         rt2x00_set_field32(&reg, BCN_OFFSET0_BCN1, 0xe8); /* 0x3a00 */
1903         rt2x00_set_field32(&reg, BCN_OFFSET0_BCN2, 0xf0); /* 0x3c00 */
1904         rt2x00_set_field32(&reg, BCN_OFFSET0_BCN3, 0xf8); /* 0x3e00 */
1905         rt2800_register_write(rt2x00dev, BCN_OFFSET0, reg);
1906
1907         rt2800_register_read(rt2x00dev, BCN_OFFSET1, &reg);
1908         rt2x00_set_field32(&reg, BCN_OFFSET1_BCN4, 0xc8); /* 0x3200 */
1909         rt2x00_set_field32(&reg, BCN_OFFSET1_BCN5, 0xd0); /* 0x3400 */
1910         rt2x00_set_field32(&reg, BCN_OFFSET1_BCN6, 0x77); /* 0x1dc0 */
1911         rt2x00_set_field32(&reg, BCN_OFFSET1_BCN7, 0x6f); /* 0x1bc0 */
1912         rt2800_register_write(rt2x00dev, BCN_OFFSET1, reg);
1913
1914         rt2800_register_write(rt2x00dev, LEGACY_BASIC_RATE, 0x0000013f);
1915         rt2800_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
1916
1917         rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000);
1918
1919         rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
1920         rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL, 1600);
1921         rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 0);
1922         rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, 0);
1923         rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 0);
1924         rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
1925         rt2x00_set_field32(&reg, BCN_TIME_CFG_TX_TIME_COMPENSATE, 0);
1926         rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1927
1928         rt2800_config_filter(rt2x00dev, FIF_ALLMULTI);
1929
1930         rt2800_register_read(rt2x00dev, BKOFF_SLOT_CFG, &reg);
1931         rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_SLOT_TIME, 9);
1932         rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_CC_DELAY_TIME, 2);
1933         rt2800_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg);
1934
1935         if (rt2x00_rt(rt2x00dev, RT3071) ||
1936             rt2x00_rt(rt2x00dev, RT3090) ||
1937             rt2x00_rt(rt2x00dev, RT3390)) {
1938                 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
1939                 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
1940                 if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
1941                     rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) ||
1942                     rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E)) {
1943                         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
1944                         if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_DAC_TEST))
1945                                 rt2800_register_write(rt2x00dev, TX_SW_CFG2,
1946                                                       0x0000002c);
1947                         else
1948                                 rt2800_register_write(rt2x00dev, TX_SW_CFG2,
1949                                                       0x0000000f);
1950                 } else {
1951                         rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
1952                 }
1953         } else if (rt2x00_rt(rt2x00dev, RT3070)) {
1954                 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
1955
1956                 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F)) {
1957                         rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
1958                         rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x0000002c);
1959                 } else {
1960                         rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
1961                         rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
1962                 }
1963         } else if (rt2800_is_305x_soc(rt2x00dev)) {
1964                 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
1965                 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
1966                 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x0000001f);
1967         } else {
1968                 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000000);
1969                 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
1970         }
1971
1972         rt2800_register_read(rt2x00dev, TX_LINK_CFG, &reg);
1973         rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB_LIFETIME, 32);
1974         rt2x00_set_field32(&reg, TX_LINK_CFG_MFB_ENABLE, 0);
1975         rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_UMFS_ENABLE, 0);
1976         rt2x00_set_field32(&reg, TX_LINK_CFG_TX_MRQ_EN, 0);
1977         rt2x00_set_field32(&reg, TX_LINK_CFG_TX_RDG_EN, 0);
1978         rt2x00_set_field32(&reg, TX_LINK_CFG_TX_CF_ACK_EN, 1);
1979         rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB, 0);
1980         rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFS, 0);
1981         rt2800_register_write(rt2x00dev, TX_LINK_CFG, reg);
1982
1983         rt2800_register_read(rt2x00dev, TX_TIMEOUT_CFG, &reg);
1984         rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_MPDU_LIFETIME, 9);
1985         rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_RX_ACK_TIMEOUT, 32);
1986         rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_TX_OP_TIMEOUT, 10);
1987         rt2800_register_write(rt2x00dev, TX_TIMEOUT_CFG, reg);
1988
1989         rt2800_register_read(rt2x00dev, MAX_LEN_CFG, &reg);
1990         rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_MPDU, AGGREGATION_SIZE);
1991         if (rt2x00_rt_rev_gte(rt2x00dev, RT2872, REV_RT2872E) ||
1992             rt2x00_rt(rt2x00dev, RT2883) ||
1993             rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070E))
1994                 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, 2);
1995         else
1996                 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, 1);
1997         rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_PSDU, 0);
1998         rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_MPDU, 0);
1999         rt2800_register_write(rt2x00dev, MAX_LEN_CFG, reg);
2000
2001         rt2800_register_read(rt2x00dev, LED_CFG, &reg);
2002         rt2x00_set_field32(&reg, LED_CFG_ON_PERIOD, 70);
2003         rt2x00_set_field32(&reg, LED_CFG_OFF_PERIOD, 30);
2004         rt2x00_set_field32(&reg, LED_CFG_SLOW_BLINK_PERIOD, 3);
2005         rt2x00_set_field32(&reg, LED_CFG_R_LED_MODE, 3);
2006         rt2x00_set_field32(&reg, LED_CFG_G_LED_MODE, 3);
2007         rt2x00_set_field32(&reg, LED_CFG_Y_LED_MODE, 3);
2008         rt2x00_set_field32(&reg, LED_CFG_LED_POLAR, 1);
2009         rt2800_register_write(rt2x00dev, LED_CFG, reg);
2010
2011         rt2800_register_write(rt2x00dev, PBF_MAX_PCNT, 0x1f3fbf9f);
2012
2013         rt2800_register_read(rt2x00dev, TX_RTY_CFG, &reg);
2014         rt2x00_set_field32(&reg, TX_RTY_CFG_SHORT_RTY_LIMIT, 15);
2015         rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_LIMIT, 31);
2016         rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_THRE, 2000);
2017         rt2x00_set_field32(&reg, TX_RTY_CFG_NON_AGG_RTY_MODE, 0);
2018         rt2x00_set_field32(&reg, TX_RTY_CFG_AGG_RTY_MODE, 0);
2019         rt2x00_set_field32(&reg, TX_RTY_CFG_TX_AUTO_FB_ENABLE, 1);
2020         rt2800_register_write(rt2x00dev, TX_RTY_CFG, reg);
2021
2022         rt2800_register_read(rt2x00dev, AUTO_RSP_CFG, &reg);
2023         rt2x00_set_field32(&reg, AUTO_RSP_CFG_AUTORESPONDER, 1);
2024         rt2x00_set_field32(&reg, AUTO_RSP_CFG_BAC_ACK_POLICY, 1);
2025         rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MMODE, 0);
2026         rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MREF, 0);
2027         rt2x00_set_field32(&reg, AUTO_RSP_CFG_AR_PREAMBLE, 1);
2028         rt2x00_set_field32(&reg, AUTO_RSP_CFG_DUAL_CTS_EN, 0);
2029         rt2x00_set_field32(&reg, AUTO_RSP_CFG_ACK_CTS_PSM_BIT, 0);
2030         rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
2031
2032         rt2800_register_read(rt2x00dev, CCK_PROT_CFG, &reg);
2033         rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_RATE, 3);
2034         rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_CTRL, 0);
2035         rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_NAV, 1);
2036         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_CCK, 1);
2037         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
2038         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM20, 1);
2039         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM40, 0);
2040         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF20, 1);
2041         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF40, 0);
2042         rt2x00_set_field32(&reg, CCK_PROT_CFG_RTS_TH_EN, 1);
2043         rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg);
2044
2045         rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
2046         rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_RATE, 3);
2047         rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL, 0);
2048         rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_NAV, 1);
2049         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_CCK, 1);
2050         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
2051         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM20, 1);
2052         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM40, 0);
2053         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF20, 1);
2054         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF40, 0);
2055         rt2x00_set_field32(&reg, OFDM_PROT_CFG_RTS_TH_EN, 1);
2056         rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
2057
2058         rt2800_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
2059         rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_RATE, 0x4004);
2060         rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_CTRL, 0);
2061         rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_NAV, 1);
2062         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_CCK, 1);
2063         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
2064         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
2065         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
2066         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
2067         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
2068         rt2x00_set_field32(&reg, MM20_PROT_CFG_RTS_TH_EN, 0);
2069         rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
2070
2071         rt2800_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
2072         rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_RATE, 0x4084);
2073         rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_CTRL, 0);
2074         rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_NAV, 1);
2075         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_CCK, 1);
2076         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
2077         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
2078         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
2079         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
2080         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
2081         rt2x00_set_field32(&reg, MM40_PROT_CFG_RTS_TH_EN, 0);
2082         rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
2083
2084         rt2800_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
2085         rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_RATE, 0x4004);
2086         rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_CTRL, 0);
2087         rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_NAV, 1);
2088         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_CCK, 1);
2089         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
2090         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
2091         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
2092         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
2093         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
2094         rt2x00_set_field32(&reg, GF20_PROT_CFG_RTS_TH_EN, 0);
2095         rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
2096
2097         rt2800_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
2098         rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_RATE, 0x4084);
2099         rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_CTRL, 0);
2100         rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_NAV, 1);
2101         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_CCK, 1);
2102         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
2103         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
2104         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
2105         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
2106         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
2107         rt2x00_set_field32(&reg, GF40_PROT_CFG_RTS_TH_EN, 0);
2108         rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
2109
2110         if (rt2x00_is_usb(rt2x00dev)) {
2111                 rt2800_register_write(rt2x00dev, PBF_CFG, 0xf40006);
2112
2113                 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
2114                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
2115                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
2116                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
2117                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
2118                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE, 3);
2119                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 0);
2120                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_BIG_ENDIAN, 0);
2121                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_HDR_SCATTER, 0);
2122                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_HDR_SEG_LEN, 0);
2123                 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
2124         }
2125
2126         /*
2127          * The legacy driver also sets TXOP_CTRL_CFG_RESERVED_TRUN_EN to 1
2128          * although it is reserved.
2129          */
2130         rt2800_register_read(rt2x00dev, TXOP_CTRL_CFG, &reg);
2131         rt2x00_set_field32(&reg, TXOP_CTRL_CFG_TIMEOUT_TRUN_EN, 1);
2132         rt2x00_set_field32(&reg, TXOP_CTRL_CFG_AC_TRUN_EN, 1);
2133         rt2x00_set_field32(&reg, TXOP_CTRL_CFG_TXRATEGRP_TRUN_EN, 1);
2134         rt2x00_set_field32(&reg, TXOP_CTRL_CFG_USER_MODE_TRUN_EN, 1);
2135         rt2x00_set_field32(&reg, TXOP_CTRL_CFG_MIMO_PS_TRUN_EN, 1);
2136         rt2x00_set_field32(&reg, TXOP_CTRL_CFG_RESERVED_TRUN_EN, 1);
2137         rt2x00_set_field32(&reg, TXOP_CTRL_CFG_LSIG_TXOP_EN, 0);
2138         rt2x00_set_field32(&reg, TXOP_CTRL_CFG_EXT_CCA_EN, 0);
2139         rt2x00_set_field32(&reg, TXOP_CTRL_CFG_EXT_CCA_DLY, 88);
2140         rt2x00_set_field32(&reg, TXOP_CTRL_CFG_EXT_CWMIN, 0);
2141         rt2800_register_write(rt2x00dev, TXOP_CTRL_CFG, reg);
2142
2143         rt2800_register_write(rt2x00dev, TXOP_HLDR_ET, 0x00000002);
2144
2145         rt2800_register_read(rt2x00dev, TX_RTS_CFG, &reg);
2146         rt2x00_set_field32(&reg, TX_RTS_CFG_AUTO_RTS_RETRY_LIMIT, 32);
2147         rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_THRES,
2148                            IEEE80211_MAX_RTS_THRESHOLD);
2149         rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_FBK_EN, 0);
2150         rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg);
2151
2152         rt2800_register_write(rt2x00dev, EXP_ACK_TIME, 0x002400ca);
2153
2154         /*
2155          * Usually the CCK SIFS time should be set to 10 and the OFDM SIFS
2156          * time should be set to 16. However, the original Ralink driver uses
2157          * 16 for both and indeed using a value of 10 for CCK SIFS results in
2158          * connection problems with 11g + CTS protection. Hence, use the same
2159          * defaults as the Ralink driver: 16 for both, CCK and OFDM SIFS.
2160          */
2161         rt2800_register_read(rt2x00dev, XIFS_TIME_CFG, &reg);
2162         rt2x00_set_field32(&reg, XIFS_TIME_CFG_CCKM_SIFS_TIME, 16);
2163         rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_SIFS_TIME, 16);
2164         rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_XIFS_TIME, 4);
2165         rt2x00_set_field32(&reg, XIFS_TIME_CFG_EIFS, 314);
2166         rt2x00_set_field32(&reg, XIFS_TIME_CFG_BB_RXEND_ENABLE, 1);
2167         rt2800_register_write(rt2x00dev, XIFS_TIME_CFG, reg);
2168
2169         rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000003);
2170
2171         /*
2172          * ASIC will keep garbage value after boot, clear encryption keys.
2173          */
2174         for (i = 0; i < 4; i++)
2175                 rt2800_register_write(rt2x00dev,
2176                                          SHARED_KEY_MODE_ENTRY(i), 0);
2177
2178         for (i = 0; i < 256; i++) {
2179                 static const u32 wcid[2] = { 0xffffffff, 0x00ffffff };
2180                 rt2800_register_multiwrite(rt2x00dev, MAC_WCID_ENTRY(i),
2181                                               wcid, sizeof(wcid));
2182
2183                 rt2800_register_write(rt2x00dev, MAC_WCID_ATTR_ENTRY(i), 1);
2184                 rt2800_register_write(rt2x00dev, MAC_IVEIV_ENTRY(i), 0);
2185         }
2186
2187         /*
2188          * Clear all beacons
2189          */
2190         rt2800_clear_beacon(rt2x00dev, HW_BEACON_BASE0);
2191         rt2800_clear_beacon(rt2x00dev, HW_BEACON_BASE1);
2192         rt2800_clear_beacon(rt2x00dev, HW_BEACON_BASE2);
2193         rt2800_clear_beacon(rt2x00dev, HW_BEACON_BASE3);
2194         rt2800_clear_beacon(rt2x00dev, HW_BEACON_BASE4);
2195         rt2800_clear_beacon(rt2x00dev, HW_BEACON_BASE5);
2196         rt2800_clear_beacon(rt2x00dev, HW_BEACON_BASE6);
2197         rt2800_clear_beacon(rt2x00dev, HW_BEACON_BASE7);
2198
2199         if (rt2x00_is_usb(rt2x00dev)) {
2200                 rt2800_register_read(rt2x00dev, US_CYC_CNT, &reg);
2201                 rt2x00_set_field32(&reg, US_CYC_CNT_CLOCK_CYCLE, 30);
2202                 rt2800_register_write(rt2x00dev, US_CYC_CNT, reg);
2203         }
2204
2205         rt2800_register_read(rt2x00dev, HT_FBK_CFG0, &reg);
2206         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS0FBK, 0);
2207         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS1FBK, 0);
2208         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS2FBK, 1);
2209         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS3FBK, 2);
2210         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS4FBK, 3);
2211         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS5FBK, 4);
2212         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS6FBK, 5);
2213         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS7FBK, 6);
2214         rt2800_register_write(rt2x00dev, HT_FBK_CFG0, reg);
2215
2216         rt2800_register_read(rt2x00dev, HT_FBK_CFG1, &reg);
2217         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS8FBK, 8);
2218         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS9FBK, 8);
2219         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS10FBK, 9);
2220         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS11FBK, 10);
2221         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS12FBK, 11);
2222         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS13FBK, 12);
2223         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS14FBK, 13);
2224         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS15FBK, 14);
2225         rt2800_register_write(rt2x00dev, HT_FBK_CFG1, reg);
2226
2227         rt2800_register_read(rt2x00dev, LG_FBK_CFG0, &reg);
2228         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS0FBK, 8);
2229         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS1FBK, 8);
2230         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS2FBK, 9);
2231         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS3FBK, 10);
2232         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS4FBK, 11);
2233         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS5FBK, 12);
2234         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS6FBK, 13);
2235         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS7FBK, 14);
2236         rt2800_register_write(rt2x00dev, LG_FBK_CFG0, reg);
2237
2238         rt2800_register_read(rt2x00dev, LG_FBK_CFG1, &reg);
2239         rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS0FBK, 0);
2240         rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS1FBK, 0);
2241         rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS2FBK, 1);
2242         rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS3FBK, 2);
2243         rt2800_register_write(rt2x00dev, LG_FBK_CFG1, reg);
2244
2245         /*
2246          * Do not force the BA window size, we use the TXWI to set it
2247          */
2248         rt2800_register_read(rt2x00dev, AMPDU_BA_WINSIZE, &reg);
2249         rt2x00_set_field32(&reg, AMPDU_BA_WINSIZE_FORCE_WINSIZE_ENABLE, 0);
2250         rt2x00_set_field32(&reg, AMPDU_BA_WINSIZE_FORCE_WINSIZE, 0);
2251         rt2800_register_write(rt2x00dev, AMPDU_BA_WINSIZE, reg);
2252
2253         /*
2254          * We must clear the error counters.
2255          * These registers are cleared on read,
2256          * so we may pass a useless variable to store the value.
2257          */
2258         rt2800_register_read(rt2x00dev, RX_STA_CNT0, &reg);
2259         rt2800_register_read(rt2x00dev, RX_STA_CNT1, &reg);
2260         rt2800_register_read(rt2x00dev, RX_STA_CNT2, &reg);
2261         rt2800_register_read(rt2x00dev, TX_STA_CNT0, &reg);
2262         rt2800_register_read(rt2x00dev, TX_STA_CNT1, &reg);
2263         rt2800_register_read(rt2x00dev, TX_STA_CNT2, &reg);
2264
2265         /*
2266          * Setup leadtime for pre tbtt interrupt to 6ms
2267          */
2268         rt2800_register_read(rt2x00dev, INT_TIMER_CFG, &reg);
2269         rt2x00_set_field32(&reg, INT_TIMER_CFG_PRE_TBTT_TIMER, 6 << 4);
2270         rt2800_register_write(rt2x00dev, INT_TIMER_CFG, reg);
2271
2272         /*
2273          * Set up channel statistics timer
2274          */
2275         rt2800_register_read(rt2x00dev, CH_TIME_CFG, &reg);
2276         rt2x00_set_field32(&reg, CH_TIME_CFG_EIFS_BUSY, 1);
2277         rt2x00_set_field32(&reg, CH_TIME_CFG_NAV_BUSY, 1);
2278         rt2x00_set_field32(&reg, CH_TIME_CFG_RX_BUSY, 1);
2279         rt2x00_set_field32(&reg, CH_TIME_CFG_TX_BUSY, 1);
2280         rt2x00_set_field32(&reg, CH_TIME_CFG_TMR_EN, 1);
2281         rt2800_register_write(rt2x00dev, CH_TIME_CFG, reg);
2282
2283         return 0;
2284 }
2285
2286 static int rt2800_wait_bbp_rf_ready(struct rt2x00_dev *rt2x00dev)
2287 {
2288         unsigned int i;
2289         u32 reg;
2290
2291         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
2292                 rt2800_register_read(rt2x00dev, MAC_STATUS_CFG, &reg);
2293                 if (!rt2x00_get_field32(reg, MAC_STATUS_CFG_BBP_RF_BUSY))
2294                         return 0;
2295
2296                 udelay(REGISTER_BUSY_DELAY);
2297         }
2298
2299         ERROR(rt2x00dev, "BBP/RF register access failed, aborting.\n");
2300         return -EACCES;
2301 }
2302
2303 static int rt2800_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)
2304 {
2305         unsigned int i;
2306         u8 value;
2307
2308         /*
2309          * BBP was enabled after firmware was loaded,
2310          * but we need to reactivate it now.
2311          */
2312         rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
2313         rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
2314         msleep(1);
2315
2316         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
2317                 rt2800_bbp_read(rt2x00dev, 0, &value);
2318                 if ((value != 0xff) && (value != 0x00))
2319                         return 0;
2320                 udelay(REGISTER_BUSY_DELAY);
2321         }
2322
2323         ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
2324         return -EACCES;
2325 }
2326
2327 static int rt2800_init_bbp(struct rt2x00_dev *rt2x00dev)
2328 {
2329         unsigned int i;
2330         u16 eeprom;
2331         u8 reg_id;
2332         u8 value;
2333
2334         if (unlikely(rt2800_wait_bbp_rf_ready(rt2x00dev) ||
2335                      rt2800_wait_bbp_ready(rt2x00dev)))
2336                 return -EACCES;
2337
2338         if (rt2800_is_305x_soc(rt2x00dev))
2339                 rt2800_bbp_write(rt2x00dev, 31, 0x08);
2340
2341         rt2800_bbp_write(rt2x00dev, 65, 0x2c);
2342         rt2800_bbp_write(rt2x00dev, 66, 0x38);
2343
2344         if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C)) {
2345                 rt2800_bbp_write(rt2x00dev, 69, 0x16);
2346                 rt2800_bbp_write(rt2x00dev, 73, 0x12);
2347         } else {
2348                 rt2800_bbp_write(rt2x00dev, 69, 0x12);
2349                 rt2800_bbp_write(rt2x00dev, 73, 0x10);
2350         }
2351
2352         rt2800_bbp_write(rt2x00dev, 70, 0x0a);
2353
2354         if (rt2x00_rt(rt2x00dev, RT3070) ||
2355             rt2x00_rt(rt2x00dev, RT3071) ||
2356             rt2x00_rt(rt2x00dev, RT3090) ||
2357             rt2x00_rt(rt2x00dev, RT3390)) {
2358                 rt2800_bbp_write(rt2x00dev, 79, 0x13);
2359                 rt2800_bbp_write(rt2x00dev, 80, 0x05);
2360                 rt2800_bbp_write(rt2x00dev, 81, 0x33);
2361         } else if (rt2800_is_305x_soc(rt2x00dev)) {
2362                 rt2800_bbp_write(rt2x00dev, 78, 0x0e);
2363                 rt2800_bbp_write(rt2x00dev, 80, 0x08);
2364         } else {
2365                 rt2800_bbp_write(rt2x00dev, 81, 0x37);
2366         }
2367
2368         rt2800_bbp_write(rt2x00dev, 82, 0x62);
2369         rt2800_bbp_write(rt2x00dev, 83, 0x6a);
2370
2371         if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860D))
2372                 rt2800_bbp_write(rt2x00dev, 84, 0x19);
2373         else
2374                 rt2800_bbp_write(rt2x00dev, 84, 0x99);
2375
2376         rt2800_bbp_write(rt2x00dev, 86, 0x00);
2377         rt2800_bbp_write(rt2x00dev, 91, 0x04);
2378         rt2800_bbp_write(rt2x00dev, 92, 0x00);
2379
2380         if (rt2x00_rt_rev_gte(rt2x00dev, RT3070, REV_RT3070F) ||
2381             rt2x00_rt_rev_gte(rt2x00dev, RT3071, REV_RT3071E) ||
2382             rt2x00_rt_rev_gte(rt2x00dev, RT3090, REV_RT3090E) ||
2383             rt2x00_rt_rev_gte(rt2x00dev, RT3390, REV_RT3390E) ||
2384             rt2800_is_305x_soc(rt2x00dev))
2385                 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
2386         else
2387                 rt2800_bbp_write(rt2x00dev, 103, 0x00);
2388
2389         if (rt2800_is_305x_soc(rt2x00dev))
2390                 rt2800_bbp_write(rt2x00dev, 105, 0x01);
2391         else
2392                 rt2800_bbp_write(rt2x00dev, 105, 0x05);
2393         rt2800_bbp_write(rt2x00dev, 106, 0x35);
2394
2395         if (rt2x00_rt(rt2x00dev, RT3071) ||
2396             rt2x00_rt(rt2x00dev, RT3090) ||
2397             rt2x00_rt(rt2x00dev, RT3390)) {
2398                 rt2800_bbp_read(rt2x00dev, 138, &value);
2399
2400                 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom);
2401                 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) == 1)
2402                         value |= 0x20;
2403                 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) == 1)
2404                         value &= ~0x02;
2405
2406                 rt2800_bbp_write(rt2x00dev, 138, value);
2407         }
2408
2409
2410         for (i = 0; i < EEPROM_BBP_SIZE; i++) {
2411                 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
2412
2413                 if (eeprom != 0xffff && eeprom != 0x0000) {
2414                         reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
2415                         value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
2416                         rt2800_bbp_write(rt2x00dev, reg_id, value);
2417                 }
2418         }
2419
2420         return 0;
2421 }
2422
2423 static u8 rt2800_init_rx_filter(struct rt2x00_dev *rt2x00dev,
2424                                 bool bw40, u8 rfcsr24, u8 filter_target)
2425 {
2426         unsigned int i;
2427         u8 bbp;
2428         u8 rfcsr;
2429         u8 passband;
2430         u8 stopband;
2431         u8 overtuned = 0;
2432
2433         rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
2434
2435         rt2800_bbp_read(rt2x00dev, 4, &bbp);
2436         rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * bw40);
2437         rt2800_bbp_write(rt2x00dev, 4, bbp);
2438
2439         rt2800_rfcsr_read(rt2x00dev, 22, &rfcsr);
2440         rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 1);
2441         rt2800_rfcsr_write(rt2x00dev, 22, rfcsr);
2442
2443         /*
2444          * Set power & frequency of passband test tone
2445          */
2446         rt2800_bbp_write(rt2x00dev, 24, 0);
2447
2448         for (i = 0; i < 100; i++) {
2449                 rt2800_bbp_write(rt2x00dev, 25, 0x90);
2450                 msleep(1);
2451
2452                 rt2800_bbp_read(rt2x00dev, 55, &passband);
2453                 if (passband)
2454                         break;
2455         }
2456
2457         /*
2458          * Set power & frequency of stopband test tone
2459          */
2460         rt2800_bbp_write(rt2x00dev, 24, 0x06);
2461
2462         for (i = 0; i < 100; i++) {
2463                 rt2800_bbp_write(rt2x00dev, 25, 0x90);
2464                 msleep(1);
2465
2466                 rt2800_bbp_read(rt2x00dev, 55, &stopband);
2467
2468                 if ((passband - stopband) <= filter_target) {
2469                         rfcsr24++;
2470                         overtuned += ((passband - stopband) == filter_target);
2471                 } else
2472                         break;
2473
2474                 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
2475         }
2476
2477         rfcsr24 -= !!overtuned;
2478
2479         rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
2480         return rfcsr24;
2481 }
2482
2483 static int rt2800_init_rfcsr(struct rt2x00_dev *rt2x00dev)
2484 {
2485         u8 rfcsr;
2486         u8 bbp;
2487         u32 reg;
2488         u16 eeprom;
2489
2490         if (!rt2x00_rt(rt2x00dev, RT3070) &&
2491             !rt2x00_rt(rt2x00dev, RT3071) &&
2492             !rt2x00_rt(rt2x00dev, RT3090) &&
2493             !rt2x00_rt(rt2x00dev, RT3390) &&
2494             !rt2800_is_305x_soc(rt2x00dev))
2495                 return 0;
2496
2497         /*
2498          * Init RF calibration.
2499          */
2500         rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
2501         rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 1);
2502         rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
2503         msleep(1);
2504         rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 0);
2505         rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
2506
2507         if (rt2x00_rt(rt2x00dev, RT3070) ||
2508             rt2x00_rt(rt2x00dev, RT3071) ||
2509             rt2x00_rt(rt2x00dev, RT3090)) {
2510                 rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
2511                 rt2800_rfcsr_write(rt2x00dev, 5, 0x03);
2512                 rt2800_rfcsr_write(rt2x00dev, 6, 0x02);
2513                 rt2800_rfcsr_write(rt2x00dev, 7, 0x70);
2514                 rt2800_rfcsr_write(rt2x00dev, 9, 0x0f);
2515                 rt2800_rfcsr_write(rt2x00dev, 10, 0x41);
2516                 rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
2517                 rt2800_rfcsr_write(rt2x00dev, 12, 0x7b);
2518                 rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
2519                 rt2800_rfcsr_write(rt2x00dev, 15, 0x58);
2520                 rt2800_rfcsr_write(rt2x00dev, 16, 0xb3);
2521                 rt2800_rfcsr_write(rt2x00dev, 17, 0x92);
2522                 rt2800_rfcsr_write(rt2x00dev, 18, 0x2c);
2523                 rt2800_rfcsr_write(rt2x00dev, 19, 0x02);
2524                 rt2800_rfcsr_write(rt2x00dev, 20, 0xba);
2525                 rt2800_rfcsr_write(rt2x00dev, 21, 0xdb);
2526                 rt2800_rfcsr_write(rt2x00dev, 24, 0x16);
2527                 rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
2528                 rt2800_rfcsr_write(rt2x00dev, 29, 0x1f);
2529         } else if (rt2x00_rt(rt2x00dev, RT3390)) {
2530                 rt2800_rfcsr_write(rt2x00dev, 0, 0xa0);
2531                 rt2800_rfcsr_write(rt2x00dev, 1, 0xe1);
2532                 rt2800_rfcsr_write(rt2x00dev, 2, 0xf1);
2533                 rt2800_rfcsr_write(rt2x00dev, 3, 0x62);
2534                 rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
2535                 rt2800_rfcsr_write(rt2x00dev, 5, 0x8b);
2536                 rt2800_rfcsr_write(rt2x00dev, 6, 0x42);
2537                 rt2800_rfcsr_write(rt2x00dev, 7, 0x34);
2538                 rt2800_rfcsr_write(rt2x00dev, 8, 0x00);
2539                 rt2800_rfcsr_write(rt2x00dev, 9, 0xc0);
2540                 rt2800_rfcsr_write(rt2x00dev, 10, 0x61);
2541                 rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
2542                 rt2800_rfcsr_write(rt2x00dev, 12, 0x3b);
2543                 rt2800_rfcsr_write(rt2x00dev, 13, 0xe0);
2544                 rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
2545                 rt2800_rfcsr_write(rt2x00dev, 15, 0x53);
2546                 rt2800_rfcsr_write(rt2x00dev, 16, 0xe0);
2547                 rt2800_rfcsr_write(rt2x00dev, 17, 0x94);
2548                 rt2800_rfcsr_write(rt2x00dev, 18, 0x5c);
2549                 rt2800_rfcsr_write(rt2x00dev, 19, 0x4a);
2550                 rt2800_rfcsr_write(rt2x00dev, 20, 0xb2);
2551                 rt2800_rfcsr_write(rt2x00dev, 21, 0xf6);
2552                 rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
2553                 rt2800_rfcsr_write(rt2x00dev, 23, 0x14);
2554                 rt2800_rfcsr_write(rt2x00dev, 24, 0x08);
2555                 rt2800_rfcsr_write(rt2x00dev, 25, 0x3d);
2556                 rt2800_rfcsr_write(rt2x00dev, 26, 0x85);
2557                 rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
2558                 rt2800_rfcsr_write(rt2x00dev, 28, 0x41);
2559                 rt2800_rfcsr_write(rt2x00dev, 29, 0x8f);
2560                 rt2800_rfcsr_write(rt2x00dev, 30, 0x20);
2561                 rt2800_rfcsr_write(rt2x00dev, 31, 0x0f);
2562         } else if (rt2800_is_305x_soc(rt2x00dev)) {
2563                 rt2800_rfcsr_write(rt2x00dev, 0, 0x50);
2564                 rt2800_rfcsr_write(rt2x00dev, 1, 0x01);
2565                 rt2800_rfcsr_write(rt2x00dev, 2, 0xf7);
2566                 rt2800_rfcsr_write(rt2x00dev, 3, 0x75);
2567                 rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
2568                 rt2800_rfcsr_write(rt2x00dev, 5, 0x03);
2569                 rt2800_rfcsr_write(rt2x00dev, 6, 0x02);
2570                 rt2800_rfcsr_write(rt2x00dev, 7, 0x50);
2571                 rt2800_rfcsr_write(rt2x00dev, 8, 0x39);
2572                 rt2800_rfcsr_write(rt2x00dev, 9, 0x0f);
2573                 rt2800_rfcsr_write(rt2x00dev, 10, 0x60);
2574                 rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
2575                 rt2800_rfcsr_write(rt2x00dev, 12, 0x75);
2576                 rt2800_rfcsr_write(rt2x00dev, 13, 0x75);
2577                 rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
2578                 rt2800_rfcsr_write(rt2x00dev, 15, 0x58);
2579                 rt2800_rfcsr_write(rt2x00dev, 16, 0xb3);
2580                 rt2800_rfcsr_write(rt2x00dev, 17, 0x92);
2581                 rt2800_rfcsr_write(rt2x00dev, 18, 0x2c);
2582                 rt2800_rfcsr_write(rt2x00dev, 19, 0x02);
2583                 rt2800_rfcsr_write(rt2x00dev, 20, 0xba);
2584                 rt2800_rfcsr_write(rt2x00dev, 21, 0xdb);
2585                 rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
2586                 rt2800_rfcsr_write(rt2x00dev, 23, 0x31);
2587                 rt2800_rfcsr_write(rt2x00dev, 24, 0x08);
2588                 rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
2589                 rt2800_rfcsr_write(rt2x00dev, 26, 0x25);
2590                 rt2800_rfcsr_write(rt2x00dev, 27, 0x23);
2591                 rt2800_rfcsr_write(rt2x00dev, 28, 0x13);
2592                 rt2800_rfcsr_write(rt2x00dev, 29, 0x83);
2593                 rt2800_rfcsr_write(rt2x00dev, 30, 0x00);
2594                 rt2800_rfcsr_write(rt2x00dev, 31, 0x00);
2595                 return 0;
2596         }
2597
2598         if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F)) {
2599                 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
2600                 rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
2601                 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 3);
2602                 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
2603         } else if (rt2x00_rt(rt2x00dev, RT3071) ||
2604                    rt2x00_rt(rt2x00dev, RT3090)) {
2605                 rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
2606                 rt2x00_set_field8(&rfcsr, RFCSR6_R2, 1);
2607                 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
2608
2609                 rt2800_rfcsr_write(rt2x00dev, 31, 0x14);
2610
2611                 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
2612                 rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
2613                 if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
2614                     rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E)) {
2615                         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
2616                         if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_DAC_TEST))
2617                                 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 3);
2618                         else
2619                                 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 0);
2620                 }
2621                 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
2622         } else if (rt2x00_rt(rt2x00dev, RT3390)) {
2623                 rt2800_register_read(rt2x00dev, GPIO_SWITCH, &reg);
2624                 rt2x00_set_field32(&reg, GPIO_SWITCH_5, 0);
2625                 rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg);
2626         }
2627
2628         /*
2629          * Set RX Filter calibration for 20MHz and 40MHz
2630          */
2631         if (rt2x00_rt(rt2x00dev, RT3070)) {
2632                 rt2x00dev->calibration[0] =
2633                         rt2800_init_rx_filter(rt2x00dev, false, 0x07, 0x16);
2634                 rt2x00dev->calibration[1] =
2635                         rt2800_init_rx_filter(rt2x00dev, true, 0x27, 0x19);
2636         } else if (rt2x00_rt(rt2x00dev, RT3071) ||
2637                    rt2x00_rt(rt2x00dev, RT3090) ||
2638                    rt2x00_rt(rt2x00dev, RT3390)) {
2639                 rt2x00dev->calibration[0] =
2640                         rt2800_init_rx_filter(rt2x00dev, false, 0x07, 0x13);
2641                 rt2x00dev->calibration[1] =
2642                         rt2800_init_rx_filter(rt2x00dev, true, 0x27, 0x15);
2643         }
2644
2645         /*
2646          * Set back to initial state
2647          */
2648         rt2800_bbp_write(rt2x00dev, 24, 0);
2649
2650         rt2800_rfcsr_read(rt2x00dev, 22, &rfcsr);
2651         rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 0);
2652         rt2800_rfcsr_write(rt2x00dev, 22, rfcsr);
2653
2654         /*
2655          * set BBP back to BW20
2656          */
2657         rt2800_bbp_read(rt2x00dev, 4, &bbp);
2658         rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 0);
2659         rt2800_bbp_write(rt2x00dev, 4, bbp);
2660
2661         if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F) ||
2662             rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
2663             rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) ||
2664             rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E))
2665                 rt2800_rfcsr_write(rt2x00dev, 27, 0x03);
2666
2667         rt2800_register_read(rt2x00dev, OPT_14_CSR, &reg);
2668         rt2x00_set_field32(&reg, OPT_14_CSR_BIT0, 1);
2669         rt2800_register_write(rt2x00dev, OPT_14_CSR, reg);
2670
2671         rt2800_rfcsr_read(rt2x00dev, 17, &rfcsr);
2672         rt2x00_set_field8(&rfcsr, RFCSR17_TX_LO1_EN, 0);
2673         if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
2674             rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) ||
2675             rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E)) {
2676                 if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags))
2677                         rt2x00_set_field8(&rfcsr, RFCSR17_R, 1);
2678         }
2679         rt2x00_eeprom_read(rt2x00dev, EEPROM_TXMIXER_GAIN_BG, &eeprom);
2680         if (rt2x00_get_field16(eeprom, EEPROM_TXMIXER_GAIN_BG_VAL) >= 1)
2681                 rt2x00_set_field8(&rfcsr, RFCSR17_TXMIXER_GAIN,
2682                                   rt2x00_get_field16(eeprom,
2683                                                    EEPROM_TXMIXER_GAIN_BG_VAL));
2684         rt2800_rfcsr_write(rt2x00dev, 17, rfcsr);
2685
2686         if (rt2x00_rt(rt2x00dev, RT3090)) {
2687                 rt2800_bbp_read(rt2x00dev, 138, &bbp);
2688
2689                 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom);
2690                 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) == 1)
2691                         rt2x00_set_field8(&bbp, BBP138_RX_ADC1, 0);
2692                 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) == 1)
2693                         rt2x00_set_field8(&bbp, BBP138_TX_DAC1, 1);
2694
2695                 rt2800_bbp_write(rt2x00dev, 138, bbp);
2696         }
2697
2698         if (rt2x00_rt(rt2x00dev, RT3071) ||
2699             rt2x00_rt(rt2x00dev, RT3090) ||
2700             rt2x00_rt(rt2x00dev, RT3390)) {
2701                 rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
2702                 rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
2703                 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0);
2704                 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0);
2705                 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
2706                 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
2707                 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
2708
2709                 rt2800_rfcsr_read(rt2x00dev, 15, &rfcsr);
2710                 rt2x00_set_field8(&rfcsr, RFCSR15_TX_LO2_EN, 0);
2711                 rt2800_rfcsr_write(rt2x00dev, 15, rfcsr);
2712
2713                 rt2800_rfcsr_read(rt2x00dev, 20, &rfcsr);
2714                 rt2x00_set_field8(&rfcsr, RFCSR20_RX_LO1_EN, 0);
2715                 rt2800_rfcsr_write(rt2x00dev, 20, rfcsr);
2716
2717                 rt2800_rfcsr_read(rt2x00dev, 21, &rfcsr);
2718                 rt2x00_set_field8(&rfcsr, RFCSR21_RX_LO2_EN, 0);
2719                 rt2800_rfcsr_write(rt2x00dev, 21, rfcsr);
2720         }
2721
2722         if (rt2x00_rt(rt2x00dev, RT3070) || rt2x00_rt(rt2x00dev, RT3071)) {
2723                 rt2800_rfcsr_read(rt2x00dev, 27, &rfcsr);
2724                 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F) ||
2725                     rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E))
2726                         rt2x00_set_field8(&rfcsr, RFCSR27_R1, 3);
2727                 else
2728                         rt2x00_set_field8(&rfcsr, RFCSR27_R1, 0);
2729                 rt2x00_set_field8(&rfcsr, RFCSR27_R2, 0);
2730                 rt2x00_set_field8(&rfcsr, RFCSR27_R3, 0);
2731                 rt2x00_set_field8(&rfcsr, RFCSR27_R4, 0);
2732                 rt2800_rfcsr_write(rt2x00dev, 27, rfcsr);
2733         }
2734
2735         return 0;
2736 }
2737
2738 int rt2800_enable_radio(struct rt2x00_dev *rt2x00dev)
2739 {
2740         u32 reg;
2741         u16 word;
2742
2743         /*
2744          * Initialize all registers.
2745          */
2746         if (unlikely(rt2800_wait_wpdma_ready(rt2x00dev) ||
2747                      rt2800_init_registers(rt2x00dev) ||
2748                      rt2800_init_bbp(rt2x00dev) ||
2749                      rt2800_init_rfcsr(rt2x00dev)))
2750                 return -EIO;
2751
2752         /*
2753          * Send signal to firmware during boot time.
2754          */
2755         rt2800_mcu_request(rt2x00dev, MCU_BOOT_SIGNAL, 0, 0, 0);
2756
2757         if (rt2x00_is_usb(rt2x00dev) &&
2758             (rt2x00_rt(rt2x00dev, RT3070) ||
2759              rt2x00_rt(rt2x00dev, RT3071) ||
2760              rt2x00_rt(rt2x00dev, RT3572))) {
2761                 udelay(200);
2762                 rt2800_mcu_request(rt2x00dev, MCU_CURRENT, 0, 0, 0);
2763                 udelay(10);
2764         }
2765
2766         /*
2767          * Enable RX.
2768          */
2769         rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
2770         rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 1);
2771         rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 0);
2772         rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
2773
2774         udelay(50);
2775
2776         rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
2777         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 1);
2778         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 1);
2779         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE, 2);
2780         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
2781         rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
2782
2783         rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
2784         rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 1);
2785         rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 1);
2786         rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
2787
2788         /*
2789          * Initialize LED control
2790          */
2791         rt2x00_eeprom_read(rt2x00dev, EEPROM_LED_AG_CONF, &word);
2792         rt2800_mcu_request(rt2x00dev, MCU_LED_AG_CONF, 0xff,
2793                            word & 0xff, (word >> 8) & 0xff);
2794
2795         rt2x00_eeprom_read(rt2x00dev, EEPROM_LED_ACT_CONF, &word);
2796         rt2800_mcu_request(rt2x00dev, MCU_LED_ACT_CONF, 0xff,
2797                            word & 0xff, (word >> 8) & 0xff);
2798
2799         rt2x00_eeprom_read(rt2x00dev, EEPROM_LED_POLARITY, &word);
2800         rt2800_mcu_request(rt2x00dev, MCU_LED_LED_POLARITY, 0xff,
2801                            word & 0xff, (word >> 8) & 0xff);
2802
2803         return 0;
2804 }
2805 EXPORT_SYMBOL_GPL(rt2800_enable_radio);
2806
2807 void rt2800_disable_radio(struct rt2x00_dev *rt2x00dev)
2808 {
2809         u32 reg;
2810
2811         rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
2812         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
2813         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
2814         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
2815         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
2816         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
2817         rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
2818
2819         /* Wait for DMA, ignore error */
2820         rt2800_wait_wpdma_ready(rt2x00dev);
2821
2822         rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
2823         rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 0);
2824         rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 0);
2825         rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
2826
2827         rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0);
2828         rt2800_register_write(rt2x00dev, TX_PIN_CFG, 0);
2829 }
2830 EXPORT_SYMBOL_GPL(rt2800_disable_radio);
2831
2832 int rt2800_efuse_detect(struct rt2x00_dev *rt2x00dev)
2833 {
2834         u32 reg;
2835
2836         rt2800_register_read(rt2x00dev, EFUSE_CTRL, &reg);
2837
2838         return rt2x00_get_field32(reg, EFUSE_CTRL_PRESENT);
2839 }
2840 EXPORT_SYMBOL_GPL(rt2800_efuse_detect);
2841
2842 static void rt2800_efuse_read(struct rt2x00_dev *rt2x00dev, unsigned int i)
2843 {
2844         u32 reg;
2845
2846         mutex_lock(&rt2x00dev->csr_mutex);
2847
2848         rt2800_register_read_lock(rt2x00dev, EFUSE_CTRL, &reg);
2849         rt2x00_set_field32(&reg, EFUSE_CTRL_ADDRESS_IN, i);
2850         rt2x00_set_field32(&reg, EFUSE_CTRL_MODE, 0);
2851         rt2x00_set_field32(&reg, EFUSE_CTRL_KICK, 1);
2852         rt2800_register_write_lock(rt2x00dev, EFUSE_CTRL, reg);
2853
2854         /* Wait until the EEPROM has been loaded */
2855         rt2800_regbusy_read(rt2x00dev, EFUSE_CTRL, EFUSE_CTRL_KICK, &reg);
2856
2857         /* Apparently the data is read from end to start */
2858         rt2800_register_read_lock(rt2x00dev, EFUSE_DATA3,
2859                                         (u32 *)&rt2x00dev->eeprom[i]);
2860         rt2800_register_read_lock(rt2x00dev, EFUSE_DATA2,
2861                                         (u32 *)&rt2x00dev->eeprom[i + 2]);
2862         rt2800_register_read_lock(rt2x00dev, EFUSE_DATA1,
2863                                         (u32 *)&rt2x00dev->eeprom[i + 4]);
2864         rt2800_register_read_lock(rt2x00dev, EFUSE_DATA0,
2865                                         (u32 *)&rt2x00dev->eeprom[i + 6]);
2866
2867         mutex_unlock(&rt2x00dev->csr_mutex);
2868 }
2869
2870 void rt2800_read_eeprom_efuse(struct rt2x00_dev *rt2x00dev)
2871 {
2872         unsigned int i;
2873
2874         for (i = 0; i < EEPROM_SIZE / sizeof(u16); i += 8)
2875                 rt2800_efuse_read(rt2x00dev, i);
2876 }
2877 EXPORT_SYMBOL_GPL(rt2800_read_eeprom_efuse);
2878
2879 int rt2800_validate_eeprom(struct rt2x00_dev *rt2x00dev)
2880 {
2881         u16 word;
2882         u8 *mac;
2883         u8 default_lna_gain;
2884
2885         /*
2886          * Start validation of the data that has been read.
2887          */
2888         mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
2889         if (!is_valid_ether_addr(mac)) {
2890                 random_ether_addr(mac);
2891                 EEPROM(rt2x00dev, "MAC: %pM\n", mac);
2892         }
2893
2894         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &word);
2895         if (word == 0xffff) {
2896                 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_RXPATH, 2);
2897                 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_TXPATH, 1);
2898                 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_RF_TYPE, RF2820);
2899                 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC_CONF0, word);
2900                 EEPROM(rt2x00dev, "Antenna: 0x%04x\n", word);
2901         } else if (rt2x00_rt(rt2x00dev, RT2860) ||
2902                    rt2x00_rt(rt2x00dev, RT2872)) {
2903                 /*
2904                  * There is a max of 2 RX streams for RT28x0 series
2905                  */
2906                 if (rt2x00_get_field16(word, EEPROM_NIC_CONF0_RXPATH) > 2)
2907                         rt2x00_set_field16(&word, EEPROM_NIC_CONF0_RXPATH, 2);
2908                 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC_CONF0, word);
2909         }
2910
2911         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &word);
2912         if (word == 0xffff) {
2913                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_HW_RADIO, 0);
2914                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_EXTERNAL_TX_ALC, 0);
2915                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_EXTERNAL_LNA_2G, 0);
2916                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_EXTERNAL_LNA_5G, 0);
2917                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_CARDBUS_ACCEL, 0);
2918                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_SB_2G, 0);
2919                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_SB_5G, 0);
2920                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_WPS_PBC, 0);
2921                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_2G, 0);
2922                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_5G, 0);
2923                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BROADBAND_EXT_LNA, 0);
2924                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_ANT_DIVERSITY, 0);
2925                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_INTERNAL_TX_ALC, 0);
2926                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BT_COEXIST, 0);
2927                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_DAC_TEST, 0);
2928                 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC_CONF1, word);
2929                 EEPROM(rt2x00dev, "NIC: 0x%04x\n", word);
2930         }
2931
2932         rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &word);
2933         if ((word & 0x00ff) == 0x00ff) {
2934                 rt2x00_set_field16(&word, EEPROM_FREQ_OFFSET, 0);
2935                 rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
2936                 EEPROM(rt2x00dev, "Freq: 0x%04x\n", word);
2937         }
2938         if ((word & 0xff00) == 0xff00) {
2939                 rt2x00_set_field16(&word, EEPROM_FREQ_LED_MODE,
2940                                    LED_MODE_TXRX_ACTIVITY);
2941                 rt2x00_set_field16(&word, EEPROM_FREQ_LED_POLARITY, 0);
2942                 rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
2943                 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED_AG_CONF, 0x5555);
2944                 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED_ACT_CONF, 0x2221);
2945                 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED_POLARITY, 0xa9f8);
2946                 EEPROM(rt2x00dev, "Led Mode: 0x%04x\n", word);
2947         }
2948
2949         /*
2950          * During the LNA validation we are going to use
2951          * lna0 as correct value. Note that EEPROM_LNA
2952          * is never validated.
2953          */
2954         rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &word);
2955         default_lna_gain = rt2x00_get_field16(word, EEPROM_LNA_A0);
2956
2957         rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG, &word);
2958         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET0)) > 10)
2959                 rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET0, 0);
2960         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET1)) > 10)
2961                 rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET1, 0);
2962         rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_BG, word);
2963
2964         rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &word);
2965         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG2_OFFSET2)) > 10)
2966                 rt2x00_set_field16(&word, EEPROM_RSSI_BG2_OFFSET2, 0);
2967         if (rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0x00 ||
2968             rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0xff)
2969                 rt2x00_set_field16(&word, EEPROM_RSSI_BG2_LNA_A1,
2970                                    default_lna_gain);
2971         rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_BG2, word);
2972
2973         rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A, &word);
2974         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET0)) > 10)
2975                 rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET0, 0);
2976         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET1)) > 10)
2977                 rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET1, 0);
2978         rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_A, word);
2979
2980         rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &word);
2981         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A2_OFFSET2)) > 10)
2982                 rt2x00_set_field16(&word, EEPROM_RSSI_A2_OFFSET2, 0);
2983         if (rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0x00 ||
2984             rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0xff)
2985                 rt2x00_set_field16(&word, EEPROM_RSSI_A2_LNA_A2,
2986                                    default_lna_gain);
2987         rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_A2, word);
2988
2989         rt2x00_eeprom_read(rt2x00dev, EEPROM_MAX_TX_POWER, &word);
2990         if (rt2x00_get_field16(word, EEPROM_MAX_TX_POWER_24GHZ) == 0xff)
2991                 rt2x00_set_field16(&word, EEPROM_MAX_TX_POWER_24GHZ, MAX_G_TXPOWER);
2992         if (rt2x00_get_field16(word, EEPROM_MAX_TX_POWER_5GHZ) == 0xff)
2993                 rt2x00_set_field16(&word, EEPROM_MAX_TX_POWER_5GHZ, MAX_A_TXPOWER);
2994         rt2x00_eeprom_write(rt2x00dev, EEPROM_MAX_TX_POWER, word);
2995
2996         return 0;
2997 }
2998 EXPORT_SYMBOL_GPL(rt2800_validate_eeprom);
2999
3000 int rt2800_init_eeprom(struct rt2x00_dev *rt2x00dev)
3001 {
3002         u32 reg;
3003         u16 value;
3004         u16 eeprom;
3005
3006         /*
3007          * Read EEPROM word for configuration.
3008          */
3009         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom);
3010
3011         /*
3012          * Identify RF chipset.
3013          */
3014         value = rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RF_TYPE);
3015         rt2800_register_read(rt2x00dev, MAC_CSR0, &reg);
3016
3017         rt2x00_set_chip(rt2x00dev, rt2x00_get_field32(reg, MAC_CSR0_CHIPSET),
3018                         value, rt2x00_get_field32(reg, MAC_CSR0_REVISION));
3019
3020         if (!rt2x00_rt(rt2x00dev, RT2860) &&
3021             !rt2x00_rt(rt2x00dev, RT2872) &&
3022             !rt2x00_rt(rt2x00dev, RT2883) &&
3023             !rt2x00_rt(rt2x00dev, RT3070) &&
3024             !rt2x00_rt(rt2x00dev, RT3071) &&
3025             !rt2x00_rt(rt2x00dev, RT3090) &&
3026             !rt2x00_rt(rt2x00dev, RT3390) &&
3027             !rt2x00_rt(rt2x00dev, RT3572)) {
3028                 ERROR(rt2x00dev, "Invalid RT chipset detected.\n");
3029                 return -ENODEV;
3030         }
3031
3032         if (!rt2x00_rf(rt2x00dev, RF2820) &&
3033             !rt2x00_rf(rt2x00dev, RF2850) &&
3034             !rt2x00_rf(rt2x00dev, RF2720) &&
3035             !rt2x00_rf(rt2x00dev, RF2750) &&
3036             !rt2x00_rf(rt2x00dev, RF3020) &&
3037             !rt2x00_rf(rt2x00dev, RF2020) &&
3038             !rt2x00_rf(rt2x00dev, RF3021) &&
3039             !rt2x00_rf(rt2x00dev, RF3022) &&
3040             !rt2x00_rf(rt2x00dev, RF3052) &&
3041             !rt2x00_rf(rt2x00dev, RF3320)) {
3042                 ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
3043                 return -ENODEV;
3044         }
3045
3046         /*
3047          * Identify default antenna configuration.
3048          */
3049         rt2x00dev->default_ant.tx =
3050             rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH);
3051         rt2x00dev->default_ant.rx =
3052             rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH);
3053
3054         /*
3055          * Read frequency offset and RF programming sequence.
3056          */
3057         rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom);
3058         rt2x00dev->freq_offset = rt2x00_get_field16(eeprom, EEPROM_FREQ_OFFSET);
3059
3060         /*
3061          * Read external LNA informations.
3062          */
3063         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
3064
3065         if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_EXTERNAL_LNA_5G))
3066                 __set_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags);
3067         if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_EXTERNAL_LNA_2G))
3068                 __set_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags);
3069
3070         /*
3071          * Detect if this device has an hardware controlled radio.
3072          */
3073         if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_HW_RADIO))
3074                 __set_bit(CONFIG_SUPPORT_HW_BUTTON, &rt2x00dev->flags);
3075
3076         /*
3077          * Store led settings, for correct led behaviour.
3078          */
3079 #ifdef CONFIG_RT2X00_LIB_LEDS
3080         rt2800_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO);
3081         rt2800_init_led(rt2x00dev, &rt2x00dev->led_assoc, LED_TYPE_ASSOC);
3082         rt2800_init_led(rt2x00dev, &rt2x00dev->led_qual, LED_TYPE_QUALITY);
3083
3084         rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &rt2x00dev->led_mcu_reg);
3085 #endif /* CONFIG_RT2X00_LIB_LEDS */
3086
3087         return 0;
3088 }
3089 EXPORT_SYMBOL_GPL(rt2800_init_eeprom);
3090
3091 /*
3092  * RF value list for rt28xx
3093  * Supports: 2.4 GHz (all) & 5.2 GHz (RF2850 & RF2750)
3094  */
3095 static const struct rf_channel rf_vals[] = {
3096         { 1,  0x18402ecc, 0x184c0786, 0x1816b455, 0x1800510b },
3097         { 2,  0x18402ecc, 0x184c0786, 0x18168a55, 0x1800519f },
3098         { 3,  0x18402ecc, 0x184c078a, 0x18168a55, 0x1800518b },
3099         { 4,  0x18402ecc, 0x184c078a, 0x18168a55, 0x1800519f },
3100         { 5,  0x18402ecc, 0x184c078e, 0x18168a55, 0x1800518b },
3101         { 6,  0x18402ecc, 0x184c078e, 0x18168a55, 0x1800519f },
3102         { 7,  0x18402ecc, 0x184c0792, 0x18168a55, 0x1800518b },
3103         { 8,  0x18402ecc, 0x184c0792, 0x18168a55, 0x1800519f },
3104         { 9,  0x18402ecc, 0x184c0796, 0x18168a55, 0x1800518b },
3105         { 10, 0x18402ecc, 0x184c0796, 0x18168a55, 0x1800519f },
3106         { 11, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800518b },
3107         { 12, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800519f },
3108         { 13, 0x18402ecc, 0x184c079e, 0x18168a55, 0x1800518b },
3109         { 14, 0x18402ecc, 0x184c07a2, 0x18168a55, 0x18005193 },
3110
3111         /* 802.11 UNI / HyperLan 2 */
3112         { 36, 0x18402ecc, 0x184c099a, 0x18158a55, 0x180ed1a3 },
3113         { 38, 0x18402ecc, 0x184c099e, 0x18158a55, 0x180ed193 },
3114         { 40, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed183 },
3115         { 44, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed1a3 },
3116         { 46, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed18b },
3117         { 48, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed19b },
3118         { 52, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed193 },
3119         { 54, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed1a3 },
3120         { 56, 0x18402ec8, 0x184c068e, 0x18158a55, 0x180ed18b },
3121         { 60, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed183 },
3122         { 62, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed193 },
3123         { 64, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed1a3 },
3124
3125         /* 802.11 HyperLan 2 */
3126         { 100, 0x18402ec8, 0x184c06b2, 0x18178a55, 0x180ed783 },
3127         { 102, 0x18402ec8, 0x184c06b2, 0x18578a55, 0x180ed793 },
3128         { 104, 0x18402ec8, 0x185c06b2, 0x18578a55, 0x180ed1a3 },
3129         { 108, 0x18402ecc, 0x185c0a32, 0x18578a55, 0x180ed193 },
3130         { 110, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed183 },
3131         { 112, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed19b },
3132         { 116, 0x18402ecc, 0x184c0a3a, 0x18178a55, 0x180ed1a3 },
3133         { 118, 0x18402ecc, 0x184c0a3e, 0x18178a55, 0x180ed193 },
3134         { 120, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed183 },
3135         { 124, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed193 },
3136         { 126, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed15b },
3137         { 128, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed1a3 },
3138         { 132, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed18b },
3139         { 134, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed193 },
3140         { 136, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed19b },
3141         { 140, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed183 },
3142
3143         /* 802.11 UNII */
3144         { 149, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed1a7 },
3145         { 151, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed187 },
3146         { 153, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed18f },
3147         { 157, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed19f },
3148         { 159, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed1a7 },
3149         { 161, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed187 },
3150         { 165, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed197 },
3151         { 167, 0x18402ec4, 0x184c03d2, 0x18179855, 0x1815531f },
3152         { 169, 0x18402ec4, 0x184c03d2, 0x18179855, 0x18155327 },
3153         { 171, 0x18402ec4, 0x184c03d6, 0x18179855, 0x18155307 },
3154         { 173, 0x18402ec4, 0x184c03d6, 0x18179855, 0x1815530f },
3155
3156         /* 802.11 Japan */
3157         { 184, 0x15002ccc, 0x1500491e, 0x1509be55, 0x150c0a0b },
3158         { 188, 0x15002ccc, 0x15004922, 0x1509be55, 0x150c0a13 },
3159         { 192, 0x15002ccc, 0x15004926, 0x1509be55, 0x150c0a1b },
3160         { 196, 0x15002ccc, 0x1500492a, 0x1509be55, 0x150c0a23 },
3161         { 208, 0x15002ccc, 0x1500493a, 0x1509be55, 0x150c0a13 },
3162         { 212, 0x15002ccc, 0x1500493e, 0x1509be55, 0x150c0a1b },
3163         { 216, 0x15002ccc, 0x15004982, 0x1509be55, 0x150c0a23 },
3164 };
3165
3166 /*
3167  * RF value list for rt3xxx
3168  * Supports: 2.4 GHz (all) & 5.2 GHz (RF3052)
3169  */
3170 static const struct rf_channel rf_vals_3x[] = {
3171         {1,  241, 2, 2 },
3172         {2,  241, 2, 7 },
3173         {3,  242, 2, 2 },
3174         {4,  242, 2, 7 },
3175         {5,  243, 2, 2 },
3176         {6,  243, 2, 7 },
3177         {7,  244, 2, 2 },
3178         {8,  244, 2, 7 },
3179         {9,  245, 2, 2 },
3180         {10, 245, 2, 7 },
3181         {11, 246, 2, 2 },
3182         {12, 246, 2, 7 },
3183         {13, 247, 2, 2 },
3184         {14, 248, 2, 4 },
3185
3186         /* 802.11 UNI / HyperLan 2 */
3187         {36, 0x56, 0, 4},
3188         {38, 0x56, 0, 6},
3189         {40, 0x56, 0, 8},
3190         {44, 0x57, 0, 0},
3191         {46, 0x57, 0, 2},
3192         {48, 0x57, 0, 4},
3193         {52, 0x57, 0, 8},
3194         {54, 0x57, 0, 10},
3195         {56, 0x58, 0, 0},
3196         {60, 0x58, 0, 4},
3197         {62, 0x58, 0, 6},
3198         {64, 0x58, 0, 8},
3199
3200         /* 802.11 HyperLan 2 */
3201         {100, 0x5b, 0, 8},
3202         {102, 0x5b, 0, 10},
3203         {104, 0x5c, 0, 0},
3204         {108, 0x5c, 0, 4},
3205         {110, 0x5c, 0, 6},
3206         {112, 0x5c, 0, 8},
3207         {116, 0x5d, 0, 0},
3208         {118, 0x5d, 0, 2},
3209         {120, 0x5d, 0, 4},
3210         {124, 0x5d, 0, 8},
3211         {126, 0x5d, 0, 10},
3212         {128, 0x5e, 0, 0},
3213         {132, 0x5e, 0, 4},
3214         {134, 0x5e, 0, 6},
3215         {136, 0x5e, 0, 8},
3216         {140, 0x5f, 0, 0},
3217
3218         /* 802.11 UNII */
3219         {149, 0x5f, 0, 9},
3220         {151, 0x5f, 0, 11},
3221         {153, 0x60, 0, 1},
3222         {157, 0x60, 0, 5},
3223         {159, 0x60, 0, 7},
3224         {161, 0x60, 0, 9},
3225         {165, 0x61, 0, 1},
3226         {167, 0x61, 0, 3},
3227         {169, 0x61, 0, 5},
3228         {171, 0x61, 0, 7},
3229         {173, 0x61, 0, 9},
3230 };
3231
3232 int rt2800_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
3233 {
3234         struct hw_mode_spec *spec = &rt2x00dev->spec;
3235         struct channel_info *info;
3236         char *default_power1;
3237         char *default_power2;
3238         unsigned int i;
3239         unsigned short max_power;
3240         u16 eeprom;
3241
3242         /*
3243          * Disable powersaving as default on PCI devices.
3244          */
3245         if (rt2x00_is_pci(rt2x00dev) || rt2x00_is_soc(rt2x00dev))
3246                 rt2x00dev->hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
3247
3248         /*
3249          * Initialize all hw fields.
3250          */
3251         rt2x00dev->hw->flags =
3252             IEEE80211_HW_SIGNAL_DBM |
3253             IEEE80211_HW_SUPPORTS_PS |
3254             IEEE80211_HW_PS_NULLFUNC_STACK |
3255             IEEE80211_HW_AMPDU_AGGREGATION;
3256         /*
3257          * Don't set IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING for USB devices
3258          * unless we are capable of sending the buffered frames out after the
3259          * DTIM transmission using rt2x00lib_beacondone. This will send out
3260          * multicast and broadcast traffic immediately instead of buffering it
3261          * infinitly and thus dropping it after some time.
3262          */
3263         if (!rt2x00_is_usb(rt2x00dev))
3264                 rt2x00dev->hw->flags |=
3265                         IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING;
3266
3267         SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev);
3268         SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
3269                                 rt2x00_eeprom_addr(rt2x00dev,
3270                                                    EEPROM_MAC_ADDR_0));
3271
3272         /*
3273          * As rt2800 has a global fallback table we cannot specify
3274          * more then one tx rate per frame but since the hw will
3275          * try several rates (based on the fallback table) we should
3276          * initialize max_report_rates to the maximum number of rates
3277          * we are going to try. Otherwise mac80211 will truncate our
3278          * reported tx rates and the rc algortihm will end up with
3279          * incorrect data.
3280          */
3281         rt2x00dev->hw->max_rates = 1;
3282         rt2x00dev->hw->max_report_rates = 7;
3283         rt2x00dev->hw->max_rate_tries = 1;
3284
3285         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom);
3286
3287         /*
3288          * Initialize hw_mode information.
3289          */
3290         spec->supported_bands = SUPPORT_BAND_2GHZ;
3291         spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM;
3292
3293         if (rt2x00_rf(rt2x00dev, RF2820) ||
3294             rt2x00_rf(rt2x00dev, RF2720)) {
3295                 spec->num_channels = 14;
3296                 spec->channels = rf_vals;
3297         } else if (rt2x00_rf(rt2x00dev, RF2850) ||
3298                    rt2x00_rf(rt2x00dev, RF2750)) {
3299                 spec->supported_bands |= SUPPORT_BAND_5GHZ;
3300                 spec->num_channels = ARRAY_SIZE(rf_vals);
3301                 spec->channels = rf_vals;
3302         } else if (rt2x00_rf(rt2x00dev, RF3020) ||
3303                    rt2x00_rf(rt2x00dev, RF2020) ||
3304                    rt2x00_rf(rt2x00dev, RF3021) ||
3305                    rt2x00_rf(rt2x00dev, RF3022) ||
3306                    rt2x00_rf(rt2x00dev, RF3320)) {
3307                 spec->num_channels = 14;
3308                 spec->channels = rf_vals_3x;
3309         } else if (rt2x00_rf(rt2x00dev, RF3052)) {
3310                 spec->supported_bands |= SUPPORT_BAND_5GHZ;
3311                 spec->num_channels = ARRAY_SIZE(rf_vals_3x);
3312                 spec->channels = rf_vals_3x;
3313         }
3314
3315         /*
3316          * Initialize HT information.
3317          */
3318         if (!rt2x00_rf(rt2x00dev, RF2020))
3319                 spec->ht.ht_supported = true;
3320         else
3321                 spec->ht.ht_supported = false;
3322
3323         spec->ht.cap =
3324             IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
3325             IEEE80211_HT_CAP_GRN_FLD |
3326             IEEE80211_HT_CAP_SGI_20 |
3327             IEEE80211_HT_CAP_SGI_40;
3328
3329         if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) >= 2)
3330                 spec->ht.cap |= IEEE80211_HT_CAP_TX_STBC;
3331
3332         spec->ht.cap |=
3333             rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) <<
3334                 IEEE80211_HT_CAP_RX_STBC_SHIFT;
3335
3336         spec->ht.ampdu_factor = 3;
3337         spec->ht.ampdu_density = 4;
3338         spec->ht.mcs.tx_params =
3339             IEEE80211_HT_MCS_TX_DEFINED |
3340             IEEE80211_HT_MCS_TX_RX_DIFF |
3341             ((rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) - 1) <<
3342                 IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT);
3343
3344         switch (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH)) {
3345         case 3:
3346                 spec->ht.mcs.rx_mask[2] = 0xff;
3347         case 2:
3348                 spec->ht.mcs.rx_mask[1] = 0xff;
3349         case 1:
3350                 spec->ht.mcs.rx_mask[0] = 0xff;
3351                 spec->ht.mcs.rx_mask[4] = 0x1; /* MCS32 */
3352                 break;
3353         }
3354
3355         /*
3356          * Create channel information array
3357          */
3358         info = kcalloc(spec->num_channels, sizeof(*info), GFP_KERNEL);
3359         if (!info)
3360                 return -ENOMEM;
3361
3362         spec->channels_info = info;
3363
3364         rt2x00_eeprom_read(rt2x00dev, EEPROM_MAX_TX_POWER, &eeprom);
3365         max_power = rt2x00_get_field16(eeprom, EEPROM_MAX_TX_POWER_24GHZ);
3366         default_power1 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG1);
3367         default_power2 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG2);
3368
3369         for (i = 0; i < 14; i++) {
3370                 info[i].max_power = max_power;
3371                 info[i].default_power1 = TXPOWER_G_FROM_DEV(default_power1[i]);
3372                 info[i].default_power2 = TXPOWER_G_FROM_DEV(default_power2[i]);
3373         }
3374
3375         if (spec->num_channels > 14) {
3376                 max_power = rt2x00_get_field16(eeprom, EEPROM_MAX_TX_POWER_5GHZ);
3377                 default_power1 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A1);
3378                 default_power2 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A2);
3379
3380                 for (i = 14; i < spec->num_channels; i++) {
3381                         info[i].max_power = max_power;
3382                         info[i].default_power1 = TXPOWER_A_FROM_DEV(default_power1[i]);
3383                         info[i].default_power2 = TXPOWER_A_FROM_DEV(default_power2[i]);
3384                 }
3385         }
3386
3387         return 0;
3388 }
3389 EXPORT_SYMBOL_GPL(rt2800_probe_hw_mode);
3390
3391 /*
3392  * IEEE80211 stack callback functions.
3393  */
3394 void rt2800_get_tkip_seq(struct ieee80211_hw *hw, u8 hw_key_idx, u32 *iv32,
3395                          u16 *iv16)
3396 {
3397         struct rt2x00_dev *rt2x00dev = hw->priv;
3398         struct mac_iveiv_entry iveiv_entry;
3399         u32 offset;
3400
3401         offset = MAC_IVEIV_ENTRY(hw_key_idx);
3402         rt2800_register_multiread(rt2x00dev, offset,
3403                                       &iveiv_entry, sizeof(iveiv_entry));
3404
3405         memcpy(iv16, &iveiv_entry.iv[0], sizeof(*iv16));
3406         memcpy(iv32, &iveiv_entry.iv[4], sizeof(*iv32));
3407 }
3408 EXPORT_SYMBOL_GPL(rt2800_get_tkip_seq);
3409
3410 int rt2800_set_rts_threshold(struct ieee80211_hw *hw, u32 value)
3411 {
3412         struct rt2x00_dev *rt2x00dev = hw->priv;
3413         u32 reg;
3414         bool enabled = (value < IEEE80211_MAX_RTS_THRESHOLD);
3415
3416         rt2800_register_read(rt2x00dev, TX_RTS_CFG, &reg);
3417         rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_THRES, value);
3418         rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg);
3419
3420         rt2800_register_read(rt2x00dev, CCK_PROT_CFG, &reg);
3421         rt2x00_set_field32(&reg, CCK_PROT_CFG_RTS_TH_EN, enabled);
3422         rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg);
3423
3424         rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
3425         rt2x00_set_field32(&reg, OFDM_PROT_CFG_RTS_TH_EN, enabled);
3426         rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
3427
3428         rt2800_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
3429         rt2x00_set_field32(&reg, MM20_PROT_CFG_RTS_TH_EN, enabled);
3430         rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
3431
3432         rt2800_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
3433         rt2x00_set_field32(&reg, MM40_PROT_CFG_RTS_TH_EN, enabled);
3434         rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
3435
3436         rt2800_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
3437         rt2x00_set_field32(&reg, GF20_PROT_CFG_RTS_TH_EN, enabled);
3438         rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
3439
3440         rt2800_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
3441         rt2x00_set_field32(&reg, GF40_PROT_CFG_RTS_TH_EN, enabled);
3442         rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
3443
3444         return 0;
3445 }
3446 EXPORT_SYMBOL_GPL(rt2800_set_rts_threshold);
3447
3448 int rt2800_conf_tx(struct ieee80211_hw *hw, u16 queue_idx,
3449                    const struct ieee80211_tx_queue_params *params)
3450 {
3451         struct rt2x00_dev *rt2x00dev = hw->priv;
3452         struct data_queue *queue;
3453         struct rt2x00_field32 field;
3454         int retval;
3455         u32 reg;
3456         u32 offset;
3457
3458         /*
3459          * First pass the configuration through rt2x00lib, that will
3460          * update the queue settings and validate the input. After that
3461          * we are free to update the registers based on the value
3462          * in the queue parameter.
3463          */
3464         retval = rt2x00mac_conf_tx(hw, queue_idx, params);
3465         if (retval)
3466                 return retval;
3467
3468         /*
3469          * We only need to perform additional register initialization
3470          * for WMM queues/
3471          */
3472         if (queue_idx >= 4)
3473                 return 0;
3474
3475         queue = rt2x00queue_get_queue(rt2x00dev, queue_idx);
3476
3477         /* Update WMM TXOP register */
3478         offset = WMM_TXOP0_CFG + (sizeof(u32) * (!!(queue_idx & 2)));
3479         field.bit_offset = (queue_idx & 1) * 16;
3480         field.bit_mask = 0xffff << field.bit_offset;
3481
3482         rt2800_register_read(rt2x00dev, offset, &reg);
3483         rt2x00_set_field32(&reg, field, queue->txop);
3484         rt2800_register_write(rt2x00dev, offset, reg);
3485
3486         /* Update WMM registers */
3487         field.bit_offset = queue_idx * 4;
3488         field.bit_mask = 0xf << field.bit_offset;
3489
3490         rt2800_register_read(rt2x00dev, WMM_AIFSN_CFG, &reg);
3491         rt2x00_set_field32(&reg, field, queue->aifs);
3492         rt2800_register_write(rt2x00dev, WMM_AIFSN_CFG, reg);
3493
3494         rt2800_register_read(rt2x00dev, WMM_CWMIN_CFG, &reg);
3495         rt2x00_set_field32(&reg, field, queue->cw_min);
3496         rt2800_register_write(rt2x00dev, WMM_CWMIN_CFG, reg);
3497
3498         rt2800_register_read(rt2x00dev, WMM_CWMAX_CFG, &reg);
3499         rt2x00_set_field32(&reg, field, queue->cw_max);
3500         rt2800_register_write(rt2x00dev, WMM_CWMAX_CFG, reg);
3501
3502         /* Update EDCA registers */
3503         offset = EDCA_AC0_CFG + (sizeof(u32) * queue_idx);
3504
3505         rt2800_register_read(rt2x00dev, offset, &reg);
3506         rt2x00_set_field32(&reg, EDCA_AC0_CFG_TX_OP, queue->txop);
3507         rt2x00_set_field32(&reg, EDCA_AC0_CFG_AIFSN, queue->aifs);
3508         rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMIN, queue->cw_min);
3509         rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMAX, queue->cw_max);
3510         rt2800_register_write(rt2x00dev, offset, reg);
3511
3512         return 0;
3513 }
3514 EXPORT_SYMBOL_GPL(rt2800_conf_tx);
3515
3516 u64 rt2800_get_tsf(struct ieee80211_hw *hw)
3517 {
3518         struct rt2x00_dev *rt2x00dev = hw->priv;
3519         u64 tsf;
3520         u32 reg;
3521
3522         rt2800_register_read(rt2x00dev, TSF_TIMER_DW1, &reg);
3523         tsf = (u64) rt2x00_get_field32(reg, TSF_TIMER_DW1_HIGH_WORD) << 32;
3524         rt2800_register_read(rt2x00dev, TSF_TIMER_DW0, &reg);
3525         tsf |= rt2x00_get_field32(reg, TSF_TIMER_DW0_LOW_WORD);
3526
3527         return tsf;
3528 }
3529 EXPORT_SYMBOL_GPL(rt2800_get_tsf);
3530
3531 int rt2800_ampdu_action(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
3532                         enum ieee80211_ampdu_mlme_action action,
3533                         struct ieee80211_sta *sta, u16 tid, u16 *ssn)
3534 {
3535         int ret = 0;
3536
3537         switch (action) {
3538         case IEEE80211_AMPDU_RX_START:
3539         case IEEE80211_AMPDU_RX_STOP:
3540                 /*
3541                  * The hw itself takes care of setting up BlockAck mechanisms.
3542                  * So, we only have to allow mac80211 to nagotiate a BlockAck
3543                  * agreement. Once that is done, the hw will BlockAck incoming
3544                  * AMPDUs without further setup.
3545                  */
3546                 break;
3547         case IEEE80211_AMPDU_TX_START:
3548                 ieee80211_start_tx_ba_cb_irqsafe(vif, sta->addr, tid);
3549                 break;
3550         case IEEE80211_AMPDU_TX_STOP:
3551                 ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid);
3552                 break;
3553         case IEEE80211_AMPDU_TX_OPERATIONAL:
3554                 break;
3555         default:
3556                 WARNING((struct rt2x00_dev *)hw->priv, "Unknown AMPDU action\n");
3557         }
3558
3559         return ret;
3560 }
3561 EXPORT_SYMBOL_GPL(rt2800_ampdu_action);
3562
3563 int rt2800_get_survey(struct ieee80211_hw *hw, int idx,
3564                       struct survey_info *survey)
3565 {
3566         struct rt2x00_dev *rt2x00dev = hw->priv;
3567         struct ieee80211_conf *conf = &hw->conf;
3568         u32 idle, busy, busy_ext;
3569
3570         if (idx != 0)
3571                 return -ENOENT;
3572
3573         survey->channel = conf->channel;
3574
3575         rt2800_register_read(rt2x00dev, CH_IDLE_STA, &idle);
3576         rt2800_register_read(rt2x00dev, CH_BUSY_STA, &busy);
3577         rt2800_register_read(rt2x00dev, CH_BUSY_STA_SEC, &busy_ext);
3578
3579         if (idle || busy) {
3580                 survey->filled = SURVEY_INFO_CHANNEL_TIME |
3581                                  SURVEY_INFO_CHANNEL_TIME_BUSY |
3582                                  SURVEY_INFO_CHANNEL_TIME_EXT_BUSY;
3583
3584                 survey->channel_time = (idle + busy) / 1000;
3585                 survey->channel_time_busy = busy / 1000;
3586                 survey->channel_time_ext_busy = busy_ext / 1000;
3587         }
3588
3589         return 0;
3590
3591 }
3592 EXPORT_SYMBOL_GPL(rt2800_get_survey);
3593
3594 MODULE_AUTHOR(DRV_PROJECT ", Bartlomiej Zolnierkiewicz");
3595 MODULE_VERSION(DRV_VERSION);
3596 MODULE_DESCRIPTION("Ralink RT2800 library");
3597 MODULE_LICENSE("GPL");