drivers/net/wireless/rt2x00/rt2800lib.c

   1 /*
   2         Copyright (C) 2010 Willow Garage <http://www.willowgarage.com>
   3         Copyright (C) 2010 Ivo van Doorn <IvDoorn@gmail.com>
   4         Copyright (C) 2009 Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>
   5         Copyright (C) 2009 Gertjan van Wingerde <gwingerde@gmail.com>
   6
   7         Based on the original rt2800pci.c and rt2800usb.c.
   8           Copyright (C) 2009 Alban Browaeys <prahal@yahoo.com>
   9           Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org>
  10           Copyright (C) 2009 Luis Correia <luis.f.correia@gmail.com>
  11           Copyright (C) 2009 Mattias Nissler <mattias.nissler@gmx.de>
  12           Copyright (C) 2009 Mark Asselstine <asselsm@gmail.com>
  13           Copyright (C) 2009 Xose Vazquez Perez <xose.vazquez@gmail.com>
  14           <http://rt2x00.serialmonkey.com>
  15
  16         This program is free software; you can redistribute it and/or modify
  17         it under the terms of the GNU General Public License as published by
  18         the Free Software Foundation; either version 2 of the License, or
  19         (at your option) any later version.
  20
  21         This program is distributed in the hope that it will be useful,
  22         but WITHOUT ANY WARRANTY; without even the implied warranty of
  23         MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  24         GNU General Public License for more details.
  25
  26         You should have received a copy of the GNU General Public License
  27         along with this program; if not, write to the
  28         Free Software Foundation, Inc.,
  29         59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  30  */
  31
  32 /*
  33         Module: rt2800lib
  34         Abstract: rt2800 generic device routines.
  35  */
  36
  37 #include <linux/crc-ccitt.h>
  38 #include <linux/kernel.h>
  39 #include <linux/module.h>
  40 #include <linux/slab.h>
  41
  42 #include "rt2x00.h"
  43 #include "rt2800lib.h"
  44 #include "rt2800.h"
  45
  46 /*
  47  * Register access.
  48  * All access to the CSR registers will go through the methods
  49  * rt2800_register_read and rt2800_register_write.
  50  * BBP and RF register require indirect register access,
  51  * and use the CSR registers BBPCSR and RFCSR to achieve this.
  52  * These indirect registers work with busy bits,
  53  * and we will try maximal REGISTER_BUSY_COUNT times to access
  54  * the register while taking a REGISTER_BUSY_DELAY us delay
  55  * between each attampt. When the busy bit is still set at that time,
  56  * the access attempt is considered to have failed,
  57  * and we will print an error.
  58  * The _lock versions must be used if you already hold the csr_mutex
  59  */
  60 #define WAIT_FOR_BBP(__dev, __reg) \
  61         rt2800_regbusy_read((__dev), BBP_CSR_CFG, BBP_CSR_CFG_BUSY, (__reg))
  62 #define WAIT_FOR_RFCSR(__dev, __reg) \
  63         rt2800_regbusy_read((__dev), RF_CSR_CFG, RF_CSR_CFG_BUSY, (__reg))
  64 #define WAIT_FOR_RF(__dev, __reg) \
  65         rt2800_regbusy_read((__dev), RF_CSR_CFG0, RF_CSR_CFG0_BUSY, (__reg))
  66 #define WAIT_FOR_MCU(__dev, __reg) \
  67         rt2800_regbusy_read((__dev), H2M_MAILBOX_CSR, \
  68                             H2M_MAILBOX_CSR_OWNER, (__reg))
  69
  70 static inline bool rt2800_is_305x_soc(struct rt2x00_dev *rt2x00dev)
  71 {
  72         /* check for rt2872 on SoC */
  73         if (!rt2x00_is_soc(rt2x00dev) ||
  74             !rt2x00_rt(rt2x00dev, RT2872))
  75                 return false;
  76
  77         /* we know for sure that these rf chipsets are used on rt305x boards */
  78         if (rt2x00_rf(rt2x00dev, RF3020) ||
  79             rt2x00_rf(rt2x00dev, RF3021) ||
  80             rt2x00_rf(rt2x00dev, RF3022))
  81                 return true;
  82
  83         WARNING(rt2x00dev, "Unknown RF chipset on rt305x\n");
  84         return false;
  85 }
  86
  87 static void rt2800_bbp_write(struct rt2x00_dev *rt2x00dev,
  88                              const unsigned int word, const u8 value)
  89 {
  90         u32 reg;
  91
  92         mutex_lock(&rt2x00dev->csr_mutex);
  93
  94         /*
  95          * Wait until the BBP becomes available, afterwards we
  96          * can safely write the new data into the register.
  97          */
  98         if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
  99                 reg = 0;
 100                 rt2x00_set_field32(&reg, BBP_CSR_CFG_VALUE, value);
 101                 rt2x00_set_field32(&reg, BBP_CSR_CFG_REGNUM, word);
 102                 rt2x00_set_field32(&reg, BBP_CSR_CFG_BUSY, 1);
 103                 rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 0);
 104                 rt2x00_set_field32(&reg, BBP_CSR_CFG_BBP_RW_MODE, 1);
 105
 106                 rt2800_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg);
 107         }
 108
 109         mutex_unlock(&rt2x00dev->csr_mutex);
 110 }
 111
 112 static void rt2800_bbp_read(struct rt2x00_dev *rt2x00dev,
 113                             const unsigned int word, u8 *value)
 114 {
 115         u32 reg;
 116
 117         mutex_lock(&rt2x00dev->csr_mutex);
 118
 119         /*
 120          * Wait until the BBP becomes available, afterwards we
 121          * can safely write the read request into the register.
 122          * After the data has been written, we wait until hardware
 123          * returns the correct value, if at any time the register
 124          * doesn't become available in time, reg will be 0xffffffff
 125          * which means we return 0xff to the caller.
 126          */
 127         if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
 128                 reg = 0;
 129                 rt2x00_set_field32(&reg, BBP_CSR_CFG_REGNUM, word);
 130                 rt2x00_set_field32(&reg, BBP_CSR_CFG_BUSY, 1);
 131                 rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 1);
 132                 rt2x00_set_field32(&reg, BBP_CSR_CFG_BBP_RW_MODE, 1);
 133
 134                 rt2800_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg);
 135
 136                 WAIT_FOR_BBP(rt2x00dev, &reg);
 137         }
 138
 139         *value = rt2x00_get_field32(reg, BBP_CSR_CFG_VALUE);
 140
 141         mutex_unlock(&rt2x00dev->csr_mutex);
 142 }
 143
 144 static void rt2800_rfcsr_write(struct rt2x00_dev *rt2x00dev,
 145                                const unsigned int word, const u8 value)
 146 {
 147         u32 reg;
 148
 149         mutex_lock(&rt2x00dev->csr_mutex);
 150
 151         /*
 152          * Wait until the RFCSR becomes available, afterwards we
 153          * can safely write the new data into the register.
 154          */
 155         if (WAIT_FOR_RFCSR(rt2x00dev, &reg)) {
 156                 reg = 0;
 157                 rt2x00_set_field32(&reg, RF_CSR_CFG_DATA, value);
 158                 rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM, word);
 159                 rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE, 1);
 160                 rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY, 1);
 161
 162                 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
 163         }
 164
 165         mutex_unlock(&rt2x00dev->csr_mutex);
 166 }
 167
 168 static void rt2800_rfcsr_read(struct rt2x00_dev *rt2x00dev,
 169                               const unsigned int word, u8 *value)
 170 {
 171         u32 reg;
 172
 173         mutex_lock(&rt2x00dev->csr_mutex);
 174
 175         /*
 176          * Wait until the RFCSR becomes available, afterwards we
 177          * can safely write the read request into the register.
 178          * After the data has been written, we wait until hardware
 179          * returns the correct value, if at any time the register
 180          * doesn't become available in time, reg will be 0xffffffff
 181          * which means we return 0xff to the caller.
 182          */
 183         if (WAIT_FOR_RFCSR(rt2x00dev, &reg)) {
 184                 reg = 0;
 185                 rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM, word);
 186                 rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE, 0);
 187                 rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY, 1);
 188
 189                 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
 190
 191                 WAIT_FOR_RFCSR(rt2x00dev, &reg);
 192         }
 193
 194         *value = rt2x00_get_field32(reg, RF_CSR_CFG_DATA);
 195
 196         mutex_unlock(&rt2x00dev->csr_mutex);
 197 }
 198
 199 static void rt2800_rf_write(struct rt2x00_dev *rt2x00dev,
 200                             const unsigned int word, const u32 value)
 201 {
 202         u32 reg;
 203
 204         mutex_lock(&rt2x00dev->csr_mutex);
 205
 206         /*
 207          * Wait until the RF becomes available, afterwards we
 208          * can safely write the new data into the register.
 209          */
 210         if (WAIT_FOR_RF(rt2x00dev, &reg)) {
 211                 reg = 0;
 212                 rt2x00_set_field32(&reg, RF_CSR_CFG0_REG_VALUE_BW, value);
 213                 rt2x00_set_field32(&reg, RF_CSR_CFG0_STANDBYMODE, 0);
 214                 rt2x00_set_field32(&reg, RF_CSR_CFG0_SEL, 0);
 215                 rt2x00_set_field32(&reg, RF_CSR_CFG0_BUSY, 1);
 216
 217                 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG0, reg);
 218                 rt2x00_rf_write(rt2x00dev, word, value);
 219         }
 220
 221         mutex_unlock(&rt2x00dev->csr_mutex);
 222 }
 223
 224 static int rt2800_enable_wlan_rt3290(struct rt2x00_dev *rt2x00dev)
 225 {
 226         u32 reg;
 227         int i, count;
 228
 229         rt2800_register_read(rt2x00dev, WLAN_FUN_CTRL, &reg);
 230         if (rt2x00_get_field32(reg, WLAN_EN))
 231                 return 0;
 232
 233         rt2x00_set_field32(&reg, WLAN_GPIO_OUT_OE_BIT_ALL, 0xff);
 234         rt2x00_set_field32(&reg, FRC_WL_ANT_SET, 1);
 235         rt2x00_set_field32(&reg, WLAN_CLK_EN, 0);
 236         rt2x00_set_field32(&reg, WLAN_EN, 1);
 237         rt2800_register_write(rt2x00dev, WLAN_FUN_CTRL, reg);
 238
 239         udelay(REGISTER_BUSY_DELAY);
 240
 241         count = 0;
 242         do {
 243                 /*
 244                  * Check PLL_LD & XTAL_RDY.
 245                  */
 246                 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
 247                         rt2800_register_read(rt2x00dev, CMB_CTRL, &reg);
 248                         if (rt2x00_get_field32(reg, PLL_LD) &&
 249                             rt2x00_get_field32(reg, XTAL_RDY))
 250                                 break;
 251                         udelay(REGISTER_BUSY_DELAY);
 252                 }
 253
 254                 if (i >= REGISTER_BUSY_COUNT) {
 255
 256                         if (count >= 10)
 257                                 return -EIO;
 258
 259                         rt2800_register_write(rt2x00dev, 0x58, 0x018);
 260                         udelay(REGISTER_BUSY_DELAY);
 261                         rt2800_register_write(rt2x00dev, 0x58, 0x418);
 262                         udelay(REGISTER_BUSY_DELAY);
 263                         rt2800_register_write(rt2x00dev, 0x58, 0x618);
 264                         udelay(REGISTER_BUSY_DELAY);
 265                         count++;
 266                 } else {
 267                         count = 0;
 268                 }
 269
 270                 rt2800_register_read(rt2x00dev, WLAN_FUN_CTRL, &reg);
 271                 rt2x00_set_field32(&reg, PCIE_APP0_CLK_REQ, 0);
 272                 rt2x00_set_field32(&reg, WLAN_CLK_EN, 1);
 273                 rt2x00_set_field32(&reg, WLAN_RESET, 1);
 274                 rt2800_register_write(rt2x00dev, WLAN_FUN_CTRL, reg);
 275                 udelay(10);
 276                 rt2x00_set_field32(&reg, WLAN_RESET, 0);
 277                 rt2800_register_write(rt2x00dev, WLAN_FUN_CTRL, reg);
 278                 udelay(10);
 279                 rt2800_register_write(rt2x00dev, INT_SOURCE_CSR, 0x7fffffff);
 280         } while (count != 0);
 281
 282         return 0;
 283 }
 284
 285 void rt2800_mcu_request(struct rt2x00_dev *rt2x00dev,
 286                         const u8 command, const u8 token,
 287                         const u8 arg0, const u8 arg1)
 288 {
 289         u32 reg;
 290
 291         /*
 292          * SOC devices don't support MCU requests.
 293          */
 294         if (rt2x00_is_soc(rt2x00dev))
 295                 return;
 296
 297         mutex_lock(&rt2x00dev->csr_mutex);
 298
 299         /*
 300          * Wait until the MCU becomes available, afterwards we
 301          * can safely write the new data into the register.
 302          */
 303         if (WAIT_FOR_MCU(rt2x00dev, &reg)) {
 304                 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_OWNER, 1);
 305                 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_CMD_TOKEN, token);
 306                 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG0, arg0);
 307                 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG1, arg1);
 308                 rt2800_register_write_lock(rt2x00dev, H2M_MAILBOX_CSR, reg);
 309
 310                 reg = 0;
 311                 rt2x00_set_field32(&reg, HOST_CMD_CSR_HOST_COMMAND, command);
 312                 rt2800_register_write_lock(rt2x00dev, HOST_CMD_CSR, reg);
 313         }
 314
 315         mutex_unlock(&rt2x00dev->csr_mutex);
 316 }
 317 EXPORT_SYMBOL_GPL(rt2800_mcu_request);
 318
 319 int rt2800_wait_csr_ready(struct rt2x00_dev *rt2x00dev)
 320 {
 321         unsigned int i = 0;
 322         u32 reg;
 323
 324         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
 325                 rt2800_register_read(rt2x00dev, MAC_CSR0, &reg);
 326                 if (reg && reg != ~0)
 327                         return 0;
 328                 msleep(1);
 329         }
 330
 331         ERROR(rt2x00dev, "Unstable hardware.\n");
 332         return -EBUSY;
 333 }
 334 EXPORT_SYMBOL_GPL(rt2800_wait_csr_ready);
 335
 336 int rt2800_wait_wpdma_ready(struct rt2x00_dev *rt2x00dev)
 337 {
 338         unsigned int i;
 339         u32 reg;
 340
 341         /*
 342          * Some devices are really slow to respond here. Wait a whole second
 343          * before timing out.
 344          */
 345         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
 346                 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
 347                 if (!rt2x00_get_field32(reg, WPDMA_GLO_CFG_TX_DMA_BUSY) &&
 348                     !rt2x00_get_field32(reg, WPDMA_GLO_CFG_RX_DMA_BUSY))
 349                         return 0;
 350
 351                 msleep(10);
 352         }
 353
 354         ERROR(rt2x00dev, "WPDMA TX/RX busy [0x%08x].\n", reg);
 355         return -EACCES;
 356 }
 357 EXPORT_SYMBOL_GPL(rt2800_wait_wpdma_ready);
 358
 359 void rt2800_disable_wpdma(struct rt2x00_dev *rt2x00dev)
 360 {
 361         u32 reg;
 362
 363         rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
 364         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
 365         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
 366         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
 367         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
 368         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
 369         rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
 370 }
 371 EXPORT_SYMBOL_GPL(rt2800_disable_wpdma);
 372
 373 static bool rt2800_check_firmware_crc(const u8 *data, const size_t len)
 374 {
 375         u16 fw_crc;
 376         u16 crc;
 377
 378         /*
 379          * The last 2 bytes in the firmware array are the crc checksum itself,
 380          * this means that we should never pass those 2 bytes to the crc
 381          * algorithm.
 382          */
 383         fw_crc = (data[len - 2] << 8 | data[len - 1]);
 384
 385         /*
 386          * Use the crc ccitt algorithm.
 387          * This will return the same value as the legacy driver which
 388          * used bit ordering reversion on the both the firmware bytes
 389          * before input input as well as on the final output.
 390          * Obviously using crc ccitt directly is much more efficient.
 391          */
 392         crc = crc_ccitt(~0, data, len - 2);
 393
 394         /*
 395          * There is a small difference between the crc-itu-t + bitrev and
 396          * the crc-ccitt crc calculation. In the latter method the 2 bytes
 397          * will be swapped, use swab16 to convert the crc to the correct
 398          * value.
 399          */
 400         crc = swab16(crc);
 401
 402         return fw_crc == crc;
 403 }
 404
 405 int rt2800_check_firmware(struct rt2x00_dev *rt2x00dev,
 406                           const u8 *data, const size_t len)
 407 {
 408         size_t offset = 0;
 409         size_t fw_len;
 410         bool multiple;
 411
 412         /*
 413          * PCI(e) & SOC devices require firmware with a length
 414          * of 8kb. USB devices require firmware files with a length
 415          * of 4kb. Certain USB chipsets however require different firmware,
 416          * which Ralink only provides attached to the original firmware
 417          * file. Thus for USB devices, firmware files have a length
 418          * which is a multiple of 4kb. The firmware for rt3290 chip also
 419          * have a length which is a multiple of 4kb.
 420          */
 421         if (rt2x00_is_usb(rt2x00dev) || rt2x00_rt(rt2x00dev, RT3290))
 422                 fw_len = 4096;
 423         else
 424                 fw_len = 8192;
 425
 426         multiple = true;
 427         /*
 428          * Validate the firmware length
 429          */
 430         if (len != fw_len && (!multiple || (len % fw_len) != 0))
 431                 return FW_BAD_LENGTH;
 432
 433         /*
 434          * Check if the chipset requires one of the upper parts
 435          * of the firmware.
 436          */
 437         if (rt2x00_is_usb(rt2x00dev) &&
 438             !rt2x00_rt(rt2x00dev, RT2860) &&
 439             !rt2x00_rt(rt2x00dev, RT2872) &&
 440             !rt2x00_rt(rt2x00dev, RT3070) &&
 441             ((len / fw_len) == 1))
 442                 return FW_BAD_VERSION;
 443
 444         /*
 445          * 8kb firmware files must be checked as if it were
 446          * 2 separate firmware files.
 447          */
 448         while (offset < len) {
 449                 if (!rt2800_check_firmware_crc(data + offset, fw_len))
 450                         return FW_BAD_CRC;
 451
 452                 offset += fw_len;
 453         }
 454
 455         return FW_OK;
 456 }
 457 EXPORT_SYMBOL_GPL(rt2800_check_firmware);
 458
 459 int rt2800_load_firmware(struct rt2x00_dev *rt2x00dev,
 460                          const u8 *data, const size_t len)
 461 {
 462         unsigned int i;
 463         u32 reg;
 464         int retval;
 465
 466         if (rt2x00_rt(rt2x00dev, RT3290)) {
 467                 retval = rt2800_enable_wlan_rt3290(rt2x00dev);
 468                 if (retval)
 469                         return -EBUSY;
 470         }
 471
 472         /*
 473          * If driver doesn't wake up firmware here,
 474          * rt2800_load_firmware will hang forever when interface is up again.
 475          */
 476         rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0x00000000);
 477
 478         /*
 479          * Wait for stable hardware.
 480          */
 481         if (rt2800_wait_csr_ready(rt2x00dev))
 482                 return -EBUSY;
 483
 484         if (rt2x00_is_pci(rt2x00dev)) {
 485                 if (rt2x00_rt(rt2x00dev, RT3290) ||
 486                     rt2x00_rt(rt2x00dev, RT3572) ||
 487                     rt2x00_rt(rt2x00dev, RT5390) ||
 488                     rt2x00_rt(rt2x00dev, RT5392)) {
 489                         rt2800_register_read(rt2x00dev, AUX_CTRL, &reg);
 490                         rt2x00_set_field32(&reg, AUX_CTRL_FORCE_PCIE_CLK, 1);
 491                         rt2x00_set_field32(&reg, AUX_CTRL_WAKE_PCIE_EN, 1);
 492                         rt2800_register_write(rt2x00dev, AUX_CTRL, reg);
 493                 }
 494                 rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000002);
 495         }
 496
 497         rt2800_disable_wpdma(rt2x00dev);
 498
 499         /*
 500          * Write firmware to the device.
 501          */
 502         rt2800_drv_write_firmware(rt2x00dev, data, len);
 503
 504         /*
 505          * Wait for device to stabilize.
 506          */
 507         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
 508                 rt2800_register_read(rt2x00dev, PBF_SYS_CTRL, &reg);
 509                 if (rt2x00_get_field32(reg, PBF_SYS_CTRL_READY))
 510                         break;
 511                 msleep(1);
 512         }
 513
 514         if (i == REGISTER_BUSY_COUNT) {
 515                 ERROR(rt2x00dev, "PBF system register not ready.\n");
 516                 return -EBUSY;
 517         }
 518
 519         /*
 520          * Disable DMA, will be reenabled later when enabling
 521          * the radio.
 522          */
 523         rt2800_disable_wpdma(rt2x00dev);
 524
 525         /*
 526          * Initialize firmware.
 527          */
 528         rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
 529         rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
 530         if (rt2x00_is_usb(rt2x00dev))
 531                 rt2800_register_write(rt2x00dev, H2M_INT_SRC, 0);
 532         msleep(1);
 533
 534         return 0;
 535 }
 536 EXPORT_SYMBOL_GPL(rt2800_load_firmware);
 537
 538 void rt2800_write_tx_data(struct queue_entry *entry,
 539                           struct txentry_desc *txdesc)
 540 {
 541         __le32 *txwi = rt2800_drv_get_txwi(entry);
 542         u32 word;
 543
 544         /*
 545          * Initialize TX Info descriptor
 546          */
 547         rt2x00_desc_read(txwi, 0, &word);
 548         rt2x00_set_field32(&word, TXWI_W0_FRAG,
 549                            test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
 550         rt2x00_set_field32(&word, TXWI_W0_MIMO_PS,
 551                            test_bit(ENTRY_TXD_HT_MIMO_PS, &txdesc->flags));
 552         rt2x00_set_field32(&word, TXWI_W0_CF_ACK, 0);
 553         rt2x00_set_field32(&word, TXWI_W0_TS,
 554                            test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
 555         rt2x00_set_field32(&word, TXWI_W0_AMPDU,
 556                            test_bit(ENTRY_TXD_HT_AMPDU, &txdesc->flags));
 557         rt2x00_set_field32(&word, TXWI_W0_MPDU_DENSITY,
 558                            txdesc->u.ht.mpdu_density);
 559         rt2x00_set_field32(&word, TXWI_W0_TX_OP, txdesc->u.ht.txop);
 560         rt2x00_set_field32(&word, TXWI_W0_MCS, txdesc->u.ht.mcs);
 561         rt2x00_set_field32(&word, TXWI_W0_BW,
 562                            test_bit(ENTRY_TXD_HT_BW_40, &txdesc->flags));
 563         rt2x00_set_field32(&word, TXWI_W0_SHORT_GI,
 564                            test_bit(ENTRY_TXD_HT_SHORT_GI, &txdesc->flags));
 565         rt2x00_set_field32(&word, TXWI_W0_STBC, txdesc->u.ht.stbc);
 566         rt2x00_set_field32(&word, TXWI_W0_PHYMODE, txdesc->rate_mode);
 567         rt2x00_desc_write(txwi, 0, word);
 568
 569         rt2x00_desc_read(txwi, 1, &word);
 570         rt2x00_set_field32(&word, TXWI_W1_ACK,
 571                            test_bit(ENTRY_TXD_ACK, &txdesc->flags));
 572         rt2x00_set_field32(&word, TXWI_W1_NSEQ,
 573                            test_bit(ENTRY_TXD_GENERATE_SEQ, &txdesc->flags));
 574         rt2x00_set_field32(&word, TXWI_W1_BW_WIN_SIZE, txdesc->u.ht.ba_size);
 575         rt2x00_set_field32(&word, TXWI_W1_WIRELESS_CLI_ID,
 576                            test_bit(ENTRY_TXD_ENCRYPT, &txdesc->flags) ?
 577                            txdesc->key_idx : txdesc->u.ht.wcid);
 578         rt2x00_set_field32(&word, TXWI_W1_MPDU_TOTAL_BYTE_COUNT,
 579                            txdesc->length);
 580         rt2x00_set_field32(&word, TXWI_W1_PACKETID_QUEUE, entry->queue->qid);
 581         rt2x00_set_field32(&word, TXWI_W1_PACKETID_ENTRY, (entry->entry_idx % 3) + 1);
 582         rt2x00_desc_write(txwi, 1, word);
 583
 584         /*
 585          * Always write 0 to IV/EIV fields, hardware will insert the IV
 586          * from the IVEIV register when TXD_W3_WIV is set to 0.
 587          * When TXD_W3_WIV is set to 1 it will use the IV data
 588          * from the descriptor. The TXWI_W1_WIRELESS_CLI_ID indicates which
 589          * crypto entry in the registers should be used to encrypt the frame.
 590          */
 591         _rt2x00_desc_write(txwi, 2, 0 /* skbdesc->iv[0] */);
 592         _rt2x00_desc_write(txwi, 3, 0 /* skbdesc->iv[1] */);
 593 }
 594 EXPORT_SYMBOL_GPL(rt2800_write_tx_data);
 595
 596 static int rt2800_agc_to_rssi(struct rt2x00_dev *rt2x00dev, u32 rxwi_w2)
 597 {
 598         s8 rssi0 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI0);
 599         s8 rssi1 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI1);
 600         s8 rssi2 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI2);
 601         u16 eeprom;
 602         u8 offset0;
 603         u8 offset1;
 604         u8 offset2;
 605
 606         if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ) {
 607                 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG, &eeprom);
 608                 offset0 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG_OFFSET0);
 609                 offset1 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG_OFFSET1);
 610                 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &eeprom);
 611                 offset2 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG2_OFFSET2);
 612         } else {
 613                 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A, &eeprom);
 614                 offset0 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A_OFFSET0);
 615                 offset1 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A_OFFSET1);
 616                 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &eeprom);
 617                 offset2 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A2_OFFSET2);
 618         }
 619
 620         /*
 621          * Convert the value from the descriptor into the RSSI value
 622          * If the value in the descriptor is 0, it is considered invalid
 623          * and the default (extremely low) rssi value is assumed
 624          */
 625         rssi0 = (rssi0) ? (-12 - offset0 - rt2x00dev->lna_gain - rssi0) : -128;
 626         rssi1 = (rssi1) ? (-12 - offset1 - rt2x00dev->lna_gain - rssi1) : -128;
 627         rssi2 = (rssi2) ? (-12 - offset2 - rt2x00dev->lna_gain - rssi2) : -128;
 628
 629         /*
 630          * mac80211 only accepts a single RSSI value. Calculating the
 631          * average doesn't deliver a fair answer either since -60:-60 would
 632          * be considered equally good as -50:-70 while the second is the one
 633          * which gives less energy...
 634          */
 635         rssi0 = max(rssi0, rssi1);
 636         return (int)max(rssi0, rssi2);
 637 }
 638
 639 void rt2800_process_rxwi(struct queue_entry *entry,
 640                          struct rxdone_entry_desc *rxdesc)
 641 {
 642         __le32 *rxwi = (__le32 *) entry->skb->data;
 643         u32 word;
 644
 645         rt2x00_desc_read(rxwi, 0, &word);
 646
 647         rxdesc->cipher = rt2x00_get_field32(word, RXWI_W0_UDF);
 648         rxdesc->size = rt2x00_get_field32(word, RXWI_W0_MPDU_TOTAL_BYTE_COUNT);
 649
 650         rt2x00_desc_read(rxwi, 1, &word);
 651
 652         if (rt2x00_get_field32(word, RXWI_W1_SHORT_GI))
 653                 rxdesc->flags |= RX_FLAG_SHORT_GI;
 654
 655         if (rt2x00_get_field32(word, RXWI_W1_BW))
 656                 rxdesc->flags |= RX_FLAG_40MHZ;
 657
 658         /*
 659          * Detect RX rate, always use MCS as signal type.
 660          */
 661         rxdesc->dev_flags |= RXDONE_SIGNAL_MCS;
 662         rxdesc->signal = rt2x00_get_field32(word, RXWI_W1_MCS);
 663         rxdesc->rate_mode = rt2x00_get_field32(word, RXWI_W1_PHYMODE);
 664
 665         /*
 666          * Mask of 0x8 bit to remove the short preamble flag.
 667          */
 668         if (rxdesc->rate_mode == RATE_MODE_CCK)
 669                 rxdesc->signal &= ~0x8;
 670
 671         rt2x00_desc_read(rxwi, 2, &word);
 672
 673         /*
 674          * Convert descriptor AGC value to RSSI value.
 675          */
 676         rxdesc->rssi = rt2800_agc_to_rssi(entry->queue->rt2x00dev, word);
 677
 678         /*
 679          * Remove RXWI descriptor from start of buffer.
 680          */
 681         skb_pull(entry->skb, RXWI_DESC_SIZE);
 682 }
 683 EXPORT_SYMBOL_GPL(rt2800_process_rxwi);
 684
 685 void rt2800_txdone_entry(struct queue_entry *entry, u32 status, __le32 *txwi)
 686 {
 687         struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
 688         struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
 689         struct txdone_entry_desc txdesc;
 690         u32 word;
 691         u16 mcs, real_mcs;
 692         int aggr, ampdu;
 693
 694         /*
 695          * Obtain the status about this packet.
 696          */
 697         txdesc.flags = 0;
 698         rt2x00_desc_read(txwi, 0, &word);
 699
 700         mcs = rt2x00_get_field32(word, TXWI_W0_MCS);
 701         ampdu = rt2x00_get_field32(word, TXWI_W0_AMPDU);
 702
 703         real_mcs = rt2x00_get_field32(status, TX_STA_FIFO_MCS);
 704         aggr = rt2x00_get_field32(status, TX_STA_FIFO_TX_AGGRE);
 705
 706         /*
 707          * If a frame was meant to be sent as a single non-aggregated MPDU
 708          * but ended up in an aggregate the used tx rate doesn't correlate
 709          * with the one specified in the TXWI as the whole aggregate is sent
 710          * with the same rate.
 711          *
 712          * For example: two frames are sent to rt2x00, the first one sets
 713          * AMPDU=1 and requests MCS7 whereas the second frame sets AMDPU=0
 714          * and requests MCS15. If the hw aggregates both frames into one
 715          * AMDPU the tx status for both frames will contain MCS7 although
 716          * the frame was sent successfully.
 717          *
 718          * Hence, replace the requested rate with the real tx rate to not
 719          * confuse the rate control algortihm by providing clearly wrong
 720          * data.
 721          */
 722         if (unlikely(aggr == 1 && ampdu == 0 && real_mcs != mcs)) {
 723                 skbdesc->tx_rate_idx = real_mcs;
 724                 mcs = real_mcs;
 725         }
 726
 727         if (aggr == 1 || ampdu == 1)
 728                 __set_bit(TXDONE_AMPDU, &txdesc.flags);
 729
 730         /*
 731          * Ralink has a retry mechanism using a global fallback
 732          * table. We setup this fallback table to try the immediate
 733          * lower rate for all rates. In the TX_STA_FIFO, the MCS field
 734          * always contains the MCS used for the last transmission, be
 735          * it successful or not.
 736          */
 737         if (rt2x00_get_field32(status, TX_STA_FIFO_TX_SUCCESS)) {
 738                 /*
 739                  * Transmission succeeded. The number of retries is
 740                  * mcs - real_mcs
 741                  */
 742                 __set_bit(TXDONE_SUCCESS, &txdesc.flags);
 743                 txdesc.retry = ((mcs > real_mcs) ? mcs - real_mcs : 0);
 744         } else {
 745                 /*
 746                  * Transmission failed. The number of retries is
 747                  * always 7 in this case (for a total number of 8
 748                  * frames sent).
 749                  */
 750                 __set_bit(TXDONE_FAILURE, &txdesc.flags);
 751                 txdesc.retry = rt2x00dev->long_retry;
 752         }
 753
 754         /*
 755          * the frame was retried at least once
 756          * -> hw used fallback rates
 757          */
 758         if (txdesc.retry)
 759                 __set_bit(TXDONE_FALLBACK, &txdesc.flags);
 760
 761         rt2x00lib_txdone(entry, &txdesc);
 762 }
 763 EXPORT_SYMBOL_GPL(rt2800_txdone_entry);
 764
 765 void rt2800_write_beacon(struct queue_entry *entry, struct txentry_desc *txdesc)
 766 {
 767         struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
 768         struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
 769         unsigned int beacon_base;
 770         unsigned int padding_len;
 771         u32 orig_reg, reg;
 772
 773         /*
 774          * Disable beaconing while we are reloading the beacon data,
 775          * otherwise we might be sending out invalid data.
 776          */
 777         rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
 778         orig_reg = reg;
 779         rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
 780         rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
 781
 782         /*
 783          * Add space for the TXWI in front of the skb.
 784          */
 785         memset(skb_push(entry->skb, TXWI_DESC_SIZE), 0, TXWI_DESC_SIZE);
 786
 787         /*
 788          * Register descriptor details in skb frame descriptor.
 789          */
 790         skbdesc->flags |= SKBDESC_DESC_IN_SKB;
 791         skbdesc->desc = entry->skb->data;
 792         skbdesc->desc_len = TXWI_DESC_SIZE;
 793
 794         /*
 795          * Add the TXWI for the beacon to the skb.
 796          */
 797         rt2800_write_tx_data(entry, txdesc);
 798
 799         /*
 800          * Dump beacon to userspace through debugfs.
 801          */
 802         rt2x00debug_dump_frame(rt2x00dev, DUMP_FRAME_BEACON, entry->skb);
 803
 804         /*
 805          * Write entire beacon with TXWI and padding to register.
 806          */
 807         padding_len = roundup(entry->skb->len, 4) - entry->skb->len;
 808         if (padding_len && skb_pad(entry->skb, padding_len)) {
 809                 ERROR(rt2x00dev, "Failure padding beacon, aborting\n");
 810                 /* skb freed by skb_pad() on failure */
 811                 entry->skb = NULL;
 812                 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, orig_reg);
 813                 return;
 814         }
 815
 816         beacon_base = HW_BEACON_OFFSET(entry->entry_idx);
 817         rt2800_register_multiwrite(rt2x00dev, beacon_base, entry->skb->data,
 818                                    entry->skb->len + padding_len);
 819
 820         /*
 821          * Enable beaconing again.
 822          */
 823         rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 1);
 824         rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
 825
 826         /*
 827          * Clean up beacon skb.
 828          */
 829         dev_kfree_skb_any(entry->skb);
 830         entry->skb = NULL;
 831 }
 832 EXPORT_SYMBOL_GPL(rt2800_write_beacon);
 833
 834 static inline void rt2800_clear_beacon_register(struct rt2x00_dev *rt2x00dev,
 835                                                 unsigned int beacon_base)
 836 {
 837         int i;
 838
 839         /*
 840          * For the Beacon base registers we only need to clear
 841          * the whole TXWI which (when set to 0) will invalidate
 842          * the entire beacon.
 843          */
 844         for (i = 0; i < TXWI_DESC_SIZE; i += sizeof(__le32))
 845                 rt2800_register_write(rt2x00dev, beacon_base + i, 0);
 846 }
 847
 848 void rt2800_clear_beacon(struct queue_entry *entry)
 849 {
 850         struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
 851         u32 reg;
 852
 853         /*
 854          * Disable beaconing while we are reloading the beacon data,
 855          * otherwise we might be sending out invalid data.
 856          */
 857         rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
 858         rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
 859         rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
 860
 861         /*
 862          * Clear beacon.
 863          */
 864         rt2800_clear_beacon_register(rt2x00dev,
 865                                      HW_BEACON_OFFSET(entry->entry_idx));
 866
 867         /*
 868          * Enabled beaconing again.
 869          */
 870         rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 1);
 871         rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
 872 }
 873 EXPORT_SYMBOL_GPL(rt2800_clear_beacon);
 874
 875 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
 876 const struct rt2x00debug rt2800_rt2x00debug = {
 877         .owner  = THIS_MODULE,
 878         .csr    = {
 879                 .read           = rt2800_register_read,
 880                 .write          = rt2800_register_write,
 881                 .flags          = RT2X00DEBUGFS_OFFSET,
 882                 .word_base      = CSR_REG_BASE,
 883                 .word_size      = sizeof(u32),
 884                 .word_count     = CSR_REG_SIZE / sizeof(u32),
 885         },
 886         .eeprom = {
 887                 .read           = rt2x00_eeprom_read,
 888                 .write          = rt2x00_eeprom_write,
 889                 .word_base      = EEPROM_BASE,
 890                 .word_size      = sizeof(u16),
 891                 .word_count     = EEPROM_SIZE / sizeof(u16),
 892         },
 893         .bbp    = {
 894                 .read           = rt2800_bbp_read,
 895                 .write          = rt2800_bbp_write,
 896                 .word_base      = BBP_BASE,
 897                 .word_size      = sizeof(u8),
 898                 .word_count     = BBP_SIZE / sizeof(u8),
 899         },
 900         .rf     = {
 901                 .read           = rt2x00_rf_read,
 902                 .write          = rt2800_rf_write,
 903                 .word_base      = RF_BASE,
 904                 .word_size      = sizeof(u32),
 905                 .word_count     = RF_SIZE / sizeof(u32),
 906         },
 907         .rfcsr  = {
 908                 .read           = rt2800_rfcsr_read,
 909                 .write          = rt2800_rfcsr_write,
 910                 .word_base      = RFCSR_BASE,
 911                 .word_size      = sizeof(u8),
 912                 .word_count     = RFCSR_SIZE / sizeof(u8),
 913         },
 914 };
 915 EXPORT_SYMBOL_GPL(rt2800_rt2x00debug);
 916 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
 917
 918 int rt2800_rfkill_poll(struct rt2x00_dev *rt2x00dev)
 919 {
 920         u32 reg;
 921
 922         if (rt2x00_rt(rt2x00dev, RT3290)) {
 923                 rt2800_register_read(rt2x00dev, WLAN_FUN_CTRL, &reg);
 924                 return rt2x00_get_field32(reg, WLAN_GPIO_IN_BIT0);
 925         } else {
 926                 rt2800_register_read(rt2x00dev, GPIO_CTRL, &reg);
 927                 return rt2x00_get_field32(reg, GPIO_CTRL_VAL2);
 928         }
 929 }
 930 EXPORT_SYMBOL_GPL(rt2800_rfkill_poll);
 931
 932 #ifdef CONFIG_RT2X00_LIB_LEDS
 933 static void rt2800_brightness_set(struct led_classdev *led_cdev,
 934                                   enum led_brightness brightness)
 935 {
 936         struct rt2x00_led *led =
 937             container_of(led_cdev, struct rt2x00_led, led_dev);
 938         unsigned int enabled = brightness != LED_OFF;
 939         unsigned int bg_mode =
 940             (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_2GHZ);
 941         unsigned int polarity =
 942                 rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
 943                                    EEPROM_FREQ_LED_POLARITY);
 944         unsigned int ledmode =
 945                 rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
 946                                    EEPROM_FREQ_LED_MODE);
 947         u32 reg;
 948
 949         /* Check for SoC (SOC devices don't support MCU requests) */
 950         if (rt2x00_is_soc(led->rt2x00dev)) {
 951                 rt2800_register_read(led->rt2x00dev, LED_CFG, &reg);
 952
 953                 /* Set LED Polarity */
 954                 rt2x00_set_field32(&reg, LED_CFG_LED_POLAR, polarity);
 955
 956                 /* Set LED Mode */
 957                 if (led->type == LED_TYPE_RADIO) {
 958                         rt2x00_set_field32(&reg, LED_CFG_G_LED_MODE,
 959                                            enabled ? 3 : 0);
 960                 } else if (led->type == LED_TYPE_ASSOC) {
 961                         rt2x00_set_field32(&reg, LED_CFG_Y_LED_MODE,
 962                                            enabled ? 3 : 0);
 963                 } else if (led->type == LED_TYPE_QUALITY) {
 964                         rt2x00_set_field32(&reg, LED_CFG_R_LED_MODE,
 965                                            enabled ? 3 : 0);
 966                 }
 967
 968                 rt2800_register_write(led->rt2x00dev, LED_CFG, reg);
 969
 970         } else {
 971                 if (led->type == LED_TYPE_RADIO) {
 972                         rt2800_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
 973                                               enabled ? 0x20 : 0);
 974                 } else if (led->type == LED_TYPE_ASSOC) {
 975                         rt2800_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
 976                                               enabled ? (bg_mode ? 0x60 : 0xa0) : 0x20);
 977                 } else if (led->type == LED_TYPE_QUALITY) {
 978                         /*
 979                          * The brightness is divided into 6 levels (0 - 5),
 980                          * The specs tell us the following levels:
 981                          *      0, 1 ,3, 7, 15, 31
 982                          * to determine the level in a simple way we can simply
 983                          * work with bitshifting:
 984                          *      (1 << level) - 1
 985                          */
 986                         rt2800_mcu_request(led->rt2x00dev, MCU_LED_STRENGTH, 0xff,
 987                                               (1 << brightness / (LED_FULL / 6)) - 1,
 988                                               polarity);
 989                 }
 990         }
 991 }
 992
 993 static void rt2800_init_led(struct rt2x00_dev *rt2x00dev,
 994                      struct rt2x00_led *led, enum led_type type)
 995 {
 996         led->rt2x00dev = rt2x00dev;
 997         led->type = type;
 998         led->led_dev.brightness_set = rt2800_brightness_set;
 999         led->flags = LED_INITIALIZED;
1000 }
1001 #endif /* CONFIG_RT2X00_LIB_LEDS */
1002
1003 /*
1004  * Configuration handlers.
1005  */
1006 static void rt2800_config_wcid(struct rt2x00_dev *rt2x00dev,
1007                                const u8 *address,
1008                                int wcid)
1009 {
1010         struct mac_wcid_entry wcid_entry;
1011         u32 offset;
1012
1013         offset = MAC_WCID_ENTRY(wcid);
1014
1015         memset(&wcid_entry, 0xff, sizeof(wcid_entry));
1016         if (address)
1017                 memcpy(wcid_entry.mac, address, ETH_ALEN);
1018
1019         rt2800_register_multiwrite(rt2x00dev, offset,
1020                                       &wcid_entry, sizeof(wcid_entry));
1021 }
1022
1023 static void rt2800_delete_wcid_attr(struct rt2x00_dev *rt2x00dev, int wcid)
1024 {
1025         u32 offset;
1026         offset = MAC_WCID_ATTR_ENTRY(wcid);
1027         rt2800_register_write(rt2x00dev, offset, 0);
1028 }
1029
1030 static void rt2800_config_wcid_attr_bssidx(struct rt2x00_dev *rt2x00dev,
1031                                            int wcid, u32 bssidx)
1032 {
1033         u32 offset = MAC_WCID_ATTR_ENTRY(wcid);
1034         u32 reg;
1035
1036         /*
1037          * The BSS Idx numbers is split in a main value of 3 bits,
1038          * and a extended field for adding one additional bit to the value.
1039          */
1040         rt2800_register_read(rt2x00dev, offset, &reg);
1041         rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_BSS_IDX, (bssidx & 0x7));
1042         rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_BSS_IDX_EXT,
1043                            (bssidx & 0x8) >> 3);
1044         rt2800_register_write(rt2x00dev, offset, reg);
1045 }
1046
1047 static void rt2800_config_wcid_attr_cipher(struct rt2x00_dev *rt2x00dev,
1048                                            struct rt2x00lib_crypto *crypto,
1049                                            struct ieee80211_key_conf *key)
1050 {
1051         struct mac_iveiv_entry iveiv_entry;
1052         u32 offset;
1053         u32 reg;
1054
1055         offset = MAC_WCID_ATTR_ENTRY(key->hw_key_idx);
1056
1057         if (crypto->cmd == SET_KEY) {
1058                 rt2800_register_read(rt2x00dev, offset, &reg);
1059                 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_KEYTAB,
1060                                    !!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE));
1061                 /*
1062                  * Both the cipher as the BSS Idx numbers are split in a main
1063                  * value of 3 bits, and a extended field for adding one additional
1064                  * bit to the value.
1065                  */
1066                 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER,
1067                                    (crypto->cipher & 0x7));
1068                 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER_EXT,
1069                                    (crypto->cipher & 0x8) >> 3);
1070                 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_RX_WIUDF, crypto->cipher);
1071                 rt2800_register_write(rt2x00dev, offset, reg);
1072         } else {
1073                 /* Delete the cipher without touching the bssidx */
1074                 rt2800_register_read(rt2x00dev, offset, &reg);
1075                 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_KEYTAB, 0);
1076                 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER, 0);
1077                 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER_EXT, 0);
1078                 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_RX_WIUDF, 0);
1079                 rt2800_register_write(rt2x00dev, offset, reg);
1080         }
1081
1082         offset = MAC_IVEIV_ENTRY(key->hw_key_idx);
1083
1084         memset(&iveiv_entry, 0, sizeof(iveiv_entry));
1085         if ((crypto->cipher == CIPHER_TKIP) ||
1086             (crypto->cipher == CIPHER_TKIP_NO_MIC) ||
1087             (crypto->cipher == CIPHER_AES))
1088                 iveiv_entry.iv[3] |= 0x20;
1089         iveiv_entry.iv[3] |= key->keyidx << 6;
1090         rt2800_register_multiwrite(rt2x00dev, offset,
1091                                       &iveiv_entry, sizeof(iveiv_entry));
1092 }
1093
1094 int rt2800_config_shared_key(struct rt2x00_dev *rt2x00dev,
1095                              struct rt2x00lib_crypto *crypto,
1096                              struct ieee80211_key_conf *key)
1097 {
1098         struct hw_key_entry key_entry;
1099         struct rt2x00_field32 field;
1100         u32 offset;
1101         u32 reg;
1102
1103         if (crypto->cmd == SET_KEY) {
1104                 key->hw_key_idx = (4 * crypto->bssidx) + key->keyidx;
1105
1106                 memcpy(key_entry.key, crypto->key,
1107                        sizeof(key_entry.key));
1108                 memcpy(key_entry.tx_mic, crypto->tx_mic,
1109                        sizeof(key_entry.tx_mic));
1110                 memcpy(key_entry.rx_mic, crypto->rx_mic,
1111                        sizeof(key_entry.rx_mic));
1112
1113                 offset = SHARED_KEY_ENTRY(key->hw_key_idx);
1114                 rt2800_register_multiwrite(rt2x00dev, offset,
1115                                               &key_entry, sizeof(key_entry));
1116         }
1117
1118         /*
1119          * The cipher types are stored over multiple registers
1120          * starting with SHARED_KEY_MODE_BASE each word will have
1121          * 32 bits and contains the cipher types for 2 bssidx each.
1122          * Using the correct defines correctly will cause overhead,
1123          * so just calculate the correct offset.
1124          */
1125         field.bit_offset = 4 * (key->hw_key_idx % 8);
1126         field.bit_mask = 0x7 << field.bit_offset;
1127
1128         offset = SHARED_KEY_MODE_ENTRY(key->hw_key_idx / 8);
1129
1130         rt2800_register_read(rt2x00dev, offset, &reg);
1131         rt2x00_set_field32(&reg, field,
1132                            (crypto->cmd == SET_KEY) * crypto->cipher);
1133         rt2800_register_write(rt2x00dev, offset, reg);
1134
1135         /*
1136          * Update WCID information
1137          */
1138         rt2800_config_wcid(rt2x00dev, crypto->address, key->hw_key_idx);
1139         rt2800_config_wcid_attr_bssidx(rt2x00dev, key->hw_key_idx,
1140                                        crypto->bssidx);
1141         rt2800_config_wcid_attr_cipher(rt2x00dev, crypto, key);
1142
1143         return 0;
1144 }
1145 EXPORT_SYMBOL_GPL(rt2800_config_shared_key);
1146
1147 static inline int rt2800_find_wcid(struct rt2x00_dev *rt2x00dev)
1148 {
1149         struct mac_wcid_entry wcid_entry;
1150         int idx;
1151         u32 offset;
1152
1153         /*
1154          * Search for the first free WCID entry and return the corresponding
1155          * index.
1156          *
1157          * Make sure the WCID starts _after_ the last possible shared key
1158          * entry (>32).
1159          *
1160          * Since parts of the pairwise key table might be shared with
1161          * the beacon frame buffers 6 & 7 we should only write into the
1162          * first 222 entries.
1163          */
1164         for (idx = 33; idx <= 222; idx++) {
1165                 offset = MAC_WCID_ENTRY(idx);
1166                 rt2800_register_multiread(rt2x00dev, offset, &wcid_entry,
1167                                           sizeof(wcid_entry));
1168                 if (is_broadcast_ether_addr(wcid_entry.mac))
1169                         return idx;
1170         }
1171
1172         /*
1173          * Use -1 to indicate that we don't have any more space in the WCID
1174          * table.
1175          */
1176         return -1;
1177 }
1178
1179 int rt2800_config_pairwise_key(struct rt2x00_dev *rt2x00dev,
1180                                struct rt2x00lib_crypto *crypto,
1181                                struct ieee80211_key_conf *key)
1182 {
1183         struct hw_key_entry key_entry;
1184         u32 offset;
1185
1186         if (crypto->cmd == SET_KEY) {
1187                 /*
1188                  * Allow key configuration only for STAs that are
1189                  * known by the hw.
1190                  */
1191                 if (crypto->wcid < 0)
1192                         return -ENOSPC;
1193                 key->hw_key_idx = crypto->wcid;
1194
1195                 memcpy(key_entry.key, crypto->key,
1196                        sizeof(key_entry.key));
1197                 memcpy(key_entry.tx_mic, crypto->tx_mic,
1198                        sizeof(key_entry.tx_mic));
1199                 memcpy(key_entry.rx_mic, crypto->rx_mic,
1200                        sizeof(key_entry.rx_mic));
1201
1202                 offset = PAIRWISE_KEY_ENTRY(key->hw_key_idx);
1203                 rt2800_register_multiwrite(rt2x00dev, offset,
1204                                               &key_entry, sizeof(key_entry));
1205         }
1206
1207         /*
1208          * Update WCID information
1209          */
1210         rt2800_config_wcid_attr_cipher(rt2x00dev, crypto, key);
1211
1212         return 0;
1213 }
1214 EXPORT_SYMBOL_GPL(rt2800_config_pairwise_key);
1215
1216 int rt2800_sta_add(struct rt2x00_dev *rt2x00dev, struct ieee80211_vif *vif,
1217                    struct ieee80211_sta *sta)
1218 {
1219         int wcid;
1220         struct rt2x00_sta *sta_priv = sta_to_rt2x00_sta(sta);
1221
1222         /*
1223          * Find next free WCID.
1224          */
1225         wcid = rt2800_find_wcid(rt2x00dev);
1226
1227         /*
1228          * Store selected wcid even if it is invalid so that we can
1229          * later decide if the STA is uploaded into the hw.
1230          */
1231         sta_priv->wcid = wcid;
1232
1233         /*
1234          * No space left in the device, however, we can still communicate
1235          * with the STA -> No error.
1236          */
1237         if (wcid < 0)
1238                 return 0;
1239
1240         /*
1241          * Clean up WCID attributes and write STA address to the device.
1242          */
1243         rt2800_delete_wcid_attr(rt2x00dev, wcid);
1244         rt2800_config_wcid(rt2x00dev, sta->addr, wcid);
1245         rt2800_config_wcid_attr_bssidx(rt2x00dev, wcid,
1246                                        rt2x00lib_get_bssidx(rt2x00dev, vif));
1247         return 0;
1248 }
1249 EXPORT_SYMBOL_GPL(rt2800_sta_add);
1250
1251 int rt2800_sta_remove(struct rt2x00_dev *rt2x00dev, int wcid)
1252 {
1253         /*
1254          * Remove WCID entry, no need to clean the attributes as they will
1255          * get renewed when the WCID is reused.
1256          */
1257         rt2800_config_wcid(rt2x00dev, NULL, wcid);
1258
1259         return 0;
1260 }
1261 EXPORT_SYMBOL_GPL(rt2800_sta_remove);
1262
1263 void rt2800_config_filter(struct rt2x00_dev *rt2x00dev,
1264                           const unsigned int filter_flags)
1265 {
1266         u32 reg;
1267
1268         /*
1269          * Start configuration steps.
1270          * Note that the version error will always be dropped
1271          * and broadcast frames will always be accepted since
1272          * there is no filter for it at this time.
1273          */
1274         rt2800_register_read(rt2x00dev, RX_FILTER_CFG, &reg);
1275         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CRC_ERROR,
1276                            !(filter_flags & FIF_FCSFAIL));
1277         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_PHY_ERROR,
1278                            !(filter_flags & FIF_PLCPFAIL));
1279         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_NOT_TO_ME,
1280                            !(filter_flags & FIF_PROMISC_IN_BSS));
1281         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_NOT_MY_BSSD, 0);
1282         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_VER_ERROR, 1);
1283         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_MULTICAST,
1284                            !(filter_flags & FIF_ALLMULTI));
1285         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BROADCAST, 0);
1286         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_DUPLICATE, 1);
1287         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CF_END_ACK,
1288                            !(filter_flags & FIF_CONTROL));
1289         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CF_END,
1290                            !(filter_flags & FIF_CONTROL));
1291         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_ACK,
1292                            !(filter_flags & FIF_CONTROL));
1293         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CTS,
1294                            !(filter_flags & FIF_CONTROL));
1295         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_RTS,
1296                            !(filter_flags & FIF_CONTROL));
1297         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_PSPOLL,
1298                            !(filter_flags & FIF_PSPOLL));
1299         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BA, 0);
1300         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BAR,
1301                            !(filter_flags & FIF_CONTROL));
1302         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CNTL,
1303                            !(filter_flags & FIF_CONTROL));
1304         rt2800_register_write(rt2x00dev, RX_FILTER_CFG, reg);
1305 }
1306 EXPORT_SYMBOL_GPL(rt2800_config_filter);
1307
1308 void rt2800_config_intf(struct rt2x00_dev *rt2x00dev, struct rt2x00_intf *intf,
1309                         struct rt2x00intf_conf *conf, const unsigned int flags)
1310 {
1311         u32 reg;
1312         bool update_bssid = false;
1313
1314         if (flags & CONFIG_UPDATE_TYPE) {
1315                 /*
1316                  * Enable synchronisation.
1317                  */
1318                 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
1319                 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, conf->sync);
1320                 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1321
1322                 if (conf->sync == TSF_SYNC_AP_NONE) {
1323                         /*
1324                          * Tune beacon queue transmit parameters for AP mode
1325                          */
1326                         rt2800_register_read(rt2x00dev, TBTT_SYNC_CFG, &reg);
1327                         rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_CWMIN, 0);
1328                         rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_AIFSN, 1);
1329                         rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_EXP_WIN, 32);
1330                         rt2x00_set_field32(&reg, TBTT_SYNC_CFG_TBTT_ADJUST, 0);
1331                         rt2800_register_write(rt2x00dev, TBTT_SYNC_CFG, reg);
1332                 } else {
1333                         rt2800_register_read(rt2x00dev, TBTT_SYNC_CFG, &reg);
1334                         rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_CWMIN, 4);
1335                         rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_AIFSN, 2);
1336                         rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_EXP_WIN, 32);
1337                         rt2x00_set_field32(&reg, TBTT_SYNC_CFG_TBTT_ADJUST, 16);
1338                         rt2800_register_write(rt2x00dev, TBTT_SYNC_CFG, reg);
1339                 }
1340         }
1341
1342         if (flags & CONFIG_UPDATE_MAC) {
1343                 if (flags & CONFIG_UPDATE_TYPE &&
1344                     conf->sync == TSF_SYNC_AP_NONE) {
1345                         /*
1346                          * The BSSID register has to be set to our own mac
1347                          * address in AP mode.
1348                          */
1349                         memcpy(conf->bssid, conf->mac, sizeof(conf->mac));
1350                         update_bssid = true;
1351                 }
1352
1353                 if (!is_zero_ether_addr((const u8 *)conf->mac)) {
1354                         reg = le32_to_cpu(conf->mac[1]);
1355                         rt2x00_set_field32(&reg, MAC_ADDR_DW1_UNICAST_TO_ME_MASK, 0xff);
1356                         conf->mac[1] = cpu_to_le32(reg);
1357                 }
1358
1359                 rt2800_register_multiwrite(rt2x00dev, MAC_ADDR_DW0,
1360                                               conf->mac, sizeof(conf->mac));
1361         }
1362
1363         if ((flags & CONFIG_UPDATE_BSSID) || update_bssid) {
1364                 if (!is_zero_ether_addr((const u8 *)conf->bssid)) {
1365                         reg = le32_to_cpu(conf->bssid[1]);
1366                         rt2x00_set_field32(&reg, MAC_BSSID_DW1_BSS_ID_MASK, 3);
1367                         rt2x00_set_field32(&reg, MAC_BSSID_DW1_BSS_BCN_NUM, 7);
1368                         conf->bssid[1] = cpu_to_le32(reg);
1369                 }
1370
1371                 rt2800_register_multiwrite(rt2x00dev, MAC_BSSID_DW0,
1372                                               conf->bssid, sizeof(conf->bssid));
1373         }
1374 }
1375 EXPORT_SYMBOL_GPL(rt2800_config_intf);
1376
1377 static void rt2800_config_ht_opmode(struct rt2x00_dev *rt2x00dev,
1378                                     struct rt2x00lib_erp *erp)
1379 {
1380         bool any_sta_nongf = !!(erp->ht_opmode &
1381                                 IEEE80211_HT_OP_MODE_NON_GF_STA_PRSNT);
1382         u8 protection = erp->ht_opmode & IEEE80211_HT_OP_MODE_PROTECTION;
1383         u8 mm20_mode, mm40_mode, gf20_mode, gf40_mode;
1384         u16 mm20_rate, mm40_rate, gf20_rate, gf40_rate;
1385         u32 reg;
1386
1387         /* default protection rate for HT20: OFDM 24M */
1388         mm20_rate = gf20_rate = 0x4004;
1389
1390         /* default protection rate for HT40: duplicate OFDM 24M */
1391         mm40_rate = gf40_rate = 0x4084;
1392
1393         switch (protection) {
1394         case IEEE80211_HT_OP_MODE_PROTECTION_NONE:
1395                 /*
1396                  * All STAs in this BSS are HT20/40 but there might be
1397                  * STAs not supporting greenfield mode.
1398                  * => Disable protection for HT transmissions.
1399                  */
1400                 mm20_mode = mm40_mode = gf20_mode = gf40_mode = 0;
1401
1402                 break;
1403         case IEEE80211_HT_OP_MODE_PROTECTION_20MHZ:
1404                 /*
1405                  * All STAs in this BSS are HT20 or HT20/40 but there
1406                  * might be STAs not supporting greenfield mode.
1407                  * => Protect all HT40 transmissions.
1408                  */
1409                 mm20_mode = gf20_mode = 0;
1410                 mm40_mode = gf40_mode = 2;
1411
1412                 break;
1413         case IEEE80211_HT_OP_MODE_PROTECTION_NONMEMBER:
1414                 /*
1415                  * Nonmember protection:
1416                  * According to 802.11n we _should_ protect all
1417                  * HT transmissions (but we don't have to).
1418                  *
1419                  * But if cts_protection is enabled we _shall_ protect
1420                  * all HT transmissions using a CCK rate.
1421                  *
1422                  * And if any station is non GF we _shall_ protect
1423                  * GF transmissions.
1424                  *
1425                  * We decide to protect everything
1426                  * -> fall through to mixed mode.
1427                  */
1428         case IEEE80211_HT_OP_MODE_PROTECTION_NONHT_MIXED:
1429                 /*
1430                  * Legacy STAs are present
1431                  * => Protect all HT transmissions.
1432                  */
1433                 mm20_mode = mm40_mode = gf20_mode = gf40_mode = 2;
1434
1435                 /*
1436                  * If erp protection is needed we have to protect HT
1437                  * transmissions with CCK 11M long preamble.
1438                  */
1439                 if (erp->cts_protection) {
1440                         /* don't duplicate RTS/CTS in CCK mode */
1441                         mm20_rate = mm40_rate = 0x0003;
1442                         gf20_rate = gf40_rate = 0x0003;
1443                 }
1444                 break;
1445         }
1446
1447         /* check for STAs not supporting greenfield mode */
1448         if (any_sta_nongf)
1449                 gf20_mode = gf40_mode = 2;
1450
1451         /* Update HT protection config */
1452         rt2800_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
1453         rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_RATE, mm20_rate);
1454         rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_CTRL, mm20_mode);
1455         rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
1456
1457         rt2800_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
1458         rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_RATE, mm40_rate);
1459         rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_CTRL, mm40_mode);
1460         rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
1461
1462         rt2800_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
1463         rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_RATE, gf20_rate);
1464         rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_CTRL, gf20_mode);
1465         rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
1466
1467         rt2800_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
1468         rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_RATE, gf40_rate);
1469         rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_CTRL, gf40_mode);
1470         rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
1471 }
1472
1473 void rt2800_config_erp(struct rt2x00_dev *rt2x00dev, struct rt2x00lib_erp *erp,
1474                        u32 changed)
1475 {
1476         u32 reg;
1477
1478         if (changed & BSS_CHANGED_ERP_PREAMBLE) {
1479                 rt2800_register_read(rt2x00dev, AUTO_RSP_CFG, &reg);
1480                 rt2x00_set_field32(&reg, AUTO_RSP_CFG_BAC_ACK_POLICY,
1481                                    !!erp->short_preamble);
1482                 rt2x00_set_field32(&reg, AUTO_RSP_CFG_AR_PREAMBLE,
1483                                    !!erp->short_preamble);
1484                 rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
1485         }
1486
1487         if (changed & BSS_CHANGED_ERP_CTS_PROT) {
1488                 rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
1489                 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL,
1490                                    erp->cts_protection ? 2 : 0);
1491                 rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
1492         }
1493
1494         if (changed & BSS_CHANGED_BASIC_RATES) {
1495                 rt2800_register_write(rt2x00dev, LEGACY_BASIC_RATE,
1496                                          erp->basic_rates);
1497                 rt2800_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
1498         }
1499
1500         if (changed & BSS_CHANGED_ERP_SLOT) {
1501                 rt2800_register_read(rt2x00dev, BKOFF_SLOT_CFG, &reg);
1502                 rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_SLOT_TIME,
1503                                    erp->slot_time);
1504                 rt2800_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg);
1505
1506                 rt2800_register_read(rt2x00dev, XIFS_TIME_CFG, &reg);
1507                 rt2x00_set_field32(&reg, XIFS_TIME_CFG_EIFS, erp->eifs);
1508                 rt2800_register_write(rt2x00dev, XIFS_TIME_CFG, reg);
1509         }
1510
1511         if (changed & BSS_CHANGED_BEACON_INT) {
1512                 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
1513                 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL,
1514                                    erp->beacon_int * 16);
1515                 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1516         }
1517
1518         if (changed & BSS_CHANGED_HT)
1519                 rt2800_config_ht_opmode(rt2x00dev, erp);
1520 }
1521 EXPORT_SYMBOL_GPL(rt2800_config_erp);
1522
1523 static void rt2800_config_3572bt_ant(struct rt2x00_dev *rt2x00dev)
1524 {
1525         u32 reg;
1526         u16 eeprom;
1527         u8 led_ctrl, led_g_mode, led_r_mode;
1528
1529         rt2800_register_read(rt2x00dev, GPIO_SWITCH, &reg);
1530         if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ) {
1531                 rt2x00_set_field32(&reg, GPIO_SWITCH_0, 1);
1532                 rt2x00_set_field32(&reg, GPIO_SWITCH_1, 1);
1533         } else {
1534                 rt2x00_set_field32(&reg, GPIO_SWITCH_0, 0);
1535                 rt2x00_set_field32(&reg, GPIO_SWITCH_1, 0);
1536         }
1537         rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg);
1538
1539         rt2800_register_read(rt2x00dev, LED_CFG, &reg);
1540         led_g_mode = rt2x00_get_field32(reg, LED_CFG_LED_POLAR) ? 3 : 0;
1541         led_r_mode = rt2x00_get_field32(reg, LED_CFG_LED_POLAR) ? 0 : 3;
1542         if (led_g_mode != rt2x00_get_field32(reg, LED_CFG_G_LED_MODE) ||
1543             led_r_mode != rt2x00_get_field32(reg, LED_CFG_R_LED_MODE)) {
1544                 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom);
1545                 led_ctrl = rt2x00_get_field16(eeprom, EEPROM_FREQ_LED_MODE);
1546                 if (led_ctrl == 0 || led_ctrl > 0x40) {
1547                         rt2x00_set_field32(&reg, LED_CFG_G_LED_MODE, led_g_mode);
1548                         rt2x00_set_field32(&reg, LED_CFG_R_LED_MODE, led_r_mode);
1549                         rt2800_register_write(rt2x00dev, LED_CFG, reg);
1550                 } else {
1551                         rt2800_mcu_request(rt2x00dev, MCU_BAND_SELECT, 0xff,
1552                                            (led_g_mode << 2) | led_r_mode, 1);
1553                 }
1554         }
1555 }
1556
1557 static void rt2800_set_ant_diversity(struct rt2x00_dev *rt2x00dev,
1558                                      enum antenna ant)
1559 {
1560         u32 reg;
1561         u8 eesk_pin = (ant == ANTENNA_A) ? 1 : 0;
1562         u8 gpio_bit3 = (ant == ANTENNA_A) ? 0 : 1;
1563
1564         if (rt2x00_is_pci(rt2x00dev)) {
1565                 rt2800_register_read(rt2x00dev, E2PROM_CSR, &reg);
1566                 rt2x00_set_field32(&reg, E2PROM_CSR_DATA_CLOCK, eesk_pin);
1567                 rt2800_register_write(rt2x00dev, E2PROM_CSR, reg);
1568         } else if (rt2x00_is_usb(rt2x00dev))
1569                 rt2800_mcu_request(rt2x00dev, MCU_ANT_SELECT, 0xff,
1570                                    eesk_pin, 0);
1571
1572         rt2800_register_read(rt2x00dev, GPIO_CTRL, &reg);
1573         rt2x00_set_field32(&reg, GPIO_CTRL_DIR3, 0);
1574         rt2x00_set_field32(&reg, GPIO_CTRL_VAL3, gpio_bit3);
1575         rt2800_register_write(rt2x00dev, GPIO_CTRL, reg);
1576 }
1577
1578 void rt2800_config_ant(struct rt2x00_dev *rt2x00dev, struct antenna_setup *ant)
1579 {
1580         u8 r1;
1581         u8 r3;
1582         u16 eeprom;
1583
1584         rt2800_bbp_read(rt2x00dev, 1, &r1);
1585         rt2800_bbp_read(rt2x00dev, 3, &r3);
1586
1587         if (rt2x00_rt(rt2x00dev, RT3572) &&
1588             test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags))
1589                 rt2800_config_3572bt_ant(rt2x00dev);
1590
1591         /*
1592          * Configure the TX antenna.
1593          */
1594         switch (ant->tx_chain_num) {
1595         case 1:
1596                 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 0);
1597                 break;
1598         case 2:
1599                 if (rt2x00_rt(rt2x00dev, RT3572) &&
1600                     test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags))
1601                         rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 1);
1602                 else
1603                         rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 2);
1604                 break;
1605         case 3:
1606                 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 0);
1607                 break;
1608         }
1609
1610         /*
1611          * Configure the RX antenna.
1612          */
1613         switch (ant->rx_chain_num) {
1614         case 1:
1615                 if (rt2x00_rt(rt2x00dev, RT3070) ||
1616                     rt2x00_rt(rt2x00dev, RT3090) ||
1617                     rt2x00_rt(rt2x00dev, RT3352) ||
1618                     rt2x00_rt(rt2x00dev, RT3390)) {
1619                         rt2x00_eeprom_read(rt2x00dev,
1620                                            EEPROM_NIC_CONF1, &eeprom);
1621                         if (rt2x00_get_field16(eeprom,
1622                                                 EEPROM_NIC_CONF1_ANT_DIVERSITY))
1623                                 rt2800_set_ant_diversity(rt2x00dev,
1624                                                 rt2x00dev->default_ant.rx);
1625                 }
1626                 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 0);
1627                 break;
1628         case 2:
1629                 if (rt2x00_rt(rt2x00dev, RT3572) &&
1630                     test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags)) {
1631                         rt2x00_set_field8(&r3, BBP3_RX_ADC, 1);
1632                         rt2x00_set_field8(&r3, BBP3_RX_ANTENNA,
1633                                 rt2x00dev->curr_band == IEEE80211_BAND_5GHZ);
1634                         rt2800_set_ant_diversity(rt2x00dev, ANTENNA_B);
1635                 } else {
1636                         rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 1);
1637                 }
1638                 break;
1639         case 3:
1640                 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 2);
1641                 break;
1642         }
1643
1644         rt2800_bbp_write(rt2x00dev, 3, r3);
1645         rt2800_bbp_write(rt2x00dev, 1, r1);
1646 }
1647 EXPORT_SYMBOL_GPL(rt2800_config_ant);
1648
1649 static void rt2800_config_lna_gain(struct rt2x00_dev *rt2x00dev,
1650                                    struct rt2x00lib_conf *libconf)
1651 {
1652         u16 eeprom;
1653         short lna_gain;
1654
1655         if (libconf->rf.channel <= 14) {
1656                 rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom);
1657                 lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_BG);
1658         } else if (libconf->rf.channel <= 64) {
1659                 rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom);
1660                 lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_A0);
1661         } else if (libconf->rf.channel <= 128) {
1662                 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &eeprom);
1663                 lna_gain = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG2_LNA_A1);
1664         } else {
1665                 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &eeprom);
1666                 lna_gain = rt2x00_get_field16(eeprom, EEPROM_RSSI_A2_LNA_A2);
1667         }
1668
1669         rt2x00dev->lna_gain = lna_gain;
1670 }
1671
1672 static void rt2800_config_channel_rf2xxx(struct rt2x00_dev *rt2x00dev,
1673                                          struct ieee80211_conf *conf,
1674                                          struct rf_channel *rf,
1675                                          struct channel_info *info)
1676 {
1677         rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset);
1678
1679         if (rt2x00dev->default_ant.tx_chain_num == 1)
1680                 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_TX1, 1);
1681
1682         if (rt2x00dev->default_ant.rx_chain_num == 1) {
1683                 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX1, 1);
1684                 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
1685         } else if (rt2x00dev->default_ant.rx_chain_num == 2)
1686                 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
1687
1688         if (rf->channel > 14) {
1689                 /*
1690                  * When TX power is below 0, we should increase it by 7 to
1691                  * make it a positive value (Minimum value is -7).
1692                  * However this means that values between 0 and 7 have
1693                  * double meaning, and we should set a 7DBm boost flag.
1694                  */
1695                 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A_7DBM_BOOST,
1696                                    (info->default_power1 >= 0));
1697
1698                 if (info->default_power1 < 0)
1699                         info->default_power1 += 7;
1700
1701                 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A, info->default_power1);
1702
1703                 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A_7DBM_BOOST,
1704                                    (info->default_power2 >= 0));
1705
1706                 if (info->default_power2 < 0)
1707                         info->default_power2 += 7;
1708
1709                 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A, info->default_power2);
1710         } else {
1711                 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_G, info->default_power1);
1712                 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_G, info->default_power2);
1713         }
1714
1715         rt2x00_set_field32(&rf->rf4, RF4_HT40, conf_is_ht40(conf));
1716
1717         rt2800_rf_write(rt2x00dev, 1, rf->rf1);
1718         rt2800_rf_write(rt2x00dev, 2, rf->rf2);
1719         rt2800_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
1720         rt2800_rf_write(rt2x00dev, 4, rf->rf4);
1721
1722         udelay(200);
1723
1724         rt2800_rf_write(rt2x00dev, 1, rf->rf1);
1725         rt2800_rf_write(rt2x00dev, 2, rf->rf2);
1726         rt2800_rf_write(rt2x00dev, 3, rf->rf3 | 0x00000004);
1727         rt2800_rf_write(rt2x00dev, 4, rf->rf4);
1728
1729         udelay(200);
1730
1731         rt2800_rf_write(rt2x00dev, 1, rf->rf1);
1732         rt2800_rf_write(rt2x00dev, 2, rf->rf2);
1733         rt2800_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
1734         rt2800_rf_write(rt2x00dev, 4, rf->rf4);
1735 }
1736
1737 static void rt2800_config_channel_rf3xxx(struct rt2x00_dev *rt2x00dev,
1738                                          struct ieee80211_conf *conf,
1739                                          struct rf_channel *rf,
1740                                          struct channel_info *info)
1741 {
1742         struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
1743         u8 rfcsr, calib_tx, calib_rx;
1744
1745         rt2800_rfcsr_write(rt2x00dev, 2, rf->rf1);
1746
1747         rt2800_rfcsr_read(rt2x00dev, 3, &rfcsr);
1748         rt2x00_set_field8(&rfcsr, RFCSR3_K, rf->rf3);
1749         rt2800_rfcsr_write(rt2x00dev, 3, rfcsr);
1750
1751         rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
1752         rt2x00_set_field8(&rfcsr, RFCSR6_R1, rf->rf2);
1753         rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
1754
1755         rt2800_rfcsr_read(rt2x00dev, 12, &rfcsr);
1756         rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER, info->default_power1);
1757         rt2800_rfcsr_write(rt2x00dev, 12, rfcsr);
1758
1759         rt2800_rfcsr_read(rt2x00dev, 13, &rfcsr);
1760         rt2x00_set_field8(&rfcsr, RFCSR13_TX_POWER, info->default_power2);
1761         rt2800_rfcsr_write(rt2x00dev, 13, rfcsr);
1762
1763         rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
1764         rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0);
1765         rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD,
1766                           rt2x00dev->default_ant.rx_chain_num <= 1);
1767         rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD,
1768                           rt2x00dev->default_ant.rx_chain_num <= 2);
1769         rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0);
1770         rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD,
1771                           rt2x00dev->default_ant.tx_chain_num <= 1);
1772         rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD,
1773                           rt2x00dev->default_ant.tx_chain_num <= 2);
1774         rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
1775
1776         rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
1777         rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 1);
1778         rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
1779         msleep(1);
1780         rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 0);
1781         rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
1782
1783         rt2800_rfcsr_read(rt2x00dev, 23, &rfcsr);
1784         rt2x00_set_field8(&rfcsr, RFCSR23_FREQ_OFFSET, rt2x00dev->freq_offset);
1785         rt2800_rfcsr_write(rt2x00dev, 23, rfcsr);
1786
1787         if (rt2x00_rt(rt2x00dev, RT3390)) {
1788                 calib_tx = conf_is_ht40(conf) ? 0x68 : 0x4f;
1789                 calib_rx = conf_is_ht40(conf) ? 0x6f : 0x4f;
1790         } else {
1791                 if (conf_is_ht40(conf)) {
1792                         calib_tx = drv_data->calibration_bw40;
1793                         calib_rx = drv_data->calibration_bw40;
1794                 } else {
1795                         calib_tx = drv_data->calibration_bw20;
1796                         calib_rx = drv_data->calibration_bw20;
1797                 }
1798         }
1799
1800         rt2800_rfcsr_read(rt2x00dev, 24, &rfcsr);
1801         rt2x00_set_field8(&rfcsr, RFCSR24_TX_CALIB, calib_tx);
1802         rt2800_rfcsr_write(rt2x00dev, 24, rfcsr);
1803
1804         rt2800_rfcsr_read(rt2x00dev, 31, &rfcsr);
1805         rt2x00_set_field8(&rfcsr, RFCSR31_RX_CALIB, calib_rx);
1806         rt2800_rfcsr_write(rt2x00dev, 31, rfcsr);
1807
1808         rt2800_rfcsr_read(rt2x00dev, 7, &rfcsr);
1809         rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1);
1810         rt2800_rfcsr_write(rt2x00dev, 7, rfcsr);
1811
1812         rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
1813         rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 1);
1814         rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
1815         msleep(1);
1816         rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 0);
1817         rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
1818 }
1819
1820 static void rt2800_config_channel_rf3052(struct rt2x00_dev *rt2x00dev,
1821                                          struct ieee80211_conf *conf,
1822                                          struct rf_channel *rf,
1823                                          struct channel_info *info)
1824 {
1825         struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
1826         u8 rfcsr;
1827         u32 reg;
1828
1829         if (rf->channel <= 14) {
1830                 rt2800_bbp_write(rt2x00dev, 25, drv_data->bbp25);
1831                 rt2800_bbp_write(rt2x00dev, 26, drv_data->bbp26);
1832         } else {
1833                 rt2800_bbp_write(rt2x00dev, 25, 0x09);
1834                 rt2800_bbp_write(rt2x00dev, 26, 0xff);
1835         }
1836
1837         rt2800_rfcsr_write(rt2x00dev, 2, rf->rf1);
1838         rt2800_rfcsr_write(rt2x00dev, 3, rf->rf3);
1839
1840         rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
1841         rt2x00_set_field8(&rfcsr, RFCSR6_R1, rf->rf2);
1842         if (rf->channel <= 14)
1843                 rt2x00_set_field8(&rfcsr, RFCSR6_TXDIV, 2);
1844         else
1845                 rt2x00_set_field8(&rfcsr, RFCSR6_TXDIV, 1);
1846         rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
1847
1848         rt2800_rfcsr_read(rt2x00dev, 5, &rfcsr);
1849         if (rf->channel <= 14)
1850                 rt2x00_set_field8(&rfcsr, RFCSR5_R1, 1);
1851         else
1852                 rt2x00_set_field8(&rfcsr, RFCSR5_R1, 2);
1853         rt2800_rfcsr_write(rt2x00dev, 5, rfcsr);
1854
1855         rt2800_rfcsr_read(rt2x00dev, 12, &rfcsr);
1856         if (rf->channel <= 14) {
1857                 rt2x00_set_field8(&rfcsr, RFCSR12_DR0, 3);
1858                 rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER,
1859                                   info->default_power1);
1860         } else {
1861                 rt2x00_set_field8(&rfcsr, RFCSR12_DR0, 7);
1862                 rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER,
1863                                 (info->default_power1 & 0x3) |
1864                                 ((info->default_power1 & 0xC) << 1));
1865         }
1866         rt2800_rfcsr_write(rt2x00dev, 12, rfcsr);
1867
1868         rt2800_rfcsr_read(rt2x00dev, 13, &rfcsr);
1869         if (rf->channel <= 14) {
1870                 rt2x00_set_field8(&rfcsr, RFCSR13_DR0, 3);
1871                 rt2x00_set_field8(&rfcsr, RFCSR13_TX_POWER,
1872                                   info->default_power2);
1873         } else {
1874                 rt2x00_set_field8(&rfcsr, RFCSR13_DR0, 7);
1875                 rt2x00_set_field8(&rfcsr, RFCSR13_TX_POWER,
1876                                 (info->default_power2 & 0x3) |
1877                                 ((info->default_power2 & 0xC) << 1));
1878         }
1879         rt2800_rfcsr_write(rt2x00dev, 13, rfcsr);
1880
1881         rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
1882         rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0);
1883         rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0);
1884         rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 0);
1885         rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 0);
1886         rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 0);
1887         rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 0);
1888         if (test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags)) {
1889                 if (rf->channel <= 14) {
1890                         rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 1);
1891                         rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 1);
1892                 }
1893                 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 1);
1894                 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 1);
1895         } else {
1896                 switch (rt2x00dev->default_ant.tx_chain_num) {
1897                 case 1:
1898                         rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
1899                 case 2:
1900                         rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 1);
1901                         break;
1902                 }
1903
1904                 switch (rt2x00dev->default_ant.rx_chain_num) {
1905                 case 1:
1906                         rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
1907                 case 2:
1908                         rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 1);
1909                         break;
1910                 }
1911         }
1912         rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
1913
1914         rt2800_rfcsr_read(rt2x00dev, 23, &rfcsr);
1915         rt2x00_set_field8(&rfcsr, RFCSR23_FREQ_OFFSET, rt2x00dev->freq_offset);
1916         rt2800_rfcsr_write(rt2x00dev, 23, rfcsr);
1917
1918         if (conf_is_ht40(conf)) {
1919                 rt2800_rfcsr_write(rt2x00dev, 24, drv_data->calibration_bw40);
1920                 rt2800_rfcsr_write(rt2x00dev, 31, drv_data->calibration_bw40);
1921         } else {
1922                 rt2800_rfcsr_write(rt2x00dev, 24, drv_data->calibration_bw20);
1923                 rt2800_rfcsr_write(rt2x00dev, 31, drv_data->calibration_bw20);
1924         }
1925
1926         if (rf->channel <= 14) {
1927                 rt2800_rfcsr_write(rt2x00dev, 7, 0xd8);
1928                 rt2800_rfcsr_write(rt2x00dev, 9, 0xc3);
1929                 rt2800_rfcsr_write(rt2x00dev, 10, 0xf1);
1930                 rt2800_rfcsr_write(rt2x00dev, 11, 0xb9);
1931                 rt2800_rfcsr_write(rt2x00dev, 15, 0x53);
1932                 rfcsr = 0x4c;
1933                 rt2x00_set_field8(&rfcsr, RFCSR16_TXMIXER_GAIN,
1934                                   drv_data->txmixer_gain_24g);
1935                 rt2800_rfcsr_write(rt2x00dev, 16, rfcsr);
1936                 rt2800_rfcsr_write(rt2x00dev, 17, 0x23);
1937                 rt2800_rfcsr_write(rt2x00dev, 19, 0x93);
1938                 rt2800_rfcsr_write(rt2x00dev, 20, 0xb3);
1939                 rt2800_rfcsr_write(rt2x00dev, 25, 0x15);
1940                 rt2800_rfcsr_write(rt2x00dev, 26, 0x85);
1941                 rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
1942                 rt2800_rfcsr_write(rt2x00dev, 29, 0x9b);
1943         } else {
1944                 rt2800_rfcsr_read(rt2x00dev, 7, &rfcsr);
1945                 rt2x00_set_field8(&rfcsr, RFCSR7_BIT2, 1);
1946                 rt2x00_set_field8(&rfcsr, RFCSR7_BIT3, 0);
1947                 rt2x00_set_field8(&rfcsr, RFCSR7_BIT4, 1);
1948                 rt2x00_set_field8(&rfcsr, RFCSR7_BITS67, 0);
1949                 rt2800_rfcsr_write(rt2x00dev, 7, rfcsr);
1950                 rt2800_rfcsr_write(rt2x00dev, 9, 0xc0);
1951                 rt2800_rfcsr_write(rt2x00dev, 10, 0xf1);
1952                 rt2800_rfcsr_write(rt2x00dev, 11, 0x00);
1953                 rt2800_rfcsr_write(rt2x00dev, 15, 0x43);
1954                 rfcsr = 0x7a;
1955                 rt2x00_set_field8(&rfcsr, RFCSR16_TXMIXER_GAIN,
1956                                   drv_data->txmixer_gain_5g);
1957                 rt2800_rfcsr_write(rt2x00dev, 16, rfcsr);
1958                 rt2800_rfcsr_write(rt2x00dev, 17, 0x23);
1959                 if (rf->channel <= 64) {
1960                         rt2800_rfcsr_write(rt2x00dev, 19, 0xb7);
1961                         rt2800_rfcsr_write(rt2x00dev, 20, 0xf6);
1962                         rt2800_rfcsr_write(rt2x00dev, 25, 0x3d);
1963                 } else if (rf->channel <= 128) {
1964                         rt2800_rfcsr_write(rt2x00dev, 19, 0x74);
1965                         rt2800_rfcsr_write(rt2x00dev, 20, 0xf4);
1966                         rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
1967                 } else {
1968                         rt2800_rfcsr_write(rt2x00dev, 19, 0x72);
1969                         rt2800_rfcsr_write(rt2x00dev, 20, 0xf3);
1970                         rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
1971                 }
1972                 rt2800_rfcsr_write(rt2x00dev, 26, 0x87);
1973                 rt2800_rfcsr_write(rt2x00dev, 27, 0x01);
1974                 rt2800_rfcsr_write(rt2x00dev, 29, 0x9f);
1975         }
1976
1977         rt2800_register_read(rt2x00dev, GPIO_CTRL, &reg);
1978         rt2x00_set_field32(&reg, GPIO_CTRL_DIR7, 0);
1979         if (rf->channel <= 14)
1980                 rt2x00_set_field32(&reg, GPIO_CTRL_VAL7, 1);
1981         else
1982                 rt2x00_set_field32(&reg, GPIO_CTRL_VAL7, 0);
1983         rt2800_register_write(rt2x00dev, GPIO_CTRL, reg);
1984
1985         rt2800_rfcsr_read(rt2x00dev, 7, &rfcsr);
1986         rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1);
1987         rt2800_rfcsr_write(rt2x00dev, 7, rfcsr);
1988 }
1989
1990 #define POWER_BOUND             0x27
1991 #define POWER_BOUND_5G          0x2b
1992 #define FREQ_OFFSET_BOUND       0x5f
1993
1994 static void rt2800_adjust_freq_offset(struct rt2x00_dev *rt2x00dev)
1995 {
1996         u8 rfcsr;
1997
1998         rt2800_rfcsr_read(rt2x00dev, 17, &rfcsr);
1999         if (rt2x00dev->freq_offset > FREQ_OFFSET_BOUND)
2000                 rt2x00_set_field8(&rfcsr, RFCSR17_CODE, FREQ_OFFSET_BOUND);
2001         else
2002                 rt2x00_set_field8(&rfcsr, RFCSR17_CODE, rt2x00dev->freq_offset);
2003         rt2800_rfcsr_write(rt2x00dev, 17, rfcsr);
2004 }
2005
2006 static void rt2800_config_channel_rf3290(struct rt2x00_dev *rt2x00dev,
2007                                          struct ieee80211_conf *conf,
2008                                          struct rf_channel *rf,
2009                                          struct channel_info *info)
2010 {
2011         u8 rfcsr;
2012
2013         rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1);
2014         rt2800_rfcsr_write(rt2x00dev, 9, rf->rf3);
2015         rt2800_rfcsr_read(rt2x00dev, 11, &rfcsr);
2016         rt2x00_set_field8(&rfcsr, RFCSR11_R, rf->rf2);
2017         rt2800_rfcsr_write(rt2x00dev, 11, rfcsr);
2018
2019         rt2800_rfcsr_read(rt2x00dev, 49, &rfcsr);
2020         if (info->default_power1 > POWER_BOUND)
2021                 rt2x00_set_field8(&rfcsr, RFCSR49_TX, POWER_BOUND);
2022         else
2023                 rt2x00_set_field8(&rfcsr, RFCSR49_TX, info->default_power1);
2024         rt2800_rfcsr_write(rt2x00dev, 49, rfcsr);
2025
2026         rt2800_adjust_freq_offset(rt2x00dev);
2027
2028         if (rf->channel <= 14) {
2029                 if (rf->channel == 6)
2030                         rt2800_bbp_write(rt2x00dev, 68, 0x0c);
2031                 else
2032                         rt2800_bbp_write(rt2x00dev, 68, 0x0b);
2033
2034                 if (rf->channel >= 1 && rf->channel <= 6)
2035                         rt2800_bbp_write(rt2x00dev, 59, 0x0f);
2036                 else if (rf->channel >= 7 && rf->channel <= 11)
2037                         rt2800_bbp_write(rt2x00dev, 59, 0x0e);
2038                 else if (rf->channel >= 12 && rf->channel <= 14)
2039                         rt2800_bbp_write(rt2x00dev, 59, 0x0d);
2040         }
2041 }
2042
2043 static void rt2800_config_channel_rf3322(struct rt2x00_dev *rt2x00dev,
2044                                          struct ieee80211_conf *conf,
2045                                          struct rf_channel *rf,
2046                                          struct channel_info *info)
2047 {
2048         u8 rfcsr;
2049
2050         rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1);
2051         rt2800_rfcsr_write(rt2x00dev, 9, rf->rf3);
2052
2053         rt2800_rfcsr_write(rt2x00dev, 11, 0x42);
2054         rt2800_rfcsr_write(rt2x00dev, 12, 0x1c);
2055         rt2800_rfcsr_write(rt2x00dev, 13, 0x00);
2056
2057         if (info->default_power1 > POWER_BOUND)
2058                 rt2800_rfcsr_write(rt2x00dev, 47, POWER_BOUND);
2059         else
2060                 rt2800_rfcsr_write(rt2x00dev, 47, info->default_power1);
2061
2062         if (info->default_power2 > POWER_BOUND)
2063                 rt2800_rfcsr_write(rt2x00dev, 48, POWER_BOUND);
2064         else
2065                 rt2800_rfcsr_write(rt2x00dev, 48, info->default_power2);
2066
2067         rt2800_adjust_freq_offset(rt2x00dev);
2068
2069         rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
2070         rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 1);
2071         rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 1);
2072
2073         if ( rt2x00dev->default_ant.tx_chain_num == 2 )
2074                 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
2075         else
2076                 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 0);
2077
2078         if ( rt2x00dev->default_ant.rx_chain_num == 2 )
2079                 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
2080         else
2081                 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 0);
2082
2083         rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 0);
2084         rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 0);
2085
2086         rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
2087
2088         rt2800_rfcsr_write(rt2x00dev, 31, 80);
2089 }
2090
2091 static void rt2800_config_channel_rf53xx(struct rt2x00_dev *rt2x00dev,
2092                                          struct ieee80211_conf *conf,
2093                                          struct rf_channel *rf,
2094                                          struct channel_info *info)
2095 {
2096         u8 rfcsr;
2097
2098         rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1);
2099         rt2800_rfcsr_write(rt2x00dev, 9, rf->rf3);
2100         rt2800_rfcsr_read(rt2x00dev, 11, &rfcsr);
2101         rt2x00_set_field8(&rfcsr, RFCSR11_R, rf->rf2);
2102         rt2800_rfcsr_write(rt2x00dev, 11, rfcsr);
2103
2104         rt2800_rfcsr_read(rt2x00dev, 49, &rfcsr);
2105         if (info->default_power1 > POWER_BOUND)
2106                 rt2x00_set_field8(&rfcsr, RFCSR49_TX, POWER_BOUND);
2107         else
2108                 rt2x00_set_field8(&rfcsr, RFCSR49_TX, info->default_power1);
2109         rt2800_rfcsr_write(rt2x00dev, 49, rfcsr);
2110
2111         if (rt2x00_rt(rt2x00dev, RT5392)) {
2112                 rt2800_rfcsr_read(rt2x00dev, 50, &rfcsr);
2113                 if (info->default_power1 > POWER_BOUND)
2114                         rt2x00_set_field8(&rfcsr, RFCSR50_TX, POWER_BOUND);
2115                 else
2116                         rt2x00_set_field8(&rfcsr, RFCSR50_TX,
2117                                           info->default_power2);
2118                 rt2800_rfcsr_write(rt2x00dev, 50, rfcsr);
2119         }
2120
2121         rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
2122         if (rt2x00_rt(rt2x00dev, RT5392)) {
2123                 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
2124                 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
2125         }
2126         rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
2127         rt2x00_set_field8(&rfcsr, RFCSR1_PLL_PD, 1);
2128         rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 1);
2129         rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 1);
2130         rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
2131
2132         rt2800_adjust_freq_offset(rt2x00dev);
2133
2134         if (rf->channel <= 14) {
2135                 int idx = rf->channel-1;
2136
2137                 if (test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags)) {
2138                         if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) {
2139                                 /* r55/r59 value array of channel 1~14 */
2140                                 static const char r55_bt_rev[] = {0x83, 0x83,
2141                                         0x83, 0x73, 0x73, 0x63, 0x53, 0x53,
2142                                         0x53, 0x43, 0x43, 0x43, 0x43, 0x43};
2143                                 static const char r59_bt_rev[] = {0x0e, 0x0e,
2144                                         0x0e, 0x0e, 0x0e, 0x0b, 0x0a, 0x09,
2145                                         0x07, 0x07, 0x07, 0x07, 0x07, 0x07};
2146
2147                                 rt2800_rfcsr_write(rt2x00dev, 55,
2148                                                    r55_bt_rev[idx]);
2149                                 rt2800_rfcsr_write(rt2x00dev, 59,
2150                                                    r59_bt_rev[idx]);
2151                         } else {
2152                                 static const char r59_bt[] = {0x8b, 0x8b, 0x8b,
2153                                         0x8b, 0x8b, 0x8b, 0x8b, 0x8a, 0x89,
2154                                         0x88, 0x88, 0x86, 0x85, 0x84};
2155
2156                                 rt2800_rfcsr_write(rt2x00dev, 59, r59_bt[idx]);
2157                         }
2158                 } else {
2159                         if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) {
2160                                 static const char r55_nonbt_rev[] = {0x23, 0x23,
2161                                         0x23, 0x23, 0x13, 0x13, 0x03, 0x03,
2162                                         0x03, 0x03, 0x03, 0x03, 0x03, 0x03};
2163                                 static const char r59_nonbt_rev[] = {0x07, 0x07,
2164                                         0x07, 0x07, 0x07, 0x07, 0x07, 0x07,
2165                                         0x07, 0x07, 0x06, 0x05, 0x04, 0x04};
2166
2167                                 rt2800_rfcsr_write(rt2x00dev, 55,
2168                                                    r55_nonbt_rev[idx]);
2169                                 rt2800_rfcsr_write(rt2x00dev, 59,
2170                                                    r59_nonbt_rev[idx]);
2171                         } else if (rt2x00_rt(rt2x00dev, RT5390) ||
2172                                    rt2x00_rt(rt2x00dev, RT5392)) {
2173                                 static const char r59_non_bt[] = {0x8f, 0x8f,
2174                                         0x8f, 0x8f, 0x8f, 0x8f, 0x8f, 0x8d,
2175                                         0x8a, 0x88, 0x88, 0x87, 0x87, 0x86};
2176
2177                                 rt2800_rfcsr_write(rt2x00dev, 59,
2178                                                    r59_non_bt[idx]);
2179                         }
2180                 }
2181         }
2182 }
2183
2184 static void rt2800_config_channel_rf55xx(struct rt2x00_dev *rt2x00dev,
2185                                          struct ieee80211_conf *conf,
2186                                          struct rf_channel *rf,
2187                                          struct channel_info *info)
2188 {
2189         u8 rfcsr, ep_reg;
2190         u32 reg;
2191         int power_bound;
2192
2193         /* TODO */
2194         const bool is_11b = false;
2195         const bool is_type_ep = false;
2196
2197         rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
2198         rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL,
2199                            (rf->channel > 14 || conf_is_ht40(conf)) ? 5 : 0);
2200         rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
2201
2202         /* Order of values on rf_channel entry: N, K, mod, R */
2203         rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1 & 0xff);
2204
2205         rt2800_rfcsr_read(rt2x00dev,  9, &rfcsr);
2206         rt2x00_set_field8(&rfcsr, RFCSR9_K, rf->rf2 & 0xf);
2207         rt2x00_set_field8(&rfcsr, RFCSR9_N, (rf->rf1 & 0x100) >> 8);
2208         rt2x00_set_field8(&rfcsr, RFCSR9_MOD, ((rf->rf3 - 8) & 0x4) >> 2);
2209         rt2800_rfcsr_write(rt2x00dev, 9, rfcsr);
2210
2211         rt2800_rfcsr_read(rt2x00dev, 11, &rfcsr);
2212         rt2x00_set_field8(&rfcsr, RFCSR11_R, rf->rf4 - 1);
2213         rt2x00_set_field8(&rfcsr, RFCSR11_MOD, (rf->rf3 - 8) & 0x3);
2214         rt2800_rfcsr_write(rt2x00dev, 11, rfcsr);
2215
2216         if (rf->channel <= 14) {
2217                 rt2800_rfcsr_write(rt2x00dev, 10, 0x90);
2218                 /* FIXME: RF11 owerwrite ? */
2219                 rt2800_rfcsr_write(rt2x00dev, 11, 0x4A);
2220                 rt2800_rfcsr_write(rt2x00dev, 12, 0x52);
2221                 rt2800_rfcsr_write(rt2x00dev, 13, 0x42);
2222                 rt2800_rfcsr_write(rt2x00dev, 22, 0x40);
2223                 rt2800_rfcsr_write(rt2x00dev, 24, 0x4A);
2224                 rt2800_rfcsr_write(rt2x00dev, 25, 0x80);
2225                 rt2800_rfcsr_write(rt2x00dev, 27, 0x42);
2226                 rt2800_rfcsr_write(rt2x00dev, 36, 0x80);
2227                 rt2800_rfcsr_write(rt2x00dev, 37, 0x08);
2228                 rt2800_rfcsr_write(rt2x00dev, 38, 0x89);
2229                 rt2800_rfcsr_write(rt2x00dev, 39, 0x1B);
2230                 rt2800_rfcsr_write(rt2x00dev, 40, 0x0D);
2231                 rt2800_rfcsr_write(rt2x00dev, 41, 0x9B);
2232                 rt2800_rfcsr_write(rt2x00dev, 42, 0xD5);
2233                 rt2800_rfcsr_write(rt2x00dev, 43, 0x72);
2234                 rt2800_rfcsr_write(rt2x00dev, 44, 0x0E);
2235                 rt2800_rfcsr_write(rt2x00dev, 45, 0xA2);
2236                 rt2800_rfcsr_write(rt2x00dev, 46, 0x6B);
2237                 rt2800_rfcsr_write(rt2x00dev, 48, 0x10);
2238                 rt2800_rfcsr_write(rt2x00dev, 51, 0x3E);
2239                 rt2800_rfcsr_write(rt2x00dev, 52, 0x48);
2240                 rt2800_rfcsr_write(rt2x00dev, 54, 0x38);
2241                 rt2800_rfcsr_write(rt2x00dev, 56, 0xA1);
2242                 rt2800_rfcsr_write(rt2x00dev, 57, 0x00);
2243                 rt2800_rfcsr_write(rt2x00dev, 58, 0x39);
2244                 rt2800_rfcsr_write(rt2x00dev, 60, 0x45);
2245                 rt2800_rfcsr_write(rt2x00dev, 61, 0x91);
2246                 rt2800_rfcsr_write(rt2x00dev, 62, 0x39);
2247
2248                 /* TODO RF27 <- tssi */
2249
2250                 rfcsr = rf->channel <= 10 ? 0x07 : 0x06;
2251                 rt2800_rfcsr_write(rt2x00dev, 23, rfcsr);
2252                 rt2800_rfcsr_write(rt2x00dev, 59, rfcsr);
2253
2254                 if (is_11b) {
2255                         /* CCK */
2256                         rt2800_rfcsr_write(rt2x00dev, 31, 0xF8);
2257                         rt2800_rfcsr_write(rt2x00dev, 32, 0xC0);
2258                         if (is_type_ep)
2259                                 rt2800_rfcsr_write(rt2x00dev, 55, 0x06);
2260                         else
2261                                 rt2800_rfcsr_write(rt2x00dev, 55, 0x47);
2262                 } else {
2263                         /* OFDM */
2264                         if (is_type_ep)
2265                                 rt2800_rfcsr_write(rt2x00dev, 55, 0x03);
2266                         else
2267                                 rt2800_rfcsr_write(rt2x00dev, 55, 0x43);
2268                 }
2269
2270                 power_bound = POWER_BOUND;
2271                 ep_reg = 0x2;
2272         } else {
2273                 rt2800_rfcsr_write(rt2x00dev, 10, 0x97);
2274                 /* FIMXE: RF11 overwrite */
2275                 rt2800_rfcsr_write(rt2x00dev, 11, 0x40);
2276                 rt2800_rfcsr_write(rt2x00dev, 25, 0xBF);
2277                 rt2800_rfcsr_write(rt2x00dev, 27, 0x42);
2278                 rt2800_rfcsr_write(rt2x00dev, 36, 0x00);
2279                 rt2800_rfcsr_write(rt2x00dev, 37, 0x04);
2280                 rt2800_rfcsr_write(rt2x00dev, 38, 0x85);
2281                 rt2800_rfcsr_write(rt2x00dev, 40, 0x42);
2282                 rt2800_rfcsr_write(rt2x00dev, 41, 0xBB);
2283                 rt2800_rfcsr_write(rt2x00dev, 42, 0xD7);
2284                 rt2800_rfcsr_write(rt2x00dev, 45, 0x41);
2285                 rt2800_rfcsr_write(rt2x00dev, 48, 0x00);
2286                 rt2800_rfcsr_write(rt2x00dev, 57, 0x77);
2287                 rt2800_rfcsr_write(rt2x00dev, 60, 0x05);
2288                 rt2800_rfcsr_write(rt2x00dev, 61, 0x01);
2289
2290                 /* TODO RF27 <- tssi */
2291
2292                 if (rf->channel >= 36 && rf->channel <= 64) {
2293
2294                         rt2800_rfcsr_write(rt2x00dev, 12, 0x2E);
2295                         rt2800_rfcsr_write(rt2x00dev, 13, 0x22);
2296                         rt2800_rfcsr_write(rt2x00dev, 22, 0x60);
2297                         rt2800_rfcsr_write(rt2x00dev, 23, 0x7F);
2298                         if (rf->channel <= 50)
2299                                 rt2800_rfcsr_write(rt2x00dev, 24, 0x09);
2300                         else if (rf->channel >= 52)
2301                                 rt2800_rfcsr_write(rt2x00dev, 24, 0x07);
2302                         rt2800_rfcsr_write(rt2x00dev, 39, 0x1C);
2303                         rt2800_rfcsr_write(rt2x00dev, 43, 0x5B);
2304                         rt2800_rfcsr_write(rt2x00dev, 44, 0X40);
2305                         rt2800_rfcsr_write(rt2x00dev, 46, 0X00);
2306                         rt2800_rfcsr_write(rt2x00dev, 51, 0xFE);
2307                         rt2800_rfcsr_write(rt2x00dev, 52, 0x0C);
2308                         rt2800_rfcsr_write(rt2x00dev, 54, 0xF8);
2309                         if (rf->channel <= 50) {
2310                                 rt2800_rfcsr_write(rt2x00dev, 55, 0x06),
2311                                 rt2800_rfcsr_write(rt2x00dev, 56, 0xD3);
2312                         } else if (rf->channel >= 52) {
2313                                 rt2800_rfcsr_write(rt2x00dev, 55, 0x04);
2314                                 rt2800_rfcsr_write(rt2x00dev, 56, 0xBB);
2315                         }
2316
2317                         rt2800_rfcsr_write(rt2x00dev, 58, 0x15);
2318                         rt2800_rfcsr_write(rt2x00dev, 59, 0x7F);
2319                         rt2800_rfcsr_write(rt2x00dev, 62, 0x15);
2320
2321                 } else if (rf->channel >= 100 && rf->channel <= 165) {
2322
2323                         rt2800_rfcsr_write(rt2x00dev, 12, 0x0E);
2324                         rt2800_rfcsr_write(rt2x00dev, 13, 0x42);
2325                         rt2800_rfcsr_write(rt2x00dev, 22, 0x40);
2326                         if (rf->channel <= 153) {
2327                                 rt2800_rfcsr_write(rt2x00dev, 23, 0x3C);
2328                                 rt2800_rfcsr_write(rt2x00dev, 24, 0x06);
2329                         } else if (rf->channel >= 155) {
2330                                 rt2800_rfcsr_write(rt2x00dev, 23, 0x38);
2331                                 rt2800_rfcsr_write(rt2x00dev, 24, 0x05);
2332                         }
2333                         if (rf->channel <= 138) {
2334                                 rt2800_rfcsr_write(rt2x00dev, 39, 0x1A);
2335                                 rt2800_rfcsr_write(rt2x00dev, 43, 0x3B);
2336                                 rt2800_rfcsr_write(rt2x00dev, 44, 0x20);
2337                                 rt2800_rfcsr_write(rt2x00dev, 46, 0x18);
2338                         } else if (rf->channel >= 140) {
2339                                 rt2800_rfcsr_write(rt2x00dev, 39, 0x18);
2340                                 rt2800_rfcsr_write(rt2x00dev, 43, 0x1B);
2341                                 rt2800_rfcsr_write(rt2x00dev, 44, 0x10);
2342                                 rt2800_rfcsr_write(rt2x00dev, 46, 0X08);
2343                         }
2344                         if (rf->channel <= 124)
2345                                 rt2800_rfcsr_write(rt2x00dev, 51, 0xFC);
2346                         else if (rf->channel >= 126)
2347                                 rt2800_rfcsr_write(rt2x00dev, 51, 0xEC);
2348                         if (rf->channel <= 138)
2349                                 rt2800_rfcsr_write(rt2x00dev, 52, 0x06);
2350                         else if (rf->channel >= 140)
2351                                 rt2800_rfcsr_write(rt2x00dev, 52, 0x06);
2352                         rt2800_rfcsr_write(rt2x00dev, 54, 0xEB);
2353                         if (rf->channel <= 138)
2354                                 rt2800_rfcsr_write(rt2x00dev, 55, 0x01);
2355                         else if (rf->channel >= 140)
2356                                 rt2800_rfcsr_write(rt2x00dev, 55, 0x00);
2357                         if (rf->channel <= 128)
2358                                 rt2800_rfcsr_write(rt2x00dev, 56, 0xBB);
2359                         else if (rf->channel >= 130)
2360                                 rt2800_rfcsr_write(rt2x00dev, 56, 0xAB);
2361                         if (rf->channel <= 116)
2362                                 rt2800_rfcsr_write(rt2x00dev, 58, 0x1D);
2363                         else if (rf->channel >= 118)
2364                                 rt2800_rfcsr_write(rt2x00dev, 58, 0x15);
2365                         if (rf->channel <= 138)
2366                                 rt2800_rfcsr_write(rt2x00dev, 59, 0x3F);
2367                         else if (rf->channel >= 140)
2368                                 rt2800_rfcsr_write(rt2x00dev, 59, 0x7C);
2369                         if (rf->channel <= 116)
2370                                 rt2800_rfcsr_write(rt2x00dev, 62, 0x1D);
2371                         else if (rf->channel >= 118)
2372                                 rt2800_rfcsr_write(rt2x00dev, 62, 0x15);
2373                 }
2374
2375                 power_bound = POWER_BOUND_5G;
2376                 ep_reg = 0x3;
2377         }
2378
2379         rt2800_rfcsr_read(rt2x00dev, 49, &rfcsr);
2380         if (info->default_power1 > power_bound)
2381                 rt2x00_set_field8(&rfcsr, RFCSR49_TX, power_bound);
2382         else
2383                 rt2x00_set_field8(&rfcsr, RFCSR49_TX, info->default_power1);
2384         if (is_type_ep)
2385                 rt2x00_set_field8(&rfcsr, RFCSR49_EP, ep_reg);
2386         rt2800_rfcsr_write(rt2x00dev, 49, rfcsr);
2387
2388         rt2800_rfcsr_read(rt2x00dev, 50, &rfcsr);
2389         if (info->default_power1 > power_bound)
2390                 rt2x00_set_field8(&rfcsr, RFCSR50_TX, power_bound);
2391         else
2392                 rt2x00_set_field8(&rfcsr, RFCSR50_TX, info->default_power2);
2393         if (is_type_ep)
2394                 rt2x00_set_field8(&rfcsr, RFCSR50_EP, ep_reg);
2395         rt2800_rfcsr_write(rt2x00dev, 50, rfcsr);
2396
2397         rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
2398         rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
2399         rt2x00_set_field8(&rfcsr, RFCSR1_PLL_PD, 1);
2400
2401         rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD,
2402                           rt2x00dev->default_ant.tx_chain_num >= 1);
2403         rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD,
2404                           rt2x00dev->default_ant.tx_chain_num == 2);
2405         rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 0);
2406
2407         rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD,
2408                           rt2x00dev->default_ant.rx_chain_num >= 1);
2409         rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD,
2410                           rt2x00dev->default_ant.rx_chain_num == 2);
2411         rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 0);
2412
2413         rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
2414         rt2800_rfcsr_write(rt2x00dev, 6, 0xe4);
2415
2416         if (conf_is_ht40(conf))
2417                 rt2800_rfcsr_write(rt2x00dev, 30, 0x16);
2418         else
2419                 rt2800_rfcsr_write(rt2x00dev, 30, 0x10);
2420
2421         if (!is_11b) {
2422                 rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
2423                 rt2800_rfcsr_write(rt2x00dev, 32, 0x80);
2424         }
2425
2426         /* TODO proper frequency adjustment */
2427         rt2800_adjust_freq_offset(rt2x00dev);
2428
2429         /* TODO merge with others */
2430         rt2800_rfcsr_read(rt2x00dev, 3, &rfcsr);
2431         rt2x00_set_field8(&rfcsr, RFCSR3_VCOCAL_EN, 1);
2432         rt2800_rfcsr_write(rt2x00dev, 3, rfcsr);
2433
2434         /* BBP settings */
2435         rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain);
2436         rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain);
2437         rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain);
2438
2439         rt2800_bbp_write(rt2x00dev, 79, (rf->channel <= 14) ? 0x1C : 0x18);
2440         rt2800_bbp_write(rt2x00dev, 80, (rf->channel <= 14) ? 0x0E : 0x08);
2441         rt2800_bbp_write(rt2x00dev, 81, (rf->channel <= 14) ? 0x3A : 0x38);
2442         rt2800_bbp_write(rt2x00dev, 82, (rf->channel <= 14) ? 0x62 : 0x92);
2443
2444         /* GLRT band configuration */
2445         rt2800_bbp_write(rt2x00dev, 195, 128);
2446         rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0xE0 : 0xF0);
2447         rt2800_bbp_write(rt2x00dev, 195, 129);
2448         rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0x1F : 0x1E);
2449         rt2800_bbp_write(rt2x00dev, 195, 130);
2450         rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0x38 : 0x28);
2451         rt2800_bbp_write(rt2x00dev, 195, 131);
2452         rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0x32 : 0x20);
2453         rt2800_bbp_write(rt2x00dev, 195, 133);
2454         rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0x28 : 0x7F);
2455         rt2800_bbp_write(rt2x00dev, 195, 124);
2456         rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0x19 : 0x7F);
2457 }
2458
2459 static void rt2800_config_channel(struct rt2x00_dev *rt2x00dev,
2460                                   struct ieee80211_conf *conf,
2461                                   struct rf_channel *rf,
2462                                   struct channel_info *info)
2463 {
2464         u32 reg;
2465         unsigned int tx_pin;
2466         u8 bbp, rfcsr;
2467
2468         if (rf->channel <= 14) {
2469                 info->default_power1 = TXPOWER_G_TO_DEV(info->default_power1);
2470                 info->default_power2 = TXPOWER_G_TO_DEV(info->default_power2);
2471         } else {
2472                 info->default_power1 = TXPOWER_A_TO_DEV(info->default_power1);
2473                 info->default_power2 = TXPOWER_A_TO_DEV(info->default_power2);
2474         }
2475
2476         switch (rt2x00dev->chip.rf) {
2477         case RF2020:
2478         case RF3020:
2479         case RF3021:
2480         case RF3022:
2481         case RF3320:
2482                 rt2800_config_channel_rf3xxx(rt2x00dev, conf, rf, info);
2483                 break;
2484         case RF3052:
2485                 rt2800_config_channel_rf3052(rt2x00dev, conf, rf, info);
2486                 break;
2487         case RF3290:
2488                 rt2800_config_channel_rf3290(rt2x00dev, conf, rf, info);
2489                 break;
2490         case RF3322:
2491                 rt2800_config_channel_rf3322(rt2x00dev, conf, rf, info);
2492                 break;
2493         case RF5360:
2494         case RF5370:
2495         case RF5372:
2496         case RF5390:
2497         case RF5392:
2498                 rt2800_config_channel_rf53xx(rt2x00dev, conf, rf, info);
2499                 break;
2500         case RF5592:
2501                 rt2800_config_channel_rf55xx(rt2x00dev, conf, rf, info);
2502                 break;
2503         default:
2504                 rt2800_config_channel_rf2xxx(rt2x00dev, conf, rf, info);
2505         }
2506
2507         if (rt2x00_rf(rt2x00dev, RF3290) ||
2508             rt2x00_rf(rt2x00dev, RF3322) ||
2509             rt2x00_rf(rt2x00dev, RF5360) ||
2510             rt2x00_rf(rt2x00dev, RF5370) ||
2511             rt2x00_rf(rt2x00dev, RF5372) ||
2512             rt2x00_rf(rt2x00dev, RF5390) ||
2513             rt2x00_rf(rt2x00dev, RF5392)) {
2514                 rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
2515                 rt2x00_set_field8(&rfcsr, RFCSR30_TX_H20M, 0);
2516                 rt2x00_set_field8(&rfcsr, RFCSR30_RX_H20M, 0);
2517                 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
2518
2519                 rt2800_rfcsr_read(rt2x00dev, 3, &rfcsr);
2520                 rt2x00_set_field8(&rfcsr, RFCSR3_VCOCAL_EN, 1);
2521                 rt2800_rfcsr_write(rt2x00dev, 3, rfcsr);
2522         }
2523
2524         /*
2525          * Change BBP settings
2526          */
2527         if (rt2x00_rt(rt2x00dev, RT3352)) {
2528                 rt2800_bbp_write(rt2x00dev, 27, 0x0);
2529                 rt2800_bbp_write(rt2x00dev, 66, 0x26 + rt2x00dev->lna_gain);
2530                 rt2800_bbp_write(rt2x00dev, 27, 0x20);
2531                 rt2800_bbp_write(rt2x00dev, 66, 0x26 + rt2x00dev->lna_gain);
2532         } else {
2533                 rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain);
2534                 rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain);
2535                 rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain);
2536                 rt2800_bbp_write(rt2x00dev, 86, 0);
2537         }
2538
2539         if (rf->channel <= 14) {
2540                 if (!rt2x00_rt(rt2x00dev, RT5390) &&
2541                     !rt2x00_rt(rt2x00dev, RT5392)) {
2542                         if (test_bit(CAPABILITY_EXTERNAL_LNA_BG,
2543                                      &rt2x00dev->cap_flags)) {
2544                                 rt2800_bbp_write(rt2x00dev, 82, 0x62);
2545                                 rt2800_bbp_write(rt2x00dev, 75, 0x46);
2546                         } else {
2547                                 rt2800_bbp_write(rt2x00dev, 82, 0x84);
2548                                 rt2800_bbp_write(rt2x00dev, 75, 0x50);
2549                         }
2550                 }
2551         } else {
2552                 if (rt2x00_rt(rt2x00dev, RT3572))
2553                         rt2800_bbp_write(rt2x00dev, 82, 0x94);
2554                 else
2555                         rt2800_bbp_write(rt2x00dev, 82, 0xf2);
2556
2557                 if (test_bit(CAPABILITY_EXTERNAL_LNA_A, &rt2x00dev->cap_flags))
2558                         rt2800_bbp_write(rt2x00dev, 75, 0x46);
2559                 else
2560                         rt2800_bbp_write(rt2x00dev, 75, 0x50);
2561         }
2562
2563         rt2800_register_read(rt2x00dev, TX_BAND_CFG, &reg);
2564         rt2x00_set_field32(&reg, TX_BAND_CFG_HT40_MINUS, conf_is_ht40_minus(conf));
2565         rt2x00_set_field32(&reg, TX_BAND_CFG_A, rf->channel > 14);
2566         rt2x00_set_field32(&reg, TX_BAND_CFG_BG, rf->channel <= 14);
2567         rt2800_register_write(rt2x00dev, TX_BAND_CFG, reg);
2568
2569         if (rt2x00_rt(rt2x00dev, RT3572))
2570                 rt2800_rfcsr_write(rt2x00dev, 8, 0);
2571
2572         tx_pin = 0;
2573
2574         /* Turn on unused PA or LNA when not using 1T or 1R */
2575         if (rt2x00dev->default_ant.tx_chain_num == 2) {
2576                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A1_EN,
2577                                    rf->channel > 14);
2578                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G1_EN,
2579                                    rf->channel <= 14);
2580         }
2581
2582         /* Turn on unused PA or LNA when not using 1T or 1R */
2583         if (rt2x00dev->default_ant.rx_chain_num == 2) {
2584                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A1_EN, 1);
2585                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G1_EN, 1);
2586         }
2587
2588         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A0_EN, 1);
2589         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G0_EN, 1);
2590         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_RFTR_EN, 1);
2591         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_TRSW_EN, 1);
2592         if (test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags))
2593                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN, 1);
2594         else
2595                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN,
2596                                    rf->channel <= 14);
2597         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A0_EN, rf->channel > 14);
2598
2599         rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin);
2600
2601         if (rt2x00_rt(rt2x00dev, RT3572))
2602                 rt2800_rfcsr_write(rt2x00dev, 8, 0x80);
2603
2604         if (rt2x00_rt(rt2x00dev, RT5592)) {
2605                 rt2800_bbp_write(rt2x00dev, 195, 141);
2606                 rt2800_bbp_write(rt2x00dev, 196, conf_is_ht40(conf) ? 0x10 : 0x1a);
2607
2608                 /* TODO AGC adjust */
2609                 /* TODO IQ calibration */
2610         }
2611
2612         rt2800_bbp_read(rt2x00dev, 4, &bbp);
2613         rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * conf_is_ht40(conf));
2614         rt2800_bbp_write(rt2x00dev, 4, bbp);
2615
2616         rt2800_bbp_read(rt2x00dev, 3, &bbp);
2617         rt2x00_set_field8(&bbp, BBP3_HT40_MINUS, conf_is_ht40_minus(conf));
2618         rt2800_bbp_write(rt2x00dev, 3, bbp);
2619
2620         if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C)) {
2621                 if (conf_is_ht40(conf)) {
2622                         rt2800_bbp_write(rt2x00dev, 69, 0x1a);
2623                         rt2800_bbp_write(rt2x00dev, 70, 0x0a);
2624                         rt2800_bbp_write(rt2x00dev, 73, 0x16);
2625                 } else {
2626                         rt2800_bbp_write(rt2x00dev, 69, 0x16);
2627                         rt2800_bbp_write(rt2x00dev, 70, 0x08);
2628                         rt2800_bbp_write(rt2x00dev, 73, 0x11);
2629                 }
2630         }
2631
2632         msleep(1);
2633
2634         /*
2635          * Clear channel statistic counters
2636          */
2637         rt2800_register_read(rt2x00dev, CH_IDLE_STA, &reg);
2638         rt2800_register_read(rt2x00dev, CH_BUSY_STA, &reg);
2639         rt2800_register_read(rt2x00dev, CH_BUSY_STA_SEC, &reg);
2640
2641         /*
2642          * Clear update flag
2643          */
2644         if (rt2x00_rt(rt2x00dev, RT3352)) {
2645                 rt2800_bbp_read(rt2x00dev, 49, &bbp);
2646                 rt2x00_set_field8(&bbp, BBP49_UPDATE_FLAG, 0);
2647                 rt2800_bbp_write(rt2x00dev, 49, bbp);
2648         }
2649 }
2650
2651 static int rt2800_get_gain_calibration_delta(struct rt2x00_dev *rt2x00dev)
2652 {
2653         u8 tssi_bounds[9];
2654         u8 current_tssi;
2655         u16 eeprom;
2656         u8 step;
2657         int i;
2658
2659         /*
2660          * Read TSSI boundaries for temperature compensation from
2661          * the EEPROM.
2662          *
2663          * Array idx               0    1    2    3    4    5    6    7    8
2664          * Matching Delta value   -4   -3   -2   -1    0   +1   +2   +3   +4
2665          * Example TSSI bounds  0xF0 0xD0 0xB5 0xA0 0x88 0x45 0x25 0x15 0x00
2666          */
2667         if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ) {
2668                 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG1, &eeprom);
2669                 tssi_bounds[0] = rt2x00_get_field16(eeprom,
2670                                         EEPROM_TSSI_BOUND_BG1_MINUS4);
2671                 tssi_bounds[1] = rt2x00_get_field16(eeprom,
2672                                         EEPROM_TSSI_BOUND_BG1_MINUS3);
2673
2674                 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG2, &eeprom);
2675                 tssi_bounds[2] = rt2x00_get_field16(eeprom,
2676                                         EEPROM_TSSI_BOUND_BG2_MINUS2);
2677                 tssi_bounds[3] = rt2x00_get_field16(eeprom,
2678                                         EEPROM_TSSI_BOUND_BG2_MINUS1);
2679
2680                 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG3, &eeprom);
2681                 tssi_bounds[4] = rt2x00_get_field16(eeprom,
2682                                         EEPROM_TSSI_BOUND_BG3_REF);
2683                 tssi_bounds[5] = rt2x00_get_field16(eeprom,
2684                                         EEPROM_TSSI_BOUND_BG3_PLUS1);
2685
2686                 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG4, &eeprom);
2687                 tssi_bounds[6] = rt2x00_get_field16(eeprom,
2688                                         EEPROM_TSSI_BOUND_BG4_PLUS2);
2689                 tssi_bounds[7] = rt2x00_get_field16(eeprom,
2690                                         EEPROM_TSSI_BOUND_BG4_PLUS3);
2691
2692                 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG5, &eeprom);
2693                 tssi_bounds[8] = rt2x00_get_field16(eeprom,
2694                                         EEPROM_TSSI_BOUND_BG5_PLUS4);
2695
2696                 step = rt2x00_get_field16(eeprom,
2697                                           EEPROM_TSSI_BOUND_BG5_AGC_STEP);
2698         } else {
2699                 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A1, &eeprom);
2700                 tssi_bounds[0] = rt2x00_get_field16(eeprom,
2701                                         EEPROM_TSSI_BOUND_A1_MINUS4);
2702                 tssi_bounds[1] = rt2x00_get_field16(eeprom,
2703                                         EEPROM_TSSI_BOUND_A1_MINUS3);
2704
2705                 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A2, &eeprom);
2706                 tssi_bounds[2] = rt2x00_get_field16(eeprom,
2707                                         EEPROM_TSSI_BOUND_A2_MINUS2);
2708                 tssi_bounds[3] = rt2x00_get_field16(eeprom,
2709                                         EEPROM_TSSI_BOUND_A2_MINUS1);
2710
2711                 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A3, &eeprom);
2712                 tssi_bounds[4] = rt2x00_get_field16(eeprom,
2713                                         EEPROM_TSSI_BOUND_A3_REF);
2714                 tssi_bounds[5] = rt2x00_get_field16(eeprom,
2715                                         EEPROM_TSSI_BOUND_A3_PLUS1);
2716
2717                 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A4, &eeprom);
2718                 tssi_bounds[6] = rt2x00_get_field16(eeprom,
2719                                         EEPROM_TSSI_BOUND_A4_PLUS2);
2720                 tssi_bounds[7] = rt2x00_get_field16(eeprom,
2721                                         EEPROM_TSSI_BOUND_A4_PLUS3);
2722
2723                 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A5, &eeprom);
2724                 tssi_bounds[8] = rt2x00_get_field16(eeprom,
2725                                         EEPROM_TSSI_BOUND_A5_PLUS4);
2726
2727                 step = rt2x00_get_field16(eeprom,
2728                                           EEPROM_TSSI_BOUND_A5_AGC_STEP);
2729         }
2730
2731         /*
2732          * Check if temperature compensation is supported.
2733          */
2734         if (tssi_bounds[4] == 0xff || step == 0xff)
2735                 return 0;
2736
2737         /*
2738          * Read current TSSI (BBP 49).
2739          */
2740         rt2800_bbp_read(rt2x00dev, 49, &current_tssi);
2741
2742         /*
2743          * Compare TSSI value (BBP49) with the compensation boundaries
2744          * from the EEPROM and increase or decrease tx power.
2745          */
2746         for (i = 0; i <= 3; i++) {
2747                 if (current_tssi > tssi_bounds[i])
2748                         break;
2749         }
2750
2751         if (i == 4) {
2752                 for (i = 8; i >= 5; i--) {
2753                         if (current_tssi < tssi_bounds[i])
2754                                 break;
2755                 }
2756         }
2757
2758         return (i - 4) * step;
2759 }
2760
2761 static int rt2800_get_txpower_bw_comp(struct rt2x00_dev *rt2x00dev,
2762                                       enum ieee80211_band band)
2763 {
2764         u16 eeprom;
2765         u8 comp_en;
2766         u8 comp_type;
2767         int comp_value = 0;
2768
2769         rt2x00_eeprom_read(rt2x00dev, EEPROM_TXPOWER_DELTA, &eeprom);
2770
2771         /*
2772          * HT40 compensation not required.
2773          */
2774         if (eeprom == 0xffff ||
2775             !test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags))
2776                 return 0;
2777
2778         if (band == IEEE80211_BAND_2GHZ) {
2779                 comp_en = rt2x00_get_field16(eeprom,
2780                                  EEPROM_TXPOWER_DELTA_ENABLE_2G);
2781                 if (comp_en) {
2782                         comp_type = rt2x00_get_field16(eeprom,
2783                                            EEPROM_TXPOWER_DELTA_TYPE_2G);
2784                         comp_value = rt2x00_get_field16(eeprom,
2785                                             EEPROM_TXPOWER_DELTA_VALUE_2G);
2786                         if (!comp_type)
2787                                 comp_value = -comp_value;
2788                 }
2789         } else {
2790                 comp_en = rt2x00_get_field16(eeprom,
2791                                  EEPROM_TXPOWER_DELTA_ENABLE_5G);
2792                 if (comp_en) {
2793                         comp_type = rt2x00_get_field16(eeprom,
2794                                            EEPROM_TXPOWER_DELTA_TYPE_5G);
2795                         comp_value = rt2x00_get_field16(eeprom,
2796                                             EEPROM_TXPOWER_DELTA_VALUE_5G);
2797                         if (!comp_type)
2798                                 comp_value = -comp_value;
2799                 }
2800         }
2801
2802         return comp_value;
2803 }
2804
2805 static int rt2800_get_txpower_reg_delta(struct rt2x00_dev *rt2x00dev,
2806                                         int power_level, int max_power)
2807 {
2808         int delta;
2809
2810         if (test_bit(CAPABILITY_POWER_LIMIT, &rt2x00dev->cap_flags))
2811                 return 0;
2812
2813         /*
2814          * XXX: We don't know the maximum transmit power of our hardware since
2815          * the EEPROM doesn't expose it. We only know that we are calibrated
2816          * to 100% tx power.
2817          *
2818          * Hence, we assume the regulatory limit that cfg80211 calulated for
2819          * the current channel is our maximum and if we are requested to lower
2820          * the value we just reduce our tx power accordingly.
2821          */
2822         delta = power_level - max_power;
2823         return min(delta, 0);
2824 }
2825
2826 static u8 rt2800_compensate_txpower(struct rt2x00_dev *rt2x00dev, int is_rate_b,
2827                                    enum ieee80211_band band, int power_level,
2828                                    u8 txpower, int delta)
2829 {
2830         u16 eeprom;
2831         u8 criterion;
2832         u8 eirp_txpower;
2833         u8 eirp_txpower_criterion;
2834         u8 reg_limit;
2835
2836         if (test_bit(CAPABILITY_POWER_LIMIT, &rt2x00dev->cap_flags)) {
2837                 /*
2838                  * Check if eirp txpower exceed txpower_limit.
2839                  * We use OFDM 6M as criterion and its eirp txpower
2840                  * is stored at EEPROM_EIRP_MAX_TX_POWER.
2841                  * .11b data rate need add additional 4dbm
2842                  * when calculating eirp txpower.
2843                  */
2844                 rt2x00_eeprom_read(rt2x00dev, EEPROM_TXPOWER_BYRATE + 1,
2845                                    &eeprom);
2846                 criterion = rt2x00_get_field16(eeprom,
2847                                                EEPROM_TXPOWER_BYRATE_RATE0);
2848
2849                 rt2x00_eeprom_read(rt2x00dev, EEPROM_EIRP_MAX_TX_POWER,
2850                                    &eeprom);
2851
2852                 if (band == IEEE80211_BAND_2GHZ)
2853                         eirp_txpower_criterion = rt2x00_get_field16(eeprom,
2854                                                  EEPROM_EIRP_MAX_TX_POWER_2GHZ);
2855                 else
2856                         eirp_txpower_criterion = rt2x00_get_field16(eeprom,
2857                                                  EEPROM_EIRP_MAX_TX_POWER_5GHZ);
2858
2859                 eirp_txpower = eirp_txpower_criterion + (txpower - criterion) +
2860                                (is_rate_b ? 4 : 0) + delta;
2861
2862                 reg_limit = (eirp_txpower > power_level) ?
2863                                         (eirp_txpower - power_level) : 0;
2864         } else
2865                 reg_limit = 0;
2866
2867         txpower = max(0, txpower + delta - reg_limit);
2868         return min_t(u8, txpower, 0xc);
2869 }
2870
2871 /*
2872  * We configure transmit power using MAC TX_PWR_CFG_{0,...,N} registers and
2873  * BBP R1 register. TX_PWR_CFG_X allow to configure per rate TX power values,
2874  * 4 bits for each rate (tune from 0 to 15 dBm). BBP_R1 controls transmit power
2875  * for all rates, but allow to set only 4 discrete values: -12, -6, 0 and 6 dBm.
2876  * Reference per rate transmit power values are located in the EEPROM at
2877  * EEPROM_TXPOWER_BYRATE offset. We adjust them and BBP R1 settings according to
2878  * current conditions (i.e. band, bandwidth, temperature, user settings).
2879  */
2880 static void rt2800_config_txpower(struct rt2x00_dev *rt2x00dev,
2881                                   struct ieee80211_channel *chan,
2882                                   int power_level)
2883 {
2884         u8 txpower, r1;
2885         u16 eeprom;
2886         u32 reg, offset;
2887         int i, is_rate_b, delta, power_ctrl;
2888         enum ieee80211_band band = chan->band;
2889
2890         /*
2891          * Calculate HT40 compensation. For 40MHz we need to add or subtract
2892          * value read from EEPROM (different for 2GHz and for 5GHz).
2893          */
2894         delta = rt2800_get_txpower_bw_comp(rt2x00dev, band);
2895
2896         /*
2897          * Calculate temperature compensation. Depends on measurement of current
2898          * TSSI (Transmitter Signal Strength Indication) we know TX power (due
2899          * to temperature or maybe other factors) is smaller or bigger than
2900          * expected. We adjust it, based on TSSI reference and boundaries values
2901          * provided in EEPROM.
2902          */
2903         delta += rt2800_get_gain_calibration_delta(rt2x00dev);
2904
2905         /*
2906          * Decrease power according to user settings, on devices with unknown
2907          * maximum tx power. For other devices we take user power_level into
2908          * consideration on rt2800_compensate_txpower().
2909          */
2910         delta += rt2800_get_txpower_reg_delta(rt2x00dev, power_level,
2911                                               chan->max_power);
2912
2913         /*
2914          * BBP_R1 controls TX power for all rates, it allow to set the following
2915          * gains -12, -6, 0, +6 dBm by setting values 2, 1, 0, 3 respectively.
2916          *
2917          * TODO: we do not use +6 dBm option to do not increase power beyond
2918          * regulatory limit, however this could be utilized for devices with
2919          * CAPABILITY_POWER_LIMIT.
2920          */
2921         rt2800_bbp_read(rt2x00dev, 1, &r1);
2922         if (delta <= -12) {
2923                 power_ctrl = 2;
2924                 delta += 12;
2925         } else if (delta <= -6) {
2926                 power_ctrl = 1;
2927                 delta += 6;
2928         } else {
2929                 power_ctrl = 0;
2930         }
2931         rt2x00_set_field8(&r1, BBP1_TX_POWER_CTRL, power_ctrl);
2932         rt2800_bbp_write(rt2x00dev, 1, r1);
2933         offset = TX_PWR_CFG_0;
2934
2935         for (i = 0; i < EEPROM_TXPOWER_BYRATE_SIZE; i += 2) {
2936                 /* just to be safe */
2937                 if (offset > TX_PWR_CFG_4)
2938                         break;
2939
2940                 rt2800_register_read(rt2x00dev, offset, &reg);
2941
2942                 /* read the next four txpower values */
2943                 rt2x00_eeprom_read(rt2x00dev, EEPROM_TXPOWER_BYRATE + i,
2944                                    &eeprom);
2945
2946                 is_rate_b = i ? 0 : 1;
2947                 /*
2948                  * TX_PWR_CFG_0: 1MBS, TX_PWR_CFG_1: 24MBS,
2949                  * TX_PWR_CFG_2: MCS4, TX_PWR_CFG_3: MCS12,
2950                  * TX_PWR_CFG_4: unknown
2951                  */
2952                 txpower = rt2x00_get_field16(eeprom,
2953                                              EEPROM_TXPOWER_BYRATE_RATE0);
2954                 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
2955                                              power_level, txpower, delta);
2956                 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE0, txpower);
2957
2958                 /*
2959                  * TX_PWR_CFG_0: 2MBS, TX_PWR_CFG_1: 36MBS,
2960                  * TX_PWR_CFG_2: MCS5, TX_PWR_CFG_3: MCS13,
2961                  * TX_PWR_CFG_4: unknown
2962                  */
2963                 txpower = rt2x00_get_field16(eeprom,
2964                                              EEPROM_TXPOWER_BYRATE_RATE1);
2965                 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
2966                                              power_level, txpower, delta);
2967                 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE1, txpower);
2968
2969                 /*
2970                  * TX_PWR_CFG_0: 5.5MBS, TX_PWR_CFG_1: 48MBS,
2971                  * TX_PWR_CFG_2: MCS6,  TX_PWR_CFG_3: MCS14,
2972                  * TX_PWR_CFG_4: unknown
2973                  */
2974                 txpower = rt2x00_get_field16(eeprom,
2975                                              EEPROM_TXPOWER_BYRATE_RATE2);
2976                 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
2977                                              power_level, txpower, delta);
2978                 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE2, txpower);
2979
2980                 /*
2981                  * TX_PWR_CFG_0: 11MBS, TX_PWR_CFG_1: 54MBS,
2982                  * TX_PWR_CFG_2: MCS7,  TX_PWR_CFG_3: MCS15,
2983                  * TX_PWR_CFG_4: unknown
2984                  */
2985                 txpower = rt2x00_get_field16(eeprom,
2986                                              EEPROM_TXPOWER_BYRATE_RATE3);
2987                 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
2988                                              power_level, txpower, delta);
2989                 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE3, txpower);
2990
2991                 /* read the next four txpower values */
2992                 rt2x00_eeprom_read(rt2x00dev, EEPROM_TXPOWER_BYRATE + i + 1,
2993                                    &eeprom);
2994
2995                 is_rate_b = 0;
2996                 /*
2997                  * TX_PWR_CFG_0: 6MBS, TX_PWR_CFG_1: MCS0,
2998                  * TX_PWR_CFG_2: MCS8, TX_PWR_CFG_3: unknown,
2999                  * TX_PWR_CFG_4: unknown
3000                  */
3001                 txpower = rt2x00_get_field16(eeprom,
3002                                              EEPROM_TXPOWER_BYRATE_RATE0);
3003                 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
3004                                              power_level, txpower, delta);
3005                 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE4, txpower);
3006
3007                 /*
3008                  * TX_PWR_CFG_0: 9MBS, TX_PWR_CFG_1: MCS1,
3009                  * TX_PWR_CFG_2: MCS9, TX_PWR_CFG_3: unknown,
3010                  * TX_PWR_CFG_4: unknown
3011                  */
3012                 txpower = rt2x00_get_field16(eeprom,
3013                                              EEPROM_TXPOWER_BYRATE_RATE1);
3014                 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
3015                                              power_level, txpower, delta);
3016                 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE5, txpower);
3017
3018                 /*
3019                  * TX_PWR_CFG_0: 12MBS, TX_PWR_CFG_1: MCS2,
3020                  * TX_PWR_CFG_2: MCS10, TX_PWR_CFG_3: unknown,
3021                  * TX_PWR_CFG_4: unknown
3022                  */
3023                 txpower = rt2x00_get_field16(eeprom,
3024                                              EEPROM_TXPOWER_BYRATE_RATE2);
3025                 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
3026                                              power_level, txpower, delta);
3027                 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE6, txpower);
3028
3029                 /*
3030                  * TX_PWR_CFG_0: 18MBS, TX_PWR_CFG_1: MCS3,
3031                  * TX_PWR_CFG_2: MCS11, TX_PWR_CFG_3: unknown,
3032                  * TX_PWR_CFG_4: unknown
3033                  */
3034                 txpower = rt2x00_get_field16(eeprom,
3035                                              EEPROM_TXPOWER_BYRATE_RATE3);
3036                 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
3037                                              power_level, txpower, delta);
3038                 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE7, txpower);
3039
3040                 rt2800_register_write(rt2x00dev, offset, reg);
3041
3042                 /* next TX_PWR_CFG register */
3043                 offset += 4;
3044         }
3045 }
3046
3047 void rt2800_gain_calibration(struct rt2x00_dev *rt2x00dev)
3048 {
3049         rt2800_config_txpower(rt2x00dev, rt2x00dev->hw->conf.channel,
3050                               rt2x00dev->tx_power);
3051 }
3052 EXPORT_SYMBOL_GPL(rt2800_gain_calibration);
3053
3054 void rt2800_vco_calibration(struct rt2x00_dev *rt2x00dev)
3055 {
3056         u32     tx_pin;
3057         u8      rfcsr;
3058
3059         /*
3060          * A voltage-controlled oscillator(VCO) is an electronic oscillator
3061          * designed to be controlled in oscillation frequency by a voltage
3062          * input. Maybe the temperature will affect the frequency of
3063          * oscillation to be shifted. The VCO calibration will be called
3064          * periodically to adjust the frequency to be precision.
3065         */
3066
3067         rt2800_register_read(rt2x00dev, TX_PIN_CFG, &tx_pin);
3068         tx_pin &= TX_PIN_CFG_PA_PE_DISABLE;
3069         rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin);
3070
3071         switch (rt2x00dev->chip.rf) {
3072         case RF2020:
3073         case RF3020:
3074         case RF3021:
3075         case RF3022:
3076         case RF3320:
3077         case RF3052:
3078                 rt2800_rfcsr_read(rt2x00dev, 7, &rfcsr);
3079                 rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1);
3080                 rt2800_rfcsr_write(rt2x00dev, 7, rfcsr);
3081                 break;
3082         case RF3290:
3083         case RF5360:
3084         case RF5370:
3085         case RF5372:
3086         case RF5390:
3087         case RF5392:
3088                 rt2800_rfcsr_read(rt2x00dev, 3, &rfcsr);
3089                 rt2x00_set_field8(&rfcsr, RFCSR3_VCOCAL_EN, 1);
3090                 rt2800_rfcsr_write(rt2x00dev, 3, rfcsr);
3091                 break;
3092         default:
3093                 return;
3094         }
3095
3096         mdelay(1);
3097
3098         rt2800_register_read(rt2x00dev, TX_PIN_CFG, &tx_pin);
3099         if (rt2x00dev->rf_channel <= 14) {
3100                 switch (rt2x00dev->default_ant.tx_chain_num) {
3101                 case 3:
3102                         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G2_EN, 1);
3103                         /* fall through */
3104                 case 2:
3105                         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G1_EN, 1);
3106                         /* fall through */
3107                 case 1:
3108                 default:
3109                         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN, 1);
3110                         break;
3111                 }
3112         } else {
3113                 switch (rt2x00dev->default_ant.tx_chain_num) {
3114                 case 3:
3115                         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A2_EN, 1);
3116                         /* fall through */
3117                 case 2:
3118                         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A1_EN, 1);
3119                         /* fall through */
3120                 case 1:
3121                 default:
3122                         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A0_EN, 1);
3123                         break;
3124                 }
3125         }
3126         rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin);
3127
3128 }
3129 EXPORT_SYMBOL_GPL(rt2800_vco_calibration);
3130
3131 static void rt2800_config_retry_limit(struct rt2x00_dev *rt2x00dev,
3132                                       struct rt2x00lib_conf *libconf)
3133 {
3134         u32 reg;
3135
3136         rt2800_register_read(rt2x00dev, TX_RTY_CFG, &reg);
3137         rt2x00_set_field32(&reg, TX_RTY_CFG_SHORT_RTY_LIMIT,
3138                            libconf->conf->short_frame_max_tx_count);
3139         rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_LIMIT,
3140                            libconf->conf->long_frame_max_tx_count);
3141         rt2800_register_write(rt2x00dev, TX_RTY_CFG, reg);
3142 }
3143
3144 static void rt2800_config_ps(struct rt2x00_dev *rt2x00dev,
3145                              struct rt2x00lib_conf *libconf)
3146 {
3147         enum dev_state state =
3148             (libconf->conf->flags & IEEE80211_CONF_PS) ?
3149                 STATE_SLEEP : STATE_AWAKE;
3150         u32 reg;
3151
3152         if (state == STATE_SLEEP) {
3153                 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0);
3154
3155                 rt2800_register_read(rt2x00dev, AUTOWAKEUP_CFG, &reg);
3156                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 5);
3157                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE,
3158                                    libconf->conf->listen_interval - 1);
3159                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTOWAKE, 1);
3160                 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg);
3161
3162                 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
3163         } else {
3164                 rt2800_register_read(rt2x00dev, AUTOWAKEUP_CFG, &reg);
3165                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 0);
3166                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE, 0);
3167                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTOWAKE, 0);
3168                 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg);
3169
3170                 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
3171         }
3172 }
3173
3174 void rt2800_config(struct rt2x00_dev *rt2x00dev,
3175                    struct rt2x00lib_conf *libconf,
3176                    const unsigned int flags)
3177 {
3178         /* Always recalculate LNA gain before changing configuration */
3179         rt2800_config_lna_gain(rt2x00dev, libconf);
3180
3181         if (flags & IEEE80211_CONF_CHANGE_CHANNEL) {
3182                 rt2800_config_channel(rt2x00dev, libconf->conf,
3183                                       &libconf->rf, &libconf->channel);
3184                 rt2800_config_txpower(rt2x00dev, libconf->conf->channel,
3185                                       libconf->conf->power_level);
3186         }
3187         if (flags & IEEE80211_CONF_CHANGE_POWER)
3188                 rt2800_config_txpower(rt2x00dev, libconf->conf->channel,
3189                                       libconf->conf->power_level);
3190         if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
3191                 rt2800_config_retry_limit(rt2x00dev, libconf);
3192         if (flags & IEEE80211_CONF_CHANGE_PS)
3193                 rt2800_config_ps(rt2x00dev, libconf);
3194 }
3195 EXPORT_SYMBOL_GPL(rt2800_config);
3196
3197 /*
3198  * Link tuning
3199  */
3200 void rt2800_link_stats(struct rt2x00_dev *rt2x00dev, struct link_qual *qual)
3201 {
3202         u32 reg;
3203
3204         /*
3205          * Update FCS error count from register.
3206          */
3207         rt2800_register_read(rt2x00dev, RX_STA_CNT0, &reg);
3208         qual->rx_failed = rt2x00_get_field32(reg, RX_STA_CNT0_CRC_ERR);
3209 }
3210 EXPORT_SYMBOL_GPL(rt2800_link_stats);
3211
3212 static u8 rt2800_get_default_vgc(struct rt2x00_dev *rt2x00dev)
3213 {
3214         u8 vgc;
3215
3216         if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ) {
3217                 if (rt2x00_rt(rt2x00dev, RT3070) ||
3218                     rt2x00_rt(rt2x00dev, RT3071) ||
3219                     rt2x00_rt(rt2x00dev, RT3090) ||
3220                     rt2x00_rt(rt2x00dev, RT3290) ||
3221                     rt2x00_rt(rt2x00dev, RT3390) ||
3222                     rt2x00_rt(rt2x00dev, RT3572) ||
3223                     rt2x00_rt(rt2x00dev, RT5390) ||
3224                     rt2x00_rt(rt2x00dev, RT5392))
3225                         vgc = 0x1c + (2 * rt2x00dev->lna_gain);
3226                 else
3227                         vgc = 0x2e + rt2x00dev->lna_gain;
3228         } else { /* 5GHZ band */
3229                 if (rt2x00_rt(rt2x00dev, RT3572))
3230                         vgc = 0x22 + (rt2x00dev->lna_gain * 5) / 3;
3231                 else {
3232                         if (!test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags))
3233                                 vgc = 0x32 + (rt2x00dev->lna_gain * 5) / 3;
3234                         else
3235                                 vgc = 0x3a + (rt2x00dev->lna_gain * 5) / 3;
3236                 }
3237         }
3238
3239         return vgc;
3240 }
3241
3242 static inline void rt2800_set_vgc(struct rt2x00_dev *rt2x00dev,
3243                                   struct link_qual *qual, u8 vgc_level)
3244 {
3245         if (qual->vgc_level != vgc_level) {
3246                 rt2800_bbp_write(rt2x00dev, 66, vgc_level);
3247                 qual->vgc_level = vgc_level;
3248                 qual->vgc_level_reg = vgc_level;
3249         }
3250 }
3251
3252 void rt2800_reset_tuner(struct rt2x00_dev *rt2x00dev, struct link_qual *qual)
3253 {
3254         rt2800_set_vgc(rt2x00dev, qual, rt2800_get_default_vgc(rt2x00dev));
3255 }
3256 EXPORT_SYMBOL_GPL(rt2800_reset_tuner);
3257
3258 void rt2800_link_tuner(struct rt2x00_dev *rt2x00dev, struct link_qual *qual,
3259                        const u32 count)
3260 {
3261         if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C))
3262                 return;
3263
3264         /*
3265          * When RSSI is better then -80 increase VGC level with 0x10
3266          */
3267         rt2800_set_vgc(rt2x00dev, qual,
3268                        rt2800_get_default_vgc(rt2x00dev) +
3269                        ((qual->rssi > -80) * 0x10));
3270 }
3271 EXPORT_SYMBOL_GPL(rt2800_link_tuner);
3272
3273 /*
3274  * Initialization functions.
3275  */
3276 static int rt2800_init_registers(struct rt2x00_dev *rt2x00dev)
3277 {
3278         u32 reg;
3279         u16 eeprom;
3280         unsigned int i;
3281         int ret;
3282
3283         rt2800_disable_wpdma(rt2x00dev);
3284
3285         ret = rt2800_drv_init_registers(rt2x00dev);
3286         if (ret)
3287                 return ret;
3288
3289         rt2800_register_read(rt2x00dev, BCN_OFFSET0, &reg);
3290         rt2x00_set_field32(&reg, BCN_OFFSET0_BCN0, 0xe0); /* 0x3800 */
3291         rt2x00_set_field32(&reg, BCN_OFFSET0_BCN1, 0xe8); /* 0x3a00 */
3292         rt2x00_set_field32(&reg, BCN_OFFSET0_BCN2, 0xf0); /* 0x3c00 */
3293         rt2x00_set_field32(&reg, BCN_OFFSET0_BCN3, 0xf8); /* 0x3e00 */
3294         rt2800_register_write(rt2x00dev, BCN_OFFSET0, reg);
3295
3296         rt2800_register_read(rt2x00dev, BCN_OFFSET1, &reg);
3297         rt2x00_set_field32(&reg, BCN_OFFSET1_BCN4, 0xc8); /* 0x3200 */
3298         rt2x00_set_field32(&reg, BCN_OFFSET1_BCN5, 0xd0); /* 0x3400 */
3299         rt2x00_set_field32(&reg, BCN_OFFSET1_BCN6, 0x77); /* 0x1dc0 */
3300         rt2x00_set_field32(&reg, BCN_OFFSET1_BCN7, 0x6f); /* 0x1bc0 */
3301         rt2800_register_write(rt2x00dev, BCN_OFFSET1, reg);
3302
3303         rt2800_register_write(rt2x00dev, LEGACY_BASIC_RATE, 0x0000013f);
3304         rt2800_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
3305
3306         rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000);
3307
3308         rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
3309         rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL, 1600);
3310         rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 0);
3311         rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, 0);
3312         rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 0);
3313         rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
3314         rt2x00_set_field32(&reg, BCN_TIME_CFG_TX_TIME_COMPENSATE, 0);
3315         rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
3316
3317         rt2800_config_filter(rt2x00dev, FIF_ALLMULTI);
3318
3319         rt2800_register_read(rt2x00dev, BKOFF_SLOT_CFG, &reg);
3320         rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_SLOT_TIME, 9);
3321         rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_CC_DELAY_TIME, 2);
3322         rt2800_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg);
3323
3324         if (rt2x00_rt(rt2x00dev, RT3290)) {
3325                 rt2800_register_read(rt2x00dev, WLAN_FUN_CTRL, &reg);
3326                 if (rt2x00_get_field32(reg, WLAN_EN) == 1) {
3327                         rt2x00_set_field32(&reg, PCIE_APP0_CLK_REQ, 1);
3328                         rt2800_register_write(rt2x00dev, WLAN_FUN_CTRL, reg);
3329                 }
3330
3331                 rt2800_register_read(rt2x00dev, CMB_CTRL, &reg);
3332                 if (!(rt2x00_get_field32(reg, LDO0_EN) == 1)) {
3333                         rt2x00_set_field32(&reg, LDO0_EN, 1);
3334                         rt2x00_set_field32(&reg, LDO_BGSEL, 3);
3335                         rt2800_register_write(rt2x00dev, CMB_CTRL, reg);
3336                 }
3337
3338                 rt2800_register_read(rt2x00dev, OSC_CTRL, &reg);
3339                 rt2x00_set_field32(&reg, OSC_ROSC_EN, 1);
3340                 rt2x00_set_field32(&reg, OSC_CAL_REQ, 1);
3341                 rt2x00_set_field32(&reg, OSC_REF_CYCLE, 0x27);
3342                 rt2800_register_write(rt2x00dev, OSC_CTRL, reg);
3343
3344                 rt2800_register_read(rt2x00dev, COEX_CFG0, &reg);
3345                 rt2x00_set_field32(&reg, COEX_CFG_ANT, 0x5e);
3346                 rt2800_register_write(rt2x00dev, COEX_CFG0, reg);
3347
3348                 rt2800_register_read(rt2x00dev, COEX_CFG2, &reg);
3349                 rt2x00_set_field32(&reg, BT_COEX_CFG1, 0x00);
3350                 rt2x00_set_field32(&reg, BT_COEX_CFG0, 0x17);
3351                 rt2x00_set_field32(&reg, WL_COEX_CFG1, 0x93);
3352                 rt2x00_set_field32(&reg, WL_COEX_CFG0, 0x7f);
3353                 rt2800_register_write(rt2x00dev, COEX_CFG2, reg);
3354
3355                 rt2800_register_read(rt2x00dev, PLL_CTRL, &reg);
3356                 rt2x00_set_field32(&reg, PLL_CONTROL, 1);
3357                 rt2800_register_write(rt2x00dev, PLL_CTRL, reg);
3358         }
3359
3360         if (rt2x00_rt(rt2x00dev, RT3071) ||
3361             rt2x00_rt(rt2x00dev, RT3090) ||
3362             rt2x00_rt(rt2x00dev, RT3290) ||
3363             rt2x00_rt(rt2x00dev, RT3390)) {
3364
3365                 if (rt2x00_rt(rt2x00dev, RT3290))
3366                         rt2800_register_write(rt2x00dev, TX_SW_CFG0,
3367                                               0x00000404);
3368                 else
3369                         rt2800_register_write(rt2x00dev, TX_SW_CFG0,
3370                                               0x00000400);
3371
3372                 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
3373                 if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
3374                     rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) ||
3375                     rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E)) {
3376                         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
3377                         if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_DAC_TEST))
3378                                 rt2800_register_write(rt2x00dev, TX_SW_CFG2,
3379                                                       0x0000002c);
3380                         else
3381                                 rt2800_register_write(rt2x00dev, TX_SW_CFG2,
3382                                                       0x0000000f);
3383                 } else {
3384                         rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
3385                 }
3386         } else if (rt2x00_rt(rt2x00dev, RT3070)) {
3387                 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
3388
3389                 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F)) {
3390                         rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
3391                         rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x0000002c);
3392                 } else {
3393                         rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
3394                         rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
3395                 }
3396         } else if (rt2800_is_305x_soc(rt2x00dev)) {
3397                 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
3398                 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
3399                 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000030);
3400         } else if (rt2x00_rt(rt2x00dev, RT3352)) {
3401                 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000402);
3402                 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
3403                 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
3404         } else if (rt2x00_rt(rt2x00dev, RT3572)) {
3405                 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
3406                 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
3407         } else if (rt2x00_rt(rt2x00dev, RT5390) ||
3408                    rt2x00_rt(rt2x00dev, RT5392) ||
3409                    rt2x00_rt(rt2x00dev, RT5592)) {
3410                 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000404);
3411                 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
3412                 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
3413         } else {
3414                 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000000);
3415                 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
3416         }
3417
3418         rt2800_register_read(rt2x00dev, TX_LINK_CFG, &reg);
3419         rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB_LIFETIME, 32);
3420         rt2x00_set_field32(&reg, TX_LINK_CFG_MFB_ENABLE, 0);
3421         rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_UMFS_ENABLE, 0);
3422         rt2x00_set_field32(&reg, TX_LINK_CFG_TX_MRQ_EN, 0);
3423         rt2x00_set_field32(&reg, TX_LINK_CFG_TX_RDG_EN, 0);
3424         rt2x00_set_field32(&reg, TX_LINK_CFG_TX_CF_ACK_EN, 1);
3425         rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB, 0);
3426         rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFS, 0);
3427         rt2800_register_write(rt2x00dev, TX_LINK_CFG, reg);
3428
3429         rt2800_register_read(rt2x00dev, TX_TIMEOUT_CFG, &reg);
3430         rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_MPDU_LIFETIME, 9);
3431         rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_RX_ACK_TIMEOUT, 32);
3432         rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_TX_OP_TIMEOUT, 10);
3433         rt2800_register_write(rt2x00dev, TX_TIMEOUT_CFG, reg);
3434
3435         rt2800_register_read(rt2x00dev, MAX_LEN_CFG, &reg);
3436         rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_MPDU, AGGREGATION_SIZE);
3437         if (rt2x00_rt_rev_gte(rt2x00dev, RT2872, REV_RT2872E) ||
3438             rt2x00_rt(rt2x00dev, RT2883) ||
3439             rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070E))
3440                 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, 2);
3441         else
3442                 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, 1);
3443         rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_PSDU, 0);
3444         rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_MPDU, 0);
3445         rt2800_register_write(rt2x00dev, MAX_LEN_CFG, reg);
3446
3447         rt2800_register_read(rt2x00dev, LED_CFG, &reg);
3448         rt2x00_set_field32(&reg, LED_CFG_ON_PERIOD, 70);
3449         rt2x00_set_field32(&reg, LED_CFG_OFF_PERIOD, 30);
3450         rt2x00_set_field32(&reg, LED_CFG_SLOW_BLINK_PERIOD, 3);
3451         rt2x00_set_field32(&reg, LED_CFG_R_LED_MODE, 3);
3452         rt2x00_set_field32(&reg, LED_CFG_G_LED_MODE, 3);
3453         rt2x00_set_field32(&reg, LED_CFG_Y_LED_MODE, 3);
3454         rt2x00_set_field32(&reg, LED_CFG_LED_POLAR, 1);
3455         rt2800_register_write(rt2x00dev, LED_CFG, reg);
3456
3457         rt2800_register_write(rt2x00dev, PBF_MAX_PCNT, 0x1f3fbf9f);
3458
3459         rt2800_register_read(rt2x00dev, TX_RTY_CFG, &reg);
3460         rt2x00_set_field32(&reg, TX_RTY_CFG_SHORT_RTY_LIMIT, 15);
3461         rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_LIMIT, 31);
3462         rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_THRE, 2000);
3463         rt2x00_set_field32(&reg, TX_RTY_CFG_NON_AGG_RTY_MODE, 0);
3464         rt2x00_set_field32(&reg, TX_RTY_CFG_AGG_RTY_MODE, 0);
3465         rt2x00_set_field32(&reg, TX_RTY_CFG_TX_AUTO_FB_ENABLE, 1);
3466         rt2800_register_write(rt2x00dev, TX_RTY_CFG, reg);
3467
3468         rt2800_register_read(rt2x00dev, AUTO_RSP_CFG, &reg);
3469         rt2x00_set_field32(&reg, AUTO_RSP_CFG_AUTORESPONDER, 1);
3470         rt2x00_set_field32(&reg, AUTO_RSP_CFG_BAC_ACK_POLICY, 1);
3471         rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MMODE, 0);
3472         rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MREF, 0);
3473         rt2x00_set_field32(&reg, AUTO_RSP_CFG_AR_PREAMBLE, 1);
3474         rt2x00_set_field32(&reg, AUTO_RSP_CFG_DUAL_CTS_EN, 0);
3475         rt2x00_set_field32(&reg, AUTO_RSP_CFG_ACK_CTS_PSM_BIT, 0);
3476         rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
3477
3478         rt2800_register_read(rt2x00dev, CCK_PROT_CFG, &reg);
3479         rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_RATE, 3);
3480         rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_CTRL, 0);
3481         rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_NAV_SHORT, 1);
3482         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_CCK, 1);
3483         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
3484         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM20, 1);
3485         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM40, 0);
3486         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF20, 1);
3487         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF40, 0);
3488         rt2x00_set_field32(&reg, CCK_PROT_CFG_RTS_TH_EN, 1);
3489         rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg);
3490
3491         rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
3492         rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_RATE, 3);
3493         rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL, 0);
3494         rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_NAV_SHORT, 1);
3495         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_CCK, 1);
3496         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
3497         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM20, 1);
3498         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM40, 0);
3499         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF20, 1);
3500         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF40, 0);
3501         rt2x00_set_field32(&reg, OFDM_PROT_CFG_RTS_TH_EN, 1);
3502         rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
3503
3504         rt2800_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
3505         rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_RATE, 0x4004);
3506         rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_CTRL, 0);
3507         rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_NAV_SHORT, 1);
3508         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_CCK, 1);
3509         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
3510         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
3511         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
3512         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
3513         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
3514         rt2x00_set_field32(&reg, MM20_PROT_CFG_RTS_TH_EN, 0);
3515         rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
3516
3517         rt2800_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
3518         rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_RATE, 0x4084);
3519         rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_CTRL, 0);
3520         rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_NAV_SHORT, 1);
3521         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_CCK, 1);
3522         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
3523         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
3524         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
3525         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
3526         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
3527         rt2x00_set_field32(&reg, MM40_PROT_CFG_RTS_TH_EN, 0);
3528         rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
3529
3530         rt2800_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
3531         rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_RATE, 0x4004);
3532         rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_CTRL, 0);
3533         rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_NAV_SHORT, 1);
3534         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_CCK, 1);
3535         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
3536         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
3537         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
3538         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
3539         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
3540         rt2x00_set_field32(&reg, GF20_PROT_CFG_RTS_TH_EN, 0);
3541         rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
3542
3543         rt2800_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
3544         rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_RATE, 0x4084);
3545         rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_CTRL, 0);
3546         rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_NAV_SHORT, 1);
3547         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_CCK, 1);
3548         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
3549         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
3550         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
3551         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
3552         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
3553         rt2x00_set_field32(&reg, GF40_PROT_CFG_RTS_TH_EN, 0);
3554         rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
3555
3556         if (rt2x00_is_usb(rt2x00dev)) {
3557                 rt2800_register_write(rt2x00dev, PBF_CFG, 0xf40006);
3558
3559                 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
3560                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
3561                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
3562                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
3563                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
3564                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE, 3);
3565                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 0);
3566                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_BIG_ENDIAN, 0);
3567                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_HDR_SCATTER, 0);
3568                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_HDR_SEG_LEN, 0);
3569                 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
3570         }
3571
3572         /*
3573          * The legacy driver also sets TXOP_CTRL_CFG_RESERVED_TRUN_EN to 1
3574          * although it is reserved.
3575          */
3576         rt2800_register_read(rt2x00dev, TXOP_CTRL_CFG, &reg);
3577         rt2x00_set_field32(&reg, TXOP_CTRL_CFG_TIMEOUT_TRUN_EN, 1);
3578         rt2x00_set_field32(&reg, TXOP_CTRL_CFG_AC_TRUN_EN, 1);
3579         rt2x00_set_field32(&reg, TXOP_CTRL_CFG_TXRATEGRP_TRUN_EN, 1);
3580         rt2x00_set_field32(&reg, TXOP_CTRL_CFG_USER_MODE_TRUN_EN, 1);
3581         rt2x00_set_field32(&reg, TXOP_CTRL_CFG_MIMO_PS_TRUN_EN, 1);
3582         rt2x00_set_field32(&reg, TXOP_CTRL_CFG_RESERVED_TRUN_EN, 1);
3583         rt2x00_set_field32(&reg, TXOP_CTRL_CFG_LSIG_TXOP_EN, 0);
3584         rt2x00_set_field32(&reg, TXOP_CTRL_CFG_EXT_CCA_EN, 0);
3585         rt2x00_set_field32(&reg, TXOP_CTRL_CFG_EXT_CCA_DLY, 88);
3586         rt2x00_set_field32(&reg, TXOP_CTRL_CFG_EXT_CWMIN, 0);
3587         rt2800_register_write(rt2x00dev, TXOP_CTRL_CFG, reg);
3588
3589         reg = rt2x00_rt(rt2x00dev, RT5592) ? 0x00000082 : 0x00000002;
3590         rt2800_register_write(rt2x00dev, TXOP_HLDR_ET, reg);
3591
3592         rt2800_register_read(rt2x00dev, TX_RTS_CFG, &reg);
3593         rt2x00_set_field32(&reg, TX_RTS_CFG_AUTO_RTS_RETRY_LIMIT, 32);
3594         rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_THRES,
3595                            IEEE80211_MAX_RTS_THRESHOLD);
3596         rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_FBK_EN, 0);
3597         rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg);
3598
3599         rt2800_register_write(rt2x00dev, EXP_ACK_TIME, 0x002400ca);
3600
3601         /*
3602          * Usually the CCK SIFS time should be set to 10 and the OFDM SIFS
3603          * time should be set to 16. However, the original Ralink driver uses
3604          * 16 for both and indeed using a value of 10 for CCK SIFS results in
3605          * connection problems with 11g + CTS protection. Hence, use the same
3606          * defaults as the Ralink driver: 16 for both, CCK and OFDM SIFS.
3607          */
3608         rt2800_register_read(rt2x00dev, XIFS_TIME_CFG, &reg);
3609         rt2x00_set_field32(&reg, XIFS_TIME_CFG_CCKM_SIFS_TIME, 16);
3610         rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_SIFS_TIME, 16);
3611         rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_XIFS_TIME, 4);
3612         rt2x00_set_field32(&reg, XIFS_TIME_CFG_EIFS, 314);
3613         rt2x00_set_field32(&reg, XIFS_TIME_CFG_BB_RXEND_ENABLE, 1);
3614         rt2800_register_write(rt2x00dev, XIFS_TIME_CFG, reg);
3615
3616         rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000003);
3617
3618         /*
3619          * ASIC will keep garbage value after boot, clear encryption keys.
3620          */
3621         for (i = 0; i < 4; i++)
3622                 rt2800_register_write(rt2x00dev,
3623                                          SHARED_KEY_MODE_ENTRY(i), 0);
3624
3625         for (i = 0; i < 256; i++) {
3626                 rt2800_config_wcid(rt2x00dev, NULL, i);
3627                 rt2800_delete_wcid_attr(rt2x00dev, i);
3628                 rt2800_register_write(rt2x00dev, MAC_IVEIV_ENTRY(i), 0);
3629         }
3630
3631         /*
3632          * Clear all beacons
3633          */
3634         rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE0);
3635         rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE1);
3636         rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE2);
3637         rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE3);
3638         rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE4);
3639         rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE5);
3640         rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE6);
3641         rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE7);
3642
3643         if (rt2x00_is_usb(rt2x00dev)) {
3644                 rt2800_register_read(rt2x00dev, US_CYC_CNT, &reg);
3645                 rt2x00_set_field32(&reg, US_CYC_CNT_CLOCK_CYCLE, 30);
3646                 rt2800_register_write(rt2x00dev, US_CYC_CNT, reg);
3647         } else if (rt2x00_is_pcie(rt2x00dev)) {
3648                 rt2800_register_read(rt2x00dev, US_CYC_CNT, &reg);
3649                 rt2x00_set_field32(&reg, US_CYC_CNT_CLOCK_CYCLE, 125);
3650                 rt2800_register_write(rt2x00dev, US_CYC_CNT, reg);
3651         }
3652
3653         rt2800_register_read(rt2x00dev, HT_FBK_CFG0, &reg);
3654         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS0FBK, 0);
3655         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS1FBK, 0);
3656         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS2FBK, 1);
3657         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS3FBK, 2);
3658         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS4FBK, 3);
3659         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS5FBK, 4);
3660         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS6FBK, 5);
3661         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS7FBK, 6);
3662         rt2800_register_write(rt2x00dev, HT_FBK_CFG0, reg);
3663
3664         rt2800_register_read(rt2x00dev, HT_FBK_CFG1, &reg);
3665         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS8FBK, 8);
3666         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS9FBK, 8);
3667         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS10FBK, 9);
3668         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS11FBK, 10);
3669         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS12FBK, 11);
3670         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS13FBK, 12);
3671         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS14FBK, 13);
3672         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS15FBK, 14);
3673         rt2800_register_write(rt2x00dev, HT_FBK_CFG1, reg);
3674
3675         rt2800_register_read(rt2x00dev, LG_FBK_CFG0, &reg);
3676         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS0FBK, 8);
3677         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS1FBK, 8);
3678         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS2FBK, 9);
3679         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS3FBK, 10);
3680         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS4FBK, 11);
3681         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS5FBK, 12);
3682         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS6FBK, 13);
3683         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS7FBK, 14);
3684         rt2800_register_write(rt2x00dev, LG_FBK_CFG0, reg);
3685
3686         rt2800_register_read(rt2x00dev, LG_FBK_CFG1, &reg);
3687         rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS0FBK, 0);
3688         rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS1FBK, 0);
3689         rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS2FBK, 1);
3690         rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS3FBK, 2);
3691         rt2800_register_write(rt2x00dev, LG_FBK_CFG1, reg);
3692
3693         /*
3694          * Do not force the BA window size, we use the TXWI to set it
3695          */
3696         rt2800_register_read(rt2x00dev, AMPDU_BA_WINSIZE, &reg);
3697         rt2x00_set_field32(&reg, AMPDU_BA_WINSIZE_FORCE_WINSIZE_ENABLE, 0);
3698         rt2x00_set_field32(&reg, AMPDU_BA_WINSIZE_FORCE_WINSIZE, 0);
3699         rt2800_register_write(rt2x00dev, AMPDU_BA_WINSIZE, reg);
3700
3701         /*
3702          * We must clear the error counters.
3703          * These registers are cleared on read,
3704          * so we may pass a useless variable to store the value.
3705          */
3706         rt2800_register_read(rt2x00dev, RX_STA_CNT0, &reg);
3707         rt2800_register_read(rt2x00dev, RX_STA_CNT1, &reg);
3708         rt2800_register_read(rt2x00dev, RX_STA_CNT2, &reg);
3709         rt2800_register_read(rt2x00dev, TX_STA_CNT0, &reg);
3710         rt2800_register_read(rt2x00dev, TX_STA_CNT1, &reg);
3711         rt2800_register_read(rt2x00dev, TX_STA_CNT2, &reg);
3712
3713         /*
3714          * Setup leadtime for pre tbtt interrupt to 6ms
3715          */
3716         rt2800_register_read(rt2x00dev, INT_TIMER_CFG, &reg);
3717         rt2x00_set_field32(&reg, INT_TIMER_CFG_PRE_TBTT_TIMER, 6 << 4);
3718         rt2800_register_write(rt2x00dev, INT_TIMER_CFG, reg);
3719
3720         /*
3721          * Set up channel statistics timer
3722          */
3723         rt2800_register_read(rt2x00dev, CH_TIME_CFG, &reg);
3724         rt2x00_set_field32(&reg, CH_TIME_CFG_EIFS_BUSY, 1);
3725         rt2x00_set_field32(&reg, CH_TIME_CFG_NAV_BUSY, 1);
3726         rt2x00_set_field32(&reg, CH_TIME_CFG_RX_BUSY, 1);
3727         rt2x00_set_field32(&reg, CH_TIME_CFG_TX_BUSY, 1);
3728         rt2x00_set_field32(&reg, CH_TIME_CFG_TMR_EN, 1);
3729         rt2800_register_write(rt2x00dev, CH_TIME_CFG, reg);
3730
3731         return 0;
3732 }
3733
3734 static int rt2800_wait_bbp_rf_ready(struct rt2x00_dev *rt2x00dev)
3735 {
3736         unsigned int i;
3737         u32 reg;
3738
3739         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
3740                 rt2800_register_read(rt2x00dev, MAC_STATUS_CFG, &reg);
3741                 if (!rt2x00_get_field32(reg, MAC_STATUS_CFG_BBP_RF_BUSY))
3742                         return 0;
3743
3744                 udelay(REGISTER_BUSY_DELAY);
3745         }
3746
3747         ERROR(rt2x00dev, "BBP/RF register access failed, aborting.\n");
3748         return -EACCES;
3749 }
3750
3751 static int rt2800_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)
3752 {
3753         unsigned int i;
3754         u8 value;
3755
3756         /*
3757          * BBP was enabled after firmware was loaded,
3758          * but we need to reactivate it now.
3759          */
3760         rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
3761         rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
3762         msleep(1);
3763
3764         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
3765                 rt2800_bbp_read(rt2x00dev, 0, &value);
3766                 if ((value != 0xff) && (value != 0x00))
3767                         return 0;
3768                 udelay(REGISTER_BUSY_DELAY);
3769         }
3770
3771         ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
3772         return -EACCES;
3773 }
3774
3775 static void rt2800_bbp4_mac_if_ctrl(struct rt2x00_dev *rt2x00dev)
3776 {
3777         u8 value;
3778
3779         rt2800_bbp_read(rt2x00dev, 4, &value);
3780         rt2x00_set_field8(&value, BBP4_MAC_IF_CTRL, 1);
3781         rt2800_bbp_write(rt2x00dev, 4, value);
3782 }
3783
3784 static void rt2800_init_freq_calibration(struct rt2x00_dev *rt2x00dev)
3785 {
3786         rt2800_bbp_write(rt2x00dev, 142, 1);
3787         rt2800_bbp_write(rt2x00dev, 143, 57);
3788 }
3789
3790 static void rt2800_init_bbp_5592_glrt(struct rt2x00_dev *rt2x00dev)
3791 {
3792         const u8 glrt_table[] = {
3793                 0xE0, 0x1F, 0X38, 0x32, 0x08, 0x28, 0x19, 0x0A, 0xFF, 0x00, /* 128 ~ 137 */
3794                 0x16, 0x10, 0x10, 0x0B, 0x36, 0x2C, 0x26, 0x24, 0x42, 0x36, /* 138 ~ 147 */
3795                 0x30, 0x2D, 0x4C, 0x46, 0x3D, 0x40, 0x3E, 0x42, 0x3D, 0x40, /* 148 ~ 157 */
3796                 0X3C, 0x34, 0x2C, 0x2F, 0x3C, 0x35, 0x2E, 0x2A, 0x49, 0x41, /* 158 ~ 167 */
3797                 0x36, 0x31, 0x30, 0x30, 0x0E, 0x0D, 0x28, 0x21, 0x1C, 0x16, /* 168 ~ 177 */
3798                 0x50, 0x4A, 0x43, 0x40, 0x10, 0x10, 0x10, 0x10, 0x00, 0x00, /* 178 ~ 187 */
3799                 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 188 ~ 197 */
3800                 0x00, 0x00, 0x7D, 0x14, 0x32, 0x2C, 0x36, 0x4C, 0x43, 0x2C, /* 198 ~ 207 */
3801                 0x2E, 0x36, 0x30, 0x6E,                                     /* 208 ~ 211 */
3802         };
3803         int i;
3804
3805         for (i = 0; i < ARRAY_SIZE(glrt_table); i++) {
3806                 rt2800_bbp_write(rt2x00dev, 195, 128 + i);
3807                 rt2800_bbp_write(rt2x00dev, 196, glrt_table[i]);
3808         }
3809 };
3810
3811 static void rt2800_init_bbb_early(struct rt2x00_dev *rt2x00dev)
3812 {
3813         rt2800_bbp_write(rt2x00dev, 65, 0x2C);
3814         rt2800_bbp_write(rt2x00dev, 66, 0x38);
3815         rt2800_bbp_write(rt2x00dev, 68, 0x0B);
3816         rt2800_bbp_write(rt2x00dev, 69, 0x12);
3817         rt2800_bbp_write(rt2x00dev, 70, 0x0a);
3818         rt2800_bbp_write(rt2x00dev, 73, 0x10);
3819         rt2800_bbp_write(rt2x00dev, 81, 0x37);
3820         rt2800_bbp_write(rt2x00dev, 82, 0x62);
3821         rt2800_bbp_write(rt2x00dev, 83, 0x6A);
3822         rt2800_bbp_write(rt2x00dev, 84, 0x99);
3823         rt2800_bbp_write(rt2x00dev, 86, 0x00);
3824         rt2800_bbp_write(rt2x00dev, 91, 0x04);
3825         rt2800_bbp_write(rt2x00dev, 92, 0x00);
3826         rt2800_bbp_write(rt2x00dev, 103, 0x00);
3827         rt2800_bbp_write(rt2x00dev, 105, 0x05);
3828         rt2800_bbp_write(rt2x00dev, 106, 0x35);
3829 }
3830
3831 static void rt2800_init_bbp_5592(struct rt2x00_dev *rt2x00dev)
3832 {
3833         int ant, div_mode;
3834         u16 eeprom;
3835         u8 value;
3836
3837         rt2800_init_bbb_early(rt2x00dev);
3838
3839         rt2800_bbp_read(rt2x00dev, 105, &value);
3840         rt2x00_set_field8(&value, BBP105_MLD,
3841                           rt2x00dev->default_ant.rx_chain_num == 2);
3842         rt2800_bbp_write(rt2x00dev, 105, value);
3843
3844         rt2800_bbp4_mac_if_ctrl(rt2x00dev);
3845
3846         rt2800_bbp_write(rt2x00dev, 20, 0x06);
3847         rt2800_bbp_write(rt2x00dev, 31, 0x08);
3848         rt2800_bbp_write(rt2x00dev, 65, 0x2C);
3849         rt2800_bbp_write(rt2x00dev, 68, 0xDD);
3850         rt2800_bbp_write(rt2x00dev, 69, 0x1A);
3851         rt2800_bbp_write(rt2x00dev, 70, 0x05);
3852         rt2800_bbp_write(rt2x00dev, 73, 0x13);
3853         rt2800_bbp_write(rt2x00dev, 74, 0x0F);
3854         rt2800_bbp_write(rt2x00dev, 75, 0x4F);
3855         rt2800_bbp_write(rt2x00dev, 76, 0x28);
3856         rt2800_bbp_write(rt2x00dev, 77, 0x59);
3857         rt2800_bbp_write(rt2x00dev, 84, 0x9A);
3858         rt2800_bbp_write(rt2x00dev, 86, 0x38);
3859         rt2800_bbp_write(rt2x00dev, 88, 0x90);
3860         rt2800_bbp_write(rt2x00dev, 91, 0x04);
3861         rt2800_bbp_write(rt2x00dev, 92, 0x02);
3862         rt2800_bbp_write(rt2x00dev, 95, 0x9a);
3863         rt2800_bbp_write(rt2x00dev, 98, 0x12);
3864         rt2800_bbp_write(rt2x00dev, 103, 0xC0);
3865         rt2800_bbp_write(rt2x00dev, 104, 0x92);
3866         /* FIXME BBP105 owerwrite */
3867         rt2800_bbp_write(rt2x00dev, 105, 0x3C);
3868         rt2800_bbp_write(rt2x00dev, 106, 0x35);
3869         rt2800_bbp_write(rt2x00dev, 128, 0x12);
3870         rt2800_bbp_write(rt2x00dev, 134, 0xD0);
3871         rt2800_bbp_write(rt2x00dev, 135, 0xF6);
3872         rt2800_bbp_write(rt2x00dev, 137, 0x0F);
3873
3874         /* Initialize GLRT (Generalized Likehood Radio Test) */
3875         rt2800_init_bbp_5592_glrt(rt2x00dev);
3876
3877         rt2800_bbp4_mac_if_ctrl(rt2x00dev);
3878
3879         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
3880         div_mode = rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_ANT_DIVERSITY);
3881         ant = (div_mode == 3) ? 1 : 0;
3882         rt2800_bbp_read(rt2x00dev, 152, &value);
3883         if (ant == 0) {
3884                 /* Main antenna */
3885                 rt2x00_set_field8(&value, BBP152_RX_DEFAULT_ANT, 1);
3886         } else {
3887                 /* Auxiliary antenna */
3888                 rt2x00_set_field8(&value, BBP152_RX_DEFAULT_ANT, 0);
3889         }
3890         rt2800_bbp_write(rt2x00dev, 152, value);
3891
3892         if (rt2x00_rt_rev_gte(rt2x00dev, RT5592, REV_RT5592C)) {
3893                 rt2800_bbp_read(rt2x00dev, 254, &value);
3894                 rt2x00_set_field8(&value, BBP254_BIT7, 1);
3895                 rt2800_bbp_write(rt2x00dev, 254, value);
3896         }
3897
3898         rt2800_init_freq_calibration(rt2x00dev);
3899
3900         rt2800_bbp_write(rt2x00dev, 84, 0x19);
3901         if (rt2x00_rt_rev_gte(rt2x00dev, RT5592, REV_RT5592C))
3902                 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
3903 }
3904
3905 static int rt2800_init_bbp(struct rt2x00_dev *rt2x00dev)
3906 {
3907         unsigned int i;
3908         u16 eeprom;
3909         u8 reg_id;
3910         u8 value;
3911
3912         if (unlikely(rt2800_wait_bbp_rf_ready(rt2x00dev) ||
3913                      rt2800_wait_bbp_ready(rt2x00dev)))
3914                 return -EACCES;
3915
3916         if (rt2x00_rt(rt2x00dev, RT5592)) {
3917                 rt2800_init_bbp_5592(rt2x00dev);
3918                 return 0;
3919         }
3920
3921         if (rt2x00_rt(rt2x00dev, RT3352)) {
3922                 rt2800_bbp_write(rt2x00dev, 3, 0x00);
3923                 rt2800_bbp_write(rt2x00dev, 4, 0x50);
3924         }
3925
3926         if (rt2x00_rt(rt2x00dev, RT3290) ||
3927             rt2x00_rt(rt2x00dev, RT5390) ||
3928             rt2x00_rt(rt2x00dev, RT5392))
3929                 rt2800_bbp4_mac_if_ctrl(rt2x00dev);
3930
3931         if (rt2800_is_305x_soc(rt2x00dev) ||
3932             rt2x00_rt(rt2x00dev, RT3290) ||
3933             rt2x00_rt(rt2x00dev, RT3352) ||
3934             rt2x00_rt(rt2x00dev, RT3572) ||
3935             rt2x00_rt(rt2x00dev, RT5390) ||
3936             rt2x00_rt(rt2x00dev, RT5392))
3937                 rt2800_bbp_write(rt2x00dev, 31, 0x08);
3938
3939         if (rt2x00_rt(rt2x00dev, RT3352))
3940                 rt2800_bbp_write(rt2x00dev, 47, 0x48);
3941
3942         rt2800_bbp_write(rt2x00dev, 65, 0x2c);
3943         rt2800_bbp_write(rt2x00dev, 66, 0x38);
3944
3945         if (rt2x00_rt(rt2x00dev, RT3290) ||
3946             rt2x00_rt(rt2x00dev, RT3352) ||
3947             rt2x00_rt(rt2x00dev, RT5390) ||
3948             rt2x00_rt(rt2x00dev, RT5392))
3949                 rt2800_bbp_write(rt2x00dev, 68, 0x0b);
3950
3951         if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C)) {
3952                 rt2800_bbp_write(rt2x00dev, 69, 0x16);
3953                 rt2800_bbp_write(rt2x00dev, 73, 0x12);
3954         } else if (rt2x00_rt(rt2x00dev, RT3290) ||
3955                    rt2x00_rt(rt2x00dev, RT3352) ||
3956                    rt2x00_rt(rt2x00dev, RT5390) ||
3957                    rt2x00_rt(rt2x00dev, RT5392)) {
3958                 rt2800_bbp_write(rt2x00dev, 69, 0x12);
3959                 rt2800_bbp_write(rt2x00dev, 73, 0x13);
3960                 rt2800_bbp_write(rt2x00dev, 75, 0x46);
3961                 rt2800_bbp_write(rt2x00dev, 76, 0x28);
3962
3963                 if (rt2x00_rt(rt2x00dev, RT3290))
3964                         rt2800_bbp_write(rt2x00dev, 77, 0x58);
3965                 else
3966                         rt2800_bbp_write(rt2x00dev, 77, 0x59);
3967         } else {
3968                 rt2800_bbp_write(rt2x00dev, 69, 0x12);
3969                 rt2800_bbp_write(rt2x00dev, 73, 0x10);
3970         }
3971
3972         rt2800_bbp_write(rt2x00dev, 70, 0x0a);
3973
3974         if (rt2x00_rt(rt2x00dev, RT3070) ||
3975             rt2x00_rt(rt2x00dev, RT3071) ||
3976             rt2x00_rt(rt2x00dev, RT3090) ||
3977             rt2x00_rt(rt2x00dev, RT3390) ||
3978             rt2x00_rt(rt2x00dev, RT3572) ||
3979             rt2x00_rt(rt2x00dev, RT5390) ||
3980             rt2x00_rt(rt2x00dev, RT5392)) {
3981                 rt2800_bbp_write(rt2x00dev, 79, 0x13);
3982                 rt2800_bbp_write(rt2x00dev, 80, 0x05);
3983                 rt2800_bbp_write(rt2x00dev, 81, 0x33);
3984         } else if (rt2800_is_305x_soc(rt2x00dev)) {
3985                 rt2800_bbp_write(rt2x00dev, 78, 0x0e);
3986                 rt2800_bbp_write(rt2x00dev, 80, 0x08);
3987         } else if (rt2x00_rt(rt2x00dev, RT3290)) {
3988                 rt2800_bbp_write(rt2x00dev, 74, 0x0b);
3989                 rt2800_bbp_write(rt2x00dev, 79, 0x18);
3990                 rt2800_bbp_write(rt2x00dev, 80, 0x09);
3991                 rt2800_bbp_write(rt2x00dev, 81, 0x33);
3992         } else if (rt2x00_rt(rt2x00dev, RT3352)) {
3993                 rt2800_bbp_write(rt2x00dev, 78, 0x0e);
3994                 rt2800_bbp_write(rt2x00dev, 80, 0x08);
3995                 rt2800_bbp_write(rt2x00dev, 81, 0x37);
3996         } else {
3997                 rt2800_bbp_write(rt2x00dev, 81, 0x37);
3998         }
3999
4000         rt2800_bbp_write(rt2x00dev, 82, 0x62);
4001         if (rt2x00_rt(rt2x00dev, RT3290) ||
4002             rt2x00_rt(rt2x00dev, RT5390) ||
4003             rt2x00_rt(rt2x00dev, RT5392))
4004                 rt2800_bbp_write(rt2x00dev, 83, 0x7a);
4005         else
4006                 rt2800_bbp_write(rt2x00dev, 83, 0x6a);
4007
4008         if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860D))
4009                 rt2800_bbp_write(rt2x00dev, 84, 0x19);
4010         else if (rt2x00_rt(rt2x00dev, RT3290) ||
4011                  rt2x00_rt(rt2x00dev, RT5390) ||
4012                  rt2x00_rt(rt2x00dev, RT5392))
4013                 rt2800_bbp_write(rt2x00dev, 84, 0x9a);
4014         else
4015                 rt2800_bbp_write(rt2x00dev, 84, 0x99);
4016
4017         if (rt2x00_rt(rt2x00dev, RT3290) ||
4018             rt2x00_rt(rt2x00dev, RT3352) ||
4019             rt2x00_rt(rt2x00dev, RT5390) ||
4020             rt2x00_rt(rt2x00dev, RT5392))
4021                 rt2800_bbp_write(rt2x00dev, 86, 0x38);
4022         else
4023                 rt2800_bbp_write(rt2x00dev, 86, 0x00);
4024
4025         if (rt2x00_rt(rt2x00dev, RT3352) ||
4026             rt2x00_rt(rt2x00dev, RT5392))
4027                 rt2800_bbp_write(rt2x00dev, 88, 0x90);
4028
4029         rt2800_bbp_write(rt2x00dev, 91, 0x04);
4030
4031         if (rt2x00_rt(rt2x00dev, RT3290) ||
4032             rt2x00_rt(rt2x00dev, RT3352) ||
4033             rt2x00_rt(rt2x00dev, RT5390) ||
4034             rt2x00_rt(rt2x00dev, RT5392))
4035                 rt2800_bbp_write(rt2x00dev, 92, 0x02);
4036         else
4037                 rt2800_bbp_write(rt2x00dev, 92, 0x00);
4038
4039         if (rt2x00_rt(rt2x00dev, RT5392)) {
4040                 rt2800_bbp_write(rt2x00dev, 95, 0x9a);
4041                 rt2800_bbp_write(rt2x00dev, 98, 0x12);
4042         }
4043
4044         if (rt2x00_rt_rev_gte(rt2x00dev, RT3070, REV_RT3070F) ||
4045             rt2x00_rt_rev_gte(rt2x00dev, RT3071, REV_RT3071E) ||
4046             rt2x00_rt_rev_gte(rt2x00dev, RT3090, REV_RT3090E) ||
4047             rt2x00_rt_rev_gte(rt2x00dev, RT3390, REV_RT3390E) ||
4048             rt2x00_rt(rt2x00dev, RT3290) ||
4049             rt2x00_rt(rt2x00dev, RT3352) ||
4050             rt2x00_rt(rt2x00dev, RT3572) ||
4051             rt2x00_rt(rt2x00dev, RT5390) ||
4052             rt2x00_rt(rt2x00dev, RT5392) ||
4053             rt2800_is_305x_soc(rt2x00dev))
4054                 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
4055         else
4056                 rt2800_bbp_write(rt2x00dev, 103, 0x00);
4057
4058         if (rt2x00_rt(rt2x00dev, RT3290) ||
4059             rt2x00_rt(rt2x00dev, RT3352) ||
4060             rt2x00_rt(rt2x00dev, RT5390) ||
4061             rt2x00_rt(rt2x00dev, RT5392))
4062                 rt2800_bbp_write(rt2x00dev, 104, 0x92);
4063
4064         if (rt2800_is_305x_soc(rt2x00dev))
4065                 rt2800_bbp_write(rt2x00dev, 105, 0x01);
4066         else if (rt2x00_rt(rt2x00dev, RT3290))
4067                 rt2800_bbp_write(rt2x00dev, 105, 0x1c);
4068         else if (rt2x00_rt(rt2x00dev, RT3352))
4069                 rt2800_bbp_write(rt2x00dev, 105, 0x34);
4070         else if (rt2x00_rt(rt2x00dev, RT5390) ||
4071                  rt2x00_rt(rt2x00dev, RT5392))
4072                 rt2800_bbp_write(rt2x00dev, 105, 0x3c);
4073         else
4074                 rt2800_bbp_write(rt2x00dev, 105, 0x05);
4075
4076         if (rt2x00_rt(rt2x00dev, RT3290) ||
4077             rt2x00_rt(rt2x00dev, RT5390))
4078                 rt2800_bbp_write(rt2x00dev, 106, 0x03);
4079         else if (rt2x00_rt(rt2x00dev, RT3352))
4080                 rt2800_bbp_write(rt2x00dev, 106, 0x05);
4081         else if (rt2x00_rt(rt2x00dev, RT5392))
4082                 rt2800_bbp_write(rt2x00dev, 106, 0x12);
4083         else
4084                 rt2800_bbp_write(rt2x00dev, 106, 0x35);
4085
4086         if (rt2x00_rt(rt2x00dev, RT3352))
4087                 rt2800_bbp_write(rt2x00dev, 120, 0x50);
4088
4089         if (rt2x00_rt(rt2x00dev, RT3290) ||
4090             rt2x00_rt(rt2x00dev, RT5390) ||
4091             rt2x00_rt(rt2x00dev, RT5392))
4092                 rt2800_bbp_write(rt2x00dev, 128, 0x12);
4093
4094         if (rt2x00_rt(rt2x00dev, RT5392)) {
4095                 rt2800_bbp_write(rt2x00dev, 134, 0xd0);
4096                 rt2800_bbp_write(rt2x00dev, 135, 0xf6);
4097         }
4098
4099         if (rt2x00_rt(rt2x00dev, RT3352))
4100                 rt2800_bbp_write(rt2x00dev, 137, 0x0f);
4101
4102         if (rt2x00_rt(rt2x00dev, RT3071) ||
4103             rt2x00_rt(rt2x00dev, RT3090) ||
4104             rt2x00_rt(rt2x00dev, RT3390) ||
4105             rt2x00_rt(rt2x00dev, RT3572) ||
4106             rt2x00_rt(rt2x00dev, RT5390) ||
4107             rt2x00_rt(rt2x00dev, RT5392)) {
4108                 rt2800_bbp_read(rt2x00dev, 138, &value);
4109
4110                 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom);
4111                 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) == 1)
4112                         value |= 0x20;
4113                 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) == 1)
4114                         value &= ~0x02;
4115
4116                 rt2800_bbp_write(rt2x00dev, 138, value);
4117         }
4118
4119         if (rt2x00_rt(rt2x00dev, RT3290)) {
4120                 rt2800_bbp_write(rt2x00dev, 67, 0x24);
4121                 rt2800_bbp_write(rt2x00dev, 143, 0x04);
4122                 rt2800_bbp_write(rt2x00dev, 142, 0x99);
4123                 rt2800_bbp_write(rt2x00dev, 150, 0x30);
4124                 rt2800_bbp_write(rt2x00dev, 151, 0x2e);
4125                 rt2800_bbp_write(rt2x00dev, 152, 0x20);
4126                 rt2800_bbp_write(rt2x00dev, 153, 0x34);
4127                 rt2800_bbp_write(rt2x00dev, 154, 0x40);
4128                 rt2800_bbp_write(rt2x00dev, 155, 0x3b);
4129                 rt2800_bbp_write(rt2x00dev, 253, 0x04);
4130
4131                 rt2800_bbp_read(rt2x00dev, 47, &value);
4132                 rt2x00_set_field8(&value, BBP47_TSSI_ADC6, 1);
4133                 rt2800_bbp_write(rt2x00dev, 47, value);
4134
4135                 /* Use 5-bit ADC for Acquisition and 8-bit ADC for data */
4136                 rt2800_bbp_read(rt2x00dev, 3, &value);
4137                 rt2x00_set_field8(&value, BBP3_ADC_MODE_SWITCH, 1);
4138                 rt2x00_set_field8(&value, BBP3_ADC_INIT_MODE, 1);
4139                 rt2800_bbp_write(rt2x00dev, 3, value);
4140         }
4141
4142         if (rt2x00_rt(rt2x00dev, RT3352)) {
4143                 rt2800_bbp_write(rt2x00dev, 163, 0xbd);
4144                 /* Set ITxBF timeout to 0x9c40=1000msec */
4145                 rt2800_bbp_write(rt2x00dev, 179, 0x02);
4146                 rt2800_bbp_write(rt2x00dev, 180, 0x00);
4147                 rt2800_bbp_write(rt2x00dev, 182, 0x40);
4148                 rt2800_bbp_write(rt2x00dev, 180, 0x01);
4149                 rt2800_bbp_write(rt2x00dev, 182, 0x9c);
4150                 rt2800_bbp_write(rt2x00dev, 179, 0x00);
4151                 /* Reprogram the inband interface to put right values in RXWI */
4152                 rt2800_bbp_write(rt2x00dev, 142, 0x04);
4153                 rt2800_bbp_write(rt2x00dev, 143, 0x3b);
4154                 rt2800_bbp_write(rt2x00dev, 142, 0x06);
4155                 rt2800_bbp_write(rt2x00dev, 143, 0xa0);
4156                 rt2800_bbp_write(rt2x00dev, 142, 0x07);
4157                 rt2800_bbp_write(rt2x00dev, 143, 0xa1);
4158                 rt2800_bbp_write(rt2x00dev, 142, 0x08);
4159                 rt2800_bbp_write(rt2x00dev, 143, 0xa2);
4160
4161                 rt2800_bbp_write(rt2x00dev, 148, 0xc8);
4162         }
4163
4164         if (rt2x00_rt(rt2x00dev, RT5390) ||
4165             rt2x00_rt(rt2x00dev, RT5392)) {
4166                 int ant, div_mode;
4167
4168                 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
4169                 div_mode = rt2x00_get_field16(eeprom,
4170                                               EEPROM_NIC_CONF1_ANT_DIVERSITY);
4171                 ant = (div_mode == 3) ? 1 : 0;
4172
4173                 /* check if this is a Bluetooth combo card */
4174                 if (test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags)) {
4175                         u32 reg;
4176
4177                         rt2800_register_read(rt2x00dev, GPIO_CTRL, &reg);
4178                         rt2x00_set_field32(&reg, GPIO_CTRL_DIR3, 0);
4179                         rt2x00_set_field32(&reg, GPIO_CTRL_DIR6, 0);
4180                         rt2x00_set_field32(&reg, GPIO_CTRL_VAL3, 0);
4181                         rt2x00_set_field32(&reg, GPIO_CTRL_VAL6, 0);
4182                         if (ant == 0)
4183                                 rt2x00_set_field32(&reg, GPIO_CTRL_VAL3, 1);
4184                         else if (ant == 1)
4185                                 rt2x00_set_field32(&reg, GPIO_CTRL_VAL6, 1);
4186                         rt2800_register_write(rt2x00dev, GPIO_CTRL, reg);
4187                 }
4188
4189                 /* This chip has hardware antenna diversity*/
4190                 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390R)) {
4191                         rt2800_bbp_write(rt2x00dev, 150, 0); /* Disable Antenna Software OFDM */
4192                         rt2800_bbp_write(rt2x00dev, 151, 0); /* Disable Antenna Software CCK */
4193                         rt2800_bbp_write(rt2x00dev, 154, 0); /* Clear previously selected antenna */
4194                 }
4195
4196                 rt2800_bbp_read(rt2x00dev, 152, &value);
4197                 if (ant == 0)
4198                         rt2x00_set_field8(&value, BBP152_RX_DEFAULT_ANT, 1);
4199                 else
4200                         rt2x00_set_field8(&value, BBP152_RX_DEFAULT_ANT, 0);
4201                 rt2800_bbp_write(rt2x00dev, 152, value);
4202
4203                 rt2800_init_freq_calibration(rt2x00dev);
4204         }
4205
4206         for (i = 0; i < EEPROM_BBP_SIZE; i++) {
4207                 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
4208
4209                 if (eeprom != 0xffff && eeprom != 0x0000) {
4210                         reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
4211                         value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
4212                         rt2800_bbp_write(rt2x00dev, reg_id, value);
4213                 }
4214         }
4215
4216         return 0;
4217 }
4218
4219 static u8 rt2800_init_rx_filter(struct rt2x00_dev *rt2x00dev,
4220                                 bool bw40, u8 rfcsr24, u8 filter_target)
4221 {
4222         unsigned int i;
4223         u8 bbp;
4224         u8 rfcsr;
4225         u8 passband;
4226         u8 stopband;
4227         u8 overtuned = 0;
4228
4229         rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
4230
4231         rt2800_bbp_read(rt2x00dev, 4, &bbp);
4232         rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * bw40);
4233         rt2800_bbp_write(rt2x00dev, 4, bbp);
4234
4235         rt2800_rfcsr_read(rt2x00dev, 31, &rfcsr);
4236         rt2x00_set_field8(&rfcsr, RFCSR31_RX_H20M, bw40);
4237         rt2800_rfcsr_write(rt2x00dev, 31, rfcsr);
4238
4239         rt2800_rfcsr_read(rt2x00dev, 22, &rfcsr);
4240         rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 1);
4241         rt2800_rfcsr_write(rt2x00dev, 22, rfcsr);
4242
4243         /*
4244          * Set power & frequency of passband test tone
4245          */
4246         rt2800_bbp_write(rt2x00dev, 24, 0);
4247
4248         for (i = 0; i < 100; i++) {
4249                 rt2800_bbp_write(rt2x00dev, 25, 0x90);
4250                 msleep(1);
4251
4252                 rt2800_bbp_read(rt2x00dev, 55, &passband);
4253                 if (passband)
4254                         break;
4255         }
4256
4257         /*
4258          * Set power & frequency of stopband test tone
4259          */
4260         rt2800_bbp_write(rt2x00dev, 24, 0x06);
4261
4262         for (i = 0; i < 100; i++) {
4263                 rt2800_bbp_write(rt2x00dev, 25, 0x90);
4264                 msleep(1);
4265
4266                 rt2800_bbp_read(rt2x00dev, 55, &stopband);
4267
4268                 if ((passband - stopband) <= filter_target) {
4269                         rfcsr24++;
4270                         overtuned += ((passband - stopband) == filter_target);
4271                 } else
4272                         break;
4273
4274                 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
4275         }
4276
4277         rfcsr24 -= !!overtuned;
4278
4279         rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
4280         return rfcsr24;
4281 }
4282
4283 static void rt2800_init_rfcsr_305x_soc(struct rt2x00_dev *rt2x00dev)
4284 {
4285         rt2800_rfcsr_write(rt2x00dev, 0, 0x50);
4286         rt2800_rfcsr_write(rt2x00dev, 1, 0x01);
4287         rt2800_rfcsr_write(rt2x00dev, 2, 0xf7);
4288         rt2800_rfcsr_write(rt2x00dev, 3, 0x75);
4289         rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
4290         rt2800_rfcsr_write(rt2x00dev, 5, 0x03);
4291         rt2800_rfcsr_write(rt2x00dev, 6, 0x02);
4292         rt2800_rfcsr_write(rt2x00dev, 7, 0x50);
4293         rt2800_rfcsr_write(rt2x00dev, 8, 0x39);
4294         rt2800_rfcsr_write(rt2x00dev, 9, 0x0f);
4295         rt2800_rfcsr_write(rt2x00dev, 10, 0x60);
4296         rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
4297         rt2800_rfcsr_write(rt2x00dev, 12, 0x75);
4298         rt2800_rfcsr_write(rt2x00dev, 13, 0x75);
4299         rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
4300         rt2800_rfcsr_write(rt2x00dev, 15, 0x58);
4301         rt2800_rfcsr_write(rt2x00dev, 16, 0xb3);
4302         rt2800_rfcsr_write(rt2x00dev, 17, 0x92);
4303         rt2800_rfcsr_write(rt2x00dev, 18, 0x2c);
4304         rt2800_rfcsr_write(rt2x00dev, 19, 0x02);
4305         rt2800_rfcsr_write(rt2x00dev, 20, 0xba);
4306         rt2800_rfcsr_write(rt2x00dev, 21, 0xdb);
4307         rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
4308         rt2800_rfcsr_write(rt2x00dev, 23, 0x31);
4309         rt2800_rfcsr_write(rt2x00dev, 24, 0x08);
4310         rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
4311         rt2800_rfcsr_write(rt2x00dev, 26, 0x25);
4312         rt2800_rfcsr_write(rt2x00dev, 27, 0x23);
4313         rt2800_rfcsr_write(rt2x00dev, 28, 0x13);
4314         rt2800_rfcsr_write(rt2x00dev, 29, 0x83);
4315         rt2800_rfcsr_write(rt2x00dev, 30, 0x00);
4316         rt2800_rfcsr_write(rt2x00dev, 31, 0x00);
4317 }
4318
4319 static void rt2800_init_rfcsr_30xx(struct rt2x00_dev *rt2x00dev)
4320 {
4321         rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
4322         rt2800_rfcsr_write(rt2x00dev, 5, 0x03);
4323         rt2800_rfcsr_write(rt2x00dev, 6, 0x02);
4324         rt2800_rfcsr_write(rt2x00dev, 7, 0x60);
4325         rt2800_rfcsr_write(rt2x00dev, 9, 0x0f);
4326         rt2800_rfcsr_write(rt2x00dev, 10, 0x41);
4327         rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
4328         rt2800_rfcsr_write(rt2x00dev, 12, 0x7b);
4329         rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
4330         rt2800_rfcsr_write(rt2x00dev, 15, 0x58);
4331         rt2800_rfcsr_write(rt2x00dev, 16, 0xb3);
4332         rt2800_rfcsr_write(rt2x00dev, 17, 0x92);
4333         rt2800_rfcsr_write(rt2x00dev, 18, 0x2c);
4334         rt2800_rfcsr_write(rt2x00dev, 19, 0x02);
4335         rt2800_rfcsr_write(rt2x00dev, 20, 0xba);
4336         rt2800_rfcsr_write(rt2x00dev, 21, 0xdb);
4337         rt2800_rfcsr_write(rt2x00dev, 24, 0x16);
4338         rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
4339         rt2800_rfcsr_write(rt2x00dev, 29, 0x1f);
4340 }
4341
4342 static void rt2800_init_rfcsr_3290(struct rt2x00_dev *rt2x00dev)
4343 {
4344         rt2800_rfcsr_write(rt2x00dev, 1, 0x0f);
4345         rt2800_rfcsr_write(rt2x00dev, 2, 0x80);
4346         rt2800_rfcsr_write(rt2x00dev, 3, 0x08);
4347         rt2800_rfcsr_write(rt2x00dev, 4, 0x00);
4348         rt2800_rfcsr_write(rt2x00dev, 6, 0xa0);
4349         rt2800_rfcsr_write(rt2x00dev, 8, 0xf3);
4350         rt2800_rfcsr_write(rt2x00dev, 9, 0x02);
4351         rt2800_rfcsr_write(rt2x00dev, 10, 0x53);
4352         rt2800_rfcsr_write(rt2x00dev, 11, 0x4a);
4353         rt2800_rfcsr_write(rt2x00dev, 12, 0x46);
4354         rt2800_rfcsr_write(rt2x00dev, 13, 0x9f);
4355         rt2800_rfcsr_write(rt2x00dev, 18, 0x02);
4356         rt2800_rfcsr_write(rt2x00dev, 22, 0x20);
4357         rt2800_rfcsr_write(rt2x00dev, 25, 0x83);
4358         rt2800_rfcsr_write(rt2x00dev, 26, 0x82);
4359         rt2800_rfcsr_write(rt2x00dev, 27, 0x09);
4360         rt2800_rfcsr_write(rt2x00dev, 29, 0x10);
4361         rt2800_rfcsr_write(rt2x00dev, 30, 0x10);
4362         rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
4363         rt2800_rfcsr_write(rt2x00dev, 32, 0x80);
4364         rt2800_rfcsr_write(rt2x00dev, 33, 0x00);
4365         rt2800_rfcsr_write(rt2x00dev, 34, 0x05);
4366         rt2800_rfcsr_write(rt2x00dev, 35, 0x12);
4367         rt2800_rfcsr_write(rt2x00dev, 36, 0x00);
4368         rt2800_rfcsr_write(rt2x00dev, 38, 0x85);
4369         rt2800_rfcsr_write(rt2x00dev, 39, 0x1b);
4370         rt2800_rfcsr_write(rt2x00dev, 40, 0x0b);
4371         rt2800_rfcsr_write(rt2x00dev, 41, 0xbb);
4372         rt2800_rfcsr_write(rt2x00dev, 42, 0xd5);
4373         rt2800_rfcsr_write(rt2x00dev, 43, 0x7b);
4374         rt2800_rfcsr_write(rt2x00dev, 44, 0x0e);
4375         rt2800_rfcsr_write(rt2x00dev, 45, 0xa2);
4376         rt2800_rfcsr_write(rt2x00dev, 46, 0x73);
4377         rt2800_rfcsr_write(rt2x00dev, 47, 0x00);
4378         rt2800_rfcsr_write(rt2x00dev, 48, 0x10);
4379         rt2800_rfcsr_write(rt2x00dev, 49, 0x98);
4380         rt2800_rfcsr_write(rt2x00dev, 52, 0x38);
4381         rt2800_rfcsr_write(rt2x00dev, 53, 0x00);
4382         rt2800_rfcsr_write(rt2x00dev, 54, 0x78);
4383         rt2800_rfcsr_write(rt2x00dev, 55, 0x43);
4384         rt2800_rfcsr_write(rt2x00dev, 56, 0x02);
4385         rt2800_rfcsr_write(rt2x00dev, 57, 0x80);
4386         rt2800_rfcsr_write(rt2x00dev, 58, 0x7f);
4387         rt2800_rfcsr_write(rt2x00dev, 59, 0x09);
4388         rt2800_rfcsr_write(rt2x00dev, 60, 0x45);
4389         rt2800_rfcsr_write(rt2x00dev, 61, 0xc1);
4390 }
4391
4392 static void rt2800_init_rfcsr_3352(struct rt2x00_dev *rt2x00dev)
4393 {
4394         rt2800_rfcsr_write(rt2x00dev, 0, 0xf0);
4395         rt2800_rfcsr_write(rt2x00dev, 1, 0x23);
4396         rt2800_rfcsr_write(rt2x00dev, 2, 0x50);
4397         rt2800_rfcsr_write(rt2x00dev, 3, 0x18);
4398         rt2800_rfcsr_write(rt2x00dev, 4, 0x00);
4399         rt2800_rfcsr_write(rt2x00dev, 5, 0x00);
4400         rt2800_rfcsr_write(rt2x00dev, 6, 0x33);
4401         rt2800_rfcsr_write(rt2x00dev, 7, 0x00);
4402         rt2800_rfcsr_write(rt2x00dev, 8, 0xf1);
4403         rt2800_rfcsr_write(rt2x00dev, 9, 0x02);
4404         rt2800_rfcsr_write(rt2x00dev, 10, 0xd2);
4405         rt2800_rfcsr_write(rt2x00dev, 11, 0x42);
4406         rt2800_rfcsr_write(rt2x00dev, 12, 0x1c);
4407         rt2800_rfcsr_write(rt2x00dev, 13, 0x00);
4408         rt2800_rfcsr_write(rt2x00dev, 14, 0x5a);
4409         rt2800_rfcsr_write(rt2x00dev, 15, 0x00);
4410         rt2800_rfcsr_write(rt2x00dev, 16, 0x01);
4411         rt2800_rfcsr_write(rt2x00dev, 18, 0x45);
4412         rt2800_rfcsr_write(rt2x00dev, 19, 0x02);
4413         rt2800_rfcsr_write(rt2x00dev, 20, 0x00);
4414         rt2800_rfcsr_write(rt2x00dev, 21, 0x00);
4415         rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
4416         rt2800_rfcsr_write(rt2x00dev, 23, 0x00);
4417         rt2800_rfcsr_write(rt2x00dev, 24, 0x00);
4418         rt2800_rfcsr_write(rt2x00dev, 25, 0x80);
4419         rt2800_rfcsr_write(rt2x00dev, 26, 0x00);
4420         rt2800_rfcsr_write(rt2x00dev, 27, 0x03);
4421         rt2800_rfcsr_write(rt2x00dev, 28, 0x03);
4422         rt2800_rfcsr_write(rt2x00dev, 29, 0x00);
4423         rt2800_rfcsr_write(rt2x00dev, 30, 0x10);
4424         rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
4425         rt2800_rfcsr_write(rt2x00dev, 32, 0x80);
4426         rt2800_rfcsr_write(rt2x00dev, 33, 0x00);
4427         rt2800_rfcsr_write(rt2x00dev, 34, 0x01);
4428         rt2800_rfcsr_write(rt2x00dev, 35, 0x03);
4429         rt2800_rfcsr_write(rt2x00dev, 36, 0xbd);
4430         rt2800_rfcsr_write(rt2x00dev, 37, 0x3c);
4431         rt2800_rfcsr_write(rt2x00dev, 38, 0x5f);
4432         rt2800_rfcsr_write(rt2x00dev, 39, 0xc5);
4433         rt2800_rfcsr_write(rt2x00dev, 40, 0x33);
4434         rt2800_rfcsr_write(rt2x00dev, 41, 0x5b);
4435         rt2800_rfcsr_write(rt2x00dev, 42, 0x5b);
4436         rt2800_rfcsr_write(rt2x00dev, 43, 0xdb);
4437         rt2800_rfcsr_write(rt2x00dev, 44, 0xdb);
4438         rt2800_rfcsr_write(rt2x00dev, 45, 0xdb);
4439         rt2800_rfcsr_write(rt2x00dev, 46, 0xdd);
4440         rt2800_rfcsr_write(rt2x00dev, 47, 0x0d);
4441         rt2800_rfcsr_write(rt2x00dev, 48, 0x14);
4442         rt2800_rfcsr_write(rt2x00dev, 49, 0x00);
4443         rt2800_rfcsr_write(rt2x00dev, 50, 0x2d);
4444         rt2800_rfcsr_write(rt2x00dev, 51, 0x7f);
4445         rt2800_rfcsr_write(rt2x00dev, 52, 0x00);
4446         rt2800_rfcsr_write(rt2x00dev, 53, 0x52);
4447         rt2800_rfcsr_write(rt2x00dev, 54, 0x1b);
4448         rt2800_rfcsr_write(rt2x00dev, 55, 0x7f);
4449         rt2800_rfcsr_write(rt2x00dev, 56, 0x00);
4450         rt2800_rfcsr_write(rt2x00dev, 57, 0x52);
4451         rt2800_rfcsr_write(rt2x00dev, 58, 0x1b);
4452         rt2800_rfcsr_write(rt2x00dev, 59, 0x00);
4453         rt2800_rfcsr_write(rt2x00dev, 60, 0x00);
4454         rt2800_rfcsr_write(rt2x00dev, 61, 0x00);
4455         rt2800_rfcsr_write(rt2x00dev, 62, 0x00);
4456         rt2800_rfcsr_write(rt2x00dev, 63, 0x00);
4457 }
4458
4459 static void rt2800_init_rfcsr_3390(struct rt2x00_dev *rt2x00dev)
4460 {
4461         rt2800_rfcsr_write(rt2x00dev, 0, 0xa0);
4462         rt2800_rfcsr_write(rt2x00dev, 1, 0xe1);
4463         rt2800_rfcsr_write(rt2x00dev, 2, 0xf1);
4464         rt2800_rfcsr_write(rt2x00dev, 3, 0x62);
4465         rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
4466         rt2800_rfcsr_write(rt2x00dev, 5, 0x8b);
4467         rt2800_rfcsr_write(rt2x00dev, 6, 0x42);
4468         rt2800_rfcsr_write(rt2x00dev, 7, 0x34);
4469         rt2800_rfcsr_write(rt2x00dev, 8, 0x00);
4470         rt2800_rfcsr_write(rt2x00dev, 9, 0xc0);
4471         rt2800_rfcsr_write(rt2x00dev, 10, 0x61);
4472         rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
4473         rt2800_rfcsr_write(rt2x00dev, 12, 0x3b);
4474         rt2800_rfcsr_write(rt2x00dev, 13, 0xe0);
4475         rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
4476         rt2800_rfcsr_write(rt2x00dev, 15, 0x53);
4477         rt2800_rfcsr_write(rt2x00dev, 16, 0xe0);
4478         rt2800_rfcsr_write(rt2x00dev, 17, 0x94);
4479         rt2800_rfcsr_write(rt2x00dev, 18, 0x5c);
4480         rt2800_rfcsr_write(rt2x00dev, 19, 0x4a);
4481         rt2800_rfcsr_write(rt2x00dev, 20, 0xb2);
4482         rt2800_rfcsr_write(rt2x00dev, 21, 0xf6);
4483         rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
4484         rt2800_rfcsr_write(rt2x00dev, 23, 0x14);
4485         rt2800_rfcsr_write(rt2x00dev, 24, 0x08);
4486         rt2800_rfcsr_write(rt2x00dev, 25, 0x3d);
4487         rt2800_rfcsr_write(rt2x00dev, 26, 0x85);
4488         rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
4489         rt2800_rfcsr_write(rt2x00dev, 28, 0x41);
4490         rt2800_rfcsr_write(rt2x00dev, 29, 0x8f);
4491         rt2800_rfcsr_write(rt2x00dev, 30, 0x20);
4492         rt2800_rfcsr_write(rt2x00dev, 31, 0x0f);
4493 }
4494
4495 static void rt2800_init_rfcsr_3572(struct rt2x00_dev *rt2x00dev)
4496 {
4497         rt2800_rfcsr_write(rt2x00dev, 0, 0x70);
4498         rt2800_rfcsr_write(rt2x00dev, 1, 0x81);
4499         rt2800_rfcsr_write(rt2x00dev, 2, 0xf1);
4500         rt2800_rfcsr_write(rt2x00dev, 3, 0x02);
4501         rt2800_rfcsr_write(rt2x00dev, 4, 0x4c);
4502         rt2800_rfcsr_write(rt2x00dev, 5, 0x05);
4503         rt2800_rfcsr_write(rt2x00dev, 6, 0x4a);
4504         rt2800_rfcsr_write(rt2x00dev, 7, 0xd8);
4505         rt2800_rfcsr_write(rt2x00dev, 9, 0xc3);
4506         rt2800_rfcsr_write(rt2x00dev, 10, 0xf1);
4507         rt2800_rfcsr_write(rt2x00dev, 11, 0xb9);
4508         rt2800_rfcsr_write(rt2x00dev, 12, 0x70);
4509         rt2800_rfcsr_write(rt2x00dev, 13, 0x65);
4510         rt2800_rfcsr_write(rt2x00dev, 14, 0xa0);
4511         rt2800_rfcsr_write(rt2x00dev, 15, 0x53);
4512         rt2800_rfcsr_write(rt2x00dev, 16, 0x4c);
4513         rt2800_rfcsr_write(rt2x00dev, 17, 0x23);
4514         rt2800_rfcsr_write(rt2x00dev, 18, 0xac);
4515         rt2800_rfcsr_write(rt2x00dev, 19, 0x93);
4516         rt2800_rfcsr_write(rt2x00dev, 20, 0xb3);
4517         rt2800_rfcsr_write(rt2x00dev, 21, 0xd0);
4518         rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
4519         rt2800_rfcsr_write(rt2x00dev, 23, 0x3c);
4520         rt2800_rfcsr_write(rt2x00dev, 24, 0x16);
4521         rt2800_rfcsr_write(rt2x00dev, 25, 0x15);
4522         rt2800_rfcsr_write(rt2x00dev, 26, 0x85);
4523         rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
4524         rt2800_rfcsr_write(rt2x00dev, 28, 0x00);
4525         rt2800_rfcsr_write(rt2x00dev, 29, 0x9b);
4526         rt2800_rfcsr_write(rt2x00dev, 30, 0x09);
4527         rt2800_rfcsr_write(rt2x00dev, 31, 0x10);
4528 }
4529
4530 static void rt2800_init_rfcsr_5390(struct rt2x00_dev *rt2x00dev)
4531 {
4532         rt2800_rfcsr_write(rt2x00dev, 1, 0x0f);
4533         rt2800_rfcsr_write(rt2x00dev, 2, 0x80);
4534         rt2800_rfcsr_write(rt2x00dev, 3, 0x88);
4535         rt2800_rfcsr_write(rt2x00dev, 5, 0x10);
4536         if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
4537                 rt2800_rfcsr_write(rt2x00dev, 6, 0xe0);
4538         else
4539                 rt2800_rfcsr_write(rt2x00dev, 6, 0xa0);
4540         rt2800_rfcsr_write(rt2x00dev, 7, 0x00);
4541         rt2800_rfcsr_write(rt2x00dev, 10, 0x53);
4542         rt2800_rfcsr_write(rt2x00dev, 11, 0x4a);
4543         rt2800_rfcsr_write(rt2x00dev, 12, 0xc6);
4544         rt2800_rfcsr_write(rt2x00dev, 13, 0x9f);
4545         rt2800_rfcsr_write(rt2x00dev, 14, 0x00);
4546         rt2800_rfcsr_write(rt2x00dev, 15, 0x00);
4547         rt2800_rfcsr_write(rt2x00dev, 16, 0x00);
4548         rt2800_rfcsr_write(rt2x00dev, 18, 0x03);
4549         rt2800_rfcsr_write(rt2x00dev, 19, 0x00);
4550
4551         rt2800_rfcsr_write(rt2x00dev, 20, 0x00);
4552         rt2800_rfcsr_write(rt2x00dev, 21, 0x00);
4553         rt2800_rfcsr_write(rt2x00dev, 22, 0x20);
4554         rt2800_rfcsr_write(rt2x00dev, 23, 0x00);
4555         rt2800_rfcsr_write(rt2x00dev, 24, 0x00);
4556         if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
4557                 rt2800_rfcsr_write(rt2x00dev, 25, 0x80);
4558         else
4559                 rt2800_rfcsr_write(rt2x00dev, 25, 0xc0);
4560         rt2800_rfcsr_write(rt2x00dev, 26, 0x00);
4561         rt2800_rfcsr_write(rt2x00dev, 27, 0x09);
4562         rt2800_rfcsr_write(rt2x00dev, 28, 0x00);
4563         rt2800_rfcsr_write(rt2x00dev, 29, 0x10);
4564
4565         rt2800_rfcsr_write(rt2x00dev, 30, 0x00);
4566         rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
4567         rt2800_rfcsr_write(rt2x00dev, 32, 0x80);
4568         rt2800_rfcsr_write(rt2x00dev, 33, 0x00);
4569         rt2800_rfcsr_write(rt2x00dev, 34, 0x07);
4570         rt2800_rfcsr_write(rt2x00dev, 35, 0x12);
4571         rt2800_rfcsr_write(rt2x00dev, 36, 0x00);
4572         rt2800_rfcsr_write(rt2x00dev, 37, 0x08);
4573         rt2800_rfcsr_write(rt2x00dev, 38, 0x85);
4574         rt2800_rfcsr_write(rt2x00dev, 39, 0x1b);
4575
4576         if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
4577                 rt2800_rfcsr_write(rt2x00dev, 40, 0x0b);
4578         else
4579                 rt2800_rfcsr_write(rt2x00dev, 40, 0x4b);
4580         rt2800_rfcsr_write(rt2x00dev, 41, 0xbb);
4581         rt2800_rfcsr_write(rt2x00dev, 42, 0xd2);
4582         rt2800_rfcsr_write(rt2x00dev, 43, 0x9a);
4583         rt2800_rfcsr_write(rt2x00dev, 44, 0x0e);
4584         rt2800_rfcsr_write(rt2x00dev, 45, 0xa2);
4585         if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
4586                 rt2800_rfcsr_write(rt2x00dev, 46, 0x73);
4587         else
4588                 rt2800_rfcsr_write(rt2x00dev, 46, 0x7b);
4589         rt2800_rfcsr_write(rt2x00dev, 47, 0x00);
4590         rt2800_rfcsr_write(rt2x00dev, 48, 0x10);
4591         rt2800_rfcsr_write(rt2x00dev, 49, 0x94);
4592
4593         rt2800_rfcsr_write(rt2x00dev, 52, 0x38);
4594         if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
4595                 rt2800_rfcsr_write(rt2x00dev, 53, 0x00);
4596         else
4597                 rt2800_rfcsr_write(rt2x00dev, 53, 0x84);
4598         rt2800_rfcsr_write(rt2x00dev, 54, 0x78);
4599         rt2800_rfcsr_write(rt2x00dev, 55, 0x44);
4600         rt2800_rfcsr_write(rt2x00dev, 56, 0x22);
4601         rt2800_rfcsr_write(rt2x00dev, 57, 0x80);
4602         rt2800_rfcsr_write(rt2x00dev, 58, 0x7f);
4603         rt2800_rfcsr_write(rt2x00dev, 59, 0x63);
4604
4605         rt2800_rfcsr_write(rt2x00dev, 60, 0x45);
4606         if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
4607                 rt2800_rfcsr_write(rt2x00dev, 61, 0xd1);
4608         else
4609                 rt2800_rfcsr_write(rt2x00dev, 61, 0xdd);
4610         rt2800_rfcsr_write(rt2x00dev, 62, 0x00);
4611         rt2800_rfcsr_write(rt2x00dev, 63, 0x00);
4612 }
4613
4614 static void rt2800_init_rfcsr_5392(struct rt2x00_dev *rt2x00dev)
4615 {
4616         rt2800_rfcsr_write(rt2x00dev, 1, 0x17);
4617         rt2800_rfcsr_write(rt2x00dev, 2, 0x80);
4618         rt2800_rfcsr_write(rt2x00dev, 3, 0x88);
4619         rt2800_rfcsr_write(rt2x00dev, 5, 0x10);
4620         rt2800_rfcsr_write(rt2x00dev, 6, 0xe0);
4621         rt2800_rfcsr_write(rt2x00dev, 7, 0x00);
4622         rt2800_rfcsr_write(rt2x00dev, 10, 0x53);
4623         rt2800_rfcsr_write(rt2x00dev, 11, 0x4a);
4624         rt2800_rfcsr_write(rt2x00dev, 12, 0x46);
4625         rt2800_rfcsr_write(rt2x00dev, 13, 0x9f);
4626         rt2800_rfcsr_write(rt2x00dev, 14, 0x00);
4627         rt2800_rfcsr_write(rt2x00dev, 15, 0x00);
4628         rt2800_rfcsr_write(rt2x00dev, 16, 0x00);
4629         rt2800_rfcsr_write(rt2x00dev, 18, 0x03);
4630         rt2800_rfcsr_write(rt2x00dev, 19, 0x4d);
4631         rt2800_rfcsr_write(rt2x00dev, 20, 0x00);
4632         rt2800_rfcsr_write(rt2x00dev, 21, 0x8d);
4633         rt2800_rfcsr_write(rt2x00dev, 22, 0x20);
4634         rt2800_rfcsr_write(rt2x00dev, 23, 0x0b);
4635         rt2800_rfcsr_write(rt2x00dev, 24, 0x44);
4636         rt2800_rfcsr_write(rt2x00dev, 25, 0x80);
4637         rt2800_rfcsr_write(rt2x00dev, 26, 0x82);
4638         rt2800_rfcsr_write(rt2x00dev, 27, 0x09);
4639         rt2800_rfcsr_write(rt2x00dev, 28, 0x00);
4640         rt2800_rfcsr_write(rt2x00dev, 29, 0x10);
4641         rt2800_rfcsr_write(rt2x00dev, 30, 0x10);
4642         rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
4643         rt2800_rfcsr_write(rt2x00dev, 32, 0x20);
4644         rt2800_rfcsr_write(rt2x00dev, 33, 0xC0);
4645         rt2800_rfcsr_write(rt2x00dev, 34, 0x07);
4646         rt2800_rfcsr_write(rt2x00dev, 35, 0x12);
4647         rt2800_rfcsr_write(rt2x00dev, 36, 0x00);
4648         rt2800_rfcsr_write(rt2x00dev, 37, 0x08);
4649         rt2800_rfcsr_write(rt2x00dev, 38, 0x89);
4650         rt2800_rfcsr_write(rt2x00dev, 39, 0x1b);
4651         rt2800_rfcsr_write(rt2x00dev, 40, 0x0f);
4652         rt2800_rfcsr_write(rt2x00dev, 41, 0xbb);
4653         rt2800_rfcsr_write(rt2x00dev, 42, 0xd5);
4654         rt2800_rfcsr_write(rt2x00dev, 43, 0x9b);
4655         rt2800_rfcsr_write(rt2x00dev, 44, 0x0e);
4656         rt2800_rfcsr_write(rt2x00dev, 45, 0xa2);
4657         rt2800_rfcsr_write(rt2x00dev, 46, 0x73);
4658         rt2800_rfcsr_write(rt2x00dev, 47, 0x0c);
4659         rt2800_rfcsr_write(rt2x00dev, 48, 0x10);
4660         rt2800_rfcsr_write(rt2x00dev, 49, 0x94);
4661         rt2800_rfcsr_write(rt2x00dev, 50, 0x94);
4662         rt2800_rfcsr_write(rt2x00dev, 51, 0x3a);
4663         rt2800_rfcsr_write(rt2x00dev, 52, 0x48);
4664         rt2800_rfcsr_write(rt2x00dev, 53, 0x44);
4665         rt2800_rfcsr_write(rt2x00dev, 54, 0x38);
4666         rt2800_rfcsr_write(rt2x00dev, 55, 0x43);
4667         rt2800_rfcsr_write(rt2x00dev, 56, 0xa1);
4668         rt2800_rfcsr_write(rt2x00dev, 57, 0x00);
4669         rt2800_rfcsr_write(rt2x00dev, 58, 0x39);
4670         rt2800_rfcsr_write(rt2x00dev, 59, 0x07);
4671         rt2800_rfcsr_write(rt2x00dev, 60, 0x45);
4672         rt2800_rfcsr_write(rt2x00dev, 61, 0x91);
4673         rt2800_rfcsr_write(rt2x00dev, 62, 0x39);
4674         rt2800_rfcsr_write(rt2x00dev, 63, 0x07);
4675 }
4676
4677 static void rt2800_init_rfcsr_5592(struct rt2x00_dev *rt2x00dev)
4678 {
4679         rt2800_rfcsr_write(rt2x00dev, 1, 0x3F);
4680         rt2800_rfcsr_write(rt2x00dev, 3, 0x08);
4681         rt2800_rfcsr_write(rt2x00dev, 3, 0x08);
4682         rt2800_rfcsr_write(rt2x00dev, 5, 0x10);
4683         rt2800_rfcsr_write(rt2x00dev, 6, 0xE4);
4684         rt2800_rfcsr_write(rt2x00dev, 7, 0x00);
4685         rt2800_rfcsr_write(rt2x00dev, 14, 0x00);
4686         rt2800_rfcsr_write(rt2x00dev, 15, 0x00);
4687         rt2800_rfcsr_write(rt2x00dev, 16, 0x00);
4688         rt2800_rfcsr_write(rt2x00dev, 18, 0x03);
4689         rt2800_rfcsr_write(rt2x00dev, 19, 0x4D);
4690         rt2800_rfcsr_write(rt2x00dev, 20, 0x10);
4691         rt2800_rfcsr_write(rt2x00dev, 21, 0x8D);
4692         rt2800_rfcsr_write(rt2x00dev, 26, 0x82);
4693         rt2800_rfcsr_write(rt2x00dev, 28, 0x00);
4694         rt2800_rfcsr_write(rt2x00dev, 29, 0x10);
4695         rt2800_rfcsr_write(rt2x00dev, 33, 0xC0);
4696         rt2800_rfcsr_write(rt2x00dev, 34, 0x07);
4697         rt2800_rfcsr_write(rt2x00dev, 35, 0x12);
4698         rt2800_rfcsr_write(rt2x00dev, 47, 0x0C);
4699         rt2800_rfcsr_write(rt2x00dev, 53, 0x22);
4700         rt2800_rfcsr_write(rt2x00dev, 63, 0x07);
4701
4702         rt2800_rfcsr_write(rt2x00dev, 2, 0x80);
4703         msleep(1);
4704
4705         rt2800_adjust_freq_offset(rt2x00dev);
4706 }
4707
4708 static int rt2800_init_rfcsr(struct rt2x00_dev *rt2x00dev)
4709 {
4710         struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
4711         u8 rfcsr;
4712         u8 bbp;
4713         u32 reg;
4714         u16 eeprom;
4715
4716         if (!rt2x00_rt(rt2x00dev, RT3070) &&
4717             !rt2x00_rt(rt2x00dev, RT3071) &&
4718             !rt2x00_rt(rt2x00dev, RT3090) &&
4719             !rt2x00_rt(rt2x00dev, RT3290) &&
4720             !rt2x00_rt(rt2x00dev, RT3352) &&
4721             !rt2x00_rt(rt2x00dev, RT3390) &&
4722             !rt2x00_rt(rt2x00dev, RT3572) &&
4723             !rt2x00_rt(rt2x00dev, RT5390) &&
4724             !rt2x00_rt(rt2x00dev, RT5392) &&
4725             !rt2x00_rt(rt2x00dev, RT5392) &&
4726             !rt2x00_rt(rt2x00dev, RT5592) &&
4727             !rt2800_is_305x_soc(rt2x00dev))
4728                 return 0;
4729
4730         /*
4731          * Init RF calibration.
4732          */
4733
4734         if (rt2x00_rt(rt2x00dev, RT3290) ||
4735             rt2x00_rt(rt2x00dev, RT5390) ||
4736             rt2x00_rt(rt2x00dev, RT5392)) {
4737                 rt2800_rfcsr_read(rt2x00dev, 2, &rfcsr);
4738                 rt2x00_set_field8(&rfcsr, RFCSR2_RESCAL_EN, 1);
4739                 rt2800_rfcsr_write(rt2x00dev, 2, rfcsr);
4740                 msleep(1);
4741                 rt2x00_set_field8(&rfcsr, RFCSR2_RESCAL_EN, 0);
4742                 rt2800_rfcsr_write(rt2x00dev, 2, rfcsr);
4743         } else {
4744                 rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
4745                 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 1);
4746                 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
4747                 msleep(1);
4748                 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 0);
4749                 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
4750         }
4751
4752         if (rt2800_is_305x_soc(rt2x00dev)) {
4753                 rt2800_init_rfcsr_305x_soc(rt2x00dev);
4754                 return 0;
4755         }
4756
4757         switch (rt2x00dev->chip.rt) {
4758         case RT3070:
4759         case RT3071:
4760         case RT3090:
4761                 rt2800_init_rfcsr_30xx(rt2x00dev);
4762                 break;
4763         case RT3290:
4764                 rt2800_init_rfcsr_3290(rt2x00dev);
4765                 break;
4766         case RT3352:
4767                 rt2800_init_rfcsr_3352(rt2x00dev);
4768                 break;
4769         case RT3390:
4770                 rt2800_init_rfcsr_3390(rt2x00dev);
4771                 break;
4772         case RT3572:
4773                 rt2800_init_rfcsr_3572(rt2x00dev);
4774                 break;
4775         case RT5390:
4776                 rt2800_init_rfcsr_5390(rt2x00dev);
4777                 break;
4778         case RT5392:
4779                 rt2800_init_rfcsr_5392(rt2x00dev);
4780                 break;
4781         case RT5592:
4782                 rt2800_init_rfcsr_5592(rt2x00dev);
4783                 break;
4784         }
4785
4786         if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F)) {
4787                 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
4788                 rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
4789                 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 3);
4790                 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
4791         } else if (rt2x00_rt(rt2x00dev, RT3071) ||
4792                    rt2x00_rt(rt2x00dev, RT3090)) {
4793                 rt2800_rfcsr_write(rt2x00dev, 31, 0x14);
4794
4795                 rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
4796                 rt2x00_set_field8(&rfcsr, RFCSR6_R2, 1);
4797                 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
4798
4799                 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
4800                 rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
4801                 if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
4802                     rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E)) {
4803                         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
4804                         if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_DAC_TEST))
4805                                 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 3);
4806                         else
4807                                 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 0);
4808                 }
4809                 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
4810
4811                 rt2800_register_read(rt2x00dev, GPIO_SWITCH, &reg);
4812                 rt2x00_set_field32(&reg, GPIO_SWITCH_5, 0);
4813                 rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg);
4814         } else if (rt2x00_rt(rt2x00dev, RT3390)) {
4815                 rt2800_register_read(rt2x00dev, GPIO_SWITCH, &reg);
4816                 rt2x00_set_field32(&reg, GPIO_SWITCH_5, 0);
4817                 rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg);
4818         } else if (rt2x00_rt(rt2x00dev, RT3572)) {
4819                 rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
4820                 rt2x00_set_field8(&rfcsr, RFCSR6_R2, 1);
4821                 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
4822
4823                 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
4824                 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 3);
4825                 rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
4826                 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
4827                 msleep(1);
4828                 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
4829                 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 0);
4830                 rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
4831                 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
4832         }
4833
4834         /*
4835          * Set RX Filter calibration for 20MHz and 40MHz
4836          */
4837         if (rt2x00_rt(rt2x00dev, RT3070)) {
4838                 drv_data->calibration_bw20 =
4839                         rt2800_init_rx_filter(rt2x00dev, false, 0x07, 0x16);
4840                 drv_data->calibration_bw40 =
4841                         rt2800_init_rx_filter(rt2x00dev, true, 0x27, 0x19);
4842         } else if (rt2x00_rt(rt2x00dev, RT3071) ||
4843                    rt2x00_rt(rt2x00dev, RT3090) ||
4844                    rt2x00_rt(rt2x00dev, RT3352) ||
4845                    rt2x00_rt(rt2x00dev, RT3390) ||
4846                    rt2x00_rt(rt2x00dev, RT3572)) {
4847                 drv_data->calibration_bw20 =
4848                         rt2800_init_rx_filter(rt2x00dev, false, 0x07, 0x13);
4849                 drv_data->calibration_bw40 =
4850                         rt2800_init_rx_filter(rt2x00dev, true, 0x27, 0x15);
4851         }
4852
4853         /*
4854          * Save BBP 25 & 26 values for later use in channel switching
4855          */
4856         rt2800_bbp_read(rt2x00dev, 25, &drv_data->bbp25);
4857         rt2800_bbp_read(rt2x00dev, 26, &drv_data->bbp26);
4858
4859         if (!rt2x00_rt(rt2x00dev, RT5390) &&
4860             !rt2x00_rt(rt2x00dev, RT5392)) {
4861                 /*
4862                  * Set back to initial state
4863                  */
4864                 rt2800_bbp_write(rt2x00dev, 24, 0);
4865
4866                 rt2800_rfcsr_read(rt2x00dev, 22, &rfcsr);
4867                 rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 0);
4868                 rt2800_rfcsr_write(rt2x00dev, 22, rfcsr);
4869
4870                 /*
4871                  * Set BBP back to BW20
4872                  */
4873                 rt2800_bbp_read(rt2x00dev, 4, &bbp);
4874                 rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 0);
4875                 rt2800_bbp_write(rt2x00dev, 4, bbp);
4876         }
4877
4878         if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F) ||
4879             rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
4880             rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) ||
4881             rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E) ||
4882             rt2x00_rt_rev_lt(rt2x00dev, RT5592, REV_RT5592C))
4883                 rt2800_rfcsr_write(rt2x00dev, 27, 0x03);
4884
4885         rt2800_register_read(rt2x00dev, OPT_14_CSR, &reg);
4886         rt2x00_set_field32(&reg, OPT_14_CSR_BIT0, 1);
4887         rt2800_register_write(rt2x00dev, OPT_14_CSR, reg);
4888
4889         if (!rt2x00_rt(rt2x00dev, RT5390) &&
4890             !rt2x00_rt(rt2x00dev, RT5392)) {
4891                 rt2800_rfcsr_read(rt2x00dev, 17, &rfcsr);
4892                 rt2x00_set_field8(&rfcsr, RFCSR17_TX_LO1_EN, 0);
4893                 if (rt2x00_rt(rt2x00dev, RT3070) ||
4894                     rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
4895                     rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) ||
4896                     rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E)) {
4897                         if (!test_bit(CAPABILITY_EXTERNAL_LNA_BG,
4898                                       &rt2x00dev->cap_flags))
4899                                 rt2x00_set_field8(&rfcsr, RFCSR17_R, 1);
4900                 }
4901                 rt2x00_set_field8(&rfcsr, RFCSR17_TXMIXER_GAIN,
4902                                   drv_data->txmixer_gain_24g);
4903                 rt2800_rfcsr_write(rt2x00dev, 17, rfcsr);
4904         }
4905
4906         if (rt2x00_rt(rt2x00dev, RT3090) ||
4907             rt2x00_rt(rt2x00dev, RT5592)) {
4908                 rt2800_bbp_read(rt2x00dev, 138, &bbp);
4909
4910                 /*  Turn off unused DAC1 and ADC1 to reduce power consumption */
4911                 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom);
4912                 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) == 1)
4913                         rt2x00_set_field8(&bbp, BBP138_RX_ADC1, 0);
4914                 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) == 1)
4915                         rt2x00_set_field8(&bbp, BBP138_TX_DAC1, 1);
4916
4917                 rt2800_bbp_write(rt2x00dev, 138, bbp);
4918         }
4919
4920         if (rt2x00_rt(rt2x00dev, RT3071) ||
4921             rt2x00_rt(rt2x00dev, RT3090) ||
4922             rt2x00_rt(rt2x00dev, RT3390)) {
4923                 rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
4924                 rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
4925                 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0);
4926                 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0);
4927                 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
4928                 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
4929                 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
4930
4931                 rt2800_rfcsr_read(rt2x00dev, 15, &rfcsr);
4932                 rt2x00_set_field8(&rfcsr, RFCSR15_TX_LO2_EN, 0);
4933                 rt2800_rfcsr_write(rt2x00dev, 15, rfcsr);
4934
4935                 rt2800_rfcsr_read(rt2x00dev, 20, &rfcsr);
4936                 rt2x00_set_field8(&rfcsr, RFCSR20_RX_LO1_EN, 0);
4937                 rt2800_rfcsr_write(rt2x00dev, 20, rfcsr);
4938
4939                 rt2800_rfcsr_read(rt2x00dev, 21, &rfcsr);
4940                 rt2x00_set_field8(&rfcsr, RFCSR21_RX_LO2_EN, 0);
4941                 rt2800_rfcsr_write(rt2x00dev, 21, rfcsr);
4942         }
4943
4944         if (rt2x00_rt(rt2x00dev, RT3070)) {
4945                 rt2800_rfcsr_read(rt2x00dev, 27, &rfcsr);
4946                 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F))
4947                         rt2x00_set_field8(&rfcsr, RFCSR27_R1, 3);
4948                 else
4949                         rt2x00_set_field8(&rfcsr, RFCSR27_R1, 0);
4950                 rt2x00_set_field8(&rfcsr, RFCSR27_R2, 0);
4951                 rt2x00_set_field8(&rfcsr, RFCSR27_R3, 0);
4952                 rt2x00_set_field8(&rfcsr, RFCSR27_R4, 0);
4953                 rt2800_rfcsr_write(rt2x00dev, 27, rfcsr);
4954         }
4955
4956         if (rt2x00_rt(rt2x00dev, RT3290)) {
4957                 rt2800_rfcsr_read(rt2x00dev, 29, &rfcsr);
4958                 rt2x00_set_field8(&rfcsr, RFCSR29_RSSI_GAIN, 3);
4959                 rt2800_rfcsr_write(rt2x00dev, 29, rfcsr);
4960         }
4961
4962         if (rt2x00_rt(rt2x00dev, RT5390) ||
4963             rt2x00_rt(rt2x00dev, RT5392) ||
4964             rt2x00_rt(rt2x00dev, RT5592)) {
4965                 rt2800_rfcsr_read(rt2x00dev, 38, &rfcsr);
4966                 rt2x00_set_field8(&rfcsr, RFCSR38_RX_LO1_EN, 0);
4967                 rt2800_rfcsr_write(rt2x00dev, 38, rfcsr);
4968
4969                 rt2800_rfcsr_read(rt2x00dev, 39, &rfcsr);
4970                 rt2x00_set_field8(&rfcsr, RFCSR39_RX_LO2_EN, 0);
4971                 rt2800_rfcsr_write(rt2x00dev, 39, rfcsr);
4972
4973                 rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
4974                 rt2x00_set_field8(&rfcsr, RFCSR30_RX_VCM, 2);
4975                 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
4976         }
4977
4978         return 0;
4979 }
4980
4981 int rt2800_enable_radio(struct rt2x00_dev *rt2x00dev)
4982 {
4983         u32 reg;
4984         u16 word;
4985
4986         /*
4987          * Initialize all registers.
4988          */
4989         if (unlikely(rt2800_wait_wpdma_ready(rt2x00dev) ||
4990                      rt2800_init_registers(rt2x00dev) ||
4991                      rt2800_init_bbp(rt2x00dev) ||
4992                      rt2800_init_rfcsr(rt2x00dev)))
4993                 return -EIO;
4994
4995         /*
4996          * Send signal to firmware during boot time.
4997          */
4998         rt2800_mcu_request(rt2x00dev, MCU_BOOT_SIGNAL, 0, 0, 0);
4999
5000         if (rt2x00_is_usb(rt2x00dev) &&
5001             (rt2x00_rt(rt2x00dev, RT3070) ||
5002              rt2x00_rt(rt2x00dev, RT3071) ||
5003              rt2x00_rt(rt2x00dev, RT3572))) {
5004                 udelay(200);
5005                 rt2800_mcu_request(rt2x00dev, MCU_CURRENT, 0, 0, 0);
5006                 udelay(10);
5007         }
5008
5009         /*
5010          * Enable RX.
5011          */
5012         rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
5013         rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 1);
5014         rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 0);
5015         rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
5016
5017         udelay(50);
5018
5019         rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
5020         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 1);
5021         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 1);
5022         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE, 2);
5023         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
5024         rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
5025
5026         rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
5027         rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 1);
5028         rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 1);
5029         rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
5030
5031         /*
5032          * Initialize LED control
5033          */
5034         rt2x00_eeprom_read(rt2x00dev, EEPROM_LED_AG_CONF, &word);
5035         rt2800_mcu_request(rt2x00dev, MCU_LED_AG_CONF, 0xff,
5036                            word & 0xff, (word >> 8) & 0xff);
5037
5038         rt2x00_eeprom_read(rt2x00dev, EEPROM_LED_ACT_CONF, &word);
5039         rt2800_mcu_request(rt2x00dev, MCU_LED_ACT_CONF, 0xff,
5040                            word & 0xff, (word >> 8) & 0xff);
5041
5042         rt2x00_eeprom_read(rt2x00dev, EEPROM_LED_POLARITY, &word);
5043         rt2800_mcu_request(rt2x00dev, MCU_LED_LED_POLARITY, 0xff,
5044                            word & 0xff, (word >> 8) & 0xff);
5045
5046         return 0;
5047 }
5048 EXPORT_SYMBOL_GPL(rt2800_enable_radio);
5049
5050 void rt2800_disable_radio(struct rt2x00_dev *rt2x00dev)
5051 {
5052         u32 reg;
5053
5054         rt2800_disable_wpdma(rt2x00dev);
5055
5056         /* Wait for DMA, ignore error */
5057         rt2800_wait_wpdma_ready(rt2x00dev);
5058
5059         rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
5060         rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 0);
5061         rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 0);
5062         rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
5063 }
5064 EXPORT_SYMBOL_GPL(rt2800_disable_radio);
5065
5066 int rt2800_efuse_detect(struct rt2x00_dev *rt2x00dev)
5067 {
5068         u32 reg;
5069         u16 efuse_ctrl_reg;
5070
5071         if (rt2x00_rt(rt2x00dev, RT3290))
5072                 efuse_ctrl_reg = EFUSE_CTRL_3290;
5073         else
5074                 efuse_ctrl_reg = EFUSE_CTRL;
5075
5076         rt2800_register_read(rt2x00dev, efuse_ctrl_reg, &reg);
5077         return rt2x00_get_field32(reg, EFUSE_CTRL_PRESENT);
5078 }
5079 EXPORT_SYMBOL_GPL(rt2800_efuse_detect);
5080
5081 static void rt2800_efuse_read(struct rt2x00_dev *rt2x00dev, unsigned int i)
5082 {
5083         u32 reg;
5084         u16 efuse_ctrl_reg;
5085         u16 efuse_data0_reg;
5086         u16 efuse_data1_reg;
5087         u16 efuse_data2_reg;
5088         u16 efuse_data3_reg;
5089
5090         if (rt2x00_rt(rt2x00dev, RT3290)) {
5091                 efuse_ctrl_reg = EFUSE_CTRL_3290;
5092                 efuse_data0_reg = EFUSE_DATA0_3290;
5093                 efuse_data1_reg = EFUSE_DATA1_3290;
5094                 efuse_data2_reg = EFUSE_DATA2_3290;
5095                 efuse_data3_reg = EFUSE_DATA3_3290;
5096         } else {
5097                 efuse_ctrl_reg = EFUSE_CTRL;
5098                 efuse_data0_reg = EFUSE_DATA0;
5099                 efuse_data1_reg = EFUSE_DATA1;
5100                 efuse_data2_reg = EFUSE_DATA2;
5101                 efuse_data3_reg = EFUSE_DATA3;
5102         }
5103         mutex_lock(&rt2x00dev->csr_mutex);
5104
5105         rt2800_register_read_lock(rt2x00dev, efuse_ctrl_reg, &reg);
5106         rt2x00_set_field32(&reg, EFUSE_CTRL_ADDRESS_IN, i);
5107         rt2x00_set_field32(&reg, EFUSE_CTRL_MODE, 0);
5108         rt2x00_set_field32(&reg, EFUSE_CTRL_KICK, 1);
5109         rt2800_register_write_lock(rt2x00dev, efuse_ctrl_reg, reg);
5110
5111         /* Wait until the EEPROM has been loaded */
5112         rt2800_regbusy_read(rt2x00dev, efuse_ctrl_reg, EFUSE_CTRL_KICK, &reg);
5113         /* Apparently the data is read from end to start */
5114         rt2800_register_read_lock(rt2x00dev, efuse_data3_reg, &reg);
5115         /* The returned value is in CPU order, but eeprom is le */
5116         *(u32 *)&rt2x00dev->eeprom[i] = cpu_to_le32(reg);
5117         rt2800_register_read_lock(rt2x00dev, efuse_data2_reg, &reg);
5118         *(u32 *)&rt2x00dev->eeprom[i + 2] = cpu_to_le32(reg);
5119         rt2800_register_read_lock(rt2x00dev, efuse_data1_reg, &reg);
5120         *(u32 *)&rt2x00dev->eeprom[i + 4] = cpu_to_le32(reg);
5121         rt2800_register_read_lock(rt2x00dev, efuse_data0_reg, &reg);
5122         *(u32 *)&rt2x00dev->eeprom[i + 6] = cpu_to_le32(reg);
5123
5124         mutex_unlock(&rt2x00dev->csr_mutex);
5125 }
5126
5127 int rt2800_read_eeprom_efuse(struct rt2x00_dev *rt2x00dev)
5128 {
5129         unsigned int i;
5130
5131         for (i = 0; i < EEPROM_SIZE / sizeof(u16); i += 8)
5132                 rt2800_efuse_read(rt2x00dev, i);
5133
5134         return 0;
5135 }
5136 EXPORT_SYMBOL_GPL(rt2800_read_eeprom_efuse);
5137
5138 static int rt2800_validate_eeprom(struct rt2x00_dev *rt2x00dev)
5139 {
5140         struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
5141         u16 word;
5142         u8 *mac;
5143         u8 default_lna_gain;
5144         int retval;
5145
5146         /*
5147          * Read the EEPROM.
5148          */
5149         retval = rt2800_read_eeprom(rt2x00dev);
5150         if (retval)
5151                 return retval;
5152
5153         /*
5154          * Start validation of the data that has been read.
5155          */
5156         mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
5157         if (!is_valid_ether_addr(mac)) {
5158                 eth_random_addr(mac);
5159                 EEPROM(rt2x00dev, "MAC: %pM\n", mac);
5160         }
5161
5162         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &word);
5163         if (word == 0xffff) {
5164                 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_RXPATH, 2);
5165                 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_TXPATH, 1);
5166                 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_RF_TYPE, RF2820);
5167                 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC_CONF0, word);
5168                 EEPROM(rt2x00dev, "Antenna: 0x%04x\n", word);
5169         } else if (rt2x00_rt(rt2x00dev, RT2860) ||
5170                    rt2x00_rt(rt2x00dev, RT2872)) {
5171                 /*
5172                  * There is a max of 2 RX streams for RT28x0 series
5173                  */
5174                 if (rt2x00_get_field16(word, EEPROM_NIC_CONF0_RXPATH) > 2)
5175                         rt2x00_set_field16(&word, EEPROM_NIC_CONF0_RXPATH, 2);
5176                 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC_CONF0, word);
5177         }
5178
5179         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &word);
5180         if (word == 0xffff) {
5181                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_HW_RADIO, 0);
5182                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_EXTERNAL_TX_ALC, 0);
5183                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_EXTERNAL_LNA_2G, 0);
5184                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_EXTERNAL_LNA_5G, 0);
5185                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_CARDBUS_ACCEL, 0);
5186                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_SB_2G, 0);
5187                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_SB_5G, 0);
5188                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_WPS_PBC, 0);
5189                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_2G, 0);
5190                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_5G, 0);
5191                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BROADBAND_EXT_LNA, 0);
5192                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_ANT_DIVERSITY, 0);
5193                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_INTERNAL_TX_ALC, 0);
5194                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BT_COEXIST, 0);
5195                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_DAC_TEST, 0);
5196                 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC_CONF1, word);
5197                 EEPROM(rt2x00dev, "NIC: 0x%04x\n", word);
5198         }
5199
5200         rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &word);
5201         if ((word & 0x00ff) == 0x00ff) {
5202                 rt2x00_set_field16(&word, EEPROM_FREQ_OFFSET, 0);
5203                 rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
5204                 EEPROM(rt2x00dev, "Freq: 0x%04x\n", word);
5205         }
5206         if ((word & 0xff00) == 0xff00) {
5207                 rt2x00_set_field16(&word, EEPROM_FREQ_LED_MODE,
5208                                    LED_MODE_TXRX_ACTIVITY);
5209                 rt2x00_set_field16(&word, EEPROM_FREQ_LED_POLARITY, 0);
5210                 rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
5211                 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED_AG_CONF, 0x5555);
5212                 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED_ACT_CONF, 0x2221);
5213                 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED_POLARITY, 0xa9f8);
5214                 EEPROM(rt2x00dev, "Led Mode: 0x%04x\n", word);
5215         }
5216
5217         /*
5218          * During the LNA validation we are going to use
5219          * lna0 as correct value. Note that EEPROM_LNA
5220          * is never validated.
5221          */
5222         rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &word);
5223         default_lna_gain = rt2x00_get_field16(word, EEPROM_LNA_A0);
5224
5225         rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG, &word);
5226         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET0)) > 10)
5227                 rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET0, 0);
5228         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET1)) > 10)
5229                 rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET1, 0);
5230         rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_BG, word);
5231
5232         rt2x00_eeprom_read(rt2x00dev, EEPROM_TXMIXER_GAIN_BG, &word);
5233         if ((word & 0x00ff) != 0x00ff) {
5234                 drv_data->txmixer_gain_24g =
5235                         rt2x00_get_field16(word, EEPROM_TXMIXER_GAIN_BG_VAL);
5236         } else {
5237                 drv_data->txmixer_gain_24g = 0;
5238         }
5239
5240         rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &word);
5241         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG2_OFFSET2)) > 10)
5242                 rt2x00_set_field16(&word, EEPROM_RSSI_BG2_OFFSET2, 0);
5243         if (rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0x00 ||
5244             rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0xff)
5245                 rt2x00_set_field16(&word, EEPROM_RSSI_BG2_LNA_A1,
5246                                    default_lna_gain);
5247         rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_BG2, word);
5248
5249         rt2x00_eeprom_read(rt2x00dev, EEPROM_TXMIXER_GAIN_A, &word);
5250         if ((word & 0x00ff) != 0x00ff) {
5251                 drv_data->txmixer_gain_5g =
5252                         rt2x00_get_field16(word, EEPROM_TXMIXER_GAIN_A_VAL);
5253         } else {
5254                 drv_data->txmixer_gain_5g = 0;
5255         }
5256
5257         rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A, &word);
5258         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET0)) > 10)
5259                 rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET0, 0);
5260         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET1)) > 10)
5261                 rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET1, 0);
5262         rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_A, word);
5263
5264         rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &word);
5265         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A2_OFFSET2)) > 10)
5266                 rt2x00_set_field16(&word, EEPROM_RSSI_A2_OFFSET2, 0);
5267         if (rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0x00 ||
5268             rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0xff)
5269                 rt2x00_set_field16(&word, EEPROM_RSSI_A2_LNA_A2,
5270                                    default_lna_gain);
5271         rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_A2, word);
5272
5273         return 0;
5274 }
5275
5276 static int rt2800_init_eeprom(struct rt2x00_dev *rt2x00dev)
5277 {
5278         u32 reg;
5279         u16 value;
5280         u16 eeprom;
5281
5282         /*
5283          * Read EEPROM word for configuration.
5284          */
5285         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom);
5286
5287         /*
5288          * Identify RF chipset by EEPROM value
5289          * RT28xx/RT30xx: defined in "EEPROM_NIC_CONF0_RF_TYPE" field
5290          * RT53xx: defined in "EEPROM_CHIP_ID" field
5291          */
5292         if (rt2x00_rt(rt2x00dev, RT3290))
5293                 rt2800_register_read(rt2x00dev, MAC_CSR0_3290, &reg);
5294         else
5295                 rt2800_register_read(rt2x00dev, MAC_CSR0, &reg);
5296
5297         if (rt2x00_get_field32(reg, MAC_CSR0_CHIPSET) == RT3290 ||
5298             rt2x00_get_field32(reg, MAC_CSR0_CHIPSET) == RT5390 ||
5299             rt2x00_get_field32(reg, MAC_CSR0_CHIPSET) == RT5392)
5300                 rt2x00_eeprom_read(rt2x00dev, EEPROM_CHIP_ID, &value);
5301         else
5302                 value = rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RF_TYPE);
5303
5304         rt2x00_set_chip(rt2x00dev, rt2x00_get_field32(reg, MAC_CSR0_CHIPSET),
5305                         value, rt2x00_get_field32(reg, MAC_CSR0_REVISION));
5306
5307         switch (rt2x00dev->chip.rt) {
5308         case RT2860:
5309         case RT2872:
5310         case RT2883:
5311         case RT3070:
5312         case RT3071:
5313         case RT3090:
5314         case RT3290:
5315         case RT3352:
5316         case RT3390:
5317         case RT3572:
5318         case RT5390:
5319         case RT5392:
5320         case RT5592:
5321                 break;
5322         default:
5323                 ERROR(rt2x00dev, "Invalid RT chipset 0x%04x detected.\n", rt2x00dev->chip.rt);
5324                 return -ENODEV;
5325         }
5326
5327         switch (rt2x00dev->chip.rf) {
5328         case RF2820:
5329         case RF2850:
5330         case RF2720:
5331         case RF2750:
5332         case RF3020:
5333         case RF2020:
5334         case RF3021:
5335         case RF3022:
5336         case RF3052:
5337         case RF3290:
5338         case RF3320:
5339         case RF3322:
5340         case RF5360:
5341         case RF5370:
5342         case RF5372:
5343         case RF5390:
5344         case RF5392:
5345         case RF5592:
5346                 break;
5347         default:
5348                 ERROR(rt2x00dev, "Invalid RF chipset 0x%04x detected.\n",
5349                       rt2x00dev->chip.rf);
5350                 return -ENODEV;
5351         }
5352
5353         /*
5354          * Identify default antenna configuration.
5355          */
5356         rt2x00dev->default_ant.tx_chain_num =
5357             rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH);
5358         rt2x00dev->default_ant.rx_chain_num =
5359             rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH);
5360
5361         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
5362
5363         if (rt2x00_rt(rt2x00dev, RT3070) ||
5364             rt2x00_rt(rt2x00dev, RT3090) ||
5365             rt2x00_rt(rt2x00dev, RT3352) ||
5366             rt2x00_rt(rt2x00dev, RT3390)) {
5367                 value = rt2x00_get_field16(eeprom,
5368                                 EEPROM_NIC_CONF1_ANT_DIVERSITY);
5369                 switch (value) {
5370                 case 0:
5371                 case 1:
5372                 case 2:
5373                         rt2x00dev->default_ant.tx = ANTENNA_A;
5374                         rt2x00dev->default_ant.rx = ANTENNA_A;
5375                         break;
5376                 case 3:
5377                         rt2x00dev->default_ant.tx = ANTENNA_A;
5378                         rt2x00dev->default_ant.rx = ANTENNA_B;
5379                         break;
5380                 }
5381         } else {
5382                 rt2x00dev->default_ant.tx = ANTENNA_A;
5383                 rt2x00dev->default_ant.rx = ANTENNA_A;
5384         }
5385
5386         if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390R)) {
5387                 rt2x00dev->default_ant.tx = ANTENNA_HW_DIVERSITY; /* Unused */
5388                 rt2x00dev->default_ant.rx = ANTENNA_HW_DIVERSITY; /* Unused */
5389         }
5390
5391         /*
5392          * Determine external LNA informations.
5393          */
5394         if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_EXTERNAL_LNA_5G))
5395                 __set_bit(CAPABILITY_EXTERNAL_LNA_A, &rt2x00dev->cap_flags);
5396         if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_EXTERNAL_LNA_2G))
5397                 __set_bit(CAPABILITY_EXTERNAL_LNA_BG, &rt2x00dev->cap_flags);
5398
5399         /*
5400          * Detect if this device has an hardware controlled radio.
5401          */
5402         if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_HW_RADIO))
5403                 __set_bit(CAPABILITY_HW_BUTTON, &rt2x00dev->cap_flags);
5404
5405         /*
5406          * Detect if this device has Bluetooth co-existence.
5407          */
5408         if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_BT_COEXIST))
5409                 __set_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags);
5410
5411         /*
5412          * Read frequency offset and RF programming sequence.
5413          */
5414         rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom);
5415         rt2x00dev->freq_offset = rt2x00_get_field16(eeprom, EEPROM_FREQ_OFFSET);
5416
5417         /*
5418          * Store led settings, for correct led behaviour.
5419          */
5420 #ifdef CONFIG_RT2X00_LIB_LEDS
5421         rt2800_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO);
5422         rt2800_init_led(rt2x00dev, &rt2x00dev->led_assoc, LED_TYPE_ASSOC);
5423         rt2800_init_led(rt2x00dev, &rt2x00dev->led_qual, LED_TYPE_QUALITY);
5424
5425         rt2x00dev->led_mcu_reg = eeprom;
5426 #endif /* CONFIG_RT2X00_LIB_LEDS */
5427
5428         /*
5429          * Check if support EIRP tx power limit feature.
5430          */
5431         rt2x00_eeprom_read(rt2x00dev, EEPROM_EIRP_MAX_TX_POWER, &eeprom);
5432
5433         if (rt2x00_get_field16(eeprom, EEPROM_EIRP_MAX_TX_POWER_2GHZ) <
5434                                         EIRP_MAX_TX_POWER_LIMIT)
5435                 __set_bit(CAPABILITY_POWER_LIMIT, &rt2x00dev->cap_flags);
5436
5437         return 0;
5438 }
5439
5440 /*
5441  * RF value list for rt28xx
5442  * Supports: 2.4 GHz (all) & 5.2 GHz (RF2850 & RF2750)
5443  */
5444 static const struct rf_channel rf_vals[] = {
5445         { 1,  0x18402ecc, 0x184c0786, 0x1816b455, 0x1800510b },
5446         { 2,  0x18402ecc, 0x184c0786, 0x18168a55, 0x1800519f },
5447         { 3,  0x18402ecc, 0x184c078a, 0x18168a55, 0x1800518b },
5448         { 4,  0x18402ecc, 0x184c078a, 0x18168a55, 0x1800519f },
5449         { 5,  0x18402ecc, 0x184c078e, 0x18168a55, 0x1800518b },
5450         { 6,  0x18402ecc, 0x184c078e, 0x18168a55, 0x1800519f },
5451         { 7,  0x18402ecc, 0x184c0792, 0x18168a55, 0x1800518b },
5452         { 8,  0x18402ecc, 0x184c0792, 0x18168a55, 0x1800519f },
5453         { 9,  0x18402ecc, 0x184c0796, 0x18168a55, 0x1800518b },
5454         { 10, 0x18402ecc, 0x184c0796, 0x18168a55, 0x1800519f },
5455         { 11, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800518b },
5456         { 12, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800519f },
5457         { 13, 0x18402ecc, 0x184c079e, 0x18168a55, 0x1800518b },
5458         { 14, 0x18402ecc, 0x184c07a2, 0x18168a55, 0x18005193 },
5459
5460         /* 802.11 UNI / HyperLan 2 */
5461         { 36, 0x18402ecc, 0x184c099a, 0x18158a55, 0x180ed1a3 },
5462         { 38, 0x18402ecc, 0x184c099e, 0x18158a55, 0x180ed193 },
5463         { 40, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed183 },
5464         { 44, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed1a3 },
5465         { 46, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed18b },
5466         { 48, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed19b },
5467         { 52, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed193 },
5468         { 54, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed1a3 },
5469         { 56, 0x18402ec8, 0x184c068e, 0x18158a55, 0x180ed18b },
5470         { 60, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed183 },
5471         { 62, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed193 },
5472         { 64, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed1a3 },
5473
5474         /* 802.11 HyperLan 2 */
5475         { 100, 0x18402ec8, 0x184c06b2, 0x18178a55, 0x180ed783 },
5476         { 102, 0x18402ec8, 0x184c06b2, 0x18578a55, 0x180ed793 },
5477         { 104, 0x18402ec8, 0x185c06b2, 0x18578a55, 0x180ed1a3 },
5478         { 108, 0x18402ecc, 0x185c0a32, 0x18578a55, 0x180ed193 },
5479         { 110, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed183 },
5480         { 112, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed19b },
5481         { 116, 0x18402ecc, 0x184c0a3a, 0x18178a55, 0x180ed1a3 },
5482         { 118, 0x18402ecc, 0x184c0a3e, 0x18178a55, 0x180ed193 },
5483         { 120, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed183 },
5484         { 124, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed193 },
5485         { 126, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed15b },
5486         { 128, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed1a3 },
5487         { 132, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed18b },
5488         { 134, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed193 },
5489         { 136, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed19b },
5490         { 140, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed183 },
5491
5492         /* 802.11 UNII */
5493         { 149, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed1a7 },
5494         { 151, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed187 },
5495         { 153, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed18f },
5496         { 157, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed19f },
5497         { 159, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed1a7 },
5498         { 161, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed187 },
5499         { 165, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed197 },
5500         { 167, 0x18402ec4, 0x184c03d2, 0x18179855, 0x1815531f },
5501         { 169, 0x18402ec4, 0x184c03d2, 0x18179855, 0x18155327 },
5502         { 171, 0x18402ec4, 0x184c03d6, 0x18179855, 0x18155307 },
5503         { 173, 0x18402ec4, 0x184c03d6, 0x18179855, 0x1815530f },
5504
5505         /* 802.11 Japan */
5506         { 184, 0x15002ccc, 0x1500491e, 0x1509be55, 0x150c0a0b },
5507         { 188, 0x15002ccc, 0x15004922, 0x1509be55, 0x150c0a13 },
5508         { 192, 0x15002ccc, 0x15004926, 0x1509be55, 0x150c0a1b },
5509         { 196, 0x15002ccc, 0x1500492a, 0x1509be55, 0x150c0a23 },
5510         { 208, 0x15002ccc, 0x1500493a, 0x1509be55, 0x150c0a13 },
5511         { 212, 0x15002ccc, 0x1500493e, 0x1509be55, 0x150c0a1b },
5512         { 216, 0x15002ccc, 0x15004982, 0x1509be55, 0x150c0a23 },
5513 };
5514
5515 /*
5516  * RF value list for rt3xxx
5517  * Supports: 2.4 GHz (all) & 5.2 GHz (RF3052)
5518  */
5519 static const struct rf_channel rf_vals_3x[] = {
5520         {1,  241, 2, 2 },
5521         {2,  241, 2, 7 },
5522         {3,  242, 2, 2 },
5523         {4,  242, 2, 7 },
5524         {5,  243, 2, 2 },
5525         {6,  243, 2, 7 },
5526         {7,  244, 2, 2 },
5527         {8,  244, 2, 7 },
5528         {9,  245, 2, 2 },
5529         {10, 245, 2, 7 },
5530         {11, 246, 2, 2 },
5531         {12, 246, 2, 7 },
5532         {13, 247, 2, 2 },
5533         {14, 248, 2, 4 },
5534
5535         /* 802.11 UNI / HyperLan 2 */
5536         {36, 0x56, 0, 4},
5537         {38, 0x56, 0, 6},
5538         {40, 0x56, 0, 8},
5539         {44, 0x57, 0, 0},
5540         {46, 0x57, 0, 2},
5541         {48, 0x57, 0, 4},
5542         {52, 0x57, 0, 8},
5543         {54, 0x57, 0, 10},
5544         {56, 0x58, 0, 0},
5545         {60, 0x58, 0, 4},
5546         {62, 0x58, 0, 6},
5547         {64, 0x58, 0, 8},
5548
5549         /* 802.11 HyperLan 2 */
5550         {100, 0x5b, 0, 8},
5551         {102, 0x5b, 0, 10},
5552         {104, 0x5c, 0, 0},
5553         {108, 0x5c, 0, 4},
5554         {110, 0x5c, 0, 6},
5555         {112, 0x5c, 0, 8},
5556         {116, 0x5d, 0, 0},
5557         {118, 0x5d, 0, 2},
5558         {120, 0x5d, 0, 4},
5559         {124, 0x5d, 0, 8},
5560         {126, 0x5d, 0, 10},
5561         {128, 0x5e, 0, 0},
5562         {132, 0x5e, 0, 4},
5563         {134, 0x5e, 0, 6},
5564         {136, 0x5e, 0, 8},
5565         {140, 0x5f, 0, 0},
5566
5567         /* 802.11 UNII */
5568         {149, 0x5f, 0, 9},
5569         {151, 0x5f, 0, 11},
5570         {153, 0x60, 0, 1},
5571         {157, 0x60, 0, 5},
5572         {159, 0x60, 0, 7},
5573         {161, 0x60, 0, 9},
5574         {165, 0x61, 0, 1},
5575         {167, 0x61, 0, 3},
5576         {169, 0x61, 0, 5},
5577         {171, 0x61, 0, 7},
5578         {173, 0x61, 0, 9},
5579 };
5580
5581 static const struct rf_channel rf_vals_5592_xtal20[] = {
5582         /* Channel, N, K, mod, R */
5583         {1, 482, 4, 10, 3},
5584         {2, 483, 4, 10, 3},
5585         {3, 484, 4, 10, 3},
5586         {4, 485, 4, 10, 3},
5587         {5, 486, 4, 10, 3},
5588         {6, 487, 4, 10, 3},
5589         {7, 488, 4, 10, 3},
5590         {8, 489, 4, 10, 3},
5591         {9, 490, 4, 10, 3},
5592         {10, 491, 4, 10, 3},
5593         {11, 492, 4, 10, 3},
5594         {12, 493, 4, 10, 3},
5595         {13, 494, 4, 10, 3},
5596         {14, 496, 8, 10, 3},
5597         {36, 172, 8, 12, 1},
5598         {38, 173, 0, 12, 1},
5599         {40, 173, 4, 12, 1},
5600         {42, 173, 8, 12, 1},
5601         {44, 174, 0, 12, 1},
5602         {46, 174, 4, 12, 1},
5603         {48, 174, 8, 12, 1},
5604         {50, 175, 0, 12, 1},
5605         {52, 175, 4, 12, 1},
5606         {54, 175, 8, 12, 1},
5607         {56, 176, 0, 12, 1},
5608         {58, 176, 4, 12, 1},
5609         {60, 176, 8, 12, 1},
5610         {62, 177, 0, 12, 1},
5611         {64, 177, 4, 12, 1},
5612         {100, 183, 4, 12, 1},
5613         {102, 183, 8, 12, 1},
5614         {104, 184, 0, 12, 1},
5615         {106, 184, 4, 12, 1},
5616         {108, 184, 8, 12, 1},
5617         {110, 185, 0, 12, 1},
5618         {112, 185, 4, 12, 1},
5619         {114, 185, 8, 12, 1},
5620         {116, 186, 0, 12, 1},
5621         {118, 186, 4, 12, 1},
5622         {120, 186, 8, 12, 1},
5623         {122, 187, 0, 12, 1},
5624         {124, 187, 4, 12, 1},
5625         {126, 187, 8, 12, 1},
5626         {128, 188, 0, 12, 1},
5627         {130, 188, 4, 12, 1},
5628         {132, 188, 8, 12, 1},
5629         {134, 189, 0, 12, 1},
5630         {136, 189, 4, 12, 1},
5631         {138, 189, 8, 12, 1},
5632         {140, 190, 0, 12, 1},
5633         {149, 191, 6, 12, 1},
5634         {151, 191, 10, 12, 1},
5635         {153, 192, 2, 12, 1},
5636         {155, 192, 6, 12, 1},
5637         {157, 192, 10, 12, 1},
5638         {159, 193, 2, 12, 1},
5639         {161, 193, 6, 12, 1},
5640         {165, 194, 2, 12, 1},
5641         {184, 164, 0, 12, 1},
5642         {188, 164, 4, 12, 1},
5643         {192, 165, 8, 12, 1},
5644         {196, 166, 0, 12, 1},
5645 };
5646
5647 static const struct rf_channel rf_vals_5592_xtal40[] = {
5648         /* Channel, N, K, mod, R */
5649         {1, 241, 2, 10, 3},
5650         {2, 241, 7, 10, 3},
5651         {3, 242, 2, 10, 3},
5652         {4, 242, 7, 10, 3},
5653         {5, 243, 2, 10, 3},
5654         {6, 243, 7, 10, 3},
5655         {7, 244, 2, 10, 3},
5656         {8, 244, 7, 10, 3},
5657         {9, 245, 2, 10, 3},
5658         {10, 245, 7, 10, 3},
5659         {11, 246, 2, 10, 3},
5660         {12, 246, 7, 10, 3},
5661         {13, 247, 2, 10, 3},
5662         {14, 248, 4, 10, 3},
5663         {36, 86, 4, 12, 1},
5664         {38, 86, 6, 12, 1},
5665         {40, 86, 8, 12, 1},
5666         {42, 86, 10, 12, 1},
5667         {44, 87, 0, 12, 1},
5668         {46, 87, 2, 12, 1},
5669         {48, 87, 4, 12, 1},
5670         {50, 87, 6, 12, 1},
5671         {52, 87, 8, 12, 1},
5672         {54, 87, 10, 12, 1},
5673         {56, 88, 0, 12, 1},
5674         {58, 88, 2, 12, 1},
5675         {60, 88, 4, 12, 1},
5676         {62, 88, 6, 12, 1},
5677         {64, 88, 8, 12, 1},
5678         {100, 91, 8, 12, 1},
5679         {102, 91, 10, 12, 1},
5680         {104, 92, 0, 12, 1},
5681         {106, 92, 2, 12, 1},
5682         {108, 92, 4, 12, 1},
5683         {110, 92, 6, 12, 1},
5684         {112, 92, 8, 12, 1},
5685         {114, 92, 10, 12, 1},
5686         {116, 93, 0, 12, 1},
5687         {118, 93, 2, 12, 1},
5688         {120, 93, 4, 12, 1},
5689         {122, 93, 6, 12, 1},
5690         {124, 93, 8, 12, 1},
5691         {126, 93, 10, 12, 1},
5692         {128, 94, 0, 12, 1},
5693         {130, 94, 2, 12, 1},
5694         {132, 94, 4, 12, 1},
5695         {134, 94, 6, 12, 1},
5696         {136, 94, 8, 12, 1},
5697         {138, 94, 10, 12, 1},
5698         {140, 95, 0, 12, 1},
5699         {149, 95, 9, 12, 1},
5700         {151, 95, 11, 12, 1},
5701         {153, 96, 1, 12, 1},
5702         {155, 96, 3, 12, 1},
5703         {157, 96, 5, 12, 1},
5704         {159, 96, 7, 12, 1},
5705         {161, 96, 9, 12, 1},
5706         {165, 97, 1, 12, 1},
5707         {184, 82, 0, 12, 1},
5708         {188, 82, 4, 12, 1},
5709         {192, 82, 8, 12, 1},
5710         {196, 83, 0, 12, 1},
5711 };
5712
5713 static int rt2800_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
5714 {
5715         struct hw_mode_spec *spec = &rt2x00dev->spec;
5716         struct channel_info *info;
5717         char *default_power1;
5718         char *default_power2;
5719         unsigned int i;
5720         u16 eeprom;
5721         u32 reg;
5722
5723         /*
5724          * Disable powersaving as default on PCI devices.
5725          */
5726         if (rt2x00_is_pci(rt2x00dev) || rt2x00_is_soc(rt2x00dev))
5727                 rt2x00dev->hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
5728
5729         /*
5730          * Initialize all hw fields.
5731          */
5732         rt2x00dev->hw->flags =
5733             IEEE80211_HW_SIGNAL_DBM |
5734             IEEE80211_HW_SUPPORTS_PS |
5735             IEEE80211_HW_PS_NULLFUNC_STACK |
5736             IEEE80211_HW_AMPDU_AGGREGATION |
5737             IEEE80211_HW_REPORTS_TX_ACK_STATUS;
5738
5739         /*
5740          * Don't set IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING for USB devices
5741          * unless we are capable of sending the buffered frames out after the
5742          * DTIM transmission using rt2x00lib_beacondone. This will send out
5743          * multicast and broadcast traffic immediately instead of buffering it
5744          * infinitly and thus dropping it after some time.
5745          */
5746         if (!rt2x00_is_usb(rt2x00dev))
5747                 rt2x00dev->hw->flags |=
5748                         IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING;
5749
5750         SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev);
5751         SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
5752                                 rt2x00_eeprom_addr(rt2x00dev,
5753                                                    EEPROM_MAC_ADDR_0));
5754
5755         /*
5756          * As rt2800 has a global fallback table we cannot specify
5757          * more then one tx rate per frame but since the hw will
5758          * try several rates (based on the fallback table) we should
5759          * initialize max_report_rates to the maximum number of rates
5760          * we are going to try. Otherwise mac80211 will truncate our
5761          * reported tx rates and the rc algortihm will end up with
5762          * incorrect data.
5763          */
5764         rt2x00dev->hw->max_rates = 1;
5765         rt2x00dev->hw->max_report_rates = 7;
5766         rt2x00dev->hw->max_rate_tries = 1;
5767
5768         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom);
5769
5770         /*
5771          * Initialize hw_mode information.
5772          */
5773         spec->supported_bands = SUPPORT_BAND_2GHZ;
5774         spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM;
5775
5776         if (rt2x00_rf(rt2x00dev, RF2820) ||
5777             rt2x00_rf(rt2x00dev, RF2720)) {
5778                 spec->num_channels = 14;
5779                 spec->channels = rf_vals;
5780         } else if (rt2x00_rf(rt2x00dev, RF2850) ||
5781                    rt2x00_rf(rt2x00dev, RF2750)) {
5782                 spec->supported_bands |= SUPPORT_BAND_5GHZ;
5783                 spec->num_channels = ARRAY_SIZE(rf_vals);
5784                 spec->channels = rf_vals;
5785         } else if (rt2x00_rf(rt2x00dev, RF3020) ||
5786                    rt2x00_rf(rt2x00dev, RF2020) ||
5787                    rt2x00_rf(rt2x00dev, RF3021) ||
5788                    rt2x00_rf(rt2x00dev, RF3022) ||
5789                    rt2x00_rf(rt2x00dev, RF3290) ||
5790                    rt2x00_rf(rt2x00dev, RF3320) ||
5791                    rt2x00_rf(rt2x00dev, RF3322) ||
5792                    rt2x00_rf(rt2x00dev, RF5360) ||
5793                    rt2x00_rf(rt2x00dev, RF5370) ||
5794                    rt2x00_rf(rt2x00dev, RF5372) ||
5795                    rt2x00_rf(rt2x00dev, RF5390) ||
5796                    rt2x00_rf(rt2x00dev, RF5392)) {
5797                 spec->num_channels = 14;
5798                 spec->channels = rf_vals_3x;
5799         } else if (rt2x00_rf(rt2x00dev, RF3052)) {
5800                 spec->supported_bands |= SUPPORT_BAND_5GHZ;
5801                 spec->num_channels = ARRAY_SIZE(rf_vals_3x);
5802                 spec->channels = rf_vals_3x;
5803         } else if (rt2x00_rf(rt2x00dev, RF5592)) {
5804                 spec->supported_bands |= SUPPORT_BAND_5GHZ;
5805
5806                 rt2800_register_read(rt2x00dev, MAC_DEBUG_INDEX, &reg);
5807                 if (rt2x00_get_field32(reg, MAC_DEBUG_INDEX_XTAL)) {
5808                         spec->num_channels = ARRAY_SIZE(rf_vals_5592_xtal40);
5809                         spec->channels = rf_vals_5592_xtal40;
5810                 } else {
5811                         spec->num_channels = ARRAY_SIZE(rf_vals_5592_xtal20);
5812                         spec->channels = rf_vals_5592_xtal20;
5813                 }
5814         }
5815
5816         if (WARN_ON_ONCE(!spec->channels))
5817                 return -ENODEV;
5818
5819         /*
5820          * Initialize HT information.
5821          */
5822         if (!rt2x00_rf(rt2x00dev, RF2020))
5823                 spec->ht.ht_supported = true;
5824         else
5825                 spec->ht.ht_supported = false;
5826
5827         spec->ht.cap =
5828             IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
5829             IEEE80211_HT_CAP_GRN_FLD |
5830             IEEE80211_HT_CAP_SGI_20 |
5831             IEEE80211_HT_CAP_SGI_40;
5832
5833         if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) >= 2)
5834                 spec->ht.cap |= IEEE80211_HT_CAP_TX_STBC;
5835
5836         spec->ht.cap |=
5837             rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) <<
5838                 IEEE80211_HT_CAP_RX_STBC_SHIFT;
5839
5840         spec->ht.ampdu_factor = 3;
5841         spec->ht.ampdu_density = 4;
5842         spec->ht.mcs.tx_params =
5843             IEEE80211_HT_MCS_TX_DEFINED |
5844             IEEE80211_HT_MCS_TX_RX_DIFF |
5845             ((rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) - 1) <<
5846                 IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT);
5847
5848         switch (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH)) {
5849         case 3:
5850                 spec->ht.mcs.rx_mask[2] = 0xff;
5851         case 2:
5852                 spec->ht.mcs.rx_mask[1] = 0xff;
5853         case 1:
5854                 spec->ht.mcs.rx_mask[0] = 0xff;
5855                 spec->ht.mcs.rx_mask[4] = 0x1; /* MCS32 */
5856                 break;
5857         }
5858
5859         /*
5860          * Create channel information array
5861          */
5862         info = kcalloc(spec->num_channels, sizeof(*info), GFP_KERNEL);
5863         if (!info)
5864                 return -ENOMEM;
5865
5866         spec->channels_info = info;
5867
5868         default_power1 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG1);
5869         default_power2 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG2);
5870
5871         for (i = 0; i < 14; i++) {
5872                 info[i].default_power1 = default_power1[i];
5873                 info[i].default_power2 = default_power2[i];
5874         }
5875
5876         if (spec->num_channels > 14) {
5877                 default_power1 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A1);
5878                 default_power2 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A2);
5879
5880                 for (i = 14; i < spec->num_channels; i++) {
5881                         info[i].default_power1 = default_power1[i];
5882                         info[i].default_power2 = default_power2[i];
5883                 }
5884         }
5885
5886         switch (rt2x00dev->chip.rf) {
5887         case RF2020:
5888         case RF3020:
5889         case RF3021:
5890         case RF3022:
5891         case RF3320:
5892         case RF3052:
5893         case RF3290:
5894         case RF5360:
5895         case RF5370:
5896         case RF5372:
5897         case RF5390:
5898         case RF5392:
5899                 __set_bit(CAPABILITY_VCO_RECALIBRATION, &rt2x00dev->cap_flags);
5900                 break;
5901         }
5902
5903         return 0;
5904 }
5905
5906 int rt2800_probe_hw(struct rt2x00_dev *rt2x00dev)
5907 {
5908         int retval;
5909         u32 reg;
5910
5911         /*
5912          * Allocate eeprom data.
5913          */
5914         retval = rt2800_validate_eeprom(rt2x00dev);
5915         if (retval)
5916                 return retval;
5917
5918         retval = rt2800_init_eeprom(rt2x00dev);
5919         if (retval)
5920                 return retval;
5921
5922         /*
5923          * Enable rfkill polling by setting GPIO direction of the
5924          * rfkill switch GPIO pin correctly.
5925          */
5926         rt2800_register_read(rt2x00dev, GPIO_CTRL, &reg);
5927         rt2x00_set_field32(&reg, GPIO_CTRL_DIR2, 1);
5928         rt2800_register_write(rt2x00dev, GPIO_CTRL, reg);
5929
5930         /*
5931          * Initialize hw specifications.
5932          */
5933         retval = rt2800_probe_hw_mode(rt2x00dev);
5934         if (retval)
5935                 return retval;
5936
5937         /*
5938          * Set device capabilities.
5939          */
5940         __set_bit(CAPABILITY_CONTROL_FILTERS, &rt2x00dev->cap_flags);
5941         __set_bit(CAPABILITY_CONTROL_FILTER_PSPOLL, &rt2x00dev->cap_flags);
5942         if (!rt2x00_is_usb(rt2x00dev))
5943                 __set_bit(CAPABILITY_PRE_TBTT_INTERRUPT, &rt2x00dev->cap_flags);
5944
5945         /*
5946          * Set device requirements.
5947          */
5948         if (!rt2x00_is_soc(rt2x00dev))
5949                 __set_bit(REQUIRE_FIRMWARE, &rt2x00dev->cap_flags);
5950         __set_bit(REQUIRE_L2PAD, &rt2x00dev->cap_flags);
5951         __set_bit(REQUIRE_TXSTATUS_FIFO, &rt2x00dev->cap_flags);
5952         if (!rt2800_hwcrypt_disabled(rt2x00dev))
5953                 __set_bit(CAPABILITY_HW_CRYPTO, &rt2x00dev->cap_flags);
5954         __set_bit(CAPABILITY_LINK_TUNING, &rt2x00dev->cap_flags);
5955         __set_bit(REQUIRE_HT_TX_DESC, &rt2x00dev->cap_flags);
5956         if (rt2x00_is_usb(rt2x00dev))
5957                 __set_bit(REQUIRE_PS_AUTOWAKE, &rt2x00dev->cap_flags);
5958         else {
5959                 __set_bit(REQUIRE_DMA, &rt2x00dev->cap_flags);
5960                 __set_bit(REQUIRE_TASKLET_CONTEXT, &rt2x00dev->cap_flags);
5961         }
5962
5963         /*
5964          * Set the rssi offset.
5965          */
5966         rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
5967
5968         return 0;
5969 }
5970 EXPORT_SYMBOL_GPL(rt2800_probe_hw);
5971
5972 /*
5973  * IEEE80211 stack callback functions.
5974  */
5975 void rt2800_get_tkip_seq(struct ieee80211_hw *hw, u8 hw_key_idx, u32 *iv32,
5976                          u16 *iv16)
5977 {
5978         struct rt2x00_dev *rt2x00dev = hw->priv;
5979         struct mac_iveiv_entry iveiv_entry;
5980         u32 offset;
5981
5982         offset = MAC_IVEIV_ENTRY(hw_key_idx);
5983         rt2800_register_multiread(rt2x00dev, offset,
5984                                       &iveiv_entry, sizeof(iveiv_entry));
5985
5986         memcpy(iv16, &iveiv_entry.iv[0], sizeof(*iv16));
5987         memcpy(iv32, &iveiv_entry.iv[4], sizeof(*iv32));
5988 }
5989 EXPORT_SYMBOL_GPL(rt2800_get_tkip_seq);
5990
5991 int rt2800_set_rts_threshold(struct ieee80211_hw *hw, u32 value)
5992 {
5993         struct rt2x00_dev *rt2x00dev = hw->priv;
5994         u32 reg;
5995         bool enabled = (value < IEEE80211_MAX_RTS_THRESHOLD);
5996
5997         rt2800_register_read(rt2x00dev, TX_RTS_CFG, &reg);
5998         rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_THRES, value);
5999         rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg);
6000
6001         rt2800_register_read(rt2x00dev, CCK_PROT_CFG, &reg);
6002         rt2x00_set_field32(&reg, CCK_PROT_CFG_RTS_TH_EN, enabled);
6003         rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg);
6004
6005         rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
6006         rt2x00_set_field32(&reg, OFDM_PROT_CFG_RTS_TH_EN, enabled);
6007         rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
6008
6009         rt2800_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
6010         rt2x00_set_field32(&reg, MM20_PROT_CFG_RTS_TH_EN, enabled);
6011         rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
6012
6013         rt2800_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
6014         rt2x00_set_field32(&reg, MM40_PROT_CFG_RTS_TH_EN, enabled);
6015         rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
6016
6017         rt2800_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
6018         rt2x00_set_field32(&reg, GF20_PROT_CFG_RTS_TH_EN, enabled);
6019         rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
6020
6021         rt2800_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
6022         rt2x00_set_field32(&reg, GF40_PROT_CFG_RTS_TH_EN, enabled);
6023         rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
6024
6025         return 0;
6026 }
6027 EXPORT_SYMBOL_GPL(rt2800_set_rts_threshold);
6028
6029 int rt2800_conf_tx(struct ieee80211_hw *hw,
6030                    struct ieee80211_vif *vif, u16 queue_idx,
6031                    const struct ieee80211_tx_queue_params *params)
6032 {
6033         struct rt2x00_dev *rt2x00dev = hw->priv;
6034         struct data_queue *queue;
6035         struct rt2x00_field32 field;
6036         int retval;
6037         u32 reg;
6038         u32 offset;
6039
6040         /*
6041          * First pass the configuration through rt2x00lib, that will
6042          * update the queue settings and validate the input. After that
6043          * we are free to update the registers based on the value
6044          * in the queue parameter.
6045          */
6046         retval = rt2x00mac_conf_tx(hw, vif, queue_idx, params);
6047         if (retval)
6048                 return retval;
6049
6050         /*
6051          * We only need to perform additional register initialization
6052          * for WMM queues/
6053          */
6054         if (queue_idx >= 4)
6055                 return 0;
6056
6057         queue = rt2x00queue_get_tx_queue(rt2x00dev, queue_idx);
6058
6059         /* Update WMM TXOP register */
6060         offset = WMM_TXOP0_CFG + (sizeof(u32) * (!!(queue_idx & 2)));
6061         field.bit_offset = (queue_idx & 1) * 16;
6062         field.bit_mask = 0xffff << field.bit_offset;
6063
6064         rt2800_register_read(rt2x00dev, offset, &reg);
6065         rt2x00_set_field32(&reg, field, queue->txop);
6066         rt2800_register_write(rt2x00dev, offset, reg);
6067
6068         /* Update WMM registers */
6069         field.bit_offset = queue_idx * 4;
6070         field.bit_mask = 0xf << field.bit_offset;
6071
6072         rt2800_register_read(rt2x00dev, WMM_AIFSN_CFG, &reg);
6073         rt2x00_set_field32(&reg, field, queue->aifs);
6074         rt2800_register_write(rt2x00dev, WMM_AIFSN_CFG, reg);
6075
6076         rt2800_register_read(rt2x00dev, WMM_CWMIN_CFG, &reg);
6077         rt2x00_set_field32(&reg, field, queue->cw_min);
6078         rt2800_register_write(rt2x00dev, WMM_CWMIN_CFG, reg);
6079
6080         rt2800_register_read(rt2x00dev, WMM_CWMAX_CFG, &reg);
6081         rt2x00_set_field32(&reg, field, queue->cw_max);
6082         rt2800_register_write(rt2x00dev, WMM_CWMAX_CFG, reg);
6083
6084         /* Update EDCA registers */
6085         offset = EDCA_AC0_CFG + (sizeof(u32) * queue_idx);
6086
6087         rt2800_register_read(rt2x00dev, offset, &reg);
6088         rt2x00_set_field32(&reg, EDCA_AC0_CFG_TX_OP, queue->txop);
6089         rt2x00_set_field32(&reg, EDCA_AC0_CFG_AIFSN, queue->aifs);
6090         rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMIN, queue->cw_min);
6091         rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMAX, queue->cw_max);
6092         rt2800_register_write(rt2x00dev, offset, reg);
6093
6094         return 0;
6095 }
6096 EXPORT_SYMBOL_GPL(rt2800_conf_tx);
6097
6098 u64 rt2800_get_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
6099 {
6100         struct rt2x00_dev *rt2x00dev = hw->priv;
6101         u64 tsf;
6102         u32 reg;
6103
6104         rt2800_register_read(rt2x00dev, TSF_TIMER_DW1, &reg);
6105         tsf = (u64) rt2x00_get_field32(reg, TSF_TIMER_DW1_HIGH_WORD) << 32;
6106         rt2800_register_read(rt2x00dev, TSF_TIMER_DW0, &reg);
6107         tsf |= rt2x00_get_field32(reg, TSF_TIMER_DW0_LOW_WORD);
6108
6109         return tsf;
6110 }
6111 EXPORT_SYMBOL_GPL(rt2800_get_tsf);
6112
6113 int rt2800_ampdu_action(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
6114                         enum ieee80211_ampdu_mlme_action action,
6115                         struct ieee80211_sta *sta, u16 tid, u16 *ssn,
6116                         u8 buf_size)
6117 {
6118         struct rt2x00_sta *sta_priv = (struct rt2x00_sta *)sta->drv_priv;
6119         int ret = 0;
6120
6121         /*
6122          * Don't allow aggregation for stations the hardware isn't aware
6123          * of because tx status reports for frames to an unknown station
6124          * always contain wcid=255 and thus we can't distinguish between
6125          * multiple stations which leads to unwanted situations when the
6126          * hw reorders frames due to aggregation.
6127          */
6128         if (sta_priv->wcid < 0)
6129                 return 1;
6130
6131         switch (action) {
6132         case IEEE80211_AMPDU_RX_START:
6133         case IEEE80211_AMPDU_RX_STOP:
6134                 /*
6135                  * The hw itself takes care of setting up BlockAck mechanisms.
6136                  * So, we only have to allow mac80211 to nagotiate a BlockAck
6137                  * agreement. Once that is done, the hw will BlockAck incoming
6138                  * AMPDUs without further setup.
6139                  */
6140                 break;
6141         case IEEE80211_AMPDU_TX_START:
6142                 ieee80211_start_tx_ba_cb_irqsafe(vif, sta->addr, tid);
6143                 break;
6144         case IEEE80211_AMPDU_TX_STOP_CONT:
6145         case IEEE80211_AMPDU_TX_STOP_FLUSH:
6146         case IEEE80211_AMPDU_TX_STOP_FLUSH_CONT:
6147                 ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid);
6148                 break;
6149         case IEEE80211_AMPDU_TX_OPERATIONAL:
6150                 break;
6151         default:
6152                 WARNING((struct rt2x00_dev *)hw->priv, "Unknown AMPDU action\n");
6153         }
6154
6155         return ret;
6156 }
6157 EXPORT_SYMBOL_GPL(rt2800_ampdu_action);
6158
6159 int rt2800_get_survey(struct ieee80211_hw *hw, int idx,
6160                       struct survey_info *survey)
6161 {
6162         struct rt2x00_dev *rt2x00dev = hw->priv;
6163         struct ieee80211_conf *conf = &hw->conf;
6164         u32 idle, busy, busy_ext;
6165
6166         if (idx != 0)
6167                 return -ENOENT;
6168
6169         survey->channel = conf->channel;
6170
6171         rt2800_register_read(rt2x00dev, CH_IDLE_STA, &idle);
6172         rt2800_register_read(rt2x00dev, CH_BUSY_STA, &busy);
6173         rt2800_register_read(rt2x00dev, CH_BUSY_STA_SEC, &busy_ext);
6174
6175         if (idle || busy) {
6176                 survey->filled = SURVEY_INFO_CHANNEL_TIME |
6177                                  SURVEY_INFO_CHANNEL_TIME_BUSY |
6178                                  SURVEY_INFO_CHANNEL_TIME_EXT_BUSY;
6179
6180                 survey->channel_time = (idle + busy) / 1000;
6181                 survey->channel_time_busy = busy / 1000;
6182                 survey->channel_time_ext_busy = busy_ext / 1000;
6183         }
6184
6185         if (!(hw->conf.flags & IEEE80211_CONF_OFFCHANNEL))
6186                 survey->filled |= SURVEY_INFO_IN_USE;
6187
6188         return 0;
6189
6190 }
6191 EXPORT_SYMBOL_GPL(rt2800_get_survey);
6192
6193 MODULE_AUTHOR(DRV_PROJECT ", Bartlomiej Zolnierkiewicz");
6194 MODULE_VERSION(DRV_VERSION);
6195 MODULE_DESCRIPTION("Ralink RT2800 library");
6196 MODULE_LICENSE("GPL");